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radeonsi: simplify si_llvm_emit_ddxy
[mesa.git] / src / gallium / drivers / radeonsi / si_shader.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Tom Stellard <thomas.stellard@amd.com>
25 * Michel Dänzer <michel.daenzer@amd.com>
26 * Christian König <christian.koenig@amd.com>
27 */
28
29 #include "gallivm/lp_bld_const.h"
30 #include "gallivm/lp_bld_gather.h"
31 #include "gallivm/lp_bld_intr.h"
32 #include "gallivm/lp_bld_logic.h"
33 #include "gallivm/lp_bld_arit.h"
34 #include "gallivm/lp_bld_flow.h"
35 #include "gallivm/lp_bld_misc.h"
36 #include "radeon/radeon_llvm.h"
37 #include "radeon/radeon_elf_util.h"
38 #include "radeon/radeon_llvm_emit.h"
39 #include "util/u_memory.h"
40 #include "util/u_string.h"
41 #include "tgsi/tgsi_build.h"
42 #include "tgsi/tgsi_util.h"
43 #include "tgsi/tgsi_dump.h"
44
45 #include "si_pipe.h"
46 #include "sid.h"
47
48
49 static const char *scratch_rsrc_dword0_symbol =
50 "SCRATCH_RSRC_DWORD0";
51
52 static const char *scratch_rsrc_dword1_symbol =
53 "SCRATCH_RSRC_DWORD1";
54
55 struct si_shader_output_values
56 {
57 LLVMValueRef values[4];
58 unsigned name;
59 unsigned sid;
60 };
61
62 struct si_shader_context
63 {
64 struct radeon_llvm_context radeon_bld;
65 struct si_shader *shader;
66 struct si_screen *screen;
67
68 unsigned type; /* PIPE_SHADER_* specifies the type of shader. */
69 bool is_gs_copy_shader;
70
71 /* Whether to generate the optimized shader variant compiled as a whole
72 * (without a prolog and epilog)
73 */
74 bool is_monolithic;
75
76 int param_streamout_config;
77 int param_streamout_write_index;
78 int param_streamout_offset[4];
79 int param_vertex_id;
80 int param_rel_auto_id;
81 int param_vs_prim_id;
82 int param_instance_id;
83 int param_vertex_index0;
84 int param_tes_u;
85 int param_tes_v;
86 int param_tes_rel_patch_id;
87 int param_tes_patch_id;
88 int param_es2gs_offset;
89 int param_oc_lds;
90
91 /* Sets a bit if the dynamic HS control word was 0x80000000. The bit is
92 * 0x800000 for VS, 0x1 for ES.
93 */
94 int param_tess_offchip;
95
96 LLVMTargetMachineRef tm;
97
98 unsigned invariant_load_md_kind;
99 unsigned range_md_kind;
100 unsigned uniform_md_kind;
101 LLVMValueRef empty_md;
102
103 /* Preloaded descriptors. */
104 LLVMValueRef esgs_ring;
105 LLVMValueRef gsvs_ring[4];
106
107 LLVMValueRef lds;
108 LLVMValueRef gs_next_vertex[4];
109 LLVMValueRef return_value;
110
111 LLVMTypeRef voidt;
112 LLVMTypeRef i1;
113 LLVMTypeRef i8;
114 LLVMTypeRef i32;
115 LLVMTypeRef i64;
116 LLVMTypeRef i128;
117 LLVMTypeRef f32;
118 LLVMTypeRef v16i8;
119 LLVMTypeRef v2i32;
120 LLVMTypeRef v4i32;
121 LLVMTypeRef v4f32;
122 LLVMTypeRef v8i32;
123
124 LLVMValueRef shared_memory;
125 };
126
127 static struct si_shader_context *si_shader_context(
128 struct lp_build_tgsi_context *bld_base)
129 {
130 return (struct si_shader_context *)bld_base;
131 }
132
133 static void si_init_shader_ctx(struct si_shader_context *ctx,
134 struct si_screen *sscreen,
135 struct si_shader *shader,
136 LLVMTargetMachineRef tm);
137
138 static void si_llvm_emit_barrier(const struct lp_build_tgsi_action *action,
139 struct lp_build_tgsi_context *bld_base,
140 struct lp_build_emit_data *emit_data);
141
142 static void si_dump_shader_key(unsigned shader, union si_shader_key *key,
143 FILE *f);
144
145 /* Ideally pass the sample mask input to the PS epilog as v13, which
146 * is its usual location, so that the shader doesn't have to add v_mov.
147 */
148 #define PS_EPILOG_SAMPLEMASK_MIN_LOC 13
149
150 /* The VS location of the PrimitiveID input is the same in the epilog,
151 * so that the main shader part doesn't have to move it.
152 */
153 #define VS_EPILOG_PRIMID_LOC 2
154
155 enum {
156 CONST_ADDR_SPACE = 2,
157 LOCAL_ADDR_SPACE = 3,
158 };
159
160 #define SENDMSG_GS 2
161 #define SENDMSG_GS_DONE 3
162
163 #define SENDMSG_GS_OP_NOP (0 << 4)
164 #define SENDMSG_GS_OP_CUT (1 << 4)
165 #define SENDMSG_GS_OP_EMIT (2 << 4)
166 #define SENDMSG_GS_OP_EMIT_CUT (3 << 4)
167
168 /**
169 * Returns a unique index for a semantic name and index. The index must be
170 * less than 64, so that a 64-bit bitmask of used inputs or outputs can be
171 * calculated.
172 */
173 unsigned si_shader_io_get_unique_index(unsigned semantic_name, unsigned index)
174 {
175 switch (semantic_name) {
176 case TGSI_SEMANTIC_POSITION:
177 return 0;
178 case TGSI_SEMANTIC_PSIZE:
179 return 1;
180 case TGSI_SEMANTIC_CLIPDIST:
181 assert(index <= 1);
182 return 2 + index;
183 case TGSI_SEMANTIC_GENERIC:
184 if (index <= 63-4)
185 return 4 + index;
186 else
187 /* same explanation as in the default statement,
188 * the only user hitting this is st/nine.
189 */
190 return 0;
191
192 /* patch indices are completely separate and thus start from 0 */
193 case TGSI_SEMANTIC_TESSOUTER:
194 return 0;
195 case TGSI_SEMANTIC_TESSINNER:
196 return 1;
197 case TGSI_SEMANTIC_PATCH:
198 return 2 + index;
199
200 default:
201 /* Don't fail here. The result of this function is only used
202 * for LS, TCS, TES, and GS, where legacy GL semantics can't
203 * occur, but this function is called for all vertex shaders
204 * before it's known whether LS will be compiled or not.
205 */
206 return 0;
207 }
208 }
209
210 /**
211 * Get the value of a shader input parameter and extract a bitfield.
212 */
213 static LLVMValueRef unpack_param(struct si_shader_context *ctx,
214 unsigned param, unsigned rshift,
215 unsigned bitwidth)
216 {
217 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
218 LLVMValueRef value = LLVMGetParam(ctx->radeon_bld.main_fn,
219 param);
220
221 if (LLVMGetTypeKind(LLVMTypeOf(value)) == LLVMFloatTypeKind)
222 value = bitcast(&ctx->radeon_bld.soa.bld_base,
223 TGSI_TYPE_UNSIGNED, value);
224
225 if (rshift)
226 value = LLVMBuildLShr(gallivm->builder, value,
227 lp_build_const_int32(gallivm, rshift), "");
228
229 if (rshift + bitwidth < 32) {
230 unsigned mask = (1 << bitwidth) - 1;
231 value = LLVMBuildAnd(gallivm->builder, value,
232 lp_build_const_int32(gallivm, mask), "");
233 }
234
235 return value;
236 }
237
238 static LLVMValueRef get_rel_patch_id(struct si_shader_context *ctx)
239 {
240 switch (ctx->type) {
241 case PIPE_SHADER_TESS_CTRL:
242 return unpack_param(ctx, SI_PARAM_REL_IDS, 0, 8);
243
244 case PIPE_SHADER_TESS_EVAL:
245 return LLVMGetParam(ctx->radeon_bld.main_fn,
246 ctx->param_tes_rel_patch_id);
247
248 default:
249 assert(0);
250 return NULL;
251 }
252 }
253
254 /* Tessellation shaders pass outputs to the next shader using LDS.
255 *
256 * LS outputs = TCS inputs
257 * TCS outputs = TES inputs
258 *
259 * The LDS layout is:
260 * - TCS inputs for patch 0
261 * - TCS inputs for patch 1
262 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
263 * - ...
264 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
265 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
266 * - TCS outputs for patch 1
267 * - Per-patch TCS outputs for patch 1
268 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
269 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
270 * - ...
271 *
272 * All three shaders VS(LS), TCS, TES share the same LDS space.
273 */
274
275 static LLVMValueRef
276 get_tcs_in_patch_stride(struct si_shader_context *ctx)
277 {
278 if (ctx->type == PIPE_SHADER_VERTEX)
279 return unpack_param(ctx, SI_PARAM_LS_OUT_LAYOUT, 0, 13);
280 else if (ctx->type == PIPE_SHADER_TESS_CTRL)
281 return unpack_param(ctx, SI_PARAM_TCS_IN_LAYOUT, 0, 13);
282 else {
283 assert(0);
284 return NULL;
285 }
286 }
287
288 static LLVMValueRef
289 get_tcs_out_patch_stride(struct si_shader_context *ctx)
290 {
291 return unpack_param(ctx, SI_PARAM_TCS_OUT_LAYOUT, 0, 13);
292 }
293
294 static LLVMValueRef
295 get_tcs_out_patch0_offset(struct si_shader_context *ctx)
296 {
297 return lp_build_mul_imm(&ctx->radeon_bld.soa.bld_base.uint_bld,
298 unpack_param(ctx,
299 SI_PARAM_TCS_OUT_OFFSETS,
300 0, 16),
301 4);
302 }
303
304 static LLVMValueRef
305 get_tcs_out_patch0_patch_data_offset(struct si_shader_context *ctx)
306 {
307 return lp_build_mul_imm(&ctx->radeon_bld.soa.bld_base.uint_bld,
308 unpack_param(ctx,
309 SI_PARAM_TCS_OUT_OFFSETS,
310 16, 16),
311 4);
312 }
313
314 static LLVMValueRef
315 get_tcs_in_current_patch_offset(struct si_shader_context *ctx)
316 {
317 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
318 LLVMValueRef patch_stride = get_tcs_in_patch_stride(ctx);
319 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
320
321 return LLVMBuildMul(gallivm->builder, patch_stride, rel_patch_id, "");
322 }
323
324 static LLVMValueRef
325 get_tcs_out_current_patch_offset(struct si_shader_context *ctx)
326 {
327 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
328 LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(ctx);
329 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
330 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
331
332 return LLVMBuildAdd(gallivm->builder, patch0_offset,
333 LLVMBuildMul(gallivm->builder, patch_stride,
334 rel_patch_id, ""),
335 "");
336 }
337
338 static LLVMValueRef
339 get_tcs_out_current_patch_data_offset(struct si_shader_context *ctx)
340 {
341 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
342 LLVMValueRef patch0_patch_data_offset =
343 get_tcs_out_patch0_patch_data_offset(ctx);
344 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
345 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
346
347 return LLVMBuildAdd(gallivm->builder, patch0_patch_data_offset,
348 LLVMBuildMul(gallivm->builder, patch_stride,
349 rel_patch_id, ""),
350 "");
351 }
352
353 static LLVMValueRef build_gep0(struct si_shader_context *ctx,
354 LLVMValueRef base_ptr, LLVMValueRef index)
355 {
356 LLVMValueRef indices[2] = {
357 LLVMConstInt(ctx->i32, 0, 0),
358 index,
359 };
360 return LLVMBuildGEP(ctx->radeon_bld.gallivm.builder, base_ptr,
361 indices, 2, "");
362 }
363
364 static void build_indexed_store(struct si_shader_context *ctx,
365 LLVMValueRef base_ptr, LLVMValueRef index,
366 LLVMValueRef value)
367 {
368 struct lp_build_tgsi_context *bld_base = &ctx->radeon_bld.soa.bld_base;
369 struct gallivm_state *gallivm = bld_base->base.gallivm;
370
371 LLVMBuildStore(gallivm->builder, value,
372 build_gep0(ctx, base_ptr, index));
373 }
374
375 /**
376 * Build an LLVM bytecode indexed load using LLVMBuildGEP + LLVMBuildLoad.
377 * It's equivalent to doing a load from &base_ptr[index].
378 *
379 * \param base_ptr Where the array starts.
380 * \param index The element index into the array.
381 * \param uniform Whether the base_ptr and index can be assumed to be
382 * dynamically uniform
383 */
384 static LLVMValueRef build_indexed_load(struct si_shader_context *ctx,
385 LLVMValueRef base_ptr, LLVMValueRef index,
386 bool uniform)
387 {
388 struct lp_build_tgsi_context *bld_base = &ctx->radeon_bld.soa.bld_base;
389 struct gallivm_state *gallivm = bld_base->base.gallivm;
390 LLVMValueRef pointer;
391
392 pointer = build_gep0(ctx, base_ptr, index);
393 if (uniform)
394 LLVMSetMetadata(pointer, ctx->uniform_md_kind, ctx->empty_md);
395 return LLVMBuildLoad(gallivm->builder, pointer, "");
396 }
397
398 /**
399 * Do a load from &base_ptr[index], but also add a flag that it's loading
400 * a constant from a dynamically uniform index.
401 */
402 static LLVMValueRef build_indexed_load_const(
403 struct si_shader_context *ctx,
404 LLVMValueRef base_ptr, LLVMValueRef index)
405 {
406 LLVMValueRef result = build_indexed_load(ctx, base_ptr, index, true);
407 LLVMSetMetadata(result, ctx->invariant_load_md_kind, ctx->empty_md);
408 return result;
409 }
410
411 static LLVMValueRef get_instance_index_for_fetch(
412 struct radeon_llvm_context *radeon_bld,
413 unsigned param_start_instance, unsigned divisor)
414 {
415 struct si_shader_context *ctx =
416 si_shader_context(&radeon_bld->soa.bld_base);
417 struct gallivm_state *gallivm = radeon_bld->soa.bld_base.base.gallivm;
418
419 LLVMValueRef result = LLVMGetParam(radeon_bld->main_fn,
420 ctx->param_instance_id);
421
422 /* The division must be done before START_INSTANCE is added. */
423 if (divisor > 1)
424 result = LLVMBuildUDiv(gallivm->builder, result,
425 lp_build_const_int32(gallivm, divisor), "");
426
427 return LLVMBuildAdd(gallivm->builder, result,
428 LLVMGetParam(radeon_bld->main_fn, param_start_instance), "");
429 }
430
431 static void declare_input_vs(
432 struct radeon_llvm_context *radeon_bld,
433 unsigned input_index,
434 const struct tgsi_full_declaration *decl,
435 LLVMValueRef out[4])
436 {
437 struct lp_build_context *base = &radeon_bld->soa.bld_base.base;
438 struct gallivm_state *gallivm = base->gallivm;
439 struct si_shader_context *ctx =
440 si_shader_context(&radeon_bld->soa.bld_base);
441 unsigned divisor =
442 ctx->shader->key.vs.prolog.instance_divisors[input_index];
443
444 unsigned chan;
445
446 LLVMValueRef t_list_ptr;
447 LLVMValueRef t_offset;
448 LLVMValueRef t_list;
449 LLVMValueRef attribute_offset;
450 LLVMValueRef buffer_index;
451 LLVMValueRef args[3];
452 LLVMValueRef input;
453
454 /* Load the T list */
455 t_list_ptr = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_VERTEX_BUFFERS);
456
457 t_offset = lp_build_const_int32(gallivm, input_index);
458
459 t_list = build_indexed_load_const(ctx, t_list_ptr, t_offset);
460
461 /* Build the attribute offset */
462 attribute_offset = lp_build_const_int32(gallivm, 0);
463
464 if (!ctx->is_monolithic) {
465 buffer_index = LLVMGetParam(radeon_bld->main_fn,
466 ctx->param_vertex_index0 +
467 input_index);
468 } else if (divisor) {
469 /* Build index from instance ID, start instance and divisor */
470 ctx->shader->info.uses_instanceid = true;
471 buffer_index = get_instance_index_for_fetch(&ctx->radeon_bld,
472 SI_PARAM_START_INSTANCE,
473 divisor);
474 } else {
475 /* Load the buffer index for vertices. */
476 LLVMValueRef vertex_id = LLVMGetParam(ctx->radeon_bld.main_fn,
477 ctx->param_vertex_id);
478 LLVMValueRef base_vertex = LLVMGetParam(radeon_bld->main_fn,
479 SI_PARAM_BASE_VERTEX);
480 buffer_index = LLVMBuildAdd(gallivm->builder, base_vertex, vertex_id, "");
481 }
482
483 args[0] = t_list;
484 args[1] = attribute_offset;
485 args[2] = buffer_index;
486 input = lp_build_intrinsic(gallivm->builder,
487 "llvm.SI.vs.load.input", ctx->v4f32, args, 3,
488 LLVMReadNoneAttribute);
489
490 /* Break up the vec4 into individual components */
491 for (chan = 0; chan < 4; chan++) {
492 LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan);
493 out[chan] = LLVMBuildExtractElement(gallivm->builder,
494 input, llvm_chan, "");
495 }
496 }
497
498 static LLVMValueRef get_primitive_id(struct lp_build_tgsi_context *bld_base,
499 unsigned swizzle)
500 {
501 struct si_shader_context *ctx = si_shader_context(bld_base);
502
503 if (swizzle > 0)
504 return bld_base->uint_bld.zero;
505
506 switch (ctx->type) {
507 case PIPE_SHADER_VERTEX:
508 return LLVMGetParam(ctx->radeon_bld.main_fn,
509 ctx->param_vs_prim_id);
510 case PIPE_SHADER_TESS_CTRL:
511 return LLVMGetParam(ctx->radeon_bld.main_fn,
512 SI_PARAM_PATCH_ID);
513 case PIPE_SHADER_TESS_EVAL:
514 return LLVMGetParam(ctx->radeon_bld.main_fn,
515 ctx->param_tes_patch_id);
516 case PIPE_SHADER_GEOMETRY:
517 return LLVMGetParam(ctx->radeon_bld.main_fn,
518 SI_PARAM_PRIMITIVE_ID);
519 default:
520 assert(0);
521 return bld_base->uint_bld.zero;
522 }
523 }
524
525 /**
526 * Return the value of tgsi_ind_register for indexing.
527 * This is the indirect index with the constant offset added to it.
528 */
529 static LLVMValueRef get_indirect_index(struct si_shader_context *ctx,
530 const struct tgsi_ind_register *ind,
531 int rel_index)
532 {
533 struct gallivm_state *gallivm = ctx->radeon_bld.soa.bld_base.base.gallivm;
534 LLVMValueRef result;
535
536 result = ctx->radeon_bld.soa.addr[ind->Index][ind->Swizzle];
537 result = LLVMBuildLoad(gallivm->builder, result, "");
538 result = LLVMBuildAdd(gallivm->builder, result,
539 lp_build_const_int32(gallivm, rel_index), "");
540 return result;
541 }
542
543 /**
544 * Like get_indirect_index, but restricts the return value to a (possibly
545 * undefined) value inside [0..num).
546 */
547 static LLVMValueRef get_bounded_indirect_index(struct si_shader_context *ctx,
548 const struct tgsi_ind_register *ind,
549 int rel_index, unsigned num)
550 {
551 LLVMValueRef result = get_indirect_index(ctx, ind, rel_index);
552
553 /* LLVM 3.8: If indirect resource indexing is used:
554 * - SI & CIK hang
555 * - VI crashes
556 */
557 if (HAVE_LLVM <= 0x0308)
558 return LLVMGetUndef(ctx->i32);
559
560 return radeon_llvm_bound_index(&ctx->radeon_bld, result, num);
561 }
562
563
564 /**
565 * Calculate a dword address given an input or output register and a stride.
566 */
567 static LLVMValueRef get_dw_address(struct si_shader_context *ctx,
568 const struct tgsi_full_dst_register *dst,
569 const struct tgsi_full_src_register *src,
570 LLVMValueRef vertex_dw_stride,
571 LLVMValueRef base_addr)
572 {
573 struct gallivm_state *gallivm = ctx->radeon_bld.soa.bld_base.base.gallivm;
574 struct tgsi_shader_info *info = &ctx->shader->selector->info;
575 ubyte *name, *index, *array_first;
576 int first, param;
577 struct tgsi_full_dst_register reg;
578
579 /* Set the register description. The address computation is the same
580 * for sources and destinations. */
581 if (src) {
582 reg.Register.File = src->Register.File;
583 reg.Register.Index = src->Register.Index;
584 reg.Register.Indirect = src->Register.Indirect;
585 reg.Register.Dimension = src->Register.Dimension;
586 reg.Indirect = src->Indirect;
587 reg.Dimension = src->Dimension;
588 reg.DimIndirect = src->DimIndirect;
589 } else
590 reg = *dst;
591
592 /* If the register is 2-dimensional (e.g. an array of vertices
593 * in a primitive), calculate the base address of the vertex. */
594 if (reg.Register.Dimension) {
595 LLVMValueRef index;
596
597 if (reg.Dimension.Indirect)
598 index = get_indirect_index(ctx, &reg.DimIndirect,
599 reg.Dimension.Index);
600 else
601 index = lp_build_const_int32(gallivm, reg.Dimension.Index);
602
603 base_addr = LLVMBuildAdd(gallivm->builder, base_addr,
604 LLVMBuildMul(gallivm->builder, index,
605 vertex_dw_stride, ""), "");
606 }
607
608 /* Get information about the register. */
609 if (reg.Register.File == TGSI_FILE_INPUT) {
610 name = info->input_semantic_name;
611 index = info->input_semantic_index;
612 array_first = info->input_array_first;
613 } else if (reg.Register.File == TGSI_FILE_OUTPUT) {
614 name = info->output_semantic_name;
615 index = info->output_semantic_index;
616 array_first = info->output_array_first;
617 } else {
618 assert(0);
619 return NULL;
620 }
621
622 if (reg.Register.Indirect) {
623 /* Add the relative address of the element. */
624 LLVMValueRef ind_index;
625
626 if (reg.Indirect.ArrayID)
627 first = array_first[reg.Indirect.ArrayID];
628 else
629 first = reg.Register.Index;
630
631 ind_index = get_indirect_index(ctx, &reg.Indirect,
632 reg.Register.Index - first);
633
634 base_addr = LLVMBuildAdd(gallivm->builder, base_addr,
635 LLVMBuildMul(gallivm->builder, ind_index,
636 lp_build_const_int32(gallivm, 4), ""), "");
637
638 param = si_shader_io_get_unique_index(name[first], index[first]);
639 } else {
640 param = si_shader_io_get_unique_index(name[reg.Register.Index],
641 index[reg.Register.Index]);
642 }
643
644 /* Add the base address of the element. */
645 return LLVMBuildAdd(gallivm->builder, base_addr,
646 lp_build_const_int32(gallivm, param * 4), "");
647 }
648
649 /* The offchip buffer layout for TCS->TES is
650 *
651 * - attribute 0 of patch 0 vertex 0
652 * - attribute 0 of patch 0 vertex 1
653 * - attribute 0 of patch 0 vertex 2
654 * ...
655 * - attribute 0 of patch 1 vertex 0
656 * - attribute 0 of patch 1 vertex 1
657 * ...
658 * - attribute 1 of patch 0 vertex 0
659 * - attribute 1 of patch 0 vertex 1
660 * ...
661 * - per patch attribute 0 of patch 0
662 * - per patch attribute 0 of patch 1
663 * ...
664 *
665 * Note that every attribute has 4 components.
666 */
667 static LLVMValueRef get_tcs_tes_buffer_address(struct si_shader_context *ctx,
668 LLVMValueRef vertex_index,
669 LLVMValueRef param_index)
670 {
671 struct gallivm_state *gallivm = ctx->radeon_bld.soa.bld_base.base.gallivm;
672 LLVMValueRef base_addr, vertices_per_patch, num_patches, total_vertices;
673 LLVMValueRef param_stride, constant16;
674
675 vertices_per_patch = unpack_param(ctx, SI_PARAM_TCS_OFFCHIP_LAYOUT, 9, 6);
676 num_patches = unpack_param(ctx, SI_PARAM_TCS_OFFCHIP_LAYOUT, 0, 9);
677 total_vertices = LLVMBuildMul(gallivm->builder, vertices_per_patch,
678 num_patches, "");
679
680 constant16 = lp_build_const_int32(gallivm, 16);
681 if (vertex_index) {
682 base_addr = LLVMBuildMul(gallivm->builder, get_rel_patch_id(ctx),
683 vertices_per_patch, "");
684
685 base_addr = LLVMBuildAdd(gallivm->builder, base_addr,
686 vertex_index, "");
687
688 param_stride = total_vertices;
689 } else {
690 base_addr = get_rel_patch_id(ctx);
691 param_stride = num_patches;
692 }
693
694 base_addr = LLVMBuildAdd(gallivm->builder, base_addr,
695 LLVMBuildMul(gallivm->builder, param_index,
696 param_stride, ""), "");
697
698 base_addr = LLVMBuildMul(gallivm->builder, base_addr, constant16, "");
699
700 if (!vertex_index) {
701 LLVMValueRef patch_data_offset =
702 unpack_param(ctx, SI_PARAM_TCS_OFFCHIP_LAYOUT, 16, 16);
703
704 base_addr = LLVMBuildAdd(gallivm->builder, base_addr,
705 patch_data_offset, "");
706 }
707 return base_addr;
708 }
709
710 static LLVMValueRef get_tcs_tes_buffer_address_from_reg(
711 struct si_shader_context *ctx,
712 const struct tgsi_full_dst_register *dst,
713 const struct tgsi_full_src_register *src)
714 {
715 struct gallivm_state *gallivm = ctx->radeon_bld.soa.bld_base.base.gallivm;
716 struct tgsi_shader_info *info = &ctx->shader->selector->info;
717 ubyte *name, *index, *array_first;
718 struct tgsi_full_src_register reg;
719 LLVMValueRef vertex_index = NULL;
720 LLVMValueRef param_index = NULL;
721 unsigned param_index_base, param_base;
722
723 reg = src ? *src : tgsi_full_src_register_from_dst(dst);
724
725 if (reg.Register.Dimension) {
726
727 if (reg.Dimension.Indirect)
728 vertex_index = get_indirect_index(ctx, &reg.DimIndirect,
729 reg.Dimension.Index);
730 else
731 vertex_index = lp_build_const_int32(gallivm,
732 reg.Dimension.Index);
733 }
734
735 /* Get information about the register. */
736 if (reg.Register.File == TGSI_FILE_INPUT) {
737 name = info->input_semantic_name;
738 index = info->input_semantic_index;
739 array_first = info->input_array_first;
740 } else if (reg.Register.File == TGSI_FILE_OUTPUT) {
741 name = info->output_semantic_name;
742 index = info->output_semantic_index;
743 array_first = info->output_array_first;
744 } else {
745 assert(0);
746 return NULL;
747 }
748
749 if (reg.Register.Indirect) {
750 if (reg.Indirect.ArrayID)
751 param_base = array_first[reg.Indirect.ArrayID];
752 else
753 param_base = reg.Register.Index;
754
755 param_index = get_indirect_index(ctx, &reg.Indirect,
756 reg.Register.Index - param_base);
757
758 } else {
759 param_base = reg.Register.Index;
760 param_index = lp_build_const_int32(gallivm, 0);
761 }
762
763 param_index_base = si_shader_io_get_unique_index(name[param_base],
764 index[param_base]);
765
766 param_index = LLVMBuildAdd(gallivm->builder, param_index,
767 lp_build_const_int32(gallivm, param_index_base),
768 "");
769
770 return get_tcs_tes_buffer_address(ctx, vertex_index, param_index);
771 }
772
773 /* TBUFFER_STORE_FORMAT_{X,XY,XYZ,XYZW} <- the suffix is selected by num_channels=1..4.
774 * The type of vdata must be one of i32 (num_channels=1), v2i32 (num_channels=2),
775 * or v4i32 (num_channels=3,4). */
776 static void build_tbuffer_store(struct si_shader_context *ctx,
777 LLVMValueRef rsrc,
778 LLVMValueRef vdata,
779 unsigned num_channels,
780 LLVMValueRef vaddr,
781 LLVMValueRef soffset,
782 unsigned inst_offset,
783 unsigned dfmt,
784 unsigned nfmt,
785 unsigned offen,
786 unsigned idxen,
787 unsigned glc,
788 unsigned slc,
789 unsigned tfe)
790 {
791 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
792 LLVMValueRef args[] = {
793 rsrc,
794 vdata,
795 LLVMConstInt(ctx->i32, num_channels, 0),
796 vaddr,
797 soffset,
798 LLVMConstInt(ctx->i32, inst_offset, 0),
799 LLVMConstInt(ctx->i32, dfmt, 0),
800 LLVMConstInt(ctx->i32, nfmt, 0),
801 LLVMConstInt(ctx->i32, offen, 0),
802 LLVMConstInt(ctx->i32, idxen, 0),
803 LLVMConstInt(ctx->i32, glc, 0),
804 LLVMConstInt(ctx->i32, slc, 0),
805 LLVMConstInt(ctx->i32, tfe, 0)
806 };
807
808 /* The instruction offset field has 12 bits */
809 assert(offen || inst_offset < (1 << 12));
810
811 /* The intrinsic is overloaded, we need to add a type suffix for overloading to work. */
812 unsigned func = CLAMP(num_channels, 1, 3) - 1;
813 const char *types[] = {"i32", "v2i32", "v4i32"};
814 char name[256];
815 snprintf(name, sizeof(name), "llvm.SI.tbuffer.store.%s", types[func]);
816
817 lp_build_intrinsic(gallivm->builder, name, ctx->voidt,
818 args, ARRAY_SIZE(args), 0);
819 }
820
821 static void build_tbuffer_store_dwords(struct si_shader_context *ctx,
822 LLVMValueRef rsrc,
823 LLVMValueRef vdata,
824 unsigned num_channels,
825 LLVMValueRef vaddr,
826 LLVMValueRef soffset,
827 unsigned inst_offset)
828 {
829 static unsigned dfmt[] = {
830 V_008F0C_BUF_DATA_FORMAT_32,
831 V_008F0C_BUF_DATA_FORMAT_32_32,
832 V_008F0C_BUF_DATA_FORMAT_32_32_32,
833 V_008F0C_BUF_DATA_FORMAT_32_32_32_32
834 };
835 assert(num_channels >= 1 && num_channels <= 4);
836
837 build_tbuffer_store(ctx, rsrc, vdata, num_channels, vaddr, soffset,
838 inst_offset, dfmt[num_channels-1],
839 V_008F0C_BUF_NUM_FORMAT_UINT, 1, 0, 1, 1, 0);
840 }
841
842 static LLVMValueRef build_buffer_load(struct si_shader_context *ctx,
843 LLVMValueRef rsrc,
844 int num_channels,
845 LLVMValueRef vindex,
846 LLVMValueRef voffset,
847 LLVMValueRef soffset,
848 unsigned inst_offset,
849 unsigned glc,
850 unsigned slc)
851 {
852 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
853 unsigned func = CLAMP(num_channels, 1, 3) - 1;
854
855 if (HAVE_LLVM >= 0x309) {
856 LLVMValueRef args[] = {
857 LLVMBuildBitCast(gallivm->builder, rsrc, ctx->v4i32, ""),
858 vindex ? vindex : LLVMConstInt(ctx->i32, 0, 0),
859 LLVMConstInt(ctx->i32, inst_offset, 0),
860 LLVMConstInt(ctx->i1, glc, 0),
861 LLVMConstInt(ctx->i1, slc, 0)
862 };
863
864 LLVMTypeRef types[] = {ctx->f32, LLVMVectorType(ctx->f32, 2),
865 ctx->v4f32};
866 const char *type_names[] = {"f32", "v2f32", "v4f32"};
867 char name[256];
868
869 if (voffset) {
870 args[2] = LLVMBuildAdd(gallivm->builder, args[2], voffset,
871 "");
872 }
873
874 if (soffset) {
875 args[2] = LLVMBuildAdd(gallivm->builder, args[2], soffset,
876 "");
877 }
878
879 snprintf(name, sizeof(name), "llvm.amdgcn.buffer.load.%s",
880 type_names[func]);
881
882 return lp_build_intrinsic(gallivm->builder, name, types[func], args,
883 ARRAY_SIZE(args), LLVMReadOnlyAttribute);
884 } else {
885 LLVMValueRef args[] = {
886 LLVMBuildBitCast(gallivm->builder, rsrc, ctx->v16i8, ""),
887 voffset ? voffset : vindex,
888 soffset,
889 LLVMConstInt(ctx->i32, inst_offset, 0),
890 LLVMConstInt(ctx->i32, voffset ? 1 : 0, 0), // offen
891 LLVMConstInt(ctx->i32, vindex ? 1 : 0, 0), //idxen
892 LLVMConstInt(ctx->i32, glc, 0),
893 LLVMConstInt(ctx->i32, slc, 0),
894 LLVMConstInt(ctx->i32, 0, 0), // TFE
895 };
896
897 LLVMTypeRef types[] = {ctx->i32, LLVMVectorType(ctx->i32, 2),
898 ctx->v4i32};
899 const char *type_names[] = {"i32", "v2i32", "v4i32"};
900 const char *arg_type = "i32";
901 char name[256];
902
903 if (voffset && vindex) {
904 LLVMValueRef vaddr[] = {vindex, voffset};
905
906 arg_type = "v2i32";
907 args[1] = lp_build_gather_values(gallivm, vaddr, 2);
908 }
909
910 snprintf(name, sizeof(name), "llvm.SI.buffer.load.dword.%s.%s",
911 type_names[func], arg_type);
912
913 return lp_build_intrinsic(gallivm->builder, name, types[func], args,
914 ARRAY_SIZE(args), LLVMReadOnlyAttribute);
915 }
916 }
917
918 static LLVMValueRef buffer_load(struct lp_build_tgsi_context *bld_base,
919 enum tgsi_opcode_type type, unsigned swizzle,
920 LLVMValueRef buffer, LLVMValueRef offset,
921 LLVMValueRef base)
922 {
923 struct si_shader_context *ctx = si_shader_context(bld_base);
924 struct gallivm_state *gallivm = bld_base->base.gallivm;
925 LLVMValueRef value, value2;
926 LLVMTypeRef llvm_type = tgsi2llvmtype(bld_base, type);
927 LLVMTypeRef vec_type = LLVMVectorType(llvm_type, 4);
928
929 if (swizzle == ~0) {
930 value = build_buffer_load(ctx, buffer, 4, NULL, base, offset,
931 0, 1, 0);
932
933 return LLVMBuildBitCast(gallivm->builder, value, vec_type, "");
934 }
935
936 if (!tgsi_type_is_64bit(type)) {
937 value = build_buffer_load(ctx, buffer, 4, NULL, base, offset,
938 0, 1, 0);
939
940 value = LLVMBuildBitCast(gallivm->builder, value, vec_type, "");
941 return LLVMBuildExtractElement(gallivm->builder, value,
942 lp_build_const_int32(gallivm, swizzle), "");
943 }
944
945 value = build_buffer_load(ctx, buffer, 1, NULL, base, offset,
946 swizzle * 4, 1, 0);
947
948 value2 = build_buffer_load(ctx, buffer, 1, NULL, base, offset,
949 swizzle * 4 + 4, 1, 0);
950
951 return radeon_llvm_emit_fetch_64bit(bld_base, type, value, value2);
952 }
953
954 /**
955 * Load from LDS.
956 *
957 * \param type output value type
958 * \param swizzle offset (typically 0..3); it can be ~0, which loads a vec4
959 * \param dw_addr address in dwords
960 */
961 static LLVMValueRef lds_load(struct lp_build_tgsi_context *bld_base,
962 enum tgsi_opcode_type type, unsigned swizzle,
963 LLVMValueRef dw_addr)
964 {
965 struct si_shader_context *ctx = si_shader_context(bld_base);
966 struct gallivm_state *gallivm = bld_base->base.gallivm;
967 LLVMValueRef value;
968
969 if (swizzle == ~0) {
970 LLVMValueRef values[TGSI_NUM_CHANNELS];
971
972 for (unsigned chan = 0; chan < TGSI_NUM_CHANNELS; chan++)
973 values[chan] = lds_load(bld_base, type, chan, dw_addr);
974
975 return lp_build_gather_values(bld_base->base.gallivm, values,
976 TGSI_NUM_CHANNELS);
977 }
978
979 dw_addr = lp_build_add(&bld_base->uint_bld, dw_addr,
980 lp_build_const_int32(gallivm, swizzle));
981
982 value = build_indexed_load(ctx, ctx->lds, dw_addr, false);
983 if (tgsi_type_is_64bit(type)) {
984 LLVMValueRef value2;
985 dw_addr = lp_build_add(&bld_base->uint_bld, dw_addr,
986 lp_build_const_int32(gallivm, swizzle + 1));
987 value2 = build_indexed_load(ctx, ctx->lds, dw_addr, false);
988 return radeon_llvm_emit_fetch_64bit(bld_base, type, value, value2);
989 }
990
991 return LLVMBuildBitCast(gallivm->builder, value,
992 tgsi2llvmtype(bld_base, type), "");
993 }
994
995 /**
996 * Store to LDS.
997 *
998 * \param swizzle offset (typically 0..3)
999 * \param dw_addr address in dwords
1000 * \param value value to store
1001 */
1002 static void lds_store(struct lp_build_tgsi_context *bld_base,
1003 unsigned swizzle, LLVMValueRef dw_addr,
1004 LLVMValueRef value)
1005 {
1006 struct si_shader_context *ctx = si_shader_context(bld_base);
1007 struct gallivm_state *gallivm = bld_base->base.gallivm;
1008
1009 dw_addr = lp_build_add(&bld_base->uint_bld, dw_addr,
1010 lp_build_const_int32(gallivm, swizzle));
1011
1012 value = LLVMBuildBitCast(gallivm->builder, value, ctx->i32, "");
1013 build_indexed_store(ctx, ctx->lds,
1014 dw_addr, value);
1015 }
1016
1017 static LLVMValueRef fetch_input_tcs(
1018 struct lp_build_tgsi_context *bld_base,
1019 const struct tgsi_full_src_register *reg,
1020 enum tgsi_opcode_type type, unsigned swizzle)
1021 {
1022 struct si_shader_context *ctx = si_shader_context(bld_base);
1023 LLVMValueRef dw_addr, stride;
1024
1025 stride = unpack_param(ctx, SI_PARAM_TCS_IN_LAYOUT, 13, 8);
1026 dw_addr = get_tcs_in_current_patch_offset(ctx);
1027 dw_addr = get_dw_address(ctx, NULL, reg, stride, dw_addr);
1028
1029 return lds_load(bld_base, type, swizzle, dw_addr);
1030 }
1031
1032 static LLVMValueRef fetch_output_tcs(
1033 struct lp_build_tgsi_context *bld_base,
1034 const struct tgsi_full_src_register *reg,
1035 enum tgsi_opcode_type type, unsigned swizzle)
1036 {
1037 struct si_shader_context *ctx = si_shader_context(bld_base);
1038 LLVMValueRef dw_addr, stride;
1039
1040 if (reg->Register.Dimension) {
1041 stride = unpack_param(ctx, SI_PARAM_TCS_OUT_LAYOUT, 13, 8);
1042 dw_addr = get_tcs_out_current_patch_offset(ctx);
1043 dw_addr = get_dw_address(ctx, NULL, reg, stride, dw_addr);
1044 } else {
1045 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1046 dw_addr = get_dw_address(ctx, NULL, reg, NULL, dw_addr);
1047 }
1048
1049 return lds_load(bld_base, type, swizzle, dw_addr);
1050 }
1051
1052 static LLVMValueRef fetch_input_tes(
1053 struct lp_build_tgsi_context *bld_base,
1054 const struct tgsi_full_src_register *reg,
1055 enum tgsi_opcode_type type, unsigned swizzle)
1056 {
1057 struct si_shader_context *ctx = si_shader_context(bld_base);
1058 struct gallivm_state *gallivm = bld_base->base.gallivm;
1059 LLVMValueRef rw_buffers, buffer, base, addr;
1060
1061 rw_buffers = LLVMGetParam(ctx->radeon_bld.main_fn,
1062 SI_PARAM_RW_BUFFERS);
1063 buffer = build_indexed_load_const(ctx, rw_buffers,
1064 lp_build_const_int32(gallivm, SI_HS_RING_TESS_OFFCHIP));
1065
1066 base = LLVMGetParam(ctx->radeon_bld.main_fn, ctx->param_oc_lds);
1067 addr = get_tcs_tes_buffer_address_from_reg(ctx, NULL, reg);
1068
1069 return buffer_load(bld_base, type, swizzle, buffer, base, addr);
1070 }
1071
1072 static void store_output_tcs(struct lp_build_tgsi_context *bld_base,
1073 const struct tgsi_full_instruction *inst,
1074 const struct tgsi_opcode_info *info,
1075 LLVMValueRef dst[4])
1076 {
1077 struct si_shader_context *ctx = si_shader_context(bld_base);
1078 struct gallivm_state *gallivm = bld_base->base.gallivm;
1079 const struct tgsi_full_dst_register *reg = &inst->Dst[0];
1080 unsigned chan_index;
1081 LLVMValueRef dw_addr, stride;
1082 LLVMValueRef rw_buffers, buffer, base, buf_addr;
1083 LLVMValueRef values[4];
1084
1085 /* Only handle per-patch and per-vertex outputs here.
1086 * Vectors will be lowered to scalars and this function will be called again.
1087 */
1088 if (reg->Register.File != TGSI_FILE_OUTPUT ||
1089 (dst[0] && LLVMGetTypeKind(LLVMTypeOf(dst[0])) == LLVMVectorTypeKind)) {
1090 radeon_llvm_emit_store(bld_base, inst, info, dst);
1091 return;
1092 }
1093
1094 if (reg->Register.Dimension) {
1095 stride = unpack_param(ctx, SI_PARAM_TCS_OUT_LAYOUT, 13, 8);
1096 dw_addr = get_tcs_out_current_patch_offset(ctx);
1097 dw_addr = get_dw_address(ctx, reg, NULL, stride, dw_addr);
1098 } else {
1099 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1100 dw_addr = get_dw_address(ctx, reg, NULL, NULL, dw_addr);
1101 }
1102
1103 rw_buffers = LLVMGetParam(ctx->radeon_bld.main_fn,
1104 SI_PARAM_RW_BUFFERS);
1105 buffer = build_indexed_load_const(ctx, rw_buffers,
1106 lp_build_const_int32(gallivm, SI_HS_RING_TESS_OFFCHIP));
1107
1108 base = LLVMGetParam(ctx->radeon_bld.main_fn, ctx->param_oc_lds);
1109 buf_addr = get_tcs_tes_buffer_address_from_reg(ctx, reg, NULL);
1110
1111
1112 TGSI_FOR_EACH_DST0_ENABLED_CHANNEL(inst, chan_index) {
1113 LLVMValueRef value = dst[chan_index];
1114
1115 if (inst->Instruction.Saturate)
1116 value = radeon_llvm_saturate(bld_base, value);
1117
1118 lds_store(bld_base, chan_index, dw_addr, value);
1119
1120 value = LLVMBuildBitCast(gallivm->builder, value, ctx->i32, "");
1121 values[chan_index] = value;
1122
1123 if (inst->Dst[0].Register.WriteMask != 0xF) {
1124 build_tbuffer_store_dwords(ctx, buffer, value, 1,
1125 buf_addr, base,
1126 4 * chan_index);
1127 }
1128 }
1129
1130 if (inst->Dst[0].Register.WriteMask == 0xF) {
1131 LLVMValueRef value = lp_build_gather_values(bld_base->base.gallivm,
1132 values, 4);
1133 build_tbuffer_store_dwords(ctx, buffer, value, 4, buf_addr,
1134 base, 0);
1135 }
1136 }
1137
1138 static LLVMValueRef fetch_input_gs(
1139 struct lp_build_tgsi_context *bld_base,
1140 const struct tgsi_full_src_register *reg,
1141 enum tgsi_opcode_type type,
1142 unsigned swizzle)
1143 {
1144 struct lp_build_context *base = &bld_base->base;
1145 struct si_shader_context *ctx = si_shader_context(bld_base);
1146 struct si_shader *shader = ctx->shader;
1147 struct lp_build_context *uint = &ctx->radeon_bld.soa.bld_base.uint_bld;
1148 struct gallivm_state *gallivm = base->gallivm;
1149 LLVMValueRef vtx_offset;
1150 LLVMValueRef args[9];
1151 unsigned vtx_offset_param;
1152 struct tgsi_shader_info *info = &shader->selector->info;
1153 unsigned semantic_name = info->input_semantic_name[reg->Register.Index];
1154 unsigned semantic_index = info->input_semantic_index[reg->Register.Index];
1155 unsigned param;
1156 LLVMValueRef value;
1157
1158 if (swizzle != ~0 && semantic_name == TGSI_SEMANTIC_PRIMID)
1159 return get_primitive_id(bld_base, swizzle);
1160
1161 if (!reg->Register.Dimension)
1162 return NULL;
1163
1164 if (swizzle == ~0) {
1165 LLVMValueRef values[TGSI_NUM_CHANNELS];
1166 unsigned chan;
1167 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1168 values[chan] = fetch_input_gs(bld_base, reg, type, chan);
1169 }
1170 return lp_build_gather_values(bld_base->base.gallivm, values,
1171 TGSI_NUM_CHANNELS);
1172 }
1173
1174 /* Get the vertex offset parameter */
1175 vtx_offset_param = reg->Dimension.Index;
1176 if (vtx_offset_param < 2) {
1177 vtx_offset_param += SI_PARAM_VTX0_OFFSET;
1178 } else {
1179 assert(vtx_offset_param < 6);
1180 vtx_offset_param += SI_PARAM_VTX2_OFFSET - 2;
1181 }
1182 vtx_offset = lp_build_mul_imm(uint,
1183 LLVMGetParam(ctx->radeon_bld.main_fn,
1184 vtx_offset_param),
1185 4);
1186
1187 param = si_shader_io_get_unique_index(semantic_name, semantic_index);
1188 args[0] = ctx->esgs_ring;
1189 args[1] = vtx_offset;
1190 args[2] = lp_build_const_int32(gallivm, (param * 4 + swizzle) * 256);
1191 args[3] = uint->zero;
1192 args[4] = uint->one; /* OFFEN */
1193 args[5] = uint->zero; /* IDXEN */
1194 args[6] = uint->one; /* GLC */
1195 args[7] = uint->zero; /* SLC */
1196 args[8] = uint->zero; /* TFE */
1197
1198 value = lp_build_intrinsic(gallivm->builder,
1199 "llvm.SI.buffer.load.dword.i32.i32",
1200 ctx->i32, args, 9,
1201 LLVMReadOnlyAttribute);
1202 if (tgsi_type_is_64bit(type)) {
1203 LLVMValueRef value2;
1204 args[2] = lp_build_const_int32(gallivm, (param * 4 + swizzle + 1) * 256);
1205 value2 = lp_build_intrinsic(gallivm->builder,
1206 "llvm.SI.buffer.load.dword.i32.i32",
1207 ctx->i32, args, 9,
1208 LLVMReadOnlyAttribute);
1209 return radeon_llvm_emit_fetch_64bit(bld_base, type,
1210 value, value2);
1211 }
1212 return LLVMBuildBitCast(gallivm->builder,
1213 value,
1214 tgsi2llvmtype(bld_base, type), "");
1215 }
1216
1217 static int lookup_interp_param_index(unsigned interpolate, unsigned location)
1218 {
1219 switch (interpolate) {
1220 case TGSI_INTERPOLATE_CONSTANT:
1221 return 0;
1222
1223 case TGSI_INTERPOLATE_LINEAR:
1224 if (location == TGSI_INTERPOLATE_LOC_SAMPLE)
1225 return SI_PARAM_LINEAR_SAMPLE;
1226 else if (location == TGSI_INTERPOLATE_LOC_CENTROID)
1227 return SI_PARAM_LINEAR_CENTROID;
1228 else
1229 return SI_PARAM_LINEAR_CENTER;
1230 break;
1231 case TGSI_INTERPOLATE_COLOR:
1232 case TGSI_INTERPOLATE_PERSPECTIVE:
1233 if (location == TGSI_INTERPOLATE_LOC_SAMPLE)
1234 return SI_PARAM_PERSP_SAMPLE;
1235 else if (location == TGSI_INTERPOLATE_LOC_CENTROID)
1236 return SI_PARAM_PERSP_CENTROID;
1237 else
1238 return SI_PARAM_PERSP_CENTER;
1239 break;
1240 default:
1241 fprintf(stderr, "Warning: Unhandled interpolation mode.\n");
1242 return -1;
1243 }
1244 }
1245
1246 /* This shouldn't be used by explicit INTERP opcodes. */
1247 static unsigned select_interp_param(struct si_shader_context *ctx,
1248 unsigned param)
1249 {
1250 if (!ctx->is_monolithic)
1251 return param;
1252
1253 if (ctx->shader->key.ps.prolog.force_persp_sample_interp) {
1254 switch (param) {
1255 case SI_PARAM_PERSP_CENTROID:
1256 case SI_PARAM_PERSP_CENTER:
1257 return SI_PARAM_PERSP_SAMPLE;
1258 }
1259 }
1260 if (ctx->shader->key.ps.prolog.force_linear_sample_interp) {
1261 switch (param) {
1262 case SI_PARAM_LINEAR_CENTROID:
1263 case SI_PARAM_LINEAR_CENTER:
1264 return SI_PARAM_LINEAR_SAMPLE;
1265 }
1266 }
1267 if (ctx->shader->key.ps.prolog.force_persp_center_interp) {
1268 switch (param) {
1269 case SI_PARAM_PERSP_CENTROID:
1270 case SI_PARAM_PERSP_SAMPLE:
1271 return SI_PARAM_PERSP_CENTER;
1272 }
1273 }
1274 if (ctx->shader->key.ps.prolog.force_linear_center_interp) {
1275 switch (param) {
1276 case SI_PARAM_LINEAR_CENTROID:
1277 case SI_PARAM_LINEAR_SAMPLE:
1278 return SI_PARAM_LINEAR_CENTER;
1279 }
1280 }
1281
1282 return param;
1283 }
1284
1285 /**
1286 * Interpolate a fragment shader input.
1287 *
1288 * @param ctx context
1289 * @param input_index index of the input in hardware
1290 * @param semantic_name TGSI_SEMANTIC_*
1291 * @param semantic_index semantic index
1292 * @param num_interp_inputs number of all interpolated inputs (= BCOLOR offset)
1293 * @param colors_read_mask color components read (4 bits for each color, 8 bits in total)
1294 * @param interp_param interpolation weights (i,j)
1295 * @param prim_mask SI_PARAM_PRIM_MASK
1296 * @param face SI_PARAM_FRONT_FACE
1297 * @param result the return value (4 components)
1298 */
1299 static void interp_fs_input(struct si_shader_context *ctx,
1300 unsigned input_index,
1301 unsigned semantic_name,
1302 unsigned semantic_index,
1303 unsigned num_interp_inputs,
1304 unsigned colors_read_mask,
1305 LLVMValueRef interp_param,
1306 LLVMValueRef prim_mask,
1307 LLVMValueRef face,
1308 LLVMValueRef result[4])
1309 {
1310 struct lp_build_context *base = &ctx->radeon_bld.soa.bld_base.base;
1311 struct lp_build_context *uint = &ctx->radeon_bld.soa.bld_base.uint_bld;
1312 struct gallivm_state *gallivm = base->gallivm;
1313 const char *intr_name;
1314 LLVMValueRef attr_number;
1315
1316 unsigned chan;
1317
1318 attr_number = lp_build_const_int32(gallivm, input_index);
1319
1320 /* fs.constant returns the param from the middle vertex, so it's not
1321 * really useful for flat shading. It's meant to be used for custom
1322 * interpolation (but the intrinsic can't fetch from the other two
1323 * vertices).
1324 *
1325 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
1326 * to do the right thing. The only reason we use fs.constant is that
1327 * fs.interp cannot be used on integers, because they can be equal
1328 * to NaN.
1329 */
1330 intr_name = interp_param ? "llvm.SI.fs.interp" : "llvm.SI.fs.constant";
1331
1332 if (semantic_name == TGSI_SEMANTIC_COLOR &&
1333 ctx->shader->key.ps.prolog.color_two_side) {
1334 LLVMValueRef args[4];
1335 LLVMValueRef is_face_positive;
1336 LLVMValueRef back_attr_number;
1337
1338 /* If BCOLOR0 is used, BCOLOR1 is at offset "num_inputs + 1",
1339 * otherwise it's at offset "num_inputs".
1340 */
1341 unsigned back_attr_offset = num_interp_inputs;
1342 if (semantic_index == 1 && colors_read_mask & 0xf)
1343 back_attr_offset += 1;
1344
1345 back_attr_number = lp_build_const_int32(gallivm, back_attr_offset);
1346
1347 is_face_positive = LLVMBuildICmp(gallivm->builder, LLVMIntNE,
1348 face, uint->zero, "");
1349
1350 args[2] = prim_mask;
1351 args[3] = interp_param;
1352 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1353 LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan);
1354 LLVMValueRef front, back;
1355
1356 args[0] = llvm_chan;
1357 args[1] = attr_number;
1358 front = lp_build_intrinsic(gallivm->builder, intr_name,
1359 ctx->f32, args, args[3] ? 4 : 3,
1360 LLVMReadNoneAttribute);
1361
1362 args[1] = back_attr_number;
1363 back = lp_build_intrinsic(gallivm->builder, intr_name,
1364 ctx->f32, args, args[3] ? 4 : 3,
1365 LLVMReadNoneAttribute);
1366
1367 result[chan] = LLVMBuildSelect(gallivm->builder,
1368 is_face_positive,
1369 front,
1370 back,
1371 "");
1372 }
1373 } else if (semantic_name == TGSI_SEMANTIC_FOG) {
1374 LLVMValueRef args[4];
1375
1376 args[0] = uint->zero;
1377 args[1] = attr_number;
1378 args[2] = prim_mask;
1379 args[3] = interp_param;
1380 result[0] = lp_build_intrinsic(gallivm->builder, intr_name,
1381 ctx->f32, args, args[3] ? 4 : 3,
1382 LLVMReadNoneAttribute);
1383 result[1] =
1384 result[2] = lp_build_const_float(gallivm, 0.0f);
1385 result[3] = lp_build_const_float(gallivm, 1.0f);
1386 } else {
1387 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1388 LLVMValueRef args[4];
1389 LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan);
1390
1391 args[0] = llvm_chan;
1392 args[1] = attr_number;
1393 args[2] = prim_mask;
1394 args[3] = interp_param;
1395 result[chan] = lp_build_intrinsic(gallivm->builder, intr_name,
1396 ctx->f32, args, args[3] ? 4 : 3,
1397 LLVMReadNoneAttribute);
1398 }
1399 }
1400 }
1401
1402 /* LLVMGetParam with bc_optimize resolved. */
1403 static LLVMValueRef get_interp_param(struct si_shader_context *ctx,
1404 int interp_param_idx)
1405 {
1406 LLVMBuilderRef builder = ctx->radeon_bld.gallivm.builder;
1407 LLVMValueRef main_fn = ctx->radeon_bld.main_fn;
1408 LLVMValueRef param = NULL;
1409
1410 /* Handle PRIM_MASK[31] (bc_optimize). */
1411 if (ctx->is_monolithic &&
1412 ((ctx->shader->key.ps.prolog.bc_optimize_for_persp &&
1413 interp_param_idx == SI_PARAM_PERSP_CENTROID) ||
1414 (ctx->shader->key.ps.prolog.bc_optimize_for_linear &&
1415 interp_param_idx == SI_PARAM_LINEAR_CENTROID))) {
1416 /* The shader should do: if (PRIM_MASK[31]) CENTROID = CENTER;
1417 * The hw doesn't compute CENTROID if the whole wave only
1418 * contains fully-covered quads.
1419 */
1420 LLVMValueRef bc_optimize =
1421 LLVMGetParam(main_fn, SI_PARAM_PRIM_MASK);
1422 bc_optimize = LLVMBuildLShr(builder,
1423 bc_optimize,
1424 LLVMConstInt(ctx->i32, 31, 0), "");
1425 bc_optimize = LLVMBuildTrunc(builder, bc_optimize, ctx->i1, "");
1426
1427 if (ctx->shader->key.ps.prolog.bc_optimize_for_persp &&
1428 interp_param_idx == SI_PARAM_PERSP_CENTROID) {
1429 param = LLVMBuildSelect(builder, bc_optimize,
1430 LLVMGetParam(main_fn,
1431 SI_PARAM_PERSP_CENTER),
1432 LLVMGetParam(main_fn,
1433 SI_PARAM_PERSP_CENTROID),
1434 "");
1435 }
1436 if (ctx->shader->key.ps.prolog.bc_optimize_for_linear &&
1437 interp_param_idx == SI_PARAM_LINEAR_CENTROID) {
1438 param = LLVMBuildSelect(builder, bc_optimize,
1439 LLVMGetParam(main_fn,
1440 SI_PARAM_LINEAR_CENTER),
1441 LLVMGetParam(main_fn,
1442 SI_PARAM_LINEAR_CENTROID),
1443 "");
1444 }
1445 }
1446
1447 if (!param)
1448 param = LLVMGetParam(main_fn, interp_param_idx);
1449 return param;
1450 }
1451
1452 static void declare_input_fs(
1453 struct radeon_llvm_context *radeon_bld,
1454 unsigned input_index,
1455 const struct tgsi_full_declaration *decl,
1456 LLVMValueRef out[4])
1457 {
1458 struct lp_build_context *base = &radeon_bld->soa.bld_base.base;
1459 struct si_shader_context *ctx =
1460 si_shader_context(&radeon_bld->soa.bld_base);
1461 struct si_shader *shader = ctx->shader;
1462 LLVMValueRef main_fn = radeon_bld->main_fn;
1463 LLVMValueRef interp_param = NULL;
1464 int interp_param_idx;
1465
1466 /* Get colors from input VGPRs (set by the prolog). */
1467 if (!ctx->is_monolithic &&
1468 decl->Semantic.Name == TGSI_SEMANTIC_COLOR) {
1469 unsigned i = decl->Semantic.Index;
1470 unsigned colors_read = shader->selector->info.colors_read;
1471 unsigned mask = colors_read >> (i * 4);
1472 unsigned offset = SI_PARAM_POS_FIXED_PT + 1 +
1473 (i ? util_bitcount(colors_read & 0xf) : 0);
1474
1475 out[0] = mask & 0x1 ? LLVMGetParam(main_fn, offset++) : base->undef;
1476 out[1] = mask & 0x2 ? LLVMGetParam(main_fn, offset++) : base->undef;
1477 out[2] = mask & 0x4 ? LLVMGetParam(main_fn, offset++) : base->undef;
1478 out[3] = mask & 0x8 ? LLVMGetParam(main_fn, offset++) : base->undef;
1479 return;
1480 }
1481
1482 interp_param_idx = lookup_interp_param_index(decl->Interp.Interpolate,
1483 decl->Interp.Location);
1484 if (interp_param_idx == -1)
1485 return;
1486 else if (interp_param_idx) {
1487 interp_param_idx = select_interp_param(ctx,
1488 interp_param_idx);
1489 interp_param = get_interp_param(ctx, interp_param_idx);
1490 }
1491
1492 if (decl->Semantic.Name == TGSI_SEMANTIC_COLOR &&
1493 decl->Interp.Interpolate == TGSI_INTERPOLATE_COLOR &&
1494 ctx->shader->key.ps.prolog.flatshade_colors)
1495 interp_param = NULL; /* load the constant color */
1496
1497 interp_fs_input(ctx, input_index, decl->Semantic.Name,
1498 decl->Semantic.Index, shader->selector->info.num_inputs,
1499 shader->selector->info.colors_read, interp_param,
1500 LLVMGetParam(main_fn, SI_PARAM_PRIM_MASK),
1501 LLVMGetParam(main_fn, SI_PARAM_FRONT_FACE),
1502 &out[0]);
1503 }
1504
1505 static LLVMValueRef get_sample_id(struct radeon_llvm_context *radeon_bld)
1506 {
1507 return unpack_param(si_shader_context(&radeon_bld->soa.bld_base),
1508 SI_PARAM_ANCILLARY, 8, 4);
1509 }
1510
1511 /**
1512 * Set range metadata on an instruction. This can only be used on load and
1513 * call instructions. If you know an instruction can only produce the values
1514 * 0, 1, 2, you would do set_range_metadata(value, 0, 3);
1515 * \p lo is the minimum value inclusive.
1516 * \p hi is the maximum value exclusive.
1517 */
1518 static void set_range_metadata(struct si_shader_context *ctx,
1519 LLVMValueRef value, unsigned lo, unsigned hi)
1520 {
1521 LLVMValueRef range_md, md_args[2];
1522 LLVMTypeRef type = LLVMTypeOf(value);
1523 LLVMContextRef context = LLVMGetTypeContext(type);
1524
1525 md_args[0] = LLVMConstInt(type, lo, false);
1526 md_args[1] = LLVMConstInt(type, hi, false);
1527 range_md = LLVMMDNodeInContext(context, md_args, 2);
1528 LLVMSetMetadata(value, ctx->range_md_kind, range_md);
1529 }
1530
1531 static LLVMValueRef get_thread_id(struct si_shader_context *ctx)
1532 {
1533 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
1534 LLVMValueRef tid;
1535
1536 if (HAVE_LLVM < 0x0308) {
1537 tid = lp_build_intrinsic(gallivm->builder, "llvm.SI.tid",
1538 ctx->i32, NULL, 0, LLVMReadNoneAttribute);
1539 } else {
1540 LLVMValueRef tid_args[2];
1541 tid_args[0] = lp_build_const_int32(gallivm, 0xffffffff);
1542 tid_args[1] = lp_build_const_int32(gallivm, 0);
1543 tid_args[1] = lp_build_intrinsic(gallivm->builder,
1544 "llvm.amdgcn.mbcnt.lo", ctx->i32,
1545 tid_args, 2, LLVMReadNoneAttribute);
1546
1547 tid = lp_build_intrinsic(gallivm->builder,
1548 "llvm.amdgcn.mbcnt.hi", ctx->i32,
1549 tid_args, 2, LLVMReadNoneAttribute);
1550 }
1551 set_range_metadata(ctx, tid, 0, 64);
1552 return tid;
1553 }
1554
1555 /**
1556 * Load a dword from a constant buffer.
1557 */
1558 static LLVMValueRef buffer_load_const(struct si_shader_context *ctx,
1559 LLVMValueRef resource,
1560 LLVMValueRef offset)
1561 {
1562 LLVMBuilderRef builder = ctx->radeon_bld.gallivm.builder;
1563 LLVMValueRef args[2] = {resource, offset};
1564
1565 return lp_build_intrinsic(builder, "llvm.SI.load.const", ctx->f32, args, 2,
1566 LLVMReadNoneAttribute);
1567 }
1568
1569 static LLVMValueRef load_sample_position(struct radeon_llvm_context *radeon_bld, LLVMValueRef sample_id)
1570 {
1571 struct si_shader_context *ctx =
1572 si_shader_context(&radeon_bld->soa.bld_base);
1573 struct lp_build_context *uint_bld = &radeon_bld->soa.bld_base.uint_bld;
1574 struct gallivm_state *gallivm = &radeon_bld->gallivm;
1575 LLVMBuilderRef builder = gallivm->builder;
1576 LLVMValueRef desc = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_RW_BUFFERS);
1577 LLVMValueRef buf_index = lp_build_const_int32(gallivm, SI_PS_CONST_SAMPLE_POSITIONS);
1578 LLVMValueRef resource = build_indexed_load_const(ctx, desc, buf_index);
1579
1580 /* offset = sample_id * 8 (8 = 2 floats containing samplepos.xy) */
1581 LLVMValueRef offset0 = lp_build_mul_imm(uint_bld, sample_id, 8);
1582 LLVMValueRef offset1 = LLVMBuildAdd(builder, offset0, lp_build_const_int32(gallivm, 4), "");
1583
1584 LLVMValueRef pos[4] = {
1585 buffer_load_const(ctx, resource, offset0),
1586 buffer_load_const(ctx, resource, offset1),
1587 lp_build_const_float(gallivm, 0),
1588 lp_build_const_float(gallivm, 0)
1589 };
1590
1591 return lp_build_gather_values(gallivm, pos, 4);
1592 }
1593
1594 static void declare_system_value(
1595 struct radeon_llvm_context *radeon_bld,
1596 unsigned index,
1597 const struct tgsi_full_declaration *decl)
1598 {
1599 struct si_shader_context *ctx =
1600 si_shader_context(&radeon_bld->soa.bld_base);
1601 struct lp_build_context *bld = &radeon_bld->soa.bld_base.base;
1602 struct gallivm_state *gallivm = &radeon_bld->gallivm;
1603 LLVMValueRef value = 0;
1604
1605 switch (decl->Semantic.Name) {
1606 case TGSI_SEMANTIC_INSTANCEID:
1607 value = LLVMGetParam(radeon_bld->main_fn,
1608 ctx->param_instance_id);
1609 break;
1610
1611 case TGSI_SEMANTIC_VERTEXID:
1612 value = LLVMBuildAdd(gallivm->builder,
1613 LLVMGetParam(radeon_bld->main_fn,
1614 ctx->param_vertex_id),
1615 LLVMGetParam(radeon_bld->main_fn,
1616 SI_PARAM_BASE_VERTEX), "");
1617 break;
1618
1619 case TGSI_SEMANTIC_VERTEXID_NOBASE:
1620 value = LLVMGetParam(radeon_bld->main_fn,
1621 ctx->param_vertex_id);
1622 break;
1623
1624 case TGSI_SEMANTIC_BASEVERTEX:
1625 value = LLVMGetParam(radeon_bld->main_fn,
1626 SI_PARAM_BASE_VERTEX);
1627 break;
1628
1629 case TGSI_SEMANTIC_BASEINSTANCE:
1630 value = LLVMGetParam(radeon_bld->main_fn,
1631 SI_PARAM_START_INSTANCE);
1632 break;
1633
1634 case TGSI_SEMANTIC_DRAWID:
1635 value = LLVMGetParam(radeon_bld->main_fn,
1636 SI_PARAM_DRAWID);
1637 break;
1638
1639 case TGSI_SEMANTIC_INVOCATIONID:
1640 if (ctx->type == PIPE_SHADER_TESS_CTRL)
1641 value = unpack_param(ctx, SI_PARAM_REL_IDS, 8, 5);
1642 else if (ctx->type == PIPE_SHADER_GEOMETRY)
1643 value = LLVMGetParam(radeon_bld->main_fn,
1644 SI_PARAM_GS_INSTANCE_ID);
1645 else
1646 assert(!"INVOCATIONID not implemented");
1647 break;
1648
1649 case TGSI_SEMANTIC_POSITION:
1650 {
1651 LLVMValueRef pos[4] = {
1652 LLVMGetParam(radeon_bld->main_fn, SI_PARAM_POS_X_FLOAT),
1653 LLVMGetParam(radeon_bld->main_fn, SI_PARAM_POS_Y_FLOAT),
1654 LLVMGetParam(radeon_bld->main_fn, SI_PARAM_POS_Z_FLOAT),
1655 lp_build_emit_llvm_unary(&radeon_bld->soa.bld_base, TGSI_OPCODE_RCP,
1656 LLVMGetParam(radeon_bld->main_fn,
1657 SI_PARAM_POS_W_FLOAT)),
1658 };
1659 value = lp_build_gather_values(gallivm, pos, 4);
1660 break;
1661 }
1662
1663 case TGSI_SEMANTIC_FACE:
1664 value = LLVMGetParam(radeon_bld->main_fn, SI_PARAM_FRONT_FACE);
1665 break;
1666
1667 case TGSI_SEMANTIC_SAMPLEID:
1668 value = get_sample_id(radeon_bld);
1669 break;
1670
1671 case TGSI_SEMANTIC_SAMPLEPOS: {
1672 LLVMValueRef pos[4] = {
1673 LLVMGetParam(radeon_bld->main_fn, SI_PARAM_POS_X_FLOAT),
1674 LLVMGetParam(radeon_bld->main_fn, SI_PARAM_POS_Y_FLOAT),
1675 lp_build_const_float(gallivm, 0),
1676 lp_build_const_float(gallivm, 0)
1677 };
1678 pos[0] = lp_build_emit_llvm_unary(&radeon_bld->soa.bld_base,
1679 TGSI_OPCODE_FRC, pos[0]);
1680 pos[1] = lp_build_emit_llvm_unary(&radeon_bld->soa.bld_base,
1681 TGSI_OPCODE_FRC, pos[1]);
1682 value = lp_build_gather_values(gallivm, pos, 4);
1683 break;
1684 }
1685
1686 case TGSI_SEMANTIC_SAMPLEMASK:
1687 /* This can only occur with the OpenGL Core profile, which
1688 * doesn't support smoothing.
1689 */
1690 value = LLVMGetParam(radeon_bld->main_fn, SI_PARAM_SAMPLE_COVERAGE);
1691 break;
1692
1693 case TGSI_SEMANTIC_TESSCOORD:
1694 {
1695 LLVMValueRef coord[4] = {
1696 LLVMGetParam(radeon_bld->main_fn, ctx->param_tes_u),
1697 LLVMGetParam(radeon_bld->main_fn, ctx->param_tes_v),
1698 bld->zero,
1699 bld->zero
1700 };
1701
1702 /* For triangles, the vector should be (u, v, 1-u-v). */
1703 if (ctx->shader->selector->info.properties[TGSI_PROPERTY_TES_PRIM_MODE] ==
1704 PIPE_PRIM_TRIANGLES)
1705 coord[2] = lp_build_sub(bld, bld->one,
1706 lp_build_add(bld, coord[0], coord[1]));
1707
1708 value = lp_build_gather_values(gallivm, coord, 4);
1709 break;
1710 }
1711
1712 case TGSI_SEMANTIC_VERTICESIN:
1713 if (ctx->type == PIPE_SHADER_TESS_CTRL)
1714 value = unpack_param(ctx, SI_PARAM_TCS_OUT_LAYOUT, 26, 6);
1715 else if (ctx->type == PIPE_SHADER_TESS_EVAL)
1716 value = unpack_param(ctx, SI_PARAM_TCS_OFFCHIP_LAYOUT, 9, 7);
1717 else
1718 assert(!"invalid shader stage for TGSI_SEMANTIC_VERTICESIN");
1719 break;
1720
1721 case TGSI_SEMANTIC_TESSINNER:
1722 case TGSI_SEMANTIC_TESSOUTER:
1723 {
1724 LLVMValueRef rw_buffers, buffer, base, addr;
1725 int param = si_shader_io_get_unique_index(decl->Semantic.Name, 0);
1726
1727 rw_buffers = LLVMGetParam(ctx->radeon_bld.main_fn,
1728 SI_PARAM_RW_BUFFERS);
1729 buffer = build_indexed_load_const(ctx, rw_buffers,
1730 lp_build_const_int32(gallivm, SI_HS_RING_TESS_OFFCHIP));
1731
1732 base = LLVMGetParam(ctx->radeon_bld.main_fn, ctx->param_oc_lds);
1733 addr = get_tcs_tes_buffer_address(ctx, NULL,
1734 lp_build_const_int32(gallivm, param));
1735
1736 value = buffer_load(&radeon_bld->soa.bld_base, TGSI_TYPE_FLOAT,
1737 ~0, buffer, base, addr);
1738
1739 break;
1740 }
1741
1742 case TGSI_SEMANTIC_DEFAULT_TESSOUTER_SI:
1743 case TGSI_SEMANTIC_DEFAULT_TESSINNER_SI:
1744 {
1745 LLVMValueRef buf, slot, val[4];
1746 int i, offset;
1747
1748 slot = lp_build_const_int32(gallivm, SI_HS_CONST_DEFAULT_TESS_LEVELS);
1749 buf = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_RW_BUFFERS);
1750 buf = build_indexed_load_const(ctx, buf, slot);
1751 offset = decl->Semantic.Name == TGSI_SEMANTIC_DEFAULT_TESSINNER_SI ? 4 : 0;
1752
1753 for (i = 0; i < 4; i++)
1754 val[i] = buffer_load_const(ctx, buf,
1755 lp_build_const_int32(gallivm, (offset + i) * 4));
1756 value = lp_build_gather_values(gallivm, val, 4);
1757 break;
1758 }
1759
1760 case TGSI_SEMANTIC_PRIMID:
1761 value = get_primitive_id(&radeon_bld->soa.bld_base, 0);
1762 break;
1763
1764 case TGSI_SEMANTIC_GRID_SIZE:
1765 value = LLVMGetParam(radeon_bld->main_fn, SI_PARAM_GRID_SIZE);
1766 break;
1767
1768 case TGSI_SEMANTIC_BLOCK_SIZE:
1769 {
1770 LLVMValueRef values[3];
1771 unsigned i;
1772 unsigned *properties = ctx->shader->selector->info.properties;
1773 unsigned sizes[3] = {
1774 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH],
1775 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT],
1776 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH]
1777 };
1778
1779 for (i = 0; i < 3; ++i)
1780 values[i] = lp_build_const_int32(gallivm, sizes[i]);
1781
1782 value = lp_build_gather_values(gallivm, values, 3);
1783 break;
1784 }
1785
1786 case TGSI_SEMANTIC_BLOCK_ID:
1787 value = LLVMGetParam(radeon_bld->main_fn, SI_PARAM_BLOCK_ID);
1788 break;
1789
1790 case TGSI_SEMANTIC_THREAD_ID:
1791 value = LLVMGetParam(radeon_bld->main_fn, SI_PARAM_THREAD_ID);
1792 break;
1793
1794 #if HAVE_LLVM >= 0x0309
1795 case TGSI_SEMANTIC_HELPER_INVOCATION:
1796 value = lp_build_intrinsic(gallivm->builder,
1797 "llvm.amdgcn.ps.live",
1798 ctx->i1, NULL, 0,
1799 LLVMReadNoneAttribute);
1800 value = LLVMBuildNot(gallivm->builder, value, "");
1801 value = LLVMBuildSExt(gallivm->builder, value, ctx->i32, "");
1802 break;
1803 #endif
1804
1805 default:
1806 assert(!"unknown system value");
1807 return;
1808 }
1809
1810 radeon_bld->system_values[index] = value;
1811 }
1812
1813 static void declare_compute_memory(struct radeon_llvm_context *radeon_bld,
1814 const struct tgsi_full_declaration *decl)
1815 {
1816 struct si_shader_context *ctx =
1817 si_shader_context(&radeon_bld->soa.bld_base);
1818 struct si_shader_selector *sel = ctx->shader->selector;
1819 struct gallivm_state *gallivm = &radeon_bld->gallivm;
1820
1821 LLVMTypeRef i8p = LLVMPointerType(ctx->i8, LOCAL_ADDR_SPACE);
1822 LLVMValueRef var;
1823
1824 assert(decl->Declaration.MemType == TGSI_MEMORY_TYPE_SHARED);
1825 assert(decl->Range.First == decl->Range.Last);
1826 assert(!ctx->shared_memory);
1827
1828 var = LLVMAddGlobalInAddressSpace(gallivm->module,
1829 LLVMArrayType(ctx->i8, sel->local_size),
1830 "compute_lds",
1831 LOCAL_ADDR_SPACE);
1832 LLVMSetAlignment(var, 4);
1833
1834 ctx->shared_memory = LLVMBuildBitCast(gallivm->builder, var, i8p, "");
1835 }
1836
1837 static LLVMValueRef load_const_buffer_desc(struct si_shader_context *ctx, int i)
1838 {
1839 LLVMValueRef list_ptr = LLVMGetParam(ctx->radeon_bld.main_fn,
1840 SI_PARAM_CONST_BUFFERS);
1841
1842 return build_indexed_load_const(ctx, list_ptr,
1843 LLVMConstInt(ctx->i32, i, 0));
1844 }
1845
1846 static LLVMValueRef fetch_constant(
1847 struct lp_build_tgsi_context *bld_base,
1848 const struct tgsi_full_src_register *reg,
1849 enum tgsi_opcode_type type,
1850 unsigned swizzle)
1851 {
1852 struct si_shader_context *ctx = si_shader_context(bld_base);
1853 struct lp_build_context *base = &bld_base->base;
1854 const struct tgsi_ind_register *ireg = &reg->Indirect;
1855 unsigned buf, idx;
1856
1857 LLVMValueRef addr, bufp;
1858 LLVMValueRef result;
1859
1860 if (swizzle == LP_CHAN_ALL) {
1861 unsigned chan;
1862 LLVMValueRef values[4];
1863 for (chan = 0; chan < TGSI_NUM_CHANNELS; ++chan)
1864 values[chan] = fetch_constant(bld_base, reg, type, chan);
1865
1866 return lp_build_gather_values(bld_base->base.gallivm, values, 4);
1867 }
1868
1869 buf = reg->Register.Dimension ? reg->Dimension.Index : 0;
1870 idx = reg->Register.Index * 4 + swizzle;
1871
1872 if (!reg->Register.Indirect && !reg->Dimension.Indirect) {
1873 LLVMValueRef c0, c1, desc;
1874
1875 desc = load_const_buffer_desc(ctx, buf);
1876 c0 = buffer_load_const(ctx, desc,
1877 LLVMConstInt(ctx->i32, idx * 4, 0));
1878
1879 if (!tgsi_type_is_64bit(type))
1880 return bitcast(bld_base, type, c0);
1881 else {
1882 c1 = buffer_load_const(ctx, desc,
1883 LLVMConstInt(ctx->i32,
1884 (idx + 1) * 4, 0));
1885 return radeon_llvm_emit_fetch_64bit(bld_base, type,
1886 c0, c1);
1887 }
1888 }
1889
1890 if (reg->Register.Dimension && reg->Dimension.Indirect) {
1891 LLVMValueRef ptr = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_CONST_BUFFERS);
1892 LLVMValueRef index;
1893 index = get_bounded_indirect_index(ctx, &reg->DimIndirect,
1894 reg->Dimension.Index,
1895 SI_NUM_CONST_BUFFERS);
1896 bufp = build_indexed_load_const(ctx, ptr, index);
1897 } else
1898 bufp = load_const_buffer_desc(ctx, buf);
1899
1900 addr = ctx->radeon_bld.soa.addr[ireg->Index][ireg->Swizzle];
1901 addr = LLVMBuildLoad(base->gallivm->builder, addr, "load addr reg");
1902 addr = lp_build_mul_imm(&bld_base->uint_bld, addr, 16);
1903 addr = lp_build_add(&bld_base->uint_bld, addr,
1904 lp_build_const_int32(base->gallivm, idx * 4));
1905
1906 result = buffer_load_const(ctx, bufp, addr);
1907
1908 if (!tgsi_type_is_64bit(type))
1909 result = bitcast(bld_base, type, result);
1910 else {
1911 LLVMValueRef addr2, result2;
1912 addr2 = ctx->radeon_bld.soa.addr[ireg->Index][ireg->Swizzle + 1];
1913 addr2 = LLVMBuildLoad(base->gallivm->builder, addr2, "load addr reg2");
1914 addr2 = lp_build_mul_imm(&bld_base->uint_bld, addr2, 16);
1915 addr2 = lp_build_add(&bld_base->uint_bld, addr2,
1916 lp_build_const_int32(base->gallivm, idx * 4));
1917
1918 result2 = buffer_load_const(ctx, bufp, addr2);
1919
1920 result = radeon_llvm_emit_fetch_64bit(bld_base, type,
1921 result, result2);
1922 }
1923 return result;
1924 }
1925
1926 /* Upper 16 bits must be zero. */
1927 static LLVMValueRef si_llvm_pack_two_int16(struct gallivm_state *gallivm,
1928 LLVMValueRef val[2])
1929 {
1930 return LLVMBuildOr(gallivm->builder, val[0],
1931 LLVMBuildShl(gallivm->builder, val[1],
1932 lp_build_const_int32(gallivm, 16),
1933 ""), "");
1934 }
1935
1936 /* Upper 16 bits are ignored and will be dropped. */
1937 static LLVMValueRef si_llvm_pack_two_int32_as_int16(struct gallivm_state *gallivm,
1938 LLVMValueRef val[2])
1939 {
1940 LLVMValueRef v[2] = {
1941 LLVMBuildAnd(gallivm->builder, val[0],
1942 lp_build_const_int32(gallivm, 0xffff), ""),
1943 val[1],
1944 };
1945 return si_llvm_pack_two_int16(gallivm, v);
1946 }
1947
1948 /* Initialize arguments for the shader export intrinsic */
1949 static void si_llvm_init_export_args(struct lp_build_tgsi_context *bld_base,
1950 LLVMValueRef *values,
1951 unsigned target,
1952 LLVMValueRef *args)
1953 {
1954 struct si_shader_context *ctx = si_shader_context(bld_base);
1955 struct lp_build_context *uint =
1956 &ctx->radeon_bld.soa.bld_base.uint_bld;
1957 struct lp_build_context *base = &bld_base->base;
1958 struct gallivm_state *gallivm = base->gallivm;
1959 LLVMBuilderRef builder = base->gallivm->builder;
1960 LLVMValueRef val[4];
1961 unsigned spi_shader_col_format = V_028714_SPI_SHADER_32_ABGR;
1962 unsigned chan;
1963 bool is_int8;
1964
1965 /* Default is 0xf. Adjusted below depending on the format. */
1966 args[0] = lp_build_const_int32(base->gallivm, 0xf); /* writemask */
1967
1968 /* Specify whether the EXEC mask represents the valid mask */
1969 args[1] = uint->zero;
1970
1971 /* Specify whether this is the last export */
1972 args[2] = uint->zero;
1973
1974 /* Specify the target we are exporting */
1975 args[3] = lp_build_const_int32(base->gallivm, target);
1976
1977 if (ctx->type == PIPE_SHADER_FRAGMENT) {
1978 const union si_shader_key *key = &ctx->shader->key;
1979 unsigned col_formats = key->ps.epilog.spi_shader_col_format;
1980 int cbuf = target - V_008DFC_SQ_EXP_MRT;
1981
1982 assert(cbuf >= 0 && cbuf < 8);
1983 spi_shader_col_format = (col_formats >> (cbuf * 4)) & 0xf;
1984 is_int8 = (key->ps.epilog.color_is_int8 >> cbuf) & 0x1;
1985 }
1986
1987 args[4] = uint->zero; /* COMPR flag */
1988 args[5] = base->undef;
1989 args[6] = base->undef;
1990 args[7] = base->undef;
1991 args[8] = base->undef;
1992
1993 switch (spi_shader_col_format) {
1994 case V_028714_SPI_SHADER_ZERO:
1995 args[0] = uint->zero; /* writemask */
1996 args[3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_NULL);
1997 break;
1998
1999 case V_028714_SPI_SHADER_32_R:
2000 args[0] = uint->one; /* writemask */
2001 args[5] = values[0];
2002 break;
2003
2004 case V_028714_SPI_SHADER_32_GR:
2005 args[0] = lp_build_const_int32(base->gallivm, 0x3); /* writemask */
2006 args[5] = values[0];
2007 args[6] = values[1];
2008 break;
2009
2010 case V_028714_SPI_SHADER_32_AR:
2011 args[0] = lp_build_const_int32(base->gallivm, 0x9); /* writemask */
2012 args[5] = values[0];
2013 args[8] = values[3];
2014 break;
2015
2016 case V_028714_SPI_SHADER_FP16_ABGR:
2017 args[4] = uint->one; /* COMPR flag */
2018
2019 for (chan = 0; chan < 2; chan++) {
2020 LLVMValueRef pack_args[2] = {
2021 values[2 * chan],
2022 values[2 * chan + 1]
2023 };
2024 LLVMValueRef packed;
2025
2026 packed = lp_build_intrinsic(base->gallivm->builder,
2027 "llvm.SI.packf16",
2028 ctx->i32, pack_args, 2,
2029 LLVMReadNoneAttribute);
2030 args[chan + 5] =
2031 LLVMBuildBitCast(base->gallivm->builder,
2032 packed, ctx->f32, "");
2033 }
2034 break;
2035
2036 case V_028714_SPI_SHADER_UNORM16_ABGR:
2037 for (chan = 0; chan < 4; chan++) {
2038 val[chan] = radeon_llvm_saturate(bld_base, values[chan]);
2039 val[chan] = LLVMBuildFMul(builder, val[chan],
2040 lp_build_const_float(gallivm, 65535), "");
2041 val[chan] = LLVMBuildFAdd(builder, val[chan],
2042 lp_build_const_float(gallivm, 0.5), "");
2043 val[chan] = LLVMBuildFPToUI(builder, val[chan],
2044 ctx->i32, "");
2045 }
2046
2047 args[4] = uint->one; /* COMPR flag */
2048 args[5] = bitcast(bld_base, TGSI_TYPE_FLOAT,
2049 si_llvm_pack_two_int16(gallivm, val));
2050 args[6] = bitcast(bld_base, TGSI_TYPE_FLOAT,
2051 si_llvm_pack_two_int16(gallivm, val+2));
2052 break;
2053
2054 case V_028714_SPI_SHADER_SNORM16_ABGR:
2055 for (chan = 0; chan < 4; chan++) {
2056 /* Clamp between [-1, 1]. */
2057 val[chan] = lp_build_emit_llvm_binary(bld_base, TGSI_OPCODE_MIN,
2058 values[chan],
2059 lp_build_const_float(gallivm, 1));
2060 val[chan] = lp_build_emit_llvm_binary(bld_base, TGSI_OPCODE_MAX,
2061 val[chan],
2062 lp_build_const_float(gallivm, -1));
2063 /* Convert to a signed integer in [-32767, 32767]. */
2064 val[chan] = LLVMBuildFMul(builder, val[chan],
2065 lp_build_const_float(gallivm, 32767), "");
2066 /* If positive, add 0.5, else add -0.5. */
2067 val[chan] = LLVMBuildFAdd(builder, val[chan],
2068 LLVMBuildSelect(builder,
2069 LLVMBuildFCmp(builder, LLVMRealOGE,
2070 val[chan], base->zero, ""),
2071 lp_build_const_float(gallivm, 0.5),
2072 lp_build_const_float(gallivm, -0.5), ""), "");
2073 val[chan] = LLVMBuildFPToSI(builder, val[chan], ctx->i32, "");
2074 }
2075
2076 args[4] = uint->one; /* COMPR flag */
2077 args[5] = bitcast(bld_base, TGSI_TYPE_FLOAT,
2078 si_llvm_pack_two_int32_as_int16(gallivm, val));
2079 args[6] = bitcast(bld_base, TGSI_TYPE_FLOAT,
2080 si_llvm_pack_two_int32_as_int16(gallivm, val+2));
2081 break;
2082
2083 case V_028714_SPI_SHADER_UINT16_ABGR: {
2084 LLVMValueRef max = lp_build_const_int32(gallivm, is_int8 ?
2085 255 : 65535);
2086 /* Clamp. */
2087 for (chan = 0; chan < 4; chan++) {
2088 val[chan] = bitcast(bld_base, TGSI_TYPE_UNSIGNED, values[chan]);
2089 val[chan] = lp_build_emit_llvm_binary(bld_base, TGSI_OPCODE_UMIN,
2090 val[chan], max);
2091 }
2092
2093 args[4] = uint->one; /* COMPR flag */
2094 args[5] = bitcast(bld_base, TGSI_TYPE_FLOAT,
2095 si_llvm_pack_two_int16(gallivm, val));
2096 args[6] = bitcast(bld_base, TGSI_TYPE_FLOAT,
2097 si_llvm_pack_two_int16(gallivm, val+2));
2098 break;
2099 }
2100
2101 case V_028714_SPI_SHADER_SINT16_ABGR: {
2102 LLVMValueRef max = lp_build_const_int32(gallivm, is_int8 ?
2103 127 : 32767);
2104 LLVMValueRef min = lp_build_const_int32(gallivm, is_int8 ?
2105 -128 : -32768);
2106 /* Clamp. */
2107 for (chan = 0; chan < 4; chan++) {
2108 val[chan] = bitcast(bld_base, TGSI_TYPE_UNSIGNED, values[chan]);
2109 val[chan] = lp_build_emit_llvm_binary(bld_base,
2110 TGSI_OPCODE_IMIN,
2111 val[chan], max);
2112 val[chan] = lp_build_emit_llvm_binary(bld_base,
2113 TGSI_OPCODE_IMAX,
2114 val[chan], min);
2115 }
2116
2117 args[4] = uint->one; /* COMPR flag */
2118 args[5] = bitcast(bld_base, TGSI_TYPE_FLOAT,
2119 si_llvm_pack_two_int32_as_int16(gallivm, val));
2120 args[6] = bitcast(bld_base, TGSI_TYPE_FLOAT,
2121 si_llvm_pack_two_int32_as_int16(gallivm, val+2));
2122 break;
2123 }
2124
2125 case V_028714_SPI_SHADER_32_ABGR:
2126 memcpy(&args[5], values, sizeof(values[0]) * 4);
2127 break;
2128 }
2129 }
2130
2131 static void si_alpha_test(struct lp_build_tgsi_context *bld_base,
2132 LLVMValueRef alpha)
2133 {
2134 struct si_shader_context *ctx = si_shader_context(bld_base);
2135 struct gallivm_state *gallivm = bld_base->base.gallivm;
2136
2137 if (ctx->shader->key.ps.epilog.alpha_func != PIPE_FUNC_NEVER) {
2138 LLVMValueRef alpha_ref = LLVMGetParam(ctx->radeon_bld.main_fn,
2139 SI_PARAM_ALPHA_REF);
2140
2141 LLVMValueRef alpha_pass =
2142 lp_build_cmp(&bld_base->base,
2143 ctx->shader->key.ps.epilog.alpha_func,
2144 alpha, alpha_ref);
2145 LLVMValueRef arg =
2146 lp_build_select(&bld_base->base,
2147 alpha_pass,
2148 lp_build_const_float(gallivm, 1.0f),
2149 lp_build_const_float(gallivm, -1.0f));
2150
2151 lp_build_intrinsic(gallivm->builder, "llvm.AMDGPU.kill",
2152 ctx->voidt, &arg, 1, 0);
2153 } else {
2154 lp_build_intrinsic(gallivm->builder, "llvm.AMDGPU.kilp",
2155 ctx->voidt, NULL, 0, 0);
2156 }
2157 }
2158
2159 static LLVMValueRef si_scale_alpha_by_sample_mask(struct lp_build_tgsi_context *bld_base,
2160 LLVMValueRef alpha,
2161 unsigned samplemask_param)
2162 {
2163 struct si_shader_context *ctx = si_shader_context(bld_base);
2164 struct gallivm_state *gallivm = bld_base->base.gallivm;
2165 LLVMValueRef coverage;
2166
2167 /* alpha = alpha * popcount(coverage) / SI_NUM_SMOOTH_AA_SAMPLES */
2168 coverage = LLVMGetParam(ctx->radeon_bld.main_fn,
2169 samplemask_param);
2170 coverage = bitcast(bld_base, TGSI_TYPE_SIGNED, coverage);
2171
2172 coverage = lp_build_intrinsic(gallivm->builder, "llvm.ctpop.i32",
2173 ctx->i32,
2174 &coverage, 1, LLVMReadNoneAttribute);
2175
2176 coverage = LLVMBuildUIToFP(gallivm->builder, coverage,
2177 ctx->f32, "");
2178
2179 coverage = LLVMBuildFMul(gallivm->builder, coverage,
2180 lp_build_const_float(gallivm,
2181 1.0 / SI_NUM_SMOOTH_AA_SAMPLES), "");
2182
2183 return LLVMBuildFMul(gallivm->builder, alpha, coverage, "");
2184 }
2185
2186 static void si_llvm_emit_clipvertex(struct lp_build_tgsi_context *bld_base,
2187 LLVMValueRef (*pos)[9], LLVMValueRef *out_elts)
2188 {
2189 struct si_shader_context *ctx = si_shader_context(bld_base);
2190 struct lp_build_context *base = &bld_base->base;
2191 struct lp_build_context *uint = &ctx->radeon_bld.soa.bld_base.uint_bld;
2192 unsigned reg_index;
2193 unsigned chan;
2194 unsigned const_chan;
2195 LLVMValueRef base_elt;
2196 LLVMValueRef ptr = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_RW_BUFFERS);
2197 LLVMValueRef constbuf_index = lp_build_const_int32(base->gallivm,
2198 SI_VS_CONST_CLIP_PLANES);
2199 LLVMValueRef const_resource = build_indexed_load_const(ctx, ptr, constbuf_index);
2200
2201 for (reg_index = 0; reg_index < 2; reg_index ++) {
2202 LLVMValueRef *args = pos[2 + reg_index];
2203
2204 args[5] =
2205 args[6] =
2206 args[7] =
2207 args[8] = lp_build_const_float(base->gallivm, 0.0f);
2208
2209 /* Compute dot products of position and user clip plane vectors */
2210 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2211 for (const_chan = 0; const_chan < TGSI_NUM_CHANNELS; const_chan++) {
2212 args[1] = lp_build_const_int32(base->gallivm,
2213 ((reg_index * 4 + chan) * 4 +
2214 const_chan) * 4);
2215 base_elt = buffer_load_const(ctx, const_resource,
2216 args[1]);
2217 args[5 + chan] =
2218 lp_build_add(base, args[5 + chan],
2219 lp_build_mul(base, base_elt,
2220 out_elts[const_chan]));
2221 }
2222 }
2223
2224 args[0] = lp_build_const_int32(base->gallivm, 0xf);
2225 args[1] = uint->zero;
2226 args[2] = uint->zero;
2227 args[3] = lp_build_const_int32(base->gallivm,
2228 V_008DFC_SQ_EXP_POS + 2 + reg_index);
2229 args[4] = uint->zero;
2230 }
2231 }
2232
2233 static void si_dump_streamout(struct pipe_stream_output_info *so)
2234 {
2235 unsigned i;
2236
2237 if (so->num_outputs)
2238 fprintf(stderr, "STREAMOUT\n");
2239
2240 for (i = 0; i < so->num_outputs; i++) {
2241 unsigned mask = ((1 << so->output[i].num_components) - 1) <<
2242 so->output[i].start_component;
2243 fprintf(stderr, " %i: BUF%i[%i..%i] <- OUT[%i].%s%s%s%s\n",
2244 i, so->output[i].output_buffer,
2245 so->output[i].dst_offset, so->output[i].dst_offset + so->output[i].num_components - 1,
2246 so->output[i].register_index,
2247 mask & 1 ? "x" : "",
2248 mask & 2 ? "y" : "",
2249 mask & 4 ? "z" : "",
2250 mask & 8 ? "w" : "");
2251 }
2252 }
2253
2254 /* On SI, the vertex shader is responsible for writing streamout data
2255 * to buffers. */
2256 static void si_llvm_emit_streamout(struct si_shader_context *ctx,
2257 struct si_shader_output_values *outputs,
2258 unsigned noutput)
2259 {
2260 struct pipe_stream_output_info *so = &ctx->shader->selector->so;
2261 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
2262 LLVMBuilderRef builder = gallivm->builder;
2263 int i, j;
2264 struct lp_build_if_state if_ctx;
2265 LLVMValueRef so_buffers[4];
2266 LLVMValueRef buf_ptr = LLVMGetParam(ctx->radeon_bld.main_fn,
2267 SI_PARAM_RW_BUFFERS);
2268
2269 /* Load the descriptors. */
2270 for (i = 0; i < 4; ++i) {
2271 if (ctx->shader->selector->so.stride[i]) {
2272 LLVMValueRef offset = lp_build_const_int32(gallivm,
2273 SI_VS_STREAMOUT_BUF0 + i);
2274
2275 so_buffers[i] = build_indexed_load_const(ctx, buf_ptr, offset);
2276 }
2277 }
2278
2279 /* Get bits [22:16], i.e. (so_param >> 16) & 127; */
2280 LLVMValueRef so_vtx_count =
2281 unpack_param(ctx, ctx->param_streamout_config, 16, 7);
2282
2283 LLVMValueRef tid = get_thread_id(ctx);
2284
2285 /* can_emit = tid < so_vtx_count; */
2286 LLVMValueRef can_emit =
2287 LLVMBuildICmp(builder, LLVMIntULT, tid, so_vtx_count, "");
2288
2289 LLVMValueRef stream_id =
2290 unpack_param(ctx, ctx->param_streamout_config, 24, 2);
2291
2292 /* Emit the streamout code conditionally. This actually avoids
2293 * out-of-bounds buffer access. The hw tells us via the SGPR
2294 * (so_vtx_count) which threads are allowed to emit streamout data. */
2295 lp_build_if(&if_ctx, gallivm, can_emit);
2296 {
2297 /* The buffer offset is computed as follows:
2298 * ByteOffset = streamout_offset[buffer_id]*4 +
2299 * (streamout_write_index + thread_id)*stride[buffer_id] +
2300 * attrib_offset
2301 */
2302
2303 LLVMValueRef so_write_index =
2304 LLVMGetParam(ctx->radeon_bld.main_fn,
2305 ctx->param_streamout_write_index);
2306
2307 /* Compute (streamout_write_index + thread_id). */
2308 so_write_index = LLVMBuildAdd(builder, so_write_index, tid, "");
2309
2310 /* Compute the write offset for each enabled buffer. */
2311 LLVMValueRef so_write_offset[4] = {};
2312 for (i = 0; i < 4; i++) {
2313 if (!so->stride[i])
2314 continue;
2315
2316 LLVMValueRef so_offset = LLVMGetParam(ctx->radeon_bld.main_fn,
2317 ctx->param_streamout_offset[i]);
2318 so_offset = LLVMBuildMul(builder, so_offset, LLVMConstInt(ctx->i32, 4, 0), "");
2319
2320 so_write_offset[i] = LLVMBuildMul(builder, so_write_index,
2321 LLVMConstInt(ctx->i32, so->stride[i]*4, 0), "");
2322 so_write_offset[i] = LLVMBuildAdd(builder, so_write_offset[i], so_offset, "");
2323 }
2324
2325 /* Write streamout data. */
2326 for (i = 0; i < so->num_outputs; i++) {
2327 unsigned buf_idx = so->output[i].output_buffer;
2328 unsigned reg = so->output[i].register_index;
2329 unsigned start = so->output[i].start_component;
2330 unsigned num_comps = so->output[i].num_components;
2331 unsigned stream = so->output[i].stream;
2332 LLVMValueRef out[4];
2333 struct lp_build_if_state if_ctx_stream;
2334
2335 assert(num_comps && num_comps <= 4);
2336 if (!num_comps || num_comps > 4)
2337 continue;
2338
2339 if (reg >= noutput)
2340 continue;
2341
2342 /* Load the output as int. */
2343 for (j = 0; j < num_comps; j++) {
2344 out[j] = LLVMBuildBitCast(builder,
2345 outputs[reg].values[start+j],
2346 ctx->i32, "");
2347 }
2348
2349 /* Pack the output. */
2350 LLVMValueRef vdata = NULL;
2351
2352 switch (num_comps) {
2353 case 1: /* as i32 */
2354 vdata = out[0];
2355 break;
2356 case 2: /* as v2i32 */
2357 case 3: /* as v4i32 (aligned to 4) */
2358 case 4: /* as v4i32 */
2359 vdata = LLVMGetUndef(LLVMVectorType(ctx->i32, util_next_power_of_two(num_comps)));
2360 for (j = 0; j < num_comps; j++) {
2361 vdata = LLVMBuildInsertElement(builder, vdata, out[j],
2362 LLVMConstInt(ctx->i32, j, 0), "");
2363 }
2364 break;
2365 }
2366
2367 LLVMValueRef can_emit_stream =
2368 LLVMBuildICmp(builder, LLVMIntEQ,
2369 stream_id,
2370 lp_build_const_int32(gallivm, stream), "");
2371
2372 lp_build_if(&if_ctx_stream, gallivm, can_emit_stream);
2373 build_tbuffer_store_dwords(ctx, so_buffers[buf_idx],
2374 vdata, num_comps,
2375 so_write_offset[buf_idx],
2376 LLVMConstInt(ctx->i32, 0, 0),
2377 so->output[i].dst_offset*4);
2378 lp_build_endif(&if_ctx_stream);
2379 }
2380 }
2381 lp_build_endif(&if_ctx);
2382 }
2383
2384
2385 /* Generate export instructions for hardware VS shader stage */
2386 static void si_llvm_export_vs(struct lp_build_tgsi_context *bld_base,
2387 struct si_shader_output_values *outputs,
2388 unsigned noutput)
2389 {
2390 struct si_shader_context *ctx = si_shader_context(bld_base);
2391 struct si_shader *shader = ctx->shader;
2392 struct lp_build_context *base = &bld_base->base;
2393 struct lp_build_context *uint =
2394 &ctx->radeon_bld.soa.bld_base.uint_bld;
2395 LLVMValueRef args[9];
2396 LLVMValueRef pos_args[4][9] = { { 0 } };
2397 LLVMValueRef psize_value = NULL, edgeflag_value = NULL, layer_value = NULL, viewport_index_value = NULL;
2398 unsigned semantic_name, semantic_index;
2399 unsigned target;
2400 unsigned param_count = 0;
2401 unsigned pos_idx;
2402 int i;
2403
2404 if (outputs && ctx->shader->selector->so.num_outputs) {
2405 si_llvm_emit_streamout(ctx, outputs, noutput);
2406 }
2407
2408 for (i = 0; i < noutput; i++) {
2409 semantic_name = outputs[i].name;
2410 semantic_index = outputs[i].sid;
2411
2412 handle_semantic:
2413 /* Select the correct target */
2414 switch(semantic_name) {
2415 case TGSI_SEMANTIC_PSIZE:
2416 psize_value = outputs[i].values[0];
2417 continue;
2418 case TGSI_SEMANTIC_EDGEFLAG:
2419 edgeflag_value = outputs[i].values[0];
2420 continue;
2421 case TGSI_SEMANTIC_LAYER:
2422 layer_value = outputs[i].values[0];
2423 semantic_name = TGSI_SEMANTIC_GENERIC;
2424 goto handle_semantic;
2425 case TGSI_SEMANTIC_VIEWPORT_INDEX:
2426 viewport_index_value = outputs[i].values[0];
2427 semantic_name = TGSI_SEMANTIC_GENERIC;
2428 goto handle_semantic;
2429 case TGSI_SEMANTIC_POSITION:
2430 target = V_008DFC_SQ_EXP_POS;
2431 break;
2432 case TGSI_SEMANTIC_COLOR:
2433 case TGSI_SEMANTIC_BCOLOR:
2434 target = V_008DFC_SQ_EXP_PARAM + param_count;
2435 assert(i < ARRAY_SIZE(shader->info.vs_output_param_offset));
2436 shader->info.vs_output_param_offset[i] = param_count;
2437 param_count++;
2438 break;
2439 case TGSI_SEMANTIC_CLIPDIST:
2440 target = V_008DFC_SQ_EXP_POS + 2 + semantic_index;
2441 break;
2442 case TGSI_SEMANTIC_CLIPVERTEX:
2443 si_llvm_emit_clipvertex(bld_base, pos_args, outputs[i].values);
2444 continue;
2445 case TGSI_SEMANTIC_PRIMID:
2446 case TGSI_SEMANTIC_FOG:
2447 case TGSI_SEMANTIC_TEXCOORD:
2448 case TGSI_SEMANTIC_GENERIC:
2449 target = V_008DFC_SQ_EXP_PARAM + param_count;
2450 assert(i < ARRAY_SIZE(shader->info.vs_output_param_offset));
2451 shader->info.vs_output_param_offset[i] = param_count;
2452 param_count++;
2453 break;
2454 default:
2455 target = 0;
2456 fprintf(stderr,
2457 "Warning: SI unhandled vs output type:%d\n",
2458 semantic_name);
2459 }
2460
2461 si_llvm_init_export_args(bld_base, outputs[i].values, target, args);
2462
2463 if (target >= V_008DFC_SQ_EXP_POS &&
2464 target <= (V_008DFC_SQ_EXP_POS + 3)) {
2465 memcpy(pos_args[target - V_008DFC_SQ_EXP_POS],
2466 args, sizeof(args));
2467 } else {
2468 lp_build_intrinsic(base->gallivm->builder,
2469 "llvm.SI.export", ctx->voidt,
2470 args, 9, 0);
2471 }
2472
2473 if (semantic_name == TGSI_SEMANTIC_CLIPDIST) {
2474 semantic_name = TGSI_SEMANTIC_GENERIC;
2475 goto handle_semantic;
2476 }
2477 }
2478
2479 shader->info.nr_param_exports = param_count;
2480
2481 /* We need to add the position output manually if it's missing. */
2482 if (!pos_args[0][0]) {
2483 pos_args[0][0] = lp_build_const_int32(base->gallivm, 0xf); /* writemask */
2484 pos_args[0][1] = uint->zero; /* EXEC mask */
2485 pos_args[0][2] = uint->zero; /* last export? */
2486 pos_args[0][3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_POS);
2487 pos_args[0][4] = uint->zero; /* COMPR flag */
2488 pos_args[0][5] = base->zero; /* X */
2489 pos_args[0][6] = base->zero; /* Y */
2490 pos_args[0][7] = base->zero; /* Z */
2491 pos_args[0][8] = base->one; /* W */
2492 }
2493
2494 /* Write the misc vector (point size, edgeflag, layer, viewport). */
2495 if (shader->selector->info.writes_psize ||
2496 shader->selector->info.writes_edgeflag ||
2497 shader->selector->info.writes_viewport_index ||
2498 shader->selector->info.writes_layer) {
2499 pos_args[1][0] = lp_build_const_int32(base->gallivm, /* writemask */
2500 shader->selector->info.writes_psize |
2501 (shader->selector->info.writes_edgeflag << 1) |
2502 (shader->selector->info.writes_layer << 2) |
2503 (shader->selector->info.writes_viewport_index << 3));
2504 pos_args[1][1] = uint->zero; /* EXEC mask */
2505 pos_args[1][2] = uint->zero; /* last export? */
2506 pos_args[1][3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_POS + 1);
2507 pos_args[1][4] = uint->zero; /* COMPR flag */
2508 pos_args[1][5] = base->zero; /* X */
2509 pos_args[1][6] = base->zero; /* Y */
2510 pos_args[1][7] = base->zero; /* Z */
2511 pos_args[1][8] = base->zero; /* W */
2512
2513 if (shader->selector->info.writes_psize)
2514 pos_args[1][5] = psize_value;
2515
2516 if (shader->selector->info.writes_edgeflag) {
2517 /* The output is a float, but the hw expects an integer
2518 * with the first bit containing the edge flag. */
2519 edgeflag_value = LLVMBuildFPToUI(base->gallivm->builder,
2520 edgeflag_value,
2521 ctx->i32, "");
2522 edgeflag_value = lp_build_min(&bld_base->int_bld,
2523 edgeflag_value,
2524 bld_base->int_bld.one);
2525
2526 /* The LLVM intrinsic expects a float. */
2527 pos_args[1][6] = LLVMBuildBitCast(base->gallivm->builder,
2528 edgeflag_value,
2529 ctx->f32, "");
2530 }
2531
2532 if (shader->selector->info.writes_layer)
2533 pos_args[1][7] = layer_value;
2534
2535 if (shader->selector->info.writes_viewport_index)
2536 pos_args[1][8] = viewport_index_value;
2537 }
2538
2539 for (i = 0; i < 4; i++)
2540 if (pos_args[i][0])
2541 shader->info.nr_pos_exports++;
2542
2543 pos_idx = 0;
2544 for (i = 0; i < 4; i++) {
2545 if (!pos_args[i][0])
2546 continue;
2547
2548 /* Specify the target we are exporting */
2549 pos_args[i][3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_POS + pos_idx++);
2550
2551 if (pos_idx == shader->info.nr_pos_exports)
2552 /* Specify that this is the last export */
2553 pos_args[i][2] = uint->one;
2554
2555 lp_build_intrinsic(base->gallivm->builder, "llvm.SI.export",
2556 ctx->voidt, pos_args[i], 9, 0);
2557 }
2558 }
2559
2560 static void si_copy_tcs_inputs(struct lp_build_tgsi_context *bld_base)
2561 {
2562 struct si_shader_context *ctx = si_shader_context(bld_base);
2563 struct gallivm_state *gallivm = bld_base->base.gallivm;
2564 LLVMValueRef invocation_id, rw_buffers, buffer, buffer_offset;
2565 LLVMValueRef lds_vertex_stride, lds_vertex_offset, lds_base;
2566 uint64_t inputs;
2567
2568 invocation_id = unpack_param(ctx, SI_PARAM_REL_IDS, 8, 5);
2569
2570 rw_buffers = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_RW_BUFFERS);
2571 buffer = build_indexed_load_const(ctx, rw_buffers,
2572 lp_build_const_int32(gallivm, SI_HS_RING_TESS_OFFCHIP));
2573
2574 buffer_offset = LLVMGetParam(ctx->radeon_bld.main_fn, ctx->param_oc_lds);
2575
2576 lds_vertex_stride = unpack_param(ctx, SI_PARAM_TCS_IN_LAYOUT, 13, 8);
2577 lds_vertex_offset = LLVMBuildMul(gallivm->builder, invocation_id,
2578 lds_vertex_stride, "");
2579 lds_base = get_tcs_in_current_patch_offset(ctx);
2580 lds_base = LLVMBuildAdd(gallivm->builder, lds_base, lds_vertex_offset, "");
2581
2582 inputs = ctx->shader->key.tcs.epilog.inputs_to_copy;
2583 while (inputs) {
2584 unsigned i = u_bit_scan64(&inputs);
2585
2586 LLVMValueRef lds_ptr = LLVMBuildAdd(gallivm->builder, lds_base,
2587 lp_build_const_int32(gallivm, 4 * i),
2588 "");
2589
2590 LLVMValueRef buffer_addr = get_tcs_tes_buffer_address(ctx,
2591 invocation_id,
2592 lp_build_const_int32(gallivm, i));
2593
2594 LLVMValueRef value = lds_load(bld_base, TGSI_TYPE_SIGNED, ~0,
2595 lds_ptr);
2596
2597 build_tbuffer_store_dwords(ctx, buffer, value, 4, buffer_addr,
2598 buffer_offset, 0);
2599 }
2600 }
2601
2602 static void si_write_tess_factors(struct lp_build_tgsi_context *bld_base,
2603 LLVMValueRef rel_patch_id,
2604 LLVMValueRef invocation_id,
2605 LLVMValueRef tcs_out_current_patch_data_offset)
2606 {
2607 struct si_shader_context *ctx = si_shader_context(bld_base);
2608 struct gallivm_state *gallivm = bld_base->base.gallivm;
2609 struct si_shader *shader = ctx->shader;
2610 unsigned tess_inner_index, tess_outer_index;
2611 LLVMValueRef lds_base, lds_inner, lds_outer, byteoffset, buffer;
2612 LLVMValueRef out[6], vec0, vec1, rw_buffers, tf_base;
2613 unsigned stride, outer_comps, inner_comps, i;
2614 struct lp_build_if_state if_ctx, inner_if_ctx;
2615
2616 si_llvm_emit_barrier(NULL, bld_base, NULL);
2617
2618 /* Do this only for invocation 0, because the tess levels are per-patch,
2619 * not per-vertex.
2620 *
2621 * This can't jump, because invocation 0 executes this. It should
2622 * at least mask out the loads and stores for other invocations.
2623 */
2624 lp_build_if(&if_ctx, gallivm,
2625 LLVMBuildICmp(gallivm->builder, LLVMIntEQ,
2626 invocation_id, bld_base->uint_bld.zero, ""));
2627
2628 /* Determine the layout of one tess factor element in the buffer. */
2629 switch (shader->key.tcs.epilog.prim_mode) {
2630 case PIPE_PRIM_LINES:
2631 stride = 2; /* 2 dwords, 1 vec2 store */
2632 outer_comps = 2;
2633 inner_comps = 0;
2634 break;
2635 case PIPE_PRIM_TRIANGLES:
2636 stride = 4; /* 4 dwords, 1 vec4 store */
2637 outer_comps = 3;
2638 inner_comps = 1;
2639 break;
2640 case PIPE_PRIM_QUADS:
2641 stride = 6; /* 6 dwords, 2 stores (vec4 + vec2) */
2642 outer_comps = 4;
2643 inner_comps = 2;
2644 break;
2645 default:
2646 assert(0);
2647 return;
2648 }
2649
2650 /* Load tess_inner and tess_outer from LDS.
2651 * Any invocation can write them, so we can't get them from a temporary.
2652 */
2653 tess_inner_index = si_shader_io_get_unique_index(TGSI_SEMANTIC_TESSINNER, 0);
2654 tess_outer_index = si_shader_io_get_unique_index(TGSI_SEMANTIC_TESSOUTER, 0);
2655
2656 lds_base = tcs_out_current_patch_data_offset;
2657 lds_inner = LLVMBuildAdd(gallivm->builder, lds_base,
2658 lp_build_const_int32(gallivm,
2659 tess_inner_index * 4), "");
2660 lds_outer = LLVMBuildAdd(gallivm->builder, lds_base,
2661 lp_build_const_int32(gallivm,
2662 tess_outer_index * 4), "");
2663
2664 for (i = 0; i < outer_comps; i++)
2665 out[i] = lds_load(bld_base, TGSI_TYPE_SIGNED, i, lds_outer);
2666 for (i = 0; i < inner_comps; i++)
2667 out[outer_comps+i] = lds_load(bld_base, TGSI_TYPE_SIGNED, i, lds_inner);
2668
2669 /* Convert the outputs to vectors for stores. */
2670 vec0 = lp_build_gather_values(gallivm, out, MIN2(stride, 4));
2671 vec1 = NULL;
2672
2673 if (stride > 4)
2674 vec1 = lp_build_gather_values(gallivm, out+4, stride - 4);
2675
2676 /* Get the buffer. */
2677 rw_buffers = LLVMGetParam(ctx->radeon_bld.main_fn,
2678 SI_PARAM_RW_BUFFERS);
2679 buffer = build_indexed_load_const(ctx, rw_buffers,
2680 lp_build_const_int32(gallivm, SI_HS_RING_TESS_FACTOR));
2681
2682 /* Get the offset. */
2683 tf_base = LLVMGetParam(ctx->radeon_bld.main_fn,
2684 SI_PARAM_TESS_FACTOR_OFFSET);
2685 byteoffset = LLVMBuildMul(gallivm->builder, rel_patch_id,
2686 lp_build_const_int32(gallivm, 4 * stride), "");
2687
2688 lp_build_if(&inner_if_ctx, gallivm,
2689 LLVMBuildICmp(gallivm->builder, LLVMIntEQ,
2690 rel_patch_id, bld_base->uint_bld.zero, ""));
2691
2692 /* Store the dynamic HS control word. */
2693 build_tbuffer_store_dwords(ctx, buffer,
2694 lp_build_const_int32(gallivm, 0x80000000),
2695 1, lp_build_const_int32(gallivm, 0), tf_base, 0);
2696
2697 lp_build_endif(&inner_if_ctx);
2698
2699 /* Store the tessellation factors. */
2700 build_tbuffer_store_dwords(ctx, buffer, vec0,
2701 MIN2(stride, 4), byteoffset, tf_base, 4);
2702 if (vec1)
2703 build_tbuffer_store_dwords(ctx, buffer, vec1,
2704 stride - 4, byteoffset, tf_base, 20);
2705 lp_build_endif(&if_ctx);
2706 }
2707
2708 /* This only writes the tessellation factor levels. */
2709 static void si_llvm_emit_tcs_epilogue(struct lp_build_tgsi_context *bld_base)
2710 {
2711 struct si_shader_context *ctx = si_shader_context(bld_base);
2712 LLVMValueRef rel_patch_id, invocation_id, tf_lds_offset;
2713
2714 rel_patch_id = get_rel_patch_id(ctx);
2715 invocation_id = unpack_param(ctx, SI_PARAM_REL_IDS, 8, 5);
2716 tf_lds_offset = get_tcs_out_current_patch_data_offset(ctx);
2717
2718 if (!ctx->is_monolithic) {
2719 /* Return epilog parameters from this function. */
2720 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
2721 LLVMValueRef ret = ctx->return_value;
2722 LLVMValueRef rw_buffers, rw0, rw1, tf_soffset;
2723 unsigned vgpr;
2724
2725 /* RW_BUFFERS pointer */
2726 rw_buffers = LLVMGetParam(ctx->radeon_bld.main_fn,
2727 SI_PARAM_RW_BUFFERS);
2728 rw_buffers = LLVMBuildPtrToInt(builder, rw_buffers, ctx->i64, "");
2729 rw_buffers = LLVMBuildBitCast(builder, rw_buffers, ctx->v2i32, "");
2730 rw0 = LLVMBuildExtractElement(builder, rw_buffers,
2731 bld_base->uint_bld.zero, "");
2732 rw1 = LLVMBuildExtractElement(builder, rw_buffers,
2733 bld_base->uint_bld.one, "");
2734 ret = LLVMBuildInsertValue(builder, ret, rw0, 0, "");
2735 ret = LLVMBuildInsertValue(builder, ret, rw1, 1, "");
2736
2737 /* Tess factor buffer soffset is after user SGPRs. */
2738 tf_soffset = LLVMGetParam(ctx->radeon_bld.main_fn,
2739 SI_PARAM_TESS_FACTOR_OFFSET);
2740 ret = LLVMBuildInsertValue(builder, ret, tf_soffset,
2741 SI_TCS_NUM_USER_SGPR + 1, "");
2742
2743 /* VGPRs */
2744 rel_patch_id = bitcast(bld_base, TGSI_TYPE_FLOAT, rel_patch_id);
2745 invocation_id = bitcast(bld_base, TGSI_TYPE_FLOAT, invocation_id);
2746 tf_lds_offset = bitcast(bld_base, TGSI_TYPE_FLOAT, tf_lds_offset);
2747
2748 vgpr = SI_TCS_NUM_USER_SGPR + 2;
2749 ret = LLVMBuildInsertValue(builder, ret, rel_patch_id, vgpr++, "");
2750 ret = LLVMBuildInsertValue(builder, ret, invocation_id, vgpr++, "");
2751 ret = LLVMBuildInsertValue(builder, ret, tf_lds_offset, vgpr++, "");
2752 ctx->return_value = ret;
2753 return;
2754 }
2755
2756 si_copy_tcs_inputs(bld_base);
2757 si_write_tess_factors(bld_base, rel_patch_id, invocation_id, tf_lds_offset);
2758 }
2759
2760 static void si_llvm_emit_ls_epilogue(struct lp_build_tgsi_context *bld_base)
2761 {
2762 struct si_shader_context *ctx = si_shader_context(bld_base);
2763 struct si_shader *shader = ctx->shader;
2764 struct tgsi_shader_info *info = &shader->selector->info;
2765 struct gallivm_state *gallivm = bld_base->base.gallivm;
2766 unsigned i, chan;
2767 LLVMValueRef vertex_id = LLVMGetParam(ctx->radeon_bld.main_fn,
2768 ctx->param_rel_auto_id);
2769 LLVMValueRef vertex_dw_stride =
2770 unpack_param(ctx, SI_PARAM_LS_OUT_LAYOUT, 13, 8);
2771 LLVMValueRef base_dw_addr = LLVMBuildMul(gallivm->builder, vertex_id,
2772 vertex_dw_stride, "");
2773
2774 /* Write outputs to LDS. The next shader (TCS aka HS) will read
2775 * its inputs from it. */
2776 for (i = 0; i < info->num_outputs; i++) {
2777 LLVMValueRef *out_ptr = ctx->radeon_bld.soa.outputs[i];
2778 unsigned name = info->output_semantic_name[i];
2779 unsigned index = info->output_semantic_index[i];
2780 int param = si_shader_io_get_unique_index(name, index);
2781 LLVMValueRef dw_addr = LLVMBuildAdd(gallivm->builder, base_dw_addr,
2782 lp_build_const_int32(gallivm, param * 4), "");
2783
2784 for (chan = 0; chan < 4; chan++) {
2785 lds_store(bld_base, chan, dw_addr,
2786 LLVMBuildLoad(gallivm->builder, out_ptr[chan], ""));
2787 }
2788 }
2789 }
2790
2791 static void si_llvm_emit_es_epilogue(struct lp_build_tgsi_context *bld_base)
2792 {
2793 struct si_shader_context *ctx = si_shader_context(bld_base);
2794 struct gallivm_state *gallivm = bld_base->base.gallivm;
2795 struct si_shader *es = ctx->shader;
2796 struct tgsi_shader_info *info = &es->selector->info;
2797 LLVMValueRef soffset = LLVMGetParam(ctx->radeon_bld.main_fn,
2798 ctx->param_es2gs_offset);
2799 unsigned chan;
2800 int i;
2801
2802 for (i = 0; i < info->num_outputs; i++) {
2803 LLVMValueRef *out_ptr =
2804 ctx->radeon_bld.soa.outputs[i];
2805 int param_index;
2806
2807 if (info->output_semantic_name[i] == TGSI_SEMANTIC_VIEWPORT_INDEX ||
2808 info->output_semantic_name[i] == TGSI_SEMANTIC_LAYER)
2809 continue;
2810
2811 param_index = si_shader_io_get_unique_index(info->output_semantic_name[i],
2812 info->output_semantic_index[i]);
2813
2814 for (chan = 0; chan < 4; chan++) {
2815 LLVMValueRef out_val = LLVMBuildLoad(gallivm->builder, out_ptr[chan], "");
2816 out_val = LLVMBuildBitCast(gallivm->builder, out_val, ctx->i32, "");
2817
2818 build_tbuffer_store(ctx,
2819 ctx->esgs_ring,
2820 out_val, 1,
2821 LLVMGetUndef(ctx->i32), soffset,
2822 (4 * param_index + chan) * 4,
2823 V_008F0C_BUF_DATA_FORMAT_32,
2824 V_008F0C_BUF_NUM_FORMAT_UINT,
2825 0, 0, 1, 1, 0);
2826 }
2827 }
2828 }
2829
2830 static void si_llvm_emit_gs_epilogue(struct lp_build_tgsi_context *bld_base)
2831 {
2832 struct si_shader_context *ctx = si_shader_context(bld_base);
2833 struct gallivm_state *gallivm = bld_base->base.gallivm;
2834 LLVMValueRef args[2];
2835
2836 args[0] = lp_build_const_int32(gallivm, SENDMSG_GS_OP_NOP | SENDMSG_GS_DONE);
2837 args[1] = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_GS_WAVE_ID);
2838 lp_build_intrinsic(gallivm->builder, "llvm.SI.sendmsg",
2839 ctx->voidt, args, 2, 0);
2840 }
2841
2842 static void si_llvm_emit_vs_epilogue(struct lp_build_tgsi_context *bld_base)
2843 {
2844 struct si_shader_context *ctx = si_shader_context(bld_base);
2845 struct gallivm_state *gallivm = bld_base->base.gallivm;
2846 struct tgsi_shader_info *info = &ctx->shader->selector->info;
2847 struct si_shader_output_values *outputs = NULL;
2848 int i,j;
2849
2850 assert(!ctx->is_gs_copy_shader);
2851
2852 outputs = MALLOC((info->num_outputs + 1) * sizeof(outputs[0]));
2853
2854 /* Vertex color clamping.
2855 *
2856 * This uses a state constant loaded in a user data SGPR and
2857 * an IF statement is added that clamps all colors if the constant
2858 * is true.
2859 */
2860 if (ctx->type == PIPE_SHADER_VERTEX) {
2861 struct lp_build_if_state if_ctx;
2862 LLVMValueRef cond = NULL;
2863 LLVMValueRef addr, val;
2864
2865 for (i = 0; i < info->num_outputs; i++) {
2866 if (info->output_semantic_name[i] != TGSI_SEMANTIC_COLOR &&
2867 info->output_semantic_name[i] != TGSI_SEMANTIC_BCOLOR)
2868 continue;
2869
2870 /* We've found a color. */
2871 if (!cond) {
2872 /* The state is in the first bit of the user SGPR. */
2873 cond = LLVMGetParam(ctx->radeon_bld.main_fn,
2874 SI_PARAM_VS_STATE_BITS);
2875 cond = LLVMBuildTrunc(gallivm->builder, cond,
2876 ctx->i1, "");
2877 lp_build_if(&if_ctx, gallivm, cond);
2878 }
2879
2880 for (j = 0; j < 4; j++) {
2881 addr = ctx->radeon_bld.soa.outputs[i][j];
2882 val = LLVMBuildLoad(gallivm->builder, addr, "");
2883 val = radeon_llvm_saturate(bld_base, val);
2884 LLVMBuildStore(gallivm->builder, val, addr);
2885 }
2886 }
2887
2888 if (cond)
2889 lp_build_endif(&if_ctx);
2890 }
2891
2892 for (i = 0; i < info->num_outputs; i++) {
2893 outputs[i].name = info->output_semantic_name[i];
2894 outputs[i].sid = info->output_semantic_index[i];
2895
2896 for (j = 0; j < 4; j++)
2897 outputs[i].values[j] =
2898 LLVMBuildLoad(gallivm->builder,
2899 ctx->radeon_bld.soa.outputs[i][j],
2900 "");
2901 }
2902
2903 if (ctx->is_monolithic) {
2904 /* Export PrimitiveID when PS needs it. */
2905 if (si_vs_exports_prim_id(ctx->shader)) {
2906 outputs[i].name = TGSI_SEMANTIC_PRIMID;
2907 outputs[i].sid = 0;
2908 outputs[i].values[0] = bitcast(bld_base, TGSI_TYPE_FLOAT,
2909 get_primitive_id(bld_base, 0));
2910 outputs[i].values[1] = bld_base->base.undef;
2911 outputs[i].values[2] = bld_base->base.undef;
2912 outputs[i].values[3] = bld_base->base.undef;
2913 i++;
2914 }
2915 } else {
2916 /* Return the primitive ID from the LLVM function. */
2917 ctx->return_value =
2918 LLVMBuildInsertValue(gallivm->builder,
2919 ctx->return_value,
2920 bitcast(bld_base, TGSI_TYPE_FLOAT,
2921 get_primitive_id(bld_base, 0)),
2922 VS_EPILOG_PRIMID_LOC, "");
2923 }
2924
2925 si_llvm_export_vs(bld_base, outputs, i);
2926 FREE(outputs);
2927 }
2928
2929 struct si_ps_exports {
2930 unsigned num;
2931 LLVMValueRef args[10][9];
2932 };
2933
2934 unsigned si_get_spi_shader_z_format(bool writes_z, bool writes_stencil,
2935 bool writes_samplemask)
2936 {
2937 if (writes_z) {
2938 /* Z needs 32 bits. */
2939 if (writes_samplemask)
2940 return V_028710_SPI_SHADER_32_ABGR;
2941 else if (writes_stencil)
2942 return V_028710_SPI_SHADER_32_GR;
2943 else
2944 return V_028710_SPI_SHADER_32_R;
2945 } else if (writes_stencil || writes_samplemask) {
2946 /* Both stencil and sample mask need only 16 bits. */
2947 return V_028710_SPI_SHADER_UINT16_ABGR;
2948 } else {
2949 return V_028710_SPI_SHADER_ZERO;
2950 }
2951 }
2952
2953 static void si_export_mrt_z(struct lp_build_tgsi_context *bld_base,
2954 LLVMValueRef depth, LLVMValueRef stencil,
2955 LLVMValueRef samplemask, struct si_ps_exports *exp)
2956 {
2957 struct si_shader_context *ctx = si_shader_context(bld_base);
2958 struct lp_build_context *base = &bld_base->base;
2959 struct lp_build_context *uint = &bld_base->uint_bld;
2960 LLVMValueRef args[9];
2961 unsigned mask = 0;
2962 unsigned format = si_get_spi_shader_z_format(depth != NULL,
2963 stencil != NULL,
2964 samplemask != NULL);
2965
2966 assert(depth || stencil || samplemask);
2967
2968 args[1] = uint->one; /* whether the EXEC mask is valid */
2969 args[2] = uint->one; /* DONE bit */
2970
2971 /* Specify the target we are exporting */
2972 args[3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_MRTZ);
2973
2974 args[4] = uint->zero; /* COMP flag */
2975 args[5] = base->undef; /* R, depth */
2976 args[6] = base->undef; /* G, stencil test value[0:7], stencil op value[8:15] */
2977 args[7] = base->undef; /* B, sample mask */
2978 args[8] = base->undef; /* A, alpha to mask */
2979
2980 if (format == V_028710_SPI_SHADER_UINT16_ABGR) {
2981 assert(!depth);
2982 args[4] = uint->one; /* COMPR flag */
2983
2984 if (stencil) {
2985 /* Stencil should be in X[23:16]. */
2986 stencil = bitcast(bld_base, TGSI_TYPE_UNSIGNED, stencil);
2987 stencil = LLVMBuildShl(base->gallivm->builder, stencil,
2988 LLVMConstInt(ctx->i32, 16, 0), "");
2989 args[5] = bitcast(bld_base, TGSI_TYPE_FLOAT, stencil);
2990 mask |= 0x3;
2991 }
2992 if (samplemask) {
2993 /* SampleMask should be in Y[15:0]. */
2994 args[6] = samplemask;
2995 mask |= 0xc;
2996 }
2997 } else {
2998 if (depth) {
2999 args[5] = depth;
3000 mask |= 0x1;
3001 }
3002 if (stencil) {
3003 args[6] = stencil;
3004 mask |= 0x2;
3005 }
3006 if (samplemask) {
3007 args[7] = samplemask;
3008 mask |= 0x4;
3009 }
3010 }
3011
3012 /* SI (except OLAND) has a bug that it only looks
3013 * at the X writemask component. */
3014 if (ctx->screen->b.chip_class == SI &&
3015 ctx->screen->b.family != CHIP_OLAND)
3016 mask |= 0x1;
3017
3018 /* Specify which components to enable */
3019 args[0] = lp_build_const_int32(base->gallivm, mask);
3020
3021 memcpy(exp->args[exp->num++], args, sizeof(args));
3022 }
3023
3024 static void si_export_mrt_color(struct lp_build_tgsi_context *bld_base,
3025 LLVMValueRef *color, unsigned index,
3026 unsigned samplemask_param,
3027 bool is_last, struct si_ps_exports *exp)
3028 {
3029 struct si_shader_context *ctx = si_shader_context(bld_base);
3030 struct lp_build_context *base = &bld_base->base;
3031 int i;
3032
3033 /* Clamp color */
3034 if (ctx->shader->key.ps.epilog.clamp_color)
3035 for (i = 0; i < 4; i++)
3036 color[i] = radeon_llvm_saturate(bld_base, color[i]);
3037
3038 /* Alpha to one */
3039 if (ctx->shader->key.ps.epilog.alpha_to_one)
3040 color[3] = base->one;
3041
3042 /* Alpha test */
3043 if (index == 0 &&
3044 ctx->shader->key.ps.epilog.alpha_func != PIPE_FUNC_ALWAYS)
3045 si_alpha_test(bld_base, color[3]);
3046
3047 /* Line & polygon smoothing */
3048 if (ctx->shader->key.ps.epilog.poly_line_smoothing)
3049 color[3] = si_scale_alpha_by_sample_mask(bld_base, color[3],
3050 samplemask_param);
3051
3052 /* If last_cbuf > 0, FS_COLOR0_WRITES_ALL_CBUFS is true. */
3053 if (ctx->shader->key.ps.epilog.last_cbuf > 0) {
3054 LLVMValueRef args[8][9];
3055 int c, last = -1;
3056
3057 /* Get the export arguments, also find out what the last one is. */
3058 for (c = 0; c <= ctx->shader->key.ps.epilog.last_cbuf; c++) {
3059 si_llvm_init_export_args(bld_base, color,
3060 V_008DFC_SQ_EXP_MRT + c, args[c]);
3061 if (args[c][0] != bld_base->uint_bld.zero)
3062 last = c;
3063 }
3064
3065 /* Emit all exports. */
3066 for (c = 0; c <= ctx->shader->key.ps.epilog.last_cbuf; c++) {
3067 if (is_last && last == c) {
3068 args[c][1] = bld_base->uint_bld.one; /* whether the EXEC mask is valid */
3069 args[c][2] = bld_base->uint_bld.one; /* DONE bit */
3070 } else if (args[c][0] == bld_base->uint_bld.zero)
3071 continue; /* unnecessary NULL export */
3072
3073 memcpy(exp->args[exp->num++], args[c], sizeof(args[c]));
3074 }
3075 } else {
3076 LLVMValueRef args[9];
3077
3078 /* Export */
3079 si_llvm_init_export_args(bld_base, color, V_008DFC_SQ_EXP_MRT + index,
3080 args);
3081 if (is_last) {
3082 args[1] = bld_base->uint_bld.one; /* whether the EXEC mask is valid */
3083 args[2] = bld_base->uint_bld.one; /* DONE bit */
3084 } else if (args[0] == bld_base->uint_bld.zero)
3085 return; /* unnecessary NULL export */
3086
3087 memcpy(exp->args[exp->num++], args, sizeof(args));
3088 }
3089 }
3090
3091 static void si_emit_ps_exports(struct si_shader_context *ctx,
3092 struct si_ps_exports *exp)
3093 {
3094 for (unsigned i = 0; i < exp->num; i++)
3095 lp_build_intrinsic(ctx->radeon_bld.gallivm.builder,
3096 "llvm.SI.export", ctx->voidt,
3097 exp->args[i], 9, 0);
3098 }
3099
3100 static void si_export_null(struct lp_build_tgsi_context *bld_base)
3101 {
3102 struct si_shader_context *ctx = si_shader_context(bld_base);
3103 struct lp_build_context *base = &bld_base->base;
3104 struct lp_build_context *uint = &bld_base->uint_bld;
3105 LLVMValueRef args[9];
3106
3107 args[0] = lp_build_const_int32(base->gallivm, 0x0); /* enabled channels */
3108 args[1] = uint->one; /* whether the EXEC mask is valid */
3109 args[2] = uint->one; /* DONE bit */
3110 args[3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_NULL);
3111 args[4] = uint->zero; /* COMPR flag (0 = 32-bit export) */
3112 args[5] = base->undef; /* R */
3113 args[6] = base->undef; /* G */
3114 args[7] = base->undef; /* B */
3115 args[8] = base->undef; /* A */
3116
3117 lp_build_intrinsic(base->gallivm->builder, "llvm.SI.export",
3118 ctx->voidt, args, 9, 0);
3119 }
3120
3121 static void si_llvm_emit_fs_epilogue(struct lp_build_tgsi_context *bld_base)
3122 {
3123 struct si_shader_context *ctx = si_shader_context(bld_base);
3124 struct si_shader *shader = ctx->shader;
3125 struct lp_build_context *base = &bld_base->base;
3126 struct tgsi_shader_info *info = &shader->selector->info;
3127 LLVMBuilderRef builder = base->gallivm->builder;
3128 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
3129 int last_color_export = -1;
3130 int i;
3131 struct si_ps_exports exp = {};
3132
3133 /* Determine the last export. If MRTZ is present, it's always last.
3134 * Otherwise, find the last color export.
3135 */
3136 if (!info->writes_z && !info->writes_stencil && !info->writes_samplemask) {
3137 unsigned spi_format = shader->key.ps.epilog.spi_shader_col_format;
3138
3139 /* Don't export NULL and return if alpha-test is enabled. */
3140 if (shader->key.ps.epilog.alpha_func != PIPE_FUNC_ALWAYS &&
3141 shader->key.ps.epilog.alpha_func != PIPE_FUNC_NEVER &&
3142 (spi_format & 0xf) == 0)
3143 spi_format |= V_028714_SPI_SHADER_32_AR;
3144
3145 for (i = 0; i < info->num_outputs; i++) {
3146 unsigned index = info->output_semantic_index[i];
3147
3148 if (info->output_semantic_name[i] != TGSI_SEMANTIC_COLOR)
3149 continue;
3150
3151 /* If last_cbuf > 0, FS_COLOR0_WRITES_ALL_CBUFS is true. */
3152 if (shader->key.ps.epilog.last_cbuf > 0) {
3153 /* Just set this if any of the colorbuffers are enabled. */
3154 if (spi_format &
3155 ((1llu << (4 * (shader->key.ps.epilog.last_cbuf + 1))) - 1))
3156 last_color_export = i;
3157 continue;
3158 }
3159
3160 if ((spi_format >> (index * 4)) & 0xf)
3161 last_color_export = i;
3162 }
3163
3164 /* If there are no outputs, export NULL. */
3165 if (last_color_export == -1) {
3166 si_export_null(bld_base);
3167 return;
3168 }
3169 }
3170
3171 for (i = 0; i < info->num_outputs; i++) {
3172 unsigned semantic_name = info->output_semantic_name[i];
3173 unsigned semantic_index = info->output_semantic_index[i];
3174 unsigned j;
3175 LLVMValueRef color[4] = {};
3176
3177 /* Select the correct target */
3178 switch (semantic_name) {
3179 case TGSI_SEMANTIC_POSITION:
3180 depth = LLVMBuildLoad(builder,
3181 ctx->radeon_bld.soa.outputs[i][2], "");
3182 break;
3183 case TGSI_SEMANTIC_STENCIL:
3184 stencil = LLVMBuildLoad(builder,
3185 ctx->radeon_bld.soa.outputs[i][1], "");
3186 break;
3187 case TGSI_SEMANTIC_SAMPLEMASK:
3188 samplemask = LLVMBuildLoad(builder,
3189 ctx->radeon_bld.soa.outputs[i][0], "");
3190 break;
3191 case TGSI_SEMANTIC_COLOR:
3192 for (j = 0; j < 4; j++)
3193 color[j] = LLVMBuildLoad(builder,
3194 ctx->radeon_bld.soa.outputs[i][j], "");
3195
3196 si_export_mrt_color(bld_base, color, semantic_index,
3197 SI_PARAM_SAMPLE_COVERAGE,
3198 last_color_export == i, &exp);
3199 break;
3200 default:
3201 fprintf(stderr,
3202 "Warning: SI unhandled fs output type:%d\n",
3203 semantic_name);
3204 }
3205 }
3206
3207 if (depth || stencil || samplemask)
3208 si_export_mrt_z(bld_base, depth, stencil, samplemask, &exp);
3209
3210 si_emit_ps_exports(ctx, &exp);
3211 }
3212
3213 /**
3214 * Return PS outputs in this order:
3215 *
3216 * v[0:3] = color0.xyzw
3217 * v[4:7] = color1.xyzw
3218 * ...
3219 * vN+0 = Depth
3220 * vN+1 = Stencil
3221 * vN+2 = SampleMask
3222 * vN+3 = SampleMaskIn (used for OpenGL smoothing)
3223 *
3224 * The alpha-ref SGPR is returned via its original location.
3225 */
3226 static void si_llvm_return_fs_outputs(struct lp_build_tgsi_context *bld_base)
3227 {
3228 struct si_shader_context *ctx = si_shader_context(bld_base);
3229 struct si_shader *shader = ctx->shader;
3230 struct lp_build_context *base = &bld_base->base;
3231 struct tgsi_shader_info *info = &shader->selector->info;
3232 LLVMBuilderRef builder = base->gallivm->builder;
3233 unsigned i, j, first_vgpr, vgpr;
3234
3235 LLVMValueRef color[8][4] = {};
3236 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
3237 LLVMValueRef ret;
3238
3239 /* Read the output values. */
3240 for (i = 0; i < info->num_outputs; i++) {
3241 unsigned semantic_name = info->output_semantic_name[i];
3242 unsigned semantic_index = info->output_semantic_index[i];
3243
3244 switch (semantic_name) {
3245 case TGSI_SEMANTIC_COLOR:
3246 assert(semantic_index < 8);
3247 for (j = 0; j < 4; j++) {
3248 LLVMValueRef ptr = ctx->radeon_bld.soa.outputs[i][j];
3249 LLVMValueRef result = LLVMBuildLoad(builder, ptr, "");
3250 color[semantic_index][j] = result;
3251 }
3252 break;
3253 case TGSI_SEMANTIC_POSITION:
3254 depth = LLVMBuildLoad(builder,
3255 ctx->radeon_bld.soa.outputs[i][2], "");
3256 break;
3257 case TGSI_SEMANTIC_STENCIL:
3258 stencil = LLVMBuildLoad(builder,
3259 ctx->radeon_bld.soa.outputs[i][1], "");
3260 break;
3261 case TGSI_SEMANTIC_SAMPLEMASK:
3262 samplemask = LLVMBuildLoad(builder,
3263 ctx->radeon_bld.soa.outputs[i][0], "");
3264 break;
3265 default:
3266 fprintf(stderr, "Warning: SI unhandled fs output type:%d\n",
3267 semantic_name);
3268 }
3269 }
3270
3271 /* Fill the return structure. */
3272 ret = ctx->return_value;
3273
3274 /* Set SGPRs. */
3275 ret = LLVMBuildInsertValue(builder, ret,
3276 bitcast(bld_base, TGSI_TYPE_SIGNED,
3277 LLVMGetParam(ctx->radeon_bld.main_fn,
3278 SI_PARAM_ALPHA_REF)),
3279 SI_SGPR_ALPHA_REF, "");
3280
3281 /* Set VGPRs */
3282 first_vgpr = vgpr = SI_SGPR_ALPHA_REF + 1;
3283 for (i = 0; i < ARRAY_SIZE(color); i++) {
3284 if (!color[i][0])
3285 continue;
3286
3287 for (j = 0; j < 4; j++)
3288 ret = LLVMBuildInsertValue(builder, ret, color[i][j], vgpr++, "");
3289 }
3290 if (depth)
3291 ret = LLVMBuildInsertValue(builder, ret, depth, vgpr++, "");
3292 if (stencil)
3293 ret = LLVMBuildInsertValue(builder, ret, stencil, vgpr++, "");
3294 if (samplemask)
3295 ret = LLVMBuildInsertValue(builder, ret, samplemask, vgpr++, "");
3296
3297 /* Add the input sample mask for smoothing at the end. */
3298 if (vgpr < first_vgpr + PS_EPILOG_SAMPLEMASK_MIN_LOC)
3299 vgpr = first_vgpr + PS_EPILOG_SAMPLEMASK_MIN_LOC;
3300 ret = LLVMBuildInsertValue(builder, ret,
3301 LLVMGetParam(ctx->radeon_bld.main_fn,
3302 SI_PARAM_SAMPLE_COVERAGE), vgpr++, "");
3303
3304 ctx->return_value = ret;
3305 }
3306
3307 /**
3308 * Given a v8i32 resource descriptor for a buffer, extract the size of the
3309 * buffer in number of elements and return it as an i32.
3310 */
3311 static LLVMValueRef get_buffer_size(
3312 struct lp_build_tgsi_context *bld_base,
3313 LLVMValueRef descriptor)
3314 {
3315 struct si_shader_context *ctx = si_shader_context(bld_base);
3316 struct gallivm_state *gallivm = bld_base->base.gallivm;
3317 LLVMBuilderRef builder = gallivm->builder;
3318 LLVMValueRef size =
3319 LLVMBuildExtractElement(builder, descriptor,
3320 lp_build_const_int32(gallivm, 6), "");
3321
3322 if (ctx->screen->b.chip_class >= VI) {
3323 /* On VI, the descriptor contains the size in bytes,
3324 * but TXQ must return the size in elements.
3325 * The stride is always non-zero for resources using TXQ.
3326 */
3327 LLVMValueRef stride =
3328 LLVMBuildExtractElement(builder, descriptor,
3329 lp_build_const_int32(gallivm, 5), "");
3330 stride = LLVMBuildLShr(builder, stride,
3331 lp_build_const_int32(gallivm, 16), "");
3332 stride = LLVMBuildAnd(builder, stride,
3333 lp_build_const_int32(gallivm, 0x3FFF), "");
3334
3335 size = LLVMBuildUDiv(builder, size, stride, "");
3336 }
3337
3338 return size;
3339 }
3340
3341 /**
3342 * Given the i32 or vNi32 \p type, generate the textual name (e.g. for use with
3343 * intrinsic names).
3344 */
3345 static void build_int_type_name(
3346 LLVMTypeRef type,
3347 char *buf, unsigned bufsize)
3348 {
3349 assert(bufsize >= 6);
3350
3351 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
3352 snprintf(buf, bufsize, "v%ui32",
3353 LLVMGetVectorSize(type));
3354 else
3355 strcpy(buf, "i32");
3356 }
3357
3358 static void build_tex_intrinsic(const struct lp_build_tgsi_action *action,
3359 struct lp_build_tgsi_context *bld_base,
3360 struct lp_build_emit_data *emit_data);
3361
3362 /* Prevent optimizations (at least of memory accesses) across the current
3363 * point in the program by emitting empty inline assembly that is marked as
3364 * having side effects.
3365 */
3366 static void emit_optimization_barrier(struct si_shader_context *ctx)
3367 {
3368 LLVMBuilderRef builder = ctx->radeon_bld.gallivm.builder;
3369 LLVMTypeRef ftype = LLVMFunctionType(ctx->voidt, NULL, 0, false);
3370 LLVMValueRef inlineasm = LLVMConstInlineAsm(ftype, "", "", true, false);
3371 LLVMBuildCall(builder, inlineasm, NULL, 0, "");
3372 }
3373
3374 static void emit_waitcnt(struct si_shader_context *ctx)
3375 {
3376 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
3377 LLVMBuilderRef builder = gallivm->builder;
3378 LLVMValueRef args[1] = {
3379 lp_build_const_int32(gallivm, 0xf70)
3380 };
3381 lp_build_intrinsic(builder, "llvm.amdgcn.s.waitcnt",
3382 ctx->voidt, args, 1, 0);
3383 }
3384
3385 static void membar_emit(
3386 const struct lp_build_tgsi_action *action,
3387 struct lp_build_tgsi_context *bld_base,
3388 struct lp_build_emit_data *emit_data)
3389 {
3390 struct si_shader_context *ctx = si_shader_context(bld_base);
3391
3392 emit_waitcnt(ctx);
3393 }
3394
3395 static LLVMValueRef
3396 shader_buffer_fetch_rsrc(struct si_shader_context *ctx,
3397 const struct tgsi_full_src_register *reg)
3398 {
3399 LLVMValueRef index;
3400 LLVMValueRef rsrc_ptr = LLVMGetParam(ctx->radeon_bld.main_fn,
3401 SI_PARAM_SHADER_BUFFERS);
3402
3403 if (!reg->Register.Indirect)
3404 index = LLVMConstInt(ctx->i32, reg->Register.Index, 0);
3405 else
3406 index = get_bounded_indirect_index(ctx, &reg->Indirect,
3407 reg->Register.Index,
3408 SI_NUM_SHADER_BUFFERS);
3409
3410 return build_indexed_load_const(ctx, rsrc_ptr, index);
3411 }
3412
3413 static bool tgsi_is_array_sampler(unsigned target)
3414 {
3415 return target == TGSI_TEXTURE_1D_ARRAY ||
3416 target == TGSI_TEXTURE_SHADOW1D_ARRAY ||
3417 target == TGSI_TEXTURE_2D_ARRAY ||
3418 target == TGSI_TEXTURE_SHADOW2D_ARRAY ||
3419 target == TGSI_TEXTURE_CUBE_ARRAY ||
3420 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY ||
3421 target == TGSI_TEXTURE_2D_ARRAY_MSAA;
3422 }
3423
3424 static bool tgsi_is_array_image(unsigned target)
3425 {
3426 return target == TGSI_TEXTURE_3D ||
3427 target == TGSI_TEXTURE_CUBE ||
3428 target == TGSI_TEXTURE_1D_ARRAY ||
3429 target == TGSI_TEXTURE_2D_ARRAY ||
3430 target == TGSI_TEXTURE_CUBE_ARRAY ||
3431 target == TGSI_TEXTURE_2D_ARRAY_MSAA;
3432 }
3433
3434 /**
3435 * Given a 256-bit resource descriptor, force the DCC enable bit to off.
3436 *
3437 * At least on Tonga, executing image stores on images with DCC enabled and
3438 * non-trivial can eventually lead to lockups. This can occur when an
3439 * application binds an image as read-only but then uses a shader that writes
3440 * to it. The OpenGL spec allows almost arbitrarily bad behavior (including
3441 * program termination) in this case, but it doesn't cost much to be a bit
3442 * nicer: disabling DCC in the shader still leads to undefined results but
3443 * avoids the lockup.
3444 */
3445 static LLVMValueRef force_dcc_off(struct si_shader_context *ctx,
3446 LLVMValueRef rsrc)
3447 {
3448 if (ctx->screen->b.chip_class <= CIK) {
3449 return rsrc;
3450 } else {
3451 LLVMBuilderRef builder = ctx->radeon_bld.gallivm.builder;
3452 LLVMValueRef i32_6 = LLVMConstInt(ctx->i32, 6, 0);
3453 LLVMValueRef i32_C = LLVMConstInt(ctx->i32, C_008F28_COMPRESSION_EN, 0);
3454 LLVMValueRef tmp;
3455
3456 tmp = LLVMBuildExtractElement(builder, rsrc, i32_6, "");
3457 tmp = LLVMBuildAnd(builder, tmp, i32_C, "");
3458 return LLVMBuildInsertElement(builder, rsrc, tmp, i32_6, "");
3459 }
3460 }
3461
3462 /**
3463 * Load the resource descriptor for \p image.
3464 */
3465 static void
3466 image_fetch_rsrc(
3467 struct lp_build_tgsi_context *bld_base,
3468 const struct tgsi_full_src_register *image,
3469 bool dcc_off,
3470 LLVMValueRef *rsrc)
3471 {
3472 struct si_shader_context *ctx = si_shader_context(bld_base);
3473 LLVMValueRef rsrc_ptr = LLVMGetParam(ctx->radeon_bld.main_fn,
3474 SI_PARAM_IMAGES);
3475 LLVMValueRef index, tmp;
3476
3477 assert(image->Register.File == TGSI_FILE_IMAGE);
3478
3479 if (!image->Register.Indirect) {
3480 const struct tgsi_shader_info *info = bld_base->info;
3481
3482 index = LLVMConstInt(ctx->i32, image->Register.Index, 0);
3483
3484 if (info->images_writemask & (1 << image->Register.Index) &&
3485 !(info->images_buffers & (1 << image->Register.Index)))
3486 dcc_off = true;
3487 } else {
3488 /* From the GL_ARB_shader_image_load_store extension spec:
3489 *
3490 * If a shader performs an image load, store, or atomic
3491 * operation using an image variable declared as an array,
3492 * and if the index used to select an individual element is
3493 * negative or greater than or equal to the size of the
3494 * array, the results of the operation are undefined but may
3495 * not lead to termination.
3496 */
3497 index = get_bounded_indirect_index(ctx, &image->Indirect,
3498 image->Register.Index,
3499 SI_NUM_IMAGES);
3500 }
3501
3502 tmp = build_indexed_load_const(ctx, rsrc_ptr, index);
3503 if (dcc_off)
3504 tmp = force_dcc_off(ctx, tmp);
3505 *rsrc = tmp;
3506 }
3507
3508 static LLVMValueRef image_fetch_coords(
3509 struct lp_build_tgsi_context *bld_base,
3510 const struct tgsi_full_instruction *inst,
3511 unsigned src)
3512 {
3513 struct gallivm_state *gallivm = bld_base->base.gallivm;
3514 LLVMBuilderRef builder = gallivm->builder;
3515 unsigned target = inst->Memory.Texture;
3516 unsigned num_coords = tgsi_util_get_texture_coord_dim(target);
3517 LLVMValueRef coords[4];
3518 LLVMValueRef tmp;
3519 int chan;
3520
3521 for (chan = 0; chan < num_coords; ++chan) {
3522 tmp = lp_build_emit_fetch(bld_base, inst, src, chan);
3523 tmp = LLVMBuildBitCast(builder, tmp, bld_base->uint_bld.elem_type, "");
3524 coords[chan] = tmp;
3525 }
3526
3527 if (num_coords == 1)
3528 return coords[0];
3529
3530 if (num_coords == 3) {
3531 /* LLVM has difficulties lowering 3-element vectors. */
3532 coords[3] = bld_base->uint_bld.undef;
3533 num_coords = 4;
3534 }
3535
3536 return lp_build_gather_values(gallivm, coords, num_coords);
3537 }
3538
3539 /**
3540 * Append the extra mode bits that are used by image load and store.
3541 */
3542 static void image_append_args(
3543 struct si_shader_context *ctx,
3544 struct lp_build_emit_data * emit_data,
3545 unsigned target,
3546 bool atomic)
3547 {
3548 const struct tgsi_full_instruction *inst = emit_data->inst;
3549 LLVMValueRef i1false = LLVMConstInt(ctx->i1, 0, 0);
3550 LLVMValueRef i1true = LLVMConstInt(ctx->i1, 1, 0);
3551
3552 emit_data->args[emit_data->arg_count++] = i1false; /* r128 */
3553 emit_data->args[emit_data->arg_count++] =
3554 tgsi_is_array_image(target) ? i1true : i1false; /* da */
3555 if (!atomic) {
3556 emit_data->args[emit_data->arg_count++] =
3557 inst->Memory.Qualifier & (TGSI_MEMORY_COHERENT | TGSI_MEMORY_VOLATILE) ?
3558 i1true : i1false; /* glc */
3559 }
3560 emit_data->args[emit_data->arg_count++] = i1false; /* slc */
3561 }
3562
3563 /**
3564 * Given a 256 bit resource, extract the top half (which stores the buffer
3565 * resource in the case of textures and images).
3566 */
3567 static LLVMValueRef extract_rsrc_top_half(
3568 struct si_shader_context *ctx,
3569 LLVMValueRef rsrc)
3570 {
3571 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
3572 struct lp_build_tgsi_context *bld_base = &ctx->radeon_bld.soa.bld_base;
3573 LLVMTypeRef v2i128 = LLVMVectorType(ctx->i128, 2);
3574
3575 rsrc = LLVMBuildBitCast(gallivm->builder, rsrc, v2i128, "");
3576 rsrc = LLVMBuildExtractElement(gallivm->builder, rsrc, bld_base->uint_bld.one, "");
3577 rsrc = LLVMBuildBitCast(gallivm->builder, rsrc, ctx->v4i32, "");
3578
3579 return rsrc;
3580 }
3581
3582 /**
3583 * Append the resource and indexing arguments for buffer intrinsics.
3584 *
3585 * \param rsrc the v4i32 buffer resource
3586 * \param index index into the buffer (stride-based)
3587 * \param offset byte offset into the buffer
3588 */
3589 static void buffer_append_args(
3590 struct si_shader_context *ctx,
3591 struct lp_build_emit_data *emit_data,
3592 LLVMValueRef rsrc,
3593 LLVMValueRef index,
3594 LLVMValueRef offset,
3595 bool atomic)
3596 {
3597 const struct tgsi_full_instruction *inst = emit_data->inst;
3598 LLVMValueRef i1false = LLVMConstInt(ctx->i1, 0, 0);
3599 LLVMValueRef i1true = LLVMConstInt(ctx->i1, 1, 0);
3600
3601 emit_data->args[emit_data->arg_count++] = rsrc;
3602 emit_data->args[emit_data->arg_count++] = index; /* vindex */
3603 emit_data->args[emit_data->arg_count++] = offset; /* voffset */
3604 if (!atomic) {
3605 emit_data->args[emit_data->arg_count++] =
3606 inst->Memory.Qualifier & (TGSI_MEMORY_COHERENT | TGSI_MEMORY_VOLATILE) ?
3607 i1true : i1false; /* glc */
3608 }
3609 emit_data->args[emit_data->arg_count++] = i1false; /* slc */
3610 }
3611
3612 static void load_fetch_args(
3613 struct lp_build_tgsi_context * bld_base,
3614 struct lp_build_emit_data * emit_data)
3615 {
3616 struct si_shader_context *ctx = si_shader_context(bld_base);
3617 struct gallivm_state *gallivm = bld_base->base.gallivm;
3618 const struct tgsi_full_instruction * inst = emit_data->inst;
3619 unsigned target = inst->Memory.Texture;
3620 LLVMValueRef rsrc;
3621
3622 emit_data->dst_type = LLVMVectorType(bld_base->base.elem_type, 4);
3623
3624 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER) {
3625 LLVMBuilderRef builder = gallivm->builder;
3626 LLVMValueRef offset;
3627 LLVMValueRef tmp;
3628
3629 rsrc = shader_buffer_fetch_rsrc(ctx, &inst->Src[0]);
3630
3631 tmp = lp_build_emit_fetch(bld_base, inst, 1, 0);
3632 offset = LLVMBuildBitCast(builder, tmp, bld_base->uint_bld.elem_type, "");
3633
3634 buffer_append_args(ctx, emit_data, rsrc, bld_base->uint_bld.zero,
3635 offset, false);
3636 } else if (inst->Src[0].Register.File == TGSI_FILE_IMAGE) {
3637 LLVMValueRef coords;
3638
3639 image_fetch_rsrc(bld_base, &inst->Src[0], false, &rsrc);
3640 coords = image_fetch_coords(bld_base, inst, 1);
3641
3642 if (target == TGSI_TEXTURE_BUFFER) {
3643 rsrc = extract_rsrc_top_half(ctx, rsrc);
3644 buffer_append_args(ctx, emit_data, rsrc, coords,
3645 bld_base->uint_bld.zero, false);
3646 } else {
3647 emit_data->args[0] = coords;
3648 emit_data->args[1] = rsrc;
3649 emit_data->args[2] = lp_build_const_int32(gallivm, 15); /* dmask */
3650 emit_data->arg_count = 3;
3651
3652 image_append_args(ctx, emit_data, target, false);
3653 }
3654 }
3655 }
3656
3657 static void load_emit_buffer(struct si_shader_context *ctx,
3658 struct lp_build_emit_data *emit_data)
3659 {
3660 const struct tgsi_full_instruction *inst = emit_data->inst;
3661 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
3662 LLVMBuilderRef builder = gallivm->builder;
3663 uint writemask = inst->Dst[0].Register.WriteMask;
3664 uint count = util_last_bit(writemask);
3665 const char *intrinsic_name;
3666 LLVMTypeRef dst_type;
3667
3668 switch (count) {
3669 case 1:
3670 intrinsic_name = "llvm.amdgcn.buffer.load.f32";
3671 dst_type = ctx->f32;
3672 break;
3673 case 2:
3674 intrinsic_name = "llvm.amdgcn.buffer.load.v2f32";
3675 dst_type = LLVMVectorType(ctx->f32, 2);
3676 break;
3677 default: // 3 & 4
3678 intrinsic_name = "llvm.amdgcn.buffer.load.v4f32";
3679 dst_type = ctx->v4f32;
3680 count = 4;
3681 }
3682
3683 emit_data->output[emit_data->chan] = lp_build_intrinsic(
3684 builder, intrinsic_name, dst_type,
3685 emit_data->args, emit_data->arg_count,
3686 LLVMReadOnlyAttribute);
3687 }
3688
3689 static LLVMValueRef get_memory_ptr(struct si_shader_context *ctx,
3690 const struct tgsi_full_instruction *inst,
3691 LLVMTypeRef type, int arg)
3692 {
3693 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
3694 LLVMBuilderRef builder = gallivm->builder;
3695 LLVMValueRef offset, ptr;
3696 int addr_space;
3697
3698 offset = lp_build_emit_fetch(&ctx->radeon_bld.soa.bld_base, inst, arg, 0);
3699 offset = LLVMBuildBitCast(builder, offset, ctx->i32, "");
3700
3701 ptr = ctx->shared_memory;
3702 ptr = LLVMBuildGEP(builder, ptr, &offset, 1, "");
3703 addr_space = LLVMGetPointerAddressSpace(LLVMTypeOf(ptr));
3704 ptr = LLVMBuildBitCast(builder, ptr, LLVMPointerType(type, addr_space), "");
3705
3706 return ptr;
3707 }
3708
3709 static void load_emit_memory(
3710 struct si_shader_context *ctx,
3711 struct lp_build_emit_data *emit_data)
3712 {
3713 const struct tgsi_full_instruction *inst = emit_data->inst;
3714 struct lp_build_context *base = &ctx->radeon_bld.soa.bld_base.base;
3715 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
3716 LLVMBuilderRef builder = gallivm->builder;
3717 unsigned writemask = inst->Dst[0].Register.WriteMask;
3718 LLVMValueRef channels[4], ptr, derived_ptr, index;
3719 int chan;
3720
3721 ptr = get_memory_ptr(ctx, inst, base->elem_type, 1);
3722
3723 for (chan = 0; chan < 4; ++chan) {
3724 if (!(writemask & (1 << chan))) {
3725 channels[chan] = LLVMGetUndef(base->elem_type);
3726 continue;
3727 }
3728
3729 index = lp_build_const_int32(gallivm, chan);
3730 derived_ptr = LLVMBuildGEP(builder, ptr, &index, 1, "");
3731 channels[chan] = LLVMBuildLoad(builder, derived_ptr, "");
3732 }
3733 emit_data->output[emit_data->chan] = lp_build_gather_values(gallivm, channels, 4);
3734 }
3735
3736 static void load_emit(
3737 const struct lp_build_tgsi_action *action,
3738 struct lp_build_tgsi_context *bld_base,
3739 struct lp_build_emit_data *emit_data)
3740 {
3741 struct si_shader_context *ctx = si_shader_context(bld_base);
3742 struct gallivm_state *gallivm = bld_base->base.gallivm;
3743 LLVMBuilderRef builder = gallivm->builder;
3744 const struct tgsi_full_instruction * inst = emit_data->inst;
3745 char intrinsic_name[32];
3746 char coords_type[8];
3747
3748 if (inst->Src[0].Register.File == TGSI_FILE_MEMORY) {
3749 load_emit_memory(ctx, emit_data);
3750 return;
3751 }
3752
3753 if (inst->Memory.Qualifier & TGSI_MEMORY_VOLATILE)
3754 emit_waitcnt(ctx);
3755
3756 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER) {
3757 load_emit_buffer(ctx, emit_data);
3758 return;
3759 }
3760
3761 if (inst->Memory.Texture == TGSI_TEXTURE_BUFFER) {
3762 emit_data->output[emit_data->chan] =
3763 lp_build_intrinsic(
3764 builder, "llvm.amdgcn.buffer.load.format.v4f32", emit_data->dst_type,
3765 emit_data->args, emit_data->arg_count,
3766 LLVMReadOnlyAttribute);
3767 } else {
3768 build_int_type_name(LLVMTypeOf(emit_data->args[0]),
3769 coords_type, sizeof(coords_type));
3770
3771 snprintf(intrinsic_name, sizeof(intrinsic_name),
3772 "llvm.amdgcn.image.load.%s", coords_type);
3773
3774 emit_data->output[emit_data->chan] =
3775 lp_build_intrinsic(
3776 builder, intrinsic_name, emit_data->dst_type,
3777 emit_data->args, emit_data->arg_count,
3778 LLVMReadOnlyAttribute);
3779 }
3780 }
3781
3782 static void store_fetch_args(
3783 struct lp_build_tgsi_context * bld_base,
3784 struct lp_build_emit_data * emit_data)
3785 {
3786 struct si_shader_context *ctx = si_shader_context(bld_base);
3787 struct gallivm_state *gallivm = bld_base->base.gallivm;
3788 LLVMBuilderRef builder = gallivm->builder;
3789 const struct tgsi_full_instruction * inst = emit_data->inst;
3790 struct tgsi_full_src_register memory;
3791 LLVMValueRef chans[4];
3792 LLVMValueRef data;
3793 LLVMValueRef rsrc;
3794 unsigned chan;
3795
3796 emit_data->dst_type = LLVMVoidTypeInContext(gallivm->context);
3797
3798 for (chan = 0; chan < 4; ++chan) {
3799 chans[chan] = lp_build_emit_fetch(bld_base, inst, 1, chan);
3800 }
3801 data = lp_build_gather_values(gallivm, chans, 4);
3802
3803 emit_data->args[emit_data->arg_count++] = data;
3804
3805 memory = tgsi_full_src_register_from_dst(&inst->Dst[0]);
3806
3807 if (inst->Dst[0].Register.File == TGSI_FILE_BUFFER) {
3808 LLVMValueRef offset;
3809 LLVMValueRef tmp;
3810
3811 rsrc = shader_buffer_fetch_rsrc(ctx, &memory);
3812
3813 tmp = lp_build_emit_fetch(bld_base, inst, 0, 0);
3814 offset = LLVMBuildBitCast(builder, tmp, bld_base->uint_bld.elem_type, "");
3815
3816 buffer_append_args(ctx, emit_data, rsrc, bld_base->uint_bld.zero,
3817 offset, false);
3818 } else if (inst->Dst[0].Register.File == TGSI_FILE_IMAGE) {
3819 unsigned target = inst->Memory.Texture;
3820 LLVMValueRef coords;
3821
3822 coords = image_fetch_coords(bld_base, inst, 0);
3823
3824 if (target == TGSI_TEXTURE_BUFFER) {
3825 image_fetch_rsrc(bld_base, &memory, false, &rsrc);
3826
3827 rsrc = extract_rsrc_top_half(ctx, rsrc);
3828 buffer_append_args(ctx, emit_data, rsrc, coords,
3829 bld_base->uint_bld.zero, false);
3830 } else {
3831 emit_data->args[1] = coords;
3832 image_fetch_rsrc(bld_base, &memory, true, &emit_data->args[2]);
3833 emit_data->args[3] = lp_build_const_int32(gallivm, 15); /* dmask */
3834 emit_data->arg_count = 4;
3835
3836 image_append_args(ctx, emit_data, target, false);
3837 }
3838 }
3839 }
3840
3841 static void store_emit_buffer(
3842 struct si_shader_context *ctx,
3843 struct lp_build_emit_data *emit_data)
3844 {
3845 const struct tgsi_full_instruction *inst = emit_data->inst;
3846 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
3847 LLVMBuilderRef builder = gallivm->builder;
3848 struct lp_build_context *uint_bld = &ctx->radeon_bld.soa.bld_base.uint_bld;
3849 LLVMValueRef base_data = emit_data->args[0];
3850 LLVMValueRef base_offset = emit_data->args[3];
3851 unsigned writemask = inst->Dst[0].Register.WriteMask;
3852
3853 while (writemask) {
3854 int start, count;
3855 const char *intrinsic_name;
3856 LLVMValueRef data;
3857 LLVMValueRef offset;
3858 LLVMValueRef tmp;
3859
3860 u_bit_scan_consecutive_range(&writemask, &start, &count);
3861
3862 /* Due to an LLVM limitation, split 3-element writes
3863 * into a 2-element and a 1-element write. */
3864 if (count == 3) {
3865 writemask |= 1 << (start + 2);
3866 count = 2;
3867 }
3868
3869 if (count == 4) {
3870 data = base_data;
3871 intrinsic_name = "llvm.amdgcn.buffer.store.v4f32";
3872 } else if (count == 2) {
3873 LLVMTypeRef v2f32 = LLVMVectorType(ctx->f32, 2);
3874
3875 tmp = LLVMBuildExtractElement(
3876 builder, base_data,
3877 lp_build_const_int32(gallivm, start), "");
3878 data = LLVMBuildInsertElement(
3879 builder, LLVMGetUndef(v2f32), tmp,
3880 uint_bld->zero, "");
3881
3882 tmp = LLVMBuildExtractElement(
3883 builder, base_data,
3884 lp_build_const_int32(gallivm, start + 1), "");
3885 data = LLVMBuildInsertElement(
3886 builder, data, tmp, uint_bld->one, "");
3887
3888 intrinsic_name = "llvm.amdgcn.buffer.store.v2f32";
3889 } else {
3890 assert(count == 1);
3891 data = LLVMBuildExtractElement(
3892 builder, base_data,
3893 lp_build_const_int32(gallivm, start), "");
3894 intrinsic_name = "llvm.amdgcn.buffer.store.f32";
3895 }
3896
3897 offset = base_offset;
3898 if (start != 0) {
3899 offset = LLVMBuildAdd(
3900 builder, offset,
3901 lp_build_const_int32(gallivm, start * 4), "");
3902 }
3903
3904 emit_data->args[0] = data;
3905 emit_data->args[3] = offset;
3906
3907 lp_build_intrinsic(
3908 builder, intrinsic_name, emit_data->dst_type,
3909 emit_data->args, emit_data->arg_count, 0);
3910 }
3911 }
3912
3913 static void store_emit_memory(
3914 struct si_shader_context *ctx,
3915 struct lp_build_emit_data *emit_data)
3916 {
3917 const struct tgsi_full_instruction *inst = emit_data->inst;
3918 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
3919 struct lp_build_context *base = &ctx->radeon_bld.soa.bld_base.base;
3920 LLVMBuilderRef builder = gallivm->builder;
3921 unsigned writemask = inst->Dst[0].Register.WriteMask;
3922 LLVMValueRef ptr, derived_ptr, data, index;
3923 int chan;
3924
3925 ptr = get_memory_ptr(ctx, inst, base->elem_type, 0);
3926
3927 for (chan = 0; chan < 4; ++chan) {
3928 if (!(writemask & (1 << chan))) {
3929 continue;
3930 }
3931 data = lp_build_emit_fetch(&ctx->radeon_bld.soa.bld_base, inst, 1, chan);
3932 index = lp_build_const_int32(gallivm, chan);
3933 derived_ptr = LLVMBuildGEP(builder, ptr, &index, 1, "");
3934 LLVMBuildStore(builder, data, derived_ptr);
3935 }
3936 }
3937
3938 static void store_emit(
3939 const struct lp_build_tgsi_action *action,
3940 struct lp_build_tgsi_context *bld_base,
3941 struct lp_build_emit_data *emit_data)
3942 {
3943 struct si_shader_context *ctx = si_shader_context(bld_base);
3944 struct gallivm_state *gallivm = bld_base->base.gallivm;
3945 LLVMBuilderRef builder = gallivm->builder;
3946 const struct tgsi_full_instruction * inst = emit_data->inst;
3947 unsigned target = inst->Memory.Texture;
3948 char intrinsic_name[32];
3949 char coords_type[8];
3950
3951 if (inst->Dst[0].Register.File == TGSI_FILE_MEMORY) {
3952 store_emit_memory(ctx, emit_data);
3953 return;
3954 }
3955
3956 if (inst->Memory.Qualifier & TGSI_MEMORY_VOLATILE)
3957 emit_waitcnt(ctx);
3958
3959 if (inst->Dst[0].Register.File == TGSI_FILE_BUFFER) {
3960 store_emit_buffer(ctx, emit_data);
3961 return;
3962 }
3963
3964 if (target == TGSI_TEXTURE_BUFFER) {
3965 emit_data->output[emit_data->chan] = lp_build_intrinsic(
3966 builder, "llvm.amdgcn.buffer.store.format.v4f32",
3967 emit_data->dst_type, emit_data->args,
3968 emit_data->arg_count, 0);
3969 } else {
3970 build_int_type_name(LLVMTypeOf(emit_data->args[1]),
3971 coords_type, sizeof(coords_type));
3972 snprintf(intrinsic_name, sizeof(intrinsic_name),
3973 "llvm.amdgcn.image.store.%s", coords_type);
3974
3975 emit_data->output[emit_data->chan] =
3976 lp_build_intrinsic(
3977 builder, intrinsic_name, emit_data->dst_type,
3978 emit_data->args, emit_data->arg_count, 0);
3979 }
3980 }
3981
3982 static void atomic_fetch_args(
3983 struct lp_build_tgsi_context * bld_base,
3984 struct lp_build_emit_data * emit_data)
3985 {
3986 struct si_shader_context *ctx = si_shader_context(bld_base);
3987 struct gallivm_state *gallivm = bld_base->base.gallivm;
3988 LLVMBuilderRef builder = gallivm->builder;
3989 const struct tgsi_full_instruction * inst = emit_data->inst;
3990 LLVMValueRef data1, data2;
3991 LLVMValueRef rsrc;
3992 LLVMValueRef tmp;
3993
3994 emit_data->dst_type = bld_base->base.elem_type;
3995
3996 tmp = lp_build_emit_fetch(bld_base, inst, 2, 0);
3997 data1 = LLVMBuildBitCast(builder, tmp, bld_base->uint_bld.elem_type, "");
3998
3999 if (inst->Instruction.Opcode == TGSI_OPCODE_ATOMCAS) {
4000 tmp = lp_build_emit_fetch(bld_base, inst, 3, 0);
4001 data2 = LLVMBuildBitCast(builder, tmp, bld_base->uint_bld.elem_type, "");
4002 }
4003
4004 /* llvm.amdgcn.image/buffer.atomic.cmpswap reflect the hardware order
4005 * of arguments, which is reversed relative to TGSI (and GLSL)
4006 */
4007 if (inst->Instruction.Opcode == TGSI_OPCODE_ATOMCAS)
4008 emit_data->args[emit_data->arg_count++] = data2;
4009 emit_data->args[emit_data->arg_count++] = data1;
4010
4011 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER) {
4012 LLVMValueRef offset;
4013
4014 rsrc = shader_buffer_fetch_rsrc(ctx, &inst->Src[0]);
4015
4016 tmp = lp_build_emit_fetch(bld_base, inst, 1, 0);
4017 offset = LLVMBuildBitCast(builder, tmp, bld_base->uint_bld.elem_type, "");
4018
4019 buffer_append_args(ctx, emit_data, rsrc, bld_base->uint_bld.zero,
4020 offset, true);
4021 } else if (inst->Src[0].Register.File == TGSI_FILE_IMAGE) {
4022 unsigned target = inst->Memory.Texture;
4023 LLVMValueRef coords;
4024
4025 image_fetch_rsrc(bld_base, &inst->Src[0],
4026 target != TGSI_TEXTURE_BUFFER, &rsrc);
4027 coords = image_fetch_coords(bld_base, inst, 1);
4028
4029 if (target == TGSI_TEXTURE_BUFFER) {
4030 rsrc = extract_rsrc_top_half(ctx, rsrc);
4031 buffer_append_args(ctx, emit_data, rsrc, coords,
4032 bld_base->uint_bld.zero, true);
4033 } else {
4034 emit_data->args[emit_data->arg_count++] = coords;
4035 emit_data->args[emit_data->arg_count++] = rsrc;
4036
4037 image_append_args(ctx, emit_data, target, true);
4038 }
4039 }
4040 }
4041
4042 static void atomic_emit_memory(struct si_shader_context *ctx,
4043 struct lp_build_emit_data *emit_data) {
4044 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
4045 LLVMBuilderRef builder = gallivm->builder;
4046 const struct tgsi_full_instruction * inst = emit_data->inst;
4047 LLVMValueRef ptr, result, arg;
4048
4049 ptr = get_memory_ptr(ctx, inst, ctx->i32, 1);
4050
4051 arg = lp_build_emit_fetch(&ctx->radeon_bld.soa.bld_base, inst, 2, 0);
4052 arg = LLVMBuildBitCast(builder, arg, ctx->i32, "");
4053
4054 if (inst->Instruction.Opcode == TGSI_OPCODE_ATOMCAS) {
4055 LLVMValueRef new_data;
4056 new_data = lp_build_emit_fetch(&ctx->radeon_bld.soa.bld_base,
4057 inst, 3, 0);
4058
4059 new_data = LLVMBuildBitCast(builder, new_data, ctx->i32, "");
4060
4061 #if HAVE_LLVM >= 0x309
4062 result = LLVMBuildAtomicCmpXchg(builder, ptr, arg, new_data,
4063 LLVMAtomicOrderingSequentiallyConsistent,
4064 LLVMAtomicOrderingSequentiallyConsistent,
4065 false);
4066 #endif
4067
4068 result = LLVMBuildExtractValue(builder, result, 0, "");
4069 } else {
4070 LLVMAtomicRMWBinOp op;
4071
4072 switch(inst->Instruction.Opcode) {
4073 case TGSI_OPCODE_ATOMUADD:
4074 op = LLVMAtomicRMWBinOpAdd;
4075 break;
4076 case TGSI_OPCODE_ATOMXCHG:
4077 op = LLVMAtomicRMWBinOpXchg;
4078 break;
4079 case TGSI_OPCODE_ATOMAND:
4080 op = LLVMAtomicRMWBinOpAnd;
4081 break;
4082 case TGSI_OPCODE_ATOMOR:
4083 op = LLVMAtomicRMWBinOpOr;
4084 break;
4085 case TGSI_OPCODE_ATOMXOR:
4086 op = LLVMAtomicRMWBinOpXor;
4087 break;
4088 case TGSI_OPCODE_ATOMUMIN:
4089 op = LLVMAtomicRMWBinOpUMin;
4090 break;
4091 case TGSI_OPCODE_ATOMUMAX:
4092 op = LLVMAtomicRMWBinOpUMax;
4093 break;
4094 case TGSI_OPCODE_ATOMIMIN:
4095 op = LLVMAtomicRMWBinOpMin;
4096 break;
4097 case TGSI_OPCODE_ATOMIMAX:
4098 op = LLVMAtomicRMWBinOpMax;
4099 break;
4100 default:
4101 unreachable("unknown atomic opcode");
4102 }
4103
4104 result = LLVMBuildAtomicRMW(builder, op, ptr, arg,
4105 LLVMAtomicOrderingSequentiallyConsistent,
4106 false);
4107 }
4108 emit_data->output[emit_data->chan] = LLVMBuildBitCast(builder, result, emit_data->dst_type, "");
4109 }
4110
4111 static void atomic_emit(
4112 const struct lp_build_tgsi_action *action,
4113 struct lp_build_tgsi_context *bld_base,
4114 struct lp_build_emit_data *emit_data)
4115 {
4116 struct si_shader_context *ctx = si_shader_context(bld_base);
4117 struct gallivm_state *gallivm = bld_base->base.gallivm;
4118 LLVMBuilderRef builder = gallivm->builder;
4119 const struct tgsi_full_instruction * inst = emit_data->inst;
4120 char intrinsic_name[40];
4121 LLVMValueRef tmp;
4122
4123 if (inst->Src[0].Register.File == TGSI_FILE_MEMORY) {
4124 atomic_emit_memory(ctx, emit_data);
4125 return;
4126 }
4127
4128 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER ||
4129 inst->Memory.Texture == TGSI_TEXTURE_BUFFER) {
4130 snprintf(intrinsic_name, sizeof(intrinsic_name),
4131 "llvm.amdgcn.buffer.atomic.%s", action->intr_name);
4132 } else {
4133 char coords_type[8];
4134
4135 build_int_type_name(LLVMTypeOf(emit_data->args[1]),
4136 coords_type, sizeof(coords_type));
4137 snprintf(intrinsic_name, sizeof(intrinsic_name),
4138 "llvm.amdgcn.image.atomic.%s.%s",
4139 action->intr_name, coords_type);
4140 }
4141
4142 tmp = lp_build_intrinsic(
4143 builder, intrinsic_name, bld_base->uint_bld.elem_type,
4144 emit_data->args, emit_data->arg_count, 0);
4145 emit_data->output[emit_data->chan] =
4146 LLVMBuildBitCast(builder, tmp, bld_base->base.elem_type, "");
4147 }
4148
4149 static void resq_fetch_args(
4150 struct lp_build_tgsi_context * bld_base,
4151 struct lp_build_emit_data * emit_data)
4152 {
4153 struct si_shader_context *ctx = si_shader_context(bld_base);
4154 struct gallivm_state *gallivm = bld_base->base.gallivm;
4155 const struct tgsi_full_instruction *inst = emit_data->inst;
4156 const struct tgsi_full_src_register *reg = &inst->Src[0];
4157
4158 emit_data->dst_type = ctx->v4i32;
4159
4160 if (reg->Register.File == TGSI_FILE_BUFFER) {
4161 emit_data->args[0] = shader_buffer_fetch_rsrc(ctx, reg);
4162 emit_data->arg_count = 1;
4163 } else if (inst->Memory.Texture == TGSI_TEXTURE_BUFFER) {
4164 image_fetch_rsrc(bld_base, reg, false, &emit_data->args[0]);
4165 emit_data->arg_count = 1;
4166 } else {
4167 emit_data->args[0] = bld_base->uint_bld.zero; /* mip level */
4168 image_fetch_rsrc(bld_base, reg, false, &emit_data->args[1]);
4169 emit_data->args[2] = lp_build_const_int32(gallivm, 15); /* dmask */
4170 emit_data->args[3] = bld_base->uint_bld.zero; /* unorm */
4171 emit_data->args[4] = bld_base->uint_bld.zero; /* r128 */
4172 emit_data->args[5] = tgsi_is_array_image(inst->Memory.Texture) ?
4173 bld_base->uint_bld.one : bld_base->uint_bld.zero; /* da */
4174 emit_data->args[6] = bld_base->uint_bld.zero; /* glc */
4175 emit_data->args[7] = bld_base->uint_bld.zero; /* slc */
4176 emit_data->args[8] = bld_base->uint_bld.zero; /* tfe */
4177 emit_data->args[9] = bld_base->uint_bld.zero; /* lwe */
4178 emit_data->arg_count = 10;
4179 }
4180 }
4181
4182 static void resq_emit(
4183 const struct lp_build_tgsi_action *action,
4184 struct lp_build_tgsi_context *bld_base,
4185 struct lp_build_emit_data *emit_data)
4186 {
4187 struct gallivm_state *gallivm = bld_base->base.gallivm;
4188 LLVMBuilderRef builder = gallivm->builder;
4189 const struct tgsi_full_instruction *inst = emit_data->inst;
4190 LLVMValueRef out;
4191
4192 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER) {
4193 out = LLVMBuildExtractElement(builder, emit_data->args[0],
4194 lp_build_const_int32(gallivm, 2), "");
4195 } else if (inst->Memory.Texture == TGSI_TEXTURE_BUFFER) {
4196 out = get_buffer_size(bld_base, emit_data->args[0]);
4197 } else {
4198 out = lp_build_intrinsic(
4199 builder, "llvm.SI.getresinfo.i32", emit_data->dst_type,
4200 emit_data->args, emit_data->arg_count,
4201 LLVMReadNoneAttribute);
4202
4203 /* Divide the number of layers by 6 to get the number of cubes. */
4204 if (inst->Memory.Texture == TGSI_TEXTURE_CUBE_ARRAY) {
4205 LLVMValueRef imm2 = lp_build_const_int32(gallivm, 2);
4206 LLVMValueRef imm6 = lp_build_const_int32(gallivm, 6);
4207
4208 LLVMValueRef z = LLVMBuildExtractElement(builder, out, imm2, "");
4209 z = LLVMBuildSDiv(builder, z, imm6, "");
4210 out = LLVMBuildInsertElement(builder, out, z, imm2, "");
4211 }
4212 }
4213
4214 emit_data->output[emit_data->chan] = out;
4215 }
4216
4217 static void set_tex_fetch_args(struct si_shader_context *ctx,
4218 struct lp_build_emit_data *emit_data,
4219 unsigned opcode, unsigned target,
4220 LLVMValueRef res_ptr, LLVMValueRef samp_ptr,
4221 LLVMValueRef *param, unsigned count,
4222 unsigned dmask)
4223 {
4224 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
4225 unsigned num_args;
4226 unsigned is_rect = target == TGSI_TEXTURE_RECT;
4227
4228 /* Pad to power of two vector */
4229 while (count < util_next_power_of_two(count))
4230 param[count++] = LLVMGetUndef(ctx->i32);
4231
4232 /* Texture coordinates. */
4233 if (count > 1)
4234 emit_data->args[0] = lp_build_gather_values(gallivm, param, count);
4235 else
4236 emit_data->args[0] = param[0];
4237
4238 /* Resource. */
4239 emit_data->args[1] = res_ptr;
4240 num_args = 2;
4241
4242 if (opcode == TGSI_OPCODE_TXF || opcode == TGSI_OPCODE_TXQ)
4243 emit_data->dst_type = ctx->v4i32;
4244 else {
4245 emit_data->dst_type = ctx->v4f32;
4246
4247 emit_data->args[num_args++] = samp_ptr;
4248 }
4249
4250 emit_data->args[num_args++] = lp_build_const_int32(gallivm, dmask);
4251 emit_data->args[num_args++] = lp_build_const_int32(gallivm, is_rect); /* unorm */
4252 emit_data->args[num_args++] = lp_build_const_int32(gallivm, 0); /* r128 */
4253 emit_data->args[num_args++] = lp_build_const_int32(gallivm,
4254 tgsi_is_array_sampler(target)); /* da */
4255 emit_data->args[num_args++] = lp_build_const_int32(gallivm, 0); /* glc */
4256 emit_data->args[num_args++] = lp_build_const_int32(gallivm, 0); /* slc */
4257 emit_data->args[num_args++] = lp_build_const_int32(gallivm, 0); /* tfe */
4258 emit_data->args[num_args++] = lp_build_const_int32(gallivm, 0); /* lwe */
4259
4260 emit_data->arg_count = num_args;
4261 }
4262
4263 static const struct lp_build_tgsi_action tex_action;
4264
4265 enum desc_type {
4266 DESC_IMAGE,
4267 DESC_FMASK,
4268 DESC_SAMPLER
4269 };
4270
4271 static LLVMTypeRef const_array(LLVMTypeRef elem_type, int num_elements)
4272 {
4273 return LLVMPointerType(LLVMArrayType(elem_type, num_elements),
4274 CONST_ADDR_SPACE);
4275 }
4276
4277 /**
4278 * Load an image view, fmask view. or sampler state descriptor.
4279 */
4280 static LLVMValueRef load_sampler_desc_custom(struct si_shader_context *ctx,
4281 LLVMValueRef list, LLVMValueRef index,
4282 enum desc_type type)
4283 {
4284 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
4285 LLVMBuilderRef builder = gallivm->builder;
4286
4287 switch (type) {
4288 case DESC_IMAGE:
4289 /* The image is at [0:7]. */
4290 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->i32, 2, 0), "");
4291 break;
4292 case DESC_FMASK:
4293 /* The FMASK is at [8:15]. */
4294 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->i32, 2, 0), "");
4295 index = LLVMBuildAdd(builder, index, LLVMConstInt(ctx->i32, 1, 0), "");
4296 break;
4297 case DESC_SAMPLER:
4298 /* The sampler state is at [12:15]. */
4299 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->i32, 4, 0), "");
4300 index = LLVMBuildAdd(builder, index, LLVMConstInt(ctx->i32, 3, 0), "");
4301 list = LLVMBuildPointerCast(builder, list,
4302 const_array(ctx->v4i32, 0), "");
4303 break;
4304 }
4305
4306 return build_indexed_load_const(ctx, list, index);
4307 }
4308
4309 static LLVMValueRef load_sampler_desc(struct si_shader_context *ctx,
4310 LLVMValueRef index, enum desc_type type)
4311 {
4312 LLVMValueRef list = LLVMGetParam(ctx->radeon_bld.main_fn,
4313 SI_PARAM_SAMPLERS);
4314
4315 return load_sampler_desc_custom(ctx, list, index, type);
4316 }
4317
4318 /* Disable anisotropic filtering if BASE_LEVEL == LAST_LEVEL.
4319 *
4320 * SI-CI:
4321 * If BASE_LEVEL == LAST_LEVEL, the shader must disable anisotropic
4322 * filtering manually. The driver sets img7 to a mask clearing
4323 * MAX_ANISO_RATIO if BASE_LEVEL == LAST_LEVEL. The shader must do:
4324 * s_and_b32 samp0, samp0, img7
4325 *
4326 * VI:
4327 * The ANISO_OVERRIDE sampler field enables this fix in TA.
4328 */
4329 static LLVMValueRef sici_fix_sampler_aniso(struct si_shader_context *ctx,
4330 LLVMValueRef res, LLVMValueRef samp)
4331 {
4332 LLVMBuilderRef builder = ctx->radeon_bld.gallivm.builder;
4333 LLVMValueRef img7, samp0;
4334
4335 if (ctx->screen->b.chip_class >= VI)
4336 return samp;
4337
4338 img7 = LLVMBuildExtractElement(builder, res,
4339 LLVMConstInt(ctx->i32, 7, 0), "");
4340 samp0 = LLVMBuildExtractElement(builder, samp,
4341 LLVMConstInt(ctx->i32, 0, 0), "");
4342 samp0 = LLVMBuildAnd(builder, samp0, img7, "");
4343 return LLVMBuildInsertElement(builder, samp, samp0,
4344 LLVMConstInt(ctx->i32, 0, 0), "");
4345 }
4346
4347 static void tex_fetch_ptrs(
4348 struct lp_build_tgsi_context *bld_base,
4349 struct lp_build_emit_data *emit_data,
4350 LLVMValueRef *res_ptr, LLVMValueRef *samp_ptr, LLVMValueRef *fmask_ptr)
4351 {
4352 struct si_shader_context *ctx = si_shader_context(bld_base);
4353 const struct tgsi_full_instruction *inst = emit_data->inst;
4354 unsigned target = inst->Texture.Texture;
4355 unsigned sampler_src;
4356 unsigned sampler_index;
4357 LLVMValueRef index;
4358
4359 sampler_src = emit_data->inst->Instruction.NumSrcRegs - 1;
4360 sampler_index = emit_data->inst->Src[sampler_src].Register.Index;
4361
4362 if (emit_data->inst->Src[sampler_src].Register.Indirect) {
4363 const struct tgsi_full_src_register *reg = &emit_data->inst->Src[sampler_src];
4364
4365 index = get_bounded_indirect_index(ctx,
4366 &reg->Indirect,
4367 reg->Register.Index,
4368 SI_NUM_SAMPLERS);
4369 } else {
4370 index = LLVMConstInt(ctx->i32, sampler_index, 0);
4371 }
4372
4373 *res_ptr = load_sampler_desc(ctx, index, DESC_IMAGE);
4374
4375 if (target == TGSI_TEXTURE_2D_MSAA ||
4376 target == TGSI_TEXTURE_2D_ARRAY_MSAA) {
4377 if (samp_ptr)
4378 *samp_ptr = NULL;
4379 if (fmask_ptr)
4380 *fmask_ptr = load_sampler_desc(ctx, index, DESC_FMASK);
4381 } else {
4382 if (samp_ptr) {
4383 *samp_ptr = load_sampler_desc(ctx, index, DESC_SAMPLER);
4384 *samp_ptr = sici_fix_sampler_aniso(ctx, *res_ptr, *samp_ptr);
4385 }
4386 if (fmask_ptr)
4387 *fmask_ptr = NULL;
4388 }
4389 }
4390
4391 static void txq_fetch_args(
4392 struct lp_build_tgsi_context *bld_base,
4393 struct lp_build_emit_data *emit_data)
4394 {
4395 struct si_shader_context *ctx = si_shader_context(bld_base);
4396 struct gallivm_state *gallivm = bld_base->base.gallivm;
4397 LLVMBuilderRef builder = gallivm->builder;
4398 const struct tgsi_full_instruction *inst = emit_data->inst;
4399 unsigned target = inst->Texture.Texture;
4400 LLVMValueRef res_ptr;
4401 LLVMValueRef address;
4402
4403 tex_fetch_ptrs(bld_base, emit_data, &res_ptr, NULL, NULL);
4404
4405 if (target == TGSI_TEXTURE_BUFFER) {
4406 /* Read the size from the buffer descriptor directly. */
4407 LLVMValueRef res = LLVMBuildBitCast(builder, res_ptr, ctx->v8i32, "");
4408 emit_data->args[0] = get_buffer_size(bld_base, res);
4409 return;
4410 }
4411
4412 /* Textures - set the mip level. */
4413 address = lp_build_emit_fetch(bld_base, inst, 0, TGSI_CHAN_X);
4414
4415 set_tex_fetch_args(ctx, emit_data, TGSI_OPCODE_TXQ, target, res_ptr,
4416 NULL, &address, 1, 0xf);
4417 }
4418
4419 static void txq_emit(const struct lp_build_tgsi_action *action,
4420 struct lp_build_tgsi_context *bld_base,
4421 struct lp_build_emit_data *emit_data)
4422 {
4423 struct lp_build_context *base = &bld_base->base;
4424 unsigned target = emit_data->inst->Texture.Texture;
4425
4426 if (target == TGSI_TEXTURE_BUFFER) {
4427 /* Just return the buffer size. */
4428 emit_data->output[emit_data->chan] = emit_data->args[0];
4429 return;
4430 }
4431
4432 emit_data->output[emit_data->chan] = lp_build_intrinsic(
4433 base->gallivm->builder, "llvm.SI.getresinfo.i32",
4434 emit_data->dst_type, emit_data->args, emit_data->arg_count,
4435 LLVMReadNoneAttribute);
4436
4437 /* Divide the number of layers by 6 to get the number of cubes. */
4438 if (target == TGSI_TEXTURE_CUBE_ARRAY ||
4439 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
4440 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
4441 LLVMValueRef two = lp_build_const_int32(bld_base->base.gallivm, 2);
4442 LLVMValueRef six = lp_build_const_int32(bld_base->base.gallivm, 6);
4443
4444 LLVMValueRef v4 = emit_data->output[emit_data->chan];
4445 LLVMValueRef z = LLVMBuildExtractElement(builder, v4, two, "");
4446 z = LLVMBuildSDiv(builder, z, six, "");
4447
4448 emit_data->output[emit_data->chan] =
4449 LLVMBuildInsertElement(builder, v4, z, two, "");
4450 }
4451 }
4452
4453 static void tex_fetch_args(
4454 struct lp_build_tgsi_context *bld_base,
4455 struct lp_build_emit_data *emit_data)
4456 {
4457 struct si_shader_context *ctx = si_shader_context(bld_base);
4458 struct gallivm_state *gallivm = bld_base->base.gallivm;
4459 const struct tgsi_full_instruction *inst = emit_data->inst;
4460 unsigned opcode = inst->Instruction.Opcode;
4461 unsigned target = inst->Texture.Texture;
4462 LLVMValueRef coords[5], derivs[6];
4463 LLVMValueRef address[16];
4464 unsigned num_coords = tgsi_util_get_texture_coord_dim(target);
4465 int ref_pos = tgsi_util_get_shadow_ref_src_index(target);
4466 unsigned count = 0;
4467 unsigned chan;
4468 unsigned num_deriv_channels = 0;
4469 bool has_offset = inst->Texture.NumOffsets > 0;
4470 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL;
4471 unsigned dmask = 0xf;
4472
4473 tex_fetch_ptrs(bld_base, emit_data, &res_ptr, &samp_ptr, &fmask_ptr);
4474
4475 if (target == TGSI_TEXTURE_BUFFER) {
4476 LLVMTypeRef v2i128 = LLVMVectorType(ctx->i128, 2);
4477
4478 /* Bitcast and truncate v8i32 to v16i8. */
4479 LLVMValueRef res = res_ptr;
4480 res = LLVMBuildBitCast(gallivm->builder, res, v2i128, "");
4481 res = LLVMBuildExtractElement(gallivm->builder, res, bld_base->uint_bld.one, "");
4482 res = LLVMBuildBitCast(gallivm->builder, res, ctx->v16i8, "");
4483
4484 emit_data->dst_type = ctx->v4f32;
4485 emit_data->args[0] = res;
4486 emit_data->args[1] = bld_base->uint_bld.zero;
4487 emit_data->args[2] = lp_build_emit_fetch(bld_base, emit_data->inst, 0, TGSI_CHAN_X);
4488 emit_data->arg_count = 3;
4489 return;
4490 }
4491
4492 /* Fetch and project texture coordinates */
4493 coords[3] = lp_build_emit_fetch(bld_base, emit_data->inst, 0, TGSI_CHAN_W);
4494 for (chan = 0; chan < 3; chan++ ) {
4495 coords[chan] = lp_build_emit_fetch(bld_base,
4496 emit_data->inst, 0,
4497 chan);
4498 if (opcode == TGSI_OPCODE_TXP)
4499 coords[chan] = lp_build_emit_llvm_binary(bld_base,
4500 TGSI_OPCODE_DIV,
4501 coords[chan],
4502 coords[3]);
4503 }
4504
4505 if (opcode == TGSI_OPCODE_TXP)
4506 coords[3] = bld_base->base.one;
4507
4508 /* Pack offsets. */
4509 if (has_offset && opcode != TGSI_OPCODE_TXF) {
4510 /* The offsets are six-bit signed integers packed like this:
4511 * X=[5:0], Y=[13:8], and Z=[21:16].
4512 */
4513 LLVMValueRef offset[3], pack;
4514
4515 assert(inst->Texture.NumOffsets == 1);
4516
4517 for (chan = 0; chan < 3; chan++) {
4518 offset[chan] = lp_build_emit_fetch_texoffset(bld_base,
4519 emit_data->inst, 0, chan);
4520 offset[chan] = LLVMBuildAnd(gallivm->builder, offset[chan],
4521 lp_build_const_int32(gallivm, 0x3f), "");
4522 if (chan)
4523 offset[chan] = LLVMBuildShl(gallivm->builder, offset[chan],
4524 lp_build_const_int32(gallivm, chan*8), "");
4525 }
4526
4527 pack = LLVMBuildOr(gallivm->builder, offset[0], offset[1], "");
4528 pack = LLVMBuildOr(gallivm->builder, pack, offset[2], "");
4529 address[count++] = pack;
4530 }
4531
4532 /* Pack LOD bias value */
4533 if (opcode == TGSI_OPCODE_TXB)
4534 address[count++] = coords[3];
4535 if (opcode == TGSI_OPCODE_TXB2)
4536 address[count++] = lp_build_emit_fetch(bld_base, inst, 1, TGSI_CHAN_X);
4537
4538 /* Pack depth comparison value */
4539 if (tgsi_is_shadow_target(target) && opcode != TGSI_OPCODE_LODQ) {
4540 if (target == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
4541 address[count++] = lp_build_emit_fetch(bld_base, inst, 1, TGSI_CHAN_X);
4542 } else {
4543 assert(ref_pos >= 0);
4544 address[count++] = coords[ref_pos];
4545 }
4546 }
4547
4548 /* Pack user derivatives */
4549 if (opcode == TGSI_OPCODE_TXD) {
4550 int param, num_src_deriv_channels;
4551
4552 switch (target) {
4553 case TGSI_TEXTURE_3D:
4554 num_src_deriv_channels = 3;
4555 num_deriv_channels = 3;
4556 break;
4557 case TGSI_TEXTURE_2D:
4558 case TGSI_TEXTURE_SHADOW2D:
4559 case TGSI_TEXTURE_RECT:
4560 case TGSI_TEXTURE_SHADOWRECT:
4561 case TGSI_TEXTURE_2D_ARRAY:
4562 case TGSI_TEXTURE_SHADOW2D_ARRAY:
4563 num_src_deriv_channels = 2;
4564 num_deriv_channels = 2;
4565 break;
4566 case TGSI_TEXTURE_CUBE:
4567 case TGSI_TEXTURE_SHADOWCUBE:
4568 case TGSI_TEXTURE_CUBE_ARRAY:
4569 case TGSI_TEXTURE_SHADOWCUBE_ARRAY:
4570 /* Cube derivatives will be converted to 2D. */
4571 num_src_deriv_channels = 3;
4572 num_deriv_channels = 2;
4573 break;
4574 case TGSI_TEXTURE_1D:
4575 case TGSI_TEXTURE_SHADOW1D:
4576 case TGSI_TEXTURE_1D_ARRAY:
4577 case TGSI_TEXTURE_SHADOW1D_ARRAY:
4578 num_src_deriv_channels = 1;
4579 num_deriv_channels = 1;
4580 break;
4581 default:
4582 unreachable("invalid target");
4583 }
4584
4585 for (param = 0; param < 2; param++)
4586 for (chan = 0; chan < num_src_deriv_channels; chan++)
4587 derivs[param * num_src_deriv_channels + chan] =
4588 lp_build_emit_fetch(bld_base, inst, param+1, chan);
4589 }
4590
4591 if (target == TGSI_TEXTURE_CUBE ||
4592 target == TGSI_TEXTURE_CUBE_ARRAY ||
4593 target == TGSI_TEXTURE_SHADOWCUBE ||
4594 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY)
4595 radeon_llvm_emit_prepare_cube_coords(bld_base, emit_data, coords, derivs);
4596
4597 if (opcode == TGSI_OPCODE_TXD)
4598 for (int i = 0; i < num_deriv_channels * 2; i++)
4599 address[count++] = derivs[i];
4600
4601 /* Pack texture coordinates */
4602 address[count++] = coords[0];
4603 if (num_coords > 1)
4604 address[count++] = coords[1];
4605 if (num_coords > 2)
4606 address[count++] = coords[2];
4607
4608 /* Pack LOD or sample index */
4609 if (opcode == TGSI_OPCODE_TXL || opcode == TGSI_OPCODE_TXF)
4610 address[count++] = coords[3];
4611 else if (opcode == TGSI_OPCODE_TXL2)
4612 address[count++] = lp_build_emit_fetch(bld_base, inst, 1, TGSI_CHAN_X);
4613
4614 if (count > 16) {
4615 assert(!"Cannot handle more than 16 texture address parameters");
4616 count = 16;
4617 }
4618
4619 for (chan = 0; chan < count; chan++ ) {
4620 address[chan] = LLVMBuildBitCast(gallivm->builder,
4621 address[chan], ctx->i32, "");
4622 }
4623
4624 /* Adjust the sample index according to FMASK.
4625 *
4626 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
4627 * which is the identity mapping. Each nibble says which physical sample
4628 * should be fetched to get that sample.
4629 *
4630 * For example, 0x11111100 means there are only 2 samples stored and
4631 * the second sample covers 3/4 of the pixel. When reading samples 0
4632 * and 1, return physical sample 0 (determined by the first two 0s
4633 * in FMASK), otherwise return physical sample 1.
4634 *
4635 * The sample index should be adjusted as follows:
4636 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
4637 */
4638 if (target == TGSI_TEXTURE_2D_MSAA ||
4639 target == TGSI_TEXTURE_2D_ARRAY_MSAA) {
4640 struct lp_build_context *uint_bld = &bld_base->uint_bld;
4641 struct lp_build_emit_data txf_emit_data = *emit_data;
4642 LLVMValueRef txf_address[4];
4643 unsigned txf_count = count;
4644 struct tgsi_full_instruction inst = {};
4645
4646 memcpy(txf_address, address, sizeof(txf_address));
4647
4648 if (target == TGSI_TEXTURE_2D_MSAA) {
4649 txf_address[2] = bld_base->uint_bld.zero;
4650 }
4651 txf_address[3] = bld_base->uint_bld.zero;
4652
4653 /* Read FMASK using TXF. */
4654 inst.Instruction.Opcode = TGSI_OPCODE_TXF;
4655 inst.Texture.Texture = target;
4656 txf_emit_data.inst = &inst;
4657 txf_emit_data.chan = 0;
4658 set_tex_fetch_args(ctx, &txf_emit_data, TGSI_OPCODE_TXF,
4659 target, fmask_ptr, NULL,
4660 txf_address, txf_count, 0xf);
4661 build_tex_intrinsic(&tex_action, bld_base, &txf_emit_data);
4662
4663 /* Initialize some constants. */
4664 LLVMValueRef four = LLVMConstInt(ctx->i32, 4, 0);
4665 LLVMValueRef F = LLVMConstInt(ctx->i32, 0xF, 0);
4666
4667 /* Apply the formula. */
4668 LLVMValueRef fmask =
4669 LLVMBuildExtractElement(gallivm->builder,
4670 txf_emit_data.output[0],
4671 uint_bld->zero, "");
4672
4673 unsigned sample_chan = target == TGSI_TEXTURE_2D_MSAA ? 2 : 3;
4674
4675 LLVMValueRef sample_index4 =
4676 LLVMBuildMul(gallivm->builder, address[sample_chan], four, "");
4677
4678 LLVMValueRef shifted_fmask =
4679 LLVMBuildLShr(gallivm->builder, fmask, sample_index4, "");
4680
4681 LLVMValueRef final_sample =
4682 LLVMBuildAnd(gallivm->builder, shifted_fmask, F, "");
4683
4684 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
4685 * resource descriptor is 0 (invalid),
4686 */
4687 LLVMValueRef fmask_desc =
4688 LLVMBuildBitCast(gallivm->builder, fmask_ptr,
4689 ctx->v8i32, "");
4690
4691 LLVMValueRef fmask_word1 =
4692 LLVMBuildExtractElement(gallivm->builder, fmask_desc,
4693 uint_bld->one, "");
4694
4695 LLVMValueRef word1_is_nonzero =
4696 LLVMBuildICmp(gallivm->builder, LLVMIntNE,
4697 fmask_word1, uint_bld->zero, "");
4698
4699 /* Replace the MSAA sample index. */
4700 address[sample_chan] =
4701 LLVMBuildSelect(gallivm->builder, word1_is_nonzero,
4702 final_sample, address[sample_chan], "");
4703 }
4704
4705 if (opcode == TGSI_OPCODE_TXF) {
4706 /* add tex offsets */
4707 if (inst->Texture.NumOffsets) {
4708 struct lp_build_context *uint_bld = &bld_base->uint_bld;
4709 struct lp_build_tgsi_soa_context *bld = lp_soa_context(bld_base);
4710 const struct tgsi_texture_offset *off = inst->TexOffsets;
4711
4712 assert(inst->Texture.NumOffsets == 1);
4713
4714 switch (target) {
4715 case TGSI_TEXTURE_3D:
4716 address[2] = lp_build_add(uint_bld, address[2],
4717 bld->immediates[off->Index][off->SwizzleZ]);
4718 /* fall through */
4719 case TGSI_TEXTURE_2D:
4720 case TGSI_TEXTURE_SHADOW2D:
4721 case TGSI_TEXTURE_RECT:
4722 case TGSI_TEXTURE_SHADOWRECT:
4723 case TGSI_TEXTURE_2D_ARRAY:
4724 case TGSI_TEXTURE_SHADOW2D_ARRAY:
4725 address[1] =
4726 lp_build_add(uint_bld, address[1],
4727 bld->immediates[off->Index][off->SwizzleY]);
4728 /* fall through */
4729 case TGSI_TEXTURE_1D:
4730 case TGSI_TEXTURE_SHADOW1D:
4731 case TGSI_TEXTURE_1D_ARRAY:
4732 case TGSI_TEXTURE_SHADOW1D_ARRAY:
4733 address[0] =
4734 lp_build_add(uint_bld, address[0],
4735 bld->immediates[off->Index][off->SwizzleX]);
4736 break;
4737 /* texture offsets do not apply to other texture targets */
4738 }
4739 }
4740 }
4741
4742 if (opcode == TGSI_OPCODE_TG4) {
4743 unsigned gather_comp = 0;
4744
4745 /* DMASK was repurposed for GATHER4. 4 components are always
4746 * returned and DMASK works like a swizzle - it selects
4747 * the component to fetch. The only valid DMASK values are
4748 * 1=red, 2=green, 4=blue, 8=alpha. (e.g. 1 returns
4749 * (red,red,red,red) etc.) The ISA document doesn't mention
4750 * this.
4751 */
4752
4753 /* Get the component index from src1.x for Gather4. */
4754 if (!tgsi_is_shadow_target(target)) {
4755 LLVMValueRef (*imms)[4] = lp_soa_context(bld_base)->immediates;
4756 LLVMValueRef comp_imm;
4757 struct tgsi_src_register src1 = inst->Src[1].Register;
4758
4759 assert(src1.File == TGSI_FILE_IMMEDIATE);
4760
4761 comp_imm = imms[src1.Index][src1.SwizzleX];
4762 gather_comp = LLVMConstIntGetZExtValue(comp_imm);
4763 gather_comp = CLAMP(gather_comp, 0, 3);
4764 }
4765
4766 dmask = 1 << gather_comp;
4767 }
4768
4769 set_tex_fetch_args(ctx, emit_data, opcode, target, res_ptr,
4770 samp_ptr, address, count, dmask);
4771 }
4772
4773 /* Gather4 should follow the same rules as bilinear filtering, but the hardware
4774 * incorrectly forces nearest filtering if the texture format is integer.
4775 * The only effect it has on Gather4, which always returns 4 texels for
4776 * bilinear filtering, is that the final coordinates are off by 0.5 of
4777 * the texel size.
4778 *
4779 * The workaround is to subtract 0.5 from the unnormalized coordinates,
4780 * or (0.5 / size) from the normalized coordinates.
4781 */
4782 static void si_lower_gather4_integer(struct si_shader_context *ctx,
4783 struct lp_build_emit_data *emit_data,
4784 const char *intr_name,
4785 unsigned coord_vgpr_index)
4786 {
4787 LLVMBuilderRef builder = ctx->radeon_bld.gallivm.builder;
4788 LLVMValueRef coord = emit_data->args[0];
4789 LLVMValueRef half_texel[2];
4790 int c;
4791
4792 if (emit_data->inst->Texture.Texture == TGSI_TEXTURE_RECT ||
4793 emit_data->inst->Texture.Texture == TGSI_TEXTURE_SHADOWRECT) {
4794 half_texel[0] = half_texel[1] = LLVMConstReal(ctx->f32, -0.5);
4795 } else {
4796 struct tgsi_full_instruction txq_inst = {};
4797 struct lp_build_emit_data txq_emit_data = {};
4798
4799 /* Query the texture size. */
4800 txq_inst.Texture.Texture = emit_data->inst->Texture.Texture;
4801 txq_emit_data.inst = &txq_inst;
4802 txq_emit_data.dst_type = ctx->v4i32;
4803 set_tex_fetch_args(ctx, &txq_emit_data, TGSI_OPCODE_TXQ,
4804 txq_inst.Texture.Texture,
4805 emit_data->args[1], NULL,
4806 &ctx->radeon_bld.soa.bld_base.uint_bld.zero,
4807 1, 0xf);
4808 txq_emit(NULL, &ctx->radeon_bld.soa.bld_base, &txq_emit_data);
4809
4810 /* Compute -0.5 / size. */
4811 for (c = 0; c < 2; c++) {
4812 half_texel[c] =
4813 LLVMBuildExtractElement(builder, txq_emit_data.output[0],
4814 LLVMConstInt(ctx->i32, c, 0), "");
4815 half_texel[c] = LLVMBuildUIToFP(builder, half_texel[c], ctx->f32, "");
4816 half_texel[c] =
4817 lp_build_emit_llvm_unary(&ctx->radeon_bld.soa.bld_base,
4818 TGSI_OPCODE_RCP, half_texel[c]);
4819 half_texel[c] = LLVMBuildFMul(builder, half_texel[c],
4820 LLVMConstReal(ctx->f32, -0.5), "");
4821 }
4822 }
4823
4824 for (c = 0; c < 2; c++) {
4825 LLVMValueRef tmp;
4826 LLVMValueRef index = LLVMConstInt(ctx->i32, coord_vgpr_index + c, 0);
4827
4828 tmp = LLVMBuildExtractElement(builder, coord, index, "");
4829 tmp = LLVMBuildBitCast(builder, tmp, ctx->f32, "");
4830 tmp = LLVMBuildFAdd(builder, tmp, half_texel[c], "");
4831 tmp = LLVMBuildBitCast(builder, tmp, ctx->i32, "");
4832 coord = LLVMBuildInsertElement(builder, coord, tmp, index, "");
4833 }
4834
4835 emit_data->args[0] = coord;
4836 emit_data->output[emit_data->chan] =
4837 lp_build_intrinsic(builder, intr_name, emit_data->dst_type,
4838 emit_data->args, emit_data->arg_count,
4839 LLVMReadNoneAttribute);
4840 }
4841
4842 static void build_tex_intrinsic(const struct lp_build_tgsi_action *action,
4843 struct lp_build_tgsi_context *bld_base,
4844 struct lp_build_emit_data *emit_data)
4845 {
4846 struct si_shader_context *ctx = si_shader_context(bld_base);
4847 struct lp_build_context *base = &bld_base->base;
4848 const struct tgsi_full_instruction *inst = emit_data->inst;
4849 unsigned opcode = inst->Instruction.Opcode;
4850 unsigned target = inst->Texture.Texture;
4851 char intr_name[127];
4852 bool has_offset = inst->Texture.NumOffsets > 0;
4853 bool is_shadow = tgsi_is_shadow_target(target);
4854 char type[64];
4855 const char *name = "llvm.SI.image.sample";
4856 const char *infix = "";
4857
4858 if (target == TGSI_TEXTURE_BUFFER) {
4859 emit_data->output[emit_data->chan] = lp_build_intrinsic(
4860 base->gallivm->builder,
4861 "llvm.SI.vs.load.input", emit_data->dst_type,
4862 emit_data->args, emit_data->arg_count,
4863 LLVMReadNoneAttribute);
4864 return;
4865 }
4866
4867 switch (opcode) {
4868 case TGSI_OPCODE_TXF:
4869 name = target == TGSI_TEXTURE_2D_MSAA ||
4870 target == TGSI_TEXTURE_2D_ARRAY_MSAA ?
4871 "llvm.SI.image.load" :
4872 "llvm.SI.image.load.mip";
4873 is_shadow = false;
4874 has_offset = false;
4875 break;
4876 case TGSI_OPCODE_LODQ:
4877 name = "llvm.SI.getlod";
4878 is_shadow = false;
4879 has_offset = false;
4880 break;
4881 case TGSI_OPCODE_TEX:
4882 case TGSI_OPCODE_TEX2:
4883 case TGSI_OPCODE_TXP:
4884 if (ctx->type != PIPE_SHADER_FRAGMENT)
4885 infix = ".lz";
4886 break;
4887 case TGSI_OPCODE_TXB:
4888 case TGSI_OPCODE_TXB2:
4889 assert(ctx->type == PIPE_SHADER_FRAGMENT);
4890 infix = ".b";
4891 break;
4892 case TGSI_OPCODE_TXL:
4893 case TGSI_OPCODE_TXL2:
4894 infix = ".l";
4895 break;
4896 case TGSI_OPCODE_TXD:
4897 infix = ".d";
4898 break;
4899 case TGSI_OPCODE_TG4:
4900 name = "llvm.SI.gather4";
4901 infix = ".lz";
4902 break;
4903 default:
4904 assert(0);
4905 return;
4906 }
4907
4908 /* Add the type and suffixes .c, .o if needed. */
4909 build_int_type_name(LLVMTypeOf(emit_data->args[0]), type, sizeof(type));
4910 sprintf(intr_name, "%s%s%s%s.%s",
4911 name, is_shadow ? ".c" : "", infix,
4912 has_offset ? ".o" : "", type);
4913
4914 /* The hardware needs special lowering for Gather4 with integer formats. */
4915 if (opcode == TGSI_OPCODE_TG4) {
4916 struct tgsi_shader_info *info = &ctx->shader->selector->info;
4917 /* This will also work with non-constant indexing because of how
4918 * glsl_to_tgsi works and we intent to preserve that behavior.
4919 */
4920 const unsigned src_idx = 2;
4921 unsigned sampler = inst->Src[src_idx].Register.Index;
4922
4923 assert(inst->Src[src_idx].Register.File == TGSI_FILE_SAMPLER);
4924
4925 if (info->sampler_type[sampler] == TGSI_RETURN_TYPE_SINT ||
4926 info->sampler_type[sampler] == TGSI_RETURN_TYPE_UINT) {
4927 /* Texture coordinates start after:
4928 * {offset, bias, z-compare, derivatives}
4929 * Only the offset and z-compare can occur here.
4930 */
4931 si_lower_gather4_integer(ctx, emit_data, intr_name,
4932 (int)has_offset + (int)is_shadow);
4933 return;
4934 }
4935 }
4936
4937 emit_data->output[emit_data->chan] = lp_build_intrinsic(
4938 base->gallivm->builder, intr_name, emit_data->dst_type,
4939 emit_data->args, emit_data->arg_count,
4940 LLVMReadNoneAttribute);
4941 }
4942
4943 static void si_llvm_emit_txqs(
4944 const struct lp_build_tgsi_action *action,
4945 struct lp_build_tgsi_context *bld_base,
4946 struct lp_build_emit_data *emit_data)
4947 {
4948 struct si_shader_context *ctx = si_shader_context(bld_base);
4949 struct gallivm_state *gallivm = bld_base->base.gallivm;
4950 LLVMBuilderRef builder = gallivm->builder;
4951 LLVMValueRef res, samples;
4952 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL;
4953
4954 tex_fetch_ptrs(bld_base, emit_data, &res_ptr, &samp_ptr, &fmask_ptr);
4955
4956
4957 /* Read the samples from the descriptor directly. */
4958 res = LLVMBuildBitCast(builder, res_ptr, ctx->v8i32, "");
4959 samples = LLVMBuildExtractElement(
4960 builder, res,
4961 lp_build_const_int32(gallivm, 3), "");
4962 samples = LLVMBuildLShr(builder, samples,
4963 lp_build_const_int32(gallivm, 16), "");
4964 samples = LLVMBuildAnd(builder, samples,
4965 lp_build_const_int32(gallivm, 0xf), "");
4966 samples = LLVMBuildShl(builder, lp_build_const_int32(gallivm, 1),
4967 samples, "");
4968
4969 emit_data->output[emit_data->chan] = samples;
4970 }
4971
4972 /*
4973 * SI implements derivatives using the local data store (LDS)
4974 * All writes to the LDS happen in all executing threads at
4975 * the same time. TID is the Thread ID for the current
4976 * thread and is a value between 0 and 63, representing
4977 * the thread's position in the wavefront.
4978 *
4979 * For the pixel shader threads are grouped into quads of four pixels.
4980 * The TIDs of the pixels of a quad are:
4981 *
4982 * +------+------+
4983 * |4n + 0|4n + 1|
4984 * +------+------+
4985 * |4n + 2|4n + 3|
4986 * +------+------+
4987 *
4988 * So, masking the TID with 0xfffffffc yields the TID of the top left pixel
4989 * of the quad, masking with 0xfffffffd yields the TID of the top pixel of
4990 * the current pixel's column, and masking with 0xfffffffe yields the TID
4991 * of the left pixel of the current pixel's row.
4992 *
4993 * Adding 1 yields the TID of the pixel to the right of the left pixel, and
4994 * adding 2 yields the TID of the pixel below the top pixel.
4995 */
4996 /* masks for thread ID. */
4997 #define TID_MASK_TOP_LEFT 0xfffffffc
4998 #define TID_MASK_TOP 0xfffffffd
4999 #define TID_MASK_LEFT 0xfffffffe
5000
5001 static void si_llvm_emit_ddxy(
5002 const struct lp_build_tgsi_action *action,
5003 struct lp_build_tgsi_context *bld_base,
5004 struct lp_build_emit_data *emit_data)
5005 {
5006 struct si_shader_context *ctx = si_shader_context(bld_base);
5007 struct gallivm_state *gallivm = bld_base->base.gallivm;
5008 unsigned opcode = emit_data->info->opcode;
5009 LLVMValueRef thread_id, tl, trbl, tl_tid, trbl_tid, val, args[2];
5010 int idx;
5011 unsigned mask;
5012 bool has_ds_bpermute = HAVE_LLVM >= 0x0309 &&
5013 ctx->screen->b.chip_class >= VI;
5014
5015 thread_id = get_thread_id(ctx);
5016
5017 if (opcode == TGSI_OPCODE_DDX_FINE)
5018 mask = TID_MASK_LEFT;
5019 else if (opcode == TGSI_OPCODE_DDY_FINE)
5020 mask = TID_MASK_TOP;
5021 else
5022 mask = TID_MASK_TOP_LEFT;
5023
5024 tl_tid = LLVMBuildAnd(gallivm->builder, thread_id,
5025 lp_build_const_int32(gallivm, mask), "");
5026
5027 /* for DDX we want to next X pixel, DDY next Y pixel. */
5028 idx = (opcode == TGSI_OPCODE_DDX || opcode == TGSI_OPCODE_DDX_FINE) ? 1 : 2;
5029 trbl_tid = LLVMBuildAdd(gallivm->builder, tl_tid,
5030 lp_build_const_int32(gallivm, idx), "");
5031
5032 val = LLVMBuildBitCast(gallivm->builder, emit_data->args[0], ctx->i32, "");
5033
5034 if (has_ds_bpermute) {
5035 args[0] = LLVMBuildMul(gallivm->builder, tl_tid,
5036 lp_build_const_int32(gallivm, 4), "");
5037 args[1] = val;
5038 tl = lp_build_intrinsic(gallivm->builder,
5039 "llvm.amdgcn.ds.bpermute", ctx->i32,
5040 args, 2, LLVMReadNoneAttribute);
5041
5042 args[0] = LLVMBuildMul(gallivm->builder, trbl_tid,
5043 lp_build_const_int32(gallivm, 4), "");
5044 trbl = lp_build_intrinsic(gallivm->builder,
5045 "llvm.amdgcn.ds.bpermute", ctx->i32,
5046 args, 2, LLVMReadNoneAttribute);
5047 } else {
5048 LLVMValueRef store_ptr, load_ptr0, load_ptr1;
5049
5050 store_ptr = build_gep0(ctx, ctx->lds, thread_id);
5051 load_ptr0 = build_gep0(ctx, ctx->lds, tl_tid);
5052 load_ptr1 = build_gep0(ctx, ctx->lds, trbl_tid);
5053
5054 LLVMBuildStore(gallivm->builder, val, store_ptr);
5055 tl = LLVMBuildLoad(gallivm->builder, load_ptr0, "");
5056 trbl = LLVMBuildLoad(gallivm->builder, load_ptr1, "");
5057 }
5058
5059 tl = LLVMBuildBitCast(gallivm->builder, tl, ctx->f32, "");
5060 trbl = LLVMBuildBitCast(gallivm->builder, trbl, ctx->f32, "");
5061
5062 emit_data->output[emit_data->chan] =
5063 LLVMBuildFSub(gallivm->builder, trbl, tl, "");
5064 }
5065
5066 /*
5067 * this takes an I,J coordinate pair,
5068 * and works out the X and Y derivatives.
5069 * it returns DDX(I), DDX(J), DDY(I), DDY(J).
5070 */
5071 static LLVMValueRef si_llvm_emit_ddxy_interp(
5072 struct lp_build_tgsi_context *bld_base,
5073 LLVMValueRef interp_ij)
5074 {
5075 struct si_shader_context *ctx = si_shader_context(bld_base);
5076 struct gallivm_state *gallivm = bld_base->base.gallivm;
5077 LLVMValueRef store_ptr, load_ptr_x, load_ptr_y, load_ptr_ddx, load_ptr_ddy, temp, temp2;
5078 LLVMValueRef tl, tr, bl, result[4], thread_id;
5079 unsigned c;
5080
5081 thread_id = get_thread_id(ctx);
5082 store_ptr = build_gep0(ctx, ctx->lds, thread_id);
5083
5084 temp = LLVMBuildAnd(gallivm->builder, thread_id,
5085 lp_build_const_int32(gallivm, TID_MASK_LEFT), "");
5086
5087 temp2 = LLVMBuildAnd(gallivm->builder, thread_id,
5088 lp_build_const_int32(gallivm, TID_MASK_TOP), "");
5089
5090 load_ptr_x = build_gep0(ctx, ctx->lds, temp);
5091
5092 load_ptr_y = build_gep0(ctx, ctx->lds, temp2);
5093
5094 load_ptr_ddx = build_gep0(ctx, ctx->lds,
5095 LLVMBuildAdd(gallivm->builder, temp,
5096 lp_build_const_int32(gallivm, 1), ""));
5097
5098 load_ptr_ddy = build_gep0(ctx, ctx->lds,
5099 LLVMBuildAdd(gallivm->builder, temp2,
5100 lp_build_const_int32(gallivm, 2), ""));
5101
5102 for (c = 0; c < 2; ++c) {
5103 LLVMValueRef store_val;
5104 LLVMValueRef c_ll = lp_build_const_int32(gallivm, c);
5105
5106 store_val = LLVMBuildExtractElement(gallivm->builder,
5107 interp_ij, c_ll, "");
5108 LLVMBuildStore(gallivm->builder,
5109 store_val,
5110 store_ptr);
5111
5112 tl = LLVMBuildLoad(gallivm->builder, load_ptr_x, "");
5113 tl = LLVMBuildBitCast(gallivm->builder, tl, ctx->f32, "");
5114
5115 tr = LLVMBuildLoad(gallivm->builder, load_ptr_ddx, "");
5116 tr = LLVMBuildBitCast(gallivm->builder, tr, ctx->f32, "");
5117
5118 result[c] = LLVMBuildFSub(gallivm->builder, tr, tl, "");
5119
5120 tl = LLVMBuildLoad(gallivm->builder, load_ptr_y, "");
5121 tl = LLVMBuildBitCast(gallivm->builder, tl, ctx->f32, "");
5122
5123 bl = LLVMBuildLoad(gallivm->builder, load_ptr_ddy, "");
5124 bl = LLVMBuildBitCast(gallivm->builder, bl, ctx->f32, "");
5125
5126 result[c + 2] = LLVMBuildFSub(gallivm->builder, bl, tl, "");
5127 }
5128
5129 return lp_build_gather_values(gallivm, result, 4);
5130 }
5131
5132 static void interp_fetch_args(
5133 struct lp_build_tgsi_context *bld_base,
5134 struct lp_build_emit_data *emit_data)
5135 {
5136 struct si_shader_context *ctx = si_shader_context(bld_base);
5137 struct gallivm_state *gallivm = bld_base->base.gallivm;
5138 const struct tgsi_full_instruction *inst = emit_data->inst;
5139
5140 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET) {
5141 /* offset is in second src, first two channels */
5142 emit_data->args[0] = lp_build_emit_fetch(bld_base,
5143 emit_data->inst, 1,
5144 TGSI_CHAN_X);
5145 emit_data->args[1] = lp_build_emit_fetch(bld_base,
5146 emit_data->inst, 1,
5147 TGSI_CHAN_Y);
5148 emit_data->arg_count = 2;
5149 } else if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
5150 LLVMValueRef sample_position;
5151 LLVMValueRef sample_id;
5152 LLVMValueRef halfval = lp_build_const_float(gallivm, 0.5f);
5153
5154 /* fetch sample ID, then fetch its sample position,
5155 * and place into first two channels.
5156 */
5157 sample_id = lp_build_emit_fetch(bld_base,
5158 emit_data->inst, 1, TGSI_CHAN_X);
5159 sample_id = LLVMBuildBitCast(gallivm->builder, sample_id,
5160 ctx->i32, "");
5161 sample_position = load_sample_position(&ctx->radeon_bld, sample_id);
5162
5163 emit_data->args[0] = LLVMBuildExtractElement(gallivm->builder,
5164 sample_position,
5165 lp_build_const_int32(gallivm, 0), "");
5166
5167 emit_data->args[0] = LLVMBuildFSub(gallivm->builder, emit_data->args[0], halfval, "");
5168 emit_data->args[1] = LLVMBuildExtractElement(gallivm->builder,
5169 sample_position,
5170 lp_build_const_int32(gallivm, 1), "");
5171 emit_data->args[1] = LLVMBuildFSub(gallivm->builder, emit_data->args[1], halfval, "");
5172 emit_data->arg_count = 2;
5173 }
5174 }
5175
5176 static void build_interp_intrinsic(const struct lp_build_tgsi_action *action,
5177 struct lp_build_tgsi_context *bld_base,
5178 struct lp_build_emit_data *emit_data)
5179 {
5180 struct si_shader_context *ctx = si_shader_context(bld_base);
5181 struct si_shader *shader = ctx->shader;
5182 struct gallivm_state *gallivm = bld_base->base.gallivm;
5183 LLVMValueRef interp_param;
5184 const struct tgsi_full_instruction *inst = emit_data->inst;
5185 const char *intr_name;
5186 int input_index = inst->Src[0].Register.Index;
5187 int chan;
5188 int i;
5189 LLVMValueRef attr_number;
5190 LLVMValueRef params = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_PRIM_MASK);
5191 int interp_param_idx;
5192 unsigned interp = shader->selector->info.input_interpolate[input_index];
5193 unsigned location;
5194
5195 assert(inst->Src[0].Register.File == TGSI_FILE_INPUT);
5196
5197 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
5198 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE)
5199 location = TGSI_INTERPOLATE_LOC_CENTER;
5200 else
5201 location = TGSI_INTERPOLATE_LOC_CENTROID;
5202
5203 interp_param_idx = lookup_interp_param_index(interp, location);
5204 if (interp_param_idx == -1)
5205 return;
5206 else if (interp_param_idx)
5207 interp_param = get_interp_param(ctx, interp_param_idx);
5208 else
5209 interp_param = NULL;
5210
5211 attr_number = lp_build_const_int32(gallivm, input_index);
5212
5213 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
5214 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
5215 LLVMValueRef ij_out[2];
5216 LLVMValueRef ddxy_out = si_llvm_emit_ddxy_interp(bld_base, interp_param);
5217
5218 /*
5219 * take the I then J parameters, and the DDX/Y for it, and
5220 * calculate the IJ inputs for the interpolator.
5221 * temp1 = ddx * offset/sample.x + I;
5222 * interp_param.I = ddy * offset/sample.y + temp1;
5223 * temp1 = ddx * offset/sample.x + J;
5224 * interp_param.J = ddy * offset/sample.y + temp1;
5225 */
5226 for (i = 0; i < 2; i++) {
5227 LLVMValueRef ix_ll = lp_build_const_int32(gallivm, i);
5228 LLVMValueRef iy_ll = lp_build_const_int32(gallivm, i + 2);
5229 LLVMValueRef ddx_el = LLVMBuildExtractElement(gallivm->builder,
5230 ddxy_out, ix_ll, "");
5231 LLVMValueRef ddy_el = LLVMBuildExtractElement(gallivm->builder,
5232 ddxy_out, iy_ll, "");
5233 LLVMValueRef interp_el = LLVMBuildExtractElement(gallivm->builder,
5234 interp_param, ix_ll, "");
5235 LLVMValueRef temp1, temp2;
5236
5237 interp_el = LLVMBuildBitCast(gallivm->builder, interp_el,
5238 ctx->f32, "");
5239
5240 temp1 = LLVMBuildFMul(gallivm->builder, ddx_el, emit_data->args[0], "");
5241
5242 temp1 = LLVMBuildFAdd(gallivm->builder, temp1, interp_el, "");
5243
5244 temp2 = LLVMBuildFMul(gallivm->builder, ddy_el, emit_data->args[1], "");
5245
5246 temp2 = LLVMBuildFAdd(gallivm->builder, temp2, temp1, "");
5247
5248 ij_out[i] = LLVMBuildBitCast(gallivm->builder,
5249 temp2, ctx->i32, "");
5250 }
5251 interp_param = lp_build_gather_values(bld_base->base.gallivm, ij_out, 2);
5252 }
5253
5254 intr_name = interp_param ? "llvm.SI.fs.interp" : "llvm.SI.fs.constant";
5255 for (chan = 0; chan < 2; chan++) {
5256 LLVMValueRef args[4];
5257 LLVMValueRef llvm_chan;
5258 unsigned schan;
5259
5260 schan = tgsi_util_get_full_src_register_swizzle(&inst->Src[0], chan);
5261 llvm_chan = lp_build_const_int32(gallivm, schan);
5262
5263 args[0] = llvm_chan;
5264 args[1] = attr_number;
5265 args[2] = params;
5266 args[3] = interp_param;
5267
5268 emit_data->output[chan] =
5269 lp_build_intrinsic(gallivm->builder, intr_name,
5270 ctx->f32, args, args[3] ? 4 : 3,
5271 LLVMReadNoneAttribute);
5272 }
5273 }
5274
5275 static unsigned si_llvm_get_stream(struct lp_build_tgsi_context *bld_base,
5276 struct lp_build_emit_data *emit_data)
5277 {
5278 LLVMValueRef (*imms)[4] = lp_soa_context(bld_base)->immediates;
5279 struct tgsi_src_register src0 = emit_data->inst->Src[0].Register;
5280 unsigned stream;
5281
5282 assert(src0.File == TGSI_FILE_IMMEDIATE);
5283
5284 stream = LLVMConstIntGetZExtValue(imms[src0.Index][src0.SwizzleX]) & 0x3;
5285 return stream;
5286 }
5287
5288 /* Emit one vertex from the geometry shader */
5289 static void si_llvm_emit_vertex(
5290 const struct lp_build_tgsi_action *action,
5291 struct lp_build_tgsi_context *bld_base,
5292 struct lp_build_emit_data *emit_data)
5293 {
5294 struct si_shader_context *ctx = si_shader_context(bld_base);
5295 struct lp_build_context *uint = &bld_base->uint_bld;
5296 struct si_shader *shader = ctx->shader;
5297 struct tgsi_shader_info *info = &shader->selector->info;
5298 struct gallivm_state *gallivm = bld_base->base.gallivm;
5299 LLVMValueRef soffset = LLVMGetParam(ctx->radeon_bld.main_fn,
5300 SI_PARAM_GS2VS_OFFSET);
5301 LLVMValueRef gs_next_vertex;
5302 LLVMValueRef can_emit, kill;
5303 LLVMValueRef args[2];
5304 unsigned chan;
5305 int i;
5306 unsigned stream;
5307
5308 stream = si_llvm_get_stream(bld_base, emit_data);
5309
5310 /* Write vertex attribute values to GSVS ring */
5311 gs_next_vertex = LLVMBuildLoad(gallivm->builder,
5312 ctx->gs_next_vertex[stream],
5313 "");
5314
5315 /* If this thread has already emitted the declared maximum number of
5316 * vertices, kill it: excessive vertex emissions are not supposed to
5317 * have any effect, and GS threads have no externally observable
5318 * effects other than emitting vertices.
5319 */
5320 can_emit = LLVMBuildICmp(gallivm->builder, LLVMIntULE, gs_next_vertex,
5321 lp_build_const_int32(gallivm,
5322 shader->selector->gs_max_out_vertices), "");
5323 kill = lp_build_select(&bld_base->base, can_emit,
5324 lp_build_const_float(gallivm, 1.0f),
5325 lp_build_const_float(gallivm, -1.0f));
5326
5327 lp_build_intrinsic(gallivm->builder, "llvm.AMDGPU.kill",
5328 ctx->voidt, &kill, 1, 0);
5329
5330 for (i = 0; i < info->num_outputs; i++) {
5331 LLVMValueRef *out_ptr =
5332 ctx->radeon_bld.soa.outputs[i];
5333
5334 for (chan = 0; chan < 4; chan++) {
5335 LLVMValueRef out_val = LLVMBuildLoad(gallivm->builder, out_ptr[chan], "");
5336 LLVMValueRef voffset =
5337 lp_build_const_int32(gallivm, (i * 4 + chan) *
5338 shader->selector->gs_max_out_vertices);
5339
5340 voffset = lp_build_add(uint, voffset, gs_next_vertex);
5341 voffset = lp_build_mul_imm(uint, voffset, 4);
5342
5343 out_val = LLVMBuildBitCast(gallivm->builder, out_val, ctx->i32, "");
5344
5345 build_tbuffer_store(ctx,
5346 ctx->gsvs_ring[stream],
5347 out_val, 1,
5348 voffset, soffset, 0,
5349 V_008F0C_BUF_DATA_FORMAT_32,
5350 V_008F0C_BUF_NUM_FORMAT_UINT,
5351 1, 0, 1, 1, 0);
5352 }
5353 }
5354 gs_next_vertex = lp_build_add(uint, gs_next_vertex,
5355 lp_build_const_int32(gallivm, 1));
5356
5357 LLVMBuildStore(gallivm->builder, gs_next_vertex, ctx->gs_next_vertex[stream]);
5358
5359 /* Signal vertex emission */
5360 args[0] = lp_build_const_int32(gallivm, SENDMSG_GS_OP_EMIT | SENDMSG_GS | (stream << 8));
5361 args[1] = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_GS_WAVE_ID);
5362 lp_build_intrinsic(gallivm->builder, "llvm.SI.sendmsg",
5363 ctx->voidt, args, 2, 0);
5364 }
5365
5366 /* Cut one primitive from the geometry shader */
5367 static void si_llvm_emit_primitive(
5368 const struct lp_build_tgsi_action *action,
5369 struct lp_build_tgsi_context *bld_base,
5370 struct lp_build_emit_data *emit_data)
5371 {
5372 struct si_shader_context *ctx = si_shader_context(bld_base);
5373 struct gallivm_state *gallivm = bld_base->base.gallivm;
5374 LLVMValueRef args[2];
5375 unsigned stream;
5376
5377 /* Signal primitive cut */
5378 stream = si_llvm_get_stream(bld_base, emit_data);
5379 args[0] = lp_build_const_int32(gallivm, SENDMSG_GS_OP_CUT | SENDMSG_GS | (stream << 8));
5380 args[1] = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_GS_WAVE_ID);
5381 lp_build_intrinsic(gallivm->builder, "llvm.SI.sendmsg",
5382 ctx->voidt, args, 2, 0);
5383 }
5384
5385 static void si_llvm_emit_barrier(const struct lp_build_tgsi_action *action,
5386 struct lp_build_tgsi_context *bld_base,
5387 struct lp_build_emit_data *emit_data)
5388 {
5389 struct si_shader_context *ctx = si_shader_context(bld_base);
5390 struct gallivm_state *gallivm = bld_base->base.gallivm;
5391
5392 /* The real barrier instruction isn’t needed, because an entire patch
5393 * always fits into a single wave.
5394 */
5395 if (ctx->type == PIPE_SHADER_TESS_CTRL) {
5396 emit_optimization_barrier(ctx);
5397 return;
5398 }
5399
5400 lp_build_intrinsic(gallivm->builder,
5401 HAVE_LLVM >= 0x0309 ? "llvm.amdgcn.s.barrier"
5402 : "llvm.AMDGPU.barrier.local",
5403 ctx->voidt, NULL, 0, 0);
5404 }
5405
5406 static const struct lp_build_tgsi_action tex_action = {
5407 .fetch_args = tex_fetch_args,
5408 .emit = build_tex_intrinsic,
5409 };
5410
5411 static const struct lp_build_tgsi_action interp_action = {
5412 .fetch_args = interp_fetch_args,
5413 .emit = build_interp_intrinsic,
5414 };
5415
5416 static void si_create_function(struct si_shader_context *ctx,
5417 LLVMTypeRef *returns, unsigned num_returns,
5418 LLVMTypeRef *params, unsigned num_params,
5419 int last_sgpr)
5420 {
5421 int i;
5422
5423 radeon_llvm_create_func(&ctx->radeon_bld, returns, num_returns,
5424 params, num_params);
5425 radeon_llvm_shader_type(ctx->radeon_bld.main_fn, ctx->type);
5426 ctx->return_value = LLVMGetUndef(ctx->radeon_bld.return_type);
5427
5428 for (i = 0; i <= last_sgpr; ++i) {
5429 LLVMValueRef P = LLVMGetParam(ctx->radeon_bld.main_fn, i);
5430
5431 /* The combination of:
5432 * - ByVal
5433 * - dereferenceable
5434 * - invariant.load
5435 * allows the optimization passes to move loads and reduces
5436 * SGPR spilling significantly.
5437 */
5438 if (LLVMGetTypeKind(LLVMTypeOf(P)) == LLVMPointerTypeKind) {
5439 LLVMAddAttribute(P, LLVMByValAttribute);
5440 lp_add_attr_dereferenceable(P, UINT64_MAX);
5441 } else
5442 LLVMAddAttribute(P, LLVMInRegAttribute);
5443 }
5444
5445 if (ctx->screen->b.debug_flags & DBG_UNSAFE_MATH) {
5446 /* These were copied from some LLVM test. */
5447 LLVMAddTargetDependentFunctionAttr(ctx->radeon_bld.main_fn,
5448 "less-precise-fpmad",
5449 "true");
5450 LLVMAddTargetDependentFunctionAttr(ctx->radeon_bld.main_fn,
5451 "no-infs-fp-math",
5452 "true");
5453 LLVMAddTargetDependentFunctionAttr(ctx->radeon_bld.main_fn,
5454 "no-nans-fp-math",
5455 "true");
5456 LLVMAddTargetDependentFunctionAttr(ctx->radeon_bld.main_fn,
5457 "unsafe-fp-math",
5458 "true");
5459 }
5460 }
5461
5462 static void create_meta_data(struct si_shader_context *ctx)
5463 {
5464 struct gallivm_state *gallivm = ctx->radeon_bld.soa.bld_base.base.gallivm;
5465
5466 ctx->invariant_load_md_kind = LLVMGetMDKindIDInContext(gallivm->context,
5467 "invariant.load", 14);
5468 ctx->range_md_kind = LLVMGetMDKindIDInContext(gallivm->context,
5469 "range", 5);
5470 ctx->uniform_md_kind = LLVMGetMDKindIDInContext(gallivm->context,
5471 "amdgpu.uniform", 14);
5472
5473 ctx->empty_md = LLVMMDNodeInContext(gallivm->context, NULL, 0);
5474 }
5475
5476 static void declare_streamout_params(struct si_shader_context *ctx,
5477 struct pipe_stream_output_info *so,
5478 LLVMTypeRef *params, LLVMTypeRef i32,
5479 unsigned *num_params)
5480 {
5481 int i;
5482
5483 /* Streamout SGPRs. */
5484 if (so->num_outputs) {
5485 if (ctx->type != PIPE_SHADER_TESS_EVAL)
5486 params[ctx->param_streamout_config = (*num_params)++] = i32;
5487 else
5488 ctx->param_streamout_config = ctx->param_tess_offchip;
5489
5490 params[ctx->param_streamout_write_index = (*num_params)++] = i32;
5491 }
5492 /* A streamout buffer offset is loaded if the stride is non-zero. */
5493 for (i = 0; i < 4; i++) {
5494 if (!so->stride[i])
5495 continue;
5496
5497 params[ctx->param_streamout_offset[i] = (*num_params)++] = i32;
5498 }
5499 }
5500
5501 static unsigned llvm_get_type_size(LLVMTypeRef type)
5502 {
5503 LLVMTypeKind kind = LLVMGetTypeKind(type);
5504
5505 switch (kind) {
5506 case LLVMIntegerTypeKind:
5507 return LLVMGetIntTypeWidth(type) / 8;
5508 case LLVMFloatTypeKind:
5509 return 4;
5510 case LLVMPointerTypeKind:
5511 return 8;
5512 case LLVMVectorTypeKind:
5513 return LLVMGetVectorSize(type) *
5514 llvm_get_type_size(LLVMGetElementType(type));
5515 default:
5516 assert(0);
5517 return 0;
5518 }
5519 }
5520
5521 static void declare_tess_lds(struct si_shader_context *ctx)
5522 {
5523 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
5524 struct lp_build_tgsi_context *bld_base = &ctx->radeon_bld.soa.bld_base;
5525 struct lp_build_context *uint = &bld_base->uint_bld;
5526
5527 unsigned lds_size = ctx->screen->b.chip_class >= CIK ? 65536 : 32768;
5528 ctx->lds = LLVMBuildIntToPtr(gallivm->builder, uint->zero,
5529 LLVMPointerType(LLVMArrayType(ctx->i32, lds_size / 4), LOCAL_ADDR_SPACE),
5530 "tess_lds");
5531 }
5532
5533 static void create_function(struct si_shader_context *ctx)
5534 {
5535 struct lp_build_tgsi_context *bld_base = &ctx->radeon_bld.soa.bld_base;
5536 struct gallivm_state *gallivm = bld_base->base.gallivm;
5537 struct si_shader *shader = ctx->shader;
5538 LLVMTypeRef params[SI_NUM_PARAMS + SI_NUM_VERTEX_BUFFERS], v3i32;
5539 LLVMTypeRef returns[16+32*4];
5540 unsigned i, last_sgpr, num_params, num_return_sgprs;
5541 unsigned num_returns = 0;
5542
5543 v3i32 = LLVMVectorType(ctx->i32, 3);
5544
5545 params[SI_PARAM_RW_BUFFERS] = const_array(ctx->v16i8, SI_NUM_RW_BUFFERS);
5546 params[SI_PARAM_CONST_BUFFERS] = const_array(ctx->v16i8, SI_NUM_CONST_BUFFERS);
5547 params[SI_PARAM_SAMPLERS] = const_array(ctx->v8i32, SI_NUM_SAMPLERS);
5548 params[SI_PARAM_IMAGES] = const_array(ctx->v8i32, SI_NUM_IMAGES);
5549 params[SI_PARAM_SHADER_BUFFERS] = const_array(ctx->v4i32, SI_NUM_SHADER_BUFFERS);
5550
5551 switch (ctx->type) {
5552 case PIPE_SHADER_VERTEX:
5553 params[SI_PARAM_VERTEX_BUFFERS] = const_array(ctx->v16i8, SI_NUM_VERTEX_BUFFERS);
5554 params[SI_PARAM_BASE_VERTEX] = ctx->i32;
5555 params[SI_PARAM_START_INSTANCE] = ctx->i32;
5556 params[SI_PARAM_DRAWID] = ctx->i32;
5557 num_params = SI_PARAM_DRAWID+1;
5558
5559 if (shader->key.vs.as_es) {
5560 params[ctx->param_es2gs_offset = num_params++] = ctx->i32;
5561 } else if (shader->key.vs.as_ls) {
5562 params[SI_PARAM_LS_OUT_LAYOUT] = ctx->i32;
5563 num_params = SI_PARAM_LS_OUT_LAYOUT+1;
5564 } else {
5565 if (ctx->is_gs_copy_shader) {
5566 num_params = SI_PARAM_RW_BUFFERS+1;
5567 } else {
5568 params[SI_PARAM_VS_STATE_BITS] = ctx->i32;
5569 num_params = SI_PARAM_VS_STATE_BITS+1;
5570 }
5571
5572 /* The locations of the other parameters are assigned dynamically. */
5573 declare_streamout_params(ctx, &shader->selector->so,
5574 params, ctx->i32, &num_params);
5575 }
5576
5577 last_sgpr = num_params-1;
5578
5579 /* VGPRs */
5580 params[ctx->param_vertex_id = num_params++] = ctx->i32;
5581 params[ctx->param_rel_auto_id = num_params++] = ctx->i32;
5582 params[ctx->param_vs_prim_id = num_params++] = ctx->i32;
5583 params[ctx->param_instance_id = num_params++] = ctx->i32;
5584
5585 if (!ctx->is_monolithic &&
5586 !ctx->is_gs_copy_shader) {
5587 /* Vertex load indices. */
5588 ctx->param_vertex_index0 = num_params;
5589
5590 for (i = 0; i < shader->selector->info.num_inputs; i++)
5591 params[num_params++] = ctx->i32;
5592
5593 /* PrimitiveID output. */
5594 if (!shader->key.vs.as_es && !shader->key.vs.as_ls)
5595 for (i = 0; i <= VS_EPILOG_PRIMID_LOC; i++)
5596 returns[num_returns++] = ctx->f32;
5597 }
5598 break;
5599
5600 case PIPE_SHADER_TESS_CTRL:
5601 params[SI_PARAM_TCS_OFFCHIP_LAYOUT] = ctx->i32;
5602 params[SI_PARAM_TCS_OUT_OFFSETS] = ctx->i32;
5603 params[SI_PARAM_TCS_OUT_LAYOUT] = ctx->i32;
5604 params[SI_PARAM_TCS_IN_LAYOUT] = ctx->i32;
5605 params[ctx->param_oc_lds = SI_PARAM_TCS_OC_LDS] = ctx->i32;
5606 params[SI_PARAM_TESS_FACTOR_OFFSET] = ctx->i32;
5607 last_sgpr = SI_PARAM_TESS_FACTOR_OFFSET;
5608
5609 /* VGPRs */
5610 params[SI_PARAM_PATCH_ID] = ctx->i32;
5611 params[SI_PARAM_REL_IDS] = ctx->i32;
5612 num_params = SI_PARAM_REL_IDS+1;
5613
5614 if (!ctx->is_monolithic) {
5615 /* SI_PARAM_TCS_OC_LDS and PARAM_TESS_FACTOR_OFFSET are
5616 * placed after the user SGPRs.
5617 */
5618 for (i = 0; i < SI_TCS_NUM_USER_SGPR + 2; i++)
5619 returns[num_returns++] = ctx->i32; /* SGPRs */
5620
5621 for (i = 0; i < 3; i++)
5622 returns[num_returns++] = ctx->f32; /* VGPRs */
5623 }
5624 break;
5625
5626 case PIPE_SHADER_TESS_EVAL:
5627 params[SI_PARAM_TCS_OFFCHIP_LAYOUT] = ctx->i32;
5628 num_params = SI_PARAM_TCS_OFFCHIP_LAYOUT+1;
5629
5630 if (shader->key.tes.as_es) {
5631 params[ctx->param_oc_lds = num_params++] = ctx->i32;
5632 params[ctx->param_tess_offchip = num_params++] = ctx->i32;
5633 params[ctx->param_es2gs_offset = num_params++] = ctx->i32;
5634 } else {
5635 params[ctx->param_tess_offchip = num_params++] = ctx->i32;
5636 declare_streamout_params(ctx, &shader->selector->so,
5637 params, ctx->i32, &num_params);
5638 params[ctx->param_oc_lds = num_params++] = ctx->i32;
5639 }
5640 last_sgpr = num_params - 1;
5641
5642 /* VGPRs */
5643 params[ctx->param_tes_u = num_params++] = ctx->f32;
5644 params[ctx->param_tes_v = num_params++] = ctx->f32;
5645 params[ctx->param_tes_rel_patch_id = num_params++] = ctx->i32;
5646 params[ctx->param_tes_patch_id = num_params++] = ctx->i32;
5647
5648 /* PrimitiveID output. */
5649 if (!ctx->is_monolithic && !shader->key.tes.as_es)
5650 for (i = 0; i <= VS_EPILOG_PRIMID_LOC; i++)
5651 returns[num_returns++] = ctx->f32;
5652 break;
5653
5654 case PIPE_SHADER_GEOMETRY:
5655 params[SI_PARAM_GS2VS_OFFSET] = ctx->i32;
5656 params[SI_PARAM_GS_WAVE_ID] = ctx->i32;
5657 last_sgpr = SI_PARAM_GS_WAVE_ID;
5658
5659 /* VGPRs */
5660 params[SI_PARAM_VTX0_OFFSET] = ctx->i32;
5661 params[SI_PARAM_VTX1_OFFSET] = ctx->i32;
5662 params[SI_PARAM_PRIMITIVE_ID] = ctx->i32;
5663 params[SI_PARAM_VTX2_OFFSET] = ctx->i32;
5664 params[SI_PARAM_VTX3_OFFSET] = ctx->i32;
5665 params[SI_PARAM_VTX4_OFFSET] = ctx->i32;
5666 params[SI_PARAM_VTX5_OFFSET] = ctx->i32;
5667 params[SI_PARAM_GS_INSTANCE_ID] = ctx->i32;
5668 num_params = SI_PARAM_GS_INSTANCE_ID+1;
5669 break;
5670
5671 case PIPE_SHADER_FRAGMENT:
5672 params[SI_PARAM_ALPHA_REF] = ctx->f32;
5673 params[SI_PARAM_PRIM_MASK] = ctx->i32;
5674 last_sgpr = SI_PARAM_PRIM_MASK;
5675 params[SI_PARAM_PERSP_SAMPLE] = ctx->v2i32;
5676 params[SI_PARAM_PERSP_CENTER] = ctx->v2i32;
5677 params[SI_PARAM_PERSP_CENTROID] = ctx->v2i32;
5678 params[SI_PARAM_PERSP_PULL_MODEL] = v3i32;
5679 params[SI_PARAM_LINEAR_SAMPLE] = ctx->v2i32;
5680 params[SI_PARAM_LINEAR_CENTER] = ctx->v2i32;
5681 params[SI_PARAM_LINEAR_CENTROID] = ctx->v2i32;
5682 params[SI_PARAM_LINE_STIPPLE_TEX] = ctx->f32;
5683 params[SI_PARAM_POS_X_FLOAT] = ctx->f32;
5684 params[SI_PARAM_POS_Y_FLOAT] = ctx->f32;
5685 params[SI_PARAM_POS_Z_FLOAT] = ctx->f32;
5686 params[SI_PARAM_POS_W_FLOAT] = ctx->f32;
5687 params[SI_PARAM_FRONT_FACE] = ctx->i32;
5688 params[SI_PARAM_ANCILLARY] = ctx->i32;
5689 params[SI_PARAM_SAMPLE_COVERAGE] = ctx->f32;
5690 params[SI_PARAM_POS_FIXED_PT] = ctx->i32;
5691 num_params = SI_PARAM_POS_FIXED_PT+1;
5692
5693 if (!ctx->is_monolithic) {
5694 /* Color inputs from the prolog. */
5695 if (shader->selector->info.colors_read) {
5696 unsigned num_color_elements =
5697 util_bitcount(shader->selector->info.colors_read);
5698
5699 assert(num_params + num_color_elements <= ARRAY_SIZE(params));
5700 for (i = 0; i < num_color_elements; i++)
5701 params[num_params++] = ctx->f32;
5702 }
5703
5704 /* Outputs for the epilog. */
5705 num_return_sgprs = SI_SGPR_ALPHA_REF + 1;
5706 num_returns =
5707 num_return_sgprs +
5708 util_bitcount(shader->selector->info.colors_written) * 4 +
5709 shader->selector->info.writes_z +
5710 shader->selector->info.writes_stencil +
5711 shader->selector->info.writes_samplemask +
5712 1 /* SampleMaskIn */;
5713
5714 num_returns = MAX2(num_returns,
5715 num_return_sgprs +
5716 PS_EPILOG_SAMPLEMASK_MIN_LOC + 1);
5717
5718 for (i = 0; i < num_return_sgprs; i++)
5719 returns[i] = ctx->i32;
5720 for (; i < num_returns; i++)
5721 returns[i] = ctx->f32;
5722 }
5723 break;
5724
5725 case PIPE_SHADER_COMPUTE:
5726 params[SI_PARAM_GRID_SIZE] = v3i32;
5727 params[SI_PARAM_BLOCK_ID] = v3i32;
5728 last_sgpr = SI_PARAM_BLOCK_ID;
5729
5730 params[SI_PARAM_THREAD_ID] = v3i32;
5731 num_params = SI_PARAM_THREAD_ID + 1;
5732 break;
5733 default:
5734 assert(0 && "unimplemented shader");
5735 return;
5736 }
5737
5738 assert(num_params <= ARRAY_SIZE(params));
5739
5740 si_create_function(ctx, returns, num_returns, params,
5741 num_params, last_sgpr);
5742
5743 /* Reserve register locations for VGPR inputs the PS prolog may need. */
5744 if (ctx->type == PIPE_SHADER_FRAGMENT &&
5745 !ctx->is_monolithic) {
5746 radeon_llvm_add_attribute(ctx->radeon_bld.main_fn,
5747 "InitialPSInputAddr",
5748 S_0286D0_PERSP_SAMPLE_ENA(1) |
5749 S_0286D0_PERSP_CENTER_ENA(1) |
5750 S_0286D0_PERSP_CENTROID_ENA(1) |
5751 S_0286D0_LINEAR_SAMPLE_ENA(1) |
5752 S_0286D0_LINEAR_CENTER_ENA(1) |
5753 S_0286D0_LINEAR_CENTROID_ENA(1) |
5754 S_0286D0_FRONT_FACE_ENA(1) |
5755 S_0286D0_POS_FIXED_PT_ENA(1));
5756 } else if (ctx->type == PIPE_SHADER_COMPUTE) {
5757 const unsigned *properties = shader->selector->info.properties;
5758 unsigned max_work_group_size =
5759 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] *
5760 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT] *
5761 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH];
5762
5763 assert(max_work_group_size);
5764
5765 radeon_llvm_add_attribute(ctx->radeon_bld.main_fn,
5766 "amdgpu-max-work-group-size",
5767 max_work_group_size);
5768 }
5769
5770 shader->info.num_input_sgprs = 0;
5771 shader->info.num_input_vgprs = 0;
5772
5773 for (i = 0; i <= last_sgpr; ++i)
5774 shader->info.num_input_sgprs += llvm_get_type_size(params[i]) / 4;
5775
5776 /* Unused fragment shader inputs are eliminated by the compiler,
5777 * so we don't know yet how many there will be.
5778 */
5779 if (ctx->type != PIPE_SHADER_FRAGMENT)
5780 for (; i < num_params; ++i)
5781 shader->info.num_input_vgprs += llvm_get_type_size(params[i]) / 4;
5782
5783 if (bld_base->info &&
5784 (bld_base->info->opcode_count[TGSI_OPCODE_DDX] > 0 ||
5785 bld_base->info->opcode_count[TGSI_OPCODE_DDY] > 0 ||
5786 bld_base->info->opcode_count[TGSI_OPCODE_DDX_FINE] > 0 ||
5787 bld_base->info->opcode_count[TGSI_OPCODE_DDY_FINE] > 0 ||
5788 bld_base->info->opcode_count[TGSI_OPCODE_INTERP_OFFSET] > 0 ||
5789 bld_base->info->opcode_count[TGSI_OPCODE_INTERP_SAMPLE] > 0))
5790 ctx->lds =
5791 LLVMAddGlobalInAddressSpace(gallivm->module,
5792 LLVMArrayType(ctx->i32, 64),
5793 "ddxy_lds",
5794 LOCAL_ADDR_SPACE);
5795
5796 if ((ctx->type == PIPE_SHADER_VERTEX && shader->key.vs.as_ls) ||
5797 ctx->type == PIPE_SHADER_TESS_CTRL ||
5798 ctx->type == PIPE_SHADER_TESS_EVAL)
5799 declare_tess_lds(ctx);
5800 }
5801
5802 /**
5803 * Load ESGS and GSVS ring buffer resource descriptors and save the variables
5804 * for later use.
5805 */
5806 static void preload_ring_buffers(struct si_shader_context *ctx)
5807 {
5808 struct gallivm_state *gallivm =
5809 ctx->radeon_bld.soa.bld_base.base.gallivm;
5810
5811 LLVMValueRef buf_ptr = LLVMGetParam(ctx->radeon_bld.main_fn,
5812 SI_PARAM_RW_BUFFERS);
5813
5814 if ((ctx->type == PIPE_SHADER_VERTEX &&
5815 ctx->shader->key.vs.as_es) ||
5816 (ctx->type == PIPE_SHADER_TESS_EVAL &&
5817 ctx->shader->key.tes.as_es) ||
5818 ctx->type == PIPE_SHADER_GEOMETRY) {
5819 unsigned ring =
5820 ctx->type == PIPE_SHADER_GEOMETRY ? SI_GS_RING_ESGS
5821 : SI_ES_RING_ESGS;
5822 LLVMValueRef offset = lp_build_const_int32(gallivm, ring);
5823
5824 ctx->esgs_ring =
5825 build_indexed_load_const(ctx, buf_ptr, offset);
5826 }
5827
5828 if (ctx->is_gs_copy_shader) {
5829 LLVMValueRef offset = lp_build_const_int32(gallivm, SI_VS_RING_GSVS);
5830
5831 ctx->gsvs_ring[0] =
5832 build_indexed_load_const(ctx, buf_ptr, offset);
5833 }
5834 if (ctx->type == PIPE_SHADER_GEOMETRY) {
5835 int i;
5836 for (i = 0; i < 4; i++) {
5837 LLVMValueRef offset = lp_build_const_int32(gallivm, SI_GS_RING_GSVS0 + i);
5838
5839 ctx->gsvs_ring[i] =
5840 build_indexed_load_const(ctx, buf_ptr, offset);
5841 }
5842 }
5843 }
5844
5845 static void si_llvm_emit_polygon_stipple(struct si_shader_context *ctx,
5846 LLVMValueRef param_rw_buffers,
5847 unsigned param_pos_fixed_pt)
5848 {
5849 struct lp_build_tgsi_context *bld_base =
5850 &ctx->radeon_bld.soa.bld_base;
5851 struct gallivm_state *gallivm = bld_base->base.gallivm;
5852 LLVMBuilderRef builder = gallivm->builder;
5853 LLVMValueRef slot, desc, offset, row, bit, address[2];
5854
5855 /* Use the fixed-point gl_FragCoord input.
5856 * Since the stipple pattern is 32x32 and it repeats, just get 5 bits
5857 * per coordinate to get the repeating effect.
5858 */
5859 address[0] = unpack_param(ctx, param_pos_fixed_pt, 0, 5);
5860 address[1] = unpack_param(ctx, param_pos_fixed_pt, 16, 5);
5861
5862 /* Load the buffer descriptor. */
5863 slot = lp_build_const_int32(gallivm, SI_PS_CONST_POLY_STIPPLE);
5864 desc = build_indexed_load_const(ctx, param_rw_buffers, slot);
5865
5866 /* The stipple pattern is 32x32, each row has 32 bits. */
5867 offset = LLVMBuildMul(builder, address[1],
5868 LLVMConstInt(ctx->i32, 4, 0), "");
5869 row = buffer_load_const(ctx, desc, offset);
5870 row = LLVMBuildBitCast(builder, row, ctx->i32, "");
5871 bit = LLVMBuildLShr(builder, row, address[0], "");
5872 bit = LLVMBuildTrunc(builder, bit, ctx->i1, "");
5873
5874 /* The intrinsic kills the thread if arg < 0. */
5875 bit = LLVMBuildSelect(builder, bit, LLVMConstReal(ctx->f32, 0),
5876 LLVMConstReal(ctx->f32, -1), "");
5877 lp_build_intrinsic(builder, "llvm.AMDGPU.kill", ctx->voidt, &bit, 1, 0);
5878 }
5879
5880 void si_shader_binary_read_config(struct radeon_shader_binary *binary,
5881 struct si_shader_config *conf,
5882 unsigned symbol_offset)
5883 {
5884 unsigned i;
5885 const unsigned char *config =
5886 radeon_shader_binary_config_start(binary, symbol_offset);
5887 bool really_needs_scratch = false;
5888
5889 /* LLVM adds SGPR spills to the scratch size.
5890 * Find out if we really need the scratch buffer.
5891 */
5892 for (i = 0; i < binary->reloc_count; i++) {
5893 const struct radeon_shader_reloc *reloc = &binary->relocs[i];
5894
5895 if (!strcmp(scratch_rsrc_dword0_symbol, reloc->name) ||
5896 !strcmp(scratch_rsrc_dword1_symbol, reloc->name)) {
5897 really_needs_scratch = true;
5898 break;
5899 }
5900 }
5901
5902 /* XXX: We may be able to emit some of these values directly rather than
5903 * extracting fields to be emitted later.
5904 */
5905
5906 for (i = 0; i < binary->config_size_per_symbol; i+= 8) {
5907 unsigned reg = util_le32_to_cpu(*(uint32_t*)(config + i));
5908 unsigned value = util_le32_to_cpu(*(uint32_t*)(config + i + 4));
5909 switch (reg) {
5910 case R_00B028_SPI_SHADER_PGM_RSRC1_PS:
5911 case R_00B128_SPI_SHADER_PGM_RSRC1_VS:
5912 case R_00B228_SPI_SHADER_PGM_RSRC1_GS:
5913 case R_00B848_COMPUTE_PGM_RSRC1:
5914 conf->num_sgprs = MAX2(conf->num_sgprs, (G_00B028_SGPRS(value) + 1) * 8);
5915 conf->num_vgprs = MAX2(conf->num_vgprs, (G_00B028_VGPRS(value) + 1) * 4);
5916 conf->float_mode = G_00B028_FLOAT_MODE(value);
5917 conf->rsrc1 = value;
5918 break;
5919 case R_00B02C_SPI_SHADER_PGM_RSRC2_PS:
5920 conf->lds_size = MAX2(conf->lds_size, G_00B02C_EXTRA_LDS_SIZE(value));
5921 break;
5922 case R_00B84C_COMPUTE_PGM_RSRC2:
5923 conf->lds_size = MAX2(conf->lds_size, G_00B84C_LDS_SIZE(value));
5924 conf->rsrc2 = value;
5925 break;
5926 case R_0286CC_SPI_PS_INPUT_ENA:
5927 conf->spi_ps_input_ena = value;
5928 break;
5929 case R_0286D0_SPI_PS_INPUT_ADDR:
5930 conf->spi_ps_input_addr = value;
5931 break;
5932 case R_0286E8_SPI_TMPRING_SIZE:
5933 case R_00B860_COMPUTE_TMPRING_SIZE:
5934 /* WAVESIZE is in units of 256 dwords. */
5935 if (really_needs_scratch)
5936 conf->scratch_bytes_per_wave =
5937 G_00B860_WAVESIZE(value) * 256 * 4;
5938 break;
5939 case 0x4: /* SPILLED_SGPRS */
5940 conf->spilled_sgprs = value;
5941 break;
5942 case 0x8: /* SPILLED_VGPRS */
5943 conf->spilled_vgprs = value;
5944 break;
5945 default:
5946 {
5947 static bool printed;
5948
5949 if (!printed) {
5950 fprintf(stderr, "Warning: LLVM emitted unknown "
5951 "config register: 0x%x\n", reg);
5952 printed = true;
5953 }
5954 }
5955 break;
5956 }
5957 }
5958
5959 if (!conf->spi_ps_input_addr)
5960 conf->spi_ps_input_addr = conf->spi_ps_input_ena;
5961 }
5962
5963 void si_shader_apply_scratch_relocs(struct si_context *sctx,
5964 struct si_shader *shader,
5965 struct si_shader_config *config,
5966 uint64_t scratch_va)
5967 {
5968 unsigned i;
5969 uint32_t scratch_rsrc_dword0 = scratch_va;
5970 uint32_t scratch_rsrc_dword1 =
5971 S_008F04_BASE_ADDRESS_HI(scratch_va >> 32);
5972
5973 /* Enable scratch coalescing if LLVM sets ELEMENT_SIZE & INDEX_STRIDE
5974 * correctly.
5975 */
5976 if (HAVE_LLVM >= 0x0309)
5977 scratch_rsrc_dword1 |= S_008F04_SWIZZLE_ENABLE(1);
5978 else
5979 scratch_rsrc_dword1 |=
5980 S_008F04_STRIDE(config->scratch_bytes_per_wave / 64);
5981
5982 for (i = 0 ; i < shader->binary.reloc_count; i++) {
5983 const struct radeon_shader_reloc *reloc =
5984 &shader->binary.relocs[i];
5985 if (!strcmp(scratch_rsrc_dword0_symbol, reloc->name)) {
5986 util_memcpy_cpu_to_le32(shader->binary.code + reloc->offset,
5987 &scratch_rsrc_dword0, 4);
5988 } else if (!strcmp(scratch_rsrc_dword1_symbol, reloc->name)) {
5989 util_memcpy_cpu_to_le32(shader->binary.code + reloc->offset,
5990 &scratch_rsrc_dword1, 4);
5991 }
5992 }
5993 }
5994
5995 static unsigned si_get_shader_binary_size(struct si_shader *shader)
5996 {
5997 unsigned size = shader->binary.code_size;
5998
5999 if (shader->prolog)
6000 size += shader->prolog->binary.code_size;
6001 if (shader->epilog)
6002 size += shader->epilog->binary.code_size;
6003 return size;
6004 }
6005
6006 int si_shader_binary_upload(struct si_screen *sscreen, struct si_shader *shader)
6007 {
6008 const struct radeon_shader_binary *prolog =
6009 shader->prolog ? &shader->prolog->binary : NULL;
6010 const struct radeon_shader_binary *epilog =
6011 shader->epilog ? &shader->epilog->binary : NULL;
6012 const struct radeon_shader_binary *mainb = &shader->binary;
6013 unsigned bo_size = si_get_shader_binary_size(shader) +
6014 (!epilog ? mainb->rodata_size : 0);
6015 unsigned char *ptr;
6016
6017 assert(!prolog || !prolog->rodata_size);
6018 assert((!prolog && !epilog) || !mainb->rodata_size);
6019 assert(!epilog || !epilog->rodata_size);
6020
6021 r600_resource_reference(&shader->bo, NULL);
6022 shader->bo = si_resource_create_custom(&sscreen->b.b,
6023 PIPE_USAGE_IMMUTABLE,
6024 bo_size);
6025 if (!shader->bo)
6026 return -ENOMEM;
6027
6028 /* Upload. */
6029 ptr = sscreen->b.ws->buffer_map(shader->bo->buf, NULL,
6030 PIPE_TRANSFER_READ_WRITE);
6031
6032 if (prolog) {
6033 util_memcpy_cpu_to_le32(ptr, prolog->code, prolog->code_size);
6034 ptr += prolog->code_size;
6035 }
6036
6037 util_memcpy_cpu_to_le32(ptr, mainb->code, mainb->code_size);
6038 ptr += mainb->code_size;
6039
6040 if (epilog)
6041 util_memcpy_cpu_to_le32(ptr, epilog->code, epilog->code_size);
6042 else if (mainb->rodata_size > 0)
6043 util_memcpy_cpu_to_le32(ptr, mainb->rodata, mainb->rodata_size);
6044
6045 sscreen->b.ws->buffer_unmap(shader->bo->buf);
6046 return 0;
6047 }
6048
6049 static void si_shader_dump_disassembly(const struct radeon_shader_binary *binary,
6050 struct pipe_debug_callback *debug,
6051 const char *name, FILE *file)
6052 {
6053 char *line, *p;
6054 unsigned i, count;
6055
6056 if (binary->disasm_string) {
6057 fprintf(file, "Shader %s disassembly:\n", name);
6058 fprintf(file, "%s", binary->disasm_string);
6059
6060 if (debug && debug->debug_message) {
6061 /* Very long debug messages are cut off, so send the
6062 * disassembly one line at a time. This causes more
6063 * overhead, but on the plus side it simplifies
6064 * parsing of resulting logs.
6065 */
6066 pipe_debug_message(debug, SHADER_INFO,
6067 "Shader Disassembly Begin");
6068
6069 line = binary->disasm_string;
6070 while (*line) {
6071 p = util_strchrnul(line, '\n');
6072 count = p - line;
6073
6074 if (count) {
6075 pipe_debug_message(debug, SHADER_INFO,
6076 "%.*s", count, line);
6077 }
6078
6079 if (!*p)
6080 break;
6081 line = p + 1;
6082 }
6083
6084 pipe_debug_message(debug, SHADER_INFO,
6085 "Shader Disassembly End");
6086 }
6087 } else {
6088 fprintf(file, "Shader %s binary:\n", name);
6089 for (i = 0; i < binary->code_size; i += 4) {
6090 fprintf(file, "@0x%x: %02x%02x%02x%02x\n", i,
6091 binary->code[i + 3], binary->code[i + 2],
6092 binary->code[i + 1], binary->code[i]);
6093 }
6094 }
6095 }
6096
6097 static void si_shader_dump_stats(struct si_screen *sscreen,
6098 struct si_shader_config *conf,
6099 unsigned num_inputs,
6100 unsigned code_size,
6101 struct pipe_debug_callback *debug,
6102 unsigned processor,
6103 FILE *file)
6104 {
6105 unsigned lds_increment = sscreen->b.chip_class >= CIK ? 512 : 256;
6106 unsigned lds_per_wave = 0;
6107 unsigned max_simd_waves = 10;
6108
6109 /* Compute LDS usage for PS. */
6110 if (processor == PIPE_SHADER_FRAGMENT) {
6111 /* The minimum usage per wave is (num_inputs * 48). The maximum
6112 * usage is (num_inputs * 48 * 16).
6113 * We can get anything in between and it varies between waves.
6114 *
6115 * The 48 bytes per input for a single primitive is equal to
6116 * 4 bytes/component * 4 components/input * 3 points.
6117 *
6118 * Other stages don't know the size at compile time or don't
6119 * allocate LDS per wave, but instead they do it per thread group.
6120 */
6121 lds_per_wave = conf->lds_size * lds_increment +
6122 align(num_inputs * 48, lds_increment);
6123 }
6124
6125 /* Compute the per-SIMD wave counts. */
6126 if (conf->num_sgprs) {
6127 if (sscreen->b.chip_class >= VI)
6128 max_simd_waves = MIN2(max_simd_waves, 800 / conf->num_sgprs);
6129 else
6130 max_simd_waves = MIN2(max_simd_waves, 512 / conf->num_sgprs);
6131 }
6132
6133 if (conf->num_vgprs)
6134 max_simd_waves = MIN2(max_simd_waves, 256 / conf->num_vgprs);
6135
6136 /* LDS is 64KB per CU (4 SIMDs), divided into 16KB blocks per SIMD
6137 * that PS can use.
6138 */
6139 if (lds_per_wave)
6140 max_simd_waves = MIN2(max_simd_waves, 16384 / lds_per_wave);
6141
6142 if (file != stderr ||
6143 r600_can_dump_shader(&sscreen->b, processor)) {
6144 if (processor == PIPE_SHADER_FRAGMENT) {
6145 fprintf(file, "*** SHADER CONFIG ***\n"
6146 "SPI_PS_INPUT_ADDR = 0x%04x\n"
6147 "SPI_PS_INPUT_ENA = 0x%04x\n",
6148 conf->spi_ps_input_addr, conf->spi_ps_input_ena);
6149 }
6150
6151 fprintf(file, "*** SHADER STATS ***\n"
6152 "SGPRS: %d\n"
6153 "VGPRS: %d\n"
6154 "Spilled SGPRs: %d\n"
6155 "Spilled VGPRs: %d\n"
6156 "Code Size: %d bytes\n"
6157 "LDS: %d blocks\n"
6158 "Scratch: %d bytes per wave\n"
6159 "Max Waves: %d\n"
6160 "********************\n\n\n",
6161 conf->num_sgprs, conf->num_vgprs,
6162 conf->spilled_sgprs, conf->spilled_vgprs, code_size,
6163 conf->lds_size, conf->scratch_bytes_per_wave,
6164 max_simd_waves);
6165 }
6166
6167 pipe_debug_message(debug, SHADER_INFO,
6168 "Shader Stats: SGPRS: %d VGPRS: %d Code Size: %d "
6169 "LDS: %d Scratch: %d Max Waves: %d Spilled SGPRs: %d "
6170 "Spilled VGPRs: %d",
6171 conf->num_sgprs, conf->num_vgprs, code_size,
6172 conf->lds_size, conf->scratch_bytes_per_wave,
6173 max_simd_waves, conf->spilled_sgprs,
6174 conf->spilled_vgprs);
6175 }
6176
6177 static const char *si_get_shader_name(struct si_shader *shader,
6178 unsigned processor)
6179 {
6180 switch (processor) {
6181 case PIPE_SHADER_VERTEX:
6182 if (shader->key.vs.as_es)
6183 return "Vertex Shader as ES";
6184 else if (shader->key.vs.as_ls)
6185 return "Vertex Shader as LS";
6186 else
6187 return "Vertex Shader as VS";
6188 case PIPE_SHADER_TESS_CTRL:
6189 return "Tessellation Control Shader";
6190 case PIPE_SHADER_TESS_EVAL:
6191 if (shader->key.tes.as_es)
6192 return "Tessellation Evaluation Shader as ES";
6193 else
6194 return "Tessellation Evaluation Shader as VS";
6195 case PIPE_SHADER_GEOMETRY:
6196 if (shader->gs_copy_shader == NULL)
6197 return "GS Copy Shader as VS";
6198 else
6199 return "Geometry Shader";
6200 case PIPE_SHADER_FRAGMENT:
6201 return "Pixel Shader";
6202 case PIPE_SHADER_COMPUTE:
6203 return "Compute Shader";
6204 default:
6205 return "Unknown Shader";
6206 }
6207 }
6208
6209 void si_shader_dump(struct si_screen *sscreen, struct si_shader *shader,
6210 struct pipe_debug_callback *debug, unsigned processor,
6211 FILE *file)
6212 {
6213 if (file != stderr ||
6214 r600_can_dump_shader(&sscreen->b, processor))
6215 si_dump_shader_key(processor, &shader->key, file);
6216
6217 if (file != stderr && shader->binary.llvm_ir_string) {
6218 fprintf(file, "\n%s - main shader part - LLVM IR:\n\n",
6219 si_get_shader_name(shader, processor));
6220 fprintf(file, "%s\n", shader->binary.llvm_ir_string);
6221 }
6222
6223 if (file != stderr ||
6224 (r600_can_dump_shader(&sscreen->b, processor) &&
6225 !(sscreen->b.debug_flags & DBG_NO_ASM))) {
6226 fprintf(file, "\n%s:\n", si_get_shader_name(shader, processor));
6227
6228 if (shader->prolog)
6229 si_shader_dump_disassembly(&shader->prolog->binary,
6230 debug, "prolog", file);
6231
6232 si_shader_dump_disassembly(&shader->binary, debug, "main", file);
6233
6234 if (shader->epilog)
6235 si_shader_dump_disassembly(&shader->epilog->binary,
6236 debug, "epilog", file);
6237 fprintf(file, "\n");
6238 }
6239
6240 si_shader_dump_stats(sscreen, &shader->config,
6241 shader->selector ? shader->selector->info.num_inputs : 0,
6242 si_get_shader_binary_size(shader), debug, processor,
6243 file);
6244 }
6245
6246 int si_compile_llvm(struct si_screen *sscreen,
6247 struct radeon_shader_binary *binary,
6248 struct si_shader_config *conf,
6249 LLVMTargetMachineRef tm,
6250 LLVMModuleRef mod,
6251 struct pipe_debug_callback *debug,
6252 unsigned processor,
6253 const char *name)
6254 {
6255 int r = 0;
6256 unsigned count = p_atomic_inc_return(&sscreen->b.num_compilations);
6257
6258 if (r600_can_dump_shader(&sscreen->b, processor)) {
6259 fprintf(stderr, "radeonsi: Compiling shader %d\n", count);
6260
6261 if (!(sscreen->b.debug_flags & (DBG_NO_IR | DBG_PREOPT_IR))) {
6262 fprintf(stderr, "%s LLVM IR:\n\n", name);
6263 LLVMDumpModule(mod);
6264 fprintf(stderr, "\n");
6265 }
6266 }
6267
6268 if (sscreen->record_llvm_ir) {
6269 char *ir = LLVMPrintModuleToString(mod);
6270 binary->llvm_ir_string = strdup(ir);
6271 LLVMDisposeMessage(ir);
6272 }
6273
6274 if (!si_replace_shader(count, binary)) {
6275 r = radeon_llvm_compile(mod, binary, tm, debug);
6276 if (r)
6277 return r;
6278 }
6279
6280 si_shader_binary_read_config(binary, conf, 0);
6281
6282 /* Enable 64-bit and 16-bit denormals, because there is no performance
6283 * cost.
6284 *
6285 * If denormals are enabled, all floating-point output modifiers are
6286 * ignored.
6287 *
6288 * Don't enable denormals for 32-bit floats, because:
6289 * - Floating-point output modifiers would be ignored by the hw.
6290 * - Some opcodes don't support denormals, such as v_mad_f32. We would
6291 * have to stop using those.
6292 * - SI & CI would be very slow.
6293 */
6294 conf->float_mode |= V_00B028_FP_64_DENORMS;
6295
6296 FREE(binary->config);
6297 FREE(binary->global_symbol_offsets);
6298 binary->config = NULL;
6299 binary->global_symbol_offsets = NULL;
6300
6301 /* Some shaders can't have rodata because their binaries can be
6302 * concatenated.
6303 */
6304 if (binary->rodata_size &&
6305 (processor == PIPE_SHADER_VERTEX ||
6306 processor == PIPE_SHADER_TESS_CTRL ||
6307 processor == PIPE_SHADER_TESS_EVAL ||
6308 processor == PIPE_SHADER_FRAGMENT)) {
6309 fprintf(stderr, "radeonsi: The shader can't have rodata.");
6310 return -EINVAL;
6311 }
6312
6313 return r;
6314 }
6315
6316 static void si_llvm_build_ret(struct si_shader_context *ctx, LLVMValueRef ret)
6317 {
6318 if (LLVMGetTypeKind(LLVMTypeOf(ret)) == LLVMVoidTypeKind)
6319 LLVMBuildRetVoid(ctx->radeon_bld.gallivm.builder);
6320 else
6321 LLVMBuildRet(ctx->radeon_bld.gallivm.builder, ret);
6322 }
6323
6324 /* Generate code for the hardware VS shader stage to go with a geometry shader */
6325 static int si_generate_gs_copy_shader(struct si_screen *sscreen,
6326 struct si_shader_context *ctx,
6327 struct si_shader *gs,
6328 struct pipe_debug_callback *debug)
6329 {
6330 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
6331 struct lp_build_tgsi_context *bld_base = &ctx->radeon_bld.soa.bld_base;
6332 struct lp_build_context *uint = &bld_base->uint_bld;
6333 struct si_shader_output_values *outputs;
6334 struct tgsi_shader_info *gsinfo = &gs->selector->info;
6335 LLVMValueRef args[9];
6336 int i, r;
6337
6338 outputs = MALLOC(gsinfo->num_outputs * sizeof(outputs[0]));
6339
6340 si_init_shader_ctx(ctx, sscreen, ctx->shader, ctx->tm);
6341 ctx->type = PIPE_SHADER_VERTEX;
6342 ctx->is_gs_copy_shader = true;
6343
6344 create_meta_data(ctx);
6345 create_function(ctx);
6346 preload_ring_buffers(ctx);
6347
6348 args[0] = ctx->gsvs_ring[0];
6349 args[1] = lp_build_mul_imm(uint,
6350 LLVMGetParam(ctx->radeon_bld.main_fn,
6351 ctx->param_vertex_id),
6352 4);
6353 args[3] = uint->zero;
6354 args[4] = uint->one; /* OFFEN */
6355 args[5] = uint->zero; /* IDXEN */
6356 args[6] = uint->one; /* GLC */
6357 args[7] = uint->one; /* SLC */
6358 args[8] = uint->zero; /* TFE */
6359
6360 /* Fetch vertex data from GSVS ring */
6361 for (i = 0; i < gsinfo->num_outputs; ++i) {
6362 unsigned chan;
6363
6364 outputs[i].name = gsinfo->output_semantic_name[i];
6365 outputs[i].sid = gsinfo->output_semantic_index[i];
6366
6367 for (chan = 0; chan < 4; chan++) {
6368 args[2] = lp_build_const_int32(gallivm,
6369 (i * 4 + chan) *
6370 gs->selector->gs_max_out_vertices * 16 * 4);
6371
6372 outputs[i].values[chan] =
6373 LLVMBuildBitCast(gallivm->builder,
6374 lp_build_intrinsic(gallivm->builder,
6375 "llvm.SI.buffer.load.dword.i32.i32",
6376 ctx->i32, args, 9,
6377 LLVMReadOnlyAttribute),
6378 ctx->f32, "");
6379 }
6380 }
6381
6382 si_llvm_export_vs(bld_base, outputs, gsinfo->num_outputs);
6383
6384 LLVMBuildRetVoid(gallivm->builder);
6385
6386 /* Dump LLVM IR before any optimization passes */
6387 if (sscreen->b.debug_flags & DBG_PREOPT_IR &&
6388 r600_can_dump_shader(&sscreen->b, PIPE_SHADER_GEOMETRY))
6389 LLVMDumpModule(bld_base->base.gallivm->module);
6390
6391 radeon_llvm_finalize_module(&ctx->radeon_bld);
6392
6393 r = si_compile_llvm(sscreen, &ctx->shader->binary,
6394 &ctx->shader->config, ctx->tm,
6395 bld_base->base.gallivm->module,
6396 debug, PIPE_SHADER_GEOMETRY,
6397 "GS Copy Shader");
6398 if (!r) {
6399 if (r600_can_dump_shader(&sscreen->b, PIPE_SHADER_GEOMETRY))
6400 fprintf(stderr, "GS Copy Shader:\n");
6401 si_shader_dump(sscreen, ctx->shader, debug,
6402 PIPE_SHADER_GEOMETRY, stderr);
6403 r = si_shader_binary_upload(sscreen, ctx->shader);
6404 }
6405
6406 radeon_llvm_dispose(&ctx->radeon_bld);
6407
6408 FREE(outputs);
6409 return r;
6410 }
6411
6412 static void si_dump_shader_key(unsigned shader, union si_shader_key *key,
6413 FILE *f)
6414 {
6415 int i;
6416
6417 fprintf(f, "SHADER KEY\n");
6418
6419 switch (shader) {
6420 case PIPE_SHADER_VERTEX:
6421 fprintf(f, " instance_divisors = {");
6422 for (i = 0; i < ARRAY_SIZE(key->vs.prolog.instance_divisors); i++)
6423 fprintf(f, !i ? "%u" : ", %u",
6424 key->vs.prolog.instance_divisors[i]);
6425 fprintf(f, "}\n");
6426 fprintf(f, " as_es = %u\n", key->vs.as_es);
6427 fprintf(f, " as_ls = %u\n", key->vs.as_ls);
6428 fprintf(f, " export_prim_id = %u\n", key->vs.epilog.export_prim_id);
6429 break;
6430
6431 case PIPE_SHADER_TESS_CTRL:
6432 fprintf(f, " prim_mode = %u\n", key->tcs.epilog.prim_mode);
6433 break;
6434
6435 case PIPE_SHADER_TESS_EVAL:
6436 fprintf(f, " as_es = %u\n", key->tes.as_es);
6437 fprintf(f, " export_prim_id = %u\n", key->tes.epilog.export_prim_id);
6438 break;
6439
6440 case PIPE_SHADER_GEOMETRY:
6441 case PIPE_SHADER_COMPUTE:
6442 break;
6443
6444 case PIPE_SHADER_FRAGMENT:
6445 fprintf(f, " prolog.color_two_side = %u\n", key->ps.prolog.color_two_side);
6446 fprintf(f, " prolog.flatshade_colors = %u\n", key->ps.prolog.flatshade_colors);
6447 fprintf(f, " prolog.poly_stipple = %u\n", key->ps.prolog.poly_stipple);
6448 fprintf(f, " prolog.force_persp_sample_interp = %u\n", key->ps.prolog.force_persp_sample_interp);
6449 fprintf(f, " prolog.force_linear_sample_interp = %u\n", key->ps.prolog.force_linear_sample_interp);
6450 fprintf(f, " prolog.force_persp_center_interp = %u\n", key->ps.prolog.force_persp_center_interp);
6451 fprintf(f, " prolog.force_linear_center_interp = %u\n", key->ps.prolog.force_linear_center_interp);
6452 fprintf(f, " prolog.bc_optimize_for_persp = %u\n", key->ps.prolog.bc_optimize_for_persp);
6453 fprintf(f, " prolog.bc_optimize_for_linear = %u\n", key->ps.prolog.bc_optimize_for_linear);
6454 fprintf(f, " epilog.spi_shader_col_format = 0x%x\n", key->ps.epilog.spi_shader_col_format);
6455 fprintf(f, " epilog.color_is_int8 = 0x%X\n", key->ps.epilog.color_is_int8);
6456 fprintf(f, " epilog.last_cbuf = %u\n", key->ps.epilog.last_cbuf);
6457 fprintf(f, " epilog.alpha_func = %u\n", key->ps.epilog.alpha_func);
6458 fprintf(f, " epilog.alpha_to_one = %u\n", key->ps.epilog.alpha_to_one);
6459 fprintf(f, " epilog.poly_line_smoothing = %u\n", key->ps.epilog.poly_line_smoothing);
6460 fprintf(f, " epilog.clamp_color = %u\n", key->ps.epilog.clamp_color);
6461 break;
6462
6463 default:
6464 assert(0);
6465 }
6466 }
6467
6468 static void si_init_shader_ctx(struct si_shader_context *ctx,
6469 struct si_screen *sscreen,
6470 struct si_shader *shader,
6471 LLVMTargetMachineRef tm)
6472 {
6473 struct lp_build_tgsi_context *bld_base;
6474 struct lp_build_tgsi_action tmpl = {};
6475
6476 memset(ctx, 0, sizeof(*ctx));
6477 radeon_llvm_context_init(
6478 &ctx->radeon_bld, "amdgcn--",
6479 (shader && shader->selector) ? &shader->selector->info : NULL,
6480 (shader && shader->selector) ? shader->selector->tokens : NULL);
6481 ctx->tm = tm;
6482 ctx->screen = sscreen;
6483 if (shader && shader->selector)
6484 ctx->type = shader->selector->info.processor;
6485 else
6486 ctx->type = -1;
6487 ctx->shader = shader;
6488
6489 ctx->voidt = LLVMVoidTypeInContext(ctx->radeon_bld.gallivm.context);
6490 ctx->i1 = LLVMInt1TypeInContext(ctx->radeon_bld.gallivm.context);
6491 ctx->i8 = LLVMInt8TypeInContext(ctx->radeon_bld.gallivm.context);
6492 ctx->i32 = LLVMInt32TypeInContext(ctx->radeon_bld.gallivm.context);
6493 ctx->i64 = LLVMInt64TypeInContext(ctx->radeon_bld.gallivm.context);
6494 ctx->i128 = LLVMIntTypeInContext(ctx->radeon_bld.gallivm.context, 128);
6495 ctx->f32 = LLVMFloatTypeInContext(ctx->radeon_bld.gallivm.context);
6496 ctx->v16i8 = LLVMVectorType(ctx->i8, 16);
6497 ctx->v2i32 = LLVMVectorType(ctx->i32, 2);
6498 ctx->v4i32 = LLVMVectorType(ctx->i32, 4);
6499 ctx->v4f32 = LLVMVectorType(ctx->f32, 4);
6500 ctx->v8i32 = LLVMVectorType(ctx->i32, 8);
6501
6502 bld_base = &ctx->radeon_bld.soa.bld_base;
6503 bld_base->emit_fetch_funcs[TGSI_FILE_CONSTANT] = fetch_constant;
6504
6505 bld_base->op_actions[TGSI_OPCODE_INTERP_CENTROID] = interp_action;
6506 bld_base->op_actions[TGSI_OPCODE_INTERP_SAMPLE] = interp_action;
6507 bld_base->op_actions[TGSI_OPCODE_INTERP_OFFSET] = interp_action;
6508
6509 bld_base->op_actions[TGSI_OPCODE_TEX] = tex_action;
6510 bld_base->op_actions[TGSI_OPCODE_TEX2] = tex_action;
6511 bld_base->op_actions[TGSI_OPCODE_TXB] = tex_action;
6512 bld_base->op_actions[TGSI_OPCODE_TXB2] = tex_action;
6513 bld_base->op_actions[TGSI_OPCODE_TXD] = tex_action;
6514 bld_base->op_actions[TGSI_OPCODE_TXF] = tex_action;
6515 bld_base->op_actions[TGSI_OPCODE_TXL] = tex_action;
6516 bld_base->op_actions[TGSI_OPCODE_TXL2] = tex_action;
6517 bld_base->op_actions[TGSI_OPCODE_TXP] = tex_action;
6518 bld_base->op_actions[TGSI_OPCODE_TXQ].fetch_args = txq_fetch_args;
6519 bld_base->op_actions[TGSI_OPCODE_TXQ].emit = txq_emit;
6520 bld_base->op_actions[TGSI_OPCODE_TG4] = tex_action;
6521 bld_base->op_actions[TGSI_OPCODE_LODQ] = tex_action;
6522 bld_base->op_actions[TGSI_OPCODE_TXQS].emit = si_llvm_emit_txqs;
6523
6524 bld_base->op_actions[TGSI_OPCODE_LOAD].fetch_args = load_fetch_args;
6525 bld_base->op_actions[TGSI_OPCODE_LOAD].emit = load_emit;
6526 bld_base->op_actions[TGSI_OPCODE_STORE].fetch_args = store_fetch_args;
6527 bld_base->op_actions[TGSI_OPCODE_STORE].emit = store_emit;
6528 bld_base->op_actions[TGSI_OPCODE_RESQ].fetch_args = resq_fetch_args;
6529 bld_base->op_actions[TGSI_OPCODE_RESQ].emit = resq_emit;
6530
6531 tmpl.fetch_args = atomic_fetch_args;
6532 tmpl.emit = atomic_emit;
6533 bld_base->op_actions[TGSI_OPCODE_ATOMUADD] = tmpl;
6534 bld_base->op_actions[TGSI_OPCODE_ATOMUADD].intr_name = "add";
6535 bld_base->op_actions[TGSI_OPCODE_ATOMXCHG] = tmpl;
6536 bld_base->op_actions[TGSI_OPCODE_ATOMXCHG].intr_name = "swap";
6537 bld_base->op_actions[TGSI_OPCODE_ATOMCAS] = tmpl;
6538 bld_base->op_actions[TGSI_OPCODE_ATOMCAS].intr_name = "cmpswap";
6539 bld_base->op_actions[TGSI_OPCODE_ATOMAND] = tmpl;
6540 bld_base->op_actions[TGSI_OPCODE_ATOMAND].intr_name = "and";
6541 bld_base->op_actions[TGSI_OPCODE_ATOMOR] = tmpl;
6542 bld_base->op_actions[TGSI_OPCODE_ATOMOR].intr_name = "or";
6543 bld_base->op_actions[TGSI_OPCODE_ATOMXOR] = tmpl;
6544 bld_base->op_actions[TGSI_OPCODE_ATOMXOR].intr_name = "xor";
6545 bld_base->op_actions[TGSI_OPCODE_ATOMUMIN] = tmpl;
6546 bld_base->op_actions[TGSI_OPCODE_ATOMUMIN].intr_name = "umin";
6547 bld_base->op_actions[TGSI_OPCODE_ATOMUMAX] = tmpl;
6548 bld_base->op_actions[TGSI_OPCODE_ATOMUMAX].intr_name = "umax";
6549 bld_base->op_actions[TGSI_OPCODE_ATOMIMIN] = tmpl;
6550 bld_base->op_actions[TGSI_OPCODE_ATOMIMIN].intr_name = "smin";
6551 bld_base->op_actions[TGSI_OPCODE_ATOMIMAX] = tmpl;
6552 bld_base->op_actions[TGSI_OPCODE_ATOMIMAX].intr_name = "smax";
6553
6554 bld_base->op_actions[TGSI_OPCODE_MEMBAR].emit = membar_emit;
6555
6556 bld_base->op_actions[TGSI_OPCODE_DDX].emit = si_llvm_emit_ddxy;
6557 bld_base->op_actions[TGSI_OPCODE_DDY].emit = si_llvm_emit_ddxy;
6558 bld_base->op_actions[TGSI_OPCODE_DDX_FINE].emit = si_llvm_emit_ddxy;
6559 bld_base->op_actions[TGSI_OPCODE_DDY_FINE].emit = si_llvm_emit_ddxy;
6560
6561 bld_base->op_actions[TGSI_OPCODE_EMIT].emit = si_llvm_emit_vertex;
6562 bld_base->op_actions[TGSI_OPCODE_ENDPRIM].emit = si_llvm_emit_primitive;
6563 bld_base->op_actions[TGSI_OPCODE_BARRIER].emit = si_llvm_emit_barrier;
6564
6565 bld_base->op_actions[TGSI_OPCODE_MAX].emit = build_tgsi_intrinsic_nomem;
6566 bld_base->op_actions[TGSI_OPCODE_MAX].intr_name = "llvm.maxnum.f32";
6567 bld_base->op_actions[TGSI_OPCODE_MIN].emit = build_tgsi_intrinsic_nomem;
6568 bld_base->op_actions[TGSI_OPCODE_MIN].intr_name = "llvm.minnum.f32";
6569 }
6570
6571 int si_compile_tgsi_shader(struct si_screen *sscreen,
6572 LLVMTargetMachineRef tm,
6573 struct si_shader *shader,
6574 bool is_monolithic,
6575 struct pipe_debug_callback *debug)
6576 {
6577 struct si_shader_selector *sel = shader->selector;
6578 struct si_shader_context ctx;
6579 struct lp_build_tgsi_context *bld_base;
6580 LLVMModuleRef mod;
6581 int r = 0;
6582
6583 /* Dump TGSI code before doing TGSI->LLVM conversion in case the
6584 * conversion fails. */
6585 if (r600_can_dump_shader(&sscreen->b, sel->info.processor) &&
6586 !(sscreen->b.debug_flags & DBG_NO_TGSI)) {
6587 tgsi_dump(sel->tokens, 0);
6588 si_dump_streamout(&sel->so);
6589 }
6590
6591 si_init_shader_ctx(&ctx, sscreen, shader, tm);
6592 ctx.is_monolithic = is_monolithic;
6593
6594 shader->info.uses_instanceid = sel->info.uses_instanceid;
6595
6596 bld_base = &ctx.radeon_bld.soa.bld_base;
6597 ctx.radeon_bld.load_system_value = declare_system_value;
6598
6599 switch (ctx.type) {
6600 case PIPE_SHADER_VERTEX:
6601 ctx.radeon_bld.load_input = declare_input_vs;
6602 if (shader->key.vs.as_ls)
6603 bld_base->emit_epilogue = si_llvm_emit_ls_epilogue;
6604 else if (shader->key.vs.as_es)
6605 bld_base->emit_epilogue = si_llvm_emit_es_epilogue;
6606 else
6607 bld_base->emit_epilogue = si_llvm_emit_vs_epilogue;
6608 break;
6609 case PIPE_SHADER_TESS_CTRL:
6610 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_tcs;
6611 bld_base->emit_fetch_funcs[TGSI_FILE_OUTPUT] = fetch_output_tcs;
6612 bld_base->emit_store = store_output_tcs;
6613 bld_base->emit_epilogue = si_llvm_emit_tcs_epilogue;
6614 break;
6615 case PIPE_SHADER_TESS_EVAL:
6616 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_tes;
6617 if (shader->key.tes.as_es)
6618 bld_base->emit_epilogue = si_llvm_emit_es_epilogue;
6619 else
6620 bld_base->emit_epilogue = si_llvm_emit_vs_epilogue;
6621 break;
6622 case PIPE_SHADER_GEOMETRY:
6623 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_gs;
6624 bld_base->emit_epilogue = si_llvm_emit_gs_epilogue;
6625 break;
6626 case PIPE_SHADER_FRAGMENT:
6627 ctx.radeon_bld.load_input = declare_input_fs;
6628 if (is_monolithic)
6629 bld_base->emit_epilogue = si_llvm_emit_fs_epilogue;
6630 else
6631 bld_base->emit_epilogue = si_llvm_return_fs_outputs;
6632 break;
6633 case PIPE_SHADER_COMPUTE:
6634 ctx.radeon_bld.declare_memory_region = declare_compute_memory;
6635 break;
6636 default:
6637 assert(!"Unsupported shader type");
6638 return -1;
6639 }
6640
6641 create_meta_data(&ctx);
6642 create_function(&ctx);
6643 preload_ring_buffers(&ctx);
6644
6645 if (ctx.is_monolithic && sel->type == PIPE_SHADER_FRAGMENT &&
6646 shader->key.ps.prolog.poly_stipple) {
6647 LLVMValueRef list = LLVMGetParam(ctx.radeon_bld.main_fn,
6648 SI_PARAM_RW_BUFFERS);
6649 si_llvm_emit_polygon_stipple(&ctx, list,
6650 SI_PARAM_POS_FIXED_PT);
6651 }
6652
6653 if (ctx.type == PIPE_SHADER_GEOMETRY) {
6654 int i;
6655 for (i = 0; i < 4; i++) {
6656 ctx.gs_next_vertex[i] =
6657 lp_build_alloca(bld_base->base.gallivm,
6658 ctx.i32, "");
6659 }
6660 }
6661
6662 if (!lp_build_tgsi_llvm(bld_base, sel->tokens)) {
6663 fprintf(stderr, "Failed to translate shader from TGSI to LLVM\n");
6664 goto out;
6665 }
6666
6667 si_llvm_build_ret(&ctx, ctx.return_value);
6668 mod = bld_base->base.gallivm->module;
6669
6670 /* Dump LLVM IR before any optimization passes */
6671 if (sscreen->b.debug_flags & DBG_PREOPT_IR &&
6672 r600_can_dump_shader(&sscreen->b, ctx.type))
6673 LLVMDumpModule(mod);
6674
6675 radeon_llvm_finalize_module(&ctx.radeon_bld);
6676
6677 r = si_compile_llvm(sscreen, &shader->binary, &shader->config, tm,
6678 mod, debug, ctx.type, "TGSI shader");
6679 if (r) {
6680 fprintf(stderr, "LLVM failed to compile shader\n");
6681 goto out;
6682 }
6683
6684 radeon_llvm_dispose(&ctx.radeon_bld);
6685
6686 /* Validate SGPR and VGPR usage for compute to detect compiler bugs.
6687 * LLVM 3.9svn has this bug.
6688 */
6689 if (sel->type == PIPE_SHADER_COMPUTE) {
6690 unsigned *props = sel->info.properties;
6691 unsigned wave_size = 64;
6692 unsigned max_vgprs = 256;
6693 unsigned max_sgprs = sscreen->b.chip_class >= VI ? 800 : 512;
6694 unsigned max_sgprs_per_wave = 128;
6695 unsigned min_waves_per_cu =
6696 DIV_ROUND_UP(props[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] *
6697 props[TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT] *
6698 props[TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH],
6699 wave_size);
6700 unsigned min_waves_per_simd = DIV_ROUND_UP(min_waves_per_cu, 4);
6701
6702 max_vgprs = max_vgprs / min_waves_per_simd;
6703 max_sgprs = MIN2(max_sgprs / min_waves_per_simd, max_sgprs_per_wave);
6704
6705 if (shader->config.num_sgprs > max_sgprs ||
6706 shader->config.num_vgprs > max_vgprs) {
6707 fprintf(stderr, "LLVM failed to compile a shader correctly: "
6708 "SGPR:VGPR usage is %u:%u, but the hw limit is %u:%u\n",
6709 shader->config.num_sgprs, shader->config.num_vgprs,
6710 max_sgprs, max_vgprs);
6711
6712 /* Just terminate the process, because dependent
6713 * shaders can hang due to bad input data, but use
6714 * the env var to allow shader-db to work.
6715 */
6716 if (!debug_get_bool_option("SI_PASS_BAD_SHADERS", false))
6717 abort();
6718 }
6719 }
6720
6721 /* Add the scratch offset to input SGPRs. */
6722 if (shader->config.scratch_bytes_per_wave)
6723 shader->info.num_input_sgprs += 1; /* scratch byte offset */
6724
6725 /* Calculate the number of fragment input VGPRs. */
6726 if (ctx.type == PIPE_SHADER_FRAGMENT) {
6727 shader->info.num_input_vgprs = 0;
6728 shader->info.face_vgpr_index = -1;
6729
6730 if (G_0286CC_PERSP_SAMPLE_ENA(shader->config.spi_ps_input_addr))
6731 shader->info.num_input_vgprs += 2;
6732 if (G_0286CC_PERSP_CENTER_ENA(shader->config.spi_ps_input_addr))
6733 shader->info.num_input_vgprs += 2;
6734 if (G_0286CC_PERSP_CENTROID_ENA(shader->config.spi_ps_input_addr))
6735 shader->info.num_input_vgprs += 2;
6736 if (G_0286CC_PERSP_PULL_MODEL_ENA(shader->config.spi_ps_input_addr))
6737 shader->info.num_input_vgprs += 3;
6738 if (G_0286CC_LINEAR_SAMPLE_ENA(shader->config.spi_ps_input_addr))
6739 shader->info.num_input_vgprs += 2;
6740 if (G_0286CC_LINEAR_CENTER_ENA(shader->config.spi_ps_input_addr))
6741 shader->info.num_input_vgprs += 2;
6742 if (G_0286CC_LINEAR_CENTROID_ENA(shader->config.spi_ps_input_addr))
6743 shader->info.num_input_vgprs += 2;
6744 if (G_0286CC_LINE_STIPPLE_TEX_ENA(shader->config.spi_ps_input_addr))
6745 shader->info.num_input_vgprs += 1;
6746 if (G_0286CC_POS_X_FLOAT_ENA(shader->config.spi_ps_input_addr))
6747 shader->info.num_input_vgprs += 1;
6748 if (G_0286CC_POS_Y_FLOAT_ENA(shader->config.spi_ps_input_addr))
6749 shader->info.num_input_vgprs += 1;
6750 if (G_0286CC_POS_Z_FLOAT_ENA(shader->config.spi_ps_input_addr))
6751 shader->info.num_input_vgprs += 1;
6752 if (G_0286CC_POS_W_FLOAT_ENA(shader->config.spi_ps_input_addr))
6753 shader->info.num_input_vgprs += 1;
6754 if (G_0286CC_FRONT_FACE_ENA(shader->config.spi_ps_input_addr)) {
6755 shader->info.face_vgpr_index = shader->info.num_input_vgprs;
6756 shader->info.num_input_vgprs += 1;
6757 }
6758 if (G_0286CC_ANCILLARY_ENA(shader->config.spi_ps_input_addr))
6759 shader->info.num_input_vgprs += 1;
6760 if (G_0286CC_SAMPLE_COVERAGE_ENA(shader->config.spi_ps_input_addr))
6761 shader->info.num_input_vgprs += 1;
6762 if (G_0286CC_POS_FIXED_PT_ENA(shader->config.spi_ps_input_addr))
6763 shader->info.num_input_vgprs += 1;
6764 }
6765
6766 if (ctx.type == PIPE_SHADER_GEOMETRY) {
6767 shader->gs_copy_shader = CALLOC_STRUCT(si_shader);
6768 shader->gs_copy_shader->selector = shader->selector;
6769 ctx.shader = shader->gs_copy_shader;
6770 if ((r = si_generate_gs_copy_shader(sscreen, &ctx,
6771 shader, debug))) {
6772 free(shader->gs_copy_shader);
6773 shader->gs_copy_shader = NULL;
6774 goto out;
6775 }
6776 }
6777
6778 out:
6779 return r;
6780 }
6781
6782 /**
6783 * Create, compile and return a shader part (prolog or epilog).
6784 *
6785 * \param sscreen screen
6786 * \param list list of shader parts of the same category
6787 * \param key shader part key
6788 * \param tm LLVM target machine
6789 * \param debug debug callback
6790 * \param compile the callback responsible for compilation
6791 * \return non-NULL on success
6792 */
6793 static struct si_shader_part *
6794 si_get_shader_part(struct si_screen *sscreen,
6795 struct si_shader_part **list,
6796 union si_shader_part_key *key,
6797 LLVMTargetMachineRef tm,
6798 struct pipe_debug_callback *debug,
6799 bool (*compile)(struct si_screen *,
6800 LLVMTargetMachineRef,
6801 struct pipe_debug_callback *,
6802 struct si_shader_part *))
6803 {
6804 struct si_shader_part *result;
6805
6806 pipe_mutex_lock(sscreen->shader_parts_mutex);
6807
6808 /* Find existing. */
6809 for (result = *list; result; result = result->next) {
6810 if (memcmp(&result->key, key, sizeof(*key)) == 0) {
6811 pipe_mutex_unlock(sscreen->shader_parts_mutex);
6812 return result;
6813 }
6814 }
6815
6816 /* Compile a new one. */
6817 result = CALLOC_STRUCT(si_shader_part);
6818 result->key = *key;
6819 if (!compile(sscreen, tm, debug, result)) {
6820 FREE(result);
6821 pipe_mutex_unlock(sscreen->shader_parts_mutex);
6822 return NULL;
6823 }
6824
6825 result->next = *list;
6826 *list = result;
6827 pipe_mutex_unlock(sscreen->shader_parts_mutex);
6828 return result;
6829 }
6830
6831 /**
6832 * Create a vertex shader prolog.
6833 *
6834 * The inputs are the same as VS (a lot of SGPRs and 4 VGPR system values).
6835 * All inputs are returned unmodified. The vertex load indices are
6836 * stored after them, which will used by the API VS for fetching inputs.
6837 *
6838 * For example, the expected outputs for instance_divisors[] = {0, 1, 2} are:
6839 * input_v0,
6840 * input_v1,
6841 * input_v2,
6842 * input_v3,
6843 * (VertexID + BaseVertex),
6844 * (InstanceID + StartInstance),
6845 * (InstanceID / 2 + StartInstance)
6846 */
6847 static bool si_compile_vs_prolog(struct si_screen *sscreen,
6848 LLVMTargetMachineRef tm,
6849 struct pipe_debug_callback *debug,
6850 struct si_shader_part *out)
6851 {
6852 union si_shader_part_key *key = &out->key;
6853 struct si_shader shader = {};
6854 struct si_shader_context ctx;
6855 struct gallivm_state *gallivm = &ctx.radeon_bld.gallivm;
6856 LLVMTypeRef *params, *returns;
6857 LLVMValueRef ret, func;
6858 int last_sgpr, num_params, num_returns, i;
6859 bool status = true;
6860
6861 si_init_shader_ctx(&ctx, sscreen, &shader, tm);
6862 ctx.type = PIPE_SHADER_VERTEX;
6863 ctx.param_vertex_id = key->vs_prolog.num_input_sgprs;
6864 ctx.param_instance_id = key->vs_prolog.num_input_sgprs + 3;
6865
6866 /* 4 preloaded VGPRs + vertex load indices as prolog outputs */
6867 params = alloca((key->vs_prolog.num_input_sgprs + 4) *
6868 sizeof(LLVMTypeRef));
6869 returns = alloca((key->vs_prolog.num_input_sgprs + 4 +
6870 key->vs_prolog.last_input + 1) *
6871 sizeof(LLVMTypeRef));
6872 num_params = 0;
6873 num_returns = 0;
6874
6875 /* Declare input and output SGPRs. */
6876 num_params = 0;
6877 for (i = 0; i < key->vs_prolog.num_input_sgprs; i++) {
6878 params[num_params++] = ctx.i32;
6879 returns[num_returns++] = ctx.i32;
6880 }
6881 last_sgpr = num_params - 1;
6882
6883 /* 4 preloaded VGPRs (outputs must be floats) */
6884 for (i = 0; i < 4; i++) {
6885 params[num_params++] = ctx.i32;
6886 returns[num_returns++] = ctx.f32;
6887 }
6888
6889 /* Vertex load indices. */
6890 for (i = 0; i <= key->vs_prolog.last_input; i++)
6891 returns[num_returns++] = ctx.f32;
6892
6893 /* Create the function. */
6894 si_create_function(&ctx, returns, num_returns, params,
6895 num_params, last_sgpr);
6896 func = ctx.radeon_bld.main_fn;
6897
6898 /* Copy inputs to outputs. This should be no-op, as the registers match,
6899 * but it will prevent the compiler from overwriting them unintentionally.
6900 */
6901 ret = ctx.return_value;
6902 for (i = 0; i < key->vs_prolog.num_input_sgprs; i++) {
6903 LLVMValueRef p = LLVMGetParam(func, i);
6904 ret = LLVMBuildInsertValue(gallivm->builder, ret, p, i, "");
6905 }
6906 for (i = num_params - 4; i < num_params; i++) {
6907 LLVMValueRef p = LLVMGetParam(func, i);
6908 p = LLVMBuildBitCast(gallivm->builder, p, ctx.f32, "");
6909 ret = LLVMBuildInsertValue(gallivm->builder, ret, p, i, "");
6910 }
6911
6912 /* Compute vertex load indices from instance divisors. */
6913 for (i = 0; i <= key->vs_prolog.last_input; i++) {
6914 unsigned divisor = key->vs_prolog.states.instance_divisors[i];
6915 LLVMValueRef index;
6916
6917 if (divisor) {
6918 /* InstanceID / Divisor + StartInstance */
6919 index = get_instance_index_for_fetch(&ctx.radeon_bld,
6920 SI_SGPR_START_INSTANCE,
6921 divisor);
6922 } else {
6923 /* VertexID + BaseVertex */
6924 index = LLVMBuildAdd(gallivm->builder,
6925 LLVMGetParam(func, ctx.param_vertex_id),
6926 LLVMGetParam(func, SI_SGPR_BASE_VERTEX), "");
6927 }
6928
6929 index = LLVMBuildBitCast(gallivm->builder, index, ctx.f32, "");
6930 ret = LLVMBuildInsertValue(gallivm->builder, ret, index,
6931 num_params++, "");
6932 }
6933
6934 /* Compile. */
6935 si_llvm_build_ret(&ctx, ret);
6936 radeon_llvm_finalize_module(&ctx.radeon_bld);
6937
6938 if (si_compile_llvm(sscreen, &out->binary, &out->config, tm,
6939 gallivm->module, debug, ctx.type,
6940 "Vertex Shader Prolog"))
6941 status = false;
6942
6943 radeon_llvm_dispose(&ctx.radeon_bld);
6944 return status;
6945 }
6946
6947 /**
6948 * Compile the vertex shader epilog. This is also used by the tessellation
6949 * evaluation shader compiled as VS.
6950 *
6951 * The input is PrimitiveID.
6952 *
6953 * If PrimitiveID is required by the pixel shader, export it.
6954 * Otherwise, do nothing.
6955 */
6956 static bool si_compile_vs_epilog(struct si_screen *sscreen,
6957 LLVMTargetMachineRef tm,
6958 struct pipe_debug_callback *debug,
6959 struct si_shader_part *out)
6960 {
6961 union si_shader_part_key *key = &out->key;
6962 struct si_shader_context ctx;
6963 struct gallivm_state *gallivm = &ctx.radeon_bld.gallivm;
6964 struct lp_build_tgsi_context *bld_base = &ctx.radeon_bld.soa.bld_base;
6965 LLVMTypeRef params[5];
6966 int num_params, i;
6967 bool status = true;
6968
6969 si_init_shader_ctx(&ctx, sscreen, NULL, tm);
6970 ctx.type = PIPE_SHADER_VERTEX;
6971
6972 /* Declare input VGPRs. */
6973 num_params = key->vs_epilog.states.export_prim_id ?
6974 (VS_EPILOG_PRIMID_LOC + 1) : 0;
6975 assert(num_params <= ARRAY_SIZE(params));
6976
6977 for (i = 0; i < num_params; i++)
6978 params[i] = ctx.f32;
6979
6980 /* Create the function. */
6981 si_create_function(&ctx, NULL, 0, params, num_params, -1);
6982
6983 /* Emit exports. */
6984 if (key->vs_epilog.states.export_prim_id) {
6985 struct lp_build_context *base = &bld_base->base;
6986 struct lp_build_context *uint = &bld_base->uint_bld;
6987 LLVMValueRef args[9];
6988
6989 args[0] = lp_build_const_int32(base->gallivm, 0x0); /* enabled channels */
6990 args[1] = uint->zero; /* whether the EXEC mask is valid */
6991 args[2] = uint->zero; /* DONE bit */
6992 args[3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_PARAM +
6993 key->vs_epilog.prim_id_param_offset);
6994 args[4] = uint->zero; /* COMPR flag (0 = 32-bit export) */
6995 args[5] = LLVMGetParam(ctx.radeon_bld.main_fn,
6996 VS_EPILOG_PRIMID_LOC); /* X */
6997 args[6] = uint->undef; /* Y */
6998 args[7] = uint->undef; /* Z */
6999 args[8] = uint->undef; /* W */
7000
7001 lp_build_intrinsic(base->gallivm->builder, "llvm.SI.export",
7002 LLVMVoidTypeInContext(base->gallivm->context),
7003 args, 9, 0);
7004 }
7005
7006 /* Compile. */
7007 LLVMBuildRetVoid(gallivm->builder);
7008 radeon_llvm_finalize_module(&ctx.radeon_bld);
7009
7010 if (si_compile_llvm(sscreen, &out->binary, &out->config, tm,
7011 gallivm->module, debug, ctx.type,
7012 "Vertex Shader Epilog"))
7013 status = false;
7014
7015 radeon_llvm_dispose(&ctx.radeon_bld);
7016 return status;
7017 }
7018
7019 /**
7020 * Create & compile a vertex shader epilog. This a helper used by VS and TES.
7021 */
7022 static bool si_get_vs_epilog(struct si_screen *sscreen,
7023 LLVMTargetMachineRef tm,
7024 struct si_shader *shader,
7025 struct pipe_debug_callback *debug,
7026 struct si_vs_epilog_bits *states)
7027 {
7028 union si_shader_part_key epilog_key;
7029
7030 memset(&epilog_key, 0, sizeof(epilog_key));
7031 epilog_key.vs_epilog.states = *states;
7032
7033 /* Set up the PrimitiveID output. */
7034 if (shader->key.vs.epilog.export_prim_id) {
7035 unsigned index = shader->selector->info.num_outputs;
7036 unsigned offset = shader->info.nr_param_exports++;
7037
7038 epilog_key.vs_epilog.prim_id_param_offset = offset;
7039 assert(index < ARRAY_SIZE(shader->info.vs_output_param_offset));
7040 shader->info.vs_output_param_offset[index] = offset;
7041 }
7042
7043 shader->epilog = si_get_shader_part(sscreen, &sscreen->vs_epilogs,
7044 &epilog_key, tm, debug,
7045 si_compile_vs_epilog);
7046 return shader->epilog != NULL;
7047 }
7048
7049 /**
7050 * Select and compile (or reuse) vertex shader parts (prolog & epilog).
7051 */
7052 static bool si_shader_select_vs_parts(struct si_screen *sscreen,
7053 LLVMTargetMachineRef tm,
7054 struct si_shader *shader,
7055 struct pipe_debug_callback *debug)
7056 {
7057 struct tgsi_shader_info *info = &shader->selector->info;
7058 union si_shader_part_key prolog_key;
7059 unsigned i;
7060
7061 /* Get the prolog. */
7062 memset(&prolog_key, 0, sizeof(prolog_key));
7063 prolog_key.vs_prolog.states = shader->key.vs.prolog;
7064 prolog_key.vs_prolog.num_input_sgprs = shader->info.num_input_sgprs;
7065 prolog_key.vs_prolog.last_input = MAX2(1, info->num_inputs) - 1;
7066
7067 /* The prolog is a no-op if there are no inputs. */
7068 if (info->num_inputs) {
7069 shader->prolog =
7070 si_get_shader_part(sscreen, &sscreen->vs_prologs,
7071 &prolog_key, tm, debug,
7072 si_compile_vs_prolog);
7073 if (!shader->prolog)
7074 return false;
7075 }
7076
7077 /* Get the epilog. */
7078 if (!shader->key.vs.as_es && !shader->key.vs.as_ls &&
7079 !si_get_vs_epilog(sscreen, tm, shader, debug,
7080 &shader->key.vs.epilog))
7081 return false;
7082
7083 /* Set the instanceID flag. */
7084 for (i = 0; i < info->num_inputs; i++)
7085 if (prolog_key.vs_prolog.states.instance_divisors[i])
7086 shader->info.uses_instanceid = true;
7087
7088 return true;
7089 }
7090
7091 /**
7092 * Select and compile (or reuse) TES parts (epilog).
7093 */
7094 static bool si_shader_select_tes_parts(struct si_screen *sscreen,
7095 LLVMTargetMachineRef tm,
7096 struct si_shader *shader,
7097 struct pipe_debug_callback *debug)
7098 {
7099 if (shader->key.tes.as_es)
7100 return true;
7101
7102 /* TES compiled as VS. */
7103 return si_get_vs_epilog(sscreen, tm, shader, debug,
7104 &shader->key.tes.epilog);
7105 }
7106
7107 /**
7108 * Compile the TCS epilog. This writes tesselation factors to memory based on
7109 * the output primitive type of the tesselator (determined by TES).
7110 */
7111 static bool si_compile_tcs_epilog(struct si_screen *sscreen,
7112 LLVMTargetMachineRef tm,
7113 struct pipe_debug_callback *debug,
7114 struct si_shader_part *out)
7115 {
7116 union si_shader_part_key *key = &out->key;
7117 struct si_shader shader = {};
7118 struct si_shader_context ctx;
7119 struct gallivm_state *gallivm = &ctx.radeon_bld.gallivm;
7120 struct lp_build_tgsi_context *bld_base = &ctx.radeon_bld.soa.bld_base;
7121 LLVMTypeRef params[16];
7122 LLVMValueRef func;
7123 int last_sgpr, num_params;
7124 bool status = true;
7125
7126 si_init_shader_ctx(&ctx, sscreen, &shader, tm);
7127 ctx.type = PIPE_SHADER_TESS_CTRL;
7128 shader.key.tcs.epilog = key->tcs_epilog.states;
7129
7130 /* Declare inputs. Only RW_BUFFERS and TESS_FACTOR_OFFSET are used. */
7131 params[SI_PARAM_RW_BUFFERS] = const_array(ctx.v16i8, SI_NUM_RW_BUFFERS);
7132 params[SI_PARAM_CONST_BUFFERS] = ctx.i64;
7133 params[SI_PARAM_SAMPLERS] = ctx.i64;
7134 params[SI_PARAM_IMAGES] = ctx.i64;
7135 params[SI_PARAM_SHADER_BUFFERS] = ctx.i64;
7136 params[SI_PARAM_TCS_OFFCHIP_LAYOUT] = ctx.i32;
7137 params[SI_PARAM_TCS_OUT_OFFSETS] = ctx.i32;
7138 params[SI_PARAM_TCS_OUT_LAYOUT] = ctx.i32;
7139 params[SI_PARAM_TCS_IN_LAYOUT] = ctx.i32;
7140 params[ctx.param_oc_lds = SI_PARAM_TCS_OC_LDS] = ctx.i32;
7141 params[SI_PARAM_TESS_FACTOR_OFFSET] = ctx.i32;
7142 last_sgpr = SI_PARAM_TESS_FACTOR_OFFSET;
7143 num_params = last_sgpr + 1;
7144
7145 params[num_params++] = ctx.i32; /* patch index within the wave (REL_PATCH_ID) */
7146 params[num_params++] = ctx.i32; /* invocation ID within the patch */
7147 params[num_params++] = ctx.i32; /* LDS offset where tess factors should be loaded from */
7148
7149 /* Create the function. */
7150 si_create_function(&ctx, NULL, 0, params, num_params, last_sgpr);
7151 declare_tess_lds(&ctx);
7152 func = ctx.radeon_bld.main_fn;
7153
7154 si_write_tess_factors(bld_base,
7155 LLVMGetParam(func, last_sgpr + 1),
7156 LLVMGetParam(func, last_sgpr + 2),
7157 LLVMGetParam(func, last_sgpr + 3));
7158
7159 /* Compile. */
7160 LLVMBuildRetVoid(gallivm->builder);
7161 radeon_llvm_finalize_module(&ctx.radeon_bld);
7162
7163 if (si_compile_llvm(sscreen, &out->binary, &out->config, tm,
7164 gallivm->module, debug, ctx.type,
7165 "Tessellation Control Shader Epilog"))
7166 status = false;
7167
7168 radeon_llvm_dispose(&ctx.radeon_bld);
7169 return status;
7170 }
7171
7172 /**
7173 * Select and compile (or reuse) TCS parts (epilog).
7174 */
7175 static bool si_shader_select_tcs_parts(struct si_screen *sscreen,
7176 LLVMTargetMachineRef tm,
7177 struct si_shader *shader,
7178 struct pipe_debug_callback *debug)
7179 {
7180 union si_shader_part_key epilog_key;
7181
7182 /* Get the epilog. */
7183 memset(&epilog_key, 0, sizeof(epilog_key));
7184 epilog_key.tcs_epilog.states = shader->key.tcs.epilog;
7185
7186 shader->epilog = si_get_shader_part(sscreen, &sscreen->tcs_epilogs,
7187 &epilog_key, tm, debug,
7188 si_compile_tcs_epilog);
7189 return shader->epilog != NULL;
7190 }
7191
7192 /**
7193 * Compile the pixel shader prolog. This handles:
7194 * - two-side color selection and interpolation
7195 * - overriding interpolation parameters for the API PS
7196 * - polygon stippling
7197 *
7198 * All preloaded SGPRs and VGPRs are passed through unmodified unless they are
7199 * overriden by other states. (e.g. per-sample interpolation)
7200 * Interpolated colors are stored after the preloaded VGPRs.
7201 */
7202 static bool si_compile_ps_prolog(struct si_screen *sscreen,
7203 LLVMTargetMachineRef tm,
7204 struct pipe_debug_callback *debug,
7205 struct si_shader_part *out)
7206 {
7207 union si_shader_part_key *key = &out->key;
7208 struct si_shader shader = {};
7209 struct si_shader_context ctx;
7210 struct gallivm_state *gallivm = &ctx.radeon_bld.gallivm;
7211 LLVMTypeRef *params;
7212 LLVMValueRef ret, func;
7213 int last_sgpr, num_params, num_returns, i, num_color_channels;
7214 bool status = true;
7215
7216 si_init_shader_ctx(&ctx, sscreen, &shader, tm);
7217 ctx.type = PIPE_SHADER_FRAGMENT;
7218 shader.key.ps.prolog = key->ps_prolog.states;
7219
7220 /* Number of inputs + 8 color elements. */
7221 params = alloca((key->ps_prolog.num_input_sgprs +
7222 key->ps_prolog.num_input_vgprs + 8) *
7223 sizeof(LLVMTypeRef));
7224
7225 /* Declare inputs. */
7226 num_params = 0;
7227 for (i = 0; i < key->ps_prolog.num_input_sgprs; i++)
7228 params[num_params++] = ctx.i32;
7229 last_sgpr = num_params - 1;
7230
7231 for (i = 0; i < key->ps_prolog.num_input_vgprs; i++)
7232 params[num_params++] = ctx.f32;
7233
7234 /* Declare outputs (same as inputs + add colors if needed) */
7235 num_returns = num_params;
7236 num_color_channels = util_bitcount(key->ps_prolog.colors_read);
7237 for (i = 0; i < num_color_channels; i++)
7238 params[num_returns++] = ctx.f32;
7239
7240 /* Create the function. */
7241 si_create_function(&ctx, params, num_returns, params,
7242 num_params, last_sgpr);
7243 func = ctx.radeon_bld.main_fn;
7244
7245 /* Copy inputs to outputs. This should be no-op, as the registers match,
7246 * but it will prevent the compiler from overwriting them unintentionally.
7247 */
7248 ret = ctx.return_value;
7249 for (i = 0; i < num_params; i++) {
7250 LLVMValueRef p = LLVMGetParam(func, i);
7251 ret = LLVMBuildInsertValue(gallivm->builder, ret, p, i, "");
7252 }
7253
7254 /* Polygon stippling. */
7255 if (key->ps_prolog.states.poly_stipple) {
7256 /* POS_FIXED_PT is always last. */
7257 unsigned pos = key->ps_prolog.num_input_sgprs +
7258 key->ps_prolog.num_input_vgprs - 1;
7259 LLVMValueRef ptr[2], list;
7260
7261 /* Get the pointer to rw buffers. */
7262 ptr[0] = LLVMGetParam(func, SI_SGPR_RW_BUFFERS);
7263 ptr[1] = LLVMGetParam(func, SI_SGPR_RW_BUFFERS_HI);
7264 list = lp_build_gather_values(gallivm, ptr, 2);
7265 list = LLVMBuildBitCast(gallivm->builder, list, ctx.i64, "");
7266 list = LLVMBuildIntToPtr(gallivm->builder, list,
7267 const_array(ctx.v16i8, SI_NUM_RW_BUFFERS), "");
7268
7269 si_llvm_emit_polygon_stipple(&ctx, list, pos);
7270 }
7271
7272 if (key->ps_prolog.states.bc_optimize_for_persp ||
7273 key->ps_prolog.states.bc_optimize_for_linear) {
7274 unsigned i, base = key->ps_prolog.num_input_sgprs;
7275 LLVMValueRef center[2], centroid[2], tmp, bc_optimize;
7276
7277 /* The shader should do: if (PRIM_MASK[31]) CENTROID = CENTER;
7278 * The hw doesn't compute CENTROID if the whole wave only
7279 * contains fully-covered quads.
7280 *
7281 * PRIM_MASK is after user SGPRs.
7282 */
7283 bc_optimize = LLVMGetParam(func, SI_PS_NUM_USER_SGPR);
7284 bc_optimize = LLVMBuildLShr(gallivm->builder, bc_optimize,
7285 LLVMConstInt(ctx.i32, 31, 0), "");
7286 bc_optimize = LLVMBuildTrunc(gallivm->builder, bc_optimize,
7287 ctx.i1, "");
7288
7289 if (key->ps_prolog.states.bc_optimize_for_persp) {
7290 /* Read PERSP_CENTER. */
7291 for (i = 0; i < 2; i++)
7292 center[i] = LLVMGetParam(func, base + 2 + i);
7293 /* Read PERSP_CENTROID. */
7294 for (i = 0; i < 2; i++)
7295 centroid[i] = LLVMGetParam(func, base + 4 + i);
7296 /* Select PERSP_CENTROID. */
7297 for (i = 0; i < 2; i++) {
7298 tmp = LLVMBuildSelect(gallivm->builder, bc_optimize,
7299 center[i], centroid[i], "");
7300 ret = LLVMBuildInsertValue(gallivm->builder, ret,
7301 tmp, base + 4 + i, "");
7302 }
7303 }
7304 if (key->ps_prolog.states.bc_optimize_for_linear) {
7305 /* Read LINEAR_CENTER. */
7306 for (i = 0; i < 2; i++)
7307 center[i] = LLVMGetParam(func, base + 8 + i);
7308 /* Read LINEAR_CENTROID. */
7309 for (i = 0; i < 2; i++)
7310 centroid[i] = LLVMGetParam(func, base + 10 + i);
7311 /* Select LINEAR_CENTROID. */
7312 for (i = 0; i < 2; i++) {
7313 tmp = LLVMBuildSelect(gallivm->builder, bc_optimize,
7314 center[i], centroid[i], "");
7315 ret = LLVMBuildInsertValue(gallivm->builder, ret,
7316 tmp, base + 10 + i, "");
7317 }
7318 }
7319 }
7320
7321 /* Interpolate colors. */
7322 for (i = 0; i < 2; i++) {
7323 unsigned writemask = (key->ps_prolog.colors_read >> (i * 4)) & 0xf;
7324 unsigned face_vgpr = key->ps_prolog.num_input_sgprs +
7325 key->ps_prolog.face_vgpr_index;
7326 LLVMValueRef interp[2], color[4];
7327 LLVMValueRef interp_ij = NULL, prim_mask = NULL, face = NULL;
7328
7329 if (!writemask)
7330 continue;
7331
7332 /* If the interpolation qualifier is not CONSTANT (-1). */
7333 if (key->ps_prolog.color_interp_vgpr_index[i] != -1) {
7334 unsigned interp_vgpr = key->ps_prolog.num_input_sgprs +
7335 key->ps_prolog.color_interp_vgpr_index[i];
7336
7337 /* Get the (i,j) updated by bc_optimize handling. */
7338 interp[0] = LLVMBuildExtractValue(gallivm->builder, ret,
7339 interp_vgpr, "");
7340 interp[1] = LLVMBuildExtractValue(gallivm->builder, ret,
7341 interp_vgpr + 1, "");
7342 interp_ij = lp_build_gather_values(gallivm, interp, 2);
7343 interp_ij = LLVMBuildBitCast(gallivm->builder, interp_ij,
7344 ctx.v2i32, "");
7345 }
7346
7347 /* Use the absolute location of the input. */
7348 prim_mask = LLVMGetParam(func, SI_PS_NUM_USER_SGPR);
7349
7350 if (key->ps_prolog.states.color_two_side) {
7351 face = LLVMGetParam(func, face_vgpr);
7352 face = LLVMBuildBitCast(gallivm->builder, face, ctx.i32, "");
7353 }
7354
7355 interp_fs_input(&ctx,
7356 key->ps_prolog.color_attr_index[i],
7357 TGSI_SEMANTIC_COLOR, i,
7358 key->ps_prolog.num_interp_inputs,
7359 key->ps_prolog.colors_read, interp_ij,
7360 prim_mask, face, color);
7361
7362 while (writemask) {
7363 unsigned chan = u_bit_scan(&writemask);
7364 ret = LLVMBuildInsertValue(gallivm->builder, ret, color[chan],
7365 num_params++, "");
7366 }
7367 }
7368
7369 /* Force per-sample interpolation. */
7370 if (key->ps_prolog.states.force_persp_sample_interp) {
7371 unsigned i, base = key->ps_prolog.num_input_sgprs;
7372 LLVMValueRef persp_sample[2];
7373
7374 /* Read PERSP_SAMPLE. */
7375 for (i = 0; i < 2; i++)
7376 persp_sample[i] = LLVMGetParam(func, base + i);
7377 /* Overwrite PERSP_CENTER. */
7378 for (i = 0; i < 2; i++)
7379 ret = LLVMBuildInsertValue(gallivm->builder, ret,
7380 persp_sample[i], base + 2 + i, "");
7381 /* Overwrite PERSP_CENTROID. */
7382 for (i = 0; i < 2; i++)
7383 ret = LLVMBuildInsertValue(gallivm->builder, ret,
7384 persp_sample[i], base + 4 + i, "");
7385 }
7386 if (key->ps_prolog.states.force_linear_sample_interp) {
7387 unsigned i, base = key->ps_prolog.num_input_sgprs;
7388 LLVMValueRef linear_sample[2];
7389
7390 /* Read LINEAR_SAMPLE. */
7391 for (i = 0; i < 2; i++)
7392 linear_sample[i] = LLVMGetParam(func, base + 6 + i);
7393 /* Overwrite LINEAR_CENTER. */
7394 for (i = 0; i < 2; i++)
7395 ret = LLVMBuildInsertValue(gallivm->builder, ret,
7396 linear_sample[i], base + 8 + i, "");
7397 /* Overwrite LINEAR_CENTROID. */
7398 for (i = 0; i < 2; i++)
7399 ret = LLVMBuildInsertValue(gallivm->builder, ret,
7400 linear_sample[i], base + 10 + i, "");
7401 }
7402
7403 /* Force center interpolation. */
7404 if (key->ps_prolog.states.force_persp_center_interp) {
7405 unsigned i, base = key->ps_prolog.num_input_sgprs;
7406 LLVMValueRef persp_center[2];
7407
7408 /* Read PERSP_CENTER. */
7409 for (i = 0; i < 2; i++)
7410 persp_center[i] = LLVMGetParam(func, base + 2 + i);
7411 /* Overwrite PERSP_SAMPLE. */
7412 for (i = 0; i < 2; i++)
7413 ret = LLVMBuildInsertValue(gallivm->builder, ret,
7414 persp_center[i], base + i, "");
7415 /* Overwrite PERSP_CENTROID. */
7416 for (i = 0; i < 2; i++)
7417 ret = LLVMBuildInsertValue(gallivm->builder, ret,
7418 persp_center[i], base + 4 + i, "");
7419 }
7420 if (key->ps_prolog.states.force_linear_center_interp) {
7421 unsigned i, base = key->ps_prolog.num_input_sgprs;
7422 LLVMValueRef linear_center[2];
7423
7424 /* Read LINEAR_CENTER. */
7425 for (i = 0; i < 2; i++)
7426 linear_center[i] = LLVMGetParam(func, base + 8 + i);
7427 /* Overwrite LINEAR_SAMPLE. */
7428 for (i = 0; i < 2; i++)
7429 ret = LLVMBuildInsertValue(gallivm->builder, ret,
7430 linear_center[i], base + 6 + i, "");
7431 /* Overwrite LINEAR_CENTROID. */
7432 for (i = 0; i < 2; i++)
7433 ret = LLVMBuildInsertValue(gallivm->builder, ret,
7434 linear_center[i], base + 10 + i, "");
7435 }
7436
7437 /* Tell LLVM to insert WQM instruction sequence when needed. */
7438 if (key->ps_prolog.wqm) {
7439 LLVMAddTargetDependentFunctionAttr(func,
7440 "amdgpu-ps-wqm-outputs", "");
7441 }
7442
7443 /* Compile. */
7444 si_llvm_build_ret(&ctx, ret);
7445 radeon_llvm_finalize_module(&ctx.radeon_bld);
7446
7447 if (si_compile_llvm(sscreen, &out->binary, &out->config, tm,
7448 gallivm->module, debug, ctx.type,
7449 "Fragment Shader Prolog"))
7450 status = false;
7451
7452 radeon_llvm_dispose(&ctx.radeon_bld);
7453 return status;
7454 }
7455
7456 /**
7457 * Compile the pixel shader epilog. This handles everything that must be
7458 * emulated for pixel shader exports. (alpha-test, format conversions, etc)
7459 */
7460 static bool si_compile_ps_epilog(struct si_screen *sscreen,
7461 LLVMTargetMachineRef tm,
7462 struct pipe_debug_callback *debug,
7463 struct si_shader_part *out)
7464 {
7465 union si_shader_part_key *key = &out->key;
7466 struct si_shader shader = {};
7467 struct si_shader_context ctx;
7468 struct gallivm_state *gallivm = &ctx.radeon_bld.gallivm;
7469 struct lp_build_tgsi_context *bld_base = &ctx.radeon_bld.soa.bld_base;
7470 LLVMTypeRef params[16+8*4+3];
7471 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
7472 int last_sgpr, num_params, i;
7473 bool status = true;
7474 struct si_ps_exports exp = {};
7475
7476 si_init_shader_ctx(&ctx, sscreen, &shader, tm);
7477 ctx.type = PIPE_SHADER_FRAGMENT;
7478 shader.key.ps.epilog = key->ps_epilog.states;
7479
7480 /* Declare input SGPRs. */
7481 params[SI_PARAM_RW_BUFFERS] = ctx.i64;
7482 params[SI_PARAM_CONST_BUFFERS] = ctx.i64;
7483 params[SI_PARAM_SAMPLERS] = ctx.i64;
7484 params[SI_PARAM_IMAGES] = ctx.i64;
7485 params[SI_PARAM_SHADER_BUFFERS] = ctx.i64;
7486 params[SI_PARAM_ALPHA_REF] = ctx.f32;
7487 last_sgpr = SI_PARAM_ALPHA_REF;
7488
7489 /* Declare input VGPRs. */
7490 num_params = (last_sgpr + 1) +
7491 util_bitcount(key->ps_epilog.colors_written) * 4 +
7492 key->ps_epilog.writes_z +
7493 key->ps_epilog.writes_stencil +
7494 key->ps_epilog.writes_samplemask;
7495
7496 num_params = MAX2(num_params,
7497 last_sgpr + 1 + PS_EPILOG_SAMPLEMASK_MIN_LOC + 1);
7498
7499 assert(num_params <= ARRAY_SIZE(params));
7500
7501 for (i = last_sgpr + 1; i < num_params; i++)
7502 params[i] = ctx.f32;
7503
7504 /* Create the function. */
7505 si_create_function(&ctx, NULL, 0, params, num_params, last_sgpr);
7506 /* Disable elimination of unused inputs. */
7507 radeon_llvm_add_attribute(ctx.radeon_bld.main_fn,
7508 "InitialPSInputAddr", 0xffffff);
7509
7510 /* Process colors. */
7511 unsigned vgpr = last_sgpr + 1;
7512 unsigned colors_written = key->ps_epilog.colors_written;
7513 int last_color_export = -1;
7514
7515 /* Find the last color export. */
7516 if (!key->ps_epilog.writes_z &&
7517 !key->ps_epilog.writes_stencil &&
7518 !key->ps_epilog.writes_samplemask) {
7519 unsigned spi_format = key->ps_epilog.states.spi_shader_col_format;
7520
7521 /* If last_cbuf > 0, FS_COLOR0_WRITES_ALL_CBUFS is true. */
7522 if (colors_written == 0x1 && key->ps_epilog.states.last_cbuf > 0) {
7523 /* Just set this if any of the colorbuffers are enabled. */
7524 if (spi_format &
7525 ((1llu << (4 * (key->ps_epilog.states.last_cbuf + 1))) - 1))
7526 last_color_export = 0;
7527 } else {
7528 for (i = 0; i < 8; i++)
7529 if (colors_written & (1 << i) &&
7530 (spi_format >> (i * 4)) & 0xf)
7531 last_color_export = i;
7532 }
7533 }
7534
7535 while (colors_written) {
7536 LLVMValueRef color[4];
7537 int mrt = u_bit_scan(&colors_written);
7538
7539 for (i = 0; i < 4; i++)
7540 color[i] = LLVMGetParam(ctx.radeon_bld.main_fn, vgpr++);
7541
7542 si_export_mrt_color(bld_base, color, mrt,
7543 num_params - 1,
7544 mrt == last_color_export, &exp);
7545 }
7546
7547 /* Process depth, stencil, samplemask. */
7548 if (key->ps_epilog.writes_z)
7549 depth = LLVMGetParam(ctx.radeon_bld.main_fn, vgpr++);
7550 if (key->ps_epilog.writes_stencil)
7551 stencil = LLVMGetParam(ctx.radeon_bld.main_fn, vgpr++);
7552 if (key->ps_epilog.writes_samplemask)
7553 samplemask = LLVMGetParam(ctx.radeon_bld.main_fn, vgpr++);
7554
7555 if (depth || stencil || samplemask)
7556 si_export_mrt_z(bld_base, depth, stencil, samplemask, &exp);
7557 else if (last_color_export == -1)
7558 si_export_null(bld_base);
7559
7560 if (exp.num)
7561 si_emit_ps_exports(&ctx, &exp);
7562
7563 /* Compile. */
7564 LLVMBuildRetVoid(gallivm->builder);
7565 radeon_llvm_finalize_module(&ctx.radeon_bld);
7566
7567 if (si_compile_llvm(sscreen, &out->binary, &out->config, tm,
7568 gallivm->module, debug, ctx.type,
7569 "Fragment Shader Epilog"))
7570 status = false;
7571
7572 radeon_llvm_dispose(&ctx.radeon_bld);
7573 return status;
7574 }
7575
7576 /**
7577 * Select and compile (or reuse) pixel shader parts (prolog & epilog).
7578 */
7579 static bool si_shader_select_ps_parts(struct si_screen *sscreen,
7580 LLVMTargetMachineRef tm,
7581 struct si_shader *shader,
7582 struct pipe_debug_callback *debug)
7583 {
7584 struct tgsi_shader_info *info = &shader->selector->info;
7585 union si_shader_part_key prolog_key;
7586 union si_shader_part_key epilog_key;
7587 unsigned i;
7588
7589 /* Get the prolog. */
7590 memset(&prolog_key, 0, sizeof(prolog_key));
7591 prolog_key.ps_prolog.states = shader->key.ps.prolog;
7592 prolog_key.ps_prolog.colors_read = info->colors_read;
7593 prolog_key.ps_prolog.num_input_sgprs = shader->info.num_input_sgprs;
7594 prolog_key.ps_prolog.num_input_vgprs = shader->info.num_input_vgprs;
7595 prolog_key.ps_prolog.wqm = info->uses_derivatives &&
7596 (prolog_key.ps_prolog.colors_read ||
7597 prolog_key.ps_prolog.states.force_persp_sample_interp ||
7598 prolog_key.ps_prolog.states.force_linear_sample_interp ||
7599 prolog_key.ps_prolog.states.force_persp_center_interp ||
7600 prolog_key.ps_prolog.states.force_linear_center_interp ||
7601 prolog_key.ps_prolog.states.bc_optimize_for_persp ||
7602 prolog_key.ps_prolog.states.bc_optimize_for_linear);
7603
7604 if (info->colors_read) {
7605 unsigned *color = shader->selector->color_attr_index;
7606
7607 if (shader->key.ps.prolog.color_two_side) {
7608 /* BCOLORs are stored after the last input. */
7609 prolog_key.ps_prolog.num_interp_inputs = info->num_inputs;
7610 prolog_key.ps_prolog.face_vgpr_index = shader->info.face_vgpr_index;
7611 shader->config.spi_ps_input_ena |= S_0286CC_FRONT_FACE_ENA(1);
7612 }
7613
7614 for (i = 0; i < 2; i++) {
7615 unsigned interp = info->input_interpolate[color[i]];
7616 unsigned location = info->input_interpolate_loc[color[i]];
7617
7618 if (!(info->colors_read & (0xf << i*4)))
7619 continue;
7620
7621 prolog_key.ps_prolog.color_attr_index[i] = color[i];
7622
7623 if (shader->key.ps.prolog.flatshade_colors &&
7624 interp == TGSI_INTERPOLATE_COLOR)
7625 interp = TGSI_INTERPOLATE_CONSTANT;
7626
7627 switch (interp) {
7628 case TGSI_INTERPOLATE_CONSTANT:
7629 prolog_key.ps_prolog.color_interp_vgpr_index[i] = -1;
7630 break;
7631 case TGSI_INTERPOLATE_PERSPECTIVE:
7632 case TGSI_INTERPOLATE_COLOR:
7633 /* Force the interpolation location for colors here. */
7634 if (shader->key.ps.prolog.force_persp_sample_interp)
7635 location = TGSI_INTERPOLATE_LOC_SAMPLE;
7636 if (shader->key.ps.prolog.force_persp_center_interp)
7637 location = TGSI_INTERPOLATE_LOC_CENTER;
7638
7639 switch (location) {
7640 case TGSI_INTERPOLATE_LOC_SAMPLE:
7641 prolog_key.ps_prolog.color_interp_vgpr_index[i] = 0;
7642 shader->config.spi_ps_input_ena |=
7643 S_0286CC_PERSP_SAMPLE_ENA(1);
7644 break;
7645 case TGSI_INTERPOLATE_LOC_CENTER:
7646 prolog_key.ps_prolog.color_interp_vgpr_index[i] = 2;
7647 shader->config.spi_ps_input_ena |=
7648 S_0286CC_PERSP_CENTER_ENA(1);
7649 break;
7650 case TGSI_INTERPOLATE_LOC_CENTROID:
7651 prolog_key.ps_prolog.color_interp_vgpr_index[i] = 4;
7652 shader->config.spi_ps_input_ena |=
7653 S_0286CC_PERSP_CENTROID_ENA(1);
7654 break;
7655 default:
7656 assert(0);
7657 }
7658 break;
7659 case TGSI_INTERPOLATE_LINEAR:
7660 /* Force the interpolation location for colors here. */
7661 if (shader->key.ps.prolog.force_linear_sample_interp)
7662 location = TGSI_INTERPOLATE_LOC_SAMPLE;
7663 if (shader->key.ps.prolog.force_linear_center_interp)
7664 location = TGSI_INTERPOLATE_LOC_CENTER;
7665
7666 switch (location) {
7667 case TGSI_INTERPOLATE_LOC_SAMPLE:
7668 prolog_key.ps_prolog.color_interp_vgpr_index[i] = 6;
7669 shader->config.spi_ps_input_ena |=
7670 S_0286CC_LINEAR_SAMPLE_ENA(1);
7671 break;
7672 case TGSI_INTERPOLATE_LOC_CENTER:
7673 prolog_key.ps_prolog.color_interp_vgpr_index[i] = 8;
7674 shader->config.spi_ps_input_ena |=
7675 S_0286CC_LINEAR_CENTER_ENA(1);
7676 break;
7677 case TGSI_INTERPOLATE_LOC_CENTROID:
7678 prolog_key.ps_prolog.color_interp_vgpr_index[i] = 10;
7679 shader->config.spi_ps_input_ena |=
7680 S_0286CC_LINEAR_CENTROID_ENA(1);
7681 break;
7682 default:
7683 assert(0);
7684 }
7685 break;
7686 default:
7687 assert(0);
7688 }
7689 }
7690 }
7691
7692 /* The prolog is a no-op if these aren't set. */
7693 if (prolog_key.ps_prolog.colors_read ||
7694 prolog_key.ps_prolog.states.force_persp_sample_interp ||
7695 prolog_key.ps_prolog.states.force_linear_sample_interp ||
7696 prolog_key.ps_prolog.states.force_persp_center_interp ||
7697 prolog_key.ps_prolog.states.force_linear_center_interp ||
7698 prolog_key.ps_prolog.states.bc_optimize_for_persp ||
7699 prolog_key.ps_prolog.states.bc_optimize_for_linear ||
7700 prolog_key.ps_prolog.states.poly_stipple) {
7701 shader->prolog =
7702 si_get_shader_part(sscreen, &sscreen->ps_prologs,
7703 &prolog_key, tm, debug,
7704 si_compile_ps_prolog);
7705 if (!shader->prolog)
7706 return false;
7707 }
7708
7709 /* Get the epilog. */
7710 memset(&epilog_key, 0, sizeof(epilog_key));
7711 epilog_key.ps_epilog.colors_written = info->colors_written;
7712 epilog_key.ps_epilog.writes_z = info->writes_z;
7713 epilog_key.ps_epilog.writes_stencil = info->writes_stencil;
7714 epilog_key.ps_epilog.writes_samplemask = info->writes_samplemask;
7715 epilog_key.ps_epilog.states = shader->key.ps.epilog;
7716
7717 shader->epilog =
7718 si_get_shader_part(sscreen, &sscreen->ps_epilogs,
7719 &epilog_key, tm, debug,
7720 si_compile_ps_epilog);
7721 if (!shader->epilog)
7722 return false;
7723
7724 /* Enable POS_FIXED_PT if polygon stippling is enabled. */
7725 if (shader->key.ps.prolog.poly_stipple) {
7726 shader->config.spi_ps_input_ena |= S_0286CC_POS_FIXED_PT_ENA(1);
7727 assert(G_0286CC_POS_FIXED_PT_ENA(shader->config.spi_ps_input_addr));
7728 }
7729
7730 /* Set up the enable bits for per-sample shading if needed. */
7731 if (shader->key.ps.prolog.force_persp_sample_interp &&
7732 (G_0286CC_PERSP_CENTER_ENA(shader->config.spi_ps_input_ena) ||
7733 G_0286CC_PERSP_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
7734 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_CENTER_ENA;
7735 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_CENTROID_ENA;
7736 shader->config.spi_ps_input_ena |= S_0286CC_PERSP_SAMPLE_ENA(1);
7737 }
7738 if (shader->key.ps.prolog.force_linear_sample_interp &&
7739 (G_0286CC_LINEAR_CENTER_ENA(shader->config.spi_ps_input_ena) ||
7740 G_0286CC_LINEAR_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
7741 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_CENTER_ENA;
7742 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_CENTROID_ENA;
7743 shader->config.spi_ps_input_ena |= S_0286CC_LINEAR_SAMPLE_ENA(1);
7744 }
7745 if (shader->key.ps.prolog.force_persp_center_interp &&
7746 (G_0286CC_PERSP_SAMPLE_ENA(shader->config.spi_ps_input_ena) ||
7747 G_0286CC_PERSP_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
7748 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_SAMPLE_ENA;
7749 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_CENTROID_ENA;
7750 shader->config.spi_ps_input_ena |= S_0286CC_PERSP_CENTER_ENA(1);
7751 }
7752 if (shader->key.ps.prolog.force_linear_center_interp &&
7753 (G_0286CC_LINEAR_SAMPLE_ENA(shader->config.spi_ps_input_ena) ||
7754 G_0286CC_LINEAR_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
7755 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_SAMPLE_ENA;
7756 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_CENTROID_ENA;
7757 shader->config.spi_ps_input_ena |= S_0286CC_LINEAR_CENTER_ENA(1);
7758 }
7759
7760 /* POW_W_FLOAT requires that one of the perspective weights is enabled. */
7761 if (G_0286CC_POS_W_FLOAT_ENA(shader->config.spi_ps_input_ena) &&
7762 !(shader->config.spi_ps_input_ena & 0xf)) {
7763 shader->config.spi_ps_input_ena |= S_0286CC_PERSP_CENTER_ENA(1);
7764 assert(G_0286CC_PERSP_CENTER_ENA(shader->config.spi_ps_input_addr));
7765 }
7766
7767 /* At least one pair of interpolation weights must be enabled. */
7768 if (!(shader->config.spi_ps_input_ena & 0x7f)) {
7769 shader->config.spi_ps_input_ena |= S_0286CC_LINEAR_CENTER_ENA(1);
7770 assert(G_0286CC_LINEAR_CENTER_ENA(shader->config.spi_ps_input_addr));
7771 }
7772
7773 /* The sample mask input is always enabled, because the API shader always
7774 * passes it through to the epilog. Disable it here if it's unused.
7775 */
7776 if (!shader->key.ps.epilog.poly_line_smoothing &&
7777 !shader->selector->info.reads_samplemask)
7778 shader->config.spi_ps_input_ena &= C_0286CC_SAMPLE_COVERAGE_ENA;
7779
7780 return true;
7781 }
7782
7783 static void si_fix_num_sgprs(struct si_shader *shader)
7784 {
7785 unsigned min_sgprs = shader->info.num_input_sgprs + 2; /* VCC */
7786
7787 shader->config.num_sgprs = MAX2(shader->config.num_sgprs, min_sgprs);
7788 }
7789
7790 int si_shader_create(struct si_screen *sscreen, LLVMTargetMachineRef tm,
7791 struct si_shader *shader,
7792 struct pipe_debug_callback *debug)
7793 {
7794 struct si_shader *mainp = shader->selector->main_shader_part;
7795 int r;
7796
7797 /* LS, ES, VS are compiled on demand if the main part hasn't been
7798 * compiled for that stage.
7799 */
7800 if (!mainp ||
7801 (shader->selector->type == PIPE_SHADER_VERTEX &&
7802 (shader->key.vs.as_es != mainp->key.vs.as_es ||
7803 shader->key.vs.as_ls != mainp->key.vs.as_ls)) ||
7804 (shader->selector->type == PIPE_SHADER_TESS_EVAL &&
7805 shader->key.tes.as_es != mainp->key.tes.as_es) ||
7806 (shader->selector->type == PIPE_SHADER_TESS_CTRL &&
7807 shader->key.tcs.epilog.inputs_to_copy) ||
7808 shader->selector->type == PIPE_SHADER_COMPUTE) {
7809 /* Monolithic shader (compiled as a whole, has many variants,
7810 * may take a long time to compile).
7811 */
7812 r = si_compile_tgsi_shader(sscreen, tm, shader, true, debug);
7813 if (r)
7814 return r;
7815 } else {
7816 /* The shader consists of 2-3 parts:
7817 *
7818 * - the middle part is the user shader, it has 1 variant only
7819 * and it was compiled during the creation of the shader
7820 * selector
7821 * - the prolog part is inserted at the beginning
7822 * - the epilog part is inserted at the end
7823 *
7824 * The prolog and epilog have many (but simple) variants.
7825 */
7826
7827 /* Copy the compiled TGSI shader data over. */
7828 shader->is_binary_shared = true;
7829 shader->binary = mainp->binary;
7830 shader->config = mainp->config;
7831 shader->info.num_input_sgprs = mainp->info.num_input_sgprs;
7832 shader->info.num_input_vgprs = mainp->info.num_input_vgprs;
7833 shader->info.face_vgpr_index = mainp->info.face_vgpr_index;
7834 memcpy(shader->info.vs_output_param_offset,
7835 mainp->info.vs_output_param_offset,
7836 sizeof(mainp->info.vs_output_param_offset));
7837 shader->info.uses_instanceid = mainp->info.uses_instanceid;
7838 shader->info.nr_pos_exports = mainp->info.nr_pos_exports;
7839 shader->info.nr_param_exports = mainp->info.nr_param_exports;
7840
7841 /* Select prologs and/or epilogs. */
7842 switch (shader->selector->type) {
7843 case PIPE_SHADER_VERTEX:
7844 if (!si_shader_select_vs_parts(sscreen, tm, shader, debug))
7845 return -1;
7846 break;
7847 case PIPE_SHADER_TESS_CTRL:
7848 if (!si_shader_select_tcs_parts(sscreen, tm, shader, debug))
7849 return -1;
7850 break;
7851 case PIPE_SHADER_TESS_EVAL:
7852 if (!si_shader_select_tes_parts(sscreen, tm, shader, debug))
7853 return -1;
7854 break;
7855 case PIPE_SHADER_FRAGMENT:
7856 if (!si_shader_select_ps_parts(sscreen, tm, shader, debug))
7857 return -1;
7858
7859 /* Make sure we have at least as many VGPRs as there
7860 * are allocated inputs.
7861 */
7862 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
7863 shader->info.num_input_vgprs);
7864 break;
7865 }
7866
7867 /* Update SGPR and VGPR counts. */
7868 if (shader->prolog) {
7869 shader->config.num_sgprs = MAX2(shader->config.num_sgprs,
7870 shader->prolog->config.num_sgprs);
7871 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
7872 shader->prolog->config.num_vgprs);
7873 }
7874 if (shader->epilog) {
7875 shader->config.num_sgprs = MAX2(shader->config.num_sgprs,
7876 shader->epilog->config.num_sgprs);
7877 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
7878 shader->epilog->config.num_vgprs);
7879 }
7880 }
7881
7882 si_fix_num_sgprs(shader);
7883 si_shader_dump(sscreen, shader, debug, shader->selector->info.processor,
7884 stderr);
7885
7886 /* Upload. */
7887 r = si_shader_binary_upload(sscreen, shader);
7888 if (r) {
7889 fprintf(stderr, "LLVM failed to upload shader\n");
7890 return r;
7891 }
7892
7893 return 0;
7894 }
7895
7896 void si_shader_destroy(struct si_shader *shader)
7897 {
7898 if (shader->gs_copy_shader) {
7899 si_shader_destroy(shader->gs_copy_shader);
7900 FREE(shader->gs_copy_shader);
7901 }
7902
7903 if (shader->scratch_bo)
7904 r600_resource_reference(&shader->scratch_bo, NULL);
7905
7906 r600_resource_reference(&shader->bo, NULL);
7907
7908 if (!shader->is_binary_shared)
7909 radeon_shader_binary_clean(&shader->binary);
7910
7911 free(shader->shader_log);
7912 }