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radeonsi: load the right number of components for VS inputs and TBOs
[mesa.git] / src / gallium / drivers / radeonsi / si_shader.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23
24 #include "gallivm/lp_bld_const.h"
25 #include "gallivm/lp_bld_gather.h"
26 #include "gallivm/lp_bld_intr.h"
27 #include "gallivm/lp_bld_logic.h"
28 #include "gallivm/lp_bld_arit.h"
29 #include "gallivm/lp_bld_flow.h"
30 #include "gallivm/lp_bld_misc.h"
31 #include "util/u_memory.h"
32 #include "util/u_string.h"
33 #include "tgsi/tgsi_build.h"
34 #include "tgsi/tgsi_util.h"
35 #include "tgsi/tgsi_dump.h"
36
37 #include "ac_binary.h"
38 #include "ac_llvm_util.h"
39 #include "ac_exp_param.h"
40 #include "ac_shader_util.h"
41 #include "si_shader_internal.h"
42 #include "si_pipe.h"
43 #include "sid.h"
44
45 #include "compiler/nir/nir.h"
46
47 static const char *scratch_rsrc_dword0_symbol =
48 "SCRATCH_RSRC_DWORD0";
49
50 static const char *scratch_rsrc_dword1_symbol =
51 "SCRATCH_RSRC_DWORD1";
52
53 struct si_shader_output_values
54 {
55 LLVMValueRef values[4];
56 unsigned semantic_name;
57 unsigned semantic_index;
58 ubyte vertex_stream[4];
59 };
60
61 /**
62 * Used to collect types and other info about arguments of the LLVM function
63 * before the function is created.
64 */
65 struct si_function_info {
66 LLVMTypeRef types[100];
67 LLVMValueRef *assign[100];
68 unsigned num_sgpr_params;
69 unsigned num_params;
70 };
71
72 enum si_arg_regfile {
73 ARG_SGPR,
74 ARG_VGPR
75 };
76
77 static void si_init_shader_ctx(struct si_shader_context *ctx,
78 struct si_screen *sscreen,
79 LLVMTargetMachineRef tm);
80
81 static void si_llvm_emit_barrier(const struct lp_build_tgsi_action *action,
82 struct lp_build_tgsi_context *bld_base,
83 struct lp_build_emit_data *emit_data);
84
85 static void si_dump_shader_key(unsigned processor, const struct si_shader *shader,
86 FILE *f);
87
88 static void si_build_vs_prolog_function(struct si_shader_context *ctx,
89 union si_shader_part_key *key);
90 static void si_build_tcs_epilog_function(struct si_shader_context *ctx,
91 union si_shader_part_key *key);
92 static void si_build_ps_prolog_function(struct si_shader_context *ctx,
93 union si_shader_part_key *key);
94 static void si_build_ps_epilog_function(struct si_shader_context *ctx,
95 union si_shader_part_key *key);
96
97 /* Ideally pass the sample mask input to the PS epilog as v14, which
98 * is its usual location, so that the shader doesn't have to add v_mov.
99 */
100 #define PS_EPILOG_SAMPLEMASK_MIN_LOC 14
101
102 static bool llvm_type_is_64bit(struct si_shader_context *ctx,
103 LLVMTypeRef type)
104 {
105 if (type == ctx->ac.i64 || type == ctx->ac.f64)
106 return true;
107
108 return false;
109 }
110
111 static bool is_merged_shader(struct si_shader *shader)
112 {
113 if (shader->selector->screen->info.chip_class <= VI)
114 return false;
115
116 return shader->key.as_ls ||
117 shader->key.as_es ||
118 shader->selector->type == PIPE_SHADER_TESS_CTRL ||
119 shader->selector->type == PIPE_SHADER_GEOMETRY;
120 }
121
122 static void si_init_function_info(struct si_function_info *fninfo)
123 {
124 fninfo->num_params = 0;
125 fninfo->num_sgpr_params = 0;
126 }
127
128 static unsigned add_arg_assign(struct si_function_info *fninfo,
129 enum si_arg_regfile regfile, LLVMTypeRef type,
130 LLVMValueRef *assign)
131 {
132 assert(regfile != ARG_SGPR || fninfo->num_sgpr_params == fninfo->num_params);
133
134 unsigned idx = fninfo->num_params++;
135 assert(idx < ARRAY_SIZE(fninfo->types));
136
137 if (regfile == ARG_SGPR)
138 fninfo->num_sgpr_params = fninfo->num_params;
139
140 fninfo->types[idx] = type;
141 fninfo->assign[idx] = assign;
142 return idx;
143 }
144
145 static unsigned add_arg(struct si_function_info *fninfo,
146 enum si_arg_regfile regfile, LLVMTypeRef type)
147 {
148 return add_arg_assign(fninfo, regfile, type, NULL);
149 }
150
151 static void add_arg_assign_checked(struct si_function_info *fninfo,
152 enum si_arg_regfile regfile, LLVMTypeRef type,
153 LLVMValueRef *assign, unsigned idx)
154 {
155 MAYBE_UNUSED unsigned actual = add_arg_assign(fninfo, regfile, type, assign);
156 assert(actual == idx);
157 }
158
159 static void add_arg_checked(struct si_function_info *fninfo,
160 enum si_arg_regfile regfile, LLVMTypeRef type,
161 unsigned idx)
162 {
163 add_arg_assign_checked(fninfo, regfile, type, NULL, idx);
164 }
165
166 /**
167 * Returns a unique index for a per-patch semantic name and index. The index
168 * must be less than 32, so that a 32-bit bitmask of used inputs or outputs
169 * can be calculated.
170 */
171 unsigned si_shader_io_get_unique_index_patch(unsigned semantic_name, unsigned index)
172 {
173 switch (semantic_name) {
174 case TGSI_SEMANTIC_TESSOUTER:
175 return 0;
176 case TGSI_SEMANTIC_TESSINNER:
177 return 1;
178 case TGSI_SEMANTIC_PATCH:
179 assert(index < 30);
180 return 2 + index;
181
182 default:
183 assert(!"invalid semantic name");
184 return 0;
185 }
186 }
187
188 /**
189 * Returns a unique index for a semantic name and index. The index must be
190 * less than 64, so that a 64-bit bitmask of used inputs or outputs can be
191 * calculated.
192 */
193 unsigned si_shader_io_get_unique_index(unsigned semantic_name, unsigned index)
194 {
195 switch (semantic_name) {
196 case TGSI_SEMANTIC_POSITION:
197 return 0;
198 case TGSI_SEMANTIC_GENERIC:
199 /* Since some shader stages use the the highest used IO index
200 * to determine the size to allocate for inputs/outputs
201 * (in LDS, tess and GS rings). GENERIC should be placed right
202 * after POSITION to make that size as small as possible.
203 */
204 if (index < SI_MAX_IO_GENERIC)
205 return 1 + index;
206
207 assert(!"invalid generic index");
208 return 0;
209 case TGSI_SEMANTIC_PSIZE:
210 return SI_MAX_IO_GENERIC + 1;
211 case TGSI_SEMANTIC_CLIPDIST:
212 assert(index <= 1);
213 return SI_MAX_IO_GENERIC + 2 + index;
214 case TGSI_SEMANTIC_FOG:
215 return SI_MAX_IO_GENERIC + 4;
216 case TGSI_SEMANTIC_LAYER:
217 return SI_MAX_IO_GENERIC + 5;
218 case TGSI_SEMANTIC_VIEWPORT_INDEX:
219 return SI_MAX_IO_GENERIC + 6;
220 case TGSI_SEMANTIC_PRIMID:
221 return SI_MAX_IO_GENERIC + 7;
222 case TGSI_SEMANTIC_COLOR: /* these alias */
223 case TGSI_SEMANTIC_BCOLOR:
224 assert(index < 2);
225 return SI_MAX_IO_GENERIC + 8 + index;
226 case TGSI_SEMANTIC_TEXCOORD:
227 assert(index < 8);
228 assert(SI_MAX_IO_GENERIC + 10 + index < 64);
229 return SI_MAX_IO_GENERIC + 10 + index;
230 default:
231 assert(!"invalid semantic name");
232 return 0;
233 }
234 }
235
236 /**
237 * Get the value of a shader input parameter and extract a bitfield.
238 */
239 static LLVMValueRef unpack_llvm_param(struct si_shader_context *ctx,
240 LLVMValueRef value, unsigned rshift,
241 unsigned bitwidth)
242 {
243 if (LLVMGetTypeKind(LLVMTypeOf(value)) == LLVMFloatTypeKind)
244 value = ac_to_integer(&ctx->ac, value);
245
246 if (rshift)
247 value = LLVMBuildLShr(ctx->ac.builder, value,
248 LLVMConstInt(ctx->i32, rshift, 0), "");
249
250 if (rshift + bitwidth < 32) {
251 unsigned mask = (1 << bitwidth) - 1;
252 value = LLVMBuildAnd(ctx->ac.builder, value,
253 LLVMConstInt(ctx->i32, mask, 0), "");
254 }
255
256 return value;
257 }
258
259 static LLVMValueRef unpack_param(struct si_shader_context *ctx,
260 unsigned param, unsigned rshift,
261 unsigned bitwidth)
262 {
263 LLVMValueRef value = LLVMGetParam(ctx->main_fn, param);
264
265 return unpack_llvm_param(ctx, value, rshift, bitwidth);
266 }
267
268 static LLVMValueRef get_rel_patch_id(struct si_shader_context *ctx)
269 {
270 switch (ctx->type) {
271 case PIPE_SHADER_TESS_CTRL:
272 return unpack_llvm_param(ctx, ctx->abi.tcs_rel_ids, 0, 8);
273
274 case PIPE_SHADER_TESS_EVAL:
275 return LLVMGetParam(ctx->main_fn,
276 ctx->param_tes_rel_patch_id);
277
278 default:
279 assert(0);
280 return NULL;
281 }
282 }
283
284 /* Tessellation shaders pass outputs to the next shader using LDS.
285 *
286 * LS outputs = TCS inputs
287 * TCS outputs = TES inputs
288 *
289 * The LDS layout is:
290 * - TCS inputs for patch 0
291 * - TCS inputs for patch 1
292 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
293 * - ...
294 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
295 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
296 * - TCS outputs for patch 1
297 * - Per-patch TCS outputs for patch 1
298 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
299 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
300 * - ...
301 *
302 * All three shaders VS(LS), TCS, TES share the same LDS space.
303 */
304
305 static LLVMValueRef
306 get_tcs_in_patch_stride(struct si_shader_context *ctx)
307 {
308 return unpack_param(ctx, ctx->param_vs_state_bits, 8, 13);
309 }
310
311 static unsigned get_tcs_out_vertex_dw_stride_constant(struct si_shader_context *ctx)
312 {
313 assert(ctx->type == PIPE_SHADER_TESS_CTRL);
314
315 if (ctx->shader->key.mono.u.ff_tcs_inputs_to_copy)
316 return util_last_bit64(ctx->shader->key.mono.u.ff_tcs_inputs_to_copy) * 4;
317
318 return util_last_bit64(ctx->shader->selector->outputs_written) * 4;
319 }
320
321 static LLVMValueRef get_tcs_out_vertex_dw_stride(struct si_shader_context *ctx)
322 {
323 unsigned stride = get_tcs_out_vertex_dw_stride_constant(ctx);
324
325 return LLVMConstInt(ctx->i32, stride, 0);
326 }
327
328 static LLVMValueRef get_tcs_out_patch_stride(struct si_shader_context *ctx)
329 {
330 if (ctx->shader->key.mono.u.ff_tcs_inputs_to_copy)
331 return unpack_param(ctx, ctx->param_tcs_out_lds_layout, 0, 13);
332
333 const struct tgsi_shader_info *info = &ctx->shader->selector->info;
334 unsigned tcs_out_vertices = info->properties[TGSI_PROPERTY_TCS_VERTICES_OUT];
335 unsigned vertex_dw_stride = get_tcs_out_vertex_dw_stride_constant(ctx);
336 unsigned num_patch_outputs = util_last_bit64(ctx->shader->selector->patch_outputs_written);
337 unsigned patch_dw_stride = tcs_out_vertices * vertex_dw_stride +
338 num_patch_outputs * 4;
339 return LLVMConstInt(ctx->i32, patch_dw_stride, 0);
340 }
341
342 static LLVMValueRef
343 get_tcs_out_patch0_offset(struct si_shader_context *ctx)
344 {
345 return lp_build_mul_imm(&ctx->bld_base.uint_bld,
346 unpack_param(ctx,
347 ctx->param_tcs_out_lds_offsets,
348 0, 16),
349 4);
350 }
351
352 static LLVMValueRef
353 get_tcs_out_patch0_patch_data_offset(struct si_shader_context *ctx)
354 {
355 return lp_build_mul_imm(&ctx->bld_base.uint_bld,
356 unpack_param(ctx,
357 ctx->param_tcs_out_lds_offsets,
358 16, 16),
359 4);
360 }
361
362 static LLVMValueRef
363 get_tcs_in_current_patch_offset(struct si_shader_context *ctx)
364 {
365 LLVMValueRef patch_stride = get_tcs_in_patch_stride(ctx);
366 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
367
368 return LLVMBuildMul(ctx->ac.builder, patch_stride, rel_patch_id, "");
369 }
370
371 static LLVMValueRef
372 get_tcs_out_current_patch_offset(struct si_shader_context *ctx)
373 {
374 LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(ctx);
375 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
376 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
377
378 return LLVMBuildAdd(ctx->ac.builder, patch0_offset,
379 LLVMBuildMul(ctx->ac.builder, patch_stride,
380 rel_patch_id, ""),
381 "");
382 }
383
384 static LLVMValueRef
385 get_tcs_out_current_patch_data_offset(struct si_shader_context *ctx)
386 {
387 LLVMValueRef patch0_patch_data_offset =
388 get_tcs_out_patch0_patch_data_offset(ctx);
389 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
390 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
391
392 return LLVMBuildAdd(ctx->ac.builder, patch0_patch_data_offset,
393 LLVMBuildMul(ctx->ac.builder, patch_stride,
394 rel_patch_id, ""),
395 "");
396 }
397
398 static LLVMValueRef get_num_tcs_out_vertices(struct si_shader_context *ctx)
399 {
400 unsigned tcs_out_vertices =
401 ctx->shader->selector ?
402 ctx->shader->selector->info.properties[TGSI_PROPERTY_TCS_VERTICES_OUT] : 0;
403
404 /* If !tcs_out_vertices, it's either the fixed-func TCS or the TCS epilog. */
405 if (ctx->type == PIPE_SHADER_TESS_CTRL && tcs_out_vertices)
406 return LLVMConstInt(ctx->i32, tcs_out_vertices, 0);
407
408 return unpack_param(ctx, ctx->param_tcs_offchip_layout, 6, 6);
409 }
410
411 static LLVMValueRef get_tcs_in_vertex_dw_stride(struct si_shader_context *ctx)
412 {
413 unsigned stride;
414
415 switch (ctx->type) {
416 case PIPE_SHADER_VERTEX:
417 stride = util_last_bit64(ctx->shader->selector->outputs_written);
418 return LLVMConstInt(ctx->i32, stride * 4, 0);
419
420 case PIPE_SHADER_TESS_CTRL:
421 if (ctx->screen->info.chip_class >= GFX9 &&
422 ctx->shader->is_monolithic) {
423 stride = util_last_bit64(ctx->shader->key.part.tcs.ls->outputs_written);
424 return LLVMConstInt(ctx->i32, stride * 4, 0);
425 }
426 return unpack_param(ctx, ctx->param_vs_state_bits, 24, 8);
427
428 default:
429 assert(0);
430 return NULL;
431 }
432 }
433
434 static LLVMValueRef get_instance_index_for_fetch(
435 struct si_shader_context *ctx,
436 unsigned param_start_instance, LLVMValueRef divisor)
437 {
438 LLVMValueRef result = ctx->abi.instance_id;
439
440 /* The division must be done before START_INSTANCE is added. */
441 if (divisor != ctx->i32_1)
442 result = LLVMBuildUDiv(ctx->ac.builder, result, divisor, "");
443
444 return LLVMBuildAdd(ctx->ac.builder, result,
445 LLVMGetParam(ctx->main_fn, param_start_instance), "");
446 }
447
448 /* Bitcast <4 x float> to <2 x double>, extract the component, and convert
449 * to float. */
450 static LLVMValueRef extract_double_to_float(struct si_shader_context *ctx,
451 LLVMValueRef vec4,
452 unsigned double_index)
453 {
454 LLVMBuilderRef builder = ctx->ac.builder;
455 LLVMTypeRef f64 = LLVMDoubleTypeInContext(ctx->ac.context);
456 LLVMValueRef dvec2 = LLVMBuildBitCast(builder, vec4,
457 LLVMVectorType(f64, 2), "");
458 LLVMValueRef index = LLVMConstInt(ctx->i32, double_index, 0);
459 LLVMValueRef value = LLVMBuildExtractElement(builder, dvec2, index, "");
460 return LLVMBuildFPTrunc(builder, value, ctx->f32, "");
461 }
462
463 static LLVMValueRef unpack_sint16(struct si_shader_context *ctx,
464 LLVMValueRef i32, unsigned index)
465 {
466 assert(index <= 1);
467
468 if (index == 1)
469 return LLVMBuildAShr(ctx->ac.builder, i32,
470 LLVMConstInt(ctx->i32, 16, 0), "");
471
472 return LLVMBuildSExt(ctx->ac.builder,
473 LLVMBuildTrunc(ctx->ac.builder, i32,
474 ctx->ac.i16, ""),
475 ctx->i32, "");
476 }
477
478 void si_llvm_load_input_vs(
479 struct si_shader_context *ctx,
480 unsigned input_index,
481 LLVMValueRef out[4])
482 {
483 const struct tgsi_shader_info *info = &ctx->shader->selector->info;
484 unsigned vs_blit_property = info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS];
485
486 if (vs_blit_property) {
487 LLVMValueRef vertex_id = ctx->abi.vertex_id;
488 LLVMValueRef sel_x1 = LLVMBuildICmp(ctx->ac.builder,
489 LLVMIntULE, vertex_id,
490 ctx->i32_1, "");
491 /* Use LLVMIntNE, because we have 3 vertices and only
492 * the middle one should use y2.
493 */
494 LLVMValueRef sel_y1 = LLVMBuildICmp(ctx->ac.builder,
495 LLVMIntNE, vertex_id,
496 ctx->i32_1, "");
497
498 if (input_index == 0) {
499 /* Position: */
500 LLVMValueRef x1y1 = LLVMGetParam(ctx->main_fn,
501 ctx->param_vs_blit_inputs);
502 LLVMValueRef x2y2 = LLVMGetParam(ctx->main_fn,
503 ctx->param_vs_blit_inputs + 1);
504
505 LLVMValueRef x1 = unpack_sint16(ctx, x1y1, 0);
506 LLVMValueRef y1 = unpack_sint16(ctx, x1y1, 1);
507 LLVMValueRef x2 = unpack_sint16(ctx, x2y2, 0);
508 LLVMValueRef y2 = unpack_sint16(ctx, x2y2, 1);
509
510 LLVMValueRef x = LLVMBuildSelect(ctx->ac.builder, sel_x1,
511 x1, x2, "");
512 LLVMValueRef y = LLVMBuildSelect(ctx->ac.builder, sel_y1,
513 y1, y2, "");
514
515 out[0] = LLVMBuildSIToFP(ctx->ac.builder, x, ctx->f32, "");
516 out[1] = LLVMBuildSIToFP(ctx->ac.builder, y, ctx->f32, "");
517 out[2] = LLVMGetParam(ctx->main_fn,
518 ctx->param_vs_blit_inputs + 2);
519 out[3] = ctx->ac.f32_1;
520 return;
521 }
522
523 /* Color or texture coordinates: */
524 assert(input_index == 1);
525
526 if (vs_blit_property == SI_VS_BLIT_SGPRS_POS_COLOR) {
527 for (int i = 0; i < 4; i++) {
528 out[i] = LLVMGetParam(ctx->main_fn,
529 ctx->param_vs_blit_inputs + 3 + i);
530 }
531 } else {
532 assert(vs_blit_property == SI_VS_BLIT_SGPRS_POS_TEXCOORD);
533 LLVMValueRef x1 = LLVMGetParam(ctx->main_fn,
534 ctx->param_vs_blit_inputs + 3);
535 LLVMValueRef y1 = LLVMGetParam(ctx->main_fn,
536 ctx->param_vs_blit_inputs + 4);
537 LLVMValueRef x2 = LLVMGetParam(ctx->main_fn,
538 ctx->param_vs_blit_inputs + 5);
539 LLVMValueRef y2 = LLVMGetParam(ctx->main_fn,
540 ctx->param_vs_blit_inputs + 6);
541
542 out[0] = LLVMBuildSelect(ctx->ac.builder, sel_x1,
543 x1, x2, "");
544 out[1] = LLVMBuildSelect(ctx->ac.builder, sel_y1,
545 y1, y2, "");
546 out[2] = LLVMGetParam(ctx->main_fn,
547 ctx->param_vs_blit_inputs + 7);
548 out[3] = LLVMGetParam(ctx->main_fn,
549 ctx->param_vs_blit_inputs + 8);
550 }
551 return;
552 }
553
554 unsigned chan;
555 unsigned fix_fetch;
556 unsigned num_fetches;
557 unsigned fetch_stride;
558 unsigned num_channels;
559
560 LLVMValueRef t_list_ptr;
561 LLVMValueRef t_offset;
562 LLVMValueRef t_list;
563 LLVMValueRef vertex_index;
564 LLVMValueRef input[3];
565
566 /* Load the T list */
567 t_list_ptr = LLVMGetParam(ctx->main_fn, ctx->param_vertex_buffers);
568
569 t_offset = LLVMConstInt(ctx->i32, input_index, 0);
570
571 t_list = ac_build_load_to_sgpr(&ctx->ac, t_list_ptr, t_offset);
572
573 vertex_index = LLVMGetParam(ctx->main_fn,
574 ctx->param_vertex_index0 +
575 input_index);
576
577 fix_fetch = ctx->shader->key.mono.vs_fix_fetch[input_index];
578
579 /* Do multiple loads for special formats. */
580 switch (fix_fetch) {
581 case SI_FIX_FETCH_RGB_64_FLOAT:
582 num_fetches = 3; /* 3 2-dword loads */
583 fetch_stride = 8;
584 num_channels = 2;
585 break;
586 case SI_FIX_FETCH_RGBA_64_FLOAT:
587 num_fetches = 2; /* 2 4-dword loads */
588 fetch_stride = 16;
589 num_channels = 4;
590 break;
591 case SI_FIX_FETCH_RGB_8:
592 case SI_FIX_FETCH_RGB_8_INT:
593 num_fetches = 3;
594 fetch_stride = 1;
595 num_channels = 1;
596 break;
597 case SI_FIX_FETCH_RGB_16:
598 case SI_FIX_FETCH_RGB_16_INT:
599 num_fetches = 3;
600 fetch_stride = 2;
601 num_channels = 1;
602 break;
603 default:
604 num_fetches = 1;
605 fetch_stride = 0;
606 num_channels = util_last_bit(info->input_usage_mask[input_index]);
607 }
608
609 for (unsigned i = 0; i < num_fetches; i++) {
610 LLVMValueRef voffset = LLVMConstInt(ctx->i32, fetch_stride * i, 0);
611
612 input[i] = ac_build_buffer_load_format(&ctx->ac, t_list,
613 vertex_index, voffset,
614 num_channels, true);
615 input[i] = ac_build_expand_to_vec4(&ctx->ac, input[i], num_channels);
616 }
617
618 /* Break up the vec4 into individual components */
619 for (chan = 0; chan < 4; chan++) {
620 LLVMValueRef llvm_chan = LLVMConstInt(ctx->i32, chan, 0);
621 out[chan] = LLVMBuildExtractElement(ctx->ac.builder,
622 input[0], llvm_chan, "");
623 }
624
625 switch (fix_fetch) {
626 case SI_FIX_FETCH_A2_SNORM:
627 case SI_FIX_FETCH_A2_SSCALED:
628 case SI_FIX_FETCH_A2_SINT: {
629 /* The hardware returns an unsigned value; convert it to a
630 * signed one.
631 */
632 LLVMValueRef tmp = out[3];
633 LLVMValueRef c30 = LLVMConstInt(ctx->i32, 30, 0);
634
635 /* First, recover the sign-extended signed integer value. */
636 if (fix_fetch == SI_FIX_FETCH_A2_SSCALED)
637 tmp = LLVMBuildFPToUI(ctx->ac.builder, tmp, ctx->i32, "");
638 else
639 tmp = ac_to_integer(&ctx->ac, tmp);
640
641 /* For the integer-like cases, do a natural sign extension.
642 *
643 * For the SNORM case, the values are 0.0, 0.333, 0.666, 1.0
644 * and happen to contain 0, 1, 2, 3 as the two LSBs of the
645 * exponent.
646 */
647 tmp = LLVMBuildShl(ctx->ac.builder, tmp,
648 fix_fetch == SI_FIX_FETCH_A2_SNORM ?
649 LLVMConstInt(ctx->i32, 7, 0) : c30, "");
650 tmp = LLVMBuildAShr(ctx->ac.builder, tmp, c30, "");
651
652 /* Convert back to the right type. */
653 if (fix_fetch == SI_FIX_FETCH_A2_SNORM) {
654 LLVMValueRef clamp;
655 LLVMValueRef neg_one = LLVMConstReal(ctx->f32, -1.0);
656 tmp = LLVMBuildSIToFP(ctx->ac.builder, tmp, ctx->f32, "");
657 clamp = LLVMBuildFCmp(ctx->ac.builder, LLVMRealULT, tmp, neg_one, "");
658 tmp = LLVMBuildSelect(ctx->ac.builder, clamp, neg_one, tmp, "");
659 } else if (fix_fetch == SI_FIX_FETCH_A2_SSCALED) {
660 tmp = LLVMBuildSIToFP(ctx->ac.builder, tmp, ctx->f32, "");
661 }
662
663 out[3] = tmp;
664 break;
665 }
666 case SI_FIX_FETCH_RGBA_32_UNORM:
667 case SI_FIX_FETCH_RGBX_32_UNORM:
668 for (chan = 0; chan < 4; chan++) {
669 out[chan] = ac_to_integer(&ctx->ac, out[chan]);
670 out[chan] = LLVMBuildUIToFP(ctx->ac.builder,
671 out[chan], ctx->f32, "");
672 out[chan] = LLVMBuildFMul(ctx->ac.builder, out[chan],
673 LLVMConstReal(ctx->f32, 1.0 / UINT_MAX), "");
674 }
675 /* RGBX UINT returns 1 in alpha, which would be rounded to 0 by normalizing. */
676 if (fix_fetch == SI_FIX_FETCH_RGBX_32_UNORM)
677 out[3] = LLVMConstReal(ctx->f32, 1);
678 break;
679 case SI_FIX_FETCH_RGBA_32_SNORM:
680 case SI_FIX_FETCH_RGBX_32_SNORM:
681 case SI_FIX_FETCH_RGBA_32_FIXED:
682 case SI_FIX_FETCH_RGBX_32_FIXED: {
683 double scale;
684 if (fix_fetch >= SI_FIX_FETCH_RGBA_32_FIXED)
685 scale = 1.0 / 0x10000;
686 else
687 scale = 1.0 / INT_MAX;
688
689 for (chan = 0; chan < 4; chan++) {
690 out[chan] = ac_to_integer(&ctx->ac, out[chan]);
691 out[chan] = LLVMBuildSIToFP(ctx->ac.builder,
692 out[chan], ctx->f32, "");
693 out[chan] = LLVMBuildFMul(ctx->ac.builder, out[chan],
694 LLVMConstReal(ctx->f32, scale), "");
695 }
696 /* RGBX SINT returns 1 in alpha, which would be rounded to 0 by normalizing. */
697 if (fix_fetch == SI_FIX_FETCH_RGBX_32_SNORM ||
698 fix_fetch == SI_FIX_FETCH_RGBX_32_FIXED)
699 out[3] = LLVMConstReal(ctx->f32, 1);
700 break;
701 }
702 case SI_FIX_FETCH_RGBA_32_USCALED:
703 for (chan = 0; chan < 4; chan++) {
704 out[chan] = ac_to_integer(&ctx->ac, out[chan]);
705 out[chan] = LLVMBuildUIToFP(ctx->ac.builder,
706 out[chan], ctx->f32, "");
707 }
708 break;
709 case SI_FIX_FETCH_RGBA_32_SSCALED:
710 for (chan = 0; chan < 4; chan++) {
711 out[chan] = ac_to_integer(&ctx->ac, out[chan]);
712 out[chan] = LLVMBuildSIToFP(ctx->ac.builder,
713 out[chan], ctx->f32, "");
714 }
715 break;
716 case SI_FIX_FETCH_RG_64_FLOAT:
717 for (chan = 0; chan < 2; chan++)
718 out[chan] = extract_double_to_float(ctx, input[0], chan);
719
720 out[2] = LLVMConstReal(ctx->f32, 0);
721 out[3] = LLVMConstReal(ctx->f32, 1);
722 break;
723 case SI_FIX_FETCH_RGB_64_FLOAT:
724 for (chan = 0; chan < 3; chan++)
725 out[chan] = extract_double_to_float(ctx, input[chan], 0);
726
727 out[3] = LLVMConstReal(ctx->f32, 1);
728 break;
729 case SI_FIX_FETCH_RGBA_64_FLOAT:
730 for (chan = 0; chan < 4; chan++) {
731 out[chan] = extract_double_to_float(ctx, input[chan / 2],
732 chan % 2);
733 }
734 break;
735 case SI_FIX_FETCH_RGB_8:
736 case SI_FIX_FETCH_RGB_8_INT:
737 case SI_FIX_FETCH_RGB_16:
738 case SI_FIX_FETCH_RGB_16_INT:
739 for (chan = 0; chan < 3; chan++) {
740 out[chan] = LLVMBuildExtractElement(ctx->ac.builder,
741 input[chan],
742 ctx->i32_0, "");
743 }
744 if (fix_fetch == SI_FIX_FETCH_RGB_8 ||
745 fix_fetch == SI_FIX_FETCH_RGB_16) {
746 out[3] = LLVMConstReal(ctx->f32, 1);
747 } else {
748 out[3] = ac_to_float(&ctx->ac, ctx->i32_1);
749 }
750 break;
751 }
752 }
753
754 static void declare_input_vs(
755 struct si_shader_context *ctx,
756 unsigned input_index,
757 const struct tgsi_full_declaration *decl,
758 LLVMValueRef out[4])
759 {
760 si_llvm_load_input_vs(ctx, input_index, out);
761 }
762
763 static LLVMValueRef get_primitive_id(struct si_shader_context *ctx,
764 unsigned swizzle)
765 {
766 if (swizzle > 0)
767 return ctx->i32_0;
768
769 switch (ctx->type) {
770 case PIPE_SHADER_VERTEX:
771 return LLVMGetParam(ctx->main_fn,
772 ctx->param_vs_prim_id);
773 case PIPE_SHADER_TESS_CTRL:
774 return ctx->abi.tcs_patch_id;
775 case PIPE_SHADER_TESS_EVAL:
776 return ctx->abi.tes_patch_id;
777 case PIPE_SHADER_GEOMETRY:
778 return ctx->abi.gs_prim_id;
779 default:
780 assert(0);
781 return ctx->i32_0;
782 }
783 }
784
785 /**
786 * Return the value of tgsi_ind_register for indexing.
787 * This is the indirect index with the constant offset added to it.
788 */
789 LLVMValueRef si_get_indirect_index(struct si_shader_context *ctx,
790 const struct tgsi_ind_register *ind,
791 unsigned addr_mul,
792 int rel_index)
793 {
794 LLVMValueRef result;
795
796 if (ind->File == TGSI_FILE_ADDRESS) {
797 result = ctx->addrs[ind->Index][ind->Swizzle];
798 result = LLVMBuildLoad(ctx->ac.builder, result, "");
799 } else {
800 struct tgsi_full_src_register src = {};
801
802 src.Register.File = ind->File;
803 src.Register.Index = ind->Index;
804
805 /* Set the second index to 0 for constants. */
806 if (ind->File == TGSI_FILE_CONSTANT)
807 src.Register.Dimension = 1;
808
809 result = ctx->bld_base.emit_fetch_funcs[ind->File](&ctx->bld_base, &src,
810 TGSI_TYPE_SIGNED,
811 ind->Swizzle);
812 result = ac_to_integer(&ctx->ac, result);
813 }
814
815 if (addr_mul != 1)
816 result = LLVMBuildMul(ctx->ac.builder, result,
817 LLVMConstInt(ctx->i32, addr_mul, 0), "");
818 result = LLVMBuildAdd(ctx->ac.builder, result,
819 LLVMConstInt(ctx->i32, rel_index, 0), "");
820 return result;
821 }
822
823 /**
824 * Like si_get_indirect_index, but restricts the return value to a (possibly
825 * undefined) value inside [0..num).
826 */
827 LLVMValueRef si_get_bounded_indirect_index(struct si_shader_context *ctx,
828 const struct tgsi_ind_register *ind,
829 int rel_index, unsigned num)
830 {
831 LLVMValueRef result = si_get_indirect_index(ctx, ind, 1, rel_index);
832
833 return si_llvm_bound_index(ctx, result, num);
834 }
835
836 static LLVMValueRef get_dw_address_from_generic_indices(struct si_shader_context *ctx,
837 LLVMValueRef vertex_dw_stride,
838 LLVMValueRef base_addr,
839 LLVMValueRef vertex_index,
840 LLVMValueRef param_index,
841 unsigned input_index,
842 ubyte *name,
843 ubyte *index,
844 bool is_patch)
845 {
846 if (vertex_dw_stride) {
847 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
848 LLVMBuildMul(ctx->ac.builder, vertex_index,
849 vertex_dw_stride, ""), "");
850 }
851
852 if (param_index) {
853 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
854 LLVMBuildMul(ctx->ac.builder, param_index,
855 LLVMConstInt(ctx->i32, 4, 0), ""), "");
856 }
857
858 int param = is_patch ?
859 si_shader_io_get_unique_index_patch(name[input_index],
860 index[input_index]) :
861 si_shader_io_get_unique_index(name[input_index],
862 index[input_index]);
863
864 /* Add the base address of the element. */
865 return LLVMBuildAdd(ctx->ac.builder, base_addr,
866 LLVMConstInt(ctx->i32, param * 4, 0), "");
867 }
868
869 /**
870 * Calculate a dword address given an input or output register and a stride.
871 */
872 static LLVMValueRef get_dw_address(struct si_shader_context *ctx,
873 const struct tgsi_full_dst_register *dst,
874 const struct tgsi_full_src_register *src,
875 LLVMValueRef vertex_dw_stride,
876 LLVMValueRef base_addr)
877 {
878 struct tgsi_shader_info *info = &ctx->shader->selector->info;
879 ubyte *name, *index, *array_first;
880 int input_index;
881 struct tgsi_full_dst_register reg;
882 LLVMValueRef vertex_index = NULL;
883 LLVMValueRef ind_index = NULL;
884
885 /* Set the register description. The address computation is the same
886 * for sources and destinations. */
887 if (src) {
888 reg.Register.File = src->Register.File;
889 reg.Register.Index = src->Register.Index;
890 reg.Register.Indirect = src->Register.Indirect;
891 reg.Register.Dimension = src->Register.Dimension;
892 reg.Indirect = src->Indirect;
893 reg.Dimension = src->Dimension;
894 reg.DimIndirect = src->DimIndirect;
895 } else
896 reg = *dst;
897
898 /* If the register is 2-dimensional (e.g. an array of vertices
899 * in a primitive), calculate the base address of the vertex. */
900 if (reg.Register.Dimension) {
901 if (reg.Dimension.Indirect)
902 vertex_index = si_get_indirect_index(ctx, &reg.DimIndirect,
903 1, reg.Dimension.Index);
904 else
905 vertex_index = LLVMConstInt(ctx->i32, reg.Dimension.Index, 0);
906 }
907
908 /* Get information about the register. */
909 if (reg.Register.File == TGSI_FILE_INPUT) {
910 name = info->input_semantic_name;
911 index = info->input_semantic_index;
912 array_first = info->input_array_first;
913 } else if (reg.Register.File == TGSI_FILE_OUTPUT) {
914 name = info->output_semantic_name;
915 index = info->output_semantic_index;
916 array_first = info->output_array_first;
917 } else {
918 assert(0);
919 return NULL;
920 }
921
922 if (reg.Register.Indirect) {
923 /* Add the relative address of the element. */
924 if (reg.Indirect.ArrayID)
925 input_index = array_first[reg.Indirect.ArrayID];
926 else
927 input_index = reg.Register.Index;
928
929 ind_index = si_get_indirect_index(ctx, &reg.Indirect,
930 1, reg.Register.Index - input_index);
931 } else {
932 input_index = reg.Register.Index;
933 }
934
935 return get_dw_address_from_generic_indices(ctx, vertex_dw_stride,
936 base_addr, vertex_index,
937 ind_index, input_index,
938 name, index,
939 !reg.Register.Dimension);
940 }
941
942 /* The offchip buffer layout for TCS->TES is
943 *
944 * - attribute 0 of patch 0 vertex 0
945 * - attribute 0 of patch 0 vertex 1
946 * - attribute 0 of patch 0 vertex 2
947 * ...
948 * - attribute 0 of patch 1 vertex 0
949 * - attribute 0 of patch 1 vertex 1
950 * ...
951 * - attribute 1 of patch 0 vertex 0
952 * - attribute 1 of patch 0 vertex 1
953 * ...
954 * - per patch attribute 0 of patch 0
955 * - per patch attribute 0 of patch 1
956 * ...
957 *
958 * Note that every attribute has 4 components.
959 */
960 static LLVMValueRef get_tcs_tes_buffer_address(struct si_shader_context *ctx,
961 LLVMValueRef rel_patch_id,
962 LLVMValueRef vertex_index,
963 LLVMValueRef param_index)
964 {
965 LLVMValueRef base_addr, vertices_per_patch, num_patches, total_vertices;
966 LLVMValueRef param_stride, constant16;
967
968 vertices_per_patch = get_num_tcs_out_vertices(ctx);
969 num_patches = unpack_param(ctx, ctx->param_tcs_offchip_layout, 0, 6);
970 total_vertices = LLVMBuildMul(ctx->ac.builder, vertices_per_patch,
971 num_patches, "");
972
973 constant16 = LLVMConstInt(ctx->i32, 16, 0);
974 if (vertex_index) {
975 base_addr = LLVMBuildMul(ctx->ac.builder, rel_patch_id,
976 vertices_per_patch, "");
977
978 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
979 vertex_index, "");
980
981 param_stride = total_vertices;
982 } else {
983 base_addr = rel_patch_id;
984 param_stride = num_patches;
985 }
986
987 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
988 LLVMBuildMul(ctx->ac.builder, param_index,
989 param_stride, ""), "");
990
991 base_addr = LLVMBuildMul(ctx->ac.builder, base_addr, constant16, "");
992
993 if (!vertex_index) {
994 LLVMValueRef patch_data_offset =
995 unpack_param(ctx, ctx->param_tcs_offchip_layout, 12, 20);
996
997 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
998 patch_data_offset, "");
999 }
1000 return base_addr;
1001 }
1002
1003 /* This is a generic helper that can be shared by the NIR and TGSI backends */
1004 static LLVMValueRef get_tcs_tes_buffer_address_from_generic_indices(
1005 struct si_shader_context *ctx,
1006 LLVMValueRef vertex_index,
1007 LLVMValueRef param_index,
1008 unsigned param_base,
1009 ubyte *name,
1010 ubyte *index,
1011 bool is_patch)
1012 {
1013 unsigned param_index_base;
1014
1015 param_index_base = is_patch ?
1016 si_shader_io_get_unique_index_patch(name[param_base], index[param_base]) :
1017 si_shader_io_get_unique_index(name[param_base], index[param_base]);
1018
1019 if (param_index) {
1020 param_index = LLVMBuildAdd(ctx->ac.builder, param_index,
1021 LLVMConstInt(ctx->i32, param_index_base, 0),
1022 "");
1023 } else {
1024 param_index = LLVMConstInt(ctx->i32, param_index_base, 0);
1025 }
1026
1027 return get_tcs_tes_buffer_address(ctx, get_rel_patch_id(ctx),
1028 vertex_index, param_index);
1029 }
1030
1031 static LLVMValueRef get_tcs_tes_buffer_address_from_reg(
1032 struct si_shader_context *ctx,
1033 const struct tgsi_full_dst_register *dst,
1034 const struct tgsi_full_src_register *src)
1035 {
1036 struct tgsi_shader_info *info = &ctx->shader->selector->info;
1037 ubyte *name, *index, *array_first;
1038 struct tgsi_full_src_register reg;
1039 LLVMValueRef vertex_index = NULL;
1040 LLVMValueRef param_index = NULL;
1041 unsigned param_base;
1042
1043 reg = src ? *src : tgsi_full_src_register_from_dst(dst);
1044
1045 if (reg.Register.Dimension) {
1046
1047 if (reg.Dimension.Indirect)
1048 vertex_index = si_get_indirect_index(ctx, &reg.DimIndirect,
1049 1, reg.Dimension.Index);
1050 else
1051 vertex_index = LLVMConstInt(ctx->i32, reg.Dimension.Index, 0);
1052 }
1053
1054 /* Get information about the register. */
1055 if (reg.Register.File == TGSI_FILE_INPUT) {
1056 name = info->input_semantic_name;
1057 index = info->input_semantic_index;
1058 array_first = info->input_array_first;
1059 } else if (reg.Register.File == TGSI_FILE_OUTPUT) {
1060 name = info->output_semantic_name;
1061 index = info->output_semantic_index;
1062 array_first = info->output_array_first;
1063 } else {
1064 assert(0);
1065 return NULL;
1066 }
1067
1068 if (reg.Register.Indirect) {
1069 if (reg.Indirect.ArrayID)
1070 param_base = array_first[reg.Indirect.ArrayID];
1071 else
1072 param_base = reg.Register.Index;
1073
1074 param_index = si_get_indirect_index(ctx, &reg.Indirect,
1075 1, reg.Register.Index - param_base);
1076
1077 } else {
1078 param_base = reg.Register.Index;
1079 }
1080
1081 return get_tcs_tes_buffer_address_from_generic_indices(ctx, vertex_index,
1082 param_index, param_base,
1083 name, index, !reg.Register.Dimension);
1084 }
1085
1086 static LLVMValueRef buffer_load(struct lp_build_tgsi_context *bld_base,
1087 LLVMTypeRef type, unsigned swizzle,
1088 LLVMValueRef buffer, LLVMValueRef offset,
1089 LLVMValueRef base, bool can_speculate)
1090 {
1091 struct si_shader_context *ctx = si_shader_context(bld_base);
1092 LLVMValueRef value, value2;
1093 LLVMTypeRef vec_type = LLVMVectorType(type, 4);
1094
1095 if (swizzle == ~0) {
1096 value = ac_build_buffer_load(&ctx->ac, buffer, 4, NULL, base, offset,
1097 0, 1, 0, can_speculate, false);
1098
1099 return LLVMBuildBitCast(ctx->ac.builder, value, vec_type, "");
1100 }
1101
1102 if (!llvm_type_is_64bit(ctx, type)) {
1103 value = ac_build_buffer_load(&ctx->ac, buffer, 4, NULL, base, offset,
1104 0, 1, 0, can_speculate, false);
1105
1106 value = LLVMBuildBitCast(ctx->ac.builder, value, vec_type, "");
1107 return LLVMBuildExtractElement(ctx->ac.builder, value,
1108 LLVMConstInt(ctx->i32, swizzle, 0), "");
1109 }
1110
1111 value = ac_build_buffer_load(&ctx->ac, buffer, 1, NULL, base, offset,
1112 swizzle * 4, 1, 0, can_speculate, false);
1113
1114 value2 = ac_build_buffer_load(&ctx->ac, buffer, 1, NULL, base, offset,
1115 swizzle * 4 + 4, 1, 0, can_speculate, false);
1116
1117 return si_llvm_emit_fetch_64bit(bld_base, type, value, value2);
1118 }
1119
1120 /**
1121 * Load from LDS.
1122 *
1123 * \param type output value type
1124 * \param swizzle offset (typically 0..3); it can be ~0, which loads a vec4
1125 * \param dw_addr address in dwords
1126 */
1127 static LLVMValueRef lds_load(struct lp_build_tgsi_context *bld_base,
1128 LLVMTypeRef type, unsigned swizzle,
1129 LLVMValueRef dw_addr)
1130 {
1131 struct si_shader_context *ctx = si_shader_context(bld_base);
1132 LLVMValueRef value;
1133
1134 if (swizzle == ~0) {
1135 LLVMValueRef values[TGSI_NUM_CHANNELS];
1136
1137 for (unsigned chan = 0; chan < TGSI_NUM_CHANNELS; chan++)
1138 values[chan] = lds_load(bld_base, type, chan, dw_addr);
1139
1140 return lp_build_gather_values(&ctx->gallivm, values,
1141 TGSI_NUM_CHANNELS);
1142 }
1143
1144 /* Split 64-bit loads. */
1145 if (llvm_type_is_64bit(ctx, type)) {
1146 LLVMValueRef lo, hi;
1147
1148 lo = lds_load(bld_base, ctx->i32, swizzle, dw_addr);
1149 hi = lds_load(bld_base, ctx->i32, swizzle + 1, dw_addr);
1150 return si_llvm_emit_fetch_64bit(bld_base, type, lo, hi);
1151 }
1152
1153 dw_addr = lp_build_add(&bld_base->uint_bld, dw_addr,
1154 LLVMConstInt(ctx->i32, swizzle, 0));
1155
1156 value = ac_lds_load(&ctx->ac, dw_addr);
1157
1158 return LLVMBuildBitCast(ctx->ac.builder, value, type, "");
1159 }
1160
1161 /**
1162 * Store to LDS.
1163 *
1164 * \param swizzle offset (typically 0..3)
1165 * \param dw_addr address in dwords
1166 * \param value value to store
1167 */
1168 static void lds_store(struct si_shader_context *ctx,
1169 unsigned dw_offset_imm, LLVMValueRef dw_addr,
1170 LLVMValueRef value)
1171 {
1172 dw_addr = lp_build_add(&ctx->bld_base.uint_bld, dw_addr,
1173 LLVMConstInt(ctx->i32, dw_offset_imm, 0));
1174
1175 ac_lds_store(&ctx->ac, dw_addr, value);
1176 }
1177
1178 static LLVMValueRef desc_from_addr_base64k(struct si_shader_context *ctx,
1179 unsigned param)
1180 {
1181 LLVMBuilderRef builder = ctx->ac.builder;
1182
1183 LLVMValueRef addr = LLVMGetParam(ctx->main_fn, param);
1184 addr = LLVMBuildZExt(builder, addr, ctx->i64, "");
1185 addr = LLVMBuildShl(builder, addr, LLVMConstInt(ctx->i64, 16, 0), "");
1186
1187 uint64_t desc2 = 0xffffffff;
1188 uint64_t desc3 = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1189 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1190 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1191 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1192 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1193 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
1194 LLVMValueRef hi = LLVMConstInt(ctx->i64, desc2 | (desc3 << 32), 0);
1195
1196 LLVMValueRef desc = LLVMGetUndef(LLVMVectorType(ctx->i64, 2));
1197 desc = LLVMBuildInsertElement(builder, desc, addr, ctx->i32_0, "");
1198 desc = LLVMBuildInsertElement(builder, desc, hi, ctx->i32_1, "");
1199 return LLVMBuildBitCast(builder, desc, ctx->v4i32, "");
1200 }
1201
1202 static LLVMValueRef fetch_input_tcs(
1203 struct lp_build_tgsi_context *bld_base,
1204 const struct tgsi_full_src_register *reg,
1205 enum tgsi_opcode_type type, unsigned swizzle)
1206 {
1207 struct si_shader_context *ctx = si_shader_context(bld_base);
1208 LLVMValueRef dw_addr, stride;
1209
1210 stride = get_tcs_in_vertex_dw_stride(ctx);
1211 dw_addr = get_tcs_in_current_patch_offset(ctx);
1212 dw_addr = get_dw_address(ctx, NULL, reg, stride, dw_addr);
1213
1214 return lds_load(bld_base, tgsi2llvmtype(bld_base, type), swizzle, dw_addr);
1215 }
1216
1217 static LLVMValueRef si_nir_load_tcs_varyings(struct ac_shader_abi *abi,
1218 LLVMValueRef vertex_index,
1219 LLVMValueRef param_index,
1220 unsigned const_index,
1221 unsigned location,
1222 unsigned driver_location,
1223 unsigned component,
1224 unsigned num_components,
1225 bool is_patch,
1226 bool is_compact,
1227 bool load_input)
1228 {
1229 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1230 struct tgsi_shader_info *info = &ctx->shader->selector->info;
1231 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
1232 LLVMValueRef dw_addr, stride;
1233
1234 driver_location = driver_location / 4;
1235
1236 if (load_input) {
1237 stride = get_tcs_in_vertex_dw_stride(ctx);
1238 dw_addr = get_tcs_in_current_patch_offset(ctx);
1239 } else {
1240 if (is_patch) {
1241 stride = NULL;
1242 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1243 } else {
1244 stride = get_tcs_out_vertex_dw_stride(ctx);
1245 dw_addr = get_tcs_out_current_patch_offset(ctx);
1246 }
1247 }
1248
1249 if (param_index) {
1250 /* Add the constant index to the indirect index */
1251 param_index = LLVMBuildAdd(ctx->ac.builder, param_index,
1252 LLVMConstInt(ctx->i32, const_index, 0), "");
1253 } else {
1254 param_index = LLVMConstInt(ctx->i32, const_index, 0);
1255 }
1256
1257 dw_addr = get_dw_address_from_generic_indices(ctx, stride, dw_addr,
1258 vertex_index, param_index,
1259 driver_location,
1260 info->input_semantic_name,
1261 info->input_semantic_index,
1262 is_patch);
1263
1264 LLVMValueRef value[4];
1265 for (unsigned i = 0; i < num_components + component; i++) {
1266 value[i] = lds_load(bld_base, ctx->i32, i, dw_addr);
1267 }
1268
1269 return ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
1270 }
1271
1272 static LLVMValueRef fetch_output_tcs(
1273 struct lp_build_tgsi_context *bld_base,
1274 const struct tgsi_full_src_register *reg,
1275 enum tgsi_opcode_type type, unsigned swizzle)
1276 {
1277 struct si_shader_context *ctx = si_shader_context(bld_base);
1278 LLVMValueRef dw_addr, stride;
1279
1280 if (reg->Register.Dimension) {
1281 stride = get_tcs_out_vertex_dw_stride(ctx);
1282 dw_addr = get_tcs_out_current_patch_offset(ctx);
1283 dw_addr = get_dw_address(ctx, NULL, reg, stride, dw_addr);
1284 } else {
1285 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1286 dw_addr = get_dw_address(ctx, NULL, reg, NULL, dw_addr);
1287 }
1288
1289 return lds_load(bld_base, tgsi2llvmtype(bld_base, type), swizzle, dw_addr);
1290 }
1291
1292 static LLVMValueRef fetch_input_tes(
1293 struct lp_build_tgsi_context *bld_base,
1294 const struct tgsi_full_src_register *reg,
1295 enum tgsi_opcode_type type, unsigned swizzle)
1296 {
1297 struct si_shader_context *ctx = si_shader_context(bld_base);
1298 LLVMValueRef buffer, base, addr;
1299
1300 buffer = desc_from_addr_base64k(ctx, ctx->param_tcs_offchip_addr_base64k);
1301
1302 base = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
1303 addr = get_tcs_tes_buffer_address_from_reg(ctx, NULL, reg);
1304
1305 return buffer_load(bld_base, tgsi2llvmtype(bld_base, type), swizzle,
1306 buffer, base, addr, true);
1307 }
1308
1309 LLVMValueRef si_nir_load_input_tes(struct ac_shader_abi *abi,
1310 LLVMValueRef vertex_index,
1311 LLVMValueRef param_index,
1312 unsigned const_index,
1313 unsigned location,
1314 unsigned driver_location,
1315 unsigned component,
1316 unsigned num_components,
1317 bool is_patch,
1318 bool is_compact,
1319 bool load_input)
1320 {
1321 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1322 struct tgsi_shader_info *info = &ctx->shader->selector->info;
1323 LLVMValueRef buffer, base, addr;
1324
1325 driver_location = driver_location / 4;
1326
1327 buffer = desc_from_addr_base64k(ctx, ctx->param_tcs_offchip_addr_base64k);
1328
1329 base = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
1330
1331 if (param_index) {
1332 /* Add the constant index to the indirect index */
1333 param_index = LLVMBuildAdd(ctx->ac.builder, param_index,
1334 LLVMConstInt(ctx->i32, const_index, 0), "");
1335 } else {
1336 param_index = LLVMConstInt(ctx->i32, const_index, 0);
1337 }
1338
1339 addr = get_tcs_tes_buffer_address_from_generic_indices(ctx, vertex_index,
1340 param_index, driver_location,
1341 info->input_semantic_name,
1342 info->input_semantic_index,
1343 is_patch);
1344
1345 /* TODO: This will generate rather ordinary llvm code, although it
1346 * should be easy for the optimiser to fix up. In future we might want
1347 * to refactor buffer_load(), but for now this maximises code sharing
1348 * between the NIR and TGSI backends.
1349 */
1350 LLVMValueRef value[4];
1351 for (unsigned i = component; i < num_components + component; i++) {
1352 value[i] = buffer_load(&ctx->bld_base, ctx->i32, i, buffer, base, addr, true);
1353 }
1354
1355 return ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
1356 }
1357
1358 static void store_output_tcs(struct lp_build_tgsi_context *bld_base,
1359 const struct tgsi_full_instruction *inst,
1360 const struct tgsi_opcode_info *info,
1361 unsigned index,
1362 LLVMValueRef dst[4])
1363 {
1364 struct si_shader_context *ctx = si_shader_context(bld_base);
1365 const struct tgsi_full_dst_register *reg = &inst->Dst[index];
1366 const struct tgsi_shader_info *sh_info = &ctx->shader->selector->info;
1367 unsigned chan_index;
1368 LLVMValueRef dw_addr, stride;
1369 LLVMValueRef buffer, base, buf_addr;
1370 LLVMValueRef values[4];
1371 bool skip_lds_store;
1372 bool is_tess_factor = false, is_tess_inner = false;
1373
1374 /* Only handle per-patch and per-vertex outputs here.
1375 * Vectors will be lowered to scalars and this function will be called again.
1376 */
1377 if (reg->Register.File != TGSI_FILE_OUTPUT ||
1378 (dst[0] && LLVMGetTypeKind(LLVMTypeOf(dst[0])) == LLVMVectorTypeKind)) {
1379 si_llvm_emit_store(bld_base, inst, info, index, dst);
1380 return;
1381 }
1382
1383 if (reg->Register.Dimension) {
1384 stride = get_tcs_out_vertex_dw_stride(ctx);
1385 dw_addr = get_tcs_out_current_patch_offset(ctx);
1386 dw_addr = get_dw_address(ctx, reg, NULL, stride, dw_addr);
1387 skip_lds_store = !sh_info->reads_pervertex_outputs;
1388 } else {
1389 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1390 dw_addr = get_dw_address(ctx, reg, NULL, NULL, dw_addr);
1391 skip_lds_store = !sh_info->reads_perpatch_outputs;
1392
1393 if (!reg->Register.Indirect) {
1394 int name = sh_info->output_semantic_name[reg->Register.Index];
1395
1396 /* Always write tess factors into LDS for the TCS epilog. */
1397 if (name == TGSI_SEMANTIC_TESSINNER ||
1398 name == TGSI_SEMANTIC_TESSOUTER) {
1399 /* The epilog doesn't read LDS if invocation 0 defines tess factors. */
1400 skip_lds_store = !sh_info->reads_tessfactor_outputs &&
1401 ctx->shader->selector->tcs_info.tessfactors_are_def_in_all_invocs;
1402 is_tess_factor = true;
1403 is_tess_inner = name == TGSI_SEMANTIC_TESSINNER;
1404 }
1405 }
1406 }
1407
1408 buffer = desc_from_addr_base64k(ctx, ctx->param_tcs_offchip_addr_base64k);
1409
1410 base = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
1411 buf_addr = get_tcs_tes_buffer_address_from_reg(ctx, reg, NULL);
1412
1413 uint32_t writemask = reg->Register.WriteMask;
1414 while (writemask) {
1415 chan_index = u_bit_scan(&writemask);
1416 LLVMValueRef value = dst[chan_index];
1417
1418 if (inst->Instruction.Saturate)
1419 value = ac_build_clamp(&ctx->ac, value);
1420
1421 /* Skip LDS stores if there is no LDS read of this output. */
1422 if (!skip_lds_store)
1423 lds_store(ctx, chan_index, dw_addr, value);
1424
1425 value = ac_to_integer(&ctx->ac, value);
1426 values[chan_index] = value;
1427
1428 if (reg->Register.WriteMask != 0xF && !is_tess_factor) {
1429 ac_build_buffer_store_dword(&ctx->ac, buffer, value, 1,
1430 buf_addr, base,
1431 4 * chan_index, 1, 0, true, false);
1432 }
1433
1434 /* Write tess factors into VGPRs for the epilog. */
1435 if (is_tess_factor &&
1436 ctx->shader->selector->tcs_info.tessfactors_are_def_in_all_invocs) {
1437 if (!is_tess_inner) {
1438 LLVMBuildStore(ctx->ac.builder, value, /* outer */
1439 ctx->invoc0_tess_factors[chan_index]);
1440 } else if (chan_index < 2) {
1441 LLVMBuildStore(ctx->ac.builder, value, /* inner */
1442 ctx->invoc0_tess_factors[4 + chan_index]);
1443 }
1444 }
1445 }
1446
1447 if (reg->Register.WriteMask == 0xF && !is_tess_factor) {
1448 LLVMValueRef value = lp_build_gather_values(&ctx->gallivm,
1449 values, 4);
1450 ac_build_buffer_store_dword(&ctx->ac, buffer, value, 4, buf_addr,
1451 base, 0, 1, 0, true, false);
1452 }
1453 }
1454
1455 static void si_nir_store_output_tcs(struct ac_shader_abi *abi,
1456 LLVMValueRef vertex_index,
1457 LLVMValueRef param_index,
1458 unsigned const_index,
1459 unsigned location,
1460 unsigned driver_location,
1461 LLVMValueRef src,
1462 unsigned component,
1463 bool is_patch,
1464 bool is_compact,
1465 unsigned writemask)
1466 {
1467 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1468 struct tgsi_shader_info *info = &ctx->shader->selector->info;
1469 LLVMValueRef dw_addr, stride;
1470 LLVMValueRef buffer, base, addr;
1471 LLVMValueRef values[4];
1472 bool skip_lds_store;
1473 bool is_tess_factor = false, is_tess_inner = false;
1474
1475 driver_location = driver_location / 4;
1476
1477 if (param_index) {
1478 /* Add the constant index to the indirect index */
1479 param_index = LLVMBuildAdd(ctx->ac.builder, param_index,
1480 LLVMConstInt(ctx->i32, const_index, 0), "");
1481 } else {
1482 if (const_index != 0)
1483 param_index = LLVMConstInt(ctx->i32, const_index, 0);
1484 }
1485
1486 if (!is_patch) {
1487 stride = get_tcs_out_vertex_dw_stride(ctx);
1488 dw_addr = get_tcs_out_current_patch_offset(ctx);
1489 dw_addr = get_dw_address_from_generic_indices(ctx, stride, dw_addr,
1490 vertex_index, param_index,
1491 driver_location,
1492 info->output_semantic_name,
1493 info->output_semantic_index,
1494 is_patch);
1495
1496 skip_lds_store = !info->reads_pervertex_outputs;
1497 } else {
1498 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1499 dw_addr = get_dw_address_from_generic_indices(ctx, NULL, dw_addr,
1500 vertex_index, param_index,
1501 driver_location,
1502 info->output_semantic_name,
1503 info->output_semantic_index,
1504 is_patch);
1505
1506 skip_lds_store = !info->reads_perpatch_outputs;
1507
1508 if (!param_index) {
1509 int name = info->output_semantic_name[driver_location];
1510
1511 /* Always write tess factors into LDS for the TCS epilog. */
1512 if (name == TGSI_SEMANTIC_TESSINNER ||
1513 name == TGSI_SEMANTIC_TESSOUTER) {
1514 /* The epilog doesn't read LDS if invocation 0 defines tess factors. */
1515 skip_lds_store = !info->reads_tessfactor_outputs &&
1516 ctx->shader->selector->tcs_info.tessfactors_are_def_in_all_invocs;
1517 is_tess_factor = true;
1518 is_tess_inner = name == TGSI_SEMANTIC_TESSINNER;
1519 }
1520 }
1521 }
1522
1523 buffer = desc_from_addr_base64k(ctx, ctx->param_tcs_offchip_addr_base64k);
1524
1525 base = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
1526
1527 addr = get_tcs_tes_buffer_address_from_generic_indices(ctx, vertex_index,
1528 param_index, driver_location,
1529 info->output_semantic_name,
1530 info->output_semantic_index,
1531 is_patch);
1532
1533 for (unsigned chan = 0; chan < 4; chan++) {
1534 if (!(writemask & (1 << chan)))
1535 continue;
1536 LLVMValueRef value = ac_llvm_extract_elem(&ctx->ac, src, chan - component);
1537
1538 /* Skip LDS stores if there is no LDS read of this output. */
1539 if (!skip_lds_store)
1540 ac_lds_store(&ctx->ac, dw_addr, value);
1541
1542 value = ac_to_integer(&ctx->ac, value);
1543 values[chan] = value;
1544
1545 if (writemask != 0xF && !is_tess_factor) {
1546 ac_build_buffer_store_dword(&ctx->ac, buffer, value, 1,
1547 addr, base,
1548 4 * chan, 1, 0, true, false);
1549 }
1550
1551 /* Write tess factors into VGPRs for the epilog. */
1552 if (is_tess_factor &&
1553 ctx->shader->selector->tcs_info.tessfactors_are_def_in_all_invocs) {
1554 if (!is_tess_inner) {
1555 LLVMBuildStore(ctx->ac.builder, value, /* outer */
1556 ctx->invoc0_tess_factors[chan]);
1557 } else if (chan < 2) {
1558 LLVMBuildStore(ctx->ac.builder, value, /* inner */
1559 ctx->invoc0_tess_factors[4 + chan]);
1560 }
1561 }
1562 }
1563
1564 if (writemask == 0xF && !is_tess_factor) {
1565 LLVMValueRef value = lp_build_gather_values(&ctx->gallivm,
1566 values, 4);
1567 ac_build_buffer_store_dword(&ctx->ac, buffer, value, 4, addr,
1568 base, 0, 1, 0, true, false);
1569 }
1570 }
1571
1572 LLVMValueRef si_llvm_load_input_gs(struct ac_shader_abi *abi,
1573 unsigned input_index,
1574 unsigned vtx_offset_param,
1575 LLVMTypeRef type,
1576 unsigned swizzle)
1577 {
1578 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1579 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
1580 struct si_shader *shader = ctx->shader;
1581 struct lp_build_context *uint = &ctx->bld_base.uint_bld;
1582 LLVMValueRef vtx_offset, soffset;
1583 struct tgsi_shader_info *info = &shader->selector->info;
1584 unsigned semantic_name = info->input_semantic_name[input_index];
1585 unsigned semantic_index = info->input_semantic_index[input_index];
1586 unsigned param;
1587 LLVMValueRef value;
1588
1589 param = si_shader_io_get_unique_index(semantic_name, semantic_index);
1590
1591 /* GFX9 has the ESGS ring in LDS. */
1592 if (ctx->screen->info.chip_class >= GFX9) {
1593 unsigned index = vtx_offset_param;
1594
1595 switch (index / 2) {
1596 case 0:
1597 vtx_offset = unpack_param(ctx, ctx->param_gs_vtx01_offset,
1598 index % 2 ? 16 : 0, 16);
1599 break;
1600 case 1:
1601 vtx_offset = unpack_param(ctx, ctx->param_gs_vtx23_offset,
1602 index % 2 ? 16 : 0, 16);
1603 break;
1604 case 2:
1605 vtx_offset = unpack_param(ctx, ctx->param_gs_vtx45_offset,
1606 index % 2 ? 16 : 0, 16);
1607 break;
1608 default:
1609 assert(0);
1610 return NULL;
1611 }
1612
1613 vtx_offset = LLVMBuildAdd(ctx->ac.builder, vtx_offset,
1614 LLVMConstInt(ctx->i32, param * 4, 0), "");
1615 return lds_load(bld_base, type, swizzle, vtx_offset);
1616 }
1617
1618 /* GFX6: input load from the ESGS ring in memory. */
1619 if (swizzle == ~0) {
1620 LLVMValueRef values[TGSI_NUM_CHANNELS];
1621 unsigned chan;
1622 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1623 values[chan] = si_llvm_load_input_gs(abi, input_index, vtx_offset_param,
1624 type, chan);
1625 }
1626 return lp_build_gather_values(&ctx->gallivm, values,
1627 TGSI_NUM_CHANNELS);
1628 }
1629
1630 /* Get the vertex offset parameter on GFX6. */
1631 LLVMValueRef gs_vtx_offset = ctx->gs_vtx_offset[vtx_offset_param];
1632
1633 vtx_offset = lp_build_mul_imm(uint, gs_vtx_offset, 4);
1634
1635 soffset = LLVMConstInt(ctx->i32, (param * 4 + swizzle) * 256, 0);
1636
1637 value = ac_build_buffer_load(&ctx->ac, ctx->esgs_ring, 1, ctx->i32_0,
1638 vtx_offset, soffset, 0, 1, 0, true, false);
1639 if (llvm_type_is_64bit(ctx, type)) {
1640 LLVMValueRef value2;
1641 soffset = LLVMConstInt(ctx->i32, (param * 4 + swizzle + 1) * 256, 0);
1642
1643 value2 = ac_build_buffer_load(&ctx->ac, ctx->esgs_ring, 1,
1644 ctx->i32_0, vtx_offset, soffset,
1645 0, 1, 0, true, false);
1646 return si_llvm_emit_fetch_64bit(bld_base, type, value, value2);
1647 }
1648 return LLVMBuildBitCast(ctx->ac.builder, value, type, "");
1649 }
1650
1651 static LLVMValueRef fetch_input_gs(
1652 struct lp_build_tgsi_context *bld_base,
1653 const struct tgsi_full_src_register *reg,
1654 enum tgsi_opcode_type type,
1655 unsigned swizzle)
1656 {
1657 struct si_shader_context *ctx = si_shader_context(bld_base);
1658 struct tgsi_shader_info *info = &ctx->shader->selector->info;
1659
1660 unsigned semantic_name = info->input_semantic_name[reg->Register.Index];
1661 if (swizzle != ~0 && semantic_name == TGSI_SEMANTIC_PRIMID)
1662 return get_primitive_id(ctx, swizzle);
1663
1664 if (!reg->Register.Dimension)
1665 return NULL;
1666
1667 return si_llvm_load_input_gs(&ctx->abi, reg->Register.Index,
1668 reg->Dimension.Index,
1669 tgsi2llvmtype(bld_base, type),
1670 swizzle);
1671 }
1672
1673 static int lookup_interp_param_index(unsigned interpolate, unsigned location)
1674 {
1675 switch (interpolate) {
1676 case TGSI_INTERPOLATE_CONSTANT:
1677 return 0;
1678
1679 case TGSI_INTERPOLATE_LINEAR:
1680 if (location == TGSI_INTERPOLATE_LOC_SAMPLE)
1681 return SI_PARAM_LINEAR_SAMPLE;
1682 else if (location == TGSI_INTERPOLATE_LOC_CENTROID)
1683 return SI_PARAM_LINEAR_CENTROID;
1684 else
1685 return SI_PARAM_LINEAR_CENTER;
1686 break;
1687 case TGSI_INTERPOLATE_COLOR:
1688 case TGSI_INTERPOLATE_PERSPECTIVE:
1689 if (location == TGSI_INTERPOLATE_LOC_SAMPLE)
1690 return SI_PARAM_PERSP_SAMPLE;
1691 else if (location == TGSI_INTERPOLATE_LOC_CENTROID)
1692 return SI_PARAM_PERSP_CENTROID;
1693 else
1694 return SI_PARAM_PERSP_CENTER;
1695 break;
1696 default:
1697 fprintf(stderr, "Warning: Unhandled interpolation mode.\n");
1698 return -1;
1699 }
1700 }
1701
1702 static LLVMValueRef si_build_fs_interp(struct si_shader_context *ctx,
1703 unsigned attr_index, unsigned chan,
1704 LLVMValueRef prim_mask,
1705 LLVMValueRef i, LLVMValueRef j)
1706 {
1707 if (i || j) {
1708 return ac_build_fs_interp(&ctx->ac,
1709 LLVMConstInt(ctx->i32, chan, 0),
1710 LLVMConstInt(ctx->i32, attr_index, 0),
1711 prim_mask, i, j);
1712 }
1713 return ac_build_fs_interp_mov(&ctx->ac,
1714 LLVMConstInt(ctx->i32, 2, 0), /* P0 */
1715 LLVMConstInt(ctx->i32, chan, 0),
1716 LLVMConstInt(ctx->i32, attr_index, 0),
1717 prim_mask);
1718 }
1719
1720 /**
1721 * Interpolate a fragment shader input.
1722 *
1723 * @param ctx context
1724 * @param input_index index of the input in hardware
1725 * @param semantic_name TGSI_SEMANTIC_*
1726 * @param semantic_index semantic index
1727 * @param num_interp_inputs number of all interpolated inputs (= BCOLOR offset)
1728 * @param colors_read_mask color components read (4 bits for each color, 8 bits in total)
1729 * @param interp_param interpolation weights (i,j)
1730 * @param prim_mask SI_PARAM_PRIM_MASK
1731 * @param face SI_PARAM_FRONT_FACE
1732 * @param result the return value (4 components)
1733 */
1734 static void interp_fs_input(struct si_shader_context *ctx,
1735 unsigned input_index,
1736 unsigned semantic_name,
1737 unsigned semantic_index,
1738 unsigned num_interp_inputs,
1739 unsigned colors_read_mask,
1740 LLVMValueRef interp_param,
1741 LLVMValueRef prim_mask,
1742 LLVMValueRef face,
1743 LLVMValueRef result[4])
1744 {
1745 LLVMValueRef i = NULL, j = NULL;
1746 unsigned chan;
1747
1748 /* fs.constant returns the param from the middle vertex, so it's not
1749 * really useful for flat shading. It's meant to be used for custom
1750 * interpolation (but the intrinsic can't fetch from the other two
1751 * vertices).
1752 *
1753 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
1754 * to do the right thing. The only reason we use fs.constant is that
1755 * fs.interp cannot be used on integers, because they can be equal
1756 * to NaN.
1757 *
1758 * When interp is false we will use fs.constant or for newer llvm,
1759 * amdgcn.interp.mov.
1760 */
1761 bool interp = interp_param != NULL;
1762
1763 if (interp) {
1764 interp_param = LLVMBuildBitCast(ctx->ac.builder, interp_param,
1765 LLVMVectorType(ctx->f32, 2), "");
1766
1767 i = LLVMBuildExtractElement(ctx->ac.builder, interp_param,
1768 ctx->i32_0, "");
1769 j = LLVMBuildExtractElement(ctx->ac.builder, interp_param,
1770 ctx->i32_1, "");
1771 }
1772
1773 if (semantic_name == TGSI_SEMANTIC_COLOR &&
1774 ctx->shader->key.part.ps.prolog.color_two_side) {
1775 LLVMValueRef is_face_positive;
1776
1777 /* If BCOLOR0 is used, BCOLOR1 is at offset "num_inputs + 1",
1778 * otherwise it's at offset "num_inputs".
1779 */
1780 unsigned back_attr_offset = num_interp_inputs;
1781 if (semantic_index == 1 && colors_read_mask & 0xf)
1782 back_attr_offset += 1;
1783
1784 is_face_positive = LLVMBuildICmp(ctx->ac.builder, LLVMIntNE,
1785 face, ctx->i32_0, "");
1786
1787 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1788 LLVMValueRef front, back;
1789
1790 front = si_build_fs_interp(ctx,
1791 input_index, chan,
1792 prim_mask, i, j);
1793 back = si_build_fs_interp(ctx,
1794 back_attr_offset, chan,
1795 prim_mask, i, j);
1796
1797 result[chan] = LLVMBuildSelect(ctx->ac.builder,
1798 is_face_positive,
1799 front,
1800 back,
1801 "");
1802 }
1803 } else if (semantic_name == TGSI_SEMANTIC_FOG) {
1804 result[0] = si_build_fs_interp(ctx, input_index,
1805 0, prim_mask, i, j);
1806 result[1] =
1807 result[2] = LLVMConstReal(ctx->f32, 0.0f);
1808 result[3] = LLVMConstReal(ctx->f32, 1.0f);
1809 } else {
1810 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1811 result[chan] = si_build_fs_interp(ctx,
1812 input_index, chan,
1813 prim_mask, i, j);
1814 }
1815 }
1816 }
1817
1818 void si_llvm_load_input_fs(
1819 struct si_shader_context *ctx,
1820 unsigned input_index,
1821 LLVMValueRef out[4])
1822 {
1823 struct lp_build_context *base = &ctx->bld_base.base;
1824 struct si_shader *shader = ctx->shader;
1825 struct tgsi_shader_info *info = &shader->selector->info;
1826 LLVMValueRef main_fn = ctx->main_fn;
1827 LLVMValueRef interp_param = NULL;
1828 int interp_param_idx;
1829 enum tgsi_semantic semantic_name = info->input_semantic_name[input_index];
1830 unsigned semantic_index = info->input_semantic_index[input_index];
1831 enum tgsi_interpolate_mode interp_mode = info->input_interpolate[input_index];
1832 enum tgsi_interpolate_loc interp_loc = info->input_interpolate_loc[input_index];
1833
1834 /* Get colors from input VGPRs (set by the prolog). */
1835 if (semantic_name == TGSI_SEMANTIC_COLOR) {
1836 unsigned colors_read = shader->selector->info.colors_read;
1837 unsigned mask = colors_read >> (semantic_index * 4);
1838 unsigned offset = SI_PARAM_POS_FIXED_PT + 1 +
1839 (semantic_index ? util_bitcount(colors_read & 0xf) : 0);
1840
1841 out[0] = mask & 0x1 ? LLVMGetParam(main_fn, offset++) : base->undef;
1842 out[1] = mask & 0x2 ? LLVMGetParam(main_fn, offset++) : base->undef;
1843 out[2] = mask & 0x4 ? LLVMGetParam(main_fn, offset++) : base->undef;
1844 out[3] = mask & 0x8 ? LLVMGetParam(main_fn, offset++) : base->undef;
1845 return;
1846 }
1847
1848 interp_param_idx = lookup_interp_param_index(interp_mode, interp_loc);
1849 if (interp_param_idx == -1)
1850 return;
1851 else if (interp_param_idx) {
1852 interp_param = LLVMGetParam(ctx->main_fn, interp_param_idx);
1853 }
1854
1855 interp_fs_input(ctx, input_index, semantic_name,
1856 semantic_index, 0, /* this param is unused */
1857 shader->selector->info.colors_read, interp_param,
1858 ctx->abi.prim_mask,
1859 LLVMGetParam(main_fn, SI_PARAM_FRONT_FACE),
1860 &out[0]);
1861 }
1862
1863 static void declare_input_fs(
1864 struct si_shader_context *ctx,
1865 unsigned input_index,
1866 const struct tgsi_full_declaration *decl,
1867 LLVMValueRef out[4])
1868 {
1869 si_llvm_load_input_fs(ctx, input_index, out);
1870 }
1871
1872 static LLVMValueRef get_sample_id(struct si_shader_context *ctx)
1873 {
1874 return unpack_param(ctx, SI_PARAM_ANCILLARY, 8, 4);
1875 }
1876
1877
1878 /**
1879 * Load a dword from a constant buffer.
1880 */
1881 static LLVMValueRef buffer_load_const(struct si_shader_context *ctx,
1882 LLVMValueRef resource,
1883 LLVMValueRef offset)
1884 {
1885 return ac_build_buffer_load(&ctx->ac, resource, 1, NULL, offset, NULL,
1886 0, 0, 0, true, true);
1887 }
1888
1889 static LLVMValueRef load_sample_position(struct ac_shader_abi *abi, LLVMValueRef sample_id)
1890 {
1891 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1892 struct lp_build_context *uint_bld = &ctx->bld_base.uint_bld;
1893 LLVMValueRef desc = LLVMGetParam(ctx->main_fn, ctx->param_rw_buffers);
1894 LLVMValueRef buf_index = LLVMConstInt(ctx->i32, SI_PS_CONST_SAMPLE_POSITIONS, 0);
1895 LLVMValueRef resource = ac_build_load_to_sgpr(&ctx->ac, desc, buf_index);
1896
1897 /* offset = sample_id * 8 (8 = 2 floats containing samplepos.xy) */
1898 LLVMValueRef offset0 = lp_build_mul_imm(uint_bld, sample_id, 8);
1899 LLVMValueRef offset1 = LLVMBuildAdd(ctx->ac.builder, offset0, LLVMConstInt(ctx->i32, 4, 0), "");
1900
1901 LLVMValueRef pos[4] = {
1902 buffer_load_const(ctx, resource, offset0),
1903 buffer_load_const(ctx, resource, offset1),
1904 LLVMConstReal(ctx->f32, 0),
1905 LLVMConstReal(ctx->f32, 0)
1906 };
1907
1908 return lp_build_gather_values(&ctx->gallivm, pos, 4);
1909 }
1910
1911 static LLVMValueRef si_load_tess_coord(struct ac_shader_abi *abi,
1912 LLVMTypeRef type,
1913 unsigned num_components)
1914 {
1915 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1916 struct lp_build_context *bld = &ctx->bld_base.base;
1917
1918 LLVMValueRef coord[4] = {
1919 LLVMGetParam(ctx->main_fn, ctx->param_tes_u),
1920 LLVMGetParam(ctx->main_fn, ctx->param_tes_v),
1921 ctx->ac.f32_0,
1922 ctx->ac.f32_0
1923 };
1924
1925 /* For triangles, the vector should be (u, v, 1-u-v). */
1926 if (ctx->shader->selector->info.properties[TGSI_PROPERTY_TES_PRIM_MODE] ==
1927 PIPE_PRIM_TRIANGLES)
1928 coord[2] = lp_build_sub(bld, ctx->ac.f32_1,
1929 lp_build_add(bld, coord[0], coord[1]));
1930
1931 return lp_build_gather_values(&ctx->gallivm, coord, 4);
1932 }
1933
1934 static LLVMValueRef load_tess_level(struct si_shader_context *ctx,
1935 unsigned semantic_name)
1936 {
1937 LLVMValueRef buffer, base, addr;
1938
1939 int param = si_shader_io_get_unique_index_patch(semantic_name, 0);
1940
1941 buffer = desc_from_addr_base64k(ctx, ctx->param_tcs_offchip_addr_base64k);
1942
1943 base = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
1944 addr = get_tcs_tes_buffer_address(ctx, get_rel_patch_id(ctx), NULL,
1945 LLVMConstInt(ctx->i32, param, 0));
1946
1947 return buffer_load(&ctx->bld_base, ctx->f32,
1948 ~0, buffer, base, addr, true);
1949
1950 }
1951
1952 static LLVMValueRef si_load_tess_level(struct ac_shader_abi *abi,
1953 unsigned varying_id)
1954 {
1955 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1956 unsigned semantic_name;
1957
1958 switch (varying_id) {
1959 case VARYING_SLOT_TESS_LEVEL_INNER:
1960 semantic_name = TGSI_SEMANTIC_TESSINNER;
1961 break;
1962 case VARYING_SLOT_TESS_LEVEL_OUTER:
1963 semantic_name = TGSI_SEMANTIC_TESSOUTER;
1964 break;
1965 default:
1966 unreachable("unknown tess level");
1967 }
1968
1969 return load_tess_level(ctx, semantic_name);
1970
1971 }
1972
1973 static LLVMValueRef si_load_patch_vertices_in(struct ac_shader_abi *abi)
1974 {
1975 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1976 if (ctx->type == PIPE_SHADER_TESS_CTRL)
1977 return unpack_param(ctx, ctx->param_tcs_out_lds_layout, 26, 6);
1978 else if (ctx->type == PIPE_SHADER_TESS_EVAL)
1979 return get_num_tcs_out_vertices(ctx);
1980 else
1981 unreachable("invalid shader stage for TGSI_SEMANTIC_VERTICESIN");
1982 }
1983
1984 void si_load_system_value(struct si_shader_context *ctx,
1985 unsigned index,
1986 const struct tgsi_full_declaration *decl)
1987 {
1988 LLVMValueRef value = 0;
1989
1990 assert(index < RADEON_LLVM_MAX_SYSTEM_VALUES);
1991
1992 switch (decl->Semantic.Name) {
1993 case TGSI_SEMANTIC_INSTANCEID:
1994 value = ctx->abi.instance_id;
1995 break;
1996
1997 case TGSI_SEMANTIC_VERTEXID:
1998 value = LLVMBuildAdd(ctx->ac.builder,
1999 ctx->abi.vertex_id,
2000 ctx->abi.base_vertex, "");
2001 break;
2002
2003 case TGSI_SEMANTIC_VERTEXID_NOBASE:
2004 /* Unused. Clarify the meaning in indexed vs. non-indexed
2005 * draws if this is ever used again. */
2006 assert(false);
2007 break;
2008
2009 case TGSI_SEMANTIC_BASEVERTEX:
2010 {
2011 /* For non-indexed draws, the base vertex set by the driver
2012 * (for direct draws) or the CP (for indirect draws) is the
2013 * first vertex ID, but GLSL expects 0 to be returned.
2014 */
2015 LLVMValueRef vs_state = LLVMGetParam(ctx->main_fn, ctx->param_vs_state_bits);
2016 LLVMValueRef indexed;
2017
2018 indexed = LLVMBuildLShr(ctx->ac.builder, vs_state, ctx->i32_1, "");
2019 indexed = LLVMBuildTrunc(ctx->ac.builder, indexed, ctx->i1, "");
2020
2021 value = LLVMBuildSelect(ctx->ac.builder, indexed,
2022 ctx->abi.base_vertex, ctx->i32_0, "");
2023 break;
2024 }
2025
2026 case TGSI_SEMANTIC_BASEINSTANCE:
2027 value = ctx->abi.start_instance;
2028 break;
2029
2030 case TGSI_SEMANTIC_DRAWID:
2031 value = ctx->abi.draw_id;
2032 break;
2033
2034 case TGSI_SEMANTIC_INVOCATIONID:
2035 if (ctx->type == PIPE_SHADER_TESS_CTRL)
2036 value = unpack_llvm_param(ctx, ctx->abi.tcs_rel_ids, 8, 5);
2037 else if (ctx->type == PIPE_SHADER_GEOMETRY)
2038 value = ctx->abi.gs_invocation_id;
2039 else
2040 assert(!"INVOCATIONID not implemented");
2041 break;
2042
2043 case TGSI_SEMANTIC_POSITION:
2044 {
2045 LLVMValueRef pos[4] = {
2046 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_X_FLOAT),
2047 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_Y_FLOAT),
2048 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_Z_FLOAT),
2049 lp_build_emit_llvm_unary(&ctx->bld_base, TGSI_OPCODE_RCP,
2050 LLVMGetParam(ctx->main_fn,
2051 SI_PARAM_POS_W_FLOAT)),
2052 };
2053 value = lp_build_gather_values(&ctx->gallivm, pos, 4);
2054 break;
2055 }
2056
2057 case TGSI_SEMANTIC_FACE:
2058 value = ctx->abi.front_face;
2059 break;
2060
2061 case TGSI_SEMANTIC_SAMPLEID:
2062 value = get_sample_id(ctx);
2063 break;
2064
2065 case TGSI_SEMANTIC_SAMPLEPOS: {
2066 LLVMValueRef pos[4] = {
2067 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_X_FLOAT),
2068 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_Y_FLOAT),
2069 LLVMConstReal(ctx->f32, 0),
2070 LLVMConstReal(ctx->f32, 0)
2071 };
2072 pos[0] = lp_build_emit_llvm_unary(&ctx->bld_base,
2073 TGSI_OPCODE_FRC, pos[0]);
2074 pos[1] = lp_build_emit_llvm_unary(&ctx->bld_base,
2075 TGSI_OPCODE_FRC, pos[1]);
2076 value = lp_build_gather_values(&ctx->gallivm, pos, 4);
2077 break;
2078 }
2079
2080 case TGSI_SEMANTIC_SAMPLEMASK:
2081 /* This can only occur with the OpenGL Core profile, which
2082 * doesn't support smoothing.
2083 */
2084 value = LLVMGetParam(ctx->main_fn, SI_PARAM_SAMPLE_COVERAGE);
2085 break;
2086
2087 case TGSI_SEMANTIC_TESSCOORD:
2088 value = si_load_tess_coord(&ctx->abi, NULL, 4);
2089 break;
2090
2091 case TGSI_SEMANTIC_VERTICESIN:
2092 value = si_load_patch_vertices_in(&ctx->abi);
2093 break;
2094
2095 case TGSI_SEMANTIC_TESSINNER:
2096 case TGSI_SEMANTIC_TESSOUTER:
2097 value = load_tess_level(ctx, decl->Semantic.Name);
2098 break;
2099
2100 case TGSI_SEMANTIC_DEFAULT_TESSOUTER_SI:
2101 case TGSI_SEMANTIC_DEFAULT_TESSINNER_SI:
2102 {
2103 LLVMValueRef buf, slot, val[4];
2104 int i, offset;
2105
2106 slot = LLVMConstInt(ctx->i32, SI_HS_CONST_DEFAULT_TESS_LEVELS, 0);
2107 buf = LLVMGetParam(ctx->main_fn, ctx->param_rw_buffers);
2108 buf = ac_build_load_to_sgpr(&ctx->ac, buf, slot);
2109 offset = decl->Semantic.Name == TGSI_SEMANTIC_DEFAULT_TESSINNER_SI ? 4 : 0;
2110
2111 for (i = 0; i < 4; i++)
2112 val[i] = buffer_load_const(ctx, buf,
2113 LLVMConstInt(ctx->i32, (offset + i) * 4, 0));
2114 value = lp_build_gather_values(&ctx->gallivm, val, 4);
2115 break;
2116 }
2117
2118 case TGSI_SEMANTIC_PRIMID:
2119 value = get_primitive_id(ctx, 0);
2120 break;
2121
2122 case TGSI_SEMANTIC_GRID_SIZE:
2123 value = LLVMGetParam(ctx->main_fn, ctx->param_grid_size);
2124 break;
2125
2126 case TGSI_SEMANTIC_BLOCK_SIZE:
2127 {
2128 LLVMValueRef values[3];
2129 unsigned i;
2130 unsigned *properties = ctx->shader->selector->info.properties;
2131
2132 if (properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] != 0) {
2133 unsigned sizes[3] = {
2134 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH],
2135 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT],
2136 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH]
2137 };
2138
2139 for (i = 0; i < 3; ++i)
2140 values[i] = LLVMConstInt(ctx->i32, sizes[i], 0);
2141
2142 value = lp_build_gather_values(&ctx->gallivm, values, 3);
2143 } else {
2144 value = LLVMGetParam(ctx->main_fn, ctx->param_block_size);
2145 }
2146 break;
2147 }
2148
2149 case TGSI_SEMANTIC_BLOCK_ID:
2150 {
2151 LLVMValueRef values[3];
2152
2153 for (int i = 0; i < 3; i++) {
2154 values[i] = ctx->i32_0;
2155 if (ctx->param_block_id[i] >= 0) {
2156 values[i] = LLVMGetParam(ctx->main_fn,
2157 ctx->param_block_id[i]);
2158 }
2159 }
2160 value = lp_build_gather_values(&ctx->gallivm, values, 3);
2161 break;
2162 }
2163
2164 case TGSI_SEMANTIC_THREAD_ID:
2165 value = LLVMGetParam(ctx->main_fn, ctx->param_thread_id);
2166 break;
2167
2168 case TGSI_SEMANTIC_HELPER_INVOCATION:
2169 value = lp_build_intrinsic(ctx->ac.builder,
2170 "llvm.amdgcn.ps.live",
2171 ctx->i1, NULL, 0,
2172 LP_FUNC_ATTR_READNONE);
2173 value = LLVMBuildNot(ctx->ac.builder, value, "");
2174 value = LLVMBuildSExt(ctx->ac.builder, value, ctx->i32, "");
2175 break;
2176
2177 case TGSI_SEMANTIC_SUBGROUP_SIZE:
2178 value = LLVMConstInt(ctx->i32, 64, 0);
2179 break;
2180
2181 case TGSI_SEMANTIC_SUBGROUP_INVOCATION:
2182 value = ac_get_thread_id(&ctx->ac);
2183 break;
2184
2185 case TGSI_SEMANTIC_SUBGROUP_EQ_MASK:
2186 {
2187 LLVMValueRef id = ac_get_thread_id(&ctx->ac);
2188 id = LLVMBuildZExt(ctx->ac.builder, id, ctx->i64, "");
2189 value = LLVMBuildShl(ctx->ac.builder, LLVMConstInt(ctx->i64, 1, 0), id, "");
2190 value = LLVMBuildBitCast(ctx->ac.builder, value, ctx->v2i32, "");
2191 break;
2192 }
2193
2194 case TGSI_SEMANTIC_SUBGROUP_GE_MASK:
2195 case TGSI_SEMANTIC_SUBGROUP_GT_MASK:
2196 case TGSI_SEMANTIC_SUBGROUP_LE_MASK:
2197 case TGSI_SEMANTIC_SUBGROUP_LT_MASK:
2198 {
2199 LLVMValueRef id = ac_get_thread_id(&ctx->ac);
2200 if (decl->Semantic.Name == TGSI_SEMANTIC_SUBGROUP_GT_MASK ||
2201 decl->Semantic.Name == TGSI_SEMANTIC_SUBGROUP_LE_MASK) {
2202 /* All bits set except LSB */
2203 value = LLVMConstInt(ctx->i64, -2, 0);
2204 } else {
2205 /* All bits set */
2206 value = LLVMConstInt(ctx->i64, -1, 0);
2207 }
2208 id = LLVMBuildZExt(ctx->ac.builder, id, ctx->i64, "");
2209 value = LLVMBuildShl(ctx->ac.builder, value, id, "");
2210 if (decl->Semantic.Name == TGSI_SEMANTIC_SUBGROUP_LE_MASK ||
2211 decl->Semantic.Name == TGSI_SEMANTIC_SUBGROUP_LT_MASK)
2212 value = LLVMBuildNot(ctx->ac.builder, value, "");
2213 value = LLVMBuildBitCast(ctx->ac.builder, value, ctx->v2i32, "");
2214 break;
2215 }
2216
2217 default:
2218 assert(!"unknown system value");
2219 return;
2220 }
2221
2222 ctx->system_values[index] = value;
2223 }
2224
2225 void si_declare_compute_memory(struct si_shader_context *ctx,
2226 const struct tgsi_full_declaration *decl)
2227 {
2228 struct si_shader_selector *sel = ctx->shader->selector;
2229
2230 LLVMTypeRef i8p = LLVMPointerType(ctx->i8, AC_LOCAL_ADDR_SPACE);
2231 LLVMValueRef var;
2232
2233 assert(decl->Declaration.MemType == TGSI_MEMORY_TYPE_SHARED);
2234 assert(decl->Range.First == decl->Range.Last);
2235 assert(!ctx->ac.lds);
2236
2237 var = LLVMAddGlobalInAddressSpace(ctx->ac.module,
2238 LLVMArrayType(ctx->i8, sel->local_size),
2239 "compute_lds",
2240 AC_LOCAL_ADDR_SPACE);
2241 LLVMSetAlignment(var, 4);
2242
2243 ctx->ac.lds = LLVMBuildBitCast(ctx->ac.builder, var, i8p, "");
2244 }
2245
2246 static LLVMValueRef load_const_buffer_desc(struct si_shader_context *ctx, int i)
2247 {
2248 LLVMValueRef list_ptr = LLVMGetParam(ctx->main_fn,
2249 ctx->param_const_and_shader_buffers);
2250
2251 return ac_build_load_to_sgpr(&ctx->ac, list_ptr,
2252 LLVMConstInt(ctx->i32, si_get_constbuf_slot(i), 0));
2253 }
2254
2255 static LLVMValueRef load_ubo(struct ac_shader_abi *abi, LLVMValueRef index)
2256 {
2257 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
2258 LLVMValueRef ptr = LLVMGetParam(ctx->main_fn, ctx->param_const_and_shader_buffers);
2259
2260 index = si_llvm_bound_index(ctx, index, ctx->num_const_buffers);
2261 index = LLVMBuildAdd(ctx->ac.builder, index,
2262 LLVMConstInt(ctx->i32, SI_NUM_SHADER_BUFFERS, 0), "");
2263
2264 return ac_build_load_to_sgpr(&ctx->ac, ptr, index);
2265 }
2266
2267 static LLVMValueRef
2268 load_ssbo(struct ac_shader_abi *abi, LLVMValueRef index, bool write)
2269 {
2270 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
2271 LLVMValueRef rsrc_ptr = LLVMGetParam(ctx->main_fn,
2272 ctx->param_const_and_shader_buffers);
2273
2274 index = si_llvm_bound_index(ctx, index, ctx->num_shader_buffers);
2275 index = LLVMBuildSub(ctx->ac.builder,
2276 LLVMConstInt(ctx->i32, SI_NUM_SHADER_BUFFERS - 1, 0),
2277 index, "");
2278
2279 return ac_build_load_to_sgpr(&ctx->ac, rsrc_ptr, index);
2280 }
2281
2282 static LLVMValueRef fetch_constant(
2283 struct lp_build_tgsi_context *bld_base,
2284 const struct tgsi_full_src_register *reg,
2285 enum tgsi_opcode_type type,
2286 unsigned swizzle)
2287 {
2288 struct si_shader_context *ctx = si_shader_context(bld_base);
2289 struct si_shader_selector *sel = ctx->shader->selector;
2290 const struct tgsi_ind_register *ireg = &reg->Indirect;
2291 unsigned buf, idx;
2292
2293 LLVMValueRef addr, bufp;
2294
2295 if (swizzle == LP_CHAN_ALL) {
2296 unsigned chan;
2297 LLVMValueRef values[4];
2298 for (chan = 0; chan < TGSI_NUM_CHANNELS; ++chan)
2299 values[chan] = fetch_constant(bld_base, reg, type, chan);
2300
2301 return lp_build_gather_values(&ctx->gallivm, values, 4);
2302 }
2303
2304 /* Split 64-bit loads. */
2305 if (tgsi_type_is_64bit(type)) {
2306 LLVMValueRef lo, hi;
2307
2308 lo = fetch_constant(bld_base, reg, TGSI_TYPE_UNSIGNED, swizzle);
2309 hi = fetch_constant(bld_base, reg, TGSI_TYPE_UNSIGNED, swizzle + 1);
2310 return si_llvm_emit_fetch_64bit(bld_base, tgsi2llvmtype(bld_base, type),
2311 lo, hi);
2312 }
2313
2314 idx = reg->Register.Index * 4 + swizzle;
2315 if (reg->Register.Indirect) {
2316 addr = si_get_indirect_index(ctx, ireg, 16, idx * 4);
2317 } else {
2318 addr = LLVMConstInt(ctx->i32, idx * 4, 0);
2319 }
2320
2321 /* Fast path when user data SGPRs point to constant buffer 0 directly. */
2322 if (sel->info.const_buffers_declared == 1 &&
2323 sel->info.shader_buffers_declared == 0) {
2324 LLVMValueRef ptr =
2325 LLVMGetParam(ctx->main_fn, ctx->param_const_and_shader_buffers);
2326
2327 /* This enables use of s_load_dword and flat_load_dword for const buffer 0
2328 * loads, and up to x4 load opcode merging. However, it leads to horrible
2329 * code reducing SIMD wave occupancy from 8 to 2 in many cases.
2330 *
2331 * Using s_buffer_load_dword (x1) seems to be the best option right now.
2332 *
2333 * LLVM 5.0 on SI doesn't insert a required s_nop between SALU setting
2334 * a descriptor and s_buffer_load_dword using it, so we can't expand
2335 * the pointer into a full descriptor like below. We have to use
2336 * s_load_dword instead. The only case when LLVM 5.0 would select
2337 * s_buffer_load_dword (that we have to prevent) is when we use use
2338 * a literal offset where we don't need bounds checking.
2339 */
2340 if (ctx->screen->info.chip_class == SI &&
2341 HAVE_LLVM < 0x0600 &&
2342 !reg->Register.Indirect) {
2343 addr = LLVMBuildLShr(ctx->ac.builder, addr, LLVMConstInt(ctx->i32, 2, 0), "");
2344 LLVMValueRef result = ac_build_load_invariant(&ctx->ac, ptr, addr);
2345 return bitcast(bld_base, type, result);
2346 }
2347
2348 /* Do the bounds checking with a descriptor, because
2349 * doing computation and manual bounds checking of 64-bit
2350 * addresses generates horrible VALU code with very high
2351 * VGPR usage and very low SIMD occupancy.
2352 */
2353 ptr = LLVMBuildPtrToInt(ctx->ac.builder, ptr, ctx->i64, "");
2354 ptr = LLVMBuildBitCast(ctx->ac.builder, ptr, ctx->v2i32, "");
2355
2356 LLVMValueRef desc_elems[] = {
2357 LLVMBuildExtractElement(ctx->ac.builder, ptr, ctx->i32_0, ""),
2358 LLVMBuildExtractElement(ctx->ac.builder, ptr, ctx->i32_1, ""),
2359 LLVMConstInt(ctx->i32, (sel->info.const_file_max[0] + 1) * 16, 0),
2360 LLVMConstInt(ctx->i32,
2361 S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2362 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2363 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2364 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2365 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2366 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32), 0)
2367 };
2368 LLVMValueRef desc = ac_build_gather_values(&ctx->ac, desc_elems, 4);
2369 LLVMValueRef result = buffer_load_const(ctx, desc, addr);
2370 return bitcast(bld_base, type, result);
2371 }
2372
2373 assert(reg->Register.Dimension);
2374 buf = reg->Dimension.Index;
2375
2376 if (reg->Dimension.Indirect) {
2377 LLVMValueRef ptr = LLVMGetParam(ctx->main_fn, ctx->param_const_and_shader_buffers);
2378 LLVMValueRef index;
2379 index = si_get_bounded_indirect_index(ctx, &reg->DimIndirect,
2380 reg->Dimension.Index,
2381 ctx->num_const_buffers);
2382 index = LLVMBuildAdd(ctx->ac.builder, index,
2383 LLVMConstInt(ctx->i32, SI_NUM_SHADER_BUFFERS, 0), "");
2384 bufp = ac_build_load_to_sgpr(&ctx->ac, ptr, index);
2385 } else
2386 bufp = load_const_buffer_desc(ctx, buf);
2387
2388 return bitcast(bld_base, type, buffer_load_const(ctx, bufp, addr));
2389 }
2390
2391 /* Upper 16 bits must be zero. */
2392 static LLVMValueRef si_llvm_pack_two_int16(struct si_shader_context *ctx,
2393 LLVMValueRef val[2])
2394 {
2395 return LLVMBuildOr(ctx->ac.builder, val[0],
2396 LLVMBuildShl(ctx->ac.builder, val[1],
2397 LLVMConstInt(ctx->i32, 16, 0),
2398 ""), "");
2399 }
2400
2401 /* Upper 16 bits are ignored and will be dropped. */
2402 static LLVMValueRef si_llvm_pack_two_int32_as_int16(struct si_shader_context *ctx,
2403 LLVMValueRef val[2])
2404 {
2405 LLVMValueRef v[2] = {
2406 LLVMBuildAnd(ctx->ac.builder, val[0],
2407 LLVMConstInt(ctx->i32, 0xffff, 0), ""),
2408 val[1],
2409 };
2410 return si_llvm_pack_two_int16(ctx, v);
2411 }
2412
2413 /* Initialize arguments for the shader export intrinsic */
2414 static void si_llvm_init_export_args(struct si_shader_context *ctx,
2415 LLVMValueRef *values,
2416 unsigned target,
2417 struct ac_export_args *args)
2418 {
2419 LLVMValueRef f32undef = LLVMGetUndef(ctx->ac.f32);
2420 LLVMBuilderRef builder = ctx->ac.builder;
2421 LLVMValueRef val[4];
2422 unsigned spi_shader_col_format = V_028714_SPI_SHADER_32_ABGR;
2423 unsigned chan;
2424 bool is_int8, is_int10;
2425
2426 /* Default is 0xf. Adjusted below depending on the format. */
2427 args->enabled_channels = 0xf; /* writemask */
2428
2429 /* Specify whether the EXEC mask represents the valid mask */
2430 args->valid_mask = 0;
2431
2432 /* Specify whether this is the last export */
2433 args->done = 0;
2434
2435 /* Specify the target we are exporting */
2436 args->target = target;
2437
2438 if (ctx->type == PIPE_SHADER_FRAGMENT) {
2439 const struct si_shader_key *key = &ctx->shader->key;
2440 unsigned col_formats = key->part.ps.epilog.spi_shader_col_format;
2441 int cbuf = target - V_008DFC_SQ_EXP_MRT;
2442
2443 assert(cbuf >= 0 && cbuf < 8);
2444 spi_shader_col_format = (col_formats >> (cbuf * 4)) & 0xf;
2445 is_int8 = (key->part.ps.epilog.color_is_int8 >> cbuf) & 0x1;
2446 is_int10 = (key->part.ps.epilog.color_is_int10 >> cbuf) & 0x1;
2447 }
2448
2449 args->compr = false;
2450 args->out[0] = f32undef;
2451 args->out[1] = f32undef;
2452 args->out[2] = f32undef;
2453 args->out[3] = f32undef;
2454
2455 switch (spi_shader_col_format) {
2456 case V_028714_SPI_SHADER_ZERO:
2457 args->enabled_channels = 0; /* writemask */
2458 args->target = V_008DFC_SQ_EXP_NULL;
2459 break;
2460
2461 case V_028714_SPI_SHADER_32_R:
2462 args->enabled_channels = 1; /* writemask */
2463 args->out[0] = values[0];
2464 break;
2465
2466 case V_028714_SPI_SHADER_32_GR:
2467 args->enabled_channels = 0x3; /* writemask */
2468 args->out[0] = values[0];
2469 args->out[1] = values[1];
2470 break;
2471
2472 case V_028714_SPI_SHADER_32_AR:
2473 args->enabled_channels = 0x9; /* writemask */
2474 args->out[0] = values[0];
2475 args->out[3] = values[3];
2476 break;
2477
2478 case V_028714_SPI_SHADER_FP16_ABGR:
2479 args->compr = 1; /* COMPR flag */
2480
2481 for (chan = 0; chan < 2; chan++) {
2482 LLVMValueRef pack_args[2] = {
2483 values[2 * chan],
2484 values[2 * chan + 1]
2485 };
2486 LLVMValueRef packed;
2487
2488 packed = ac_build_cvt_pkrtz_f16(&ctx->ac, pack_args);
2489 args->out[chan] = ac_to_float(&ctx->ac, packed);
2490 }
2491 break;
2492
2493 case V_028714_SPI_SHADER_UNORM16_ABGR:
2494 for (chan = 0; chan < 4; chan++) {
2495 val[chan] = ac_build_clamp(&ctx->ac, values[chan]);
2496 val[chan] = LLVMBuildFMul(builder, val[chan],
2497 LLVMConstReal(ctx->f32, 65535), "");
2498 val[chan] = LLVMBuildFAdd(builder, val[chan],
2499 LLVMConstReal(ctx->f32, 0.5), "");
2500 val[chan] = LLVMBuildFPToUI(builder, val[chan],
2501 ctx->i32, "");
2502 }
2503
2504 args->compr = 1; /* COMPR flag */
2505 args->out[0] = ac_to_float(&ctx->ac, si_llvm_pack_two_int16(ctx, val));
2506 args->out[1] = ac_to_float(&ctx->ac, si_llvm_pack_two_int16(ctx, val+2));
2507 break;
2508
2509 case V_028714_SPI_SHADER_SNORM16_ABGR:
2510 for (chan = 0; chan < 4; chan++) {
2511 /* Clamp between [-1, 1]. */
2512 val[chan] = lp_build_emit_llvm_binary(&ctx->bld_base, TGSI_OPCODE_MIN,
2513 values[chan],
2514 LLVMConstReal(ctx->f32, 1));
2515 val[chan] = lp_build_emit_llvm_binary(&ctx->bld_base, TGSI_OPCODE_MAX,
2516 val[chan],
2517 LLVMConstReal(ctx->f32, -1));
2518 /* Convert to a signed integer in [-32767, 32767]. */
2519 val[chan] = LLVMBuildFMul(builder, val[chan],
2520 LLVMConstReal(ctx->f32, 32767), "");
2521 /* If positive, add 0.5, else add -0.5. */
2522 val[chan] = LLVMBuildFAdd(builder, val[chan],
2523 LLVMBuildSelect(builder,
2524 LLVMBuildFCmp(builder, LLVMRealOGE,
2525 val[chan], ctx->ac.f32_0, ""),
2526 LLVMConstReal(ctx->f32, 0.5),
2527 LLVMConstReal(ctx->f32, -0.5), ""), "");
2528 val[chan] = LLVMBuildFPToSI(builder, val[chan], ctx->i32, "");
2529 }
2530
2531 args->compr = 1; /* COMPR flag */
2532 args->out[0] = ac_to_float(&ctx->ac, si_llvm_pack_two_int32_as_int16(ctx, val));
2533 args->out[1] = ac_to_float(&ctx->ac, si_llvm_pack_two_int32_as_int16(ctx, val+2));
2534 break;
2535
2536 case V_028714_SPI_SHADER_UINT16_ABGR: {
2537 LLVMValueRef max_rgb = LLVMConstInt(ctx->i32,
2538 is_int8 ? 255 : is_int10 ? 1023 : 65535, 0);
2539 LLVMValueRef max_alpha =
2540 !is_int10 ? max_rgb : LLVMConstInt(ctx->i32, 3, 0);
2541
2542 /* Clamp. */
2543 for (chan = 0; chan < 4; chan++) {
2544 val[chan] = ac_to_integer(&ctx->ac, values[chan]);
2545 val[chan] = lp_build_emit_llvm_binary(&ctx->bld_base, TGSI_OPCODE_UMIN,
2546 val[chan],
2547 chan == 3 ? max_alpha : max_rgb);
2548 }
2549
2550 args->compr = 1; /* COMPR flag */
2551 args->out[0] = ac_to_float(&ctx->ac, si_llvm_pack_two_int16(ctx, val));
2552 args->out[1] = ac_to_float(&ctx->ac, si_llvm_pack_two_int16(ctx, val+2));
2553 break;
2554 }
2555
2556 case V_028714_SPI_SHADER_SINT16_ABGR: {
2557 LLVMValueRef max_rgb = LLVMConstInt(ctx->i32,
2558 is_int8 ? 127 : is_int10 ? 511 : 32767, 0);
2559 LLVMValueRef min_rgb = LLVMConstInt(ctx->i32,
2560 is_int8 ? -128 : is_int10 ? -512 : -32768, 0);
2561 LLVMValueRef max_alpha =
2562 !is_int10 ? max_rgb : ctx->i32_1;
2563 LLVMValueRef min_alpha =
2564 !is_int10 ? min_rgb : LLVMConstInt(ctx->i32, -2, 0);
2565
2566 /* Clamp. */
2567 for (chan = 0; chan < 4; chan++) {
2568 val[chan] = ac_to_integer(&ctx->ac, values[chan]);
2569 val[chan] = lp_build_emit_llvm_binary(&ctx->bld_base,
2570 TGSI_OPCODE_IMIN,
2571 val[chan], chan == 3 ? max_alpha : max_rgb);
2572 val[chan] = lp_build_emit_llvm_binary(&ctx->bld_base,
2573 TGSI_OPCODE_IMAX,
2574 val[chan], chan == 3 ? min_alpha : min_rgb);
2575 }
2576
2577 args->compr = 1; /* COMPR flag */
2578 args->out[0] = ac_to_float(&ctx->ac, si_llvm_pack_two_int32_as_int16(ctx, val));
2579 args->out[1] = ac_to_float(&ctx->ac, si_llvm_pack_two_int32_as_int16(ctx, val+2));
2580 break;
2581 }
2582
2583 case V_028714_SPI_SHADER_32_ABGR:
2584 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
2585 break;
2586 }
2587 }
2588
2589 static void si_alpha_test(struct lp_build_tgsi_context *bld_base,
2590 LLVMValueRef alpha)
2591 {
2592 struct si_shader_context *ctx = si_shader_context(bld_base);
2593
2594 if (ctx->shader->key.part.ps.epilog.alpha_func != PIPE_FUNC_NEVER) {
2595 static LLVMRealPredicate cond_map[PIPE_FUNC_ALWAYS + 1] = {
2596 [PIPE_FUNC_LESS] = LLVMRealOLT,
2597 [PIPE_FUNC_EQUAL] = LLVMRealOEQ,
2598 [PIPE_FUNC_LEQUAL] = LLVMRealOLE,
2599 [PIPE_FUNC_GREATER] = LLVMRealOGT,
2600 [PIPE_FUNC_NOTEQUAL] = LLVMRealONE,
2601 [PIPE_FUNC_GEQUAL] = LLVMRealOGE,
2602 };
2603 LLVMRealPredicate cond = cond_map[ctx->shader->key.part.ps.epilog.alpha_func];
2604 assert(cond);
2605
2606 LLVMValueRef alpha_ref = LLVMGetParam(ctx->main_fn,
2607 SI_PARAM_ALPHA_REF);
2608 LLVMValueRef alpha_pass =
2609 LLVMBuildFCmp(ctx->ac.builder, cond, alpha, alpha_ref, "");
2610 ac_build_kill_if_false(&ctx->ac, alpha_pass);
2611 } else {
2612 ac_build_kill_if_false(&ctx->ac, LLVMConstInt(ctx->i1, 0, 0));
2613 }
2614 }
2615
2616 static LLVMValueRef si_scale_alpha_by_sample_mask(struct lp_build_tgsi_context *bld_base,
2617 LLVMValueRef alpha,
2618 unsigned samplemask_param)
2619 {
2620 struct si_shader_context *ctx = si_shader_context(bld_base);
2621 LLVMValueRef coverage;
2622
2623 /* alpha = alpha * popcount(coverage) / SI_NUM_SMOOTH_AA_SAMPLES */
2624 coverage = LLVMGetParam(ctx->main_fn,
2625 samplemask_param);
2626 coverage = ac_to_integer(&ctx->ac, coverage);
2627
2628 coverage = lp_build_intrinsic(ctx->ac.builder, "llvm.ctpop.i32",
2629 ctx->i32,
2630 &coverage, 1, LP_FUNC_ATTR_READNONE);
2631
2632 coverage = LLVMBuildUIToFP(ctx->ac.builder, coverage,
2633 ctx->f32, "");
2634
2635 coverage = LLVMBuildFMul(ctx->ac.builder, coverage,
2636 LLVMConstReal(ctx->f32,
2637 1.0 / SI_NUM_SMOOTH_AA_SAMPLES), "");
2638
2639 return LLVMBuildFMul(ctx->ac.builder, alpha, coverage, "");
2640 }
2641
2642 static void si_llvm_emit_clipvertex(struct si_shader_context *ctx,
2643 struct ac_export_args *pos, LLVMValueRef *out_elts)
2644 {
2645 unsigned reg_index;
2646 unsigned chan;
2647 unsigned const_chan;
2648 LLVMValueRef base_elt;
2649 LLVMValueRef ptr = LLVMGetParam(ctx->main_fn, ctx->param_rw_buffers);
2650 LLVMValueRef constbuf_index = LLVMConstInt(ctx->i32,
2651 SI_VS_CONST_CLIP_PLANES, 0);
2652 LLVMValueRef const_resource = ac_build_load_to_sgpr(&ctx->ac, ptr, constbuf_index);
2653
2654 for (reg_index = 0; reg_index < 2; reg_index ++) {
2655 struct ac_export_args *args = &pos[2 + reg_index];
2656
2657 args->out[0] =
2658 args->out[1] =
2659 args->out[2] =
2660 args->out[3] = LLVMConstReal(ctx->f32, 0.0f);
2661
2662 /* Compute dot products of position and user clip plane vectors */
2663 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2664 for (const_chan = 0; const_chan < TGSI_NUM_CHANNELS; const_chan++) {
2665 LLVMValueRef addr =
2666 LLVMConstInt(ctx->i32, ((reg_index * 4 + chan) * 4 +
2667 const_chan) * 4, 0);
2668 base_elt = buffer_load_const(ctx, const_resource,
2669 addr);
2670 args->out[chan] =
2671 lp_build_add(&ctx->bld_base.base, args->out[chan],
2672 lp_build_mul(&ctx->bld_base.base, base_elt,
2673 out_elts[const_chan]));
2674 }
2675 }
2676
2677 args->enabled_channels = 0xf;
2678 args->valid_mask = 0;
2679 args->done = 0;
2680 args->target = V_008DFC_SQ_EXP_POS + 2 + reg_index;
2681 args->compr = 0;
2682 }
2683 }
2684
2685 static void si_dump_streamout(struct pipe_stream_output_info *so)
2686 {
2687 unsigned i;
2688
2689 if (so->num_outputs)
2690 fprintf(stderr, "STREAMOUT\n");
2691
2692 for (i = 0; i < so->num_outputs; i++) {
2693 unsigned mask = ((1 << so->output[i].num_components) - 1) <<
2694 so->output[i].start_component;
2695 fprintf(stderr, " %i: BUF%i[%i..%i] <- OUT[%i].%s%s%s%s\n",
2696 i, so->output[i].output_buffer,
2697 so->output[i].dst_offset, so->output[i].dst_offset + so->output[i].num_components - 1,
2698 so->output[i].register_index,
2699 mask & 1 ? "x" : "",
2700 mask & 2 ? "y" : "",
2701 mask & 4 ? "z" : "",
2702 mask & 8 ? "w" : "");
2703 }
2704 }
2705
2706 static void emit_streamout_output(struct si_shader_context *ctx,
2707 LLVMValueRef const *so_buffers,
2708 LLVMValueRef const *so_write_offsets,
2709 struct pipe_stream_output *stream_out,
2710 struct si_shader_output_values *shader_out)
2711 {
2712 unsigned buf_idx = stream_out->output_buffer;
2713 unsigned start = stream_out->start_component;
2714 unsigned num_comps = stream_out->num_components;
2715 LLVMValueRef out[4];
2716
2717 assert(num_comps && num_comps <= 4);
2718 if (!num_comps || num_comps > 4)
2719 return;
2720
2721 /* Load the output as int. */
2722 for (int j = 0; j < num_comps; j++) {
2723 assert(stream_out->stream == shader_out->vertex_stream[start + j]);
2724
2725 out[j] = ac_to_integer(&ctx->ac, shader_out->values[start + j]);
2726 }
2727
2728 /* Pack the output. */
2729 LLVMValueRef vdata = NULL;
2730
2731 switch (num_comps) {
2732 case 1: /* as i32 */
2733 vdata = out[0];
2734 break;
2735 case 2: /* as v2i32 */
2736 case 3: /* as v4i32 (aligned to 4) */
2737 case 4: /* as v4i32 */
2738 vdata = LLVMGetUndef(LLVMVectorType(ctx->i32, util_next_power_of_two(num_comps)));
2739 for (int j = 0; j < num_comps; j++) {
2740 vdata = LLVMBuildInsertElement(ctx->ac.builder, vdata, out[j],
2741 LLVMConstInt(ctx->i32, j, 0), "");
2742 }
2743 break;
2744 }
2745
2746 ac_build_buffer_store_dword(&ctx->ac, so_buffers[buf_idx],
2747 vdata, num_comps,
2748 so_write_offsets[buf_idx],
2749 ctx->i32_0,
2750 stream_out->dst_offset * 4, 1, 1, true, false);
2751 }
2752
2753 /**
2754 * Write streamout data to buffers for vertex stream @p stream (different
2755 * vertex streams can occur for GS copy shaders).
2756 */
2757 static void si_llvm_emit_streamout(struct si_shader_context *ctx,
2758 struct si_shader_output_values *outputs,
2759 unsigned noutput, unsigned stream)
2760 {
2761 struct si_shader_selector *sel = ctx->shader->selector;
2762 struct pipe_stream_output_info *so = &sel->so;
2763 LLVMBuilderRef builder = ctx->ac.builder;
2764 int i;
2765 struct lp_build_if_state if_ctx;
2766
2767 /* Get bits [22:16], i.e. (so_param >> 16) & 127; */
2768 LLVMValueRef so_vtx_count =
2769 unpack_param(ctx, ctx->param_streamout_config, 16, 7);
2770
2771 LLVMValueRef tid = ac_get_thread_id(&ctx->ac);
2772
2773 /* can_emit = tid < so_vtx_count; */
2774 LLVMValueRef can_emit =
2775 LLVMBuildICmp(builder, LLVMIntULT, tid, so_vtx_count, "");
2776
2777 /* Emit the streamout code conditionally. This actually avoids
2778 * out-of-bounds buffer access. The hw tells us via the SGPR
2779 * (so_vtx_count) which threads are allowed to emit streamout data. */
2780 lp_build_if(&if_ctx, &ctx->gallivm, can_emit);
2781 {
2782 /* The buffer offset is computed as follows:
2783 * ByteOffset = streamout_offset[buffer_id]*4 +
2784 * (streamout_write_index + thread_id)*stride[buffer_id] +
2785 * attrib_offset
2786 */
2787
2788 LLVMValueRef so_write_index =
2789 LLVMGetParam(ctx->main_fn,
2790 ctx->param_streamout_write_index);
2791
2792 /* Compute (streamout_write_index + thread_id). */
2793 so_write_index = LLVMBuildAdd(builder, so_write_index, tid, "");
2794
2795 /* Load the descriptor and compute the write offset for each
2796 * enabled buffer. */
2797 LLVMValueRef so_write_offset[4] = {};
2798 LLVMValueRef so_buffers[4];
2799 LLVMValueRef buf_ptr = LLVMGetParam(ctx->main_fn,
2800 ctx->param_rw_buffers);
2801
2802 for (i = 0; i < 4; i++) {
2803 if (!so->stride[i])
2804 continue;
2805
2806 LLVMValueRef offset = LLVMConstInt(ctx->i32,
2807 SI_VS_STREAMOUT_BUF0 + i, 0);
2808
2809 so_buffers[i] = ac_build_load_to_sgpr(&ctx->ac, buf_ptr, offset);
2810
2811 LLVMValueRef so_offset = LLVMGetParam(ctx->main_fn,
2812 ctx->param_streamout_offset[i]);
2813 so_offset = LLVMBuildMul(builder, so_offset, LLVMConstInt(ctx->i32, 4, 0), "");
2814
2815 so_write_offset[i] = LLVMBuildMul(builder, so_write_index,
2816 LLVMConstInt(ctx->i32, so->stride[i]*4, 0), "");
2817 so_write_offset[i] = LLVMBuildAdd(builder, so_write_offset[i], so_offset, "");
2818 }
2819
2820 /* Write streamout data. */
2821 for (i = 0; i < so->num_outputs; i++) {
2822 unsigned reg = so->output[i].register_index;
2823
2824 if (reg >= noutput)
2825 continue;
2826
2827 if (stream != so->output[i].stream)
2828 continue;
2829
2830 emit_streamout_output(ctx, so_buffers, so_write_offset,
2831 &so->output[i], &outputs[reg]);
2832 }
2833 }
2834 lp_build_endif(&if_ctx);
2835 }
2836
2837 static void si_export_param(struct si_shader_context *ctx, unsigned index,
2838 LLVMValueRef *values)
2839 {
2840 struct ac_export_args args;
2841
2842 si_llvm_init_export_args(ctx, values,
2843 V_008DFC_SQ_EXP_PARAM + index, &args);
2844 ac_build_export(&ctx->ac, &args);
2845 }
2846
2847 static void si_build_param_exports(struct si_shader_context *ctx,
2848 struct si_shader_output_values *outputs,
2849 unsigned noutput)
2850 {
2851 struct si_shader *shader = ctx->shader;
2852 unsigned param_count = 0;
2853
2854 for (unsigned i = 0; i < noutput; i++) {
2855 unsigned semantic_name = outputs[i].semantic_name;
2856 unsigned semantic_index = outputs[i].semantic_index;
2857
2858 if (outputs[i].vertex_stream[0] != 0 &&
2859 outputs[i].vertex_stream[1] != 0 &&
2860 outputs[i].vertex_stream[2] != 0 &&
2861 outputs[i].vertex_stream[3] != 0)
2862 continue;
2863
2864 switch (semantic_name) {
2865 case TGSI_SEMANTIC_LAYER:
2866 case TGSI_SEMANTIC_VIEWPORT_INDEX:
2867 case TGSI_SEMANTIC_CLIPDIST:
2868 case TGSI_SEMANTIC_COLOR:
2869 case TGSI_SEMANTIC_BCOLOR:
2870 case TGSI_SEMANTIC_PRIMID:
2871 case TGSI_SEMANTIC_FOG:
2872 case TGSI_SEMANTIC_TEXCOORD:
2873 case TGSI_SEMANTIC_GENERIC:
2874 break;
2875 default:
2876 continue;
2877 }
2878
2879 if ((semantic_name != TGSI_SEMANTIC_GENERIC ||
2880 semantic_index < SI_MAX_IO_GENERIC) &&
2881 shader->key.opt.kill_outputs &
2882 (1ull << si_shader_io_get_unique_index(semantic_name, semantic_index)))
2883 continue;
2884
2885 si_export_param(ctx, param_count, outputs[i].values);
2886
2887 assert(i < ARRAY_SIZE(shader->info.vs_output_param_offset));
2888 shader->info.vs_output_param_offset[i] = param_count++;
2889 }
2890
2891 shader->info.nr_param_exports = param_count;
2892 }
2893
2894 /* Generate export instructions for hardware VS shader stage */
2895 static void si_llvm_export_vs(struct si_shader_context *ctx,
2896 struct si_shader_output_values *outputs,
2897 unsigned noutput)
2898 {
2899 struct si_shader *shader = ctx->shader;
2900 struct ac_export_args pos_args[4] = {};
2901 LLVMValueRef psize_value = NULL, edgeflag_value = NULL, layer_value = NULL, viewport_index_value = NULL;
2902 unsigned pos_idx;
2903 int i;
2904
2905 /* Build position exports. */
2906 for (i = 0; i < noutput; i++) {
2907 switch (outputs[i].semantic_name) {
2908 case TGSI_SEMANTIC_POSITION:
2909 si_llvm_init_export_args(ctx, outputs[i].values,
2910 V_008DFC_SQ_EXP_POS, &pos_args[0]);
2911 break;
2912 case TGSI_SEMANTIC_PSIZE:
2913 psize_value = outputs[i].values[0];
2914 break;
2915 case TGSI_SEMANTIC_LAYER:
2916 layer_value = outputs[i].values[0];
2917 break;
2918 case TGSI_SEMANTIC_VIEWPORT_INDEX:
2919 viewport_index_value = outputs[i].values[0];
2920 break;
2921 case TGSI_SEMANTIC_EDGEFLAG:
2922 edgeflag_value = outputs[i].values[0];
2923 break;
2924 case TGSI_SEMANTIC_CLIPDIST:
2925 if (!shader->key.opt.clip_disable) {
2926 unsigned index = 2 + outputs[i].semantic_index;
2927 si_llvm_init_export_args(ctx, outputs[i].values,
2928 V_008DFC_SQ_EXP_POS + index,
2929 &pos_args[index]);
2930 }
2931 break;
2932 case TGSI_SEMANTIC_CLIPVERTEX:
2933 if (!shader->key.opt.clip_disable) {
2934 si_llvm_emit_clipvertex(ctx, pos_args,
2935 outputs[i].values);
2936 }
2937 break;
2938 }
2939 }
2940
2941 /* We need to add the position output manually if it's missing. */
2942 if (!pos_args[0].out[0]) {
2943 pos_args[0].enabled_channels = 0xf; /* writemask */
2944 pos_args[0].valid_mask = 0; /* EXEC mask */
2945 pos_args[0].done = 0; /* last export? */
2946 pos_args[0].target = V_008DFC_SQ_EXP_POS;
2947 pos_args[0].compr = 0; /* COMPR flag */
2948 pos_args[0].out[0] = ctx->ac.f32_0; /* X */
2949 pos_args[0].out[1] = ctx->ac.f32_0; /* Y */
2950 pos_args[0].out[2] = ctx->ac.f32_0; /* Z */
2951 pos_args[0].out[3] = ctx->ac.f32_1; /* W */
2952 }
2953
2954 /* Write the misc vector (point size, edgeflag, layer, viewport). */
2955 if (shader->selector->info.writes_psize ||
2956 shader->selector->info.writes_edgeflag ||
2957 shader->selector->info.writes_viewport_index ||
2958 shader->selector->info.writes_layer) {
2959 pos_args[1].enabled_channels = shader->selector->info.writes_psize |
2960 (shader->selector->info.writes_edgeflag << 1) |
2961 (shader->selector->info.writes_layer << 2);
2962
2963 pos_args[1].valid_mask = 0; /* EXEC mask */
2964 pos_args[1].done = 0; /* last export? */
2965 pos_args[1].target = V_008DFC_SQ_EXP_POS + 1;
2966 pos_args[1].compr = 0; /* COMPR flag */
2967 pos_args[1].out[0] = ctx->ac.f32_0; /* X */
2968 pos_args[1].out[1] = ctx->ac.f32_0; /* Y */
2969 pos_args[1].out[2] = ctx->ac.f32_0; /* Z */
2970 pos_args[1].out[3] = ctx->ac.f32_0; /* W */
2971
2972 if (shader->selector->info.writes_psize)
2973 pos_args[1].out[0] = psize_value;
2974
2975 if (shader->selector->info.writes_edgeflag) {
2976 /* The output is a float, but the hw expects an integer
2977 * with the first bit containing the edge flag. */
2978 edgeflag_value = LLVMBuildFPToUI(ctx->ac.builder,
2979 edgeflag_value,
2980 ctx->i32, "");
2981 edgeflag_value = ac_build_umin(&ctx->ac,
2982 edgeflag_value,
2983 ctx->i32_1);
2984
2985 /* The LLVM intrinsic expects a float. */
2986 pos_args[1].out[1] = ac_to_float(&ctx->ac, edgeflag_value);
2987 }
2988
2989 if (ctx->screen->info.chip_class >= GFX9) {
2990 /* GFX9 has the layer in out.z[10:0] and the viewport
2991 * index in out.z[19:16].
2992 */
2993 if (shader->selector->info.writes_layer)
2994 pos_args[1].out[2] = layer_value;
2995
2996 if (shader->selector->info.writes_viewport_index) {
2997 LLVMValueRef v = viewport_index_value;
2998
2999 v = ac_to_integer(&ctx->ac, v);
3000 v = LLVMBuildShl(ctx->ac.builder, v,
3001 LLVMConstInt(ctx->i32, 16, 0), "");
3002 v = LLVMBuildOr(ctx->ac.builder, v,
3003 ac_to_integer(&ctx->ac, pos_args[1].out[2]), "");
3004 pos_args[1].out[2] = ac_to_float(&ctx->ac, v);
3005 pos_args[1].enabled_channels |= 1 << 2;
3006 }
3007 } else {
3008 if (shader->selector->info.writes_layer)
3009 pos_args[1].out[2] = layer_value;
3010
3011 if (shader->selector->info.writes_viewport_index) {
3012 pos_args[1].out[3] = viewport_index_value;
3013 pos_args[1].enabled_channels |= 1 << 3;
3014 }
3015 }
3016 }
3017
3018 for (i = 0; i < 4; i++)
3019 if (pos_args[i].out[0])
3020 shader->info.nr_pos_exports++;
3021
3022 pos_idx = 0;
3023 for (i = 0; i < 4; i++) {
3024 if (!pos_args[i].out[0])
3025 continue;
3026
3027 /* Specify the target we are exporting */
3028 pos_args[i].target = V_008DFC_SQ_EXP_POS + pos_idx++;
3029
3030 if (pos_idx == shader->info.nr_pos_exports)
3031 /* Specify that this is the last export */
3032 pos_args[i].done = 1;
3033
3034 ac_build_export(&ctx->ac, &pos_args[i]);
3035 }
3036
3037 /* Build parameter exports. */
3038 si_build_param_exports(ctx, outputs, noutput);
3039 }
3040
3041 /**
3042 * Forward all outputs from the vertex shader to the TES. This is only used
3043 * for the fixed function TCS.
3044 */
3045 static void si_copy_tcs_inputs(struct lp_build_tgsi_context *bld_base)
3046 {
3047 struct si_shader_context *ctx = si_shader_context(bld_base);
3048 LLVMValueRef invocation_id, buffer, buffer_offset;
3049 LLVMValueRef lds_vertex_stride, lds_vertex_offset, lds_base;
3050 uint64_t inputs;
3051
3052 invocation_id = unpack_llvm_param(ctx, ctx->abi.tcs_rel_ids, 8, 5);
3053 buffer = desc_from_addr_base64k(ctx, ctx->param_tcs_offchip_addr_base64k);
3054 buffer_offset = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
3055
3056 lds_vertex_stride = get_tcs_in_vertex_dw_stride(ctx);
3057 lds_vertex_offset = LLVMBuildMul(ctx->ac.builder, invocation_id,
3058 lds_vertex_stride, "");
3059 lds_base = get_tcs_in_current_patch_offset(ctx);
3060 lds_base = LLVMBuildAdd(ctx->ac.builder, lds_base, lds_vertex_offset, "");
3061
3062 inputs = ctx->shader->key.mono.u.ff_tcs_inputs_to_copy;
3063 while (inputs) {
3064 unsigned i = u_bit_scan64(&inputs);
3065
3066 LLVMValueRef lds_ptr = LLVMBuildAdd(ctx->ac.builder, lds_base,
3067 LLVMConstInt(ctx->i32, 4 * i, 0),
3068 "");
3069
3070 LLVMValueRef buffer_addr = get_tcs_tes_buffer_address(ctx,
3071 get_rel_patch_id(ctx),
3072 invocation_id,
3073 LLVMConstInt(ctx->i32, i, 0));
3074
3075 LLVMValueRef value = lds_load(bld_base, ctx->ac.i32, ~0,
3076 lds_ptr);
3077
3078 ac_build_buffer_store_dword(&ctx->ac, buffer, value, 4, buffer_addr,
3079 buffer_offset, 0, 1, 0, true, false);
3080 }
3081 }
3082
3083 static void si_write_tess_factors(struct lp_build_tgsi_context *bld_base,
3084 LLVMValueRef rel_patch_id,
3085 LLVMValueRef invocation_id,
3086 LLVMValueRef tcs_out_current_patch_data_offset,
3087 LLVMValueRef invoc0_tf_outer[4],
3088 LLVMValueRef invoc0_tf_inner[2])
3089 {
3090 struct si_shader_context *ctx = si_shader_context(bld_base);
3091 struct si_shader *shader = ctx->shader;
3092 unsigned tess_inner_index, tess_outer_index;
3093 LLVMValueRef lds_base, lds_inner, lds_outer, byteoffset, buffer;
3094 LLVMValueRef out[6], vec0, vec1, tf_base, inner[4], outer[4];
3095 unsigned stride, outer_comps, inner_comps, i, offset;
3096 struct lp_build_if_state if_ctx, inner_if_ctx;
3097
3098 /* Add a barrier before loading tess factors from LDS. */
3099 if (!shader->key.part.tcs.epilog.invoc0_tess_factors_are_def)
3100 si_llvm_emit_barrier(NULL, bld_base, NULL);
3101
3102 /* Do this only for invocation 0, because the tess levels are per-patch,
3103 * not per-vertex.
3104 *
3105 * This can't jump, because invocation 0 executes this. It should
3106 * at least mask out the loads and stores for other invocations.
3107 */
3108 lp_build_if(&if_ctx, &ctx->gallivm,
3109 LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
3110 invocation_id, ctx->i32_0, ""));
3111
3112 /* Determine the layout of one tess factor element in the buffer. */
3113 switch (shader->key.part.tcs.epilog.prim_mode) {
3114 case PIPE_PRIM_LINES:
3115 stride = 2; /* 2 dwords, 1 vec2 store */
3116 outer_comps = 2;
3117 inner_comps = 0;
3118 break;
3119 case PIPE_PRIM_TRIANGLES:
3120 stride = 4; /* 4 dwords, 1 vec4 store */
3121 outer_comps = 3;
3122 inner_comps = 1;
3123 break;
3124 case PIPE_PRIM_QUADS:
3125 stride = 6; /* 6 dwords, 2 stores (vec4 + vec2) */
3126 outer_comps = 4;
3127 inner_comps = 2;
3128 break;
3129 default:
3130 assert(0);
3131 return;
3132 }
3133
3134 for (i = 0; i < 4; i++) {
3135 inner[i] = LLVMGetUndef(ctx->i32);
3136 outer[i] = LLVMGetUndef(ctx->i32);
3137 }
3138
3139 if (shader->key.part.tcs.epilog.invoc0_tess_factors_are_def) {
3140 /* Tess factors are in VGPRs. */
3141 for (i = 0; i < outer_comps; i++)
3142 outer[i] = out[i] = invoc0_tf_outer[i];
3143 for (i = 0; i < inner_comps; i++)
3144 inner[i] = out[outer_comps+i] = invoc0_tf_inner[i];
3145 } else {
3146 /* Load tess_inner and tess_outer from LDS.
3147 * Any invocation can write them, so we can't get them from a temporary.
3148 */
3149 tess_inner_index = si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSINNER, 0);
3150 tess_outer_index = si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSOUTER, 0);
3151
3152 lds_base = tcs_out_current_patch_data_offset;
3153 lds_inner = LLVMBuildAdd(ctx->ac.builder, lds_base,
3154 LLVMConstInt(ctx->i32,
3155 tess_inner_index * 4, 0), "");
3156 lds_outer = LLVMBuildAdd(ctx->ac.builder, lds_base,
3157 LLVMConstInt(ctx->i32,
3158 tess_outer_index * 4, 0), "");
3159
3160 for (i = 0; i < outer_comps; i++) {
3161 outer[i] = out[i] =
3162 lds_load(bld_base, ctx->ac.i32, i, lds_outer);
3163 }
3164 for (i = 0; i < inner_comps; i++) {
3165 inner[i] = out[outer_comps+i] =
3166 lds_load(bld_base, ctx->ac.i32, i, lds_inner);
3167 }
3168 }
3169
3170 if (shader->key.part.tcs.epilog.prim_mode == PIPE_PRIM_LINES) {
3171 /* For isolines, the hardware expects tess factors in the
3172 * reverse order from what GLSL / TGSI specify.
3173 */
3174 LLVMValueRef tmp = out[0];
3175 out[0] = out[1];
3176 out[1] = tmp;
3177 }
3178
3179 /* Convert the outputs to vectors for stores. */
3180 vec0 = lp_build_gather_values(&ctx->gallivm, out, MIN2(stride, 4));
3181 vec1 = NULL;
3182
3183 if (stride > 4)
3184 vec1 = lp_build_gather_values(&ctx->gallivm, out+4, stride - 4);
3185
3186 /* Get the buffer. */
3187 buffer = desc_from_addr_base64k(ctx, ctx->param_tcs_factor_addr_base64k);
3188
3189 /* Get the offset. */
3190 tf_base = LLVMGetParam(ctx->main_fn,
3191 ctx->param_tcs_factor_offset);
3192 byteoffset = LLVMBuildMul(ctx->ac.builder, rel_patch_id,
3193 LLVMConstInt(ctx->i32, 4 * stride, 0), "");
3194
3195 lp_build_if(&inner_if_ctx, &ctx->gallivm,
3196 LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
3197 rel_patch_id, ctx->i32_0, ""));
3198
3199 /* Store the dynamic HS control word. */
3200 offset = 0;
3201 if (ctx->screen->info.chip_class <= VI) {
3202 ac_build_buffer_store_dword(&ctx->ac, buffer,
3203 LLVMConstInt(ctx->i32, 0x80000000, 0),
3204 1, ctx->i32_0, tf_base,
3205 offset, 1, 0, true, false);
3206 offset += 4;
3207 }
3208
3209 lp_build_endif(&inner_if_ctx);
3210
3211 /* Store the tessellation factors. */
3212 ac_build_buffer_store_dword(&ctx->ac, buffer, vec0,
3213 MIN2(stride, 4), byteoffset, tf_base,
3214 offset, 1, 0, true, false);
3215 offset += 16;
3216 if (vec1)
3217 ac_build_buffer_store_dword(&ctx->ac, buffer, vec1,
3218 stride - 4, byteoffset, tf_base,
3219 offset, 1, 0, true, false);
3220
3221 /* Store the tess factors into the offchip buffer if TES reads them. */
3222 if (shader->key.part.tcs.epilog.tes_reads_tess_factors) {
3223 LLVMValueRef buf, base, inner_vec, outer_vec, tf_outer_offset;
3224 LLVMValueRef tf_inner_offset;
3225 unsigned param_outer, param_inner;
3226
3227 buf = desc_from_addr_base64k(ctx, ctx->param_tcs_offchip_addr_base64k);
3228 base = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
3229
3230 param_outer = si_shader_io_get_unique_index_patch(
3231 TGSI_SEMANTIC_TESSOUTER, 0);
3232 tf_outer_offset = get_tcs_tes_buffer_address(ctx, rel_patch_id, NULL,
3233 LLVMConstInt(ctx->i32, param_outer, 0));
3234
3235 outer_vec = lp_build_gather_values(&ctx->gallivm, outer,
3236 util_next_power_of_two(outer_comps));
3237
3238 ac_build_buffer_store_dword(&ctx->ac, buf, outer_vec,
3239 outer_comps, tf_outer_offset,
3240 base, 0, 1, 0, true, false);
3241 if (inner_comps) {
3242 param_inner = si_shader_io_get_unique_index_patch(
3243 TGSI_SEMANTIC_TESSINNER, 0);
3244 tf_inner_offset = get_tcs_tes_buffer_address(ctx, rel_patch_id, NULL,
3245 LLVMConstInt(ctx->i32, param_inner, 0));
3246
3247 inner_vec = inner_comps == 1 ? inner[0] :
3248 lp_build_gather_values(&ctx->gallivm, inner, inner_comps);
3249 ac_build_buffer_store_dword(&ctx->ac, buf, inner_vec,
3250 inner_comps, tf_inner_offset,
3251 base, 0, 1, 0, true, false);
3252 }
3253 }
3254
3255 lp_build_endif(&if_ctx);
3256 }
3257
3258 static LLVMValueRef
3259 si_insert_input_ret(struct si_shader_context *ctx, LLVMValueRef ret,
3260 unsigned param, unsigned return_index)
3261 {
3262 return LLVMBuildInsertValue(ctx->ac.builder, ret,
3263 LLVMGetParam(ctx->main_fn, param),
3264 return_index, "");
3265 }
3266
3267 static LLVMValueRef
3268 si_insert_input_ret_float(struct si_shader_context *ctx, LLVMValueRef ret,
3269 unsigned param, unsigned return_index)
3270 {
3271 LLVMBuilderRef builder = ctx->ac.builder;
3272 LLVMValueRef p = LLVMGetParam(ctx->main_fn, param);
3273
3274 return LLVMBuildInsertValue(builder, ret,
3275 ac_to_float(&ctx->ac, p),
3276 return_index, "");
3277 }
3278
3279 static LLVMValueRef
3280 si_insert_input_ptr_as_2xi32(struct si_shader_context *ctx, LLVMValueRef ret,
3281 unsigned param, unsigned return_index)
3282 {
3283 LLVMBuilderRef builder = ctx->ac.builder;
3284 LLVMValueRef ptr, lo, hi;
3285
3286 ptr = LLVMGetParam(ctx->main_fn, param);
3287 ptr = LLVMBuildPtrToInt(builder, ptr, ctx->i64, "");
3288 ptr = LLVMBuildBitCast(builder, ptr, ctx->v2i32, "");
3289 lo = LLVMBuildExtractElement(builder, ptr, ctx->i32_0, "");
3290 hi = LLVMBuildExtractElement(builder, ptr, ctx->i32_1, "");
3291 ret = LLVMBuildInsertValue(builder, ret, lo, return_index, "");
3292 return LLVMBuildInsertValue(builder, ret, hi, return_index + 1, "");
3293 }
3294
3295 /* This only writes the tessellation factor levels. */
3296 static void si_llvm_emit_tcs_epilogue(struct ac_shader_abi *abi,
3297 unsigned max_outputs,
3298 LLVMValueRef *addrs)
3299 {
3300 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
3301 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
3302 LLVMBuilderRef builder = ctx->ac.builder;
3303 LLVMValueRef rel_patch_id, invocation_id, tf_lds_offset;
3304
3305 si_copy_tcs_inputs(bld_base);
3306
3307 rel_patch_id = get_rel_patch_id(ctx);
3308 invocation_id = unpack_llvm_param(ctx, ctx->abi.tcs_rel_ids, 8, 5);
3309 tf_lds_offset = get_tcs_out_current_patch_data_offset(ctx);
3310
3311 if (ctx->screen->info.chip_class >= GFX9) {
3312 LLVMBasicBlockRef blocks[2] = {
3313 LLVMGetInsertBlock(builder),
3314 ctx->merged_wrap_if_state.entry_block
3315 };
3316 LLVMValueRef values[2];
3317
3318 lp_build_endif(&ctx->merged_wrap_if_state);
3319
3320 values[0] = rel_patch_id;
3321 values[1] = LLVMGetUndef(ctx->i32);
3322 rel_patch_id = ac_build_phi(&ctx->ac, ctx->i32, 2, values, blocks);
3323
3324 values[0] = tf_lds_offset;
3325 values[1] = LLVMGetUndef(ctx->i32);
3326 tf_lds_offset = ac_build_phi(&ctx->ac, ctx->i32, 2, values, blocks);
3327
3328 values[0] = invocation_id;
3329 values[1] = ctx->i32_1; /* cause the epilog to skip threads */
3330 invocation_id = ac_build_phi(&ctx->ac, ctx->i32, 2, values, blocks);
3331 }
3332
3333 /* Return epilog parameters from this function. */
3334 LLVMValueRef ret = ctx->return_value;
3335 unsigned vgpr;
3336
3337 if (ctx->screen->info.chip_class >= GFX9) {
3338 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_layout,
3339 8 + GFX9_SGPR_TCS_OFFCHIP_LAYOUT);
3340 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_addr_base64k,
3341 8 + GFX9_SGPR_TCS_OFFCHIP_ADDR_BASE64K);
3342 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_factor_addr_base64k,
3343 8 + GFX9_SGPR_TCS_FACTOR_ADDR_BASE64K);
3344 /* Tess offchip and tess factor offsets are at the beginning. */
3345 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_offset, 2);
3346 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_factor_offset, 4);
3347 vgpr = 8 + GFX9_SGPR_TCS_FACTOR_ADDR_BASE64K + 1;
3348 } else {
3349 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_layout,
3350 GFX6_SGPR_TCS_OFFCHIP_LAYOUT);
3351 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_addr_base64k,
3352 GFX6_SGPR_TCS_OFFCHIP_ADDR_BASE64K);
3353 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_factor_addr_base64k,
3354 GFX6_SGPR_TCS_FACTOR_ADDR_BASE64K);
3355 /* Tess offchip and tess factor offsets are after user SGPRs. */
3356 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_offset,
3357 GFX6_TCS_NUM_USER_SGPR);
3358 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_factor_offset,
3359 GFX6_TCS_NUM_USER_SGPR + 1);
3360 vgpr = GFX6_TCS_NUM_USER_SGPR + 2;
3361 }
3362
3363 /* VGPRs */
3364 rel_patch_id = ac_to_float(&ctx->ac, rel_patch_id);
3365 invocation_id = ac_to_float(&ctx->ac, invocation_id);
3366 tf_lds_offset = ac_to_float(&ctx->ac, tf_lds_offset);
3367
3368 /* Leave a hole corresponding to the two input VGPRs. This ensures that
3369 * the invocation_id output does not alias the tcs_rel_ids input,
3370 * which saves a V_MOV on gfx9.
3371 */
3372 vgpr += 2;
3373
3374 ret = LLVMBuildInsertValue(builder, ret, rel_patch_id, vgpr++, "");
3375 ret = LLVMBuildInsertValue(builder, ret, invocation_id, vgpr++, "");
3376
3377 if (ctx->shader->selector->tcs_info.tessfactors_are_def_in_all_invocs) {
3378 vgpr++; /* skip the tess factor LDS offset */
3379 for (unsigned i = 0; i < 6; i++) {
3380 LLVMValueRef value =
3381 LLVMBuildLoad(builder, ctx->invoc0_tess_factors[i], "");
3382 value = ac_to_float(&ctx->ac, value);
3383 ret = LLVMBuildInsertValue(builder, ret, value, vgpr++, "");
3384 }
3385 } else {
3386 ret = LLVMBuildInsertValue(builder, ret, tf_lds_offset, vgpr++, "");
3387 }
3388 ctx->return_value = ret;
3389 }
3390
3391 /* Pass TCS inputs from LS to TCS on GFX9. */
3392 static void si_set_ls_return_value_for_tcs(struct si_shader_context *ctx)
3393 {
3394 LLVMValueRef ret = ctx->return_value;
3395
3396 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_offset, 2);
3397 ret = si_insert_input_ret(ctx, ret, ctx->param_merged_wave_info, 3);
3398 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_factor_offset, 4);
3399 ret = si_insert_input_ret(ctx, ret, ctx->param_merged_scratch_offset, 5);
3400
3401 ret = si_insert_input_ptr_as_2xi32(ctx, ret, ctx->param_rw_buffers,
3402 8 + SI_SGPR_RW_BUFFERS);
3403 ret = si_insert_input_ptr_as_2xi32(ctx, ret,
3404 ctx->param_bindless_samplers_and_images,
3405 8 + SI_SGPR_BINDLESS_SAMPLERS_AND_IMAGES);
3406
3407 ret = si_insert_input_ret(ctx, ret, ctx->param_vs_state_bits,
3408 8 + SI_SGPR_VS_STATE_BITS);
3409 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_layout,
3410 8 + GFX9_SGPR_TCS_OFFCHIP_LAYOUT);
3411 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_out_lds_offsets,
3412 8 + GFX9_SGPR_TCS_OUT_OFFSETS);
3413 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_out_lds_layout,
3414 8 + GFX9_SGPR_TCS_OUT_LAYOUT);
3415 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_addr_base64k,
3416 8 + GFX9_SGPR_TCS_OFFCHIP_ADDR_BASE64K);
3417 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_factor_addr_base64k,
3418 8 + GFX9_SGPR_TCS_FACTOR_ADDR_BASE64K);
3419
3420 unsigned desc_param = ctx->param_tcs_factor_addr_base64k + 2;
3421 ret = si_insert_input_ptr_as_2xi32(ctx, ret, desc_param,
3422 8 + GFX9_SGPR_TCS_CONST_AND_SHADER_BUFFERS);
3423 ret = si_insert_input_ptr_as_2xi32(ctx, ret, desc_param + 1,
3424 8 + GFX9_SGPR_TCS_SAMPLERS_AND_IMAGES);
3425
3426 unsigned vgpr = 8 + GFX9_TCS_NUM_USER_SGPR;
3427 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
3428 ac_to_float(&ctx->ac, ctx->abi.tcs_patch_id),
3429 vgpr++, "");
3430 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
3431 ac_to_float(&ctx->ac, ctx->abi.tcs_rel_ids),
3432 vgpr++, "");
3433 ctx->return_value = ret;
3434 }
3435
3436 /* Pass GS inputs from ES to GS on GFX9. */
3437 static void si_set_es_return_value_for_gs(struct si_shader_context *ctx)
3438 {
3439 LLVMValueRef ret = ctx->return_value;
3440
3441 ret = si_insert_input_ret(ctx, ret, ctx->param_gs2vs_offset, 2);
3442 ret = si_insert_input_ret(ctx, ret, ctx->param_merged_wave_info, 3);
3443 ret = si_insert_input_ret(ctx, ret, ctx->param_merged_scratch_offset, 5);
3444
3445 ret = si_insert_input_ptr_as_2xi32(ctx, ret, ctx->param_rw_buffers,
3446 8 + SI_SGPR_RW_BUFFERS);
3447 ret = si_insert_input_ptr_as_2xi32(ctx, ret,
3448 ctx->param_bindless_samplers_and_images,
3449 8 + SI_SGPR_BINDLESS_SAMPLERS_AND_IMAGES);
3450
3451 unsigned desc_param = ctx->param_vs_state_bits + 1;
3452 ret = si_insert_input_ptr_as_2xi32(ctx, ret, desc_param,
3453 8 + GFX9_SGPR_GS_CONST_AND_SHADER_BUFFERS);
3454 ret = si_insert_input_ptr_as_2xi32(ctx, ret, desc_param + 1,
3455 8 + GFX9_SGPR_GS_SAMPLERS_AND_IMAGES);
3456
3457 unsigned vgpr = 8 + GFX9_GS_NUM_USER_SGPR;
3458 for (unsigned i = 0; i < 5; i++) {
3459 unsigned param = ctx->param_gs_vtx01_offset + i;
3460 ret = si_insert_input_ret_float(ctx, ret, param, vgpr++);
3461 }
3462 ctx->return_value = ret;
3463 }
3464
3465 static void si_llvm_emit_ls_epilogue(struct ac_shader_abi *abi,
3466 unsigned max_outputs,
3467 LLVMValueRef *addrs)
3468 {
3469 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
3470 struct si_shader *shader = ctx->shader;
3471 struct tgsi_shader_info *info = &shader->selector->info;
3472 unsigned i, chan;
3473 LLVMValueRef vertex_id = LLVMGetParam(ctx->main_fn,
3474 ctx->param_rel_auto_id);
3475 LLVMValueRef vertex_dw_stride = get_tcs_in_vertex_dw_stride(ctx);
3476 LLVMValueRef base_dw_addr = LLVMBuildMul(ctx->ac.builder, vertex_id,
3477 vertex_dw_stride, "");
3478
3479 /* Write outputs to LDS. The next shader (TCS aka HS) will read
3480 * its inputs from it. */
3481 for (i = 0; i < info->num_outputs; i++) {
3482 unsigned name = info->output_semantic_name[i];
3483 unsigned index = info->output_semantic_index[i];
3484
3485 /* The ARB_shader_viewport_layer_array spec contains the
3486 * following issue:
3487 *
3488 * 2) What happens if gl_ViewportIndex or gl_Layer is
3489 * written in the vertex shader and a geometry shader is
3490 * present?
3491 *
3492 * RESOLVED: The value written by the last vertex processing
3493 * stage is used. If the last vertex processing stage
3494 * (vertex, tessellation evaluation or geometry) does not
3495 * statically assign to gl_ViewportIndex or gl_Layer, index
3496 * or layer zero is assumed.
3497 *
3498 * So writes to those outputs in VS-as-LS are simply ignored.
3499 */
3500 if (name == TGSI_SEMANTIC_LAYER ||
3501 name == TGSI_SEMANTIC_VIEWPORT_INDEX)
3502 continue;
3503
3504 int param = si_shader_io_get_unique_index(name, index);
3505 LLVMValueRef dw_addr = LLVMBuildAdd(ctx->ac.builder, base_dw_addr,
3506 LLVMConstInt(ctx->i32, param * 4, 0), "");
3507
3508 for (chan = 0; chan < 4; chan++) {
3509 if (!(info->output_usagemask[i] & (1 << chan)))
3510 continue;
3511
3512 lds_store(ctx, chan, dw_addr,
3513 LLVMBuildLoad(ctx->ac.builder, addrs[4 * i + chan], ""));
3514 }
3515 }
3516
3517 if (ctx->screen->info.chip_class >= GFX9)
3518 si_set_ls_return_value_for_tcs(ctx);
3519 }
3520
3521 static void si_llvm_emit_es_epilogue(struct ac_shader_abi *abi,
3522 unsigned max_outputs,
3523 LLVMValueRef *addrs)
3524 {
3525 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
3526 struct si_shader *es = ctx->shader;
3527 struct tgsi_shader_info *info = &es->selector->info;
3528 LLVMValueRef soffset = LLVMGetParam(ctx->main_fn,
3529 ctx->param_es2gs_offset);
3530 LLVMValueRef lds_base = NULL;
3531 unsigned chan;
3532 int i;
3533
3534 if (ctx->screen->info.chip_class >= GFX9 && info->num_outputs) {
3535 unsigned itemsize_dw = es->selector->esgs_itemsize / 4;
3536 LLVMValueRef vertex_idx = ac_get_thread_id(&ctx->ac);
3537 LLVMValueRef wave_idx = unpack_param(ctx, ctx->param_merged_wave_info, 24, 4);
3538 vertex_idx = LLVMBuildOr(ctx->ac.builder, vertex_idx,
3539 LLVMBuildMul(ctx->ac.builder, wave_idx,
3540 LLVMConstInt(ctx->i32, 64, false), ""), "");
3541 lds_base = LLVMBuildMul(ctx->ac.builder, vertex_idx,
3542 LLVMConstInt(ctx->i32, itemsize_dw, 0), "");
3543 }
3544
3545 for (i = 0; i < info->num_outputs; i++) {
3546 int param;
3547
3548 if (info->output_semantic_name[i] == TGSI_SEMANTIC_VIEWPORT_INDEX ||
3549 info->output_semantic_name[i] == TGSI_SEMANTIC_LAYER)
3550 continue;
3551
3552 param = si_shader_io_get_unique_index(info->output_semantic_name[i],
3553 info->output_semantic_index[i]);
3554
3555 for (chan = 0; chan < 4; chan++) {
3556 LLVMValueRef out_val = LLVMBuildLoad(ctx->ac.builder, addrs[4 * i + chan], "");
3557 out_val = ac_to_integer(&ctx->ac, out_val);
3558
3559 /* GFX9 has the ESGS ring in LDS. */
3560 if (ctx->screen->info.chip_class >= GFX9) {
3561 lds_store(ctx, param * 4 + chan, lds_base, out_val);
3562 continue;
3563 }
3564
3565 ac_build_buffer_store_dword(&ctx->ac,
3566 ctx->esgs_ring,
3567 out_val, 1, NULL, soffset,
3568 (4 * param + chan) * 4,
3569 1, 1, true, true);
3570 }
3571 }
3572
3573 if (ctx->screen->info.chip_class >= GFX9)
3574 si_set_es_return_value_for_gs(ctx);
3575 }
3576
3577 static LLVMValueRef si_get_gs_wave_id(struct si_shader_context *ctx)
3578 {
3579 if (ctx->screen->info.chip_class >= GFX9)
3580 return unpack_param(ctx, ctx->param_merged_wave_info, 16, 8);
3581 else
3582 return LLVMGetParam(ctx->main_fn, ctx->param_gs_wave_id);
3583 }
3584
3585 static void emit_gs_epilogue(struct si_shader_context *ctx)
3586 {
3587 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_NOP | AC_SENDMSG_GS_DONE,
3588 si_get_gs_wave_id(ctx));
3589
3590 if (ctx->screen->info.chip_class >= GFX9)
3591 lp_build_endif(&ctx->merged_wrap_if_state);
3592 }
3593
3594 static void si_llvm_emit_gs_epilogue(struct ac_shader_abi *abi,
3595 unsigned max_outputs,
3596 LLVMValueRef *addrs)
3597 {
3598 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
3599 struct tgsi_shader_info UNUSED *info = &ctx->shader->selector->info;
3600
3601 assert(info->num_outputs <= max_outputs);
3602
3603 emit_gs_epilogue(ctx);
3604 }
3605
3606 static void si_tgsi_emit_gs_epilogue(struct lp_build_tgsi_context *bld_base)
3607 {
3608 struct si_shader_context *ctx = si_shader_context(bld_base);
3609 emit_gs_epilogue(ctx);
3610 }
3611
3612 static void si_llvm_emit_vs_epilogue(struct ac_shader_abi *abi,
3613 unsigned max_outputs,
3614 LLVMValueRef *addrs)
3615 {
3616 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
3617 struct tgsi_shader_info *info = &ctx->shader->selector->info;
3618 struct si_shader_output_values *outputs = NULL;
3619 int i,j;
3620
3621 assert(!ctx->shader->is_gs_copy_shader);
3622 assert(info->num_outputs <= max_outputs);
3623
3624 outputs = MALLOC((info->num_outputs + 1) * sizeof(outputs[0]));
3625
3626 /* Vertex color clamping.
3627 *
3628 * This uses a state constant loaded in a user data SGPR and
3629 * an IF statement is added that clamps all colors if the constant
3630 * is true.
3631 */
3632 if (ctx->type == PIPE_SHADER_VERTEX) {
3633 struct lp_build_if_state if_ctx;
3634 LLVMValueRef cond = NULL;
3635 LLVMValueRef addr, val;
3636
3637 for (i = 0; i < info->num_outputs; i++) {
3638 if (info->output_semantic_name[i] != TGSI_SEMANTIC_COLOR &&
3639 info->output_semantic_name[i] != TGSI_SEMANTIC_BCOLOR)
3640 continue;
3641
3642 /* We've found a color. */
3643 if (!cond) {
3644 /* The state is in the first bit of the user SGPR. */
3645 cond = LLVMGetParam(ctx->main_fn,
3646 ctx->param_vs_state_bits);
3647 cond = LLVMBuildTrunc(ctx->ac.builder, cond,
3648 ctx->i1, "");
3649 lp_build_if(&if_ctx, &ctx->gallivm, cond);
3650 }
3651
3652 for (j = 0; j < 4; j++) {
3653 addr = addrs[4 * i + j];
3654 val = LLVMBuildLoad(ctx->ac.builder, addr, "");
3655 val = ac_build_clamp(&ctx->ac, val);
3656 LLVMBuildStore(ctx->ac.builder, val, addr);
3657 }
3658 }
3659
3660 if (cond)
3661 lp_build_endif(&if_ctx);
3662 }
3663
3664 for (i = 0; i < info->num_outputs; i++) {
3665 outputs[i].semantic_name = info->output_semantic_name[i];
3666 outputs[i].semantic_index = info->output_semantic_index[i];
3667
3668 for (j = 0; j < 4; j++) {
3669 outputs[i].values[j] =
3670 LLVMBuildLoad(ctx->ac.builder,
3671 addrs[4 * i + j],
3672 "");
3673 outputs[i].vertex_stream[j] =
3674 (info->output_streams[i] >> (2 * j)) & 3;
3675 }
3676 }
3677
3678 if (ctx->shader->selector->so.num_outputs)
3679 si_llvm_emit_streamout(ctx, outputs, i, 0);
3680
3681 /* Export PrimitiveID. */
3682 if (ctx->shader->key.mono.u.vs_export_prim_id) {
3683 outputs[i].semantic_name = TGSI_SEMANTIC_PRIMID;
3684 outputs[i].semantic_index = 0;
3685 outputs[i].values[0] = ac_to_float(&ctx->ac, get_primitive_id(ctx, 0));
3686 for (j = 1; j < 4; j++)
3687 outputs[i].values[j] = LLVMConstReal(ctx->f32, 0);
3688
3689 memset(outputs[i].vertex_stream, 0,
3690 sizeof(outputs[i].vertex_stream));
3691 i++;
3692 }
3693
3694 si_llvm_export_vs(ctx, outputs, i);
3695 FREE(outputs);
3696 }
3697
3698 static void si_tgsi_emit_epilogue(struct lp_build_tgsi_context *bld_base)
3699 {
3700 struct si_shader_context *ctx = si_shader_context(bld_base);
3701
3702 ctx->abi.emit_outputs(&ctx->abi, RADEON_LLVM_MAX_OUTPUTS,
3703 &ctx->outputs[0][0]);
3704 }
3705
3706 struct si_ps_exports {
3707 unsigned num;
3708 struct ac_export_args args[10];
3709 };
3710
3711 static void si_export_mrt_z(struct lp_build_tgsi_context *bld_base,
3712 LLVMValueRef depth, LLVMValueRef stencil,
3713 LLVMValueRef samplemask, struct si_ps_exports *exp)
3714 {
3715 struct si_shader_context *ctx = si_shader_context(bld_base);
3716 struct ac_export_args args;
3717
3718 ac_export_mrt_z(&ctx->ac, depth, stencil, samplemask, &args);
3719
3720 memcpy(&exp->args[exp->num++], &args, sizeof(args));
3721 }
3722
3723 static void si_export_mrt_color(struct lp_build_tgsi_context *bld_base,
3724 LLVMValueRef *color, unsigned index,
3725 unsigned samplemask_param,
3726 bool is_last, struct si_ps_exports *exp)
3727 {
3728 struct si_shader_context *ctx = si_shader_context(bld_base);
3729 int i;
3730
3731 /* Clamp color */
3732 if (ctx->shader->key.part.ps.epilog.clamp_color)
3733 for (i = 0; i < 4; i++)
3734 color[i] = ac_build_clamp(&ctx->ac, color[i]);
3735
3736 /* Alpha to one */
3737 if (ctx->shader->key.part.ps.epilog.alpha_to_one)
3738 color[3] = ctx->ac.f32_1;
3739
3740 /* Alpha test */
3741 if (index == 0 &&
3742 ctx->shader->key.part.ps.epilog.alpha_func != PIPE_FUNC_ALWAYS)
3743 si_alpha_test(bld_base, color[3]);
3744
3745 /* Line & polygon smoothing */
3746 if (ctx->shader->key.part.ps.epilog.poly_line_smoothing)
3747 color[3] = si_scale_alpha_by_sample_mask(bld_base, color[3],
3748 samplemask_param);
3749
3750 /* If last_cbuf > 0, FS_COLOR0_WRITES_ALL_CBUFS is true. */
3751 if (ctx->shader->key.part.ps.epilog.last_cbuf > 0) {
3752 struct ac_export_args args[8];
3753 int c, last = -1;
3754
3755 /* Get the export arguments, also find out what the last one is. */
3756 for (c = 0; c <= ctx->shader->key.part.ps.epilog.last_cbuf; c++) {
3757 si_llvm_init_export_args(ctx, color,
3758 V_008DFC_SQ_EXP_MRT + c, &args[c]);
3759 if (args[c].enabled_channels)
3760 last = c;
3761 }
3762
3763 /* Emit all exports. */
3764 for (c = 0; c <= ctx->shader->key.part.ps.epilog.last_cbuf; c++) {
3765 if (is_last && last == c) {
3766 args[c].valid_mask = 1; /* whether the EXEC mask is valid */
3767 args[c].done = 1; /* DONE bit */
3768 } else if (!args[c].enabled_channels)
3769 continue; /* unnecessary NULL export */
3770
3771 memcpy(&exp->args[exp->num++], &args[c], sizeof(args[c]));
3772 }
3773 } else {
3774 struct ac_export_args args;
3775
3776 /* Export */
3777 si_llvm_init_export_args(ctx, color, V_008DFC_SQ_EXP_MRT + index,
3778 &args);
3779 if (is_last) {
3780 args.valid_mask = 1; /* whether the EXEC mask is valid */
3781 args.done = 1; /* DONE bit */
3782 } else if (!args.enabled_channels)
3783 return; /* unnecessary NULL export */
3784
3785 memcpy(&exp->args[exp->num++], &args, sizeof(args));
3786 }
3787 }
3788
3789 static void si_emit_ps_exports(struct si_shader_context *ctx,
3790 struct si_ps_exports *exp)
3791 {
3792 for (unsigned i = 0; i < exp->num; i++)
3793 ac_build_export(&ctx->ac, &exp->args[i]);
3794 }
3795
3796 static void si_export_null(struct lp_build_tgsi_context *bld_base)
3797 {
3798 struct si_shader_context *ctx = si_shader_context(bld_base);
3799 struct lp_build_context *base = &bld_base->base;
3800 struct ac_export_args args;
3801
3802 args.enabled_channels = 0x0; /* enabled channels */
3803 args.valid_mask = 1; /* whether the EXEC mask is valid */
3804 args.done = 1; /* DONE bit */
3805 args.target = V_008DFC_SQ_EXP_NULL;
3806 args.compr = 0; /* COMPR flag (0 = 32-bit export) */
3807 args.out[0] = base->undef; /* R */
3808 args.out[1] = base->undef; /* G */
3809 args.out[2] = base->undef; /* B */
3810 args.out[3] = base->undef; /* A */
3811
3812 ac_build_export(&ctx->ac, &args);
3813 }
3814
3815 /**
3816 * Return PS outputs in this order:
3817 *
3818 * v[0:3] = color0.xyzw
3819 * v[4:7] = color1.xyzw
3820 * ...
3821 * vN+0 = Depth
3822 * vN+1 = Stencil
3823 * vN+2 = SampleMask
3824 * vN+3 = SampleMaskIn (used for OpenGL smoothing)
3825 *
3826 * The alpha-ref SGPR is returned via its original location.
3827 */
3828 static void si_llvm_return_fs_outputs(struct ac_shader_abi *abi,
3829 unsigned max_outputs,
3830 LLVMValueRef *addrs)
3831 {
3832 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
3833 struct si_shader *shader = ctx->shader;
3834 struct tgsi_shader_info *info = &shader->selector->info;
3835 LLVMBuilderRef builder = ctx->ac.builder;
3836 unsigned i, j, first_vgpr, vgpr;
3837
3838 LLVMValueRef color[8][4] = {};
3839 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
3840 LLVMValueRef ret;
3841
3842 if (ctx->postponed_kill)
3843 ac_build_kill_if_false(&ctx->ac, LLVMBuildLoad(builder, ctx->postponed_kill, ""));
3844
3845 /* Read the output values. */
3846 for (i = 0; i < info->num_outputs; i++) {
3847 unsigned semantic_name = info->output_semantic_name[i];
3848 unsigned semantic_index = info->output_semantic_index[i];
3849
3850 switch (semantic_name) {
3851 case TGSI_SEMANTIC_COLOR:
3852 assert(semantic_index < 8);
3853 for (j = 0; j < 4; j++) {
3854 LLVMValueRef ptr = addrs[4 * i + j];
3855 LLVMValueRef result = LLVMBuildLoad(builder, ptr, "");
3856 color[semantic_index][j] = result;
3857 }
3858 break;
3859 case TGSI_SEMANTIC_POSITION:
3860 depth = LLVMBuildLoad(builder,
3861 addrs[4 * i + 2], "");
3862 break;
3863 case TGSI_SEMANTIC_STENCIL:
3864 stencil = LLVMBuildLoad(builder,
3865 addrs[4 * i + 1], "");
3866 break;
3867 case TGSI_SEMANTIC_SAMPLEMASK:
3868 samplemask = LLVMBuildLoad(builder,
3869 addrs[4 * i + 0], "");
3870 break;
3871 default:
3872 fprintf(stderr, "Warning: SI unhandled fs output type:%d\n",
3873 semantic_name);
3874 }
3875 }
3876
3877 /* Fill the return structure. */
3878 ret = ctx->return_value;
3879
3880 /* Set SGPRs. */
3881 ret = LLVMBuildInsertValue(builder, ret,
3882 ac_to_integer(&ctx->ac,
3883 LLVMGetParam(ctx->main_fn,
3884 SI_PARAM_ALPHA_REF)),
3885 SI_SGPR_ALPHA_REF, "");
3886
3887 /* Set VGPRs */
3888 first_vgpr = vgpr = SI_SGPR_ALPHA_REF + 1;
3889 for (i = 0; i < ARRAY_SIZE(color); i++) {
3890 if (!color[i][0])
3891 continue;
3892
3893 for (j = 0; j < 4; j++)
3894 ret = LLVMBuildInsertValue(builder, ret, color[i][j], vgpr++, "");
3895 }
3896 if (depth)
3897 ret = LLVMBuildInsertValue(builder, ret, depth, vgpr++, "");
3898 if (stencil)
3899 ret = LLVMBuildInsertValue(builder, ret, stencil, vgpr++, "");
3900 if (samplemask)
3901 ret = LLVMBuildInsertValue(builder, ret, samplemask, vgpr++, "");
3902
3903 /* Add the input sample mask for smoothing at the end. */
3904 if (vgpr < first_vgpr + PS_EPILOG_SAMPLEMASK_MIN_LOC)
3905 vgpr = first_vgpr + PS_EPILOG_SAMPLEMASK_MIN_LOC;
3906 ret = LLVMBuildInsertValue(builder, ret,
3907 LLVMGetParam(ctx->main_fn,
3908 SI_PARAM_SAMPLE_COVERAGE), vgpr++, "");
3909
3910 ctx->return_value = ret;
3911 }
3912
3913 static void membar_emit(
3914 const struct lp_build_tgsi_action *action,
3915 struct lp_build_tgsi_context *bld_base,
3916 struct lp_build_emit_data *emit_data)
3917 {
3918 struct si_shader_context *ctx = si_shader_context(bld_base);
3919 LLVMValueRef src0 = lp_build_emit_fetch(bld_base, emit_data->inst, 0, 0);
3920 unsigned flags = LLVMConstIntGetZExtValue(src0);
3921 unsigned waitcnt = NOOP_WAITCNT;
3922
3923 if (flags & TGSI_MEMBAR_THREAD_GROUP)
3924 waitcnt &= VM_CNT & LGKM_CNT;
3925
3926 if (flags & (TGSI_MEMBAR_ATOMIC_BUFFER |
3927 TGSI_MEMBAR_SHADER_BUFFER |
3928 TGSI_MEMBAR_SHADER_IMAGE))
3929 waitcnt &= VM_CNT;
3930
3931 if (flags & TGSI_MEMBAR_SHARED)
3932 waitcnt &= LGKM_CNT;
3933
3934 if (waitcnt != NOOP_WAITCNT)
3935 ac_build_waitcnt(&ctx->ac, waitcnt);
3936 }
3937
3938 static void clock_emit(
3939 const struct lp_build_tgsi_action *action,
3940 struct lp_build_tgsi_context *bld_base,
3941 struct lp_build_emit_data *emit_data)
3942 {
3943 struct si_shader_context *ctx = si_shader_context(bld_base);
3944 LLVMValueRef tmp;
3945
3946 tmp = lp_build_intrinsic(ctx->ac.builder, "llvm.readcyclecounter",
3947 ctx->i64, NULL, 0, 0);
3948 tmp = LLVMBuildBitCast(ctx->ac.builder, tmp, ctx->v2i32, "");
3949
3950 emit_data->output[0] =
3951 LLVMBuildExtractElement(ctx->ac.builder, tmp, ctx->i32_0, "");
3952 emit_data->output[1] =
3953 LLVMBuildExtractElement(ctx->ac.builder, tmp, ctx->i32_1, "");
3954 }
3955
3956 static void si_llvm_emit_ddxy(
3957 const struct lp_build_tgsi_action *action,
3958 struct lp_build_tgsi_context *bld_base,
3959 struct lp_build_emit_data *emit_data)
3960 {
3961 struct si_shader_context *ctx = si_shader_context(bld_base);
3962 unsigned opcode = emit_data->info->opcode;
3963 LLVMValueRef val;
3964 int idx;
3965 unsigned mask;
3966
3967 if (opcode == TGSI_OPCODE_DDX_FINE)
3968 mask = AC_TID_MASK_LEFT;
3969 else if (opcode == TGSI_OPCODE_DDY_FINE)
3970 mask = AC_TID_MASK_TOP;
3971 else
3972 mask = AC_TID_MASK_TOP_LEFT;
3973
3974 /* for DDX we want to next X pixel, DDY next Y pixel. */
3975 idx = (opcode == TGSI_OPCODE_DDX || opcode == TGSI_OPCODE_DDX_FINE) ? 1 : 2;
3976
3977 val = ac_to_integer(&ctx->ac, emit_data->args[0]);
3978 val = ac_build_ddxy(&ctx->ac, mask, idx, val);
3979 emit_data->output[emit_data->chan] = val;
3980 }
3981
3982 /*
3983 * this takes an I,J coordinate pair,
3984 * and works out the X and Y derivatives.
3985 * it returns DDX(I), DDX(J), DDY(I), DDY(J).
3986 */
3987 static LLVMValueRef si_llvm_emit_ddxy_interp(
3988 struct lp_build_tgsi_context *bld_base,
3989 LLVMValueRef interp_ij)
3990 {
3991 struct si_shader_context *ctx = si_shader_context(bld_base);
3992 LLVMValueRef result[4], a;
3993 unsigned i;
3994
3995 for (i = 0; i < 2; i++) {
3996 a = LLVMBuildExtractElement(ctx->ac.builder, interp_ij,
3997 LLVMConstInt(ctx->i32, i, 0), "");
3998 result[i] = lp_build_emit_llvm_unary(bld_base, TGSI_OPCODE_DDX, a);
3999 result[2+i] = lp_build_emit_llvm_unary(bld_base, TGSI_OPCODE_DDY, a);
4000 }
4001
4002 return lp_build_gather_values(&ctx->gallivm, result, 4);
4003 }
4004
4005 static void interp_fetch_args(
4006 struct lp_build_tgsi_context *bld_base,
4007 struct lp_build_emit_data *emit_data)
4008 {
4009 struct si_shader_context *ctx = si_shader_context(bld_base);
4010 const struct tgsi_full_instruction *inst = emit_data->inst;
4011
4012 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET) {
4013 /* offset is in second src, first two channels */
4014 emit_data->args[0] = lp_build_emit_fetch(bld_base,
4015 emit_data->inst, 1,
4016 TGSI_CHAN_X);
4017 emit_data->args[1] = lp_build_emit_fetch(bld_base,
4018 emit_data->inst, 1,
4019 TGSI_CHAN_Y);
4020 emit_data->arg_count = 2;
4021 } else if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
4022 LLVMValueRef sample_position;
4023 LLVMValueRef sample_id;
4024 LLVMValueRef halfval = LLVMConstReal(ctx->f32, 0.5f);
4025
4026 /* fetch sample ID, then fetch its sample position,
4027 * and place into first two channels.
4028 */
4029 sample_id = lp_build_emit_fetch(bld_base,
4030 emit_data->inst, 1, TGSI_CHAN_X);
4031 sample_id = ac_to_integer(&ctx->ac, sample_id);
4032
4033 /* Section 8.13.2 (Interpolation Functions) of the OpenGL Shading
4034 * Language 4.50 spec says about interpolateAtSample:
4035 *
4036 * "Returns the value of the input interpolant variable at
4037 * the location of sample number sample. If multisample
4038 * buffers are not available, the input variable will be
4039 * evaluated at the center of the pixel. If sample sample
4040 * does not exist, the position used to interpolate the
4041 * input variable is undefined."
4042 *
4043 * This means that sample_id values outside of the valid are
4044 * in fact valid input, and the usual mechanism for loading the
4045 * sample position doesn't work.
4046 */
4047 if (ctx->shader->key.mono.u.ps.interpolate_at_sample_force_center) {
4048 LLVMValueRef center[4] = {
4049 LLVMConstReal(ctx->f32, 0.5),
4050 LLVMConstReal(ctx->f32, 0.5),
4051 ctx->ac.f32_0,
4052 ctx->ac.f32_0,
4053 };
4054
4055 sample_position = lp_build_gather_values(&ctx->gallivm, center, 4);
4056 } else {
4057 sample_position = load_sample_position(&ctx->abi, sample_id);
4058 }
4059
4060 emit_data->args[0] = LLVMBuildExtractElement(ctx->ac.builder,
4061 sample_position,
4062 ctx->i32_0, "");
4063
4064 emit_data->args[0] = LLVMBuildFSub(ctx->ac.builder, emit_data->args[0], halfval, "");
4065 emit_data->args[1] = LLVMBuildExtractElement(ctx->ac.builder,
4066 sample_position,
4067 ctx->i32_1, "");
4068 emit_data->args[1] = LLVMBuildFSub(ctx->ac.builder, emit_data->args[1], halfval, "");
4069 emit_data->arg_count = 2;
4070 }
4071 }
4072
4073 static void build_interp_intrinsic(const struct lp_build_tgsi_action *action,
4074 struct lp_build_tgsi_context *bld_base,
4075 struct lp_build_emit_data *emit_data)
4076 {
4077 struct si_shader_context *ctx = si_shader_context(bld_base);
4078 struct si_shader *shader = ctx->shader;
4079 const struct tgsi_shader_info *info = &shader->selector->info;
4080 LLVMValueRef interp_param;
4081 const struct tgsi_full_instruction *inst = emit_data->inst;
4082 const struct tgsi_full_src_register *input = &inst->Src[0];
4083 int input_base, input_array_size;
4084 int chan;
4085 int i;
4086 LLVMValueRef prim_mask = ctx->abi.prim_mask;
4087 LLVMValueRef array_idx;
4088 int interp_param_idx;
4089 unsigned interp;
4090 unsigned location;
4091
4092 assert(input->Register.File == TGSI_FILE_INPUT);
4093
4094 if (input->Register.Indirect) {
4095 unsigned array_id = input->Indirect.ArrayID;
4096
4097 if (array_id) {
4098 input_base = info->input_array_first[array_id];
4099 input_array_size = info->input_array_last[array_id] - input_base + 1;
4100 } else {
4101 input_base = inst->Src[0].Register.Index;
4102 input_array_size = info->num_inputs - input_base;
4103 }
4104
4105 array_idx = si_get_indirect_index(ctx, &input->Indirect,
4106 1, input->Register.Index - input_base);
4107 } else {
4108 input_base = inst->Src[0].Register.Index;
4109 input_array_size = 1;
4110 array_idx = ctx->i32_0;
4111 }
4112
4113 interp = shader->selector->info.input_interpolate[input_base];
4114
4115 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
4116 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE)
4117 location = TGSI_INTERPOLATE_LOC_CENTER;
4118 else
4119 location = TGSI_INTERPOLATE_LOC_CENTROID;
4120
4121 interp_param_idx = lookup_interp_param_index(interp, location);
4122 if (interp_param_idx == -1)
4123 return;
4124 else if (interp_param_idx)
4125 interp_param = LLVMGetParam(ctx->main_fn, interp_param_idx);
4126 else
4127 interp_param = NULL;
4128
4129 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
4130 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
4131 LLVMValueRef ij_out[2];
4132 LLVMValueRef ddxy_out = si_llvm_emit_ddxy_interp(bld_base, interp_param);
4133
4134 /*
4135 * take the I then J parameters, and the DDX/Y for it, and
4136 * calculate the IJ inputs for the interpolator.
4137 * temp1 = ddx * offset/sample.x + I;
4138 * interp_param.I = ddy * offset/sample.y + temp1;
4139 * temp1 = ddx * offset/sample.x + J;
4140 * interp_param.J = ddy * offset/sample.y + temp1;
4141 */
4142 for (i = 0; i < 2; i++) {
4143 LLVMValueRef ix_ll = LLVMConstInt(ctx->i32, i, 0);
4144 LLVMValueRef iy_ll = LLVMConstInt(ctx->i32, i + 2, 0);
4145 LLVMValueRef ddx_el = LLVMBuildExtractElement(ctx->ac.builder,
4146 ddxy_out, ix_ll, "");
4147 LLVMValueRef ddy_el = LLVMBuildExtractElement(ctx->ac.builder,
4148 ddxy_out, iy_ll, "");
4149 LLVMValueRef interp_el = LLVMBuildExtractElement(ctx->ac.builder,
4150 interp_param, ix_ll, "");
4151 LLVMValueRef temp1, temp2;
4152
4153 interp_el = ac_to_float(&ctx->ac, interp_el);
4154
4155 temp1 = LLVMBuildFMul(ctx->ac.builder, ddx_el, emit_data->args[0], "");
4156
4157 temp1 = LLVMBuildFAdd(ctx->ac.builder, temp1, interp_el, "");
4158
4159 temp2 = LLVMBuildFMul(ctx->ac.builder, ddy_el, emit_data->args[1], "");
4160
4161 ij_out[i] = LLVMBuildFAdd(ctx->ac.builder, temp2, temp1, "");
4162 }
4163 interp_param = lp_build_gather_values(&ctx->gallivm, ij_out, 2);
4164 }
4165
4166 if (interp_param)
4167 interp_param = ac_to_float(&ctx->ac, interp_param);
4168
4169 for (chan = 0; chan < 4; chan++) {
4170 LLVMValueRef gather = LLVMGetUndef(LLVMVectorType(ctx->f32, input_array_size));
4171 unsigned schan = tgsi_util_get_full_src_register_swizzle(&inst->Src[0], chan);
4172
4173 for (unsigned idx = 0; idx < input_array_size; ++idx) {
4174 LLVMValueRef v, i = NULL, j = NULL;
4175
4176 if (interp_param) {
4177 i = LLVMBuildExtractElement(
4178 ctx->ac.builder, interp_param, ctx->i32_0, "");
4179 j = LLVMBuildExtractElement(
4180 ctx->ac.builder, interp_param, ctx->i32_1, "");
4181 }
4182 v = si_build_fs_interp(ctx, input_base + idx, schan,
4183 prim_mask, i, j);
4184
4185 gather = LLVMBuildInsertElement(ctx->ac.builder,
4186 gather, v, LLVMConstInt(ctx->i32, idx, false), "");
4187 }
4188
4189 emit_data->output[chan] = LLVMBuildExtractElement(
4190 ctx->ac.builder, gather, array_idx, "");
4191 }
4192 }
4193
4194 static void vote_all_emit(
4195 const struct lp_build_tgsi_action *action,
4196 struct lp_build_tgsi_context *bld_base,
4197 struct lp_build_emit_data *emit_data)
4198 {
4199 struct si_shader_context *ctx = si_shader_context(bld_base);
4200
4201 LLVMValueRef tmp = ac_build_vote_all(&ctx->ac, emit_data->args[0]);
4202 emit_data->output[emit_data->chan] =
4203 LLVMBuildSExt(ctx->ac.builder, tmp, ctx->i32, "");
4204 }
4205
4206 static void vote_any_emit(
4207 const struct lp_build_tgsi_action *action,
4208 struct lp_build_tgsi_context *bld_base,
4209 struct lp_build_emit_data *emit_data)
4210 {
4211 struct si_shader_context *ctx = si_shader_context(bld_base);
4212
4213 LLVMValueRef tmp = ac_build_vote_any(&ctx->ac, emit_data->args[0]);
4214 emit_data->output[emit_data->chan] =
4215 LLVMBuildSExt(ctx->ac.builder, tmp, ctx->i32, "");
4216 }
4217
4218 static void vote_eq_emit(
4219 const struct lp_build_tgsi_action *action,
4220 struct lp_build_tgsi_context *bld_base,
4221 struct lp_build_emit_data *emit_data)
4222 {
4223 struct si_shader_context *ctx = si_shader_context(bld_base);
4224
4225 LLVMValueRef tmp = ac_build_vote_eq(&ctx->ac, emit_data->args[0]);
4226 emit_data->output[emit_data->chan] =
4227 LLVMBuildSExt(ctx->ac.builder, tmp, ctx->i32, "");
4228 }
4229
4230 static void ballot_emit(
4231 const struct lp_build_tgsi_action *action,
4232 struct lp_build_tgsi_context *bld_base,
4233 struct lp_build_emit_data *emit_data)
4234 {
4235 struct si_shader_context *ctx = si_shader_context(bld_base);
4236 LLVMBuilderRef builder = ctx->ac.builder;
4237 LLVMValueRef tmp;
4238
4239 tmp = lp_build_emit_fetch(bld_base, emit_data->inst, 0, TGSI_CHAN_X);
4240 tmp = ac_build_ballot(&ctx->ac, tmp);
4241 tmp = LLVMBuildBitCast(builder, tmp, ctx->v2i32, "");
4242
4243 emit_data->output[0] = LLVMBuildExtractElement(builder, tmp, ctx->i32_0, "");
4244 emit_data->output[1] = LLVMBuildExtractElement(builder, tmp, ctx->i32_1, "");
4245 }
4246
4247 static void read_invoc_fetch_args(
4248 struct lp_build_tgsi_context *bld_base,
4249 struct lp_build_emit_data *emit_data)
4250 {
4251 emit_data->args[0] = lp_build_emit_fetch(bld_base, emit_data->inst,
4252 0, emit_data->src_chan);
4253
4254 /* Always read the source invocation (= lane) from the X channel. */
4255 emit_data->args[1] = lp_build_emit_fetch(bld_base, emit_data->inst,
4256 1, TGSI_CHAN_X);
4257 emit_data->arg_count = 2;
4258 }
4259
4260 static void read_lane_emit(
4261 const struct lp_build_tgsi_action *action,
4262 struct lp_build_tgsi_context *bld_base,
4263 struct lp_build_emit_data *emit_data)
4264 {
4265 struct si_shader_context *ctx = si_shader_context(bld_base);
4266
4267 /* We currently have no other way to prevent LLVM from lifting the icmp
4268 * calls to a dominating basic block.
4269 */
4270 ac_build_optimization_barrier(&ctx->ac, &emit_data->args[0]);
4271
4272 for (unsigned i = 0; i < emit_data->arg_count; ++i)
4273 emit_data->args[i] = ac_to_integer(&ctx->ac, emit_data->args[i]);
4274
4275 emit_data->output[emit_data->chan] =
4276 ac_build_intrinsic(&ctx->ac, action->intr_name,
4277 ctx->i32, emit_data->args, emit_data->arg_count,
4278 AC_FUNC_ATTR_READNONE |
4279 AC_FUNC_ATTR_CONVERGENT);
4280 }
4281
4282 static unsigned si_llvm_get_stream(struct lp_build_tgsi_context *bld_base,
4283 struct lp_build_emit_data *emit_data)
4284 {
4285 struct si_shader_context *ctx = si_shader_context(bld_base);
4286 struct tgsi_src_register src0 = emit_data->inst->Src[0].Register;
4287 LLVMValueRef imm;
4288 unsigned stream;
4289
4290 assert(src0.File == TGSI_FILE_IMMEDIATE);
4291
4292 imm = ctx->imms[src0.Index * TGSI_NUM_CHANNELS + src0.SwizzleX];
4293 stream = LLVMConstIntGetZExtValue(imm) & 0x3;
4294 return stream;
4295 }
4296
4297 /* Emit one vertex from the geometry shader */
4298 static void si_llvm_emit_vertex(struct ac_shader_abi *abi,
4299 unsigned stream,
4300 LLVMValueRef *addrs)
4301 {
4302 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
4303 struct tgsi_shader_info *info = &ctx->shader->selector->info;
4304 struct lp_build_context *uint = &ctx->bld_base.uint_bld;
4305 struct si_shader *shader = ctx->shader;
4306 struct lp_build_if_state if_state;
4307 LLVMValueRef soffset = LLVMGetParam(ctx->main_fn,
4308 ctx->param_gs2vs_offset);
4309 LLVMValueRef gs_next_vertex;
4310 LLVMValueRef can_emit;
4311 unsigned chan, offset;
4312 int i;
4313
4314 /* Write vertex attribute values to GSVS ring */
4315 gs_next_vertex = LLVMBuildLoad(ctx->ac.builder,
4316 ctx->gs_next_vertex[stream],
4317 "");
4318
4319 /* If this thread has already emitted the declared maximum number of
4320 * vertices, skip the write: excessive vertex emissions are not
4321 * supposed to have any effect.
4322 *
4323 * If the shader has no writes to memory, kill it instead. This skips
4324 * further memory loads and may allow LLVM to skip to the end
4325 * altogether.
4326 */
4327 can_emit = LLVMBuildICmp(ctx->ac.builder, LLVMIntULT, gs_next_vertex,
4328 LLVMConstInt(ctx->i32,
4329 shader->selector->gs_max_out_vertices, 0), "");
4330
4331 bool use_kill = !info->writes_memory;
4332 if (use_kill) {
4333 ac_build_kill_if_false(&ctx->ac, can_emit);
4334 } else {
4335 lp_build_if(&if_state, &ctx->gallivm, can_emit);
4336 }
4337
4338 offset = 0;
4339 for (i = 0; i < info->num_outputs; i++) {
4340 for (chan = 0; chan < 4; chan++) {
4341 if (!(info->output_usagemask[i] & (1 << chan)) ||
4342 ((info->output_streams[i] >> (2 * chan)) & 3) != stream)
4343 continue;
4344
4345 LLVMValueRef out_val = LLVMBuildLoad(ctx->ac.builder, addrs[4 * i + chan], "");
4346 LLVMValueRef voffset =
4347 LLVMConstInt(ctx->i32, offset *
4348 shader->selector->gs_max_out_vertices, 0);
4349 offset++;
4350
4351 voffset = lp_build_add(uint, voffset, gs_next_vertex);
4352 voffset = lp_build_mul_imm(uint, voffset, 4);
4353
4354 out_val = ac_to_integer(&ctx->ac, out_val);
4355
4356 ac_build_buffer_store_dword(&ctx->ac,
4357 ctx->gsvs_ring[stream],
4358 out_val, 1,
4359 voffset, soffset, 0,
4360 1, 1, true, true);
4361 }
4362 }
4363
4364 gs_next_vertex = lp_build_add(uint, gs_next_vertex,
4365 ctx->i32_1);
4366
4367 LLVMBuildStore(ctx->ac.builder, gs_next_vertex, ctx->gs_next_vertex[stream]);
4368
4369 /* Signal vertex emission */
4370 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_EMIT | AC_SENDMSG_GS | (stream << 8),
4371 si_get_gs_wave_id(ctx));
4372 if (!use_kill)
4373 lp_build_endif(&if_state);
4374 }
4375
4376 /* Emit one vertex from the geometry shader */
4377 static void si_tgsi_emit_vertex(
4378 const struct lp_build_tgsi_action *action,
4379 struct lp_build_tgsi_context *bld_base,
4380 struct lp_build_emit_data *emit_data)
4381 {
4382 struct si_shader_context *ctx = si_shader_context(bld_base);
4383 unsigned stream = si_llvm_get_stream(bld_base, emit_data);
4384
4385 si_llvm_emit_vertex(&ctx->abi, stream, ctx->outputs[0]);
4386 }
4387
4388 /* Cut one primitive from the geometry shader */
4389 static void si_llvm_emit_primitive(struct ac_shader_abi *abi,
4390 unsigned stream)
4391 {
4392 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
4393
4394 /* Signal primitive cut */
4395 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_CUT | AC_SENDMSG_GS | (stream << 8),
4396 si_get_gs_wave_id(ctx));
4397 }
4398
4399 /* Cut one primitive from the geometry shader */
4400 static void si_tgsi_emit_primitive(
4401 const struct lp_build_tgsi_action *action,
4402 struct lp_build_tgsi_context *bld_base,
4403 struct lp_build_emit_data *emit_data)
4404 {
4405 struct si_shader_context *ctx = si_shader_context(bld_base);
4406
4407 si_llvm_emit_primitive(&ctx->abi, si_llvm_get_stream(bld_base, emit_data));
4408 }
4409
4410 static void si_llvm_emit_barrier(const struct lp_build_tgsi_action *action,
4411 struct lp_build_tgsi_context *bld_base,
4412 struct lp_build_emit_data *emit_data)
4413 {
4414 struct si_shader_context *ctx = si_shader_context(bld_base);
4415
4416 /* SI only (thanks to a hw bug workaround):
4417 * The real barrier instruction isn’t needed, because an entire patch
4418 * always fits into a single wave.
4419 */
4420 if (ctx->screen->info.chip_class == SI &&
4421 ctx->type == PIPE_SHADER_TESS_CTRL) {
4422 ac_build_waitcnt(&ctx->ac, LGKM_CNT & VM_CNT);
4423 return;
4424 }
4425
4426 lp_build_intrinsic(ctx->ac.builder,
4427 "llvm.amdgcn.s.barrier",
4428 ctx->voidt, NULL, 0, LP_FUNC_ATTR_CONVERGENT);
4429 }
4430
4431 static const struct lp_build_tgsi_action interp_action = {
4432 .fetch_args = interp_fetch_args,
4433 .emit = build_interp_intrinsic,
4434 };
4435
4436 static void si_create_function(struct si_shader_context *ctx,
4437 const char *name,
4438 LLVMTypeRef *returns, unsigned num_returns,
4439 struct si_function_info *fninfo,
4440 unsigned max_workgroup_size)
4441 {
4442 int i;
4443
4444 si_llvm_create_func(ctx, name, returns, num_returns,
4445 fninfo->types, fninfo->num_params);
4446 ctx->return_value = LLVMGetUndef(ctx->return_type);
4447
4448 for (i = 0; i < fninfo->num_sgpr_params; ++i) {
4449 LLVMValueRef P = LLVMGetParam(ctx->main_fn, i);
4450
4451 /* The combination of:
4452 * - noalias
4453 * - dereferenceable
4454 * - invariant.load
4455 * allows the optimization passes to move loads and reduces
4456 * SGPR spilling significantly.
4457 */
4458 lp_add_function_attr(ctx->main_fn, i + 1, LP_FUNC_ATTR_INREG);
4459
4460 if (LLVMGetTypeKind(LLVMTypeOf(P)) == LLVMPointerTypeKind) {
4461 lp_add_function_attr(ctx->main_fn, i + 1, LP_FUNC_ATTR_NOALIAS);
4462 ac_add_attr_dereferenceable(P, UINT64_MAX);
4463 }
4464 }
4465
4466 for (i = 0; i < fninfo->num_params; ++i) {
4467 if (fninfo->assign[i])
4468 *fninfo->assign[i] = LLVMGetParam(ctx->main_fn, i);
4469 }
4470
4471 if (max_workgroup_size) {
4472 si_llvm_add_attribute(ctx->main_fn, "amdgpu-max-work-group-size",
4473 max_workgroup_size);
4474 }
4475 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
4476 "no-signed-zeros-fp-math",
4477 "true");
4478
4479 if (ctx->screen->debug_flags & DBG(UNSAFE_MATH)) {
4480 /* These were copied from some LLVM test. */
4481 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
4482 "less-precise-fpmad",
4483 "true");
4484 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
4485 "no-infs-fp-math",
4486 "true");
4487 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
4488 "no-nans-fp-math",
4489 "true");
4490 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
4491 "unsafe-fp-math",
4492 "true");
4493 }
4494 }
4495
4496 static void declare_streamout_params(struct si_shader_context *ctx,
4497 struct pipe_stream_output_info *so,
4498 struct si_function_info *fninfo)
4499 {
4500 int i;
4501
4502 /* Streamout SGPRs. */
4503 if (so->num_outputs) {
4504 if (ctx->type != PIPE_SHADER_TESS_EVAL)
4505 ctx->param_streamout_config = add_arg(fninfo, ARG_SGPR, ctx->ac.i32);
4506 else
4507 ctx->param_streamout_config = fninfo->num_params - 1;
4508
4509 ctx->param_streamout_write_index = add_arg(fninfo, ARG_SGPR, ctx->ac.i32);
4510 }
4511 /* A streamout buffer offset is loaded if the stride is non-zero. */
4512 for (i = 0; i < 4; i++) {
4513 if (!so->stride[i])
4514 continue;
4515
4516 ctx->param_streamout_offset[i] = add_arg(fninfo, ARG_SGPR, ctx->ac.i32);
4517 }
4518 }
4519
4520 static unsigned si_get_max_workgroup_size(const struct si_shader *shader)
4521 {
4522 switch (shader->selector->type) {
4523 case PIPE_SHADER_TESS_CTRL:
4524 /* Return this so that LLVM doesn't remove s_barrier
4525 * instructions on chips where we use s_barrier. */
4526 return shader->selector->screen->info.chip_class >= CIK ? 128 : 64;
4527
4528 case PIPE_SHADER_GEOMETRY:
4529 return shader->selector->screen->info.chip_class >= GFX9 ? 128 : 64;
4530
4531 case PIPE_SHADER_COMPUTE:
4532 break; /* see below */
4533
4534 default:
4535 return 0;
4536 }
4537
4538 const unsigned *properties = shader->selector->info.properties;
4539 unsigned max_work_group_size =
4540 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] *
4541 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT] *
4542 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH];
4543
4544 if (!max_work_group_size) {
4545 /* This is a variable group size compute shader,
4546 * compile it for the maximum possible group size.
4547 */
4548 max_work_group_size = SI_MAX_VARIABLE_THREADS_PER_BLOCK;
4549 }
4550 return max_work_group_size;
4551 }
4552
4553 static void declare_per_stage_desc_pointers(struct si_shader_context *ctx,
4554 struct si_function_info *fninfo,
4555 bool assign_params)
4556 {
4557 LLVMTypeRef const_shader_buf_type;
4558
4559 if (ctx->shader->selector->info.const_buffers_declared == 1 &&
4560 ctx->shader->selector->info.shader_buffers_declared == 0)
4561 const_shader_buf_type = ctx->f32;
4562 else
4563 const_shader_buf_type = ctx->v4i32;
4564
4565 unsigned const_and_shader_buffers =
4566 add_arg(fninfo, ARG_SGPR,
4567 ac_array_in_const_addr_space(const_shader_buf_type));
4568
4569 unsigned samplers_and_images =
4570 add_arg(fninfo, ARG_SGPR,
4571 ac_array_in_const_addr_space(ctx->v8i32));
4572
4573 if (assign_params) {
4574 ctx->param_const_and_shader_buffers = const_and_shader_buffers;
4575 ctx->param_samplers_and_images = samplers_and_images;
4576 }
4577 }
4578
4579 static void declare_global_desc_pointers(struct si_shader_context *ctx,
4580 struct si_function_info *fninfo)
4581 {
4582 ctx->param_rw_buffers = add_arg(fninfo, ARG_SGPR,
4583 ac_array_in_const_addr_space(ctx->v4i32));
4584 ctx->param_bindless_samplers_and_images = add_arg(fninfo, ARG_SGPR,
4585 ac_array_in_const_addr_space(ctx->v8i32));
4586 }
4587
4588 static void declare_vs_specific_input_sgprs(struct si_shader_context *ctx,
4589 struct si_function_info *fninfo)
4590 {
4591 ctx->param_vertex_buffers = add_arg(fninfo, ARG_SGPR,
4592 ac_array_in_const_addr_space(ctx->v4i32));
4593 add_arg_assign(fninfo, ARG_SGPR, ctx->i32, &ctx->abi.base_vertex);
4594 add_arg_assign(fninfo, ARG_SGPR, ctx->i32, &ctx->abi.start_instance);
4595 add_arg_assign(fninfo, ARG_SGPR, ctx->i32, &ctx->abi.draw_id);
4596 ctx->param_vs_state_bits = add_arg(fninfo, ARG_SGPR, ctx->i32);
4597 }
4598
4599 static void declare_vs_input_vgprs(struct si_shader_context *ctx,
4600 struct si_function_info *fninfo,
4601 unsigned *num_prolog_vgprs)
4602 {
4603 struct si_shader *shader = ctx->shader;
4604
4605 add_arg_assign(fninfo, ARG_VGPR, ctx->i32, &ctx->abi.vertex_id);
4606 if (shader->key.as_ls) {
4607 ctx->param_rel_auto_id = add_arg(fninfo, ARG_VGPR, ctx->i32);
4608 add_arg_assign(fninfo, ARG_VGPR, ctx->i32, &ctx->abi.instance_id);
4609 } else {
4610 add_arg_assign(fninfo, ARG_VGPR, ctx->i32, &ctx->abi.instance_id);
4611 ctx->param_vs_prim_id = add_arg(fninfo, ARG_VGPR, ctx->i32);
4612 }
4613 add_arg(fninfo, ARG_VGPR, ctx->i32); /* unused */
4614
4615 if (!shader->is_gs_copy_shader) {
4616 /* Vertex load indices. */
4617 ctx->param_vertex_index0 = fninfo->num_params;
4618 for (unsigned i = 0; i < shader->selector->info.num_inputs; i++)
4619 add_arg(fninfo, ARG_VGPR, ctx->i32);
4620 *num_prolog_vgprs += shader->selector->info.num_inputs;
4621 }
4622 }
4623
4624 static void declare_tes_input_vgprs(struct si_shader_context *ctx,
4625 struct si_function_info *fninfo)
4626 {
4627 ctx->param_tes_u = add_arg(fninfo, ARG_VGPR, ctx->f32);
4628 ctx->param_tes_v = add_arg(fninfo, ARG_VGPR, ctx->f32);
4629 ctx->param_tes_rel_patch_id = add_arg(fninfo, ARG_VGPR, ctx->i32);
4630 add_arg_assign(fninfo, ARG_VGPR, ctx->i32, &ctx->abi.tes_patch_id);
4631 }
4632
4633 enum {
4634 /* Convenient merged shader definitions. */
4635 SI_SHADER_MERGED_VERTEX_TESSCTRL = PIPE_SHADER_TYPES,
4636 SI_SHADER_MERGED_VERTEX_OR_TESSEVAL_GEOMETRY,
4637 };
4638
4639 static void create_function(struct si_shader_context *ctx)
4640 {
4641 struct si_shader *shader = ctx->shader;
4642 struct si_function_info fninfo;
4643 LLVMTypeRef returns[16+32*4];
4644 unsigned i, num_return_sgprs;
4645 unsigned num_returns = 0;
4646 unsigned num_prolog_vgprs = 0;
4647 unsigned type = ctx->type;
4648 unsigned vs_blit_property =
4649 shader->selector->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS];
4650
4651 si_init_function_info(&fninfo);
4652
4653 /* Set MERGED shaders. */
4654 if (ctx->screen->info.chip_class >= GFX9) {
4655 if (shader->key.as_ls || type == PIPE_SHADER_TESS_CTRL)
4656 type = SI_SHADER_MERGED_VERTEX_TESSCTRL; /* LS or HS */
4657 else if (shader->key.as_es || type == PIPE_SHADER_GEOMETRY)
4658 type = SI_SHADER_MERGED_VERTEX_OR_TESSEVAL_GEOMETRY;
4659 }
4660
4661 LLVMTypeRef v3i32 = LLVMVectorType(ctx->i32, 3);
4662
4663 switch (type) {
4664 case PIPE_SHADER_VERTEX:
4665 declare_global_desc_pointers(ctx, &fninfo);
4666
4667 if (vs_blit_property) {
4668 ctx->param_vs_blit_inputs = fninfo.num_params;
4669 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* i16 x1, y1 */
4670 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* i16 x2, y2 */
4671 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* depth */
4672
4673 if (vs_blit_property == SI_VS_BLIT_SGPRS_POS_COLOR) {
4674 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* color0 */
4675 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* color1 */
4676 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* color2 */
4677 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* color3 */
4678 } else if (vs_blit_property == SI_VS_BLIT_SGPRS_POS_TEXCOORD) {
4679 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* texcoord.x1 */
4680 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* texcoord.y1 */
4681 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* texcoord.x2 */
4682 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* texcoord.y2 */
4683 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* texcoord.z */
4684 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* texcoord.w */
4685 }
4686
4687 /* VGPRs */
4688 declare_vs_input_vgprs(ctx, &fninfo, &num_prolog_vgprs);
4689 break;
4690 }
4691
4692 declare_per_stage_desc_pointers(ctx, &fninfo, true);
4693 declare_vs_specific_input_sgprs(ctx, &fninfo);
4694
4695 if (shader->key.as_es) {
4696 ctx->param_es2gs_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4697 } else if (shader->key.as_ls) {
4698 /* no extra parameters */
4699 } else {
4700 if (shader->is_gs_copy_shader) {
4701 fninfo.num_params = ctx->param_rw_buffers + 1;
4702 fninfo.num_sgpr_params = fninfo.num_params;
4703 }
4704
4705 /* The locations of the other parameters are assigned dynamically. */
4706 declare_streamout_params(ctx, &shader->selector->so,
4707 &fninfo);
4708 }
4709
4710 /* VGPRs */
4711 declare_vs_input_vgprs(ctx, &fninfo, &num_prolog_vgprs);
4712 break;
4713
4714 case PIPE_SHADER_TESS_CTRL: /* SI-CI-VI */
4715 declare_global_desc_pointers(ctx, &fninfo);
4716 declare_per_stage_desc_pointers(ctx, &fninfo, true);
4717 ctx->param_tcs_offchip_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4718 ctx->param_tcs_out_lds_offsets = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4719 ctx->param_tcs_out_lds_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4720 ctx->param_vs_state_bits = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4721 ctx->param_tcs_offchip_addr_base64k = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4722 ctx->param_tcs_factor_addr_base64k = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4723 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4724 ctx->param_tcs_factor_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4725
4726 /* VGPRs */
4727 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->abi.tcs_patch_id);
4728 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->abi.tcs_rel_ids);
4729
4730 /* param_tcs_offchip_offset and param_tcs_factor_offset are
4731 * placed after the user SGPRs.
4732 */
4733 for (i = 0; i < GFX6_TCS_NUM_USER_SGPR + 2; i++)
4734 returns[num_returns++] = ctx->i32; /* SGPRs */
4735 for (i = 0; i < 11; i++)
4736 returns[num_returns++] = ctx->f32; /* VGPRs */
4737 break;
4738
4739 case SI_SHADER_MERGED_VERTEX_TESSCTRL:
4740 /* Merged stages have 8 system SGPRs at the beginning. */
4741 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* SPI_SHADER_USER_DATA_ADDR_LO_HS */
4742 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* SPI_SHADER_USER_DATA_ADDR_HI_HS */
4743 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4744 ctx->param_merged_wave_info = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4745 ctx->param_tcs_factor_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4746 ctx->param_merged_scratch_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4747 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused */
4748 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused */
4749
4750 declare_global_desc_pointers(ctx, &fninfo);
4751 declare_per_stage_desc_pointers(ctx, &fninfo,
4752 ctx->type == PIPE_SHADER_VERTEX);
4753 declare_vs_specific_input_sgprs(ctx, &fninfo);
4754
4755 ctx->param_tcs_offchip_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4756 ctx->param_tcs_out_lds_offsets = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4757 ctx->param_tcs_out_lds_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4758 ctx->param_tcs_offchip_addr_base64k = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4759 ctx->param_tcs_factor_addr_base64k = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4760 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused */
4761
4762 declare_per_stage_desc_pointers(ctx, &fninfo,
4763 ctx->type == PIPE_SHADER_TESS_CTRL);
4764
4765 /* VGPRs (first TCS, then VS) */
4766 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->abi.tcs_patch_id);
4767 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->abi.tcs_rel_ids);
4768
4769 if (ctx->type == PIPE_SHADER_VERTEX) {
4770 declare_vs_input_vgprs(ctx, &fninfo,
4771 &num_prolog_vgprs);
4772
4773 /* LS return values are inputs to the TCS main shader part. */
4774 for (i = 0; i < 8 + GFX9_TCS_NUM_USER_SGPR; i++)
4775 returns[num_returns++] = ctx->i32; /* SGPRs */
4776 for (i = 0; i < 2; i++)
4777 returns[num_returns++] = ctx->f32; /* VGPRs */
4778 } else {
4779 /* TCS return values are inputs to the TCS epilog.
4780 *
4781 * param_tcs_offchip_offset, param_tcs_factor_offset,
4782 * param_tcs_offchip_layout, and param_rw_buffers
4783 * should be passed to the epilog.
4784 */
4785 for (i = 0; i <= 8 + GFX9_SGPR_TCS_FACTOR_ADDR_BASE64K; i++)
4786 returns[num_returns++] = ctx->i32; /* SGPRs */
4787 for (i = 0; i < 11; i++)
4788 returns[num_returns++] = ctx->f32; /* VGPRs */
4789 }
4790 break;
4791
4792 case SI_SHADER_MERGED_VERTEX_OR_TESSEVAL_GEOMETRY:
4793 /* Merged stages have 8 system SGPRs at the beginning. */
4794 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused (SPI_SHADER_USER_DATA_ADDR_LO_GS) */
4795 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused (SPI_SHADER_USER_DATA_ADDR_HI_GS) */
4796 ctx->param_gs2vs_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4797 ctx->param_merged_wave_info = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4798 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4799 ctx->param_merged_scratch_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4800 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused (SPI_SHADER_PGM_LO/HI_GS << 8) */
4801 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused (SPI_SHADER_PGM_LO/HI_GS >> 24) */
4802
4803 declare_global_desc_pointers(ctx, &fninfo);
4804 declare_per_stage_desc_pointers(ctx, &fninfo,
4805 (ctx->type == PIPE_SHADER_VERTEX ||
4806 ctx->type == PIPE_SHADER_TESS_EVAL));
4807 if (ctx->type == PIPE_SHADER_VERTEX) {
4808 declare_vs_specific_input_sgprs(ctx, &fninfo);
4809 } else {
4810 /* TESS_EVAL (and also GEOMETRY):
4811 * Declare as many input SGPRs as the VS has. */
4812 ctx->param_tcs_offchip_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4813 ctx->param_tcs_offchip_addr_base64k = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4814 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused */
4815 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused */
4816 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused */
4817 ctx->param_vs_state_bits = add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused */
4818 }
4819
4820 declare_per_stage_desc_pointers(ctx, &fninfo,
4821 ctx->type == PIPE_SHADER_GEOMETRY);
4822
4823 /* VGPRs (first GS, then VS/TES) */
4824 ctx->param_gs_vtx01_offset = add_arg(&fninfo, ARG_VGPR, ctx->i32);
4825 ctx->param_gs_vtx23_offset = add_arg(&fninfo, ARG_VGPR, ctx->i32);
4826 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->abi.gs_prim_id);
4827 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->abi.gs_invocation_id);
4828 ctx->param_gs_vtx45_offset = add_arg(&fninfo, ARG_VGPR, ctx->i32);
4829
4830 if (ctx->type == PIPE_SHADER_VERTEX) {
4831 declare_vs_input_vgprs(ctx, &fninfo,
4832 &num_prolog_vgprs);
4833 } else if (ctx->type == PIPE_SHADER_TESS_EVAL) {
4834 declare_tes_input_vgprs(ctx, &fninfo);
4835 }
4836
4837 if (ctx->type == PIPE_SHADER_VERTEX ||
4838 ctx->type == PIPE_SHADER_TESS_EVAL) {
4839 /* ES return values are inputs to GS. */
4840 for (i = 0; i < 8 + GFX9_GS_NUM_USER_SGPR; i++)
4841 returns[num_returns++] = ctx->i32; /* SGPRs */
4842 for (i = 0; i < 5; i++)
4843 returns[num_returns++] = ctx->f32; /* VGPRs */
4844 }
4845 break;
4846
4847 case PIPE_SHADER_TESS_EVAL:
4848 declare_global_desc_pointers(ctx, &fninfo);
4849 declare_per_stage_desc_pointers(ctx, &fninfo, true);
4850 ctx->param_tcs_offchip_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4851 ctx->param_tcs_offchip_addr_base64k = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4852
4853 if (shader->key.as_es) {
4854 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4855 add_arg(&fninfo, ARG_SGPR, ctx->i32);
4856 ctx->param_es2gs_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4857 } else {
4858 add_arg(&fninfo, ARG_SGPR, ctx->i32);
4859 declare_streamout_params(ctx, &shader->selector->so,
4860 &fninfo);
4861 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4862 }
4863
4864 /* VGPRs */
4865 declare_tes_input_vgprs(ctx, &fninfo);
4866 break;
4867
4868 case PIPE_SHADER_GEOMETRY:
4869 declare_global_desc_pointers(ctx, &fninfo);
4870 declare_per_stage_desc_pointers(ctx, &fninfo, true);
4871 ctx->param_gs2vs_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4872 ctx->param_gs_wave_id = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4873
4874 /* VGPRs */
4875 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->gs_vtx_offset[0]);
4876 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->gs_vtx_offset[1]);
4877 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->abi.gs_prim_id);
4878 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->gs_vtx_offset[2]);
4879 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->gs_vtx_offset[3]);
4880 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->gs_vtx_offset[4]);
4881 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->gs_vtx_offset[5]);
4882 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->abi.gs_invocation_id);
4883 break;
4884
4885 case PIPE_SHADER_FRAGMENT:
4886 declare_global_desc_pointers(ctx, &fninfo);
4887 declare_per_stage_desc_pointers(ctx, &fninfo, true);
4888 add_arg_checked(&fninfo, ARG_SGPR, ctx->f32, SI_PARAM_ALPHA_REF);
4889 add_arg_assign_checked(&fninfo, ARG_SGPR, ctx->i32,
4890 &ctx->abi.prim_mask, SI_PARAM_PRIM_MASK);
4891
4892 add_arg_checked(&fninfo, ARG_VGPR, ctx->v2i32, SI_PARAM_PERSP_SAMPLE);
4893 add_arg_checked(&fninfo, ARG_VGPR, ctx->v2i32, SI_PARAM_PERSP_CENTER);
4894 add_arg_checked(&fninfo, ARG_VGPR, ctx->v2i32, SI_PARAM_PERSP_CENTROID);
4895 add_arg_checked(&fninfo, ARG_VGPR, v3i32, SI_PARAM_PERSP_PULL_MODEL);
4896 add_arg_checked(&fninfo, ARG_VGPR, ctx->v2i32, SI_PARAM_LINEAR_SAMPLE);
4897 add_arg_checked(&fninfo, ARG_VGPR, ctx->v2i32, SI_PARAM_LINEAR_CENTER);
4898 add_arg_checked(&fninfo, ARG_VGPR, ctx->v2i32, SI_PARAM_LINEAR_CENTROID);
4899 add_arg_checked(&fninfo, ARG_VGPR, ctx->f32, SI_PARAM_LINE_STIPPLE_TEX);
4900 add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->f32,
4901 &ctx->abi.frag_pos[0], SI_PARAM_POS_X_FLOAT);
4902 add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->f32,
4903 &ctx->abi.frag_pos[1], SI_PARAM_POS_Y_FLOAT);
4904 add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->f32,
4905 &ctx->abi.frag_pos[2], SI_PARAM_POS_Z_FLOAT);
4906 add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->f32,
4907 &ctx->abi.frag_pos[3], SI_PARAM_POS_W_FLOAT);
4908 add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->i32,
4909 &ctx->abi.front_face, SI_PARAM_FRONT_FACE);
4910 shader->info.face_vgpr_index = 20;
4911 add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->i32,
4912 &ctx->abi.ancillary, SI_PARAM_ANCILLARY);
4913 shader->info.ancillary_vgpr_index = 21;
4914 add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->f32,
4915 &ctx->abi.sample_coverage, SI_PARAM_SAMPLE_COVERAGE);
4916 add_arg_checked(&fninfo, ARG_VGPR, ctx->i32, SI_PARAM_POS_FIXED_PT);
4917
4918 /* Color inputs from the prolog. */
4919 if (shader->selector->info.colors_read) {
4920 unsigned num_color_elements =
4921 util_bitcount(shader->selector->info.colors_read);
4922
4923 assert(fninfo.num_params + num_color_elements <= ARRAY_SIZE(fninfo.types));
4924 for (i = 0; i < num_color_elements; i++)
4925 add_arg(&fninfo, ARG_VGPR, ctx->f32);
4926
4927 num_prolog_vgprs += num_color_elements;
4928 }
4929
4930 /* Outputs for the epilog. */
4931 num_return_sgprs = SI_SGPR_ALPHA_REF + 1;
4932 num_returns =
4933 num_return_sgprs +
4934 util_bitcount(shader->selector->info.colors_written) * 4 +
4935 shader->selector->info.writes_z +
4936 shader->selector->info.writes_stencil +
4937 shader->selector->info.writes_samplemask +
4938 1 /* SampleMaskIn */;
4939
4940 num_returns = MAX2(num_returns,
4941 num_return_sgprs +
4942 PS_EPILOG_SAMPLEMASK_MIN_LOC + 1);
4943
4944 for (i = 0; i < num_return_sgprs; i++)
4945 returns[i] = ctx->i32;
4946 for (; i < num_returns; i++)
4947 returns[i] = ctx->f32;
4948 break;
4949
4950 case PIPE_SHADER_COMPUTE:
4951 declare_global_desc_pointers(ctx, &fninfo);
4952 declare_per_stage_desc_pointers(ctx, &fninfo, true);
4953 if (shader->selector->info.uses_grid_size)
4954 ctx->param_grid_size = add_arg(&fninfo, ARG_SGPR, v3i32);
4955 if (shader->selector->info.uses_block_size)
4956 ctx->param_block_size = add_arg(&fninfo, ARG_SGPR, v3i32);
4957
4958 for (i = 0; i < 3; i++) {
4959 ctx->param_block_id[i] = -1;
4960 if (shader->selector->info.uses_block_id[i])
4961 ctx->param_block_id[i] = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4962 }
4963
4964 ctx->param_thread_id = add_arg(&fninfo, ARG_VGPR, v3i32);
4965 break;
4966 default:
4967 assert(0 && "unimplemented shader");
4968 return;
4969 }
4970
4971 si_create_function(ctx, "main", returns, num_returns, &fninfo,
4972 si_get_max_workgroup_size(shader));
4973
4974 /* Reserve register locations for VGPR inputs the PS prolog may need. */
4975 if (ctx->type == PIPE_SHADER_FRAGMENT &&
4976 ctx->separate_prolog) {
4977 si_llvm_add_attribute(ctx->main_fn,
4978 "InitialPSInputAddr",
4979 S_0286D0_PERSP_SAMPLE_ENA(1) |
4980 S_0286D0_PERSP_CENTER_ENA(1) |
4981 S_0286D0_PERSP_CENTROID_ENA(1) |
4982 S_0286D0_LINEAR_SAMPLE_ENA(1) |
4983 S_0286D0_LINEAR_CENTER_ENA(1) |
4984 S_0286D0_LINEAR_CENTROID_ENA(1) |
4985 S_0286D0_FRONT_FACE_ENA(1) |
4986 S_0286D0_ANCILLARY_ENA(1) |
4987 S_0286D0_POS_FIXED_PT_ENA(1));
4988 }
4989
4990 shader->info.num_input_sgprs = 0;
4991 shader->info.num_input_vgprs = 0;
4992
4993 for (i = 0; i < fninfo.num_sgpr_params; ++i)
4994 shader->info.num_input_sgprs += ac_get_type_size(fninfo.types[i]) / 4;
4995
4996 for (; i < fninfo.num_params; ++i)
4997 shader->info.num_input_vgprs += ac_get_type_size(fninfo.types[i]) / 4;
4998
4999 assert(shader->info.num_input_vgprs >= num_prolog_vgprs);
5000 shader->info.num_input_vgprs -= num_prolog_vgprs;
5001
5002 if (shader->key.as_ls ||
5003 ctx->type == PIPE_SHADER_TESS_CTRL ||
5004 /* GFX9 has the ESGS ring buffer in LDS. */
5005 type == SI_SHADER_MERGED_VERTEX_OR_TESSEVAL_GEOMETRY)
5006 ac_declare_lds_as_pointer(&ctx->ac);
5007 }
5008
5009 /**
5010 * Load ESGS and GSVS ring buffer resource descriptors and save the variables
5011 * for later use.
5012 */
5013 static void preload_ring_buffers(struct si_shader_context *ctx)
5014 {
5015 LLVMBuilderRef builder = ctx->ac.builder;
5016
5017 LLVMValueRef buf_ptr = LLVMGetParam(ctx->main_fn,
5018 ctx->param_rw_buffers);
5019
5020 if (ctx->screen->info.chip_class <= VI &&
5021 (ctx->shader->key.as_es || ctx->type == PIPE_SHADER_GEOMETRY)) {
5022 unsigned ring =
5023 ctx->type == PIPE_SHADER_GEOMETRY ? SI_GS_RING_ESGS
5024 : SI_ES_RING_ESGS;
5025 LLVMValueRef offset = LLVMConstInt(ctx->i32, ring, 0);
5026
5027 ctx->esgs_ring =
5028 ac_build_load_to_sgpr(&ctx->ac, buf_ptr, offset);
5029 }
5030
5031 if (ctx->shader->is_gs_copy_shader) {
5032 LLVMValueRef offset = LLVMConstInt(ctx->i32, SI_RING_GSVS, 0);
5033
5034 ctx->gsvs_ring[0] =
5035 ac_build_load_to_sgpr(&ctx->ac, buf_ptr, offset);
5036 } else if (ctx->type == PIPE_SHADER_GEOMETRY) {
5037 const struct si_shader_selector *sel = ctx->shader->selector;
5038 LLVMValueRef offset = LLVMConstInt(ctx->i32, SI_RING_GSVS, 0);
5039 LLVMValueRef base_ring;
5040
5041 base_ring = ac_build_load_to_sgpr(&ctx->ac, buf_ptr, offset);
5042
5043 /* The conceptual layout of the GSVS ring is
5044 * v0c0 .. vLv0 v0c1 .. vLc1 ..
5045 * but the real memory layout is swizzled across
5046 * threads:
5047 * t0v0c0 .. t15v0c0 t0v1c0 .. t15v1c0 ... t15vLcL
5048 * t16v0c0 ..
5049 * Override the buffer descriptor accordingly.
5050 */
5051 LLVMTypeRef v2i64 = LLVMVectorType(ctx->i64, 2);
5052 uint64_t stream_offset = 0;
5053
5054 for (unsigned stream = 0; stream < 4; ++stream) {
5055 unsigned num_components;
5056 unsigned stride;
5057 unsigned num_records;
5058 LLVMValueRef ring, tmp;
5059
5060 num_components = sel->info.num_stream_output_components[stream];
5061 if (!num_components)
5062 continue;
5063
5064 stride = 4 * num_components * sel->gs_max_out_vertices;
5065
5066 /* Limit on the stride field for <= CIK. */
5067 assert(stride < (1 << 14));
5068
5069 num_records = 64;
5070
5071 ring = LLVMBuildBitCast(builder, base_ring, v2i64, "");
5072 tmp = LLVMBuildExtractElement(builder, ring, ctx->i32_0, "");
5073 tmp = LLVMBuildAdd(builder, tmp,
5074 LLVMConstInt(ctx->i64,
5075 stream_offset, 0), "");
5076 stream_offset += stride * 64;
5077
5078 ring = LLVMBuildInsertElement(builder, ring, tmp, ctx->i32_0, "");
5079 ring = LLVMBuildBitCast(builder, ring, ctx->v4i32, "");
5080 tmp = LLVMBuildExtractElement(builder, ring, ctx->i32_1, "");
5081 tmp = LLVMBuildOr(builder, tmp,
5082 LLVMConstInt(ctx->i32,
5083 S_008F04_STRIDE(stride) |
5084 S_008F04_SWIZZLE_ENABLE(1), 0), "");
5085 ring = LLVMBuildInsertElement(builder, ring, tmp, ctx->i32_1, "");
5086 ring = LLVMBuildInsertElement(builder, ring,
5087 LLVMConstInt(ctx->i32, num_records, 0),
5088 LLVMConstInt(ctx->i32, 2, 0), "");
5089 ring = LLVMBuildInsertElement(builder, ring,
5090 LLVMConstInt(ctx->i32,
5091 S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
5092 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
5093 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
5094 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
5095 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
5096 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
5097 S_008F0C_ELEMENT_SIZE(1) | /* element_size = 4 (bytes) */
5098 S_008F0C_INDEX_STRIDE(1) | /* index_stride = 16 (elements) */
5099 S_008F0C_ADD_TID_ENABLE(1),
5100 0),
5101 LLVMConstInt(ctx->i32, 3, 0), "");
5102
5103 ctx->gsvs_ring[stream] = ring;
5104 }
5105 }
5106 }
5107
5108 static void si_llvm_emit_polygon_stipple(struct si_shader_context *ctx,
5109 LLVMValueRef param_rw_buffers,
5110 unsigned param_pos_fixed_pt)
5111 {
5112 LLVMBuilderRef builder = ctx->ac.builder;
5113 LLVMValueRef slot, desc, offset, row, bit, address[2];
5114
5115 /* Use the fixed-point gl_FragCoord input.
5116 * Since the stipple pattern is 32x32 and it repeats, just get 5 bits
5117 * per coordinate to get the repeating effect.
5118 */
5119 address[0] = unpack_param(ctx, param_pos_fixed_pt, 0, 5);
5120 address[1] = unpack_param(ctx, param_pos_fixed_pt, 16, 5);
5121
5122 /* Load the buffer descriptor. */
5123 slot = LLVMConstInt(ctx->i32, SI_PS_CONST_POLY_STIPPLE, 0);
5124 desc = ac_build_load_to_sgpr(&ctx->ac, param_rw_buffers, slot);
5125
5126 /* The stipple pattern is 32x32, each row has 32 bits. */
5127 offset = LLVMBuildMul(builder, address[1],
5128 LLVMConstInt(ctx->i32, 4, 0), "");
5129 row = buffer_load_const(ctx, desc, offset);
5130 row = ac_to_integer(&ctx->ac, row);
5131 bit = LLVMBuildLShr(builder, row, address[0], "");
5132 bit = LLVMBuildTrunc(builder, bit, ctx->i1, "");
5133 ac_build_kill_if_false(&ctx->ac, bit);
5134 }
5135
5136 void si_shader_binary_read_config(struct ac_shader_binary *binary,
5137 struct si_shader_config *conf,
5138 unsigned symbol_offset)
5139 {
5140 unsigned i;
5141 const unsigned char *config =
5142 ac_shader_binary_config_start(binary, symbol_offset);
5143 bool really_needs_scratch = false;
5144
5145 /* LLVM adds SGPR spills to the scratch size.
5146 * Find out if we really need the scratch buffer.
5147 */
5148 for (i = 0; i < binary->reloc_count; i++) {
5149 const struct ac_shader_reloc *reloc = &binary->relocs[i];
5150
5151 if (!strcmp(scratch_rsrc_dword0_symbol, reloc->name) ||
5152 !strcmp(scratch_rsrc_dword1_symbol, reloc->name)) {
5153 really_needs_scratch = true;
5154 break;
5155 }
5156 }
5157
5158 /* XXX: We may be able to emit some of these values directly rather than
5159 * extracting fields to be emitted later.
5160 */
5161
5162 for (i = 0; i < binary->config_size_per_symbol; i+= 8) {
5163 unsigned reg = util_le32_to_cpu(*(uint32_t*)(config + i));
5164 unsigned value = util_le32_to_cpu(*(uint32_t*)(config + i + 4));
5165 switch (reg) {
5166 case R_00B028_SPI_SHADER_PGM_RSRC1_PS:
5167 case R_00B128_SPI_SHADER_PGM_RSRC1_VS:
5168 case R_00B228_SPI_SHADER_PGM_RSRC1_GS:
5169 case R_00B428_SPI_SHADER_PGM_RSRC1_HS:
5170 case R_00B848_COMPUTE_PGM_RSRC1:
5171 conf->num_sgprs = MAX2(conf->num_sgprs, (G_00B028_SGPRS(value) + 1) * 8);
5172 conf->num_vgprs = MAX2(conf->num_vgprs, (G_00B028_VGPRS(value) + 1) * 4);
5173 conf->float_mode = G_00B028_FLOAT_MODE(value);
5174 conf->rsrc1 = value;
5175 break;
5176 case R_00B02C_SPI_SHADER_PGM_RSRC2_PS:
5177 conf->lds_size = MAX2(conf->lds_size, G_00B02C_EXTRA_LDS_SIZE(value));
5178 break;
5179 case R_00B84C_COMPUTE_PGM_RSRC2:
5180 conf->lds_size = MAX2(conf->lds_size, G_00B84C_LDS_SIZE(value));
5181 conf->rsrc2 = value;
5182 break;
5183 case R_0286CC_SPI_PS_INPUT_ENA:
5184 conf->spi_ps_input_ena = value;
5185 break;
5186 case R_0286D0_SPI_PS_INPUT_ADDR:
5187 conf->spi_ps_input_addr = value;
5188 break;
5189 case R_0286E8_SPI_TMPRING_SIZE:
5190 case R_00B860_COMPUTE_TMPRING_SIZE:
5191 /* WAVESIZE is in units of 256 dwords. */
5192 if (really_needs_scratch)
5193 conf->scratch_bytes_per_wave =
5194 G_00B860_WAVESIZE(value) * 256 * 4;
5195 break;
5196 case 0x4: /* SPILLED_SGPRS */
5197 conf->spilled_sgprs = value;
5198 break;
5199 case 0x8: /* SPILLED_VGPRS */
5200 conf->spilled_vgprs = value;
5201 break;
5202 default:
5203 {
5204 static bool printed;
5205
5206 if (!printed) {
5207 fprintf(stderr, "Warning: LLVM emitted unknown "
5208 "config register: 0x%x\n", reg);
5209 printed = true;
5210 }
5211 }
5212 break;
5213 }
5214 }
5215
5216 if (!conf->spi_ps_input_addr)
5217 conf->spi_ps_input_addr = conf->spi_ps_input_ena;
5218 }
5219
5220 void si_shader_apply_scratch_relocs(struct si_shader *shader,
5221 uint64_t scratch_va)
5222 {
5223 unsigned i;
5224 uint32_t scratch_rsrc_dword0 = scratch_va;
5225 uint32_t scratch_rsrc_dword1 =
5226 S_008F04_BASE_ADDRESS_HI(scratch_va >> 32);
5227
5228 /* Enable scratch coalescing. */
5229 scratch_rsrc_dword1 |= S_008F04_SWIZZLE_ENABLE(1);
5230
5231 for (i = 0 ; i < shader->binary.reloc_count; i++) {
5232 const struct ac_shader_reloc *reloc =
5233 &shader->binary.relocs[i];
5234 if (!strcmp(scratch_rsrc_dword0_symbol, reloc->name)) {
5235 util_memcpy_cpu_to_le32(shader->binary.code + reloc->offset,
5236 &scratch_rsrc_dword0, 4);
5237 } else if (!strcmp(scratch_rsrc_dword1_symbol, reloc->name)) {
5238 util_memcpy_cpu_to_le32(shader->binary.code + reloc->offset,
5239 &scratch_rsrc_dword1, 4);
5240 }
5241 }
5242 }
5243
5244 static unsigned si_get_shader_binary_size(const struct si_shader *shader)
5245 {
5246 unsigned size = shader->binary.code_size;
5247
5248 if (shader->prolog)
5249 size += shader->prolog->binary.code_size;
5250 if (shader->previous_stage)
5251 size += shader->previous_stage->binary.code_size;
5252 if (shader->prolog2)
5253 size += shader->prolog2->binary.code_size;
5254 if (shader->epilog)
5255 size += shader->epilog->binary.code_size;
5256 return size;
5257 }
5258
5259 int si_shader_binary_upload(struct si_screen *sscreen, struct si_shader *shader)
5260 {
5261 const struct ac_shader_binary *prolog =
5262 shader->prolog ? &shader->prolog->binary : NULL;
5263 const struct ac_shader_binary *previous_stage =
5264 shader->previous_stage ? &shader->previous_stage->binary : NULL;
5265 const struct ac_shader_binary *prolog2 =
5266 shader->prolog2 ? &shader->prolog2->binary : NULL;
5267 const struct ac_shader_binary *epilog =
5268 shader->epilog ? &shader->epilog->binary : NULL;
5269 const struct ac_shader_binary *mainb = &shader->binary;
5270 unsigned bo_size = si_get_shader_binary_size(shader) +
5271 (!epilog ? mainb->rodata_size : 0);
5272 unsigned char *ptr;
5273
5274 assert(!prolog || !prolog->rodata_size);
5275 assert(!previous_stage || !previous_stage->rodata_size);
5276 assert(!prolog2 || !prolog2->rodata_size);
5277 assert((!prolog && !previous_stage && !prolog2 && !epilog) ||
5278 !mainb->rodata_size);
5279 assert(!epilog || !epilog->rodata_size);
5280
5281 r600_resource_reference(&shader->bo, NULL);
5282 shader->bo = (struct r600_resource*)
5283 si_aligned_buffer_create(&sscreen->b,
5284 sscreen->cpdma_prefetch_writes_memory ?
5285 0 : R600_RESOURCE_FLAG_READ_ONLY,
5286 PIPE_USAGE_IMMUTABLE,
5287 align(bo_size, SI_CPDMA_ALIGNMENT),
5288 256);
5289 if (!shader->bo)
5290 return -ENOMEM;
5291
5292 /* Upload. */
5293 ptr = sscreen->ws->buffer_map(shader->bo->buf, NULL,
5294 PIPE_TRANSFER_READ_WRITE |
5295 PIPE_TRANSFER_UNSYNCHRONIZED);
5296
5297 /* Don't use util_memcpy_cpu_to_le32. LLVM binaries are
5298 * endian-independent. */
5299 if (prolog) {
5300 memcpy(ptr, prolog->code, prolog->code_size);
5301 ptr += prolog->code_size;
5302 }
5303 if (previous_stage) {
5304 memcpy(ptr, previous_stage->code, previous_stage->code_size);
5305 ptr += previous_stage->code_size;
5306 }
5307 if (prolog2) {
5308 memcpy(ptr, prolog2->code, prolog2->code_size);
5309 ptr += prolog2->code_size;
5310 }
5311
5312 memcpy(ptr, mainb->code, mainb->code_size);
5313 ptr += mainb->code_size;
5314
5315 if (epilog)
5316 memcpy(ptr, epilog->code, epilog->code_size);
5317 else if (mainb->rodata_size > 0)
5318 memcpy(ptr, mainb->rodata, mainb->rodata_size);
5319
5320 sscreen->ws->buffer_unmap(shader->bo->buf);
5321 return 0;
5322 }
5323
5324 static void si_shader_dump_disassembly(const struct ac_shader_binary *binary,
5325 struct pipe_debug_callback *debug,
5326 const char *name, FILE *file)
5327 {
5328 char *line, *p;
5329 unsigned i, count;
5330
5331 if (binary->disasm_string) {
5332 fprintf(file, "Shader %s disassembly:\n", name);
5333 fprintf(file, "%s", binary->disasm_string);
5334
5335 if (debug && debug->debug_message) {
5336 /* Very long debug messages are cut off, so send the
5337 * disassembly one line at a time. This causes more
5338 * overhead, but on the plus side it simplifies
5339 * parsing of resulting logs.
5340 */
5341 pipe_debug_message(debug, SHADER_INFO,
5342 "Shader Disassembly Begin");
5343
5344 line = binary->disasm_string;
5345 while (*line) {
5346 p = util_strchrnul(line, '\n');
5347 count = p - line;
5348
5349 if (count) {
5350 pipe_debug_message(debug, SHADER_INFO,
5351 "%.*s", count, line);
5352 }
5353
5354 if (!*p)
5355 break;
5356 line = p + 1;
5357 }
5358
5359 pipe_debug_message(debug, SHADER_INFO,
5360 "Shader Disassembly End");
5361 }
5362 } else {
5363 fprintf(file, "Shader %s binary:\n", name);
5364 for (i = 0; i < binary->code_size; i += 4) {
5365 fprintf(file, "@0x%x: %02x%02x%02x%02x\n", i,
5366 binary->code[i + 3], binary->code[i + 2],
5367 binary->code[i + 1], binary->code[i]);
5368 }
5369 }
5370 }
5371
5372 static void si_calculate_max_simd_waves(struct si_shader *shader)
5373 {
5374 struct si_screen *sscreen = shader->selector->screen;
5375 struct si_shader_config *conf = &shader->config;
5376 unsigned num_inputs = shader->selector->info.num_inputs;
5377 unsigned lds_increment = sscreen->info.chip_class >= CIK ? 512 : 256;
5378 unsigned lds_per_wave = 0;
5379 unsigned max_simd_waves;
5380
5381 switch (sscreen->info.family) {
5382 /* These always have 8 waves: */
5383 case CHIP_POLARIS10:
5384 case CHIP_POLARIS11:
5385 case CHIP_POLARIS12:
5386 max_simd_waves = 8;
5387 break;
5388 default:
5389 max_simd_waves = 10;
5390 }
5391
5392 /* Compute LDS usage for PS. */
5393 switch (shader->selector->type) {
5394 case PIPE_SHADER_FRAGMENT:
5395 /* The minimum usage per wave is (num_inputs * 48). The maximum
5396 * usage is (num_inputs * 48 * 16).
5397 * We can get anything in between and it varies between waves.
5398 *
5399 * The 48 bytes per input for a single primitive is equal to
5400 * 4 bytes/component * 4 components/input * 3 points.
5401 *
5402 * Other stages don't know the size at compile time or don't
5403 * allocate LDS per wave, but instead they do it per thread group.
5404 */
5405 lds_per_wave = conf->lds_size * lds_increment +
5406 align(num_inputs * 48, lds_increment);
5407 break;
5408 case PIPE_SHADER_COMPUTE:
5409 if (shader->selector) {
5410 unsigned max_workgroup_size =
5411 si_get_max_workgroup_size(shader);
5412 lds_per_wave = (conf->lds_size * lds_increment) /
5413 DIV_ROUND_UP(max_workgroup_size, 64);
5414 }
5415 break;
5416 }
5417
5418 /* Compute the per-SIMD wave counts. */
5419 if (conf->num_sgprs) {
5420 if (sscreen->info.chip_class >= VI)
5421 max_simd_waves = MIN2(max_simd_waves, 800 / conf->num_sgprs);
5422 else
5423 max_simd_waves = MIN2(max_simd_waves, 512 / conf->num_sgprs);
5424 }
5425
5426 if (conf->num_vgprs)
5427 max_simd_waves = MIN2(max_simd_waves, 256 / conf->num_vgprs);
5428
5429 /* LDS is 64KB per CU (4 SIMDs), which is 16KB per SIMD (usage above
5430 * 16KB makes some SIMDs unoccupied). */
5431 if (lds_per_wave)
5432 max_simd_waves = MIN2(max_simd_waves, 16384 / lds_per_wave);
5433
5434 conf->max_simd_waves = max_simd_waves;
5435 }
5436
5437 void si_shader_dump_stats_for_shader_db(const struct si_shader *shader,
5438 struct pipe_debug_callback *debug)
5439 {
5440 const struct si_shader_config *conf = &shader->config;
5441
5442 pipe_debug_message(debug, SHADER_INFO,
5443 "Shader Stats: SGPRS: %d VGPRS: %d Code Size: %d "
5444 "LDS: %d Scratch: %d Max Waves: %d Spilled SGPRs: %d "
5445 "Spilled VGPRs: %d PrivMem VGPRs: %d",
5446 conf->num_sgprs, conf->num_vgprs,
5447 si_get_shader_binary_size(shader),
5448 conf->lds_size, conf->scratch_bytes_per_wave,
5449 conf->max_simd_waves, conf->spilled_sgprs,
5450 conf->spilled_vgprs, conf->private_mem_vgprs);
5451 }
5452
5453 static void si_shader_dump_stats(struct si_screen *sscreen,
5454 const struct si_shader *shader,
5455 unsigned processor,
5456 FILE *file,
5457 bool check_debug_option)
5458 {
5459 const struct si_shader_config *conf = &shader->config;
5460
5461 if (!check_debug_option ||
5462 si_can_dump_shader(sscreen, processor)) {
5463 if (processor == PIPE_SHADER_FRAGMENT) {
5464 fprintf(file, "*** SHADER CONFIG ***\n"
5465 "SPI_PS_INPUT_ADDR = 0x%04x\n"
5466 "SPI_PS_INPUT_ENA = 0x%04x\n",
5467 conf->spi_ps_input_addr, conf->spi_ps_input_ena);
5468 }
5469
5470 fprintf(file, "*** SHADER STATS ***\n"
5471 "SGPRS: %d\n"
5472 "VGPRS: %d\n"
5473 "Spilled SGPRs: %d\n"
5474 "Spilled VGPRs: %d\n"
5475 "Private memory VGPRs: %d\n"
5476 "Code Size: %d bytes\n"
5477 "LDS: %d blocks\n"
5478 "Scratch: %d bytes per wave\n"
5479 "Max Waves: %d\n"
5480 "********************\n\n\n",
5481 conf->num_sgprs, conf->num_vgprs,
5482 conf->spilled_sgprs, conf->spilled_vgprs,
5483 conf->private_mem_vgprs,
5484 si_get_shader_binary_size(shader),
5485 conf->lds_size, conf->scratch_bytes_per_wave,
5486 conf->max_simd_waves);
5487 }
5488 }
5489
5490 const char *si_get_shader_name(const struct si_shader *shader, unsigned processor)
5491 {
5492 switch (processor) {
5493 case PIPE_SHADER_VERTEX:
5494 if (shader->key.as_es)
5495 return "Vertex Shader as ES";
5496 else if (shader->key.as_ls)
5497 return "Vertex Shader as LS";
5498 else
5499 return "Vertex Shader as VS";
5500 case PIPE_SHADER_TESS_CTRL:
5501 return "Tessellation Control Shader";
5502 case PIPE_SHADER_TESS_EVAL:
5503 if (shader->key.as_es)
5504 return "Tessellation Evaluation Shader as ES";
5505 else
5506 return "Tessellation Evaluation Shader as VS";
5507 case PIPE_SHADER_GEOMETRY:
5508 if (shader->is_gs_copy_shader)
5509 return "GS Copy Shader as VS";
5510 else
5511 return "Geometry Shader";
5512 case PIPE_SHADER_FRAGMENT:
5513 return "Pixel Shader";
5514 case PIPE_SHADER_COMPUTE:
5515 return "Compute Shader";
5516 default:
5517 return "Unknown Shader";
5518 }
5519 }
5520
5521 void si_shader_dump(struct si_screen *sscreen, const struct si_shader *shader,
5522 struct pipe_debug_callback *debug, unsigned processor,
5523 FILE *file, bool check_debug_option)
5524 {
5525 if (!check_debug_option ||
5526 si_can_dump_shader(sscreen, processor))
5527 si_dump_shader_key(processor, shader, file);
5528
5529 if (!check_debug_option && shader->binary.llvm_ir_string) {
5530 if (shader->previous_stage &&
5531 shader->previous_stage->binary.llvm_ir_string) {
5532 fprintf(file, "\n%s - previous stage - LLVM IR:\n\n",
5533 si_get_shader_name(shader, processor));
5534 fprintf(file, "%s\n", shader->previous_stage->binary.llvm_ir_string);
5535 }
5536
5537 fprintf(file, "\n%s - main shader part - LLVM IR:\n\n",
5538 si_get_shader_name(shader, processor));
5539 fprintf(file, "%s\n", shader->binary.llvm_ir_string);
5540 }
5541
5542 if (!check_debug_option ||
5543 (si_can_dump_shader(sscreen, processor) &&
5544 !(sscreen->debug_flags & DBG(NO_ASM)))) {
5545 fprintf(file, "\n%s:\n", si_get_shader_name(shader, processor));
5546
5547 if (shader->prolog)
5548 si_shader_dump_disassembly(&shader->prolog->binary,
5549 debug, "prolog", file);
5550 if (shader->previous_stage)
5551 si_shader_dump_disassembly(&shader->previous_stage->binary,
5552 debug, "previous stage", file);
5553 if (shader->prolog2)
5554 si_shader_dump_disassembly(&shader->prolog2->binary,
5555 debug, "prolog2", file);
5556
5557 si_shader_dump_disassembly(&shader->binary, debug, "main", file);
5558
5559 if (shader->epilog)
5560 si_shader_dump_disassembly(&shader->epilog->binary,
5561 debug, "epilog", file);
5562 fprintf(file, "\n");
5563 }
5564
5565 si_shader_dump_stats(sscreen, shader, processor, file,
5566 check_debug_option);
5567 }
5568
5569 static int si_compile_llvm(struct si_screen *sscreen,
5570 struct ac_shader_binary *binary,
5571 struct si_shader_config *conf,
5572 LLVMTargetMachineRef tm,
5573 LLVMModuleRef mod,
5574 struct pipe_debug_callback *debug,
5575 unsigned processor,
5576 const char *name)
5577 {
5578 int r = 0;
5579 unsigned count = p_atomic_inc_return(&sscreen->num_compilations);
5580
5581 if (si_can_dump_shader(sscreen, processor)) {
5582 fprintf(stderr, "radeonsi: Compiling shader %d\n", count);
5583
5584 if (!(sscreen->debug_flags & (DBG(NO_IR) | DBG(PREOPT_IR)))) {
5585 fprintf(stderr, "%s LLVM IR:\n\n", name);
5586 ac_dump_module(mod);
5587 fprintf(stderr, "\n");
5588 }
5589 }
5590
5591 if (sscreen->record_llvm_ir) {
5592 char *ir = LLVMPrintModuleToString(mod);
5593 binary->llvm_ir_string = strdup(ir);
5594 LLVMDisposeMessage(ir);
5595 }
5596
5597 if (!si_replace_shader(count, binary)) {
5598 r = si_llvm_compile(mod, binary, tm, debug);
5599 if (r)
5600 return r;
5601 }
5602
5603 si_shader_binary_read_config(binary, conf, 0);
5604
5605 /* Enable 64-bit and 16-bit denormals, because there is no performance
5606 * cost.
5607 *
5608 * If denormals are enabled, all floating-point output modifiers are
5609 * ignored.
5610 *
5611 * Don't enable denormals for 32-bit floats, because:
5612 * - Floating-point output modifiers would be ignored by the hw.
5613 * - Some opcodes don't support denormals, such as v_mad_f32. We would
5614 * have to stop using those.
5615 * - SI & CI would be very slow.
5616 */
5617 conf->float_mode |= V_00B028_FP_64_DENORMS;
5618
5619 FREE(binary->config);
5620 FREE(binary->global_symbol_offsets);
5621 binary->config = NULL;
5622 binary->global_symbol_offsets = NULL;
5623
5624 /* Some shaders can't have rodata because their binaries can be
5625 * concatenated.
5626 */
5627 if (binary->rodata_size &&
5628 (processor == PIPE_SHADER_VERTEX ||
5629 processor == PIPE_SHADER_TESS_CTRL ||
5630 processor == PIPE_SHADER_TESS_EVAL ||
5631 processor == PIPE_SHADER_FRAGMENT)) {
5632 fprintf(stderr, "radeonsi: The shader can't have rodata.");
5633 return -EINVAL;
5634 }
5635
5636 return r;
5637 }
5638
5639 static void si_llvm_build_ret(struct si_shader_context *ctx, LLVMValueRef ret)
5640 {
5641 if (LLVMGetTypeKind(LLVMTypeOf(ret)) == LLVMVoidTypeKind)
5642 LLVMBuildRetVoid(ctx->ac.builder);
5643 else
5644 LLVMBuildRet(ctx->ac.builder, ret);
5645 }
5646
5647 /* Generate code for the hardware VS shader stage to go with a geometry shader */
5648 struct si_shader *
5649 si_generate_gs_copy_shader(struct si_screen *sscreen,
5650 LLVMTargetMachineRef tm,
5651 struct si_shader_selector *gs_selector,
5652 struct pipe_debug_callback *debug)
5653 {
5654 struct si_shader_context ctx;
5655 struct si_shader *shader;
5656 LLVMBuilderRef builder;
5657 struct lp_build_tgsi_context *bld_base = &ctx.bld_base;
5658 struct lp_build_context *uint = &bld_base->uint_bld;
5659 struct si_shader_output_values *outputs;
5660 struct tgsi_shader_info *gsinfo = &gs_selector->info;
5661 int i, r;
5662
5663 outputs = MALLOC(gsinfo->num_outputs * sizeof(outputs[0]));
5664
5665 if (!outputs)
5666 return NULL;
5667
5668 shader = CALLOC_STRUCT(si_shader);
5669 if (!shader) {
5670 FREE(outputs);
5671 return NULL;
5672 }
5673
5674 /* We can leave the fence as permanently signaled because the GS copy
5675 * shader only becomes visible globally after it has been compiled. */
5676 util_queue_fence_init(&shader->ready);
5677
5678 shader->selector = gs_selector;
5679 shader->is_gs_copy_shader = true;
5680
5681 si_init_shader_ctx(&ctx, sscreen, tm);
5682 ctx.shader = shader;
5683 ctx.type = PIPE_SHADER_VERTEX;
5684
5685 builder = ctx.ac.builder;
5686
5687 create_function(&ctx);
5688 preload_ring_buffers(&ctx);
5689
5690 LLVMValueRef voffset =
5691 lp_build_mul_imm(uint, ctx.abi.vertex_id, 4);
5692
5693 /* Fetch the vertex stream ID.*/
5694 LLVMValueRef stream_id;
5695
5696 if (gs_selector->so.num_outputs)
5697 stream_id = unpack_param(&ctx, ctx.param_streamout_config, 24, 2);
5698 else
5699 stream_id = ctx.i32_0;
5700
5701 /* Fill in output information. */
5702 for (i = 0; i < gsinfo->num_outputs; ++i) {
5703 outputs[i].semantic_name = gsinfo->output_semantic_name[i];
5704 outputs[i].semantic_index = gsinfo->output_semantic_index[i];
5705
5706 for (int chan = 0; chan < 4; chan++) {
5707 outputs[i].vertex_stream[chan] =
5708 (gsinfo->output_streams[i] >> (2 * chan)) & 3;
5709 }
5710 }
5711
5712 LLVMBasicBlockRef end_bb;
5713 LLVMValueRef switch_inst;
5714
5715 end_bb = LLVMAppendBasicBlockInContext(ctx.ac.context, ctx.main_fn, "end");
5716 switch_inst = LLVMBuildSwitch(builder, stream_id, end_bb, 4);
5717
5718 for (int stream = 0; stream < 4; stream++) {
5719 LLVMBasicBlockRef bb;
5720 unsigned offset;
5721
5722 if (!gsinfo->num_stream_output_components[stream])
5723 continue;
5724
5725 if (stream > 0 && !gs_selector->so.num_outputs)
5726 continue;
5727
5728 bb = LLVMInsertBasicBlockInContext(ctx.ac.context, end_bb, "out");
5729 LLVMAddCase(switch_inst, LLVMConstInt(ctx.i32, stream, 0), bb);
5730 LLVMPositionBuilderAtEnd(builder, bb);
5731
5732 /* Fetch vertex data from GSVS ring */
5733 offset = 0;
5734 for (i = 0; i < gsinfo->num_outputs; ++i) {
5735 for (unsigned chan = 0; chan < 4; chan++) {
5736 if (!(gsinfo->output_usagemask[i] & (1 << chan)) ||
5737 outputs[i].vertex_stream[chan] != stream) {
5738 outputs[i].values[chan] = ctx.bld_base.base.undef;
5739 continue;
5740 }
5741
5742 LLVMValueRef soffset = LLVMConstInt(ctx.i32,
5743 offset * gs_selector->gs_max_out_vertices * 16 * 4, 0);
5744 offset++;
5745
5746 outputs[i].values[chan] =
5747 ac_build_buffer_load(&ctx.ac,
5748 ctx.gsvs_ring[0], 1,
5749 ctx.i32_0, voffset,
5750 soffset, 0, 1, 1,
5751 true, false);
5752 }
5753 }
5754
5755 /* Streamout and exports. */
5756 if (gs_selector->so.num_outputs) {
5757 si_llvm_emit_streamout(&ctx, outputs,
5758 gsinfo->num_outputs,
5759 stream);
5760 }
5761
5762 if (stream == 0)
5763 si_llvm_export_vs(&ctx, outputs, gsinfo->num_outputs);
5764
5765 LLVMBuildBr(builder, end_bb);
5766 }
5767
5768 LLVMPositionBuilderAtEnd(builder, end_bb);
5769
5770 LLVMBuildRetVoid(ctx.ac.builder);
5771
5772 ctx.type = PIPE_SHADER_GEOMETRY; /* override for shader dumping */
5773 si_llvm_optimize_module(&ctx);
5774
5775 r = si_compile_llvm(sscreen, &ctx.shader->binary,
5776 &ctx.shader->config, ctx.tm,
5777 ctx.gallivm.module,
5778 debug, PIPE_SHADER_GEOMETRY,
5779 "GS Copy Shader");
5780 if (!r) {
5781 if (si_can_dump_shader(sscreen, PIPE_SHADER_GEOMETRY))
5782 fprintf(stderr, "GS Copy Shader:\n");
5783 si_shader_dump(sscreen, ctx.shader, debug,
5784 PIPE_SHADER_GEOMETRY, stderr, true);
5785 r = si_shader_binary_upload(sscreen, ctx.shader);
5786 }
5787
5788 si_llvm_dispose(&ctx);
5789
5790 FREE(outputs);
5791
5792 if (r != 0) {
5793 FREE(shader);
5794 shader = NULL;
5795 }
5796 return shader;
5797 }
5798
5799 static void si_dump_shader_key_vs(const struct si_shader_key *key,
5800 const struct si_vs_prolog_bits *prolog,
5801 const char *prefix, FILE *f)
5802 {
5803 fprintf(f, " %s.instance_divisor_is_one = %u\n",
5804 prefix, prolog->instance_divisor_is_one);
5805 fprintf(f, " %s.instance_divisor_is_fetched = %u\n",
5806 prefix, prolog->instance_divisor_is_fetched);
5807 fprintf(f, " %s.ls_vgpr_fix = %u\n",
5808 prefix, prolog->ls_vgpr_fix);
5809
5810 fprintf(f, " mono.vs.fix_fetch = {");
5811 for (int i = 0; i < SI_MAX_ATTRIBS; i++)
5812 fprintf(f, !i ? "%u" : ", %u", key->mono.vs_fix_fetch[i]);
5813 fprintf(f, "}\n");
5814 }
5815
5816 static void si_dump_shader_key(unsigned processor, const struct si_shader *shader,
5817 FILE *f)
5818 {
5819 const struct si_shader_key *key = &shader->key;
5820
5821 fprintf(f, "SHADER KEY\n");
5822
5823 switch (processor) {
5824 case PIPE_SHADER_VERTEX:
5825 si_dump_shader_key_vs(key, &key->part.vs.prolog,
5826 "part.vs.prolog", f);
5827 fprintf(f, " as_es = %u\n", key->as_es);
5828 fprintf(f, " as_ls = %u\n", key->as_ls);
5829 fprintf(f, " mono.u.vs_export_prim_id = %u\n",
5830 key->mono.u.vs_export_prim_id);
5831 break;
5832
5833 case PIPE_SHADER_TESS_CTRL:
5834 if (shader->selector->screen->info.chip_class >= GFX9) {
5835 si_dump_shader_key_vs(key, &key->part.tcs.ls_prolog,
5836 "part.tcs.ls_prolog", f);
5837 }
5838 fprintf(f, " part.tcs.epilog.prim_mode = %u\n", key->part.tcs.epilog.prim_mode);
5839 fprintf(f, " mono.u.ff_tcs_inputs_to_copy = 0x%"PRIx64"\n", key->mono.u.ff_tcs_inputs_to_copy);
5840 break;
5841
5842 case PIPE_SHADER_TESS_EVAL:
5843 fprintf(f, " as_es = %u\n", key->as_es);
5844 fprintf(f, " mono.u.vs_export_prim_id = %u\n",
5845 key->mono.u.vs_export_prim_id);
5846 break;
5847
5848 case PIPE_SHADER_GEOMETRY:
5849 if (shader->is_gs_copy_shader)
5850 break;
5851
5852 if (shader->selector->screen->info.chip_class >= GFX9 &&
5853 key->part.gs.es->type == PIPE_SHADER_VERTEX) {
5854 si_dump_shader_key_vs(key, &key->part.gs.vs_prolog,
5855 "part.gs.vs_prolog", f);
5856 }
5857 fprintf(f, " part.gs.prolog.tri_strip_adj_fix = %u\n", key->part.gs.prolog.tri_strip_adj_fix);
5858 break;
5859
5860 case PIPE_SHADER_COMPUTE:
5861 break;
5862
5863 case PIPE_SHADER_FRAGMENT:
5864 fprintf(f, " part.ps.prolog.color_two_side = %u\n", key->part.ps.prolog.color_two_side);
5865 fprintf(f, " part.ps.prolog.flatshade_colors = %u\n", key->part.ps.prolog.flatshade_colors);
5866 fprintf(f, " part.ps.prolog.poly_stipple = %u\n", key->part.ps.prolog.poly_stipple);
5867 fprintf(f, " part.ps.prolog.force_persp_sample_interp = %u\n", key->part.ps.prolog.force_persp_sample_interp);
5868 fprintf(f, " part.ps.prolog.force_linear_sample_interp = %u\n", key->part.ps.prolog.force_linear_sample_interp);
5869 fprintf(f, " part.ps.prolog.force_persp_center_interp = %u\n", key->part.ps.prolog.force_persp_center_interp);
5870 fprintf(f, " part.ps.prolog.force_linear_center_interp = %u\n", key->part.ps.prolog.force_linear_center_interp);
5871 fprintf(f, " part.ps.prolog.bc_optimize_for_persp = %u\n", key->part.ps.prolog.bc_optimize_for_persp);
5872 fprintf(f, " part.ps.prolog.bc_optimize_for_linear = %u\n", key->part.ps.prolog.bc_optimize_for_linear);
5873 fprintf(f, " part.ps.epilog.spi_shader_col_format = 0x%x\n", key->part.ps.epilog.spi_shader_col_format);
5874 fprintf(f, " part.ps.epilog.color_is_int8 = 0x%X\n", key->part.ps.epilog.color_is_int8);
5875 fprintf(f, " part.ps.epilog.color_is_int10 = 0x%X\n", key->part.ps.epilog.color_is_int10);
5876 fprintf(f, " part.ps.epilog.last_cbuf = %u\n", key->part.ps.epilog.last_cbuf);
5877 fprintf(f, " part.ps.epilog.alpha_func = %u\n", key->part.ps.epilog.alpha_func);
5878 fprintf(f, " part.ps.epilog.alpha_to_one = %u\n", key->part.ps.epilog.alpha_to_one);
5879 fprintf(f, " part.ps.epilog.poly_line_smoothing = %u\n", key->part.ps.epilog.poly_line_smoothing);
5880 fprintf(f, " part.ps.epilog.clamp_color = %u\n", key->part.ps.epilog.clamp_color);
5881 break;
5882
5883 default:
5884 assert(0);
5885 }
5886
5887 if ((processor == PIPE_SHADER_GEOMETRY ||
5888 processor == PIPE_SHADER_TESS_EVAL ||
5889 processor == PIPE_SHADER_VERTEX) &&
5890 !key->as_es && !key->as_ls) {
5891 fprintf(f, " opt.kill_outputs = 0x%"PRIx64"\n", key->opt.kill_outputs);
5892 fprintf(f, " opt.clip_disable = %u\n", key->opt.clip_disable);
5893 }
5894 }
5895
5896 static void si_init_shader_ctx(struct si_shader_context *ctx,
5897 struct si_screen *sscreen,
5898 LLVMTargetMachineRef tm)
5899 {
5900 struct lp_build_tgsi_context *bld_base;
5901
5902 si_llvm_context_init(ctx, sscreen, tm);
5903
5904 bld_base = &ctx->bld_base;
5905 bld_base->emit_fetch_funcs[TGSI_FILE_CONSTANT] = fetch_constant;
5906
5907 bld_base->op_actions[TGSI_OPCODE_INTERP_CENTROID] = interp_action;
5908 bld_base->op_actions[TGSI_OPCODE_INTERP_SAMPLE] = interp_action;
5909 bld_base->op_actions[TGSI_OPCODE_INTERP_OFFSET] = interp_action;
5910
5911 bld_base->op_actions[TGSI_OPCODE_MEMBAR].emit = membar_emit;
5912
5913 bld_base->op_actions[TGSI_OPCODE_CLOCK].emit = clock_emit;
5914
5915 bld_base->op_actions[TGSI_OPCODE_DDX].emit = si_llvm_emit_ddxy;
5916 bld_base->op_actions[TGSI_OPCODE_DDY].emit = si_llvm_emit_ddxy;
5917 bld_base->op_actions[TGSI_OPCODE_DDX_FINE].emit = si_llvm_emit_ddxy;
5918 bld_base->op_actions[TGSI_OPCODE_DDY_FINE].emit = si_llvm_emit_ddxy;
5919
5920 bld_base->op_actions[TGSI_OPCODE_VOTE_ALL].emit = vote_all_emit;
5921 bld_base->op_actions[TGSI_OPCODE_VOTE_ANY].emit = vote_any_emit;
5922 bld_base->op_actions[TGSI_OPCODE_VOTE_EQ].emit = vote_eq_emit;
5923 bld_base->op_actions[TGSI_OPCODE_BALLOT].emit = ballot_emit;
5924 bld_base->op_actions[TGSI_OPCODE_READ_FIRST].intr_name = "llvm.amdgcn.readfirstlane";
5925 bld_base->op_actions[TGSI_OPCODE_READ_FIRST].emit = read_lane_emit;
5926 bld_base->op_actions[TGSI_OPCODE_READ_INVOC].intr_name = "llvm.amdgcn.readlane";
5927 bld_base->op_actions[TGSI_OPCODE_READ_INVOC].fetch_args = read_invoc_fetch_args;
5928 bld_base->op_actions[TGSI_OPCODE_READ_INVOC].emit = read_lane_emit;
5929
5930 bld_base->op_actions[TGSI_OPCODE_EMIT].emit = si_tgsi_emit_vertex;
5931 bld_base->op_actions[TGSI_OPCODE_ENDPRIM].emit = si_tgsi_emit_primitive;
5932 bld_base->op_actions[TGSI_OPCODE_BARRIER].emit = si_llvm_emit_barrier;
5933 }
5934
5935 static void si_optimize_vs_outputs(struct si_shader_context *ctx)
5936 {
5937 struct si_shader *shader = ctx->shader;
5938 struct tgsi_shader_info *info = &shader->selector->info;
5939
5940 if ((ctx->type != PIPE_SHADER_VERTEX &&
5941 ctx->type != PIPE_SHADER_TESS_EVAL) ||
5942 shader->key.as_ls ||
5943 shader->key.as_es)
5944 return;
5945
5946 ac_optimize_vs_outputs(&ctx->ac,
5947 ctx->main_fn,
5948 shader->info.vs_output_param_offset,
5949 info->num_outputs,
5950 &shader->info.nr_param_exports);
5951 }
5952
5953 static void si_count_scratch_private_memory(struct si_shader_context *ctx)
5954 {
5955 ctx->shader->config.private_mem_vgprs = 0;
5956
5957 /* Process all LLVM instructions. */
5958 LLVMBasicBlockRef bb = LLVMGetFirstBasicBlock(ctx->main_fn);
5959 while (bb) {
5960 LLVMValueRef next = LLVMGetFirstInstruction(bb);
5961
5962 while (next) {
5963 LLVMValueRef inst = next;
5964 next = LLVMGetNextInstruction(next);
5965
5966 if (LLVMGetInstructionOpcode(inst) != LLVMAlloca)
5967 continue;
5968
5969 LLVMTypeRef type = LLVMGetElementType(LLVMTypeOf(inst));
5970 /* No idea why LLVM aligns allocas to 4 elements. */
5971 unsigned alignment = LLVMGetAlignment(inst);
5972 unsigned dw_size = align(ac_get_type_size(type) / 4, alignment);
5973 ctx->shader->config.private_mem_vgprs += dw_size;
5974 }
5975 bb = LLVMGetNextBasicBlock(bb);
5976 }
5977 }
5978
5979 static void si_init_exec_from_input(struct si_shader_context *ctx,
5980 unsigned param, unsigned bitoffset)
5981 {
5982 LLVMValueRef args[] = {
5983 LLVMGetParam(ctx->main_fn, param),
5984 LLVMConstInt(ctx->i32, bitoffset, 0),
5985 };
5986 lp_build_intrinsic(ctx->ac.builder,
5987 "llvm.amdgcn.init.exec.from.input",
5988 ctx->voidt, args, 2, LP_FUNC_ATTR_CONVERGENT);
5989 }
5990
5991 static bool si_vs_needs_prolog(const struct si_shader_selector *sel,
5992 const struct si_vs_prolog_bits *key)
5993 {
5994 /* VGPR initialization fixup for Vega10 and Raven is always done in the
5995 * VS prolog. */
5996 return sel->vs_needs_prolog || key->ls_vgpr_fix;
5997 }
5998
5999 static bool si_compile_tgsi_main(struct si_shader_context *ctx,
6000 bool is_monolithic)
6001 {
6002 struct si_shader *shader = ctx->shader;
6003 struct si_shader_selector *sel = shader->selector;
6004 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
6005
6006 // TODO clean all this up!
6007 switch (ctx->type) {
6008 case PIPE_SHADER_VERTEX:
6009 ctx->load_input = declare_input_vs;
6010 if (shader->key.as_ls)
6011 ctx->abi.emit_outputs = si_llvm_emit_ls_epilogue;
6012 else if (shader->key.as_es)
6013 ctx->abi.emit_outputs = si_llvm_emit_es_epilogue;
6014 else
6015 ctx->abi.emit_outputs = si_llvm_emit_vs_epilogue;
6016 bld_base->emit_epilogue = si_tgsi_emit_epilogue;
6017 break;
6018 case PIPE_SHADER_TESS_CTRL:
6019 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_tcs;
6020 ctx->abi.load_tess_varyings = si_nir_load_tcs_varyings;
6021 bld_base->emit_fetch_funcs[TGSI_FILE_OUTPUT] = fetch_output_tcs;
6022 bld_base->emit_store = store_output_tcs;
6023 ctx->abi.store_tcs_outputs = si_nir_store_output_tcs;
6024 ctx->abi.emit_outputs = si_llvm_emit_tcs_epilogue;
6025 ctx->abi.load_patch_vertices_in = si_load_patch_vertices_in;
6026 bld_base->emit_epilogue = si_tgsi_emit_epilogue;
6027 break;
6028 case PIPE_SHADER_TESS_EVAL:
6029 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_tes;
6030 ctx->abi.load_tess_varyings = si_nir_load_input_tes;
6031 ctx->abi.load_tess_coord = si_load_tess_coord;
6032 ctx->abi.load_tess_level = si_load_tess_level;
6033 ctx->abi.load_patch_vertices_in = si_load_patch_vertices_in;
6034 if (shader->key.as_es)
6035 ctx->abi.emit_outputs = si_llvm_emit_es_epilogue;
6036 else
6037 ctx->abi.emit_outputs = si_llvm_emit_vs_epilogue;
6038 bld_base->emit_epilogue = si_tgsi_emit_epilogue;
6039 break;
6040 case PIPE_SHADER_GEOMETRY:
6041 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_gs;
6042 ctx->abi.load_inputs = si_nir_load_input_gs;
6043 ctx->abi.emit_vertex = si_llvm_emit_vertex;
6044 ctx->abi.emit_primitive = si_llvm_emit_primitive;
6045 ctx->abi.emit_outputs = si_llvm_emit_gs_epilogue;
6046 bld_base->emit_epilogue = si_tgsi_emit_gs_epilogue;
6047 break;
6048 case PIPE_SHADER_FRAGMENT:
6049 ctx->load_input = declare_input_fs;
6050 ctx->abi.emit_outputs = si_llvm_return_fs_outputs;
6051 bld_base->emit_epilogue = si_tgsi_emit_epilogue;
6052 ctx->abi.lookup_interp_param = si_nir_lookup_interp_param;
6053 ctx->abi.load_sample_position = load_sample_position;
6054 break;
6055 case PIPE_SHADER_COMPUTE:
6056 break;
6057 default:
6058 assert(!"Unsupported shader type");
6059 return false;
6060 }
6061
6062 ctx->abi.load_ubo = load_ubo;
6063 ctx->abi.load_ssbo = load_ssbo;
6064
6065 create_function(ctx);
6066 preload_ring_buffers(ctx);
6067
6068 /* For GFX9 merged shaders:
6069 * - Set EXEC for the first shader. If the prolog is present, set
6070 * EXEC there instead.
6071 * - Add a barrier before the second shader.
6072 * - In the second shader, reset EXEC to ~0 and wrap the main part in
6073 * an if-statement. This is required for correctness in geometry
6074 * shaders, to ensure that empty GS waves do not send GS_EMIT and
6075 * GS_CUT messages.
6076 *
6077 * For monolithic merged shaders, the first shader is wrapped in an
6078 * if-block together with its prolog in si_build_wrapper_function.
6079 */
6080 if (ctx->screen->info.chip_class >= GFX9) {
6081 if (!is_monolithic &&
6082 sel->info.num_instructions > 1 && /* not empty shader */
6083 (shader->key.as_es || shader->key.as_ls) &&
6084 (ctx->type == PIPE_SHADER_TESS_EVAL ||
6085 (ctx->type == PIPE_SHADER_VERTEX &&
6086 !si_vs_needs_prolog(sel, &shader->key.part.vs.prolog)))) {
6087 si_init_exec_from_input(ctx,
6088 ctx->param_merged_wave_info, 0);
6089 } else if (ctx->type == PIPE_SHADER_TESS_CTRL ||
6090 ctx->type == PIPE_SHADER_GEOMETRY) {
6091 if (!is_monolithic)
6092 ac_init_exec_full_mask(&ctx->ac);
6093
6094 /* The barrier must execute for all shaders in a
6095 * threadgroup.
6096 */
6097 si_llvm_emit_barrier(NULL, bld_base, NULL);
6098
6099 LLVMValueRef num_threads = unpack_param(ctx, ctx->param_merged_wave_info, 8, 8);
6100 LLVMValueRef ena =
6101 LLVMBuildICmp(ctx->ac.builder, LLVMIntULT,
6102 ac_get_thread_id(&ctx->ac), num_threads, "");
6103 lp_build_if(&ctx->merged_wrap_if_state, &ctx->gallivm, ena);
6104 }
6105 }
6106
6107 if (ctx->type == PIPE_SHADER_TESS_CTRL &&
6108 sel->tcs_info.tessfactors_are_def_in_all_invocs) {
6109 for (unsigned i = 0; i < 6; i++) {
6110 ctx->invoc0_tess_factors[i] =
6111 lp_build_alloca_undef(&ctx->gallivm, ctx->i32, "");
6112 }
6113 }
6114
6115 if (ctx->type == PIPE_SHADER_GEOMETRY) {
6116 int i;
6117 for (i = 0; i < 4; i++) {
6118 ctx->gs_next_vertex[i] =
6119 lp_build_alloca(&ctx->gallivm,
6120 ctx->i32, "");
6121 }
6122 }
6123
6124 if (sel->force_correct_derivs_after_kill) {
6125 ctx->postponed_kill = lp_build_alloca_undef(&ctx->gallivm, ctx->i1, "");
6126 /* true = don't kill. */
6127 LLVMBuildStore(ctx->ac.builder, LLVMConstInt(ctx->i1, 1, 0),
6128 ctx->postponed_kill);
6129 }
6130
6131 if (sel->tokens) {
6132 if (!lp_build_tgsi_llvm(bld_base, sel->tokens)) {
6133 fprintf(stderr, "Failed to translate shader from TGSI to LLVM\n");
6134 return false;
6135 }
6136 } else {
6137 if (!si_nir_build_llvm(ctx, sel->nir)) {
6138 fprintf(stderr, "Failed to translate shader from NIR to LLVM\n");
6139 return false;
6140 }
6141 }
6142
6143 si_llvm_build_ret(ctx, ctx->return_value);
6144 return true;
6145 }
6146
6147 /**
6148 * Compute the VS prolog key, which contains all the information needed to
6149 * build the VS prolog function, and set shader->info bits where needed.
6150 *
6151 * \param info Shader info of the vertex shader.
6152 * \param num_input_sgprs Number of input SGPRs for the vertex shader.
6153 * \param prolog_key Key of the VS prolog
6154 * \param shader_out The vertex shader, or the next shader if merging LS+HS or ES+GS.
6155 * \param key Output shader part key.
6156 */
6157 static void si_get_vs_prolog_key(const struct tgsi_shader_info *info,
6158 unsigned num_input_sgprs,
6159 const struct si_vs_prolog_bits *prolog_key,
6160 struct si_shader *shader_out,
6161 union si_shader_part_key *key)
6162 {
6163 memset(key, 0, sizeof(*key));
6164 key->vs_prolog.states = *prolog_key;
6165 key->vs_prolog.num_input_sgprs = num_input_sgprs;
6166 key->vs_prolog.last_input = MAX2(1, info->num_inputs) - 1;
6167 key->vs_prolog.as_ls = shader_out->key.as_ls;
6168 key->vs_prolog.as_es = shader_out->key.as_es;
6169
6170 if (shader_out->selector->type == PIPE_SHADER_TESS_CTRL) {
6171 key->vs_prolog.as_ls = 1;
6172 key->vs_prolog.num_merged_next_stage_vgprs = 2;
6173 } else if (shader_out->selector->type == PIPE_SHADER_GEOMETRY) {
6174 key->vs_prolog.as_es = 1;
6175 key->vs_prolog.num_merged_next_stage_vgprs = 5;
6176 }
6177
6178 /* Enable loading the InstanceID VGPR. */
6179 uint16_t input_mask = u_bit_consecutive(0, info->num_inputs);
6180
6181 if ((key->vs_prolog.states.instance_divisor_is_one |
6182 key->vs_prolog.states.instance_divisor_is_fetched) & input_mask)
6183 shader_out->info.uses_instanceid = true;
6184 }
6185
6186 /**
6187 * Compute the PS prolog key, which contains all the information needed to
6188 * build the PS prolog function, and set related bits in shader->config.
6189 */
6190 static void si_get_ps_prolog_key(struct si_shader *shader,
6191 union si_shader_part_key *key,
6192 bool separate_prolog)
6193 {
6194 struct tgsi_shader_info *info = &shader->selector->info;
6195
6196 memset(key, 0, sizeof(*key));
6197 key->ps_prolog.states = shader->key.part.ps.prolog;
6198 key->ps_prolog.colors_read = info->colors_read;
6199 key->ps_prolog.num_input_sgprs = shader->info.num_input_sgprs;
6200 key->ps_prolog.num_input_vgprs = shader->info.num_input_vgprs;
6201 key->ps_prolog.wqm = info->uses_derivatives &&
6202 (key->ps_prolog.colors_read ||
6203 key->ps_prolog.states.force_persp_sample_interp ||
6204 key->ps_prolog.states.force_linear_sample_interp ||
6205 key->ps_prolog.states.force_persp_center_interp ||
6206 key->ps_prolog.states.force_linear_center_interp ||
6207 key->ps_prolog.states.bc_optimize_for_persp ||
6208 key->ps_prolog.states.bc_optimize_for_linear);
6209 key->ps_prolog.ancillary_vgpr_index = shader->info.ancillary_vgpr_index;
6210
6211 if (info->colors_read) {
6212 unsigned *color = shader->selector->color_attr_index;
6213
6214 if (shader->key.part.ps.prolog.color_two_side) {
6215 /* BCOLORs are stored after the last input. */
6216 key->ps_prolog.num_interp_inputs = info->num_inputs;
6217 key->ps_prolog.face_vgpr_index = shader->info.face_vgpr_index;
6218 shader->config.spi_ps_input_ena |= S_0286CC_FRONT_FACE_ENA(1);
6219 }
6220
6221 for (unsigned i = 0; i < 2; i++) {
6222 unsigned interp = info->input_interpolate[color[i]];
6223 unsigned location = info->input_interpolate_loc[color[i]];
6224
6225 if (!(info->colors_read & (0xf << i*4)))
6226 continue;
6227
6228 key->ps_prolog.color_attr_index[i] = color[i];
6229
6230 if (shader->key.part.ps.prolog.flatshade_colors &&
6231 interp == TGSI_INTERPOLATE_COLOR)
6232 interp = TGSI_INTERPOLATE_CONSTANT;
6233
6234 switch (interp) {
6235 case TGSI_INTERPOLATE_CONSTANT:
6236 key->ps_prolog.color_interp_vgpr_index[i] = -1;
6237 break;
6238 case TGSI_INTERPOLATE_PERSPECTIVE:
6239 case TGSI_INTERPOLATE_COLOR:
6240 /* Force the interpolation location for colors here. */
6241 if (shader->key.part.ps.prolog.force_persp_sample_interp)
6242 location = TGSI_INTERPOLATE_LOC_SAMPLE;
6243 if (shader->key.part.ps.prolog.force_persp_center_interp)
6244 location = TGSI_INTERPOLATE_LOC_CENTER;
6245
6246 switch (location) {
6247 case TGSI_INTERPOLATE_LOC_SAMPLE:
6248 key->ps_prolog.color_interp_vgpr_index[i] = 0;
6249 shader->config.spi_ps_input_ena |=
6250 S_0286CC_PERSP_SAMPLE_ENA(1);
6251 break;
6252 case TGSI_INTERPOLATE_LOC_CENTER:
6253 key->ps_prolog.color_interp_vgpr_index[i] = 2;
6254 shader->config.spi_ps_input_ena |=
6255 S_0286CC_PERSP_CENTER_ENA(1);
6256 break;
6257 case TGSI_INTERPOLATE_LOC_CENTROID:
6258 key->ps_prolog.color_interp_vgpr_index[i] = 4;
6259 shader->config.spi_ps_input_ena |=
6260 S_0286CC_PERSP_CENTROID_ENA(1);
6261 break;
6262 default:
6263 assert(0);
6264 }
6265 break;
6266 case TGSI_INTERPOLATE_LINEAR:
6267 /* Force the interpolation location for colors here. */
6268 if (shader->key.part.ps.prolog.force_linear_sample_interp)
6269 location = TGSI_INTERPOLATE_LOC_SAMPLE;
6270 if (shader->key.part.ps.prolog.force_linear_center_interp)
6271 location = TGSI_INTERPOLATE_LOC_CENTER;
6272
6273 /* The VGPR assignment for non-monolithic shaders
6274 * works because InitialPSInputAddr is set on the
6275 * main shader and PERSP_PULL_MODEL is never used.
6276 */
6277 switch (location) {
6278 case TGSI_INTERPOLATE_LOC_SAMPLE:
6279 key->ps_prolog.color_interp_vgpr_index[i] =
6280 separate_prolog ? 6 : 9;
6281 shader->config.spi_ps_input_ena |=
6282 S_0286CC_LINEAR_SAMPLE_ENA(1);
6283 break;
6284 case TGSI_INTERPOLATE_LOC_CENTER:
6285 key->ps_prolog.color_interp_vgpr_index[i] =
6286 separate_prolog ? 8 : 11;
6287 shader->config.spi_ps_input_ena |=
6288 S_0286CC_LINEAR_CENTER_ENA(1);
6289 break;
6290 case TGSI_INTERPOLATE_LOC_CENTROID:
6291 key->ps_prolog.color_interp_vgpr_index[i] =
6292 separate_prolog ? 10 : 13;
6293 shader->config.spi_ps_input_ena |=
6294 S_0286CC_LINEAR_CENTROID_ENA(1);
6295 break;
6296 default:
6297 assert(0);
6298 }
6299 break;
6300 default:
6301 assert(0);
6302 }
6303 }
6304 }
6305 }
6306
6307 /**
6308 * Check whether a PS prolog is required based on the key.
6309 */
6310 static bool si_need_ps_prolog(const union si_shader_part_key *key)
6311 {
6312 return key->ps_prolog.colors_read ||
6313 key->ps_prolog.states.force_persp_sample_interp ||
6314 key->ps_prolog.states.force_linear_sample_interp ||
6315 key->ps_prolog.states.force_persp_center_interp ||
6316 key->ps_prolog.states.force_linear_center_interp ||
6317 key->ps_prolog.states.bc_optimize_for_persp ||
6318 key->ps_prolog.states.bc_optimize_for_linear ||
6319 key->ps_prolog.states.poly_stipple ||
6320 key->ps_prolog.states.samplemask_log_ps_iter;
6321 }
6322
6323 /**
6324 * Compute the PS epilog key, which contains all the information needed to
6325 * build the PS epilog function.
6326 */
6327 static void si_get_ps_epilog_key(struct si_shader *shader,
6328 union si_shader_part_key *key)
6329 {
6330 struct tgsi_shader_info *info = &shader->selector->info;
6331 memset(key, 0, sizeof(*key));
6332 key->ps_epilog.colors_written = info->colors_written;
6333 key->ps_epilog.writes_z = info->writes_z;
6334 key->ps_epilog.writes_stencil = info->writes_stencil;
6335 key->ps_epilog.writes_samplemask = info->writes_samplemask;
6336 key->ps_epilog.states = shader->key.part.ps.epilog;
6337 }
6338
6339 /**
6340 * Build the GS prolog function. Rotate the input vertices for triangle strips
6341 * with adjacency.
6342 */
6343 static void si_build_gs_prolog_function(struct si_shader_context *ctx,
6344 union si_shader_part_key *key)
6345 {
6346 unsigned num_sgprs, num_vgprs;
6347 struct si_function_info fninfo;
6348 LLVMBuilderRef builder = ctx->ac.builder;
6349 LLVMTypeRef returns[48];
6350 LLVMValueRef func, ret;
6351
6352 si_init_function_info(&fninfo);
6353
6354 if (ctx->screen->info.chip_class >= GFX9) {
6355 num_sgprs = 8 + GFX9_GS_NUM_USER_SGPR;
6356 num_vgprs = 5; /* ES inputs are not needed by GS */
6357 } else {
6358 num_sgprs = GFX6_GS_NUM_USER_SGPR + 2;
6359 num_vgprs = 8;
6360 }
6361
6362 for (unsigned i = 0; i < num_sgprs; ++i) {
6363 add_arg(&fninfo, ARG_SGPR, ctx->i32);
6364 returns[i] = ctx->i32;
6365 }
6366
6367 for (unsigned i = 0; i < num_vgprs; ++i) {
6368 add_arg(&fninfo, ARG_VGPR, ctx->i32);
6369 returns[num_sgprs + i] = ctx->f32;
6370 }
6371
6372 /* Create the function. */
6373 si_create_function(ctx, "gs_prolog", returns, num_sgprs + num_vgprs,
6374 &fninfo, 0);
6375 func = ctx->main_fn;
6376
6377 /* Set the full EXEC mask for the prolog, because we are only fiddling
6378 * with registers here. The main shader part will set the correct EXEC
6379 * mask.
6380 */
6381 if (ctx->screen->info.chip_class >= GFX9 && !key->gs_prolog.is_monolithic)
6382 ac_init_exec_full_mask(&ctx->ac);
6383
6384 /* Copy inputs to outputs. This should be no-op, as the registers match,
6385 * but it will prevent the compiler from overwriting them unintentionally.
6386 */
6387 ret = ctx->return_value;
6388 for (unsigned i = 0; i < num_sgprs; i++) {
6389 LLVMValueRef p = LLVMGetParam(func, i);
6390 ret = LLVMBuildInsertValue(builder, ret, p, i, "");
6391 }
6392 for (unsigned i = 0; i < num_vgprs; i++) {
6393 LLVMValueRef p = LLVMGetParam(func, num_sgprs + i);
6394 p = ac_to_float(&ctx->ac, p);
6395 ret = LLVMBuildInsertValue(builder, ret, p, num_sgprs + i, "");
6396 }
6397
6398 if (key->gs_prolog.states.tri_strip_adj_fix) {
6399 /* Remap the input vertices for every other primitive. */
6400 const unsigned gfx6_vtx_params[6] = {
6401 num_sgprs,
6402 num_sgprs + 1,
6403 num_sgprs + 3,
6404 num_sgprs + 4,
6405 num_sgprs + 5,
6406 num_sgprs + 6
6407 };
6408 const unsigned gfx9_vtx_params[3] = {
6409 num_sgprs,
6410 num_sgprs + 1,
6411 num_sgprs + 4,
6412 };
6413 LLVMValueRef vtx_in[6], vtx_out[6];
6414 LLVMValueRef prim_id, rotate;
6415
6416 if (ctx->screen->info.chip_class >= GFX9) {
6417 for (unsigned i = 0; i < 3; i++) {
6418 vtx_in[i*2] = unpack_param(ctx, gfx9_vtx_params[i], 0, 16);
6419 vtx_in[i*2+1] = unpack_param(ctx, gfx9_vtx_params[i], 16, 16);
6420 }
6421 } else {
6422 for (unsigned i = 0; i < 6; i++)
6423 vtx_in[i] = LLVMGetParam(func, gfx6_vtx_params[i]);
6424 }
6425
6426 prim_id = LLVMGetParam(func, num_sgprs + 2);
6427 rotate = LLVMBuildTrunc(builder, prim_id, ctx->i1, "");
6428
6429 for (unsigned i = 0; i < 6; ++i) {
6430 LLVMValueRef base, rotated;
6431 base = vtx_in[i];
6432 rotated = vtx_in[(i + 4) % 6];
6433 vtx_out[i] = LLVMBuildSelect(builder, rotate, rotated, base, "");
6434 }
6435
6436 if (ctx->screen->info.chip_class >= GFX9) {
6437 for (unsigned i = 0; i < 3; i++) {
6438 LLVMValueRef hi, out;
6439
6440 hi = LLVMBuildShl(builder, vtx_out[i*2+1],
6441 LLVMConstInt(ctx->i32, 16, 0), "");
6442 out = LLVMBuildOr(builder, vtx_out[i*2], hi, "");
6443 out = ac_to_float(&ctx->ac, out);
6444 ret = LLVMBuildInsertValue(builder, ret, out,
6445 gfx9_vtx_params[i], "");
6446 }
6447 } else {
6448 for (unsigned i = 0; i < 6; i++) {
6449 LLVMValueRef out;
6450
6451 out = ac_to_float(&ctx->ac, vtx_out[i]);
6452 ret = LLVMBuildInsertValue(builder, ret, out,
6453 gfx6_vtx_params[i], "");
6454 }
6455 }
6456 }
6457
6458 LLVMBuildRet(builder, ret);
6459 }
6460
6461 /**
6462 * Given a list of shader part functions, build a wrapper function that
6463 * runs them in sequence to form a monolithic shader.
6464 */
6465 static void si_build_wrapper_function(struct si_shader_context *ctx,
6466 LLVMValueRef *parts,
6467 unsigned num_parts,
6468 unsigned main_part,
6469 unsigned next_shader_first_part)
6470 {
6471 LLVMBuilderRef builder = ctx->ac.builder;
6472 /* PS epilog has one arg per color component; gfx9 merged shader
6473 * prologs need to forward 32 user SGPRs.
6474 */
6475 struct si_function_info fninfo;
6476 LLVMValueRef initial[64], out[64];
6477 LLVMTypeRef function_type;
6478 unsigned num_first_params;
6479 unsigned num_out, initial_num_out;
6480 MAYBE_UNUSED unsigned num_out_sgpr; /* used in debug checks */
6481 MAYBE_UNUSED unsigned initial_num_out_sgpr; /* used in debug checks */
6482 unsigned num_sgprs, num_vgprs;
6483 unsigned gprs;
6484 struct lp_build_if_state if_state;
6485
6486 si_init_function_info(&fninfo);
6487
6488 for (unsigned i = 0; i < num_parts; ++i) {
6489 lp_add_function_attr(parts[i], -1, LP_FUNC_ATTR_ALWAYSINLINE);
6490 LLVMSetLinkage(parts[i], LLVMPrivateLinkage);
6491 }
6492
6493 /* The parameters of the wrapper function correspond to those of the
6494 * first part in terms of SGPRs and VGPRs, but we use the types of the
6495 * main part to get the right types. This is relevant for the
6496 * dereferenceable attribute on descriptor table pointers.
6497 */
6498 num_sgprs = 0;
6499 num_vgprs = 0;
6500
6501 function_type = LLVMGetElementType(LLVMTypeOf(parts[0]));
6502 num_first_params = LLVMCountParamTypes(function_type);
6503
6504 for (unsigned i = 0; i < num_first_params; ++i) {
6505 LLVMValueRef param = LLVMGetParam(parts[0], i);
6506
6507 if (ac_is_sgpr_param(param)) {
6508 assert(num_vgprs == 0);
6509 num_sgprs += ac_get_type_size(LLVMTypeOf(param)) / 4;
6510 } else {
6511 num_vgprs += ac_get_type_size(LLVMTypeOf(param)) / 4;
6512 }
6513 }
6514
6515 gprs = 0;
6516 while (gprs < num_sgprs + num_vgprs) {
6517 LLVMValueRef param = LLVMGetParam(parts[main_part], fninfo.num_params);
6518 LLVMTypeRef type = LLVMTypeOf(param);
6519 unsigned size = ac_get_type_size(type) / 4;
6520
6521 add_arg(&fninfo, gprs < num_sgprs ? ARG_SGPR : ARG_VGPR, type);
6522
6523 assert(ac_is_sgpr_param(param) == (gprs < num_sgprs));
6524 assert(gprs + size <= num_sgprs + num_vgprs &&
6525 (gprs >= num_sgprs || gprs + size <= num_sgprs));
6526
6527 gprs += size;
6528 }
6529
6530 si_create_function(ctx, "wrapper", NULL, 0, &fninfo,
6531 si_get_max_workgroup_size(ctx->shader));
6532
6533 if (is_merged_shader(ctx->shader))
6534 ac_init_exec_full_mask(&ctx->ac);
6535
6536 /* Record the arguments of the function as if they were an output of
6537 * a previous part.
6538 */
6539 num_out = 0;
6540 num_out_sgpr = 0;
6541
6542 for (unsigned i = 0; i < fninfo.num_params; ++i) {
6543 LLVMValueRef param = LLVMGetParam(ctx->main_fn, i);
6544 LLVMTypeRef param_type = LLVMTypeOf(param);
6545 LLVMTypeRef out_type = i < fninfo.num_sgpr_params ? ctx->i32 : ctx->f32;
6546 unsigned size = ac_get_type_size(param_type) / 4;
6547
6548 if (size == 1) {
6549 if (param_type != out_type)
6550 param = LLVMBuildBitCast(builder, param, out_type, "");
6551 out[num_out++] = param;
6552 } else {
6553 LLVMTypeRef vector_type = LLVMVectorType(out_type, size);
6554
6555 if (LLVMGetTypeKind(param_type) == LLVMPointerTypeKind) {
6556 param = LLVMBuildPtrToInt(builder, param, ctx->i64, "");
6557 param_type = ctx->i64;
6558 }
6559
6560 if (param_type != vector_type)
6561 param = LLVMBuildBitCast(builder, param, vector_type, "");
6562
6563 for (unsigned j = 0; j < size; ++j)
6564 out[num_out++] = LLVMBuildExtractElement(
6565 builder, param, LLVMConstInt(ctx->i32, j, 0), "");
6566 }
6567
6568 if (i < fninfo.num_sgpr_params)
6569 num_out_sgpr = num_out;
6570 }
6571
6572 memcpy(initial, out, sizeof(out));
6573 initial_num_out = num_out;
6574 initial_num_out_sgpr = num_out_sgpr;
6575
6576 /* Now chain the parts. */
6577 for (unsigned part = 0; part < num_parts; ++part) {
6578 LLVMValueRef in[48];
6579 LLVMValueRef ret;
6580 LLVMTypeRef ret_type;
6581 unsigned out_idx = 0;
6582 unsigned num_params = LLVMCountParams(parts[part]);
6583
6584 /* Merged shaders are executed conditionally depending
6585 * on the number of enabled threads passed in the input SGPRs. */
6586 if (is_merged_shader(ctx->shader) && part == 0) {
6587 LLVMValueRef ena, count = initial[3];
6588
6589 count = LLVMBuildAnd(builder, count,
6590 LLVMConstInt(ctx->i32, 0x7f, 0), "");
6591 ena = LLVMBuildICmp(builder, LLVMIntULT,
6592 ac_get_thread_id(&ctx->ac), count, "");
6593 lp_build_if(&if_state, &ctx->gallivm, ena);
6594 }
6595
6596 /* Derive arguments for the next part from outputs of the
6597 * previous one.
6598 */
6599 for (unsigned param_idx = 0; param_idx < num_params; ++param_idx) {
6600 LLVMValueRef param;
6601 LLVMTypeRef param_type;
6602 bool is_sgpr;
6603 unsigned param_size;
6604 LLVMValueRef arg = NULL;
6605
6606 param = LLVMGetParam(parts[part], param_idx);
6607 param_type = LLVMTypeOf(param);
6608 param_size = ac_get_type_size(param_type) / 4;
6609 is_sgpr = ac_is_sgpr_param(param);
6610
6611 if (is_sgpr)
6612 lp_add_function_attr(parts[part], param_idx + 1, LP_FUNC_ATTR_INREG);
6613
6614 assert(out_idx + param_size <= (is_sgpr ? num_out_sgpr : num_out));
6615 assert(is_sgpr || out_idx >= num_out_sgpr);
6616
6617 if (param_size == 1)
6618 arg = out[out_idx];
6619 else
6620 arg = lp_build_gather_values(&ctx->gallivm, &out[out_idx], param_size);
6621
6622 if (LLVMTypeOf(arg) != param_type) {
6623 if (LLVMGetTypeKind(param_type) == LLVMPointerTypeKind) {
6624 arg = LLVMBuildBitCast(builder, arg, ctx->i64, "");
6625 arg = LLVMBuildIntToPtr(builder, arg, param_type, "");
6626 } else {
6627 arg = LLVMBuildBitCast(builder, arg, param_type, "");
6628 }
6629 }
6630
6631 in[param_idx] = arg;
6632 out_idx += param_size;
6633 }
6634
6635 ret = LLVMBuildCall(builder, parts[part], in, num_params, "");
6636
6637 if (is_merged_shader(ctx->shader) &&
6638 part + 1 == next_shader_first_part) {
6639 lp_build_endif(&if_state);
6640
6641 /* The second half of the merged shader should use
6642 * the inputs from the toplevel (wrapper) function,
6643 * not the return value from the last call.
6644 *
6645 * That's because the last call was executed condi-
6646 * tionally, so we can't consume it in the main
6647 * block.
6648 */
6649 memcpy(out, initial, sizeof(initial));
6650 num_out = initial_num_out;
6651 num_out_sgpr = initial_num_out_sgpr;
6652 continue;
6653 }
6654
6655 /* Extract the returned GPRs. */
6656 ret_type = LLVMTypeOf(ret);
6657 num_out = 0;
6658 num_out_sgpr = 0;
6659
6660 if (LLVMGetTypeKind(ret_type) != LLVMVoidTypeKind) {
6661 assert(LLVMGetTypeKind(ret_type) == LLVMStructTypeKind);
6662
6663 unsigned ret_size = LLVMCountStructElementTypes(ret_type);
6664
6665 for (unsigned i = 0; i < ret_size; ++i) {
6666 LLVMValueRef val =
6667 LLVMBuildExtractValue(builder, ret, i, "");
6668
6669 assert(num_out < ARRAY_SIZE(out));
6670 out[num_out++] = val;
6671
6672 if (LLVMTypeOf(val) == ctx->i32) {
6673 assert(num_out_sgpr + 1 == num_out);
6674 num_out_sgpr = num_out;
6675 }
6676 }
6677 }
6678 }
6679
6680 LLVMBuildRetVoid(builder);
6681 }
6682
6683 int si_compile_tgsi_shader(struct si_screen *sscreen,
6684 LLVMTargetMachineRef tm,
6685 struct si_shader *shader,
6686 bool is_monolithic,
6687 struct pipe_debug_callback *debug)
6688 {
6689 struct si_shader_selector *sel = shader->selector;
6690 struct si_shader_context ctx;
6691 int r = -1;
6692
6693 /* Dump TGSI code before doing TGSI->LLVM conversion in case the
6694 * conversion fails. */
6695 if (si_can_dump_shader(sscreen, sel->info.processor) &&
6696 !(sscreen->debug_flags & DBG(NO_TGSI))) {
6697 if (sel->tokens)
6698 tgsi_dump(sel->tokens, 0);
6699 else
6700 nir_print_shader(sel->nir, stderr);
6701 si_dump_streamout(&sel->so);
6702 }
6703
6704 si_init_shader_ctx(&ctx, sscreen, tm);
6705 si_llvm_context_set_tgsi(&ctx, shader);
6706 ctx.separate_prolog = !is_monolithic;
6707
6708 memset(shader->info.vs_output_param_offset, AC_EXP_PARAM_UNDEFINED,
6709 sizeof(shader->info.vs_output_param_offset));
6710
6711 shader->info.uses_instanceid = sel->info.uses_instanceid;
6712
6713 if (!si_compile_tgsi_main(&ctx, is_monolithic)) {
6714 si_llvm_dispose(&ctx);
6715 return -1;
6716 }
6717
6718 if (is_monolithic && ctx.type == PIPE_SHADER_VERTEX) {
6719 LLVMValueRef parts[2];
6720 bool need_prolog = sel->vs_needs_prolog;
6721
6722 parts[1] = ctx.main_fn;
6723
6724 if (need_prolog) {
6725 union si_shader_part_key prolog_key;
6726 si_get_vs_prolog_key(&sel->info,
6727 shader->info.num_input_sgprs,
6728 &shader->key.part.vs.prolog,
6729 shader, &prolog_key);
6730 si_build_vs_prolog_function(&ctx, &prolog_key);
6731 parts[0] = ctx.main_fn;
6732 }
6733
6734 si_build_wrapper_function(&ctx, parts + !need_prolog,
6735 1 + need_prolog, need_prolog, 0);
6736 } else if (is_monolithic && ctx.type == PIPE_SHADER_TESS_CTRL) {
6737 if (sscreen->info.chip_class >= GFX9) {
6738 struct si_shader_selector *ls = shader->key.part.tcs.ls;
6739 LLVMValueRef parts[4];
6740 bool vs_needs_prolog =
6741 si_vs_needs_prolog(ls, &shader->key.part.tcs.ls_prolog);
6742
6743 /* TCS main part */
6744 parts[2] = ctx.main_fn;
6745
6746 /* TCS epilog */
6747 union si_shader_part_key tcs_epilog_key;
6748 memset(&tcs_epilog_key, 0, sizeof(tcs_epilog_key));
6749 tcs_epilog_key.tcs_epilog.states = shader->key.part.tcs.epilog;
6750 si_build_tcs_epilog_function(&ctx, &tcs_epilog_key);
6751 parts[3] = ctx.main_fn;
6752
6753 /* VS prolog */
6754 if (vs_needs_prolog) {
6755 union si_shader_part_key vs_prolog_key;
6756 si_get_vs_prolog_key(&ls->info,
6757 shader->info.num_input_sgprs,
6758 &shader->key.part.tcs.ls_prolog,
6759 shader, &vs_prolog_key);
6760 vs_prolog_key.vs_prolog.is_monolithic = true;
6761 si_build_vs_prolog_function(&ctx, &vs_prolog_key);
6762 parts[0] = ctx.main_fn;
6763 }
6764
6765 /* VS as LS main part */
6766 struct si_shader shader_ls = {};
6767 shader_ls.selector = ls;
6768 shader_ls.key.as_ls = 1;
6769 shader_ls.key.mono = shader->key.mono;
6770 shader_ls.key.opt = shader->key.opt;
6771 si_llvm_context_set_tgsi(&ctx, &shader_ls);
6772
6773 if (!si_compile_tgsi_main(&ctx, true)) {
6774 si_llvm_dispose(&ctx);
6775 return -1;
6776 }
6777 shader->info.uses_instanceid |= ls->info.uses_instanceid;
6778 parts[1] = ctx.main_fn;
6779
6780 /* Reset the shader context. */
6781 ctx.shader = shader;
6782 ctx.type = PIPE_SHADER_TESS_CTRL;
6783
6784 si_build_wrapper_function(&ctx,
6785 parts + !vs_needs_prolog,
6786 4 - !vs_needs_prolog, 0,
6787 vs_needs_prolog ? 2 : 1);
6788 } else {
6789 LLVMValueRef parts[2];
6790 union si_shader_part_key epilog_key;
6791
6792 parts[0] = ctx.main_fn;
6793
6794 memset(&epilog_key, 0, sizeof(epilog_key));
6795 epilog_key.tcs_epilog.states = shader->key.part.tcs.epilog;
6796 si_build_tcs_epilog_function(&ctx, &epilog_key);
6797 parts[1] = ctx.main_fn;
6798
6799 si_build_wrapper_function(&ctx, parts, 2, 0, 0);
6800 }
6801 } else if (is_monolithic && ctx.type == PIPE_SHADER_GEOMETRY) {
6802 if (ctx.screen->info.chip_class >= GFX9) {
6803 struct si_shader_selector *es = shader->key.part.gs.es;
6804 LLVMValueRef es_prolog = NULL;
6805 LLVMValueRef es_main = NULL;
6806 LLVMValueRef gs_prolog = NULL;
6807 LLVMValueRef gs_main = ctx.main_fn;
6808
6809 /* GS prolog */
6810 union si_shader_part_key gs_prolog_key;
6811 memset(&gs_prolog_key, 0, sizeof(gs_prolog_key));
6812 gs_prolog_key.gs_prolog.states = shader->key.part.gs.prolog;
6813 gs_prolog_key.gs_prolog.is_monolithic = true;
6814 si_build_gs_prolog_function(&ctx, &gs_prolog_key);
6815 gs_prolog = ctx.main_fn;
6816
6817 /* ES prolog */
6818 if (es->vs_needs_prolog) {
6819 union si_shader_part_key vs_prolog_key;
6820 si_get_vs_prolog_key(&es->info,
6821 shader->info.num_input_sgprs,
6822 &shader->key.part.gs.vs_prolog,
6823 shader, &vs_prolog_key);
6824 vs_prolog_key.vs_prolog.is_monolithic = true;
6825 si_build_vs_prolog_function(&ctx, &vs_prolog_key);
6826 es_prolog = ctx.main_fn;
6827 }
6828
6829 /* ES main part */
6830 struct si_shader shader_es = {};
6831 shader_es.selector = es;
6832 shader_es.key.as_es = 1;
6833 shader_es.key.mono = shader->key.mono;
6834 shader_es.key.opt = shader->key.opt;
6835 si_llvm_context_set_tgsi(&ctx, &shader_es);
6836
6837 if (!si_compile_tgsi_main(&ctx, true)) {
6838 si_llvm_dispose(&ctx);
6839 return -1;
6840 }
6841 shader->info.uses_instanceid |= es->info.uses_instanceid;
6842 es_main = ctx.main_fn;
6843
6844 /* Reset the shader context. */
6845 ctx.shader = shader;
6846 ctx.type = PIPE_SHADER_GEOMETRY;
6847
6848 /* Prepare the array of shader parts. */
6849 LLVMValueRef parts[4];
6850 unsigned num_parts = 0, main_part, next_first_part;
6851
6852 if (es_prolog)
6853 parts[num_parts++] = es_prolog;
6854
6855 parts[main_part = num_parts++] = es_main;
6856 parts[next_first_part = num_parts++] = gs_prolog;
6857 parts[num_parts++] = gs_main;
6858
6859 si_build_wrapper_function(&ctx, parts, num_parts,
6860 main_part, next_first_part);
6861 } else {
6862 LLVMValueRef parts[2];
6863 union si_shader_part_key prolog_key;
6864
6865 parts[1] = ctx.main_fn;
6866
6867 memset(&prolog_key, 0, sizeof(prolog_key));
6868 prolog_key.gs_prolog.states = shader->key.part.gs.prolog;
6869 si_build_gs_prolog_function(&ctx, &prolog_key);
6870 parts[0] = ctx.main_fn;
6871
6872 si_build_wrapper_function(&ctx, parts, 2, 1, 0);
6873 }
6874 } else if (is_monolithic && ctx.type == PIPE_SHADER_FRAGMENT) {
6875 LLVMValueRef parts[3];
6876 union si_shader_part_key prolog_key;
6877 union si_shader_part_key epilog_key;
6878 bool need_prolog;
6879
6880 si_get_ps_prolog_key(shader, &prolog_key, false);
6881 need_prolog = si_need_ps_prolog(&prolog_key);
6882
6883 parts[need_prolog ? 1 : 0] = ctx.main_fn;
6884
6885 if (need_prolog) {
6886 si_build_ps_prolog_function(&ctx, &prolog_key);
6887 parts[0] = ctx.main_fn;
6888 }
6889
6890 si_get_ps_epilog_key(shader, &epilog_key);
6891 si_build_ps_epilog_function(&ctx, &epilog_key);
6892 parts[need_prolog ? 2 : 1] = ctx.main_fn;
6893
6894 si_build_wrapper_function(&ctx, parts, need_prolog ? 3 : 2,
6895 need_prolog ? 1 : 0, 0);
6896 }
6897
6898 si_llvm_optimize_module(&ctx);
6899
6900 /* Post-optimization transformations and analysis. */
6901 si_optimize_vs_outputs(&ctx);
6902
6903 if ((debug && debug->debug_message) ||
6904 si_can_dump_shader(sscreen, ctx.type))
6905 si_count_scratch_private_memory(&ctx);
6906
6907 /* Compile to bytecode. */
6908 r = si_compile_llvm(sscreen, &shader->binary, &shader->config, tm,
6909 ctx.gallivm.module, debug, ctx.type, "TGSI shader");
6910 si_llvm_dispose(&ctx);
6911 if (r) {
6912 fprintf(stderr, "LLVM failed to compile shader\n");
6913 return r;
6914 }
6915
6916 /* Validate SGPR and VGPR usage for compute to detect compiler bugs.
6917 * LLVM 3.9svn has this bug.
6918 */
6919 if (sel->type == PIPE_SHADER_COMPUTE) {
6920 unsigned wave_size = 64;
6921 unsigned max_vgprs = 256;
6922 unsigned max_sgprs = sscreen->info.chip_class >= VI ? 800 : 512;
6923 unsigned max_sgprs_per_wave = 128;
6924 unsigned max_block_threads = si_get_max_workgroup_size(shader);
6925 unsigned min_waves_per_cu = DIV_ROUND_UP(max_block_threads, wave_size);
6926 unsigned min_waves_per_simd = DIV_ROUND_UP(min_waves_per_cu, 4);
6927
6928 max_vgprs = max_vgprs / min_waves_per_simd;
6929 max_sgprs = MIN2(max_sgprs / min_waves_per_simd, max_sgprs_per_wave);
6930
6931 if (shader->config.num_sgprs > max_sgprs ||
6932 shader->config.num_vgprs > max_vgprs) {
6933 fprintf(stderr, "LLVM failed to compile a shader correctly: "
6934 "SGPR:VGPR usage is %u:%u, but the hw limit is %u:%u\n",
6935 shader->config.num_sgprs, shader->config.num_vgprs,
6936 max_sgprs, max_vgprs);
6937
6938 /* Just terminate the process, because dependent
6939 * shaders can hang due to bad input data, but use
6940 * the env var to allow shader-db to work.
6941 */
6942 if (!debug_get_bool_option("SI_PASS_BAD_SHADERS", false))
6943 abort();
6944 }
6945 }
6946
6947 /* Add the scratch offset to input SGPRs. */
6948 if (shader->config.scratch_bytes_per_wave && !is_merged_shader(shader))
6949 shader->info.num_input_sgprs += 1; /* scratch byte offset */
6950
6951 /* Calculate the number of fragment input VGPRs. */
6952 if (ctx.type == PIPE_SHADER_FRAGMENT) {
6953 shader->info.num_input_vgprs = 0;
6954 shader->info.face_vgpr_index = -1;
6955 shader->info.ancillary_vgpr_index = -1;
6956
6957 if (G_0286CC_PERSP_SAMPLE_ENA(shader->config.spi_ps_input_addr))
6958 shader->info.num_input_vgprs += 2;
6959 if (G_0286CC_PERSP_CENTER_ENA(shader->config.spi_ps_input_addr))
6960 shader->info.num_input_vgprs += 2;
6961 if (G_0286CC_PERSP_CENTROID_ENA(shader->config.spi_ps_input_addr))
6962 shader->info.num_input_vgprs += 2;
6963 if (G_0286CC_PERSP_PULL_MODEL_ENA(shader->config.spi_ps_input_addr))
6964 shader->info.num_input_vgprs += 3;
6965 if (G_0286CC_LINEAR_SAMPLE_ENA(shader->config.spi_ps_input_addr))
6966 shader->info.num_input_vgprs += 2;
6967 if (G_0286CC_LINEAR_CENTER_ENA(shader->config.spi_ps_input_addr))
6968 shader->info.num_input_vgprs += 2;
6969 if (G_0286CC_LINEAR_CENTROID_ENA(shader->config.spi_ps_input_addr))
6970 shader->info.num_input_vgprs += 2;
6971 if (G_0286CC_LINE_STIPPLE_TEX_ENA(shader->config.spi_ps_input_addr))
6972 shader->info.num_input_vgprs += 1;
6973 if (G_0286CC_POS_X_FLOAT_ENA(shader->config.spi_ps_input_addr))
6974 shader->info.num_input_vgprs += 1;
6975 if (G_0286CC_POS_Y_FLOAT_ENA(shader->config.spi_ps_input_addr))
6976 shader->info.num_input_vgprs += 1;
6977 if (G_0286CC_POS_Z_FLOAT_ENA(shader->config.spi_ps_input_addr))
6978 shader->info.num_input_vgprs += 1;
6979 if (G_0286CC_POS_W_FLOAT_ENA(shader->config.spi_ps_input_addr))
6980 shader->info.num_input_vgprs += 1;
6981 if (G_0286CC_FRONT_FACE_ENA(shader->config.spi_ps_input_addr)) {
6982 shader->info.face_vgpr_index = shader->info.num_input_vgprs;
6983 shader->info.num_input_vgprs += 1;
6984 }
6985 if (G_0286CC_ANCILLARY_ENA(shader->config.spi_ps_input_addr)) {
6986 shader->info.ancillary_vgpr_index = shader->info.num_input_vgprs;
6987 shader->info.num_input_vgprs += 1;
6988 }
6989 if (G_0286CC_SAMPLE_COVERAGE_ENA(shader->config.spi_ps_input_addr))
6990 shader->info.num_input_vgprs += 1;
6991 if (G_0286CC_POS_FIXED_PT_ENA(shader->config.spi_ps_input_addr))
6992 shader->info.num_input_vgprs += 1;
6993 }
6994
6995 si_calculate_max_simd_waves(shader);
6996 si_shader_dump_stats_for_shader_db(shader, debug);
6997 return 0;
6998 }
6999
7000 /**
7001 * Create, compile and return a shader part (prolog or epilog).
7002 *
7003 * \param sscreen screen
7004 * \param list list of shader parts of the same category
7005 * \param type shader type
7006 * \param key shader part key
7007 * \param prolog whether the part being requested is a prolog
7008 * \param tm LLVM target machine
7009 * \param debug debug callback
7010 * \param build the callback responsible for building the main function
7011 * \return non-NULL on success
7012 */
7013 static struct si_shader_part *
7014 si_get_shader_part(struct si_screen *sscreen,
7015 struct si_shader_part **list,
7016 enum pipe_shader_type type,
7017 bool prolog,
7018 union si_shader_part_key *key,
7019 LLVMTargetMachineRef tm,
7020 struct pipe_debug_callback *debug,
7021 void (*build)(struct si_shader_context *,
7022 union si_shader_part_key *),
7023 const char *name)
7024 {
7025 struct si_shader_part *result;
7026
7027 mtx_lock(&sscreen->shader_parts_mutex);
7028
7029 /* Find existing. */
7030 for (result = *list; result; result = result->next) {
7031 if (memcmp(&result->key, key, sizeof(*key)) == 0) {
7032 mtx_unlock(&sscreen->shader_parts_mutex);
7033 return result;
7034 }
7035 }
7036
7037 /* Compile a new one. */
7038 result = CALLOC_STRUCT(si_shader_part);
7039 result->key = *key;
7040
7041 struct si_shader shader = {};
7042 struct si_shader_context ctx;
7043
7044 si_init_shader_ctx(&ctx, sscreen, tm);
7045 ctx.shader = &shader;
7046 ctx.type = type;
7047
7048 switch (type) {
7049 case PIPE_SHADER_VERTEX:
7050 shader.key.as_ls = key->vs_prolog.as_ls;
7051 shader.key.as_es = key->vs_prolog.as_es;
7052 break;
7053 case PIPE_SHADER_TESS_CTRL:
7054 assert(!prolog);
7055 shader.key.part.tcs.epilog = key->tcs_epilog.states;
7056 break;
7057 case PIPE_SHADER_GEOMETRY:
7058 assert(prolog);
7059 break;
7060 case PIPE_SHADER_FRAGMENT:
7061 if (prolog)
7062 shader.key.part.ps.prolog = key->ps_prolog.states;
7063 else
7064 shader.key.part.ps.epilog = key->ps_epilog.states;
7065 break;
7066 default:
7067 unreachable("bad shader part");
7068 }
7069
7070 build(&ctx, key);
7071
7072 /* Compile. */
7073 si_llvm_optimize_module(&ctx);
7074
7075 if (si_compile_llvm(sscreen, &result->binary, &result->config, tm,
7076 ctx.ac.module, debug, ctx.type, name)) {
7077 FREE(result);
7078 result = NULL;
7079 goto out;
7080 }
7081
7082 result->next = *list;
7083 *list = result;
7084
7085 out:
7086 si_llvm_dispose(&ctx);
7087 mtx_unlock(&sscreen->shader_parts_mutex);
7088 return result;
7089 }
7090
7091 static LLVMValueRef si_prolog_get_rw_buffers(struct si_shader_context *ctx)
7092 {
7093 LLVMValueRef ptr[2], list;
7094 bool is_merged_shader =
7095 ctx->screen->info.chip_class >= GFX9 &&
7096 (ctx->type == PIPE_SHADER_TESS_CTRL ||
7097 ctx->type == PIPE_SHADER_GEOMETRY ||
7098 ctx->shader->key.as_ls || ctx->shader->key.as_es);
7099
7100 /* Get the pointer to rw buffers. */
7101 ptr[0] = LLVMGetParam(ctx->main_fn, (is_merged_shader ? 8 : 0) + SI_SGPR_RW_BUFFERS);
7102 ptr[1] = LLVMGetParam(ctx->main_fn, (is_merged_shader ? 8 : 0) + SI_SGPR_RW_BUFFERS_HI);
7103 list = lp_build_gather_values(&ctx->gallivm, ptr, 2);
7104 list = LLVMBuildBitCast(ctx->ac.builder, list, ctx->i64, "");
7105 list = LLVMBuildIntToPtr(ctx->ac.builder, list,
7106 ac_array_in_const_addr_space(ctx->v4i32), "");
7107 return list;
7108 }
7109
7110 /**
7111 * Build the vertex shader prolog function.
7112 *
7113 * The inputs are the same as VS (a lot of SGPRs and 4 VGPR system values).
7114 * All inputs are returned unmodified. The vertex load indices are
7115 * stored after them, which will be used by the API VS for fetching inputs.
7116 *
7117 * For example, the expected outputs for instance_divisors[] = {0, 1, 2} are:
7118 * input_v0,
7119 * input_v1,
7120 * input_v2,
7121 * input_v3,
7122 * (VertexID + BaseVertex),
7123 * (InstanceID + StartInstance),
7124 * (InstanceID / 2 + StartInstance)
7125 */
7126 static void si_build_vs_prolog_function(struct si_shader_context *ctx,
7127 union si_shader_part_key *key)
7128 {
7129 struct si_function_info fninfo;
7130 LLVMTypeRef *returns;
7131 LLVMValueRef ret, func;
7132 int num_returns, i;
7133 unsigned first_vs_vgpr = key->vs_prolog.num_merged_next_stage_vgprs;
7134 unsigned num_input_vgprs = key->vs_prolog.num_merged_next_stage_vgprs + 4;
7135 LLVMValueRef input_vgprs[9];
7136 unsigned num_all_input_regs = key->vs_prolog.num_input_sgprs +
7137 num_input_vgprs;
7138 unsigned user_sgpr_base = key->vs_prolog.num_merged_next_stage_vgprs ? 8 : 0;
7139
7140 si_init_function_info(&fninfo);
7141
7142 /* 4 preloaded VGPRs + vertex load indices as prolog outputs */
7143 returns = alloca((num_all_input_regs + key->vs_prolog.last_input + 1) *
7144 sizeof(LLVMTypeRef));
7145 num_returns = 0;
7146
7147 /* Declare input and output SGPRs. */
7148 for (i = 0; i < key->vs_prolog.num_input_sgprs; i++) {
7149 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7150 returns[num_returns++] = ctx->i32;
7151 }
7152
7153 /* Preloaded VGPRs (outputs must be floats) */
7154 for (i = 0; i < num_input_vgprs; i++) {
7155 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &input_vgprs[i]);
7156 returns[num_returns++] = ctx->f32;
7157 }
7158
7159 /* Vertex load indices. */
7160 for (i = 0; i <= key->vs_prolog.last_input; i++)
7161 returns[num_returns++] = ctx->f32;
7162
7163 /* Create the function. */
7164 si_create_function(ctx, "vs_prolog", returns, num_returns, &fninfo, 0);
7165 func = ctx->main_fn;
7166
7167 if (key->vs_prolog.num_merged_next_stage_vgprs) {
7168 if (!key->vs_prolog.is_monolithic)
7169 si_init_exec_from_input(ctx, 3, 0);
7170
7171 if (key->vs_prolog.as_ls &&
7172 ctx->screen->has_ls_vgpr_init_bug) {
7173 /* If there are no HS threads, SPI loads the LS VGPRs
7174 * starting at VGPR 0. Shift them back to where they
7175 * belong.
7176 */
7177 LLVMValueRef has_hs_threads =
7178 LLVMBuildICmp(ctx->ac.builder, LLVMIntNE,
7179 unpack_param(ctx, 3, 8, 8),
7180 ctx->i32_0, "");
7181
7182 for (i = 4; i > 0; --i) {
7183 input_vgprs[i + 1] =
7184 LLVMBuildSelect(ctx->ac.builder, has_hs_threads,
7185 input_vgprs[i + 1],
7186 input_vgprs[i - 1], "");
7187 }
7188 }
7189 }
7190
7191 ctx->abi.vertex_id = input_vgprs[first_vs_vgpr];
7192 ctx->abi.instance_id = input_vgprs[first_vs_vgpr + (key->vs_prolog.as_ls ? 2 : 1)];
7193
7194 /* Copy inputs to outputs. This should be no-op, as the registers match,
7195 * but it will prevent the compiler from overwriting them unintentionally.
7196 */
7197 ret = ctx->return_value;
7198 for (i = 0; i < key->vs_prolog.num_input_sgprs; i++) {
7199 LLVMValueRef p = LLVMGetParam(func, i);
7200 ret = LLVMBuildInsertValue(ctx->ac.builder, ret, p, i, "");
7201 }
7202 for (i = 0; i < num_input_vgprs; i++) {
7203 LLVMValueRef p = input_vgprs[i];
7204 p = ac_to_float(&ctx->ac, p);
7205 ret = LLVMBuildInsertValue(ctx->ac.builder, ret, p,
7206 key->vs_prolog.num_input_sgprs + i, "");
7207 }
7208
7209 /* Compute vertex load indices from instance divisors. */
7210 LLVMValueRef instance_divisor_constbuf = NULL;
7211
7212 if (key->vs_prolog.states.instance_divisor_is_fetched) {
7213 LLVMValueRef list = si_prolog_get_rw_buffers(ctx);
7214 LLVMValueRef buf_index =
7215 LLVMConstInt(ctx->i32, SI_VS_CONST_INSTANCE_DIVISORS, 0);
7216 instance_divisor_constbuf =
7217 ac_build_load_to_sgpr(&ctx->ac, list, buf_index);
7218 }
7219
7220 for (i = 0; i <= key->vs_prolog.last_input; i++) {
7221 bool divisor_is_one =
7222 key->vs_prolog.states.instance_divisor_is_one & (1u << i);
7223 bool divisor_is_fetched =
7224 key->vs_prolog.states.instance_divisor_is_fetched & (1u << i);
7225 LLVMValueRef index;
7226
7227 if (divisor_is_one || divisor_is_fetched) {
7228 LLVMValueRef divisor = ctx->i32_1;
7229
7230 if (divisor_is_fetched) {
7231 divisor = buffer_load_const(ctx, instance_divisor_constbuf,
7232 LLVMConstInt(ctx->i32, i * 4, 0));
7233 divisor = ac_to_integer(&ctx->ac, divisor);
7234 }
7235
7236 /* InstanceID / Divisor + StartInstance */
7237 index = get_instance_index_for_fetch(ctx,
7238 user_sgpr_base +
7239 SI_SGPR_START_INSTANCE,
7240 divisor);
7241 } else {
7242 /* VertexID + BaseVertex */
7243 index = LLVMBuildAdd(ctx->ac.builder,
7244 ctx->abi.vertex_id,
7245 LLVMGetParam(func, user_sgpr_base +
7246 SI_SGPR_BASE_VERTEX), "");
7247 }
7248
7249 index = ac_to_float(&ctx->ac, index);
7250 ret = LLVMBuildInsertValue(ctx->ac.builder, ret, index,
7251 fninfo.num_params + i, "");
7252 }
7253
7254 si_llvm_build_ret(ctx, ret);
7255 }
7256
7257 static bool si_get_vs_prolog(struct si_screen *sscreen,
7258 LLVMTargetMachineRef tm,
7259 struct si_shader *shader,
7260 struct pipe_debug_callback *debug,
7261 struct si_shader *main_part,
7262 const struct si_vs_prolog_bits *key)
7263 {
7264 struct si_shader_selector *vs = main_part->selector;
7265
7266 if (!si_vs_needs_prolog(vs, key))
7267 return true;
7268
7269 /* Get the prolog. */
7270 union si_shader_part_key prolog_key;
7271 si_get_vs_prolog_key(&vs->info, main_part->info.num_input_sgprs,
7272 key, shader, &prolog_key);
7273
7274 shader->prolog =
7275 si_get_shader_part(sscreen, &sscreen->vs_prologs,
7276 PIPE_SHADER_VERTEX, true, &prolog_key, tm,
7277 debug, si_build_vs_prolog_function,
7278 "Vertex Shader Prolog");
7279 return shader->prolog != NULL;
7280 }
7281
7282 /**
7283 * Select and compile (or reuse) vertex shader parts (prolog & epilog).
7284 */
7285 static bool si_shader_select_vs_parts(struct si_screen *sscreen,
7286 LLVMTargetMachineRef tm,
7287 struct si_shader *shader,
7288 struct pipe_debug_callback *debug)
7289 {
7290 return si_get_vs_prolog(sscreen, tm, shader, debug, shader,
7291 &shader->key.part.vs.prolog);
7292 }
7293
7294 /**
7295 * Compile the TCS epilog function. This writes tesselation factors to memory
7296 * based on the output primitive type of the tesselator (determined by TES).
7297 */
7298 static void si_build_tcs_epilog_function(struct si_shader_context *ctx,
7299 union si_shader_part_key *key)
7300 {
7301 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
7302 struct si_function_info fninfo;
7303 LLVMValueRef func;
7304
7305 si_init_function_info(&fninfo);
7306
7307 if (ctx->screen->info.chip_class >= GFX9) {
7308 add_arg(&fninfo, ARG_SGPR, ctx->i64);
7309 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7310 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* wave info */
7311 ctx->param_tcs_factor_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7312 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7313 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7314 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7315 add_arg(&fninfo, ARG_SGPR, ctx->i64);
7316 add_arg(&fninfo, ARG_SGPR, ctx->i64);
7317 add_arg(&fninfo, ARG_SGPR, ctx->i64);
7318 add_arg(&fninfo, ARG_SGPR, ctx->i64);
7319 add_arg(&fninfo, ARG_SGPR, ctx->i64);
7320 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7321 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7322 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7323 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7324 ctx->param_tcs_offchip_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7325 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7326 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7327 ctx->param_tcs_offchip_addr_base64k = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7328 ctx->param_tcs_factor_addr_base64k = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7329 } else {
7330 add_arg(&fninfo, ARG_SGPR, ctx->i64);
7331 add_arg(&fninfo, ARG_SGPR, ctx->i64);
7332 add_arg(&fninfo, ARG_SGPR, ctx->i64);
7333 add_arg(&fninfo, ARG_SGPR, ctx->i64);
7334 ctx->param_tcs_offchip_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7335 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7336 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7337 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7338 ctx->param_tcs_offchip_addr_base64k = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7339 ctx->param_tcs_factor_addr_base64k = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7340 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7341 ctx->param_tcs_factor_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7342 }
7343
7344 add_arg(&fninfo, ARG_VGPR, ctx->i32); /* VGPR gap */
7345 add_arg(&fninfo, ARG_VGPR, ctx->i32); /* VGPR gap */
7346 unsigned tess_factors_idx =
7347 add_arg(&fninfo, ARG_VGPR, ctx->i32); /* patch index within the wave (REL_PATCH_ID) */
7348 add_arg(&fninfo, ARG_VGPR, ctx->i32); /* invocation ID within the patch */
7349 add_arg(&fninfo, ARG_VGPR, ctx->i32); /* LDS offset where tess factors should be loaded from */
7350
7351 for (unsigned i = 0; i < 6; i++)
7352 add_arg(&fninfo, ARG_VGPR, ctx->i32); /* tess factors */
7353
7354 /* Create the function. */
7355 si_create_function(ctx, "tcs_epilog", NULL, 0, &fninfo,
7356 ctx->screen->info.chip_class >= CIK ? 128 : 64);
7357 ac_declare_lds_as_pointer(&ctx->ac);
7358 func = ctx->main_fn;
7359
7360 LLVMValueRef invoc0_tess_factors[6];
7361 for (unsigned i = 0; i < 6; i++)
7362 invoc0_tess_factors[i] = LLVMGetParam(func, tess_factors_idx + 3 + i);
7363
7364 si_write_tess_factors(bld_base,
7365 LLVMGetParam(func, tess_factors_idx),
7366 LLVMGetParam(func, tess_factors_idx + 1),
7367 LLVMGetParam(func, tess_factors_idx + 2),
7368 invoc0_tess_factors, invoc0_tess_factors + 4);
7369
7370 LLVMBuildRetVoid(ctx->ac.builder);
7371 }
7372
7373 /**
7374 * Select and compile (or reuse) TCS parts (epilog).
7375 */
7376 static bool si_shader_select_tcs_parts(struct si_screen *sscreen,
7377 LLVMTargetMachineRef tm,
7378 struct si_shader *shader,
7379 struct pipe_debug_callback *debug)
7380 {
7381 if (sscreen->info.chip_class >= GFX9) {
7382 struct si_shader *ls_main_part =
7383 shader->key.part.tcs.ls->main_shader_part_ls;
7384
7385 if (!si_get_vs_prolog(sscreen, tm, shader, debug, ls_main_part,
7386 &shader->key.part.tcs.ls_prolog))
7387 return false;
7388
7389 shader->previous_stage = ls_main_part;
7390 }
7391
7392 /* Get the epilog. */
7393 union si_shader_part_key epilog_key;
7394 memset(&epilog_key, 0, sizeof(epilog_key));
7395 epilog_key.tcs_epilog.states = shader->key.part.tcs.epilog;
7396
7397 shader->epilog = si_get_shader_part(sscreen, &sscreen->tcs_epilogs,
7398 PIPE_SHADER_TESS_CTRL, false,
7399 &epilog_key, tm, debug,
7400 si_build_tcs_epilog_function,
7401 "Tessellation Control Shader Epilog");
7402 return shader->epilog != NULL;
7403 }
7404
7405 /**
7406 * Select and compile (or reuse) GS parts (prolog).
7407 */
7408 static bool si_shader_select_gs_parts(struct si_screen *sscreen,
7409 LLVMTargetMachineRef tm,
7410 struct si_shader *shader,
7411 struct pipe_debug_callback *debug)
7412 {
7413 if (sscreen->info.chip_class >= GFX9) {
7414 struct si_shader *es_main_part =
7415 shader->key.part.gs.es->main_shader_part_es;
7416
7417 if (shader->key.part.gs.es->type == PIPE_SHADER_VERTEX &&
7418 !si_get_vs_prolog(sscreen, tm, shader, debug, es_main_part,
7419 &shader->key.part.gs.vs_prolog))
7420 return false;
7421
7422 shader->previous_stage = es_main_part;
7423 }
7424
7425 if (!shader->key.part.gs.prolog.tri_strip_adj_fix)
7426 return true;
7427
7428 union si_shader_part_key prolog_key;
7429 memset(&prolog_key, 0, sizeof(prolog_key));
7430 prolog_key.gs_prolog.states = shader->key.part.gs.prolog;
7431
7432 shader->prolog2 = si_get_shader_part(sscreen, &sscreen->gs_prologs,
7433 PIPE_SHADER_GEOMETRY, true,
7434 &prolog_key, tm, debug,
7435 si_build_gs_prolog_function,
7436 "Geometry Shader Prolog");
7437 return shader->prolog2 != NULL;
7438 }
7439
7440 /**
7441 * Build the pixel shader prolog function. This handles:
7442 * - two-side color selection and interpolation
7443 * - overriding interpolation parameters for the API PS
7444 * - polygon stippling
7445 *
7446 * All preloaded SGPRs and VGPRs are passed through unmodified unless they are
7447 * overriden by other states. (e.g. per-sample interpolation)
7448 * Interpolated colors are stored after the preloaded VGPRs.
7449 */
7450 static void si_build_ps_prolog_function(struct si_shader_context *ctx,
7451 union si_shader_part_key *key)
7452 {
7453 struct si_function_info fninfo;
7454 LLVMValueRef ret, func;
7455 int num_returns, i, num_color_channels;
7456
7457 assert(si_need_ps_prolog(key));
7458
7459 si_init_function_info(&fninfo);
7460
7461 /* Declare inputs. */
7462 for (i = 0; i < key->ps_prolog.num_input_sgprs; i++)
7463 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7464
7465 for (i = 0; i < key->ps_prolog.num_input_vgprs; i++)
7466 add_arg(&fninfo, ARG_VGPR, ctx->f32);
7467
7468 /* Declare outputs (same as inputs + add colors if needed) */
7469 num_returns = fninfo.num_params;
7470 num_color_channels = util_bitcount(key->ps_prolog.colors_read);
7471 for (i = 0; i < num_color_channels; i++)
7472 fninfo.types[num_returns++] = ctx->f32;
7473
7474 /* Create the function. */
7475 si_create_function(ctx, "ps_prolog", fninfo.types, num_returns,
7476 &fninfo, 0);
7477 func = ctx->main_fn;
7478
7479 /* Copy inputs to outputs. This should be no-op, as the registers match,
7480 * but it will prevent the compiler from overwriting them unintentionally.
7481 */
7482 ret = ctx->return_value;
7483 for (i = 0; i < fninfo.num_params; i++) {
7484 LLVMValueRef p = LLVMGetParam(func, i);
7485 ret = LLVMBuildInsertValue(ctx->ac.builder, ret, p, i, "");
7486 }
7487
7488 /* Polygon stippling. */
7489 if (key->ps_prolog.states.poly_stipple) {
7490 /* POS_FIXED_PT is always last. */
7491 unsigned pos = key->ps_prolog.num_input_sgprs +
7492 key->ps_prolog.num_input_vgprs - 1;
7493 LLVMValueRef list = si_prolog_get_rw_buffers(ctx);
7494
7495 si_llvm_emit_polygon_stipple(ctx, list, pos);
7496 }
7497
7498 if (key->ps_prolog.states.bc_optimize_for_persp ||
7499 key->ps_prolog.states.bc_optimize_for_linear) {
7500 unsigned i, base = key->ps_prolog.num_input_sgprs;
7501 LLVMValueRef center[2], centroid[2], tmp, bc_optimize;
7502
7503 /* The shader should do: if (PRIM_MASK[31]) CENTROID = CENTER;
7504 * The hw doesn't compute CENTROID if the whole wave only
7505 * contains fully-covered quads.
7506 *
7507 * PRIM_MASK is after user SGPRs.
7508 */
7509 bc_optimize = LLVMGetParam(func, SI_PS_NUM_USER_SGPR);
7510 bc_optimize = LLVMBuildLShr(ctx->ac.builder, bc_optimize,
7511 LLVMConstInt(ctx->i32, 31, 0), "");
7512 bc_optimize = LLVMBuildTrunc(ctx->ac.builder, bc_optimize,
7513 ctx->i1, "");
7514
7515 if (key->ps_prolog.states.bc_optimize_for_persp) {
7516 /* Read PERSP_CENTER. */
7517 for (i = 0; i < 2; i++)
7518 center[i] = LLVMGetParam(func, base + 2 + i);
7519 /* Read PERSP_CENTROID. */
7520 for (i = 0; i < 2; i++)
7521 centroid[i] = LLVMGetParam(func, base + 4 + i);
7522 /* Select PERSP_CENTROID. */
7523 for (i = 0; i < 2; i++) {
7524 tmp = LLVMBuildSelect(ctx->ac.builder, bc_optimize,
7525 center[i], centroid[i], "");
7526 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7527 tmp, base + 4 + i, "");
7528 }
7529 }
7530 if (key->ps_prolog.states.bc_optimize_for_linear) {
7531 /* Read LINEAR_CENTER. */
7532 for (i = 0; i < 2; i++)
7533 center[i] = LLVMGetParam(func, base + 8 + i);
7534 /* Read LINEAR_CENTROID. */
7535 for (i = 0; i < 2; i++)
7536 centroid[i] = LLVMGetParam(func, base + 10 + i);
7537 /* Select LINEAR_CENTROID. */
7538 for (i = 0; i < 2; i++) {
7539 tmp = LLVMBuildSelect(ctx->ac.builder, bc_optimize,
7540 center[i], centroid[i], "");
7541 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7542 tmp, base + 10 + i, "");
7543 }
7544 }
7545 }
7546
7547 /* Force per-sample interpolation. */
7548 if (key->ps_prolog.states.force_persp_sample_interp) {
7549 unsigned i, base = key->ps_prolog.num_input_sgprs;
7550 LLVMValueRef persp_sample[2];
7551
7552 /* Read PERSP_SAMPLE. */
7553 for (i = 0; i < 2; i++)
7554 persp_sample[i] = LLVMGetParam(func, base + i);
7555 /* Overwrite PERSP_CENTER. */
7556 for (i = 0; i < 2; i++)
7557 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7558 persp_sample[i], base + 2 + i, "");
7559 /* Overwrite PERSP_CENTROID. */
7560 for (i = 0; i < 2; i++)
7561 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7562 persp_sample[i], base + 4 + i, "");
7563 }
7564 if (key->ps_prolog.states.force_linear_sample_interp) {
7565 unsigned i, base = key->ps_prolog.num_input_sgprs;
7566 LLVMValueRef linear_sample[2];
7567
7568 /* Read LINEAR_SAMPLE. */
7569 for (i = 0; i < 2; i++)
7570 linear_sample[i] = LLVMGetParam(func, base + 6 + i);
7571 /* Overwrite LINEAR_CENTER. */
7572 for (i = 0; i < 2; i++)
7573 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7574 linear_sample[i], base + 8 + i, "");
7575 /* Overwrite LINEAR_CENTROID. */
7576 for (i = 0; i < 2; i++)
7577 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7578 linear_sample[i], base + 10 + i, "");
7579 }
7580
7581 /* Force center interpolation. */
7582 if (key->ps_prolog.states.force_persp_center_interp) {
7583 unsigned i, base = key->ps_prolog.num_input_sgprs;
7584 LLVMValueRef persp_center[2];
7585
7586 /* Read PERSP_CENTER. */
7587 for (i = 0; i < 2; i++)
7588 persp_center[i] = LLVMGetParam(func, base + 2 + i);
7589 /* Overwrite PERSP_SAMPLE. */
7590 for (i = 0; i < 2; i++)
7591 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7592 persp_center[i], base + i, "");
7593 /* Overwrite PERSP_CENTROID. */
7594 for (i = 0; i < 2; i++)
7595 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7596 persp_center[i], base + 4 + i, "");
7597 }
7598 if (key->ps_prolog.states.force_linear_center_interp) {
7599 unsigned i, base = key->ps_prolog.num_input_sgprs;
7600 LLVMValueRef linear_center[2];
7601
7602 /* Read LINEAR_CENTER. */
7603 for (i = 0; i < 2; i++)
7604 linear_center[i] = LLVMGetParam(func, base + 8 + i);
7605 /* Overwrite LINEAR_SAMPLE. */
7606 for (i = 0; i < 2; i++)
7607 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7608 linear_center[i], base + 6 + i, "");
7609 /* Overwrite LINEAR_CENTROID. */
7610 for (i = 0; i < 2; i++)
7611 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7612 linear_center[i], base + 10 + i, "");
7613 }
7614
7615 /* Interpolate colors. */
7616 unsigned color_out_idx = 0;
7617 for (i = 0; i < 2; i++) {
7618 unsigned writemask = (key->ps_prolog.colors_read >> (i * 4)) & 0xf;
7619 unsigned face_vgpr = key->ps_prolog.num_input_sgprs +
7620 key->ps_prolog.face_vgpr_index;
7621 LLVMValueRef interp[2], color[4];
7622 LLVMValueRef interp_ij = NULL, prim_mask = NULL, face = NULL;
7623
7624 if (!writemask)
7625 continue;
7626
7627 /* If the interpolation qualifier is not CONSTANT (-1). */
7628 if (key->ps_prolog.color_interp_vgpr_index[i] != -1) {
7629 unsigned interp_vgpr = key->ps_prolog.num_input_sgprs +
7630 key->ps_prolog.color_interp_vgpr_index[i];
7631
7632 /* Get the (i,j) updated by bc_optimize handling. */
7633 interp[0] = LLVMBuildExtractValue(ctx->ac.builder, ret,
7634 interp_vgpr, "");
7635 interp[1] = LLVMBuildExtractValue(ctx->ac.builder, ret,
7636 interp_vgpr + 1, "");
7637 interp_ij = lp_build_gather_values(&ctx->gallivm, interp, 2);
7638 }
7639
7640 /* Use the absolute location of the input. */
7641 prim_mask = LLVMGetParam(func, SI_PS_NUM_USER_SGPR);
7642
7643 if (key->ps_prolog.states.color_two_side) {
7644 face = LLVMGetParam(func, face_vgpr);
7645 face = ac_to_integer(&ctx->ac, face);
7646 }
7647
7648 interp_fs_input(ctx,
7649 key->ps_prolog.color_attr_index[i],
7650 TGSI_SEMANTIC_COLOR, i,
7651 key->ps_prolog.num_interp_inputs,
7652 key->ps_prolog.colors_read, interp_ij,
7653 prim_mask, face, color);
7654
7655 while (writemask) {
7656 unsigned chan = u_bit_scan(&writemask);
7657 ret = LLVMBuildInsertValue(ctx->ac.builder, ret, color[chan],
7658 fninfo.num_params + color_out_idx++, "");
7659 }
7660 }
7661
7662 /* Section 15.2.2 (Shader Inputs) of the OpenGL 4.5 (Core Profile) spec
7663 * says:
7664 *
7665 * "When per-sample shading is active due to the use of a fragment
7666 * input qualified by sample or due to the use of the gl_SampleID
7667 * or gl_SamplePosition variables, only the bit for the current
7668 * sample is set in gl_SampleMaskIn. When state specifies multiple
7669 * fragment shader invocations for a given fragment, the sample
7670 * mask for any single fragment shader invocation may specify a
7671 * subset of the covered samples for the fragment. In this case,
7672 * the bit corresponding to each covered sample will be set in
7673 * exactly one fragment shader invocation."
7674 *
7675 * The samplemask loaded by hardware is always the coverage of the
7676 * entire pixel/fragment, so mask bits out based on the sample ID.
7677 */
7678 if (key->ps_prolog.states.samplemask_log_ps_iter) {
7679 /* The bit pattern matches that used by fixed function fragment
7680 * processing. */
7681 static const uint16_t ps_iter_masks[] = {
7682 0xffff, /* not used */
7683 0x5555,
7684 0x1111,
7685 0x0101,
7686 0x0001,
7687 };
7688 assert(key->ps_prolog.states.samplemask_log_ps_iter < ARRAY_SIZE(ps_iter_masks));
7689
7690 uint32_t ps_iter_mask = ps_iter_masks[key->ps_prolog.states.samplemask_log_ps_iter];
7691 unsigned ancillary_vgpr = key->ps_prolog.num_input_sgprs +
7692 key->ps_prolog.ancillary_vgpr_index;
7693 LLVMValueRef sampleid = unpack_param(ctx, ancillary_vgpr, 8, 4);
7694 LLVMValueRef samplemask = LLVMGetParam(func, ancillary_vgpr + 1);
7695
7696 samplemask = ac_to_integer(&ctx->ac, samplemask);
7697 samplemask = LLVMBuildAnd(
7698 ctx->ac.builder,
7699 samplemask,
7700 LLVMBuildShl(ctx->ac.builder,
7701 LLVMConstInt(ctx->i32, ps_iter_mask, false),
7702 sampleid, ""),
7703 "");
7704 samplemask = ac_to_float(&ctx->ac, samplemask);
7705
7706 ret = LLVMBuildInsertValue(ctx->ac.builder, ret, samplemask,
7707 ancillary_vgpr + 1, "");
7708 }
7709
7710 /* Tell LLVM to insert WQM instruction sequence when needed. */
7711 if (key->ps_prolog.wqm) {
7712 LLVMAddTargetDependentFunctionAttr(func,
7713 "amdgpu-ps-wqm-outputs", "");
7714 }
7715
7716 si_llvm_build_ret(ctx, ret);
7717 }
7718
7719 /**
7720 * Build the pixel shader epilog function. This handles everything that must be
7721 * emulated for pixel shader exports. (alpha-test, format conversions, etc)
7722 */
7723 static void si_build_ps_epilog_function(struct si_shader_context *ctx,
7724 union si_shader_part_key *key)
7725 {
7726 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
7727 struct si_function_info fninfo;
7728 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
7729 int i;
7730 struct si_ps_exports exp = {};
7731
7732 si_init_function_info(&fninfo);
7733
7734 /* Declare input SGPRs. */
7735 ctx->param_rw_buffers = add_arg(&fninfo, ARG_SGPR, ctx->i64);
7736 ctx->param_bindless_samplers_and_images = add_arg(&fninfo, ARG_SGPR, ctx->i64);
7737 ctx->param_const_and_shader_buffers = add_arg(&fninfo, ARG_SGPR, ctx->i64);
7738 ctx->param_samplers_and_images = add_arg(&fninfo, ARG_SGPR, ctx->i64);
7739 add_arg_checked(&fninfo, ARG_SGPR, ctx->f32, SI_PARAM_ALPHA_REF);
7740
7741 /* Declare input VGPRs. */
7742 unsigned required_num_params =
7743 fninfo.num_sgpr_params +
7744 util_bitcount(key->ps_epilog.colors_written) * 4 +
7745 key->ps_epilog.writes_z +
7746 key->ps_epilog.writes_stencil +
7747 key->ps_epilog.writes_samplemask;
7748
7749 required_num_params = MAX2(required_num_params,
7750 fninfo.num_sgpr_params + PS_EPILOG_SAMPLEMASK_MIN_LOC + 1);
7751
7752 while (fninfo.num_params < required_num_params)
7753 add_arg(&fninfo, ARG_VGPR, ctx->f32);
7754
7755 /* Create the function. */
7756 si_create_function(ctx, "ps_epilog", NULL, 0, &fninfo, 0);
7757 /* Disable elimination of unused inputs. */
7758 si_llvm_add_attribute(ctx->main_fn,
7759 "InitialPSInputAddr", 0xffffff);
7760
7761 /* Process colors. */
7762 unsigned vgpr = fninfo.num_sgpr_params;
7763 unsigned colors_written = key->ps_epilog.colors_written;
7764 int last_color_export = -1;
7765
7766 /* Find the last color export. */
7767 if (!key->ps_epilog.writes_z &&
7768 !key->ps_epilog.writes_stencil &&
7769 !key->ps_epilog.writes_samplemask) {
7770 unsigned spi_format = key->ps_epilog.states.spi_shader_col_format;
7771
7772 /* If last_cbuf > 0, FS_COLOR0_WRITES_ALL_CBUFS is true. */
7773 if (colors_written == 0x1 && key->ps_epilog.states.last_cbuf > 0) {
7774 /* Just set this if any of the colorbuffers are enabled. */
7775 if (spi_format &
7776 ((1ull << (4 * (key->ps_epilog.states.last_cbuf + 1))) - 1))
7777 last_color_export = 0;
7778 } else {
7779 for (i = 0; i < 8; i++)
7780 if (colors_written & (1 << i) &&
7781 (spi_format >> (i * 4)) & 0xf)
7782 last_color_export = i;
7783 }
7784 }
7785
7786 while (colors_written) {
7787 LLVMValueRef color[4];
7788 int mrt = u_bit_scan(&colors_written);
7789
7790 for (i = 0; i < 4; i++)
7791 color[i] = LLVMGetParam(ctx->main_fn, vgpr++);
7792
7793 si_export_mrt_color(bld_base, color, mrt,
7794 fninfo.num_params - 1,
7795 mrt == last_color_export, &exp);
7796 }
7797
7798 /* Process depth, stencil, samplemask. */
7799 if (key->ps_epilog.writes_z)
7800 depth = LLVMGetParam(ctx->main_fn, vgpr++);
7801 if (key->ps_epilog.writes_stencil)
7802 stencil = LLVMGetParam(ctx->main_fn, vgpr++);
7803 if (key->ps_epilog.writes_samplemask)
7804 samplemask = LLVMGetParam(ctx->main_fn, vgpr++);
7805
7806 if (depth || stencil || samplemask)
7807 si_export_mrt_z(bld_base, depth, stencil, samplemask, &exp);
7808 else if (last_color_export == -1)
7809 si_export_null(bld_base);
7810
7811 if (exp.num)
7812 si_emit_ps_exports(ctx, &exp);
7813
7814 /* Compile. */
7815 LLVMBuildRetVoid(ctx->ac.builder);
7816 }
7817
7818 /**
7819 * Select and compile (or reuse) pixel shader parts (prolog & epilog).
7820 */
7821 static bool si_shader_select_ps_parts(struct si_screen *sscreen,
7822 LLVMTargetMachineRef tm,
7823 struct si_shader *shader,
7824 struct pipe_debug_callback *debug)
7825 {
7826 union si_shader_part_key prolog_key;
7827 union si_shader_part_key epilog_key;
7828
7829 /* Get the prolog. */
7830 si_get_ps_prolog_key(shader, &prolog_key, true);
7831
7832 /* The prolog is a no-op if these aren't set. */
7833 if (si_need_ps_prolog(&prolog_key)) {
7834 shader->prolog =
7835 si_get_shader_part(sscreen, &sscreen->ps_prologs,
7836 PIPE_SHADER_FRAGMENT, true,
7837 &prolog_key, tm, debug,
7838 si_build_ps_prolog_function,
7839 "Fragment Shader Prolog");
7840 if (!shader->prolog)
7841 return false;
7842 }
7843
7844 /* Get the epilog. */
7845 si_get_ps_epilog_key(shader, &epilog_key);
7846
7847 shader->epilog =
7848 si_get_shader_part(sscreen, &sscreen->ps_epilogs,
7849 PIPE_SHADER_FRAGMENT, false,
7850 &epilog_key, tm, debug,
7851 si_build_ps_epilog_function,
7852 "Fragment Shader Epilog");
7853 if (!shader->epilog)
7854 return false;
7855
7856 /* Enable POS_FIXED_PT if polygon stippling is enabled. */
7857 if (shader->key.part.ps.prolog.poly_stipple) {
7858 shader->config.spi_ps_input_ena |= S_0286CC_POS_FIXED_PT_ENA(1);
7859 assert(G_0286CC_POS_FIXED_PT_ENA(shader->config.spi_ps_input_addr));
7860 }
7861
7862 /* Set up the enable bits for per-sample shading if needed. */
7863 if (shader->key.part.ps.prolog.force_persp_sample_interp &&
7864 (G_0286CC_PERSP_CENTER_ENA(shader->config.spi_ps_input_ena) ||
7865 G_0286CC_PERSP_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
7866 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_CENTER_ENA;
7867 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_CENTROID_ENA;
7868 shader->config.spi_ps_input_ena |= S_0286CC_PERSP_SAMPLE_ENA(1);
7869 }
7870 if (shader->key.part.ps.prolog.force_linear_sample_interp &&
7871 (G_0286CC_LINEAR_CENTER_ENA(shader->config.spi_ps_input_ena) ||
7872 G_0286CC_LINEAR_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
7873 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_CENTER_ENA;
7874 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_CENTROID_ENA;
7875 shader->config.spi_ps_input_ena |= S_0286CC_LINEAR_SAMPLE_ENA(1);
7876 }
7877 if (shader->key.part.ps.prolog.force_persp_center_interp &&
7878 (G_0286CC_PERSP_SAMPLE_ENA(shader->config.spi_ps_input_ena) ||
7879 G_0286CC_PERSP_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
7880 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_SAMPLE_ENA;
7881 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_CENTROID_ENA;
7882 shader->config.spi_ps_input_ena |= S_0286CC_PERSP_CENTER_ENA(1);
7883 }
7884 if (shader->key.part.ps.prolog.force_linear_center_interp &&
7885 (G_0286CC_LINEAR_SAMPLE_ENA(shader->config.spi_ps_input_ena) ||
7886 G_0286CC_LINEAR_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
7887 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_SAMPLE_ENA;
7888 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_CENTROID_ENA;
7889 shader->config.spi_ps_input_ena |= S_0286CC_LINEAR_CENTER_ENA(1);
7890 }
7891
7892 /* POW_W_FLOAT requires that one of the perspective weights is enabled. */
7893 if (G_0286CC_POS_W_FLOAT_ENA(shader->config.spi_ps_input_ena) &&
7894 !(shader->config.spi_ps_input_ena & 0xf)) {
7895 shader->config.spi_ps_input_ena |= S_0286CC_PERSP_CENTER_ENA(1);
7896 assert(G_0286CC_PERSP_CENTER_ENA(shader->config.spi_ps_input_addr));
7897 }
7898
7899 /* At least one pair of interpolation weights must be enabled. */
7900 if (!(shader->config.spi_ps_input_ena & 0x7f)) {
7901 shader->config.spi_ps_input_ena |= S_0286CC_LINEAR_CENTER_ENA(1);
7902 assert(G_0286CC_LINEAR_CENTER_ENA(shader->config.spi_ps_input_addr));
7903 }
7904
7905 /* Samplemask fixup requires the sample ID. */
7906 if (shader->key.part.ps.prolog.samplemask_log_ps_iter) {
7907 shader->config.spi_ps_input_ena |= S_0286CC_ANCILLARY_ENA(1);
7908 assert(G_0286CC_ANCILLARY_ENA(shader->config.spi_ps_input_addr));
7909 }
7910
7911 /* The sample mask input is always enabled, because the API shader always
7912 * passes it through to the epilog. Disable it here if it's unused.
7913 */
7914 if (!shader->key.part.ps.epilog.poly_line_smoothing &&
7915 !shader->selector->info.reads_samplemask)
7916 shader->config.spi_ps_input_ena &= C_0286CC_SAMPLE_COVERAGE_ENA;
7917
7918 return true;
7919 }
7920
7921 void si_multiwave_lds_size_workaround(struct si_screen *sscreen,
7922 unsigned *lds_size)
7923 {
7924 /* SPI barrier management bug:
7925 * Make sure we have at least 4k of LDS in use to avoid the bug.
7926 * It applies to workgroup sizes of more than one wavefront.
7927 */
7928 if (sscreen->info.family == CHIP_BONAIRE ||
7929 sscreen->info.family == CHIP_KABINI ||
7930 sscreen->info.family == CHIP_MULLINS)
7931 *lds_size = MAX2(*lds_size, 8);
7932 }
7933
7934 static void si_fix_resource_usage(struct si_screen *sscreen,
7935 struct si_shader *shader)
7936 {
7937 unsigned min_sgprs = shader->info.num_input_sgprs + 2; /* VCC */
7938
7939 shader->config.num_sgprs = MAX2(shader->config.num_sgprs, min_sgprs);
7940
7941 if (shader->selector->type == PIPE_SHADER_COMPUTE &&
7942 si_get_max_workgroup_size(shader) > 64) {
7943 si_multiwave_lds_size_workaround(sscreen,
7944 &shader->config.lds_size);
7945 }
7946 }
7947
7948 int si_shader_create(struct si_screen *sscreen, LLVMTargetMachineRef tm,
7949 struct si_shader *shader,
7950 struct pipe_debug_callback *debug)
7951 {
7952 struct si_shader_selector *sel = shader->selector;
7953 struct si_shader *mainp = *si_get_main_shader_part(sel, &shader->key);
7954 int r;
7955
7956 /* LS, ES, VS are compiled on demand if the main part hasn't been
7957 * compiled for that stage.
7958 *
7959 * Vertex shaders are compiled on demand when a vertex fetch
7960 * workaround must be applied.
7961 */
7962 if (shader->is_monolithic) {
7963 /* Monolithic shader (compiled as a whole, has many variants,
7964 * may take a long time to compile).
7965 */
7966 r = si_compile_tgsi_shader(sscreen, tm, shader, true, debug);
7967 if (r)
7968 return r;
7969 } else {
7970 /* The shader consists of several parts:
7971 *
7972 * - the middle part is the user shader, it has 1 variant only
7973 * and it was compiled during the creation of the shader
7974 * selector
7975 * - the prolog part is inserted at the beginning
7976 * - the epilog part is inserted at the end
7977 *
7978 * The prolog and epilog have many (but simple) variants.
7979 *
7980 * Starting with gfx9, geometry and tessellation control
7981 * shaders also contain the prolog and user shader parts of
7982 * the previous shader stage.
7983 */
7984
7985 if (!mainp)
7986 return -1;
7987
7988 /* Copy the compiled TGSI shader data over. */
7989 shader->is_binary_shared = true;
7990 shader->binary = mainp->binary;
7991 shader->config = mainp->config;
7992 shader->info.num_input_sgprs = mainp->info.num_input_sgprs;
7993 shader->info.num_input_vgprs = mainp->info.num_input_vgprs;
7994 shader->info.face_vgpr_index = mainp->info.face_vgpr_index;
7995 shader->info.ancillary_vgpr_index = mainp->info.ancillary_vgpr_index;
7996 memcpy(shader->info.vs_output_param_offset,
7997 mainp->info.vs_output_param_offset,
7998 sizeof(mainp->info.vs_output_param_offset));
7999 shader->info.uses_instanceid = mainp->info.uses_instanceid;
8000 shader->info.nr_pos_exports = mainp->info.nr_pos_exports;
8001 shader->info.nr_param_exports = mainp->info.nr_param_exports;
8002
8003 /* Select prologs and/or epilogs. */
8004 switch (sel->type) {
8005 case PIPE_SHADER_VERTEX:
8006 if (!si_shader_select_vs_parts(sscreen, tm, shader, debug))
8007 return -1;
8008 break;
8009 case PIPE_SHADER_TESS_CTRL:
8010 if (!si_shader_select_tcs_parts(sscreen, tm, shader, debug))
8011 return -1;
8012 break;
8013 case PIPE_SHADER_TESS_EVAL:
8014 break;
8015 case PIPE_SHADER_GEOMETRY:
8016 if (!si_shader_select_gs_parts(sscreen, tm, shader, debug))
8017 return -1;
8018 break;
8019 case PIPE_SHADER_FRAGMENT:
8020 if (!si_shader_select_ps_parts(sscreen, tm, shader, debug))
8021 return -1;
8022
8023 /* Make sure we have at least as many VGPRs as there
8024 * are allocated inputs.
8025 */
8026 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
8027 shader->info.num_input_vgprs);
8028 break;
8029 }
8030
8031 /* Update SGPR and VGPR counts. */
8032 if (shader->prolog) {
8033 shader->config.num_sgprs = MAX2(shader->config.num_sgprs,
8034 shader->prolog->config.num_sgprs);
8035 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
8036 shader->prolog->config.num_vgprs);
8037 }
8038 if (shader->previous_stage) {
8039 shader->config.num_sgprs = MAX2(shader->config.num_sgprs,
8040 shader->previous_stage->config.num_sgprs);
8041 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
8042 shader->previous_stage->config.num_vgprs);
8043 shader->config.spilled_sgprs =
8044 MAX2(shader->config.spilled_sgprs,
8045 shader->previous_stage->config.spilled_sgprs);
8046 shader->config.spilled_vgprs =
8047 MAX2(shader->config.spilled_vgprs,
8048 shader->previous_stage->config.spilled_vgprs);
8049 shader->config.private_mem_vgprs =
8050 MAX2(shader->config.private_mem_vgprs,
8051 shader->previous_stage->config.private_mem_vgprs);
8052 shader->config.scratch_bytes_per_wave =
8053 MAX2(shader->config.scratch_bytes_per_wave,
8054 shader->previous_stage->config.scratch_bytes_per_wave);
8055 shader->info.uses_instanceid |=
8056 shader->previous_stage->info.uses_instanceid;
8057 }
8058 if (shader->prolog2) {
8059 shader->config.num_sgprs = MAX2(shader->config.num_sgprs,
8060 shader->prolog2->config.num_sgprs);
8061 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
8062 shader->prolog2->config.num_vgprs);
8063 }
8064 if (shader->epilog) {
8065 shader->config.num_sgprs = MAX2(shader->config.num_sgprs,
8066 shader->epilog->config.num_sgprs);
8067 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
8068 shader->epilog->config.num_vgprs);
8069 }
8070 si_calculate_max_simd_waves(shader);
8071 }
8072
8073 si_fix_resource_usage(sscreen, shader);
8074 si_shader_dump(sscreen, shader, debug, sel->info.processor,
8075 stderr, true);
8076
8077 /* Upload. */
8078 r = si_shader_binary_upload(sscreen, shader);
8079 if (r) {
8080 fprintf(stderr, "LLVM failed to upload shader\n");
8081 return r;
8082 }
8083
8084 return 0;
8085 }
8086
8087 void si_shader_destroy(struct si_shader *shader)
8088 {
8089 if (shader->scratch_bo)
8090 r600_resource_reference(&shader->scratch_bo, NULL);
8091
8092 r600_resource_reference(&shader->bo, NULL);
8093
8094 if (!shader->is_binary_shared)
8095 ac_shader_binary_clean(&shader->binary);
8096
8097 free(shader->shader_log);
8098 }