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radeonsi/nir: load FS inputs
[mesa.git] / src / gallium / drivers / radeonsi / si_shader.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Tom Stellard <thomas.stellard@amd.com>
25 * Michel Dänzer <michel.daenzer@amd.com>
26 * Christian König <christian.koenig@amd.com>
27 */
28
29 #include "gallivm/lp_bld_const.h"
30 #include "gallivm/lp_bld_gather.h"
31 #include "gallivm/lp_bld_intr.h"
32 #include "gallivm/lp_bld_logic.h"
33 #include "gallivm/lp_bld_arit.h"
34 #include "gallivm/lp_bld_flow.h"
35 #include "gallivm/lp_bld_misc.h"
36 #include "util/u_memory.h"
37 #include "util/u_string.h"
38 #include "tgsi/tgsi_build.h"
39 #include "tgsi/tgsi_util.h"
40 #include "tgsi/tgsi_dump.h"
41
42 #include "ac_binary.h"
43 #include "ac_llvm_util.h"
44 #include "ac_exp_param.h"
45 #include "si_shader_internal.h"
46 #include "si_pipe.h"
47 #include "sid.h"
48
49 #include "compiler/nir/nir.h"
50
51 static const char *scratch_rsrc_dword0_symbol =
52 "SCRATCH_RSRC_DWORD0";
53
54 static const char *scratch_rsrc_dword1_symbol =
55 "SCRATCH_RSRC_DWORD1";
56
57 struct si_shader_output_values
58 {
59 LLVMValueRef values[4];
60 unsigned semantic_name;
61 unsigned semantic_index;
62 ubyte vertex_stream[4];
63 };
64
65 /**
66 * Used to collect types and other info about arguments of the LLVM function
67 * before the function is created.
68 */
69 struct si_function_info {
70 LLVMTypeRef types[100];
71 LLVMValueRef *assign[100];
72 unsigned num_sgpr_params;
73 unsigned num_params;
74 };
75
76 enum si_arg_regfile {
77 ARG_SGPR,
78 ARG_VGPR
79 };
80
81 static void si_init_shader_ctx(struct si_shader_context *ctx,
82 struct si_screen *sscreen,
83 LLVMTargetMachineRef tm);
84
85 static void si_llvm_emit_barrier(const struct lp_build_tgsi_action *action,
86 struct lp_build_tgsi_context *bld_base,
87 struct lp_build_emit_data *emit_data);
88
89 static void si_dump_shader_key(unsigned processor, const struct si_shader *shader,
90 FILE *f);
91
92 static unsigned llvm_get_type_size(LLVMTypeRef type);
93
94 static void si_build_vs_prolog_function(struct si_shader_context *ctx,
95 union si_shader_part_key *key);
96 static void si_build_tcs_epilog_function(struct si_shader_context *ctx,
97 union si_shader_part_key *key);
98 static void si_build_ps_prolog_function(struct si_shader_context *ctx,
99 union si_shader_part_key *key);
100 static void si_build_ps_epilog_function(struct si_shader_context *ctx,
101 union si_shader_part_key *key);
102
103 /* Ideally pass the sample mask input to the PS epilog as v13, which
104 * is its usual location, so that the shader doesn't have to add v_mov.
105 */
106 #define PS_EPILOG_SAMPLEMASK_MIN_LOC 13
107
108 enum {
109 CONST_ADDR_SPACE = 2,
110 LOCAL_ADDR_SPACE = 3,
111 };
112
113 static bool is_merged_shader(struct si_shader *shader)
114 {
115 if (shader->selector->screen->b.chip_class <= VI)
116 return false;
117
118 return shader->key.as_ls ||
119 shader->key.as_es ||
120 shader->selector->type == PIPE_SHADER_TESS_CTRL ||
121 shader->selector->type == PIPE_SHADER_GEOMETRY;
122 }
123
124 static void si_init_function_info(struct si_function_info *fninfo)
125 {
126 fninfo->num_params = 0;
127 fninfo->num_sgpr_params = 0;
128 }
129
130 static unsigned add_arg_assign(struct si_function_info *fninfo,
131 enum si_arg_regfile regfile, LLVMTypeRef type,
132 LLVMValueRef *assign)
133 {
134 assert(regfile != ARG_SGPR || fninfo->num_sgpr_params == fninfo->num_params);
135
136 unsigned idx = fninfo->num_params++;
137 assert(idx < ARRAY_SIZE(fninfo->types));
138
139 if (regfile == ARG_SGPR)
140 fninfo->num_sgpr_params = fninfo->num_params;
141
142 fninfo->types[idx] = type;
143 fninfo->assign[idx] = assign;
144 return idx;
145 }
146
147 static unsigned add_arg(struct si_function_info *fninfo,
148 enum si_arg_regfile regfile, LLVMTypeRef type)
149 {
150 return add_arg_assign(fninfo, regfile, type, NULL);
151 }
152
153 static void add_arg_checked(struct si_function_info *fninfo,
154 enum si_arg_regfile regfile, LLVMTypeRef type,
155 unsigned idx)
156 {
157 MAYBE_UNUSED unsigned actual = add_arg(fninfo, regfile, type);
158 assert(actual == idx);
159 }
160
161 /**
162 * Returns a unique index for a per-patch semantic name and index. The index
163 * must be less than 32, so that a 32-bit bitmask of used inputs or outputs
164 * can be calculated.
165 */
166 unsigned si_shader_io_get_unique_index_patch(unsigned semantic_name, unsigned index)
167 {
168 switch (semantic_name) {
169 case TGSI_SEMANTIC_TESSOUTER:
170 return 0;
171 case TGSI_SEMANTIC_TESSINNER:
172 return 1;
173 case TGSI_SEMANTIC_PATCH:
174 assert(index < 30);
175 return 2 + index;
176
177 default:
178 assert(!"invalid semantic name");
179 return 0;
180 }
181 }
182
183 /**
184 * Returns a unique index for a semantic name and index. The index must be
185 * less than 64, so that a 64-bit bitmask of used inputs or outputs can be
186 * calculated.
187 */
188 unsigned si_shader_io_get_unique_index(unsigned semantic_name, unsigned index)
189 {
190 switch (semantic_name) {
191 case TGSI_SEMANTIC_POSITION:
192 return 0;
193 case TGSI_SEMANTIC_GENERIC:
194 /* Since some shader stages use the the highest used IO index
195 * to determine the size to allocate for inputs/outputs
196 * (in LDS, tess and GS rings). GENERIC should be placed right
197 * after POSITION to make that size as small as possible.
198 */
199 if (index < SI_MAX_IO_GENERIC)
200 return 1 + index;
201
202 assert(!"invalid generic index");
203 return 0;
204 case TGSI_SEMANTIC_PSIZE:
205 return SI_MAX_IO_GENERIC + 1;
206 case TGSI_SEMANTIC_CLIPDIST:
207 assert(index <= 1);
208 return SI_MAX_IO_GENERIC + 2 + index;
209 case TGSI_SEMANTIC_FOG:
210 return SI_MAX_IO_GENERIC + 4;
211 case TGSI_SEMANTIC_LAYER:
212 return SI_MAX_IO_GENERIC + 5;
213 case TGSI_SEMANTIC_VIEWPORT_INDEX:
214 return SI_MAX_IO_GENERIC + 6;
215 case TGSI_SEMANTIC_PRIMID:
216 return SI_MAX_IO_GENERIC + 7;
217 case TGSI_SEMANTIC_COLOR: /* these alias */
218 case TGSI_SEMANTIC_BCOLOR:
219 assert(index < 2);
220 return SI_MAX_IO_GENERIC + 8 + index;
221 case TGSI_SEMANTIC_TEXCOORD:
222 assert(index < 8);
223 assert(SI_MAX_IO_GENERIC + 10 + index < 64);
224 return SI_MAX_IO_GENERIC + 10 + index;
225 default:
226 assert(!"invalid semantic name");
227 return 0;
228 }
229 }
230
231 /**
232 * Helper function that builds an LLVM IR PHI node and immediately adds
233 * incoming edges.
234 */
235 static LLVMValueRef
236 build_phi(struct ac_llvm_context *ctx, LLVMTypeRef type,
237 unsigned count_incoming, LLVMValueRef *values,
238 LLVMBasicBlockRef *blocks)
239 {
240 LLVMValueRef phi = LLVMBuildPhi(ctx->builder, type, "");
241 LLVMAddIncoming(phi, values, blocks, count_incoming);
242 return phi;
243 }
244
245 /**
246 * Get the value of a shader input parameter and extract a bitfield.
247 */
248 static LLVMValueRef unpack_param(struct si_shader_context *ctx,
249 unsigned param, unsigned rshift,
250 unsigned bitwidth)
251 {
252 struct gallivm_state *gallivm = &ctx->gallivm;
253 LLVMValueRef value = LLVMGetParam(ctx->main_fn,
254 param);
255
256 if (LLVMGetTypeKind(LLVMTypeOf(value)) == LLVMFloatTypeKind)
257 value = bitcast(&ctx->bld_base,
258 TGSI_TYPE_UNSIGNED, value);
259
260 if (rshift)
261 value = LLVMBuildLShr(gallivm->builder, value,
262 LLVMConstInt(ctx->i32, rshift, 0), "");
263
264 if (rshift + bitwidth < 32) {
265 unsigned mask = (1 << bitwidth) - 1;
266 value = LLVMBuildAnd(gallivm->builder, value,
267 LLVMConstInt(ctx->i32, mask, 0), "");
268 }
269
270 return value;
271 }
272
273 static LLVMValueRef get_rel_patch_id(struct si_shader_context *ctx)
274 {
275 switch (ctx->type) {
276 case PIPE_SHADER_TESS_CTRL:
277 return unpack_param(ctx, ctx->param_tcs_rel_ids, 0, 8);
278
279 case PIPE_SHADER_TESS_EVAL:
280 return LLVMGetParam(ctx->main_fn,
281 ctx->param_tes_rel_patch_id);
282
283 default:
284 assert(0);
285 return NULL;
286 }
287 }
288
289 /* Tessellation shaders pass outputs to the next shader using LDS.
290 *
291 * LS outputs = TCS inputs
292 * TCS outputs = TES inputs
293 *
294 * The LDS layout is:
295 * - TCS inputs for patch 0
296 * - TCS inputs for patch 1
297 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
298 * - ...
299 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
300 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
301 * - TCS outputs for patch 1
302 * - Per-patch TCS outputs for patch 1
303 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
304 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
305 * - ...
306 *
307 * All three shaders VS(LS), TCS, TES share the same LDS space.
308 */
309
310 static LLVMValueRef
311 get_tcs_in_patch_stride(struct si_shader_context *ctx)
312 {
313 return unpack_param(ctx, ctx->param_vs_state_bits, 8, 13);
314 }
315
316 static LLVMValueRef
317 get_tcs_out_patch_stride(struct si_shader_context *ctx)
318 {
319 return unpack_param(ctx, ctx->param_tcs_out_lds_layout, 0, 13);
320 }
321
322 static LLVMValueRef
323 get_tcs_out_patch0_offset(struct si_shader_context *ctx)
324 {
325 return lp_build_mul_imm(&ctx->bld_base.uint_bld,
326 unpack_param(ctx,
327 ctx->param_tcs_out_lds_offsets,
328 0, 16),
329 4);
330 }
331
332 static LLVMValueRef
333 get_tcs_out_patch0_patch_data_offset(struct si_shader_context *ctx)
334 {
335 return lp_build_mul_imm(&ctx->bld_base.uint_bld,
336 unpack_param(ctx,
337 ctx->param_tcs_out_lds_offsets,
338 16, 16),
339 4);
340 }
341
342 static LLVMValueRef
343 get_tcs_in_current_patch_offset(struct si_shader_context *ctx)
344 {
345 struct gallivm_state *gallivm = &ctx->gallivm;
346 LLVMValueRef patch_stride = get_tcs_in_patch_stride(ctx);
347 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
348
349 return LLVMBuildMul(gallivm->builder, patch_stride, rel_patch_id, "");
350 }
351
352 static LLVMValueRef
353 get_tcs_out_current_patch_offset(struct si_shader_context *ctx)
354 {
355 struct gallivm_state *gallivm = &ctx->gallivm;
356 LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(ctx);
357 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
358 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
359
360 return LLVMBuildAdd(gallivm->builder, patch0_offset,
361 LLVMBuildMul(gallivm->builder, patch_stride,
362 rel_patch_id, ""),
363 "");
364 }
365
366 static LLVMValueRef
367 get_tcs_out_current_patch_data_offset(struct si_shader_context *ctx)
368 {
369 struct gallivm_state *gallivm = &ctx->gallivm;
370 LLVMValueRef patch0_patch_data_offset =
371 get_tcs_out_patch0_patch_data_offset(ctx);
372 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
373 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
374
375 return LLVMBuildAdd(gallivm->builder, patch0_patch_data_offset,
376 LLVMBuildMul(gallivm->builder, patch_stride,
377 rel_patch_id, ""),
378 "");
379 }
380
381 static LLVMValueRef get_instance_index_for_fetch(
382 struct si_shader_context *ctx,
383 unsigned param_start_instance, LLVMValueRef divisor)
384 {
385 struct gallivm_state *gallivm = &ctx->gallivm;
386
387 LLVMValueRef result = ctx->abi.instance_id;
388
389 /* The division must be done before START_INSTANCE is added. */
390 if (divisor != ctx->i32_1)
391 result = LLVMBuildUDiv(gallivm->builder, result, divisor, "");
392
393 return LLVMBuildAdd(gallivm->builder, result,
394 LLVMGetParam(ctx->main_fn, param_start_instance), "");
395 }
396
397 /* Bitcast <4 x float> to <2 x double>, extract the component, and convert
398 * to float. */
399 static LLVMValueRef extract_double_to_float(struct si_shader_context *ctx,
400 LLVMValueRef vec4,
401 unsigned double_index)
402 {
403 LLVMBuilderRef builder = ctx->gallivm.builder;
404 LLVMTypeRef f64 = LLVMDoubleTypeInContext(ctx->gallivm.context);
405 LLVMValueRef dvec2 = LLVMBuildBitCast(builder, vec4,
406 LLVMVectorType(f64, 2), "");
407 LLVMValueRef index = LLVMConstInt(ctx->i32, double_index, 0);
408 LLVMValueRef value = LLVMBuildExtractElement(builder, dvec2, index, "");
409 return LLVMBuildFPTrunc(builder, value, ctx->f32, "");
410 }
411
412 void si_llvm_load_input_vs(
413 struct si_shader_context *ctx,
414 unsigned input_index,
415 LLVMValueRef out[4])
416 {
417 struct gallivm_state *gallivm = &ctx->gallivm;
418
419 unsigned chan;
420 unsigned fix_fetch;
421 unsigned num_fetches;
422 unsigned fetch_stride;
423
424 LLVMValueRef t_list_ptr;
425 LLVMValueRef t_offset;
426 LLVMValueRef t_list;
427 LLVMValueRef vertex_index;
428 LLVMValueRef input[3];
429
430 /* Load the T list */
431 t_list_ptr = LLVMGetParam(ctx->main_fn, ctx->param_vertex_buffers);
432
433 t_offset = LLVMConstInt(ctx->i32, input_index, 0);
434
435 t_list = ac_build_indexed_load_const(&ctx->ac, t_list_ptr, t_offset);
436
437 vertex_index = LLVMGetParam(ctx->main_fn,
438 ctx->param_vertex_index0 +
439 input_index);
440
441 fix_fetch = ctx->shader->key.mono.vs_fix_fetch[input_index];
442
443 /* Do multiple loads for special formats. */
444 switch (fix_fetch) {
445 case SI_FIX_FETCH_RGB_64_FLOAT:
446 num_fetches = 3; /* 3 2-dword loads */
447 fetch_stride = 8;
448 break;
449 case SI_FIX_FETCH_RGBA_64_FLOAT:
450 num_fetches = 2; /* 2 4-dword loads */
451 fetch_stride = 16;
452 break;
453 case SI_FIX_FETCH_RGB_8:
454 case SI_FIX_FETCH_RGB_8_INT:
455 num_fetches = 3;
456 fetch_stride = 1;
457 break;
458 case SI_FIX_FETCH_RGB_16:
459 case SI_FIX_FETCH_RGB_16_INT:
460 num_fetches = 3;
461 fetch_stride = 2;
462 break;
463 default:
464 num_fetches = 1;
465 fetch_stride = 0;
466 }
467
468 for (unsigned i = 0; i < num_fetches; i++) {
469 LLVMValueRef voffset = LLVMConstInt(ctx->i32, fetch_stride * i, 0);
470
471 input[i] = ac_build_buffer_load_format(&ctx->ac, t_list,
472 vertex_index, voffset,
473 true);
474 }
475
476 /* Break up the vec4 into individual components */
477 for (chan = 0; chan < 4; chan++) {
478 LLVMValueRef llvm_chan = LLVMConstInt(ctx->i32, chan, 0);
479 out[chan] = LLVMBuildExtractElement(gallivm->builder,
480 input[0], llvm_chan, "");
481 }
482
483 switch (fix_fetch) {
484 case SI_FIX_FETCH_A2_SNORM:
485 case SI_FIX_FETCH_A2_SSCALED:
486 case SI_FIX_FETCH_A2_SINT: {
487 /* The hardware returns an unsigned value; convert it to a
488 * signed one.
489 */
490 LLVMValueRef tmp = out[3];
491 LLVMValueRef c30 = LLVMConstInt(ctx->i32, 30, 0);
492
493 /* First, recover the sign-extended signed integer value. */
494 if (fix_fetch == SI_FIX_FETCH_A2_SSCALED)
495 tmp = LLVMBuildFPToUI(gallivm->builder, tmp, ctx->i32, "");
496 else
497 tmp = LLVMBuildBitCast(gallivm->builder, tmp, ctx->i32, "");
498
499 /* For the integer-like cases, do a natural sign extension.
500 *
501 * For the SNORM case, the values are 0.0, 0.333, 0.666, 1.0
502 * and happen to contain 0, 1, 2, 3 as the two LSBs of the
503 * exponent.
504 */
505 tmp = LLVMBuildShl(gallivm->builder, tmp,
506 fix_fetch == SI_FIX_FETCH_A2_SNORM ?
507 LLVMConstInt(ctx->i32, 7, 0) : c30, "");
508 tmp = LLVMBuildAShr(gallivm->builder, tmp, c30, "");
509
510 /* Convert back to the right type. */
511 if (fix_fetch == SI_FIX_FETCH_A2_SNORM) {
512 LLVMValueRef clamp;
513 LLVMValueRef neg_one = LLVMConstReal(ctx->f32, -1.0);
514 tmp = LLVMBuildSIToFP(gallivm->builder, tmp, ctx->f32, "");
515 clamp = LLVMBuildFCmp(gallivm->builder, LLVMRealULT, tmp, neg_one, "");
516 tmp = LLVMBuildSelect(gallivm->builder, clamp, neg_one, tmp, "");
517 } else if (fix_fetch == SI_FIX_FETCH_A2_SSCALED) {
518 tmp = LLVMBuildSIToFP(gallivm->builder, tmp, ctx->f32, "");
519 }
520
521 out[3] = tmp;
522 break;
523 }
524 case SI_FIX_FETCH_RGBA_32_UNORM:
525 case SI_FIX_FETCH_RGBX_32_UNORM:
526 for (chan = 0; chan < 4; chan++) {
527 out[chan] = LLVMBuildBitCast(gallivm->builder, out[chan],
528 ctx->i32, "");
529 out[chan] = LLVMBuildUIToFP(gallivm->builder,
530 out[chan], ctx->f32, "");
531 out[chan] = LLVMBuildFMul(gallivm->builder, out[chan],
532 LLVMConstReal(ctx->f32, 1.0 / UINT_MAX), "");
533 }
534 /* RGBX UINT returns 1 in alpha, which would be rounded to 0 by normalizing. */
535 if (fix_fetch == SI_FIX_FETCH_RGBX_32_UNORM)
536 out[3] = LLVMConstReal(ctx->f32, 1);
537 break;
538 case SI_FIX_FETCH_RGBA_32_SNORM:
539 case SI_FIX_FETCH_RGBX_32_SNORM:
540 case SI_FIX_FETCH_RGBA_32_FIXED:
541 case SI_FIX_FETCH_RGBX_32_FIXED: {
542 double scale;
543 if (fix_fetch >= SI_FIX_FETCH_RGBA_32_FIXED)
544 scale = 1.0 / 0x10000;
545 else
546 scale = 1.0 / INT_MAX;
547
548 for (chan = 0; chan < 4; chan++) {
549 out[chan] = LLVMBuildBitCast(gallivm->builder, out[chan],
550 ctx->i32, "");
551 out[chan] = LLVMBuildSIToFP(gallivm->builder,
552 out[chan], ctx->f32, "");
553 out[chan] = LLVMBuildFMul(gallivm->builder, out[chan],
554 LLVMConstReal(ctx->f32, scale), "");
555 }
556 /* RGBX SINT returns 1 in alpha, which would be rounded to 0 by normalizing. */
557 if (fix_fetch == SI_FIX_FETCH_RGBX_32_SNORM ||
558 fix_fetch == SI_FIX_FETCH_RGBX_32_FIXED)
559 out[3] = LLVMConstReal(ctx->f32, 1);
560 break;
561 }
562 case SI_FIX_FETCH_RGBA_32_USCALED:
563 for (chan = 0; chan < 4; chan++) {
564 out[chan] = LLVMBuildBitCast(gallivm->builder, out[chan],
565 ctx->i32, "");
566 out[chan] = LLVMBuildUIToFP(gallivm->builder,
567 out[chan], ctx->f32, "");
568 }
569 break;
570 case SI_FIX_FETCH_RGBA_32_SSCALED:
571 for (chan = 0; chan < 4; chan++) {
572 out[chan] = LLVMBuildBitCast(gallivm->builder, out[chan],
573 ctx->i32, "");
574 out[chan] = LLVMBuildSIToFP(gallivm->builder,
575 out[chan], ctx->f32, "");
576 }
577 break;
578 case SI_FIX_FETCH_RG_64_FLOAT:
579 for (chan = 0; chan < 2; chan++)
580 out[chan] = extract_double_to_float(ctx, input[0], chan);
581
582 out[2] = LLVMConstReal(ctx->f32, 0);
583 out[3] = LLVMConstReal(ctx->f32, 1);
584 break;
585 case SI_FIX_FETCH_RGB_64_FLOAT:
586 for (chan = 0; chan < 3; chan++)
587 out[chan] = extract_double_to_float(ctx, input[chan], 0);
588
589 out[3] = LLVMConstReal(ctx->f32, 1);
590 break;
591 case SI_FIX_FETCH_RGBA_64_FLOAT:
592 for (chan = 0; chan < 4; chan++) {
593 out[chan] = extract_double_to_float(ctx, input[chan / 2],
594 chan % 2);
595 }
596 break;
597 case SI_FIX_FETCH_RGB_8:
598 case SI_FIX_FETCH_RGB_8_INT:
599 case SI_FIX_FETCH_RGB_16:
600 case SI_FIX_FETCH_RGB_16_INT:
601 for (chan = 0; chan < 3; chan++) {
602 out[chan] = LLVMBuildExtractElement(gallivm->builder,
603 input[chan],
604 ctx->i32_0, "");
605 }
606 if (fix_fetch == SI_FIX_FETCH_RGB_8 ||
607 fix_fetch == SI_FIX_FETCH_RGB_16) {
608 out[3] = LLVMConstReal(ctx->f32, 1);
609 } else {
610 out[3] = LLVMBuildBitCast(gallivm->builder, ctx->i32_1,
611 ctx->f32, "");
612 }
613 break;
614 }
615 }
616
617 static void declare_input_vs(
618 struct si_shader_context *ctx,
619 unsigned input_index,
620 const struct tgsi_full_declaration *decl,
621 LLVMValueRef out[4])
622 {
623 si_llvm_load_input_vs(ctx, input_index, out);
624 }
625
626 static LLVMValueRef get_primitive_id(struct si_shader_context *ctx,
627 unsigned swizzle)
628 {
629 if (swizzle > 0)
630 return ctx->i32_0;
631
632 switch (ctx->type) {
633 case PIPE_SHADER_VERTEX:
634 return LLVMGetParam(ctx->main_fn,
635 ctx->param_vs_prim_id);
636 case PIPE_SHADER_TESS_CTRL:
637 return LLVMGetParam(ctx->main_fn,
638 ctx->param_tcs_patch_id);
639 case PIPE_SHADER_TESS_EVAL:
640 return LLVMGetParam(ctx->main_fn,
641 ctx->param_tes_patch_id);
642 case PIPE_SHADER_GEOMETRY:
643 return LLVMGetParam(ctx->main_fn,
644 ctx->param_gs_prim_id);
645 default:
646 assert(0);
647 return ctx->i32_0;
648 }
649 }
650
651 /**
652 * Return the value of tgsi_ind_register for indexing.
653 * This is the indirect index with the constant offset added to it.
654 */
655 static LLVMValueRef get_indirect_index(struct si_shader_context *ctx,
656 const struct tgsi_ind_register *ind,
657 int rel_index)
658 {
659 struct gallivm_state *gallivm = &ctx->gallivm;
660 LLVMValueRef result;
661
662 result = ctx->addrs[ind->Index][ind->Swizzle];
663 result = LLVMBuildLoad(gallivm->builder, result, "");
664 result = LLVMBuildAdd(gallivm->builder, result,
665 LLVMConstInt(ctx->i32, rel_index, 0), "");
666 return result;
667 }
668
669 /**
670 * Like get_indirect_index, but restricts the return value to a (possibly
671 * undefined) value inside [0..num).
672 */
673 LLVMValueRef si_get_bounded_indirect_index(struct si_shader_context *ctx,
674 const struct tgsi_ind_register *ind,
675 int rel_index, unsigned num)
676 {
677 LLVMValueRef result = get_indirect_index(ctx, ind, rel_index);
678
679 return si_llvm_bound_index(ctx, result, num);
680 }
681
682
683 /**
684 * Calculate a dword address given an input or output register and a stride.
685 */
686 static LLVMValueRef get_dw_address(struct si_shader_context *ctx,
687 const struct tgsi_full_dst_register *dst,
688 const struct tgsi_full_src_register *src,
689 LLVMValueRef vertex_dw_stride,
690 LLVMValueRef base_addr)
691 {
692 struct gallivm_state *gallivm = &ctx->gallivm;
693 struct tgsi_shader_info *info = &ctx->shader->selector->info;
694 ubyte *name, *index, *array_first;
695 int first, param;
696 struct tgsi_full_dst_register reg;
697
698 /* Set the register description. The address computation is the same
699 * for sources and destinations. */
700 if (src) {
701 reg.Register.File = src->Register.File;
702 reg.Register.Index = src->Register.Index;
703 reg.Register.Indirect = src->Register.Indirect;
704 reg.Register.Dimension = src->Register.Dimension;
705 reg.Indirect = src->Indirect;
706 reg.Dimension = src->Dimension;
707 reg.DimIndirect = src->DimIndirect;
708 } else
709 reg = *dst;
710
711 /* If the register is 2-dimensional (e.g. an array of vertices
712 * in a primitive), calculate the base address of the vertex. */
713 if (reg.Register.Dimension) {
714 LLVMValueRef index;
715
716 if (reg.Dimension.Indirect)
717 index = get_indirect_index(ctx, &reg.DimIndirect,
718 reg.Dimension.Index);
719 else
720 index = LLVMConstInt(ctx->i32, reg.Dimension.Index, 0);
721
722 base_addr = LLVMBuildAdd(gallivm->builder, base_addr,
723 LLVMBuildMul(gallivm->builder, index,
724 vertex_dw_stride, ""), "");
725 }
726
727 /* Get information about the register. */
728 if (reg.Register.File == TGSI_FILE_INPUT) {
729 name = info->input_semantic_name;
730 index = info->input_semantic_index;
731 array_first = info->input_array_first;
732 } else if (reg.Register.File == TGSI_FILE_OUTPUT) {
733 name = info->output_semantic_name;
734 index = info->output_semantic_index;
735 array_first = info->output_array_first;
736 } else {
737 assert(0);
738 return NULL;
739 }
740
741 if (reg.Register.Indirect) {
742 /* Add the relative address of the element. */
743 LLVMValueRef ind_index;
744
745 if (reg.Indirect.ArrayID)
746 first = array_first[reg.Indirect.ArrayID];
747 else
748 first = reg.Register.Index;
749
750 ind_index = get_indirect_index(ctx, &reg.Indirect,
751 reg.Register.Index - first);
752
753 base_addr = LLVMBuildAdd(gallivm->builder, base_addr,
754 LLVMBuildMul(gallivm->builder, ind_index,
755 LLVMConstInt(ctx->i32, 4, 0), ""), "");
756
757 param = reg.Register.Dimension ?
758 si_shader_io_get_unique_index(name[first], index[first]) :
759 si_shader_io_get_unique_index_patch(name[first], index[first]);
760 } else {
761 param = reg.Register.Dimension ?
762 si_shader_io_get_unique_index(name[reg.Register.Index],
763 index[reg.Register.Index]) :
764 si_shader_io_get_unique_index_patch(name[reg.Register.Index],
765 index[reg.Register.Index]);
766 }
767
768 /* Add the base address of the element. */
769 return LLVMBuildAdd(gallivm->builder, base_addr,
770 LLVMConstInt(ctx->i32, param * 4, 0), "");
771 }
772
773 /* The offchip buffer layout for TCS->TES is
774 *
775 * - attribute 0 of patch 0 vertex 0
776 * - attribute 0 of patch 0 vertex 1
777 * - attribute 0 of patch 0 vertex 2
778 * ...
779 * - attribute 0 of patch 1 vertex 0
780 * - attribute 0 of patch 1 vertex 1
781 * ...
782 * - attribute 1 of patch 0 vertex 0
783 * - attribute 1 of patch 0 vertex 1
784 * ...
785 * - per patch attribute 0 of patch 0
786 * - per patch attribute 0 of patch 1
787 * ...
788 *
789 * Note that every attribute has 4 components.
790 */
791 static LLVMValueRef get_tcs_tes_buffer_address(struct si_shader_context *ctx,
792 LLVMValueRef rel_patch_id,
793 LLVMValueRef vertex_index,
794 LLVMValueRef param_index)
795 {
796 struct gallivm_state *gallivm = &ctx->gallivm;
797 LLVMValueRef base_addr, vertices_per_patch, num_patches, total_vertices;
798 LLVMValueRef param_stride, constant16;
799
800 vertices_per_patch = unpack_param(ctx, ctx->param_tcs_offchip_layout, 6, 6);
801 num_patches = unpack_param(ctx, ctx->param_tcs_offchip_layout, 0, 6);
802 total_vertices = LLVMBuildMul(gallivm->builder, vertices_per_patch,
803 num_patches, "");
804
805 constant16 = LLVMConstInt(ctx->i32, 16, 0);
806 if (vertex_index) {
807 base_addr = LLVMBuildMul(gallivm->builder, rel_patch_id,
808 vertices_per_patch, "");
809
810 base_addr = LLVMBuildAdd(gallivm->builder, base_addr,
811 vertex_index, "");
812
813 param_stride = total_vertices;
814 } else {
815 base_addr = rel_patch_id;
816 param_stride = num_patches;
817 }
818
819 base_addr = LLVMBuildAdd(gallivm->builder, base_addr,
820 LLVMBuildMul(gallivm->builder, param_index,
821 param_stride, ""), "");
822
823 base_addr = LLVMBuildMul(gallivm->builder, base_addr, constant16, "");
824
825 if (!vertex_index) {
826 LLVMValueRef patch_data_offset =
827 unpack_param(ctx, ctx->param_tcs_offchip_layout, 12, 20);
828
829 base_addr = LLVMBuildAdd(gallivm->builder, base_addr,
830 patch_data_offset, "");
831 }
832 return base_addr;
833 }
834
835 static LLVMValueRef get_tcs_tes_buffer_address_from_reg(
836 struct si_shader_context *ctx,
837 const struct tgsi_full_dst_register *dst,
838 const struct tgsi_full_src_register *src)
839 {
840 struct gallivm_state *gallivm = &ctx->gallivm;
841 struct tgsi_shader_info *info = &ctx->shader->selector->info;
842 ubyte *name, *index, *array_first;
843 struct tgsi_full_src_register reg;
844 LLVMValueRef vertex_index = NULL;
845 LLVMValueRef param_index = NULL;
846 unsigned param_index_base, param_base;
847
848 reg = src ? *src : tgsi_full_src_register_from_dst(dst);
849
850 if (reg.Register.Dimension) {
851
852 if (reg.Dimension.Indirect)
853 vertex_index = get_indirect_index(ctx, &reg.DimIndirect,
854 reg.Dimension.Index);
855 else
856 vertex_index = LLVMConstInt(ctx->i32, reg.Dimension.Index, 0);
857 }
858
859 /* Get information about the register. */
860 if (reg.Register.File == TGSI_FILE_INPUT) {
861 name = info->input_semantic_name;
862 index = info->input_semantic_index;
863 array_first = info->input_array_first;
864 } else if (reg.Register.File == TGSI_FILE_OUTPUT) {
865 name = info->output_semantic_name;
866 index = info->output_semantic_index;
867 array_first = info->output_array_first;
868 } else {
869 assert(0);
870 return NULL;
871 }
872
873 if (reg.Register.Indirect) {
874 if (reg.Indirect.ArrayID)
875 param_base = array_first[reg.Indirect.ArrayID];
876 else
877 param_base = reg.Register.Index;
878
879 param_index = get_indirect_index(ctx, &reg.Indirect,
880 reg.Register.Index - param_base);
881
882 } else {
883 param_base = reg.Register.Index;
884 param_index = ctx->i32_0;
885 }
886
887 param_index_base = reg.Register.Dimension ?
888 si_shader_io_get_unique_index(name[param_base], index[param_base]) :
889 si_shader_io_get_unique_index_patch(name[param_base], index[param_base]);
890
891 param_index = LLVMBuildAdd(gallivm->builder, param_index,
892 LLVMConstInt(ctx->i32, param_index_base, 0),
893 "");
894
895 return get_tcs_tes_buffer_address(ctx, get_rel_patch_id(ctx),
896 vertex_index, param_index);
897 }
898
899 static LLVMValueRef buffer_load(struct lp_build_tgsi_context *bld_base,
900 enum tgsi_opcode_type type, unsigned swizzle,
901 LLVMValueRef buffer, LLVMValueRef offset,
902 LLVMValueRef base, bool can_speculate)
903 {
904 struct si_shader_context *ctx = si_shader_context(bld_base);
905 struct gallivm_state *gallivm = &ctx->gallivm;
906 LLVMValueRef value, value2;
907 LLVMTypeRef llvm_type = tgsi2llvmtype(bld_base, type);
908 LLVMTypeRef vec_type = LLVMVectorType(llvm_type, 4);
909
910 if (swizzle == ~0) {
911 value = ac_build_buffer_load(&ctx->ac, buffer, 4, NULL, base, offset,
912 0, 1, 0, can_speculate, false);
913
914 return LLVMBuildBitCast(gallivm->builder, value, vec_type, "");
915 }
916
917 if (!tgsi_type_is_64bit(type)) {
918 value = ac_build_buffer_load(&ctx->ac, buffer, 4, NULL, base, offset,
919 0, 1, 0, can_speculate, false);
920
921 value = LLVMBuildBitCast(gallivm->builder, value, vec_type, "");
922 return LLVMBuildExtractElement(gallivm->builder, value,
923 LLVMConstInt(ctx->i32, swizzle, 0), "");
924 }
925
926 value = ac_build_buffer_load(&ctx->ac, buffer, 1, NULL, base, offset,
927 swizzle * 4, 1, 0, can_speculate, false);
928
929 value2 = ac_build_buffer_load(&ctx->ac, buffer, 1, NULL, base, offset,
930 swizzle * 4 + 4, 1, 0, can_speculate, false);
931
932 return si_llvm_emit_fetch_64bit(bld_base, type, value, value2);
933 }
934
935 /**
936 * Load from LDS.
937 *
938 * \param type output value type
939 * \param swizzle offset (typically 0..3); it can be ~0, which loads a vec4
940 * \param dw_addr address in dwords
941 */
942 static LLVMValueRef lds_load(struct lp_build_tgsi_context *bld_base,
943 enum tgsi_opcode_type type, unsigned swizzle,
944 LLVMValueRef dw_addr)
945 {
946 struct si_shader_context *ctx = si_shader_context(bld_base);
947 struct gallivm_state *gallivm = &ctx->gallivm;
948 LLVMValueRef value;
949
950 if (swizzle == ~0) {
951 LLVMValueRef values[TGSI_NUM_CHANNELS];
952
953 for (unsigned chan = 0; chan < TGSI_NUM_CHANNELS; chan++)
954 values[chan] = lds_load(bld_base, type, chan, dw_addr);
955
956 return lp_build_gather_values(gallivm, values,
957 TGSI_NUM_CHANNELS);
958 }
959
960 dw_addr = lp_build_add(&bld_base->uint_bld, dw_addr,
961 LLVMConstInt(ctx->i32, swizzle, 0));
962
963 value = ac_build_indexed_load(&ctx->ac, ctx->lds, dw_addr, false);
964 if (tgsi_type_is_64bit(type)) {
965 LLVMValueRef value2;
966 dw_addr = lp_build_add(&bld_base->uint_bld, dw_addr,
967 ctx->i32_1);
968 value2 = ac_build_indexed_load(&ctx->ac, ctx->lds, dw_addr, false);
969 return si_llvm_emit_fetch_64bit(bld_base, type, value, value2);
970 }
971
972 return LLVMBuildBitCast(gallivm->builder, value,
973 tgsi2llvmtype(bld_base, type), "");
974 }
975
976 /**
977 * Store to LDS.
978 *
979 * \param swizzle offset (typically 0..3)
980 * \param dw_addr address in dwords
981 * \param value value to store
982 */
983 static void lds_store(struct lp_build_tgsi_context *bld_base,
984 unsigned dw_offset_imm, LLVMValueRef dw_addr,
985 LLVMValueRef value)
986 {
987 struct si_shader_context *ctx = si_shader_context(bld_base);
988 struct gallivm_state *gallivm = &ctx->gallivm;
989
990 dw_addr = lp_build_add(&bld_base->uint_bld, dw_addr,
991 LLVMConstInt(ctx->i32, dw_offset_imm, 0));
992
993 value = LLVMBuildBitCast(gallivm->builder, value, ctx->i32, "");
994 ac_build_indexed_store(&ctx->ac, ctx->lds,
995 dw_addr, value);
996 }
997
998 static LLVMValueRef desc_from_addr_base64k(struct si_shader_context *ctx,
999 unsigned param)
1000 {
1001 LLVMBuilderRef builder = ctx->gallivm.builder;
1002
1003 LLVMValueRef addr = LLVMGetParam(ctx->main_fn, param);
1004 addr = LLVMBuildZExt(builder, addr, ctx->i64, "");
1005 addr = LLVMBuildShl(builder, addr, LLVMConstInt(ctx->i64, 16, 0), "");
1006
1007 uint64_t desc2 = 0xffffffff;
1008 uint64_t desc3 = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1009 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1010 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1011 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1012 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1013 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
1014 LLVMValueRef hi = LLVMConstInt(ctx->i64, desc2 | (desc3 << 32), 0);
1015
1016 LLVMValueRef desc = LLVMGetUndef(LLVMVectorType(ctx->i64, 2));
1017 desc = LLVMBuildInsertElement(builder, desc, addr, ctx->i32_0, "");
1018 desc = LLVMBuildInsertElement(builder, desc, hi, ctx->i32_1, "");
1019 return LLVMBuildBitCast(builder, desc, ctx->v4i32, "");
1020 }
1021
1022 static LLVMValueRef fetch_input_tcs(
1023 struct lp_build_tgsi_context *bld_base,
1024 const struct tgsi_full_src_register *reg,
1025 enum tgsi_opcode_type type, unsigned swizzle)
1026 {
1027 struct si_shader_context *ctx = si_shader_context(bld_base);
1028 LLVMValueRef dw_addr, stride;
1029
1030 stride = unpack_param(ctx, ctx->param_vs_state_bits, 24, 8);
1031 dw_addr = get_tcs_in_current_patch_offset(ctx);
1032 dw_addr = get_dw_address(ctx, NULL, reg, stride, dw_addr);
1033
1034 return lds_load(bld_base, type, swizzle, dw_addr);
1035 }
1036
1037 static LLVMValueRef fetch_output_tcs(
1038 struct lp_build_tgsi_context *bld_base,
1039 const struct tgsi_full_src_register *reg,
1040 enum tgsi_opcode_type type, unsigned swizzle)
1041 {
1042 struct si_shader_context *ctx = si_shader_context(bld_base);
1043 LLVMValueRef dw_addr, stride;
1044
1045 if (reg->Register.Dimension) {
1046 stride = unpack_param(ctx, ctx->param_tcs_out_lds_layout, 13, 8);
1047 dw_addr = get_tcs_out_current_patch_offset(ctx);
1048 dw_addr = get_dw_address(ctx, NULL, reg, stride, dw_addr);
1049 } else {
1050 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1051 dw_addr = get_dw_address(ctx, NULL, reg, NULL, dw_addr);
1052 }
1053
1054 return lds_load(bld_base, type, swizzle, dw_addr);
1055 }
1056
1057 static LLVMValueRef fetch_input_tes(
1058 struct lp_build_tgsi_context *bld_base,
1059 const struct tgsi_full_src_register *reg,
1060 enum tgsi_opcode_type type, unsigned swizzle)
1061 {
1062 struct si_shader_context *ctx = si_shader_context(bld_base);
1063 LLVMValueRef buffer, base, addr;
1064
1065 buffer = desc_from_addr_base64k(ctx, ctx->param_tcs_offchip_addr_base64k);
1066
1067 base = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
1068 addr = get_tcs_tes_buffer_address_from_reg(ctx, NULL, reg);
1069
1070 return buffer_load(bld_base, type, swizzle, buffer, base, addr, true);
1071 }
1072
1073 static void store_output_tcs(struct lp_build_tgsi_context *bld_base,
1074 const struct tgsi_full_instruction *inst,
1075 const struct tgsi_opcode_info *info,
1076 LLVMValueRef dst[4])
1077 {
1078 struct si_shader_context *ctx = si_shader_context(bld_base);
1079 struct gallivm_state *gallivm = &ctx->gallivm;
1080 const struct tgsi_full_dst_register *reg = &inst->Dst[0];
1081 const struct tgsi_shader_info *sh_info = &ctx->shader->selector->info;
1082 unsigned chan_index;
1083 LLVMValueRef dw_addr, stride;
1084 LLVMValueRef buffer, base, buf_addr;
1085 LLVMValueRef values[4];
1086 bool skip_lds_store;
1087 bool is_tess_factor = false;
1088
1089 /* Only handle per-patch and per-vertex outputs here.
1090 * Vectors will be lowered to scalars and this function will be called again.
1091 */
1092 if (reg->Register.File != TGSI_FILE_OUTPUT ||
1093 (dst[0] && LLVMGetTypeKind(LLVMTypeOf(dst[0])) == LLVMVectorTypeKind)) {
1094 si_llvm_emit_store(bld_base, inst, info, dst);
1095 return;
1096 }
1097
1098 if (reg->Register.Dimension) {
1099 stride = unpack_param(ctx, ctx->param_tcs_out_lds_layout, 13, 8);
1100 dw_addr = get_tcs_out_current_patch_offset(ctx);
1101 dw_addr = get_dw_address(ctx, reg, NULL, stride, dw_addr);
1102 skip_lds_store = !sh_info->reads_pervertex_outputs;
1103 } else {
1104 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1105 dw_addr = get_dw_address(ctx, reg, NULL, NULL, dw_addr);
1106 skip_lds_store = !sh_info->reads_perpatch_outputs;
1107
1108 if (!reg->Register.Indirect) {
1109 int name = sh_info->output_semantic_name[reg->Register.Index];
1110
1111 /* Always write tess factors into LDS for the TCS epilog. */
1112 if (name == TGSI_SEMANTIC_TESSINNER ||
1113 name == TGSI_SEMANTIC_TESSOUTER) {
1114 skip_lds_store = false;
1115 is_tess_factor = true;
1116 }
1117 }
1118 }
1119
1120 buffer = desc_from_addr_base64k(ctx, ctx->param_tcs_offchip_addr_base64k);
1121
1122 base = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
1123 buf_addr = get_tcs_tes_buffer_address_from_reg(ctx, reg, NULL);
1124
1125
1126 TGSI_FOR_EACH_DST0_ENABLED_CHANNEL(inst, chan_index) {
1127 LLVMValueRef value = dst[chan_index];
1128
1129 if (inst->Instruction.Saturate)
1130 value = ac_build_clamp(&ctx->ac, value);
1131
1132 /* Skip LDS stores if there is no LDS read of this output. */
1133 if (!skip_lds_store)
1134 lds_store(bld_base, chan_index, dw_addr, value);
1135
1136 value = LLVMBuildBitCast(gallivm->builder, value, ctx->i32, "");
1137 values[chan_index] = value;
1138
1139 if (inst->Dst[0].Register.WriteMask != 0xF && !is_tess_factor) {
1140 ac_build_buffer_store_dword(&ctx->ac, buffer, value, 1,
1141 buf_addr, base,
1142 4 * chan_index, 1, 0, true, false);
1143 }
1144 }
1145
1146 if (inst->Dst[0].Register.WriteMask == 0xF && !is_tess_factor) {
1147 LLVMValueRef value = lp_build_gather_values(gallivm,
1148 values, 4);
1149 ac_build_buffer_store_dword(&ctx->ac, buffer, value, 4, buf_addr,
1150 base, 0, 1, 0, true, false);
1151 }
1152 }
1153
1154 static LLVMValueRef fetch_input_gs(
1155 struct lp_build_tgsi_context *bld_base,
1156 const struct tgsi_full_src_register *reg,
1157 enum tgsi_opcode_type type,
1158 unsigned swizzle)
1159 {
1160 struct si_shader_context *ctx = si_shader_context(bld_base);
1161 struct si_shader *shader = ctx->shader;
1162 struct lp_build_context *uint = &ctx->bld_base.uint_bld;
1163 struct gallivm_state *gallivm = &ctx->gallivm;
1164 LLVMValueRef vtx_offset, soffset;
1165 struct tgsi_shader_info *info = &shader->selector->info;
1166 unsigned semantic_name = info->input_semantic_name[reg->Register.Index];
1167 unsigned semantic_index = info->input_semantic_index[reg->Register.Index];
1168 unsigned param;
1169 LLVMValueRef value;
1170
1171 if (swizzle != ~0 && semantic_name == TGSI_SEMANTIC_PRIMID)
1172 return get_primitive_id(ctx, swizzle);
1173
1174 if (!reg->Register.Dimension)
1175 return NULL;
1176
1177 param = si_shader_io_get_unique_index(semantic_name, semantic_index);
1178
1179 /* GFX9 has the ESGS ring in LDS. */
1180 if (ctx->screen->b.chip_class >= GFX9) {
1181 unsigned index = reg->Dimension.Index;
1182
1183 switch (index / 2) {
1184 case 0:
1185 vtx_offset = unpack_param(ctx, ctx->param_gs_vtx01_offset,
1186 index % 2 ? 16 : 0, 16);
1187 break;
1188 case 1:
1189 vtx_offset = unpack_param(ctx, ctx->param_gs_vtx23_offset,
1190 index % 2 ? 16 : 0, 16);
1191 break;
1192 case 2:
1193 vtx_offset = unpack_param(ctx, ctx->param_gs_vtx45_offset,
1194 index % 2 ? 16 : 0, 16);
1195 break;
1196 default:
1197 assert(0);
1198 return NULL;
1199 }
1200
1201 vtx_offset = LLVMBuildAdd(gallivm->builder, vtx_offset,
1202 LLVMConstInt(ctx->i32, param * 4, 0), "");
1203 return lds_load(bld_base, type, swizzle, vtx_offset);
1204 }
1205
1206 /* GFX6: input load from the ESGS ring in memory. */
1207 if (swizzle == ~0) {
1208 LLVMValueRef values[TGSI_NUM_CHANNELS];
1209 unsigned chan;
1210 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1211 values[chan] = fetch_input_gs(bld_base, reg, type, chan);
1212 }
1213 return lp_build_gather_values(gallivm, values,
1214 TGSI_NUM_CHANNELS);
1215 }
1216
1217 /* Get the vertex offset parameter on GFX6. */
1218 unsigned vtx_offset_param = reg->Dimension.Index;
1219 if (vtx_offset_param < 2) {
1220 vtx_offset_param += ctx->param_gs_vtx0_offset;
1221 } else {
1222 assert(vtx_offset_param < 6);
1223 vtx_offset_param += ctx->param_gs_vtx2_offset - 2;
1224 }
1225 vtx_offset = lp_build_mul_imm(uint,
1226 LLVMGetParam(ctx->main_fn,
1227 vtx_offset_param),
1228 4);
1229
1230 soffset = LLVMConstInt(ctx->i32, (param * 4 + swizzle) * 256, 0);
1231
1232 value = ac_build_buffer_load(&ctx->ac, ctx->esgs_ring, 1, ctx->i32_0,
1233 vtx_offset, soffset, 0, 1, 0, true, false);
1234 if (tgsi_type_is_64bit(type)) {
1235 LLVMValueRef value2;
1236 soffset = LLVMConstInt(ctx->i32, (param * 4 + swizzle + 1) * 256, 0);
1237
1238 value2 = ac_build_buffer_load(&ctx->ac, ctx->esgs_ring, 1,
1239 ctx->i32_0, vtx_offset, soffset,
1240 0, 1, 0, true, false);
1241 return si_llvm_emit_fetch_64bit(bld_base, type,
1242 value, value2);
1243 }
1244 return LLVMBuildBitCast(gallivm->builder,
1245 value,
1246 tgsi2llvmtype(bld_base, type), "");
1247 }
1248
1249 static int lookup_interp_param_index(unsigned interpolate, unsigned location)
1250 {
1251 switch (interpolate) {
1252 case TGSI_INTERPOLATE_CONSTANT:
1253 return 0;
1254
1255 case TGSI_INTERPOLATE_LINEAR:
1256 if (location == TGSI_INTERPOLATE_LOC_SAMPLE)
1257 return SI_PARAM_LINEAR_SAMPLE;
1258 else if (location == TGSI_INTERPOLATE_LOC_CENTROID)
1259 return SI_PARAM_LINEAR_CENTROID;
1260 else
1261 return SI_PARAM_LINEAR_CENTER;
1262 break;
1263 case TGSI_INTERPOLATE_COLOR:
1264 case TGSI_INTERPOLATE_PERSPECTIVE:
1265 if (location == TGSI_INTERPOLATE_LOC_SAMPLE)
1266 return SI_PARAM_PERSP_SAMPLE;
1267 else if (location == TGSI_INTERPOLATE_LOC_CENTROID)
1268 return SI_PARAM_PERSP_CENTROID;
1269 else
1270 return SI_PARAM_PERSP_CENTER;
1271 break;
1272 default:
1273 fprintf(stderr, "Warning: Unhandled interpolation mode.\n");
1274 return -1;
1275 }
1276 }
1277
1278 static LLVMValueRef si_build_fs_interp(struct si_shader_context *ctx,
1279 unsigned attr_index, unsigned chan,
1280 LLVMValueRef prim_mask,
1281 LLVMValueRef i, LLVMValueRef j)
1282 {
1283 if (i || j) {
1284 return ac_build_fs_interp(&ctx->ac,
1285 LLVMConstInt(ctx->i32, chan, 0),
1286 LLVMConstInt(ctx->i32, attr_index, 0),
1287 prim_mask, i, j);
1288 }
1289 return ac_build_fs_interp_mov(&ctx->ac,
1290 LLVMConstInt(ctx->i32, 2, 0), /* P0 */
1291 LLVMConstInt(ctx->i32, chan, 0),
1292 LLVMConstInt(ctx->i32, attr_index, 0),
1293 prim_mask);
1294 }
1295
1296 /**
1297 * Interpolate a fragment shader input.
1298 *
1299 * @param ctx context
1300 * @param input_index index of the input in hardware
1301 * @param semantic_name TGSI_SEMANTIC_*
1302 * @param semantic_index semantic index
1303 * @param num_interp_inputs number of all interpolated inputs (= BCOLOR offset)
1304 * @param colors_read_mask color components read (4 bits for each color, 8 bits in total)
1305 * @param interp_param interpolation weights (i,j)
1306 * @param prim_mask SI_PARAM_PRIM_MASK
1307 * @param face SI_PARAM_FRONT_FACE
1308 * @param result the return value (4 components)
1309 */
1310 static void interp_fs_input(struct si_shader_context *ctx,
1311 unsigned input_index,
1312 unsigned semantic_name,
1313 unsigned semantic_index,
1314 unsigned num_interp_inputs,
1315 unsigned colors_read_mask,
1316 LLVMValueRef interp_param,
1317 LLVMValueRef prim_mask,
1318 LLVMValueRef face,
1319 LLVMValueRef result[4])
1320 {
1321 struct gallivm_state *gallivm = &ctx->gallivm;
1322 LLVMValueRef i = NULL, j = NULL;
1323 unsigned chan;
1324
1325 /* fs.constant returns the param from the middle vertex, so it's not
1326 * really useful for flat shading. It's meant to be used for custom
1327 * interpolation (but the intrinsic can't fetch from the other two
1328 * vertices).
1329 *
1330 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
1331 * to do the right thing. The only reason we use fs.constant is that
1332 * fs.interp cannot be used on integers, because they can be equal
1333 * to NaN.
1334 *
1335 * When interp is false we will use fs.constant or for newer llvm,
1336 * amdgcn.interp.mov.
1337 */
1338 bool interp = interp_param != NULL;
1339
1340 if (interp) {
1341 interp_param = LLVMBuildBitCast(gallivm->builder, interp_param,
1342 LLVMVectorType(ctx->f32, 2), "");
1343
1344 i = LLVMBuildExtractElement(gallivm->builder, interp_param,
1345 ctx->i32_0, "");
1346 j = LLVMBuildExtractElement(gallivm->builder, interp_param,
1347 ctx->i32_1, "");
1348 }
1349
1350 if (semantic_name == TGSI_SEMANTIC_COLOR &&
1351 ctx->shader->key.part.ps.prolog.color_two_side) {
1352 LLVMValueRef is_face_positive;
1353
1354 /* If BCOLOR0 is used, BCOLOR1 is at offset "num_inputs + 1",
1355 * otherwise it's at offset "num_inputs".
1356 */
1357 unsigned back_attr_offset = num_interp_inputs;
1358 if (semantic_index == 1 && colors_read_mask & 0xf)
1359 back_attr_offset += 1;
1360
1361 is_face_positive = LLVMBuildICmp(gallivm->builder, LLVMIntNE,
1362 face, ctx->i32_0, "");
1363
1364 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1365 LLVMValueRef front, back;
1366
1367 front = si_build_fs_interp(ctx,
1368 input_index, chan,
1369 prim_mask, i, j);
1370 back = si_build_fs_interp(ctx,
1371 back_attr_offset, chan,
1372 prim_mask, i, j);
1373
1374 result[chan] = LLVMBuildSelect(gallivm->builder,
1375 is_face_positive,
1376 front,
1377 back,
1378 "");
1379 }
1380 } else if (semantic_name == TGSI_SEMANTIC_FOG) {
1381 result[0] = si_build_fs_interp(ctx, input_index,
1382 0, prim_mask, i, j);
1383 result[1] =
1384 result[2] = LLVMConstReal(ctx->f32, 0.0f);
1385 result[3] = LLVMConstReal(ctx->f32, 1.0f);
1386 } else {
1387 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1388 result[chan] = si_build_fs_interp(ctx,
1389 input_index, chan,
1390 prim_mask, i, j);
1391 }
1392 }
1393 }
1394
1395 void si_llvm_load_input_fs(
1396 struct si_shader_context *ctx,
1397 unsigned input_index,
1398 LLVMValueRef out[4])
1399 {
1400 struct lp_build_context *base = &ctx->bld_base.base;
1401 struct si_shader *shader = ctx->shader;
1402 struct tgsi_shader_info *info = &shader->selector->info;
1403 LLVMValueRef main_fn = ctx->main_fn;
1404 LLVMValueRef interp_param = NULL;
1405 int interp_param_idx;
1406 enum tgsi_semantic semantic_name = info->input_semantic_name[input_index];
1407 unsigned semantic_index = info->input_semantic_index[input_index];
1408 enum tgsi_interpolate_mode interp_mode = info->input_interpolate[input_index];
1409 enum tgsi_interpolate_loc interp_loc = info->input_interpolate_loc[input_index];
1410
1411 /* Get colors from input VGPRs (set by the prolog). */
1412 if (semantic_name == TGSI_SEMANTIC_COLOR) {
1413 unsigned colors_read = shader->selector->info.colors_read;
1414 unsigned mask = colors_read >> (semantic_index * 4);
1415 unsigned offset = SI_PARAM_POS_FIXED_PT + 1 +
1416 (semantic_index ? util_bitcount(colors_read & 0xf) : 0);
1417
1418 out[0] = mask & 0x1 ? LLVMGetParam(main_fn, offset++) : base->undef;
1419 out[1] = mask & 0x2 ? LLVMGetParam(main_fn, offset++) : base->undef;
1420 out[2] = mask & 0x4 ? LLVMGetParam(main_fn, offset++) : base->undef;
1421 out[3] = mask & 0x8 ? LLVMGetParam(main_fn, offset++) : base->undef;
1422 return;
1423 }
1424
1425 interp_param_idx = lookup_interp_param_index(interp_mode, interp_loc);
1426 if (interp_param_idx == -1)
1427 return;
1428 else if (interp_param_idx) {
1429 interp_param = LLVMGetParam(ctx->main_fn, interp_param_idx);
1430 }
1431
1432 interp_fs_input(ctx, input_index, semantic_name,
1433 semantic_index, 0, /* this param is unused */
1434 shader->selector->info.colors_read, interp_param,
1435 LLVMGetParam(main_fn, SI_PARAM_PRIM_MASK),
1436 LLVMGetParam(main_fn, SI_PARAM_FRONT_FACE),
1437 &out[0]);
1438 }
1439
1440 static void declare_input_fs(
1441 struct si_shader_context *ctx,
1442 unsigned input_index,
1443 const struct tgsi_full_declaration *decl,
1444 LLVMValueRef out[4])
1445 {
1446 si_llvm_load_input_fs(ctx, input_index, out);
1447 }
1448
1449 static LLVMValueRef get_sample_id(struct si_shader_context *ctx)
1450 {
1451 return unpack_param(ctx, SI_PARAM_ANCILLARY, 8, 4);
1452 }
1453
1454
1455 /**
1456 * Load a dword from a constant buffer.
1457 */
1458 static LLVMValueRef buffer_load_const(struct si_shader_context *ctx,
1459 LLVMValueRef resource,
1460 LLVMValueRef offset)
1461 {
1462 return ac_build_buffer_load(&ctx->ac, resource, 1, NULL, offset, NULL,
1463 0, 0, 0, true, true);
1464 }
1465
1466 static LLVMValueRef load_sample_position(struct si_shader_context *ctx, LLVMValueRef sample_id)
1467 {
1468 struct lp_build_context *uint_bld = &ctx->bld_base.uint_bld;
1469 struct gallivm_state *gallivm = &ctx->gallivm;
1470 LLVMBuilderRef builder = gallivm->builder;
1471 LLVMValueRef desc = LLVMGetParam(ctx->main_fn, ctx->param_rw_buffers);
1472 LLVMValueRef buf_index = LLVMConstInt(ctx->i32, SI_PS_CONST_SAMPLE_POSITIONS, 0);
1473 LLVMValueRef resource = ac_build_indexed_load_const(&ctx->ac, desc, buf_index);
1474
1475 /* offset = sample_id * 8 (8 = 2 floats containing samplepos.xy) */
1476 LLVMValueRef offset0 = lp_build_mul_imm(uint_bld, sample_id, 8);
1477 LLVMValueRef offset1 = LLVMBuildAdd(builder, offset0, LLVMConstInt(ctx->i32, 4, 0), "");
1478
1479 LLVMValueRef pos[4] = {
1480 buffer_load_const(ctx, resource, offset0),
1481 buffer_load_const(ctx, resource, offset1),
1482 LLVMConstReal(ctx->f32, 0),
1483 LLVMConstReal(ctx->f32, 0)
1484 };
1485
1486 return lp_build_gather_values(gallivm, pos, 4);
1487 }
1488
1489 static void declare_system_value(struct si_shader_context *ctx,
1490 unsigned index,
1491 const struct tgsi_full_declaration *decl)
1492 {
1493 struct lp_build_context *bld = &ctx->bld_base.base;
1494 struct gallivm_state *gallivm = &ctx->gallivm;
1495 LLVMValueRef value = 0;
1496
1497 assert(index < RADEON_LLVM_MAX_SYSTEM_VALUES);
1498
1499 switch (decl->Semantic.Name) {
1500 case TGSI_SEMANTIC_INSTANCEID:
1501 value = ctx->abi.instance_id;
1502 break;
1503
1504 case TGSI_SEMANTIC_VERTEXID:
1505 value = LLVMBuildAdd(gallivm->builder,
1506 ctx->abi.vertex_id,
1507 ctx->abi.base_vertex, "");
1508 break;
1509
1510 case TGSI_SEMANTIC_VERTEXID_NOBASE:
1511 /* Unused. Clarify the meaning in indexed vs. non-indexed
1512 * draws if this is ever used again. */
1513 assert(false);
1514 break;
1515
1516 case TGSI_SEMANTIC_BASEVERTEX:
1517 {
1518 /* For non-indexed draws, the base vertex set by the driver
1519 * (for direct draws) or the CP (for indirect draws) is the
1520 * first vertex ID, but GLSL expects 0 to be returned.
1521 */
1522 LLVMValueRef vs_state = LLVMGetParam(ctx->main_fn, ctx->param_vs_state_bits);
1523 LLVMValueRef indexed;
1524
1525 indexed = LLVMBuildLShr(gallivm->builder, vs_state, ctx->i32_1, "");
1526 indexed = LLVMBuildTrunc(gallivm->builder, indexed, ctx->i1, "");
1527
1528 value = LLVMBuildSelect(gallivm->builder, indexed,
1529 ctx->abi.base_vertex, ctx->i32_0, "");
1530 break;
1531 }
1532
1533 case TGSI_SEMANTIC_BASEINSTANCE:
1534 value = ctx->abi.start_instance;
1535 break;
1536
1537 case TGSI_SEMANTIC_DRAWID:
1538 value = ctx->abi.draw_id;
1539 break;
1540
1541 case TGSI_SEMANTIC_INVOCATIONID:
1542 if (ctx->type == PIPE_SHADER_TESS_CTRL)
1543 value = unpack_param(ctx, ctx->param_tcs_rel_ids, 8, 5);
1544 else if (ctx->type == PIPE_SHADER_GEOMETRY)
1545 value = LLVMGetParam(ctx->main_fn,
1546 ctx->param_gs_instance_id);
1547 else
1548 assert(!"INVOCATIONID not implemented");
1549 break;
1550
1551 case TGSI_SEMANTIC_POSITION:
1552 {
1553 LLVMValueRef pos[4] = {
1554 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_X_FLOAT),
1555 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_Y_FLOAT),
1556 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_Z_FLOAT),
1557 lp_build_emit_llvm_unary(&ctx->bld_base, TGSI_OPCODE_RCP,
1558 LLVMGetParam(ctx->main_fn,
1559 SI_PARAM_POS_W_FLOAT)),
1560 };
1561 value = lp_build_gather_values(gallivm, pos, 4);
1562 break;
1563 }
1564
1565 case TGSI_SEMANTIC_FACE:
1566 value = LLVMGetParam(ctx->main_fn, SI_PARAM_FRONT_FACE);
1567 break;
1568
1569 case TGSI_SEMANTIC_SAMPLEID:
1570 value = get_sample_id(ctx);
1571 break;
1572
1573 case TGSI_SEMANTIC_SAMPLEPOS: {
1574 LLVMValueRef pos[4] = {
1575 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_X_FLOAT),
1576 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_Y_FLOAT),
1577 LLVMConstReal(ctx->f32, 0),
1578 LLVMConstReal(ctx->f32, 0)
1579 };
1580 pos[0] = lp_build_emit_llvm_unary(&ctx->bld_base,
1581 TGSI_OPCODE_FRC, pos[0]);
1582 pos[1] = lp_build_emit_llvm_unary(&ctx->bld_base,
1583 TGSI_OPCODE_FRC, pos[1]);
1584 value = lp_build_gather_values(gallivm, pos, 4);
1585 break;
1586 }
1587
1588 case TGSI_SEMANTIC_SAMPLEMASK:
1589 /* This can only occur with the OpenGL Core profile, which
1590 * doesn't support smoothing.
1591 */
1592 value = LLVMGetParam(ctx->main_fn, SI_PARAM_SAMPLE_COVERAGE);
1593 break;
1594
1595 case TGSI_SEMANTIC_TESSCOORD:
1596 {
1597 LLVMValueRef coord[4] = {
1598 LLVMGetParam(ctx->main_fn, ctx->param_tes_u),
1599 LLVMGetParam(ctx->main_fn, ctx->param_tes_v),
1600 bld->zero,
1601 bld->zero
1602 };
1603
1604 /* For triangles, the vector should be (u, v, 1-u-v). */
1605 if (ctx->shader->selector->info.properties[TGSI_PROPERTY_TES_PRIM_MODE] ==
1606 PIPE_PRIM_TRIANGLES)
1607 coord[2] = lp_build_sub(bld, bld->one,
1608 lp_build_add(bld, coord[0], coord[1]));
1609
1610 value = lp_build_gather_values(gallivm, coord, 4);
1611 break;
1612 }
1613
1614 case TGSI_SEMANTIC_VERTICESIN:
1615 if (ctx->type == PIPE_SHADER_TESS_CTRL)
1616 value = unpack_param(ctx, ctx->param_tcs_out_lds_layout, 26, 6);
1617 else if (ctx->type == PIPE_SHADER_TESS_EVAL)
1618 value = unpack_param(ctx, ctx->param_tcs_offchip_layout, 6, 6);
1619 else
1620 assert(!"invalid shader stage for TGSI_SEMANTIC_VERTICESIN");
1621 break;
1622
1623 case TGSI_SEMANTIC_TESSINNER:
1624 case TGSI_SEMANTIC_TESSOUTER:
1625 {
1626 LLVMValueRef buffer, base, addr;
1627 int param = si_shader_io_get_unique_index_patch(decl->Semantic.Name, 0);
1628
1629 buffer = desc_from_addr_base64k(ctx, ctx->param_tcs_offchip_addr_base64k);
1630
1631 base = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
1632 addr = get_tcs_tes_buffer_address(ctx, get_rel_patch_id(ctx), NULL,
1633 LLVMConstInt(ctx->i32, param, 0));
1634
1635 value = buffer_load(&ctx->bld_base, TGSI_TYPE_FLOAT,
1636 ~0, buffer, base, addr, true);
1637
1638 break;
1639 }
1640
1641 case TGSI_SEMANTIC_DEFAULT_TESSOUTER_SI:
1642 case TGSI_SEMANTIC_DEFAULT_TESSINNER_SI:
1643 {
1644 LLVMValueRef buf, slot, val[4];
1645 int i, offset;
1646
1647 slot = LLVMConstInt(ctx->i32, SI_HS_CONST_DEFAULT_TESS_LEVELS, 0);
1648 buf = LLVMGetParam(ctx->main_fn, ctx->param_rw_buffers);
1649 buf = ac_build_indexed_load_const(&ctx->ac, buf, slot);
1650 offset = decl->Semantic.Name == TGSI_SEMANTIC_DEFAULT_TESSINNER_SI ? 4 : 0;
1651
1652 for (i = 0; i < 4; i++)
1653 val[i] = buffer_load_const(ctx, buf,
1654 LLVMConstInt(ctx->i32, (offset + i) * 4, 0));
1655 value = lp_build_gather_values(gallivm, val, 4);
1656 break;
1657 }
1658
1659 case TGSI_SEMANTIC_PRIMID:
1660 value = get_primitive_id(ctx, 0);
1661 break;
1662
1663 case TGSI_SEMANTIC_GRID_SIZE:
1664 value = LLVMGetParam(ctx->main_fn, ctx->param_grid_size);
1665 break;
1666
1667 case TGSI_SEMANTIC_BLOCK_SIZE:
1668 {
1669 LLVMValueRef values[3];
1670 unsigned i;
1671 unsigned *properties = ctx->shader->selector->info.properties;
1672
1673 if (properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] != 0) {
1674 unsigned sizes[3] = {
1675 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH],
1676 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT],
1677 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH]
1678 };
1679
1680 for (i = 0; i < 3; ++i)
1681 values[i] = LLVMConstInt(ctx->i32, sizes[i], 0);
1682
1683 value = lp_build_gather_values(gallivm, values, 3);
1684 } else {
1685 value = LLVMGetParam(ctx->main_fn, ctx->param_block_size);
1686 }
1687 break;
1688 }
1689
1690 case TGSI_SEMANTIC_BLOCK_ID:
1691 {
1692 LLVMValueRef values[3];
1693
1694 for (int i = 0; i < 3; i++) {
1695 values[i] = ctx->i32_0;
1696 if (ctx->param_block_id[i] >= 0) {
1697 values[i] = LLVMGetParam(ctx->main_fn,
1698 ctx->param_block_id[i]);
1699 }
1700 }
1701 value = lp_build_gather_values(gallivm, values, 3);
1702 break;
1703 }
1704
1705 case TGSI_SEMANTIC_THREAD_ID:
1706 value = LLVMGetParam(ctx->main_fn, ctx->param_thread_id);
1707 break;
1708
1709 case TGSI_SEMANTIC_HELPER_INVOCATION:
1710 value = lp_build_intrinsic(gallivm->builder,
1711 "llvm.amdgcn.ps.live",
1712 ctx->i1, NULL, 0,
1713 LP_FUNC_ATTR_READNONE);
1714 value = LLVMBuildNot(gallivm->builder, value, "");
1715 value = LLVMBuildSExt(gallivm->builder, value, ctx->i32, "");
1716 break;
1717
1718 case TGSI_SEMANTIC_SUBGROUP_SIZE:
1719 value = LLVMConstInt(ctx->i32, 64, 0);
1720 break;
1721
1722 case TGSI_SEMANTIC_SUBGROUP_INVOCATION:
1723 value = ac_get_thread_id(&ctx->ac);
1724 break;
1725
1726 case TGSI_SEMANTIC_SUBGROUP_EQ_MASK:
1727 {
1728 LLVMValueRef id = ac_get_thread_id(&ctx->ac);
1729 id = LLVMBuildZExt(gallivm->builder, id, ctx->i64, "");
1730 value = LLVMBuildShl(gallivm->builder, LLVMConstInt(ctx->i64, 1, 0), id, "");
1731 value = LLVMBuildBitCast(gallivm->builder, value, ctx->v2i32, "");
1732 break;
1733 }
1734
1735 case TGSI_SEMANTIC_SUBGROUP_GE_MASK:
1736 case TGSI_SEMANTIC_SUBGROUP_GT_MASK:
1737 case TGSI_SEMANTIC_SUBGROUP_LE_MASK:
1738 case TGSI_SEMANTIC_SUBGROUP_LT_MASK:
1739 {
1740 LLVMValueRef id = ac_get_thread_id(&ctx->ac);
1741 if (decl->Semantic.Name == TGSI_SEMANTIC_SUBGROUP_GT_MASK ||
1742 decl->Semantic.Name == TGSI_SEMANTIC_SUBGROUP_LE_MASK) {
1743 /* All bits set except LSB */
1744 value = LLVMConstInt(ctx->i64, -2, 0);
1745 } else {
1746 /* All bits set */
1747 value = LLVMConstInt(ctx->i64, -1, 0);
1748 }
1749 id = LLVMBuildZExt(gallivm->builder, id, ctx->i64, "");
1750 value = LLVMBuildShl(gallivm->builder, value, id, "");
1751 if (decl->Semantic.Name == TGSI_SEMANTIC_SUBGROUP_LE_MASK ||
1752 decl->Semantic.Name == TGSI_SEMANTIC_SUBGROUP_LT_MASK)
1753 value = LLVMBuildNot(gallivm->builder, value, "");
1754 value = LLVMBuildBitCast(gallivm->builder, value, ctx->v2i32, "");
1755 break;
1756 }
1757
1758 default:
1759 assert(!"unknown system value");
1760 return;
1761 }
1762
1763 ctx->system_values[index] = value;
1764 }
1765
1766 static void declare_compute_memory(struct si_shader_context *ctx,
1767 const struct tgsi_full_declaration *decl)
1768 {
1769 struct si_shader_selector *sel = ctx->shader->selector;
1770 struct gallivm_state *gallivm = &ctx->gallivm;
1771
1772 LLVMTypeRef i8p = LLVMPointerType(ctx->i8, LOCAL_ADDR_SPACE);
1773 LLVMValueRef var;
1774
1775 assert(decl->Declaration.MemType == TGSI_MEMORY_TYPE_SHARED);
1776 assert(decl->Range.First == decl->Range.Last);
1777 assert(!ctx->shared_memory);
1778
1779 var = LLVMAddGlobalInAddressSpace(gallivm->module,
1780 LLVMArrayType(ctx->i8, sel->local_size),
1781 "compute_lds",
1782 LOCAL_ADDR_SPACE);
1783 LLVMSetAlignment(var, 4);
1784
1785 ctx->shared_memory = LLVMBuildBitCast(gallivm->builder, var, i8p, "");
1786 }
1787
1788 static LLVMValueRef load_const_buffer_desc(struct si_shader_context *ctx, int i)
1789 {
1790 LLVMValueRef list_ptr = LLVMGetParam(ctx->main_fn,
1791 ctx->param_const_and_shader_buffers);
1792
1793 return ac_build_indexed_load_const(&ctx->ac, list_ptr,
1794 LLVMConstInt(ctx->i32, si_get_constbuf_slot(i), 0));
1795 }
1796
1797 static LLVMValueRef load_ubo(struct ac_shader_abi *abi, LLVMValueRef index)
1798 {
1799 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1800 LLVMValueRef ptr = LLVMGetParam(ctx->main_fn, ctx->param_const_and_shader_buffers);
1801
1802 index = si_llvm_bound_index(ctx, index, ctx->num_const_buffers);
1803 index = LLVMBuildAdd(ctx->gallivm.builder, index,
1804 LLVMConstInt(ctx->i32, SI_NUM_SHADER_BUFFERS, 0), "");
1805
1806 return ac_build_indexed_load_const(&ctx->ac, ptr, index);
1807 }
1808
1809 static LLVMValueRef fetch_constant(
1810 struct lp_build_tgsi_context *bld_base,
1811 const struct tgsi_full_src_register *reg,
1812 enum tgsi_opcode_type type,
1813 unsigned swizzle)
1814 {
1815 struct si_shader_context *ctx = si_shader_context(bld_base);
1816 struct lp_build_context *base = &bld_base->base;
1817 const struct tgsi_ind_register *ireg = &reg->Indirect;
1818 unsigned buf, idx;
1819
1820 LLVMValueRef addr, bufp;
1821 LLVMValueRef result;
1822
1823 if (swizzle == LP_CHAN_ALL) {
1824 unsigned chan;
1825 LLVMValueRef values[4];
1826 for (chan = 0; chan < TGSI_NUM_CHANNELS; ++chan)
1827 values[chan] = fetch_constant(bld_base, reg, type, chan);
1828
1829 return lp_build_gather_values(&ctx->gallivm, values, 4);
1830 }
1831
1832 buf = reg->Register.Dimension ? reg->Dimension.Index : 0;
1833 idx = reg->Register.Index * 4 + swizzle;
1834
1835 if (reg->Register.Dimension && reg->Dimension.Indirect) {
1836 LLVMValueRef ptr = LLVMGetParam(ctx->main_fn, ctx->param_const_and_shader_buffers);
1837 LLVMValueRef index;
1838 index = si_get_bounded_indirect_index(ctx, &reg->DimIndirect,
1839 reg->Dimension.Index,
1840 ctx->num_const_buffers);
1841 index = LLVMBuildAdd(ctx->gallivm.builder, index,
1842 LLVMConstInt(ctx->i32, SI_NUM_SHADER_BUFFERS, 0), "");
1843 bufp = ac_build_indexed_load_const(&ctx->ac, ptr, index);
1844 } else
1845 bufp = load_const_buffer_desc(ctx, buf);
1846
1847 if (reg->Register.Indirect) {
1848 addr = ctx->addrs[ireg->Index][ireg->Swizzle];
1849 addr = LLVMBuildLoad(base->gallivm->builder, addr, "load addr reg");
1850 addr = lp_build_mul_imm(&bld_base->uint_bld, addr, 16);
1851 addr = lp_build_add(&bld_base->uint_bld, addr,
1852 LLVMConstInt(ctx->i32, idx * 4, 0));
1853 } else {
1854 addr = LLVMConstInt(ctx->i32, idx * 4, 0);
1855 }
1856
1857 result = buffer_load_const(ctx, bufp, addr);
1858
1859 if (!tgsi_type_is_64bit(type))
1860 result = bitcast(bld_base, type, result);
1861 else {
1862 LLVMValueRef addr2, result2;
1863
1864 addr2 = lp_build_add(&bld_base->uint_bld, addr,
1865 LLVMConstInt(ctx->i32, 4, 0));
1866 result2 = buffer_load_const(ctx, bufp, addr2);
1867
1868 result = si_llvm_emit_fetch_64bit(bld_base, type,
1869 result, result2);
1870 }
1871 return result;
1872 }
1873
1874 /* Upper 16 bits must be zero. */
1875 static LLVMValueRef si_llvm_pack_two_int16(struct si_shader_context *ctx,
1876 LLVMValueRef val[2])
1877 {
1878 return LLVMBuildOr(ctx->gallivm.builder, val[0],
1879 LLVMBuildShl(ctx->gallivm.builder, val[1],
1880 LLVMConstInt(ctx->i32, 16, 0),
1881 ""), "");
1882 }
1883
1884 /* Upper 16 bits are ignored and will be dropped. */
1885 static LLVMValueRef si_llvm_pack_two_int32_as_int16(struct si_shader_context *ctx,
1886 LLVMValueRef val[2])
1887 {
1888 LLVMValueRef v[2] = {
1889 LLVMBuildAnd(ctx->gallivm.builder, val[0],
1890 LLVMConstInt(ctx->i32, 0xffff, 0), ""),
1891 val[1],
1892 };
1893 return si_llvm_pack_two_int16(ctx, v);
1894 }
1895
1896 /* Initialize arguments for the shader export intrinsic */
1897 static void si_llvm_init_export_args(struct lp_build_tgsi_context *bld_base,
1898 LLVMValueRef *values,
1899 unsigned target,
1900 struct ac_export_args *args)
1901 {
1902 struct si_shader_context *ctx = si_shader_context(bld_base);
1903 struct lp_build_context *base = &bld_base->base;
1904 LLVMBuilderRef builder = ctx->gallivm.builder;
1905 LLVMValueRef val[4];
1906 unsigned spi_shader_col_format = V_028714_SPI_SHADER_32_ABGR;
1907 unsigned chan;
1908 bool is_int8, is_int10;
1909
1910 /* Default is 0xf. Adjusted below depending on the format. */
1911 args->enabled_channels = 0xf; /* writemask */
1912
1913 /* Specify whether the EXEC mask represents the valid mask */
1914 args->valid_mask = 0;
1915
1916 /* Specify whether this is the last export */
1917 args->done = 0;
1918
1919 /* Specify the target we are exporting */
1920 args->target = target;
1921
1922 if (ctx->type == PIPE_SHADER_FRAGMENT) {
1923 const struct si_shader_key *key = &ctx->shader->key;
1924 unsigned col_formats = key->part.ps.epilog.spi_shader_col_format;
1925 int cbuf = target - V_008DFC_SQ_EXP_MRT;
1926
1927 assert(cbuf >= 0 && cbuf < 8);
1928 spi_shader_col_format = (col_formats >> (cbuf * 4)) & 0xf;
1929 is_int8 = (key->part.ps.epilog.color_is_int8 >> cbuf) & 0x1;
1930 is_int10 = (key->part.ps.epilog.color_is_int10 >> cbuf) & 0x1;
1931 }
1932
1933 args->compr = false;
1934 args->out[0] = base->undef;
1935 args->out[1] = base->undef;
1936 args->out[2] = base->undef;
1937 args->out[3] = base->undef;
1938
1939 switch (spi_shader_col_format) {
1940 case V_028714_SPI_SHADER_ZERO:
1941 args->enabled_channels = 0; /* writemask */
1942 args->target = V_008DFC_SQ_EXP_NULL;
1943 break;
1944
1945 case V_028714_SPI_SHADER_32_R:
1946 args->enabled_channels = 1; /* writemask */
1947 args->out[0] = values[0];
1948 break;
1949
1950 case V_028714_SPI_SHADER_32_GR:
1951 args->enabled_channels = 0x3; /* writemask */
1952 args->out[0] = values[0];
1953 args->out[1] = values[1];
1954 break;
1955
1956 case V_028714_SPI_SHADER_32_AR:
1957 args->enabled_channels = 0x9; /* writemask */
1958 args->out[0] = values[0];
1959 args->out[3] = values[3];
1960 break;
1961
1962 case V_028714_SPI_SHADER_FP16_ABGR:
1963 args->compr = 1; /* COMPR flag */
1964
1965 for (chan = 0; chan < 2; chan++) {
1966 LLVMValueRef pack_args[2] = {
1967 values[2 * chan],
1968 values[2 * chan + 1]
1969 };
1970 LLVMValueRef packed;
1971
1972 packed = ac_build_cvt_pkrtz_f16(&ctx->ac, pack_args);
1973 args->out[chan] =
1974 LLVMBuildBitCast(ctx->gallivm.builder,
1975 packed, ctx->f32, "");
1976 }
1977 break;
1978
1979 case V_028714_SPI_SHADER_UNORM16_ABGR:
1980 for (chan = 0; chan < 4; chan++) {
1981 val[chan] = ac_build_clamp(&ctx->ac, values[chan]);
1982 val[chan] = LLVMBuildFMul(builder, val[chan],
1983 LLVMConstReal(ctx->f32, 65535), "");
1984 val[chan] = LLVMBuildFAdd(builder, val[chan],
1985 LLVMConstReal(ctx->f32, 0.5), "");
1986 val[chan] = LLVMBuildFPToUI(builder, val[chan],
1987 ctx->i32, "");
1988 }
1989
1990 args->compr = 1; /* COMPR flag */
1991 args->out[0] = bitcast(bld_base, TGSI_TYPE_FLOAT,
1992 si_llvm_pack_two_int16(ctx, val));
1993 args->out[1] = bitcast(bld_base, TGSI_TYPE_FLOAT,
1994 si_llvm_pack_two_int16(ctx, val+2));
1995 break;
1996
1997 case V_028714_SPI_SHADER_SNORM16_ABGR:
1998 for (chan = 0; chan < 4; chan++) {
1999 /* Clamp between [-1, 1]. */
2000 val[chan] = lp_build_emit_llvm_binary(bld_base, TGSI_OPCODE_MIN,
2001 values[chan],
2002 LLVMConstReal(ctx->f32, 1));
2003 val[chan] = lp_build_emit_llvm_binary(bld_base, TGSI_OPCODE_MAX,
2004 val[chan],
2005 LLVMConstReal(ctx->f32, -1));
2006 /* Convert to a signed integer in [-32767, 32767]. */
2007 val[chan] = LLVMBuildFMul(builder, val[chan],
2008 LLVMConstReal(ctx->f32, 32767), "");
2009 /* If positive, add 0.5, else add -0.5. */
2010 val[chan] = LLVMBuildFAdd(builder, val[chan],
2011 LLVMBuildSelect(builder,
2012 LLVMBuildFCmp(builder, LLVMRealOGE,
2013 val[chan], base->zero, ""),
2014 LLVMConstReal(ctx->f32, 0.5),
2015 LLVMConstReal(ctx->f32, -0.5), ""), "");
2016 val[chan] = LLVMBuildFPToSI(builder, val[chan], ctx->i32, "");
2017 }
2018
2019 args->compr = 1; /* COMPR flag */
2020 args->out[0] = bitcast(bld_base, TGSI_TYPE_FLOAT,
2021 si_llvm_pack_two_int32_as_int16(ctx, val));
2022 args->out[1] = bitcast(bld_base, TGSI_TYPE_FLOAT,
2023 si_llvm_pack_two_int32_as_int16(ctx, val+2));
2024 break;
2025
2026 case V_028714_SPI_SHADER_UINT16_ABGR: {
2027 LLVMValueRef max_rgb = LLVMConstInt(ctx->i32,
2028 is_int8 ? 255 : is_int10 ? 1023 : 65535, 0);
2029 LLVMValueRef max_alpha =
2030 !is_int10 ? max_rgb : LLVMConstInt(ctx->i32, 3, 0);
2031
2032 /* Clamp. */
2033 for (chan = 0; chan < 4; chan++) {
2034 val[chan] = bitcast(bld_base, TGSI_TYPE_UNSIGNED, values[chan]);
2035 val[chan] = lp_build_emit_llvm_binary(bld_base, TGSI_OPCODE_UMIN,
2036 val[chan],
2037 chan == 3 ? max_alpha : max_rgb);
2038 }
2039
2040 args->compr = 1; /* COMPR flag */
2041 args->out[0] = bitcast(bld_base, TGSI_TYPE_FLOAT,
2042 si_llvm_pack_two_int16(ctx, val));
2043 args->out[1] = bitcast(bld_base, TGSI_TYPE_FLOAT,
2044 si_llvm_pack_two_int16(ctx, val+2));
2045 break;
2046 }
2047
2048 case V_028714_SPI_SHADER_SINT16_ABGR: {
2049 LLVMValueRef max_rgb = LLVMConstInt(ctx->i32,
2050 is_int8 ? 127 : is_int10 ? 511 : 32767, 0);
2051 LLVMValueRef min_rgb = LLVMConstInt(ctx->i32,
2052 is_int8 ? -128 : is_int10 ? -512 : -32768, 0);
2053 LLVMValueRef max_alpha =
2054 !is_int10 ? max_rgb : ctx->i32_1;
2055 LLVMValueRef min_alpha =
2056 !is_int10 ? min_rgb : LLVMConstInt(ctx->i32, -2, 0);
2057
2058 /* Clamp. */
2059 for (chan = 0; chan < 4; chan++) {
2060 val[chan] = bitcast(bld_base, TGSI_TYPE_UNSIGNED, values[chan]);
2061 val[chan] = lp_build_emit_llvm_binary(bld_base,
2062 TGSI_OPCODE_IMIN,
2063 val[chan], chan == 3 ? max_alpha : max_rgb);
2064 val[chan] = lp_build_emit_llvm_binary(bld_base,
2065 TGSI_OPCODE_IMAX,
2066 val[chan], chan == 3 ? min_alpha : min_rgb);
2067 }
2068
2069 args->compr = 1; /* COMPR flag */
2070 args->out[0] = bitcast(bld_base, TGSI_TYPE_FLOAT,
2071 si_llvm_pack_two_int32_as_int16(ctx, val));
2072 args->out[1] = bitcast(bld_base, TGSI_TYPE_FLOAT,
2073 si_llvm_pack_two_int32_as_int16(ctx, val+2));
2074 break;
2075 }
2076
2077 case V_028714_SPI_SHADER_32_ABGR:
2078 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
2079 break;
2080 }
2081 }
2082
2083 static void si_alpha_test(struct lp_build_tgsi_context *bld_base,
2084 LLVMValueRef alpha)
2085 {
2086 struct si_shader_context *ctx = si_shader_context(bld_base);
2087
2088 if (ctx->shader->key.part.ps.epilog.alpha_func != PIPE_FUNC_NEVER) {
2089 LLVMValueRef alpha_ref = LLVMGetParam(ctx->main_fn,
2090 SI_PARAM_ALPHA_REF);
2091
2092 LLVMValueRef alpha_pass =
2093 lp_build_cmp(&bld_base->base,
2094 ctx->shader->key.part.ps.epilog.alpha_func,
2095 alpha, alpha_ref);
2096 LLVMValueRef arg =
2097 lp_build_select(&bld_base->base,
2098 alpha_pass,
2099 LLVMConstReal(ctx->f32, 1.0f),
2100 LLVMConstReal(ctx->f32, -1.0f));
2101
2102 ac_build_kill(&ctx->ac, arg);
2103 } else {
2104 ac_build_kill(&ctx->ac, NULL);
2105 }
2106 }
2107
2108 static LLVMValueRef si_scale_alpha_by_sample_mask(struct lp_build_tgsi_context *bld_base,
2109 LLVMValueRef alpha,
2110 unsigned samplemask_param)
2111 {
2112 struct si_shader_context *ctx = si_shader_context(bld_base);
2113 struct gallivm_state *gallivm = &ctx->gallivm;
2114 LLVMValueRef coverage;
2115
2116 /* alpha = alpha * popcount(coverage) / SI_NUM_SMOOTH_AA_SAMPLES */
2117 coverage = LLVMGetParam(ctx->main_fn,
2118 samplemask_param);
2119 coverage = bitcast(bld_base, TGSI_TYPE_SIGNED, coverage);
2120
2121 coverage = lp_build_intrinsic(gallivm->builder, "llvm.ctpop.i32",
2122 ctx->i32,
2123 &coverage, 1, LP_FUNC_ATTR_READNONE);
2124
2125 coverage = LLVMBuildUIToFP(gallivm->builder, coverage,
2126 ctx->f32, "");
2127
2128 coverage = LLVMBuildFMul(gallivm->builder, coverage,
2129 LLVMConstReal(ctx->f32,
2130 1.0 / SI_NUM_SMOOTH_AA_SAMPLES), "");
2131
2132 return LLVMBuildFMul(gallivm->builder, alpha, coverage, "");
2133 }
2134
2135 static void si_llvm_emit_clipvertex(struct lp_build_tgsi_context *bld_base,
2136 struct ac_export_args *pos, LLVMValueRef *out_elts)
2137 {
2138 struct si_shader_context *ctx = si_shader_context(bld_base);
2139 struct lp_build_context *base = &bld_base->base;
2140 unsigned reg_index;
2141 unsigned chan;
2142 unsigned const_chan;
2143 LLVMValueRef base_elt;
2144 LLVMValueRef ptr = LLVMGetParam(ctx->main_fn, ctx->param_rw_buffers);
2145 LLVMValueRef constbuf_index = LLVMConstInt(ctx->i32,
2146 SI_VS_CONST_CLIP_PLANES, 0);
2147 LLVMValueRef const_resource = ac_build_indexed_load_const(&ctx->ac, ptr, constbuf_index);
2148
2149 for (reg_index = 0; reg_index < 2; reg_index ++) {
2150 struct ac_export_args *args = &pos[2 + reg_index];
2151
2152 args->out[0] =
2153 args->out[1] =
2154 args->out[2] =
2155 args->out[3] = LLVMConstReal(ctx->f32, 0.0f);
2156
2157 /* Compute dot products of position and user clip plane vectors */
2158 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2159 for (const_chan = 0; const_chan < TGSI_NUM_CHANNELS; const_chan++) {
2160 LLVMValueRef addr =
2161 LLVMConstInt(ctx->i32, ((reg_index * 4 + chan) * 4 +
2162 const_chan) * 4, 0);
2163 base_elt = buffer_load_const(ctx, const_resource,
2164 addr);
2165 args->out[chan] =
2166 lp_build_add(base, args->out[chan],
2167 lp_build_mul(base, base_elt,
2168 out_elts[const_chan]));
2169 }
2170 }
2171
2172 args->enabled_channels = 0xf;
2173 args->valid_mask = 0;
2174 args->done = 0;
2175 args->target = V_008DFC_SQ_EXP_POS + 2 + reg_index;
2176 args->compr = 0;
2177 }
2178 }
2179
2180 static void si_dump_streamout(struct pipe_stream_output_info *so)
2181 {
2182 unsigned i;
2183
2184 if (so->num_outputs)
2185 fprintf(stderr, "STREAMOUT\n");
2186
2187 for (i = 0; i < so->num_outputs; i++) {
2188 unsigned mask = ((1 << so->output[i].num_components) - 1) <<
2189 so->output[i].start_component;
2190 fprintf(stderr, " %i: BUF%i[%i..%i] <- OUT[%i].%s%s%s%s\n",
2191 i, so->output[i].output_buffer,
2192 so->output[i].dst_offset, so->output[i].dst_offset + so->output[i].num_components - 1,
2193 so->output[i].register_index,
2194 mask & 1 ? "x" : "",
2195 mask & 2 ? "y" : "",
2196 mask & 4 ? "z" : "",
2197 mask & 8 ? "w" : "");
2198 }
2199 }
2200
2201 static void emit_streamout_output(struct si_shader_context *ctx,
2202 LLVMValueRef const *so_buffers,
2203 LLVMValueRef const *so_write_offsets,
2204 struct pipe_stream_output *stream_out,
2205 struct si_shader_output_values *shader_out)
2206 {
2207 struct gallivm_state *gallivm = &ctx->gallivm;
2208 LLVMBuilderRef builder = gallivm->builder;
2209 unsigned buf_idx = stream_out->output_buffer;
2210 unsigned start = stream_out->start_component;
2211 unsigned num_comps = stream_out->num_components;
2212 LLVMValueRef out[4];
2213
2214 assert(num_comps && num_comps <= 4);
2215 if (!num_comps || num_comps > 4)
2216 return;
2217
2218 /* Load the output as int. */
2219 for (int j = 0; j < num_comps; j++) {
2220 assert(stream_out->stream == shader_out->vertex_stream[start + j]);
2221
2222 out[j] = LLVMBuildBitCast(builder,
2223 shader_out->values[start + j],
2224 ctx->i32, "");
2225 }
2226
2227 /* Pack the output. */
2228 LLVMValueRef vdata = NULL;
2229
2230 switch (num_comps) {
2231 case 1: /* as i32 */
2232 vdata = out[0];
2233 break;
2234 case 2: /* as v2i32 */
2235 case 3: /* as v4i32 (aligned to 4) */
2236 case 4: /* as v4i32 */
2237 vdata = LLVMGetUndef(LLVMVectorType(ctx->i32, util_next_power_of_two(num_comps)));
2238 for (int j = 0; j < num_comps; j++) {
2239 vdata = LLVMBuildInsertElement(builder, vdata, out[j],
2240 LLVMConstInt(ctx->i32, j, 0), "");
2241 }
2242 break;
2243 }
2244
2245 ac_build_buffer_store_dword(&ctx->ac, so_buffers[buf_idx],
2246 vdata, num_comps,
2247 so_write_offsets[buf_idx],
2248 ctx->i32_0,
2249 stream_out->dst_offset * 4, 1, 1, true, false);
2250 }
2251
2252 /**
2253 * Write streamout data to buffers for vertex stream @p stream (different
2254 * vertex streams can occur for GS copy shaders).
2255 */
2256 static void si_llvm_emit_streamout(struct si_shader_context *ctx,
2257 struct si_shader_output_values *outputs,
2258 unsigned noutput, unsigned stream)
2259 {
2260 struct si_shader_selector *sel = ctx->shader->selector;
2261 struct pipe_stream_output_info *so = &sel->so;
2262 struct gallivm_state *gallivm = &ctx->gallivm;
2263 LLVMBuilderRef builder = gallivm->builder;
2264 int i;
2265 struct lp_build_if_state if_ctx;
2266
2267 /* Get bits [22:16], i.e. (so_param >> 16) & 127; */
2268 LLVMValueRef so_vtx_count =
2269 unpack_param(ctx, ctx->param_streamout_config, 16, 7);
2270
2271 LLVMValueRef tid = ac_get_thread_id(&ctx->ac);
2272
2273 /* can_emit = tid < so_vtx_count; */
2274 LLVMValueRef can_emit =
2275 LLVMBuildICmp(builder, LLVMIntULT, tid, so_vtx_count, "");
2276
2277 /* Emit the streamout code conditionally. This actually avoids
2278 * out-of-bounds buffer access. The hw tells us via the SGPR
2279 * (so_vtx_count) which threads are allowed to emit streamout data. */
2280 lp_build_if(&if_ctx, gallivm, can_emit);
2281 {
2282 /* The buffer offset is computed as follows:
2283 * ByteOffset = streamout_offset[buffer_id]*4 +
2284 * (streamout_write_index + thread_id)*stride[buffer_id] +
2285 * attrib_offset
2286 */
2287
2288 LLVMValueRef so_write_index =
2289 LLVMGetParam(ctx->main_fn,
2290 ctx->param_streamout_write_index);
2291
2292 /* Compute (streamout_write_index + thread_id). */
2293 so_write_index = LLVMBuildAdd(builder, so_write_index, tid, "");
2294
2295 /* Load the descriptor and compute the write offset for each
2296 * enabled buffer. */
2297 LLVMValueRef so_write_offset[4] = {};
2298 LLVMValueRef so_buffers[4];
2299 LLVMValueRef buf_ptr = LLVMGetParam(ctx->main_fn,
2300 ctx->param_rw_buffers);
2301
2302 for (i = 0; i < 4; i++) {
2303 if (!so->stride[i])
2304 continue;
2305
2306 LLVMValueRef offset = LLVMConstInt(ctx->i32,
2307 SI_VS_STREAMOUT_BUF0 + i, 0);
2308
2309 so_buffers[i] = ac_build_indexed_load_const(&ctx->ac, buf_ptr, offset);
2310
2311 LLVMValueRef so_offset = LLVMGetParam(ctx->main_fn,
2312 ctx->param_streamout_offset[i]);
2313 so_offset = LLVMBuildMul(builder, so_offset, LLVMConstInt(ctx->i32, 4, 0), "");
2314
2315 so_write_offset[i] = LLVMBuildMul(builder, so_write_index,
2316 LLVMConstInt(ctx->i32, so->stride[i]*4, 0), "");
2317 so_write_offset[i] = LLVMBuildAdd(builder, so_write_offset[i], so_offset, "");
2318 }
2319
2320 /* Write streamout data. */
2321 for (i = 0; i < so->num_outputs; i++) {
2322 unsigned reg = so->output[i].register_index;
2323
2324 if (reg >= noutput)
2325 continue;
2326
2327 if (stream != so->output[i].stream)
2328 continue;
2329
2330 emit_streamout_output(ctx, so_buffers, so_write_offset,
2331 &so->output[i], &outputs[reg]);
2332 }
2333 }
2334 lp_build_endif(&if_ctx);
2335 }
2336
2337 static void si_export_param(struct si_shader_context *ctx, unsigned index,
2338 LLVMValueRef *values)
2339 {
2340 struct ac_export_args args;
2341
2342 si_llvm_init_export_args(&ctx->bld_base, values,
2343 V_008DFC_SQ_EXP_PARAM + index, &args);
2344 ac_build_export(&ctx->ac, &args);
2345 }
2346
2347 static void si_build_param_exports(struct si_shader_context *ctx,
2348 struct si_shader_output_values *outputs,
2349 unsigned noutput)
2350 {
2351 struct si_shader *shader = ctx->shader;
2352 unsigned param_count = 0;
2353
2354 for (unsigned i = 0; i < noutput; i++) {
2355 unsigned semantic_name = outputs[i].semantic_name;
2356 unsigned semantic_index = outputs[i].semantic_index;
2357
2358 if (outputs[i].vertex_stream[0] != 0 &&
2359 outputs[i].vertex_stream[1] != 0 &&
2360 outputs[i].vertex_stream[2] != 0 &&
2361 outputs[i].vertex_stream[3] != 0)
2362 continue;
2363
2364 switch (semantic_name) {
2365 case TGSI_SEMANTIC_LAYER:
2366 case TGSI_SEMANTIC_VIEWPORT_INDEX:
2367 case TGSI_SEMANTIC_CLIPDIST:
2368 case TGSI_SEMANTIC_COLOR:
2369 case TGSI_SEMANTIC_BCOLOR:
2370 case TGSI_SEMANTIC_PRIMID:
2371 case TGSI_SEMANTIC_FOG:
2372 case TGSI_SEMANTIC_TEXCOORD:
2373 case TGSI_SEMANTIC_GENERIC:
2374 break;
2375 default:
2376 continue;
2377 }
2378
2379 if ((semantic_name != TGSI_SEMANTIC_GENERIC ||
2380 semantic_index < SI_MAX_IO_GENERIC) &&
2381 shader->key.opt.kill_outputs &
2382 (1ull << si_shader_io_get_unique_index(semantic_name, semantic_index)))
2383 continue;
2384
2385 si_export_param(ctx, param_count, outputs[i].values);
2386
2387 assert(i < ARRAY_SIZE(shader->info.vs_output_param_offset));
2388 shader->info.vs_output_param_offset[i] = param_count++;
2389 }
2390
2391 shader->info.nr_param_exports = param_count;
2392 }
2393
2394 /* Generate export instructions for hardware VS shader stage */
2395 static void si_llvm_export_vs(struct lp_build_tgsi_context *bld_base,
2396 struct si_shader_output_values *outputs,
2397 unsigned noutput)
2398 {
2399 struct si_shader_context *ctx = si_shader_context(bld_base);
2400 struct si_shader *shader = ctx->shader;
2401 struct lp_build_context *base = &bld_base->base;
2402 struct ac_export_args pos_args[4] = {};
2403 LLVMValueRef psize_value = NULL, edgeflag_value = NULL, layer_value = NULL, viewport_index_value = NULL;
2404 unsigned pos_idx;
2405 int i;
2406
2407 /* Build position exports. */
2408 for (i = 0; i < noutput; i++) {
2409 switch (outputs[i].semantic_name) {
2410 case TGSI_SEMANTIC_POSITION:
2411 si_llvm_init_export_args(bld_base, outputs[i].values,
2412 V_008DFC_SQ_EXP_POS, &pos_args[0]);
2413 break;
2414 case TGSI_SEMANTIC_PSIZE:
2415 psize_value = outputs[i].values[0];
2416 break;
2417 case TGSI_SEMANTIC_LAYER:
2418 layer_value = outputs[i].values[0];
2419 break;
2420 case TGSI_SEMANTIC_VIEWPORT_INDEX:
2421 viewport_index_value = outputs[i].values[0];
2422 break;
2423 case TGSI_SEMANTIC_EDGEFLAG:
2424 edgeflag_value = outputs[i].values[0];
2425 break;
2426 case TGSI_SEMANTIC_CLIPDIST:
2427 if (!shader->key.opt.clip_disable) {
2428 unsigned index = 2 + outputs[i].semantic_index;
2429 si_llvm_init_export_args(bld_base, outputs[i].values,
2430 V_008DFC_SQ_EXP_POS + index,
2431 &pos_args[index]);
2432 }
2433 break;
2434 case TGSI_SEMANTIC_CLIPVERTEX:
2435 if (!shader->key.opt.clip_disable) {
2436 si_llvm_emit_clipvertex(bld_base, pos_args,
2437 outputs[i].values);
2438 }
2439 break;
2440 }
2441 }
2442
2443 /* We need to add the position output manually if it's missing. */
2444 if (!pos_args[0].out[0]) {
2445 pos_args[0].enabled_channels = 0xf; /* writemask */
2446 pos_args[0].valid_mask = 0; /* EXEC mask */
2447 pos_args[0].done = 0; /* last export? */
2448 pos_args[0].target = V_008DFC_SQ_EXP_POS;
2449 pos_args[0].compr = 0; /* COMPR flag */
2450 pos_args[0].out[0] = base->zero; /* X */
2451 pos_args[0].out[1] = base->zero; /* Y */
2452 pos_args[0].out[2] = base->zero; /* Z */
2453 pos_args[0].out[3] = base->one; /* W */
2454 }
2455
2456 /* Write the misc vector (point size, edgeflag, layer, viewport). */
2457 if (shader->selector->info.writes_psize ||
2458 shader->selector->info.writes_edgeflag ||
2459 shader->selector->info.writes_viewport_index ||
2460 shader->selector->info.writes_layer) {
2461 pos_args[1].enabled_channels = shader->selector->info.writes_psize |
2462 (shader->selector->info.writes_edgeflag << 1) |
2463 (shader->selector->info.writes_layer << 2);
2464
2465 pos_args[1].valid_mask = 0; /* EXEC mask */
2466 pos_args[1].done = 0; /* last export? */
2467 pos_args[1].target = V_008DFC_SQ_EXP_POS + 1;
2468 pos_args[1].compr = 0; /* COMPR flag */
2469 pos_args[1].out[0] = base->zero; /* X */
2470 pos_args[1].out[1] = base->zero; /* Y */
2471 pos_args[1].out[2] = base->zero; /* Z */
2472 pos_args[1].out[3] = base->zero; /* W */
2473
2474 if (shader->selector->info.writes_psize)
2475 pos_args[1].out[0] = psize_value;
2476
2477 if (shader->selector->info.writes_edgeflag) {
2478 /* The output is a float, but the hw expects an integer
2479 * with the first bit containing the edge flag. */
2480 edgeflag_value = LLVMBuildFPToUI(ctx->gallivm.builder,
2481 edgeflag_value,
2482 ctx->i32, "");
2483 edgeflag_value = lp_build_min(&bld_base->int_bld,
2484 edgeflag_value,
2485 ctx->i32_1);
2486
2487 /* The LLVM intrinsic expects a float. */
2488 pos_args[1].out[1] = LLVMBuildBitCast(ctx->gallivm.builder,
2489 edgeflag_value,
2490 ctx->f32, "");
2491 }
2492
2493 if (ctx->screen->b.chip_class >= GFX9) {
2494 /* GFX9 has the layer in out.z[10:0] and the viewport
2495 * index in out.z[19:16].
2496 */
2497 if (shader->selector->info.writes_layer)
2498 pos_args[1].out[2] = layer_value;
2499
2500 if (shader->selector->info.writes_viewport_index) {
2501 LLVMValueRef v = viewport_index_value;
2502
2503 v = bitcast(bld_base, TGSI_TYPE_UNSIGNED, v);
2504 v = LLVMBuildShl(ctx->gallivm.builder, v,
2505 LLVMConstInt(ctx->i32, 16, 0), "");
2506 v = LLVMBuildOr(ctx->gallivm.builder, v,
2507 bitcast(bld_base, TGSI_TYPE_UNSIGNED,
2508 pos_args[1].out[2]), "");
2509 pos_args[1].out[2] = bitcast(bld_base, TGSI_TYPE_FLOAT, v);
2510 pos_args[1].enabled_channels |= 1 << 2;
2511 }
2512 } else {
2513 if (shader->selector->info.writes_layer)
2514 pos_args[1].out[2] = layer_value;
2515
2516 if (shader->selector->info.writes_viewport_index) {
2517 pos_args[1].out[3] = viewport_index_value;
2518 pos_args[1].enabled_channels |= 1 << 3;
2519 }
2520 }
2521 }
2522
2523 for (i = 0; i < 4; i++)
2524 if (pos_args[i].out[0])
2525 shader->info.nr_pos_exports++;
2526
2527 pos_idx = 0;
2528 for (i = 0; i < 4; i++) {
2529 if (!pos_args[i].out[0])
2530 continue;
2531
2532 /* Specify the target we are exporting */
2533 pos_args[i].target = V_008DFC_SQ_EXP_POS + pos_idx++;
2534
2535 if (pos_idx == shader->info.nr_pos_exports)
2536 /* Specify that this is the last export */
2537 pos_args[i].done = 1;
2538
2539 ac_build_export(&ctx->ac, &pos_args[i]);
2540 }
2541
2542 /* Build parameter exports. */
2543 si_build_param_exports(ctx, outputs, noutput);
2544 }
2545
2546 /**
2547 * Forward all outputs from the vertex shader to the TES. This is only used
2548 * for the fixed function TCS.
2549 */
2550 static void si_copy_tcs_inputs(struct lp_build_tgsi_context *bld_base)
2551 {
2552 struct si_shader_context *ctx = si_shader_context(bld_base);
2553 struct gallivm_state *gallivm = &ctx->gallivm;
2554 LLVMValueRef invocation_id, buffer, buffer_offset;
2555 LLVMValueRef lds_vertex_stride, lds_vertex_offset, lds_base;
2556 uint64_t inputs;
2557
2558 invocation_id = unpack_param(ctx, ctx->param_tcs_rel_ids, 8, 5);
2559 buffer = desc_from_addr_base64k(ctx, ctx->param_tcs_offchip_addr_base64k);
2560 buffer_offset = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
2561
2562 lds_vertex_stride = unpack_param(ctx, ctx->param_vs_state_bits, 24, 8);
2563 lds_vertex_offset = LLVMBuildMul(gallivm->builder, invocation_id,
2564 lds_vertex_stride, "");
2565 lds_base = get_tcs_in_current_patch_offset(ctx);
2566 lds_base = LLVMBuildAdd(gallivm->builder, lds_base, lds_vertex_offset, "");
2567
2568 inputs = ctx->shader->key.mono.u.ff_tcs_inputs_to_copy;
2569 while (inputs) {
2570 unsigned i = u_bit_scan64(&inputs);
2571
2572 LLVMValueRef lds_ptr = LLVMBuildAdd(gallivm->builder, lds_base,
2573 LLVMConstInt(ctx->i32, 4 * i, 0),
2574 "");
2575
2576 LLVMValueRef buffer_addr = get_tcs_tes_buffer_address(ctx,
2577 get_rel_patch_id(ctx),
2578 invocation_id,
2579 LLVMConstInt(ctx->i32, i, 0));
2580
2581 LLVMValueRef value = lds_load(bld_base, TGSI_TYPE_SIGNED, ~0,
2582 lds_ptr);
2583
2584 ac_build_buffer_store_dword(&ctx->ac, buffer, value, 4, buffer_addr,
2585 buffer_offset, 0, 1, 0, true, false);
2586 }
2587 }
2588
2589 static void si_write_tess_factors(struct lp_build_tgsi_context *bld_base,
2590 LLVMValueRef rel_patch_id,
2591 LLVMValueRef invocation_id,
2592 LLVMValueRef tcs_out_current_patch_data_offset)
2593 {
2594 struct si_shader_context *ctx = si_shader_context(bld_base);
2595 struct gallivm_state *gallivm = &ctx->gallivm;
2596 struct si_shader *shader = ctx->shader;
2597 unsigned tess_inner_index, tess_outer_index;
2598 LLVMValueRef lds_base, lds_inner, lds_outer, byteoffset, buffer;
2599 LLVMValueRef out[6], vec0, vec1, tf_base, inner[4], outer[4];
2600 unsigned stride, outer_comps, inner_comps, i, offset;
2601 struct lp_build_if_state if_ctx, inner_if_ctx;
2602
2603 si_llvm_emit_barrier(NULL, bld_base, NULL);
2604
2605 /* Do this only for invocation 0, because the tess levels are per-patch,
2606 * not per-vertex.
2607 *
2608 * This can't jump, because invocation 0 executes this. It should
2609 * at least mask out the loads and stores for other invocations.
2610 */
2611 lp_build_if(&if_ctx, gallivm,
2612 LLVMBuildICmp(gallivm->builder, LLVMIntEQ,
2613 invocation_id, ctx->i32_0, ""));
2614
2615 /* Determine the layout of one tess factor element in the buffer. */
2616 switch (shader->key.part.tcs.epilog.prim_mode) {
2617 case PIPE_PRIM_LINES:
2618 stride = 2; /* 2 dwords, 1 vec2 store */
2619 outer_comps = 2;
2620 inner_comps = 0;
2621 break;
2622 case PIPE_PRIM_TRIANGLES:
2623 stride = 4; /* 4 dwords, 1 vec4 store */
2624 outer_comps = 3;
2625 inner_comps = 1;
2626 break;
2627 case PIPE_PRIM_QUADS:
2628 stride = 6; /* 6 dwords, 2 stores (vec4 + vec2) */
2629 outer_comps = 4;
2630 inner_comps = 2;
2631 break;
2632 default:
2633 assert(0);
2634 return;
2635 }
2636
2637 /* Load tess_inner and tess_outer from LDS.
2638 * Any invocation can write them, so we can't get them from a temporary.
2639 */
2640 tess_inner_index = si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSINNER, 0);
2641 tess_outer_index = si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSOUTER, 0);
2642
2643 lds_base = tcs_out_current_patch_data_offset;
2644 lds_inner = LLVMBuildAdd(gallivm->builder, lds_base,
2645 LLVMConstInt(ctx->i32,
2646 tess_inner_index * 4, 0), "");
2647 lds_outer = LLVMBuildAdd(gallivm->builder, lds_base,
2648 LLVMConstInt(ctx->i32,
2649 tess_outer_index * 4, 0), "");
2650
2651 for (i = 0; i < 4; i++) {
2652 inner[i] = LLVMGetUndef(ctx->i32);
2653 outer[i] = LLVMGetUndef(ctx->i32);
2654 }
2655
2656 if (shader->key.part.tcs.epilog.prim_mode == PIPE_PRIM_LINES) {
2657 /* For isolines, the hardware expects tess factors in the
2658 * reverse order from what GLSL / TGSI specify.
2659 */
2660 outer[0] = out[1] = lds_load(bld_base, TGSI_TYPE_SIGNED, 0, lds_outer);
2661 outer[1] = out[0] = lds_load(bld_base, TGSI_TYPE_SIGNED, 1, lds_outer);
2662 } else {
2663 for (i = 0; i < outer_comps; i++) {
2664 outer[i] = out[i] =
2665 lds_load(bld_base, TGSI_TYPE_SIGNED, i, lds_outer);
2666 }
2667 for (i = 0; i < inner_comps; i++) {
2668 inner[i] = out[outer_comps+i] =
2669 lds_load(bld_base, TGSI_TYPE_SIGNED, i, lds_inner);
2670 }
2671 }
2672
2673 /* Convert the outputs to vectors for stores. */
2674 vec0 = lp_build_gather_values(gallivm, out, MIN2(stride, 4));
2675 vec1 = NULL;
2676
2677 if (stride > 4)
2678 vec1 = lp_build_gather_values(gallivm, out+4, stride - 4);
2679
2680 /* Get the buffer. */
2681 buffer = desc_from_addr_base64k(ctx, ctx->param_tcs_factor_addr_base64k);
2682
2683 /* Get the offset. */
2684 tf_base = LLVMGetParam(ctx->main_fn,
2685 ctx->param_tcs_factor_offset);
2686 byteoffset = LLVMBuildMul(gallivm->builder, rel_patch_id,
2687 LLVMConstInt(ctx->i32, 4 * stride, 0), "");
2688
2689 lp_build_if(&inner_if_ctx, gallivm,
2690 LLVMBuildICmp(gallivm->builder, LLVMIntEQ,
2691 rel_patch_id, ctx->i32_0, ""));
2692
2693 /* Store the dynamic HS control word. */
2694 offset = 0;
2695 if (ctx->screen->b.chip_class <= VI) {
2696 ac_build_buffer_store_dword(&ctx->ac, buffer,
2697 LLVMConstInt(ctx->i32, 0x80000000, 0),
2698 1, ctx->i32_0, tf_base,
2699 offset, 1, 0, true, false);
2700 offset += 4;
2701 }
2702
2703 lp_build_endif(&inner_if_ctx);
2704
2705 /* Store the tessellation factors. */
2706 ac_build_buffer_store_dword(&ctx->ac, buffer, vec0,
2707 MIN2(stride, 4), byteoffset, tf_base,
2708 offset, 1, 0, true, false);
2709 offset += 16;
2710 if (vec1)
2711 ac_build_buffer_store_dword(&ctx->ac, buffer, vec1,
2712 stride - 4, byteoffset, tf_base,
2713 offset, 1, 0, true, false);
2714
2715 /* Store the tess factors into the offchip buffer if TES reads them. */
2716 if (shader->key.part.tcs.epilog.tes_reads_tess_factors) {
2717 LLVMValueRef buf, base, inner_vec, outer_vec, tf_outer_offset;
2718 LLVMValueRef tf_inner_offset;
2719 unsigned param_outer, param_inner;
2720
2721 buf = desc_from_addr_base64k(ctx, ctx->param_tcs_offchip_addr_base64k);
2722 base = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
2723
2724 param_outer = si_shader_io_get_unique_index_patch(
2725 TGSI_SEMANTIC_TESSOUTER, 0);
2726 tf_outer_offset = get_tcs_tes_buffer_address(ctx, rel_patch_id, NULL,
2727 LLVMConstInt(ctx->i32, param_outer, 0));
2728
2729 outer_vec = lp_build_gather_values(gallivm, outer,
2730 util_next_power_of_two(outer_comps));
2731
2732 ac_build_buffer_store_dword(&ctx->ac, buf, outer_vec,
2733 outer_comps, tf_outer_offset,
2734 base, 0, 1, 0, true, false);
2735 if (inner_comps) {
2736 param_inner = si_shader_io_get_unique_index_patch(
2737 TGSI_SEMANTIC_TESSINNER, 0);
2738 tf_inner_offset = get_tcs_tes_buffer_address(ctx, rel_patch_id, NULL,
2739 LLVMConstInt(ctx->i32, param_inner, 0));
2740
2741 inner_vec = inner_comps == 1 ? inner[0] :
2742 lp_build_gather_values(gallivm, inner, inner_comps);
2743 ac_build_buffer_store_dword(&ctx->ac, buf, inner_vec,
2744 inner_comps, tf_inner_offset,
2745 base, 0, 1, 0, true, false);
2746 }
2747 }
2748
2749 lp_build_endif(&if_ctx);
2750 }
2751
2752 static LLVMValueRef
2753 si_insert_input_ret(struct si_shader_context *ctx, LLVMValueRef ret,
2754 unsigned param, unsigned return_index)
2755 {
2756 return LLVMBuildInsertValue(ctx->gallivm.builder, ret,
2757 LLVMGetParam(ctx->main_fn, param),
2758 return_index, "");
2759 }
2760
2761 static LLVMValueRef
2762 si_insert_input_ret_float(struct si_shader_context *ctx, LLVMValueRef ret,
2763 unsigned param, unsigned return_index)
2764 {
2765 LLVMBuilderRef builder = ctx->gallivm.builder;
2766 LLVMValueRef p = LLVMGetParam(ctx->main_fn, param);
2767
2768 return LLVMBuildInsertValue(builder, ret,
2769 LLVMBuildBitCast(builder, p, ctx->f32, ""),
2770 return_index, "");
2771 }
2772
2773 static LLVMValueRef
2774 si_insert_input_ptr_as_2xi32(struct si_shader_context *ctx, LLVMValueRef ret,
2775 unsigned param, unsigned return_index)
2776 {
2777 LLVMBuilderRef builder = ctx->gallivm.builder;
2778 LLVMValueRef ptr, lo, hi;
2779
2780 ptr = LLVMGetParam(ctx->main_fn, param);
2781 ptr = LLVMBuildPtrToInt(builder, ptr, ctx->i64, "");
2782 ptr = LLVMBuildBitCast(builder, ptr, ctx->v2i32, "");
2783 lo = LLVMBuildExtractElement(builder, ptr, ctx->i32_0, "");
2784 hi = LLVMBuildExtractElement(builder, ptr, ctx->i32_1, "");
2785 ret = LLVMBuildInsertValue(builder, ret, lo, return_index, "");
2786 return LLVMBuildInsertValue(builder, ret, hi, return_index + 1, "");
2787 }
2788
2789 /* This only writes the tessellation factor levels. */
2790 static void si_llvm_emit_tcs_epilogue(struct lp_build_tgsi_context *bld_base)
2791 {
2792 struct si_shader_context *ctx = si_shader_context(bld_base);
2793 LLVMBuilderRef builder = ctx->gallivm.builder;
2794 LLVMValueRef rel_patch_id, invocation_id, tf_lds_offset;
2795
2796 si_copy_tcs_inputs(bld_base);
2797
2798 rel_patch_id = get_rel_patch_id(ctx);
2799 invocation_id = unpack_param(ctx, ctx->param_tcs_rel_ids, 8, 5);
2800 tf_lds_offset = get_tcs_out_current_patch_data_offset(ctx);
2801
2802 if (ctx->screen->b.chip_class >= GFX9) {
2803 LLVMBasicBlockRef blocks[2] = {
2804 LLVMGetInsertBlock(builder),
2805 ctx->merged_wrap_if_state.entry_block
2806 };
2807 LLVMValueRef values[2];
2808
2809 lp_build_endif(&ctx->merged_wrap_if_state);
2810
2811 values[0] = rel_patch_id;
2812 values[1] = LLVMGetUndef(ctx->i32);
2813 rel_patch_id = build_phi(&ctx->ac, ctx->i32, 2, values, blocks);
2814
2815 values[0] = tf_lds_offset;
2816 values[1] = LLVMGetUndef(ctx->i32);
2817 tf_lds_offset = build_phi(&ctx->ac, ctx->i32, 2, values, blocks);
2818
2819 values[0] = invocation_id;
2820 values[1] = ctx->i32_1; /* cause the epilog to skip threads */
2821 invocation_id = build_phi(&ctx->ac, ctx->i32, 2, values, blocks);
2822 }
2823
2824 /* Return epilog parameters from this function. */
2825 LLVMValueRef ret = ctx->return_value;
2826 unsigned vgpr;
2827
2828 if (ctx->screen->b.chip_class >= GFX9) {
2829 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_layout,
2830 8 + GFX9_SGPR_TCS_OFFCHIP_LAYOUT);
2831 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_addr_base64k,
2832 8 + GFX9_SGPR_TCS_OFFCHIP_ADDR_BASE64K);
2833 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_factor_addr_base64k,
2834 8 + GFX9_SGPR_TCS_FACTOR_ADDR_BASE64K);
2835 /* Tess offchip and tess factor offsets are at the beginning. */
2836 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_offset, 2);
2837 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_factor_offset, 4);
2838 vgpr = 8 + GFX9_SGPR_TCS_FACTOR_ADDR_BASE64K + 1;
2839 } else {
2840 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_layout,
2841 GFX6_SGPR_TCS_OFFCHIP_LAYOUT);
2842 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_addr_base64k,
2843 GFX6_SGPR_TCS_OFFCHIP_ADDR_BASE64K);
2844 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_factor_addr_base64k,
2845 GFX6_SGPR_TCS_FACTOR_ADDR_BASE64K);
2846 /* Tess offchip and tess factor offsets are after user SGPRs. */
2847 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_offset,
2848 GFX6_TCS_NUM_USER_SGPR);
2849 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_factor_offset,
2850 GFX6_TCS_NUM_USER_SGPR + 1);
2851 vgpr = GFX6_TCS_NUM_USER_SGPR + 2;
2852 }
2853
2854 /* VGPRs */
2855 rel_patch_id = bitcast(bld_base, TGSI_TYPE_FLOAT, rel_patch_id);
2856 invocation_id = bitcast(bld_base, TGSI_TYPE_FLOAT, invocation_id);
2857 tf_lds_offset = bitcast(bld_base, TGSI_TYPE_FLOAT, tf_lds_offset);
2858
2859 /* Leave a hole corresponding to the two input VGPRs. This ensures that
2860 * the invocation_id output does not alias the param_tcs_rel_ids input,
2861 * which saves a V_MOV on gfx9.
2862 */
2863 vgpr += 2;
2864
2865 ret = LLVMBuildInsertValue(builder, ret, rel_patch_id, vgpr++, "");
2866 ret = LLVMBuildInsertValue(builder, ret, invocation_id, vgpr++, "");
2867 ret = LLVMBuildInsertValue(builder, ret, tf_lds_offset, vgpr++, "");
2868 ctx->return_value = ret;
2869 }
2870
2871 /* Pass TCS inputs from LS to TCS on GFX9. */
2872 static void si_set_ls_return_value_for_tcs(struct si_shader_context *ctx)
2873 {
2874 LLVMValueRef ret = ctx->return_value;
2875
2876 ret = si_insert_input_ptr_as_2xi32(ctx, ret, ctx->param_rw_buffers, 0);
2877 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_offset, 2);
2878 ret = si_insert_input_ret(ctx, ret, ctx->param_merged_wave_info, 3);
2879 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_factor_offset, 4);
2880 ret = si_insert_input_ret(ctx, ret, ctx->param_merged_scratch_offset, 5);
2881
2882 ret = si_insert_input_ret(ctx, ret, ctx->param_vs_state_bits,
2883 8 + SI_SGPR_VS_STATE_BITS);
2884 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_layout,
2885 8 + GFX9_SGPR_TCS_OFFCHIP_LAYOUT);
2886 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_out_lds_offsets,
2887 8 + GFX9_SGPR_TCS_OUT_OFFSETS);
2888 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_out_lds_layout,
2889 8 + GFX9_SGPR_TCS_OUT_LAYOUT);
2890 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_addr_base64k,
2891 8 + GFX9_SGPR_TCS_OFFCHIP_ADDR_BASE64K);
2892 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_factor_addr_base64k,
2893 8 + GFX9_SGPR_TCS_FACTOR_ADDR_BASE64K);
2894
2895 unsigned desc_param = ctx->param_tcs_factor_addr_base64k + 2;
2896 ret = si_insert_input_ptr_as_2xi32(ctx, ret, desc_param,
2897 8 + GFX9_SGPR_TCS_CONST_AND_SHADER_BUFFERS);
2898 ret = si_insert_input_ptr_as_2xi32(ctx, ret, desc_param + 1,
2899 8 + GFX9_SGPR_TCS_SAMPLERS_AND_IMAGES);
2900
2901 unsigned vgpr = 8 + GFX9_TCS_NUM_USER_SGPR;
2902 ret = si_insert_input_ret_float(ctx, ret,
2903 ctx->param_tcs_patch_id, vgpr++);
2904 ret = si_insert_input_ret_float(ctx, ret,
2905 ctx->param_tcs_rel_ids, vgpr++);
2906 ctx->return_value = ret;
2907 }
2908
2909 /* Pass GS inputs from ES to GS on GFX9. */
2910 static void si_set_es_return_value_for_gs(struct si_shader_context *ctx)
2911 {
2912 LLVMValueRef ret = ctx->return_value;
2913
2914 ret = si_insert_input_ptr_as_2xi32(ctx, ret, ctx->param_rw_buffers, 0);
2915 ret = si_insert_input_ret(ctx, ret, ctx->param_gs2vs_offset, 2);
2916 ret = si_insert_input_ret(ctx, ret, ctx->param_merged_wave_info, 3);
2917
2918 ret = si_insert_input_ret(ctx, ret, ctx->param_merged_scratch_offset, 5);
2919
2920 unsigned desc_param = ctx->param_vs_state_bits + 1;
2921 ret = si_insert_input_ptr_as_2xi32(ctx, ret, desc_param,
2922 8 + GFX9_SGPR_GS_CONST_AND_SHADER_BUFFERS);
2923 ret = si_insert_input_ptr_as_2xi32(ctx, ret, desc_param + 1,
2924 8 + GFX9_SGPR_GS_SAMPLERS_AND_IMAGES);
2925
2926 unsigned vgpr = 8 + GFX9_GS_NUM_USER_SGPR;
2927 for (unsigned i = 0; i < 5; i++) {
2928 unsigned param = ctx->param_gs_vtx01_offset + i;
2929 ret = si_insert_input_ret_float(ctx, ret, param, vgpr++);
2930 }
2931 ctx->return_value = ret;
2932 }
2933
2934 static void si_llvm_emit_ls_epilogue(struct lp_build_tgsi_context *bld_base)
2935 {
2936 struct si_shader_context *ctx = si_shader_context(bld_base);
2937 struct si_shader *shader = ctx->shader;
2938 struct tgsi_shader_info *info = &shader->selector->info;
2939 struct gallivm_state *gallivm = &ctx->gallivm;
2940 unsigned i, chan;
2941 LLVMValueRef vertex_id = LLVMGetParam(ctx->main_fn,
2942 ctx->param_rel_auto_id);
2943 LLVMValueRef vertex_dw_stride =
2944 unpack_param(ctx, ctx->param_vs_state_bits, 24, 8);
2945 LLVMValueRef base_dw_addr = LLVMBuildMul(gallivm->builder, vertex_id,
2946 vertex_dw_stride, "");
2947
2948 /* Write outputs to LDS. The next shader (TCS aka HS) will read
2949 * its inputs from it. */
2950 for (i = 0; i < info->num_outputs; i++) {
2951 LLVMValueRef *out_ptr = ctx->outputs[i];
2952 unsigned name = info->output_semantic_name[i];
2953 unsigned index = info->output_semantic_index[i];
2954
2955 /* The ARB_shader_viewport_layer_array spec contains the
2956 * following issue:
2957 *
2958 * 2) What happens if gl_ViewportIndex or gl_Layer is
2959 * written in the vertex shader and a geometry shader is
2960 * present?
2961 *
2962 * RESOLVED: The value written by the last vertex processing
2963 * stage is used. If the last vertex processing stage
2964 * (vertex, tessellation evaluation or geometry) does not
2965 * statically assign to gl_ViewportIndex or gl_Layer, index
2966 * or layer zero is assumed.
2967 *
2968 * So writes to those outputs in VS-as-LS are simply ignored.
2969 */
2970 if (name == TGSI_SEMANTIC_LAYER ||
2971 name == TGSI_SEMANTIC_VIEWPORT_INDEX)
2972 continue;
2973
2974 int param = si_shader_io_get_unique_index(name, index);
2975 LLVMValueRef dw_addr = LLVMBuildAdd(gallivm->builder, base_dw_addr,
2976 LLVMConstInt(ctx->i32, param * 4, 0), "");
2977
2978 for (chan = 0; chan < 4; chan++) {
2979 lds_store(bld_base, chan, dw_addr,
2980 LLVMBuildLoad(gallivm->builder, out_ptr[chan], ""));
2981 }
2982 }
2983
2984 if (ctx->screen->b.chip_class >= GFX9)
2985 si_set_ls_return_value_for_tcs(ctx);
2986 }
2987
2988 static void si_llvm_emit_es_epilogue(struct lp_build_tgsi_context *bld_base)
2989 {
2990 struct si_shader_context *ctx = si_shader_context(bld_base);
2991 struct gallivm_state *gallivm = &ctx->gallivm;
2992 struct si_shader *es = ctx->shader;
2993 struct tgsi_shader_info *info = &es->selector->info;
2994 LLVMValueRef soffset = LLVMGetParam(ctx->main_fn,
2995 ctx->param_es2gs_offset);
2996 LLVMValueRef lds_base = NULL;
2997 unsigned chan;
2998 int i;
2999
3000 if (ctx->screen->b.chip_class >= GFX9 && info->num_outputs) {
3001 unsigned itemsize_dw = es->selector->esgs_itemsize / 4;
3002 LLVMValueRef vertex_idx = ac_get_thread_id(&ctx->ac);
3003 LLVMValueRef wave_idx = unpack_param(ctx, ctx->param_merged_wave_info, 24, 4);
3004 vertex_idx = LLVMBuildOr(gallivm->builder, vertex_idx,
3005 LLVMBuildMul(gallivm->builder, wave_idx,
3006 LLVMConstInt(ctx->i32, 64, false), ""), "");
3007 lds_base = LLVMBuildMul(gallivm->builder, vertex_idx,
3008 LLVMConstInt(ctx->i32, itemsize_dw, 0), "");
3009 }
3010
3011 for (i = 0; i < info->num_outputs; i++) {
3012 LLVMValueRef *out_ptr = ctx->outputs[i];
3013 int param;
3014
3015 if (info->output_semantic_name[i] == TGSI_SEMANTIC_VIEWPORT_INDEX ||
3016 info->output_semantic_name[i] == TGSI_SEMANTIC_LAYER)
3017 continue;
3018
3019 param = si_shader_io_get_unique_index(info->output_semantic_name[i],
3020 info->output_semantic_index[i]);
3021
3022 for (chan = 0; chan < 4; chan++) {
3023 LLVMValueRef out_val = LLVMBuildLoad(gallivm->builder, out_ptr[chan], "");
3024 out_val = LLVMBuildBitCast(gallivm->builder, out_val, ctx->i32, "");
3025
3026 /* GFX9 has the ESGS ring in LDS. */
3027 if (ctx->screen->b.chip_class >= GFX9) {
3028 lds_store(bld_base, param * 4 + chan, lds_base, out_val);
3029 continue;
3030 }
3031
3032 ac_build_buffer_store_dword(&ctx->ac,
3033 ctx->esgs_ring,
3034 out_val, 1, NULL, soffset,
3035 (4 * param + chan) * 4,
3036 1, 1, true, true);
3037 }
3038 }
3039
3040 if (ctx->screen->b.chip_class >= GFX9)
3041 si_set_es_return_value_for_gs(ctx);
3042 }
3043
3044 static LLVMValueRef si_get_gs_wave_id(struct si_shader_context *ctx)
3045 {
3046 if (ctx->screen->b.chip_class >= GFX9)
3047 return unpack_param(ctx, ctx->param_merged_wave_info, 16, 8);
3048 else
3049 return LLVMGetParam(ctx->main_fn, ctx->param_gs_wave_id);
3050 }
3051
3052 static void si_llvm_emit_gs_epilogue(struct lp_build_tgsi_context *bld_base)
3053 {
3054 struct si_shader_context *ctx = si_shader_context(bld_base);
3055
3056 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_NOP | AC_SENDMSG_GS_DONE,
3057 si_get_gs_wave_id(ctx));
3058
3059 if (ctx->screen->b.chip_class >= GFX9)
3060 lp_build_endif(&ctx->merged_wrap_if_state);
3061 }
3062
3063 static void si_llvm_emit_vs_epilogue(struct ac_shader_abi *abi,
3064 unsigned max_outputs,
3065 LLVMValueRef *addrs)
3066 {
3067 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
3068 struct gallivm_state *gallivm = &ctx->gallivm;
3069 struct tgsi_shader_info *info = &ctx->shader->selector->info;
3070 struct si_shader_output_values *outputs = NULL;
3071 int i,j;
3072
3073 assert(!ctx->shader->is_gs_copy_shader);
3074 assert(info->num_outputs <= max_outputs);
3075
3076 outputs = MALLOC((info->num_outputs + 1) * sizeof(outputs[0]));
3077
3078 /* Vertex color clamping.
3079 *
3080 * This uses a state constant loaded in a user data SGPR and
3081 * an IF statement is added that clamps all colors if the constant
3082 * is true.
3083 */
3084 if (ctx->type == PIPE_SHADER_VERTEX) {
3085 struct lp_build_if_state if_ctx;
3086 LLVMValueRef cond = NULL;
3087 LLVMValueRef addr, val;
3088
3089 for (i = 0; i < info->num_outputs; i++) {
3090 if (info->output_semantic_name[i] != TGSI_SEMANTIC_COLOR &&
3091 info->output_semantic_name[i] != TGSI_SEMANTIC_BCOLOR)
3092 continue;
3093
3094 /* We've found a color. */
3095 if (!cond) {
3096 /* The state is in the first bit of the user SGPR. */
3097 cond = LLVMGetParam(ctx->main_fn,
3098 ctx->param_vs_state_bits);
3099 cond = LLVMBuildTrunc(gallivm->builder, cond,
3100 ctx->i1, "");
3101 lp_build_if(&if_ctx, gallivm, cond);
3102 }
3103
3104 for (j = 0; j < 4; j++) {
3105 addr = addrs[4 * i + j];
3106 val = LLVMBuildLoad(gallivm->builder, addr, "");
3107 val = ac_build_clamp(&ctx->ac, val);
3108 LLVMBuildStore(gallivm->builder, val, addr);
3109 }
3110 }
3111
3112 if (cond)
3113 lp_build_endif(&if_ctx);
3114 }
3115
3116 for (i = 0; i < info->num_outputs; i++) {
3117 outputs[i].semantic_name = info->output_semantic_name[i];
3118 outputs[i].semantic_index = info->output_semantic_index[i];
3119
3120 for (j = 0; j < 4; j++) {
3121 outputs[i].values[j] =
3122 LLVMBuildLoad(gallivm->builder,
3123 addrs[4 * i + j],
3124 "");
3125 outputs[i].vertex_stream[j] =
3126 (info->output_streams[i] >> (2 * j)) & 3;
3127 }
3128 }
3129
3130 if (ctx->shader->selector->so.num_outputs)
3131 si_llvm_emit_streamout(ctx, outputs, i, 0);
3132
3133 /* Export PrimitiveID. */
3134 if (ctx->shader->key.mono.u.vs_export_prim_id) {
3135 outputs[i].semantic_name = TGSI_SEMANTIC_PRIMID;
3136 outputs[i].semantic_index = 0;
3137 outputs[i].values[0] = LLVMBuildBitCast(gallivm->builder,
3138 get_primitive_id(ctx, 0), ctx->f32, "");
3139 for (j = 1; j < 4; j++)
3140 outputs[i].values[j] = LLVMConstReal(ctx->f32, 0);
3141
3142 memset(outputs[i].vertex_stream, 0,
3143 sizeof(outputs[i].vertex_stream));
3144 i++;
3145 }
3146
3147 si_llvm_export_vs(&ctx->bld_base, outputs, i);
3148 FREE(outputs);
3149 }
3150
3151 static void si_tgsi_emit_epilogue(struct lp_build_tgsi_context *bld_base)
3152 {
3153 struct si_shader_context *ctx = si_shader_context(bld_base);
3154
3155 ctx->abi.emit_outputs(&ctx->abi, RADEON_LLVM_MAX_OUTPUTS,
3156 &ctx->outputs[0][0]);
3157 }
3158
3159 struct si_ps_exports {
3160 unsigned num;
3161 struct ac_export_args args[10];
3162 };
3163
3164 unsigned si_get_spi_shader_z_format(bool writes_z, bool writes_stencil,
3165 bool writes_samplemask)
3166 {
3167 if (writes_z) {
3168 /* Z needs 32 bits. */
3169 if (writes_samplemask)
3170 return V_028710_SPI_SHADER_32_ABGR;
3171 else if (writes_stencil)
3172 return V_028710_SPI_SHADER_32_GR;
3173 else
3174 return V_028710_SPI_SHADER_32_R;
3175 } else if (writes_stencil || writes_samplemask) {
3176 /* Both stencil and sample mask need only 16 bits. */
3177 return V_028710_SPI_SHADER_UINT16_ABGR;
3178 } else {
3179 return V_028710_SPI_SHADER_ZERO;
3180 }
3181 }
3182
3183 static void si_export_mrt_z(struct lp_build_tgsi_context *bld_base,
3184 LLVMValueRef depth, LLVMValueRef stencil,
3185 LLVMValueRef samplemask, struct si_ps_exports *exp)
3186 {
3187 struct si_shader_context *ctx = si_shader_context(bld_base);
3188 struct lp_build_context *base = &bld_base->base;
3189 struct ac_export_args args;
3190 unsigned mask = 0;
3191 unsigned format = si_get_spi_shader_z_format(depth != NULL,
3192 stencil != NULL,
3193 samplemask != NULL);
3194
3195 assert(depth || stencil || samplemask);
3196
3197 args.valid_mask = 1; /* whether the EXEC mask is valid */
3198 args.done = 1; /* DONE bit */
3199
3200 /* Specify the target we are exporting */
3201 args.target = V_008DFC_SQ_EXP_MRTZ;
3202
3203 args.compr = 0; /* COMP flag */
3204 args.out[0] = base->undef; /* R, depth */
3205 args.out[1] = base->undef; /* G, stencil test value[0:7], stencil op value[8:15] */
3206 args.out[2] = base->undef; /* B, sample mask */
3207 args.out[3] = base->undef; /* A, alpha to mask */
3208
3209 if (format == V_028710_SPI_SHADER_UINT16_ABGR) {
3210 assert(!depth);
3211 args.compr = 1; /* COMPR flag */
3212
3213 if (stencil) {
3214 /* Stencil should be in X[23:16]. */
3215 stencil = bitcast(bld_base, TGSI_TYPE_UNSIGNED, stencil);
3216 stencil = LLVMBuildShl(ctx->gallivm.builder, stencil,
3217 LLVMConstInt(ctx->i32, 16, 0), "");
3218 args.out[0] = bitcast(bld_base, TGSI_TYPE_FLOAT, stencil);
3219 mask |= 0x3;
3220 }
3221 if (samplemask) {
3222 /* SampleMask should be in Y[15:0]. */
3223 args.out[1] = samplemask;
3224 mask |= 0xc;
3225 }
3226 } else {
3227 if (depth) {
3228 args.out[0] = depth;
3229 mask |= 0x1;
3230 }
3231 if (stencil) {
3232 args.out[1] = stencil;
3233 mask |= 0x2;
3234 }
3235 if (samplemask) {
3236 args.out[2] = samplemask;
3237 mask |= 0x4;
3238 }
3239 }
3240
3241 /* SI (except OLAND and HAINAN) has a bug that it only looks
3242 * at the X writemask component. */
3243 if (ctx->screen->b.chip_class == SI &&
3244 ctx->screen->b.family != CHIP_OLAND &&
3245 ctx->screen->b.family != CHIP_HAINAN)
3246 mask |= 0x1;
3247
3248 /* Specify which components to enable */
3249 args.enabled_channels = mask;
3250
3251 memcpy(&exp->args[exp->num++], &args, sizeof(args));
3252 }
3253
3254 static void si_export_mrt_color(struct lp_build_tgsi_context *bld_base,
3255 LLVMValueRef *color, unsigned index,
3256 unsigned samplemask_param,
3257 bool is_last, struct si_ps_exports *exp)
3258 {
3259 struct si_shader_context *ctx = si_shader_context(bld_base);
3260 struct lp_build_context *base = &bld_base->base;
3261 int i;
3262
3263 /* Clamp color */
3264 if (ctx->shader->key.part.ps.epilog.clamp_color)
3265 for (i = 0; i < 4; i++)
3266 color[i] = ac_build_clamp(&ctx->ac, color[i]);
3267
3268 /* Alpha to one */
3269 if (ctx->shader->key.part.ps.epilog.alpha_to_one)
3270 color[3] = base->one;
3271
3272 /* Alpha test */
3273 if (index == 0 &&
3274 ctx->shader->key.part.ps.epilog.alpha_func != PIPE_FUNC_ALWAYS)
3275 si_alpha_test(bld_base, color[3]);
3276
3277 /* Line & polygon smoothing */
3278 if (ctx->shader->key.part.ps.epilog.poly_line_smoothing)
3279 color[3] = si_scale_alpha_by_sample_mask(bld_base, color[3],
3280 samplemask_param);
3281
3282 /* If last_cbuf > 0, FS_COLOR0_WRITES_ALL_CBUFS is true. */
3283 if (ctx->shader->key.part.ps.epilog.last_cbuf > 0) {
3284 struct ac_export_args args[8];
3285 int c, last = -1;
3286
3287 /* Get the export arguments, also find out what the last one is. */
3288 for (c = 0; c <= ctx->shader->key.part.ps.epilog.last_cbuf; c++) {
3289 si_llvm_init_export_args(bld_base, color,
3290 V_008DFC_SQ_EXP_MRT + c, &args[c]);
3291 if (args[c].enabled_channels)
3292 last = c;
3293 }
3294
3295 /* Emit all exports. */
3296 for (c = 0; c <= ctx->shader->key.part.ps.epilog.last_cbuf; c++) {
3297 if (is_last && last == c) {
3298 args[c].valid_mask = 1; /* whether the EXEC mask is valid */
3299 args[c].done = 1; /* DONE bit */
3300 } else if (!args[c].enabled_channels)
3301 continue; /* unnecessary NULL export */
3302
3303 memcpy(&exp->args[exp->num++], &args[c], sizeof(args[c]));
3304 }
3305 } else {
3306 struct ac_export_args args;
3307
3308 /* Export */
3309 si_llvm_init_export_args(bld_base, color, V_008DFC_SQ_EXP_MRT + index,
3310 &args);
3311 if (is_last) {
3312 args.valid_mask = 1; /* whether the EXEC mask is valid */
3313 args.done = 1; /* DONE bit */
3314 } else if (!args.enabled_channels)
3315 return; /* unnecessary NULL export */
3316
3317 memcpy(&exp->args[exp->num++], &args, sizeof(args));
3318 }
3319 }
3320
3321 static void si_emit_ps_exports(struct si_shader_context *ctx,
3322 struct si_ps_exports *exp)
3323 {
3324 for (unsigned i = 0; i < exp->num; i++)
3325 ac_build_export(&ctx->ac, &exp->args[i]);
3326 }
3327
3328 static void si_export_null(struct lp_build_tgsi_context *bld_base)
3329 {
3330 struct si_shader_context *ctx = si_shader_context(bld_base);
3331 struct lp_build_context *base = &bld_base->base;
3332 struct ac_export_args args;
3333
3334 args.enabled_channels = 0x0; /* enabled channels */
3335 args.valid_mask = 1; /* whether the EXEC mask is valid */
3336 args.done = 1; /* DONE bit */
3337 args.target = V_008DFC_SQ_EXP_NULL;
3338 args.compr = 0; /* COMPR flag (0 = 32-bit export) */
3339 args.out[0] = base->undef; /* R */
3340 args.out[1] = base->undef; /* G */
3341 args.out[2] = base->undef; /* B */
3342 args.out[3] = base->undef; /* A */
3343
3344 ac_build_export(&ctx->ac, &args);
3345 }
3346
3347 /**
3348 * Return PS outputs in this order:
3349 *
3350 * v[0:3] = color0.xyzw
3351 * v[4:7] = color1.xyzw
3352 * ...
3353 * vN+0 = Depth
3354 * vN+1 = Stencil
3355 * vN+2 = SampleMask
3356 * vN+3 = SampleMaskIn (used for OpenGL smoothing)
3357 *
3358 * The alpha-ref SGPR is returned via its original location.
3359 */
3360 static void si_llvm_return_fs_outputs(struct lp_build_tgsi_context *bld_base)
3361 {
3362 struct si_shader_context *ctx = si_shader_context(bld_base);
3363 struct si_shader *shader = ctx->shader;
3364 struct tgsi_shader_info *info = &shader->selector->info;
3365 LLVMBuilderRef builder = ctx->gallivm.builder;
3366 unsigned i, j, first_vgpr, vgpr;
3367
3368 LLVMValueRef color[8][4] = {};
3369 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
3370 LLVMValueRef ret;
3371
3372 if (ctx->postponed_kill)
3373 ac_build_kill(&ctx->ac, LLVMBuildLoad(builder, ctx->postponed_kill, ""));
3374
3375 /* Read the output values. */
3376 for (i = 0; i < info->num_outputs; i++) {
3377 unsigned semantic_name = info->output_semantic_name[i];
3378 unsigned semantic_index = info->output_semantic_index[i];
3379
3380 switch (semantic_name) {
3381 case TGSI_SEMANTIC_COLOR:
3382 assert(semantic_index < 8);
3383 for (j = 0; j < 4; j++) {
3384 LLVMValueRef ptr = ctx->outputs[i][j];
3385 LLVMValueRef result = LLVMBuildLoad(builder, ptr, "");
3386 color[semantic_index][j] = result;
3387 }
3388 break;
3389 case TGSI_SEMANTIC_POSITION:
3390 depth = LLVMBuildLoad(builder,
3391 ctx->outputs[i][2], "");
3392 break;
3393 case TGSI_SEMANTIC_STENCIL:
3394 stencil = LLVMBuildLoad(builder,
3395 ctx->outputs[i][1], "");
3396 break;
3397 case TGSI_SEMANTIC_SAMPLEMASK:
3398 samplemask = LLVMBuildLoad(builder,
3399 ctx->outputs[i][0], "");
3400 break;
3401 default:
3402 fprintf(stderr, "Warning: SI unhandled fs output type:%d\n",
3403 semantic_name);
3404 }
3405 }
3406
3407 /* Fill the return structure. */
3408 ret = ctx->return_value;
3409
3410 /* Set SGPRs. */
3411 ret = LLVMBuildInsertValue(builder, ret,
3412 bitcast(bld_base, TGSI_TYPE_SIGNED,
3413 LLVMGetParam(ctx->main_fn,
3414 SI_PARAM_ALPHA_REF)),
3415 SI_SGPR_ALPHA_REF, "");
3416
3417 /* Set VGPRs */
3418 first_vgpr = vgpr = SI_SGPR_ALPHA_REF + 1;
3419 for (i = 0; i < ARRAY_SIZE(color); i++) {
3420 if (!color[i][0])
3421 continue;
3422
3423 for (j = 0; j < 4; j++)
3424 ret = LLVMBuildInsertValue(builder, ret, color[i][j], vgpr++, "");
3425 }
3426 if (depth)
3427 ret = LLVMBuildInsertValue(builder, ret, depth, vgpr++, "");
3428 if (stencil)
3429 ret = LLVMBuildInsertValue(builder, ret, stencil, vgpr++, "");
3430 if (samplemask)
3431 ret = LLVMBuildInsertValue(builder, ret, samplemask, vgpr++, "");
3432
3433 /* Add the input sample mask for smoothing at the end. */
3434 if (vgpr < first_vgpr + PS_EPILOG_SAMPLEMASK_MIN_LOC)
3435 vgpr = first_vgpr + PS_EPILOG_SAMPLEMASK_MIN_LOC;
3436 ret = LLVMBuildInsertValue(builder, ret,
3437 LLVMGetParam(ctx->main_fn,
3438 SI_PARAM_SAMPLE_COVERAGE), vgpr++, "");
3439
3440 ctx->return_value = ret;
3441 }
3442
3443 /* Prevent optimizations (at least of memory accesses) across the current
3444 * point in the program by emitting empty inline assembly that is marked as
3445 * having side effects.
3446 *
3447 * Optionally, a value can be passed through the inline assembly to prevent
3448 * LLVM from hoisting calls to ReadNone functions.
3449 */
3450 static void emit_optimization_barrier(struct si_shader_context *ctx,
3451 LLVMValueRef *pvgpr)
3452 {
3453 static int counter = 0;
3454
3455 LLVMBuilderRef builder = ctx->gallivm.builder;
3456 char code[16];
3457
3458 snprintf(code, sizeof(code), "; %d", p_atomic_inc_return(&counter));
3459
3460 if (!pvgpr) {
3461 LLVMTypeRef ftype = LLVMFunctionType(ctx->voidt, NULL, 0, false);
3462 LLVMValueRef inlineasm = LLVMConstInlineAsm(ftype, code, "", true, false);
3463 LLVMBuildCall(builder, inlineasm, NULL, 0, "");
3464 } else {
3465 LLVMTypeRef ftype = LLVMFunctionType(ctx->i32, &ctx->i32, 1, false);
3466 LLVMValueRef inlineasm = LLVMConstInlineAsm(ftype, code, "=v,0", true, false);
3467 LLVMValueRef vgpr = *pvgpr;
3468 LLVMTypeRef vgpr_type = LLVMTypeOf(vgpr);
3469 unsigned vgpr_size = llvm_get_type_size(vgpr_type);
3470 LLVMValueRef vgpr0;
3471
3472 assert(vgpr_size % 4 == 0);
3473
3474 vgpr = LLVMBuildBitCast(builder, vgpr, LLVMVectorType(ctx->i32, vgpr_size / 4), "");
3475 vgpr0 = LLVMBuildExtractElement(builder, vgpr, ctx->i32_0, "");
3476 vgpr0 = LLVMBuildCall(builder, inlineasm, &vgpr0, 1, "");
3477 vgpr = LLVMBuildInsertElement(builder, vgpr, vgpr0, ctx->i32_0, "");
3478 vgpr = LLVMBuildBitCast(builder, vgpr, vgpr_type, "");
3479
3480 *pvgpr = vgpr;
3481 }
3482 }
3483
3484 void si_emit_waitcnt(struct si_shader_context *ctx, unsigned simm16)
3485 {
3486 struct gallivm_state *gallivm = &ctx->gallivm;
3487 LLVMBuilderRef builder = gallivm->builder;
3488 LLVMValueRef args[1] = {
3489 LLVMConstInt(ctx->i32, simm16, 0)
3490 };
3491 lp_build_intrinsic(builder, "llvm.amdgcn.s.waitcnt",
3492 ctx->voidt, args, 1, 0);
3493 }
3494
3495 static void membar_emit(
3496 const struct lp_build_tgsi_action *action,
3497 struct lp_build_tgsi_context *bld_base,
3498 struct lp_build_emit_data *emit_data)
3499 {
3500 struct si_shader_context *ctx = si_shader_context(bld_base);
3501 LLVMValueRef src0 = lp_build_emit_fetch(bld_base, emit_data->inst, 0, 0);
3502 unsigned flags = LLVMConstIntGetZExtValue(src0);
3503 unsigned waitcnt = NOOP_WAITCNT;
3504
3505 if (flags & TGSI_MEMBAR_THREAD_GROUP)
3506 waitcnt &= VM_CNT & LGKM_CNT;
3507
3508 if (flags & (TGSI_MEMBAR_ATOMIC_BUFFER |
3509 TGSI_MEMBAR_SHADER_BUFFER |
3510 TGSI_MEMBAR_SHADER_IMAGE))
3511 waitcnt &= VM_CNT;
3512
3513 if (flags & TGSI_MEMBAR_SHARED)
3514 waitcnt &= LGKM_CNT;
3515
3516 if (waitcnt != NOOP_WAITCNT)
3517 si_emit_waitcnt(ctx, waitcnt);
3518 }
3519
3520 static void clock_emit(
3521 const struct lp_build_tgsi_action *action,
3522 struct lp_build_tgsi_context *bld_base,
3523 struct lp_build_emit_data *emit_data)
3524 {
3525 struct si_shader_context *ctx = si_shader_context(bld_base);
3526 struct gallivm_state *gallivm = &ctx->gallivm;
3527 LLVMValueRef tmp;
3528
3529 tmp = lp_build_intrinsic(gallivm->builder, "llvm.readcyclecounter",
3530 ctx->i64, NULL, 0, 0);
3531 tmp = LLVMBuildBitCast(gallivm->builder, tmp, ctx->v2i32, "");
3532
3533 emit_data->output[0] =
3534 LLVMBuildExtractElement(gallivm->builder, tmp, ctx->i32_0, "");
3535 emit_data->output[1] =
3536 LLVMBuildExtractElement(gallivm->builder, tmp, ctx->i32_1, "");
3537 }
3538
3539 LLVMTypeRef si_const_array(LLVMTypeRef elem_type, int num_elements)
3540 {
3541 return LLVMPointerType(LLVMArrayType(elem_type, num_elements),
3542 CONST_ADDR_SPACE);
3543 }
3544
3545 static void si_llvm_emit_ddxy(
3546 const struct lp_build_tgsi_action *action,
3547 struct lp_build_tgsi_context *bld_base,
3548 struct lp_build_emit_data *emit_data)
3549 {
3550 struct si_shader_context *ctx = si_shader_context(bld_base);
3551 struct gallivm_state *gallivm = &ctx->gallivm;
3552 unsigned opcode = emit_data->info->opcode;
3553 LLVMValueRef val;
3554 int idx;
3555 unsigned mask;
3556
3557 if (opcode == TGSI_OPCODE_DDX_FINE)
3558 mask = AC_TID_MASK_LEFT;
3559 else if (opcode == TGSI_OPCODE_DDY_FINE)
3560 mask = AC_TID_MASK_TOP;
3561 else
3562 mask = AC_TID_MASK_TOP_LEFT;
3563
3564 /* for DDX we want to next X pixel, DDY next Y pixel. */
3565 idx = (opcode == TGSI_OPCODE_DDX || opcode == TGSI_OPCODE_DDX_FINE) ? 1 : 2;
3566
3567 val = LLVMBuildBitCast(gallivm->builder, emit_data->args[0], ctx->i32, "");
3568 val = ac_build_ddxy(&ctx->ac, ctx->screen->has_ds_bpermute,
3569 mask, idx, ctx->lds, val);
3570 emit_data->output[emit_data->chan] = val;
3571 }
3572
3573 /*
3574 * this takes an I,J coordinate pair,
3575 * and works out the X and Y derivatives.
3576 * it returns DDX(I), DDX(J), DDY(I), DDY(J).
3577 */
3578 static LLVMValueRef si_llvm_emit_ddxy_interp(
3579 struct lp_build_tgsi_context *bld_base,
3580 LLVMValueRef interp_ij)
3581 {
3582 struct si_shader_context *ctx = si_shader_context(bld_base);
3583 struct gallivm_state *gallivm = &ctx->gallivm;
3584 LLVMValueRef result[4], a;
3585 unsigned i;
3586
3587 for (i = 0; i < 2; i++) {
3588 a = LLVMBuildExtractElement(gallivm->builder, interp_ij,
3589 LLVMConstInt(ctx->i32, i, 0), "");
3590 result[i] = lp_build_emit_llvm_unary(bld_base, TGSI_OPCODE_DDX, a);
3591 result[2+i] = lp_build_emit_llvm_unary(bld_base, TGSI_OPCODE_DDY, a);
3592 }
3593
3594 return lp_build_gather_values(gallivm, result, 4);
3595 }
3596
3597 static void interp_fetch_args(
3598 struct lp_build_tgsi_context *bld_base,
3599 struct lp_build_emit_data *emit_data)
3600 {
3601 struct si_shader_context *ctx = si_shader_context(bld_base);
3602 struct gallivm_state *gallivm = &ctx->gallivm;
3603 const struct tgsi_full_instruction *inst = emit_data->inst;
3604
3605 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET) {
3606 /* offset is in second src, first two channels */
3607 emit_data->args[0] = lp_build_emit_fetch(bld_base,
3608 emit_data->inst, 1,
3609 TGSI_CHAN_X);
3610 emit_data->args[1] = lp_build_emit_fetch(bld_base,
3611 emit_data->inst, 1,
3612 TGSI_CHAN_Y);
3613 emit_data->arg_count = 2;
3614 } else if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
3615 LLVMValueRef sample_position;
3616 LLVMValueRef sample_id;
3617 LLVMValueRef halfval = LLVMConstReal(ctx->f32, 0.5f);
3618
3619 /* fetch sample ID, then fetch its sample position,
3620 * and place into first two channels.
3621 */
3622 sample_id = lp_build_emit_fetch(bld_base,
3623 emit_data->inst, 1, TGSI_CHAN_X);
3624 sample_id = LLVMBuildBitCast(gallivm->builder, sample_id,
3625 ctx->i32, "");
3626 sample_position = load_sample_position(ctx, sample_id);
3627
3628 emit_data->args[0] = LLVMBuildExtractElement(gallivm->builder,
3629 sample_position,
3630 ctx->i32_0, "");
3631
3632 emit_data->args[0] = LLVMBuildFSub(gallivm->builder, emit_data->args[0], halfval, "");
3633 emit_data->args[1] = LLVMBuildExtractElement(gallivm->builder,
3634 sample_position,
3635 ctx->i32_1, "");
3636 emit_data->args[1] = LLVMBuildFSub(gallivm->builder, emit_data->args[1], halfval, "");
3637 emit_data->arg_count = 2;
3638 }
3639 }
3640
3641 static void build_interp_intrinsic(const struct lp_build_tgsi_action *action,
3642 struct lp_build_tgsi_context *bld_base,
3643 struct lp_build_emit_data *emit_data)
3644 {
3645 struct si_shader_context *ctx = si_shader_context(bld_base);
3646 struct si_shader *shader = ctx->shader;
3647 struct gallivm_state *gallivm = &ctx->gallivm;
3648 const struct tgsi_shader_info *info = &shader->selector->info;
3649 LLVMValueRef interp_param;
3650 const struct tgsi_full_instruction *inst = emit_data->inst;
3651 const struct tgsi_full_src_register *input = &inst->Src[0];
3652 int input_base, input_array_size;
3653 int chan;
3654 int i;
3655 LLVMValueRef prim_mask = LLVMGetParam(ctx->main_fn, SI_PARAM_PRIM_MASK);
3656 LLVMValueRef array_idx;
3657 int interp_param_idx;
3658 unsigned interp;
3659 unsigned location;
3660
3661 assert(input->Register.File == TGSI_FILE_INPUT);
3662
3663 if (input->Register.Indirect) {
3664 unsigned array_id = input->Indirect.ArrayID;
3665
3666 if (array_id) {
3667 input_base = info->input_array_first[array_id];
3668 input_array_size = info->input_array_last[array_id] - input_base + 1;
3669 } else {
3670 input_base = inst->Src[0].Register.Index;
3671 input_array_size = info->num_inputs - input_base;
3672 }
3673
3674 array_idx = get_indirect_index(ctx, &input->Indirect,
3675 input->Register.Index - input_base);
3676 } else {
3677 input_base = inst->Src[0].Register.Index;
3678 input_array_size = 1;
3679 array_idx = ctx->i32_0;
3680 }
3681
3682 interp = shader->selector->info.input_interpolate[input_base];
3683
3684 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
3685 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE)
3686 location = TGSI_INTERPOLATE_LOC_CENTER;
3687 else
3688 location = TGSI_INTERPOLATE_LOC_CENTROID;
3689
3690 interp_param_idx = lookup_interp_param_index(interp, location);
3691 if (interp_param_idx == -1)
3692 return;
3693 else if (interp_param_idx)
3694 interp_param = LLVMGetParam(ctx->main_fn, interp_param_idx);
3695 else
3696 interp_param = NULL;
3697
3698 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
3699 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
3700 LLVMValueRef ij_out[2];
3701 LLVMValueRef ddxy_out = si_llvm_emit_ddxy_interp(bld_base, interp_param);
3702
3703 /*
3704 * take the I then J parameters, and the DDX/Y for it, and
3705 * calculate the IJ inputs for the interpolator.
3706 * temp1 = ddx * offset/sample.x + I;
3707 * interp_param.I = ddy * offset/sample.y + temp1;
3708 * temp1 = ddx * offset/sample.x + J;
3709 * interp_param.J = ddy * offset/sample.y + temp1;
3710 */
3711 for (i = 0; i < 2; i++) {
3712 LLVMValueRef ix_ll = LLVMConstInt(ctx->i32, i, 0);
3713 LLVMValueRef iy_ll = LLVMConstInt(ctx->i32, i + 2, 0);
3714 LLVMValueRef ddx_el = LLVMBuildExtractElement(gallivm->builder,
3715 ddxy_out, ix_ll, "");
3716 LLVMValueRef ddy_el = LLVMBuildExtractElement(gallivm->builder,
3717 ddxy_out, iy_ll, "");
3718 LLVMValueRef interp_el = LLVMBuildExtractElement(gallivm->builder,
3719 interp_param, ix_ll, "");
3720 LLVMValueRef temp1, temp2;
3721
3722 interp_el = LLVMBuildBitCast(gallivm->builder, interp_el,
3723 ctx->f32, "");
3724
3725 temp1 = LLVMBuildFMul(gallivm->builder, ddx_el, emit_data->args[0], "");
3726
3727 temp1 = LLVMBuildFAdd(gallivm->builder, temp1, interp_el, "");
3728
3729 temp2 = LLVMBuildFMul(gallivm->builder, ddy_el, emit_data->args[1], "");
3730
3731 ij_out[i] = LLVMBuildFAdd(gallivm->builder, temp2, temp1, "");
3732 }
3733 interp_param = lp_build_gather_values(gallivm, ij_out, 2);
3734 }
3735
3736 if (interp_param) {
3737 interp_param = LLVMBuildBitCast(gallivm->builder,
3738 interp_param, LLVMVectorType(ctx->f32, 2), "");
3739 }
3740
3741 for (chan = 0; chan < 4; chan++) {
3742 LLVMValueRef gather = LLVMGetUndef(LLVMVectorType(ctx->f32, input_array_size));
3743 unsigned schan = tgsi_util_get_full_src_register_swizzle(&inst->Src[0], chan);
3744
3745 for (unsigned idx = 0; idx < input_array_size; ++idx) {
3746 LLVMValueRef v, i = NULL, j = NULL;
3747
3748 if (interp_param) {
3749 interp_param = LLVMBuildBitCast(gallivm->builder,
3750 interp_param, LLVMVectorType(ctx->f32, 2), "");
3751 i = LLVMBuildExtractElement(
3752 gallivm->builder, interp_param, ctx->i32_0, "");
3753 j = LLVMBuildExtractElement(
3754 gallivm->builder, interp_param, ctx->i32_1, "");
3755 }
3756 v = si_build_fs_interp(ctx, input_base + idx, schan,
3757 prim_mask, i, j);
3758
3759 gather = LLVMBuildInsertElement(gallivm->builder,
3760 gather, v, LLVMConstInt(ctx->i32, idx, false), "");
3761 }
3762
3763 emit_data->output[chan] = LLVMBuildExtractElement(
3764 gallivm->builder, gather, array_idx, "");
3765 }
3766 }
3767
3768 static LLVMValueRef si_emit_ballot(struct si_shader_context *ctx,
3769 LLVMValueRef value)
3770 {
3771 struct gallivm_state *gallivm = &ctx->gallivm;
3772 LLVMValueRef args[3] = {
3773 value,
3774 ctx->i32_0,
3775 LLVMConstInt(ctx->i32, LLVMIntNE, 0)
3776 };
3777
3778 /* We currently have no other way to prevent LLVM from lifting the icmp
3779 * calls to a dominating basic block.
3780 */
3781 emit_optimization_barrier(ctx, &args[0]);
3782
3783 if (LLVMTypeOf(args[0]) != ctx->i32)
3784 args[0] = LLVMBuildBitCast(gallivm->builder, args[0], ctx->i32, "");
3785
3786 return lp_build_intrinsic(gallivm->builder,
3787 "llvm.amdgcn.icmp.i32",
3788 ctx->i64, args, 3,
3789 LP_FUNC_ATTR_NOUNWIND |
3790 LP_FUNC_ATTR_READNONE |
3791 LP_FUNC_ATTR_CONVERGENT);
3792 }
3793
3794 static void vote_all_emit(
3795 const struct lp_build_tgsi_action *action,
3796 struct lp_build_tgsi_context *bld_base,
3797 struct lp_build_emit_data *emit_data)
3798 {
3799 struct si_shader_context *ctx = si_shader_context(bld_base);
3800 struct gallivm_state *gallivm = &ctx->gallivm;
3801 LLVMValueRef active_set, vote_set;
3802 LLVMValueRef tmp;
3803
3804 active_set = si_emit_ballot(ctx, ctx->i32_1);
3805 vote_set = si_emit_ballot(ctx, emit_data->args[0]);
3806
3807 tmp = LLVMBuildICmp(gallivm->builder, LLVMIntEQ, vote_set, active_set, "");
3808 emit_data->output[emit_data->chan] =
3809 LLVMBuildSExt(gallivm->builder, tmp, ctx->i32, "");
3810 }
3811
3812 static void vote_any_emit(
3813 const struct lp_build_tgsi_action *action,
3814 struct lp_build_tgsi_context *bld_base,
3815 struct lp_build_emit_data *emit_data)
3816 {
3817 struct si_shader_context *ctx = si_shader_context(bld_base);
3818 struct gallivm_state *gallivm = &ctx->gallivm;
3819 LLVMValueRef vote_set;
3820 LLVMValueRef tmp;
3821
3822 vote_set = si_emit_ballot(ctx, emit_data->args[0]);
3823
3824 tmp = LLVMBuildICmp(gallivm->builder, LLVMIntNE,
3825 vote_set, LLVMConstInt(ctx->i64, 0, 0), "");
3826 emit_data->output[emit_data->chan] =
3827 LLVMBuildSExt(gallivm->builder, tmp, ctx->i32, "");
3828 }
3829
3830 static void vote_eq_emit(
3831 const struct lp_build_tgsi_action *action,
3832 struct lp_build_tgsi_context *bld_base,
3833 struct lp_build_emit_data *emit_data)
3834 {
3835 struct si_shader_context *ctx = si_shader_context(bld_base);
3836 struct gallivm_state *gallivm = &ctx->gallivm;
3837 LLVMValueRef active_set, vote_set;
3838 LLVMValueRef all, none, tmp;
3839
3840 active_set = si_emit_ballot(ctx, ctx->i32_1);
3841 vote_set = si_emit_ballot(ctx, emit_data->args[0]);
3842
3843 all = LLVMBuildICmp(gallivm->builder, LLVMIntEQ, vote_set, active_set, "");
3844 none = LLVMBuildICmp(gallivm->builder, LLVMIntEQ,
3845 vote_set, LLVMConstInt(ctx->i64, 0, 0), "");
3846 tmp = LLVMBuildOr(gallivm->builder, all, none, "");
3847 emit_data->output[emit_data->chan] =
3848 LLVMBuildSExt(gallivm->builder, tmp, ctx->i32, "");
3849 }
3850
3851 static void ballot_emit(
3852 const struct lp_build_tgsi_action *action,
3853 struct lp_build_tgsi_context *bld_base,
3854 struct lp_build_emit_data *emit_data)
3855 {
3856 struct si_shader_context *ctx = si_shader_context(bld_base);
3857 LLVMBuilderRef builder = ctx->gallivm.builder;
3858 LLVMValueRef tmp;
3859
3860 tmp = lp_build_emit_fetch(bld_base, emit_data->inst, 0, TGSI_CHAN_X);
3861 tmp = si_emit_ballot(ctx, tmp);
3862 tmp = LLVMBuildBitCast(builder, tmp, ctx->v2i32, "");
3863
3864 emit_data->output[0] = LLVMBuildExtractElement(builder, tmp, ctx->i32_0, "");
3865 emit_data->output[1] = LLVMBuildExtractElement(builder, tmp, ctx->i32_1, "");
3866 }
3867
3868 static void read_invoc_fetch_args(
3869 struct lp_build_tgsi_context *bld_base,
3870 struct lp_build_emit_data *emit_data)
3871 {
3872 emit_data->args[0] = lp_build_emit_fetch(bld_base, emit_data->inst,
3873 0, emit_data->src_chan);
3874
3875 /* Always read the source invocation (= lane) from the X channel. */
3876 emit_data->args[1] = lp_build_emit_fetch(bld_base, emit_data->inst,
3877 1, TGSI_CHAN_X);
3878 emit_data->arg_count = 2;
3879 }
3880
3881 static void read_lane_emit(
3882 const struct lp_build_tgsi_action *action,
3883 struct lp_build_tgsi_context *bld_base,
3884 struct lp_build_emit_data *emit_data)
3885 {
3886 struct si_shader_context *ctx = si_shader_context(bld_base);
3887 LLVMBuilderRef builder = ctx->gallivm.builder;
3888
3889 /* We currently have no other way to prevent LLVM from lifting the icmp
3890 * calls to a dominating basic block.
3891 */
3892 emit_optimization_barrier(ctx, &emit_data->args[0]);
3893
3894 for (unsigned i = 0; i < emit_data->arg_count; ++i) {
3895 emit_data->args[i] = LLVMBuildBitCast(builder, emit_data->args[i],
3896 ctx->i32, "");
3897 }
3898
3899 emit_data->output[emit_data->chan] =
3900 ac_build_intrinsic(&ctx->ac, action->intr_name,
3901 ctx->i32, emit_data->args, emit_data->arg_count,
3902 AC_FUNC_ATTR_READNONE |
3903 AC_FUNC_ATTR_CONVERGENT);
3904 }
3905
3906 static unsigned si_llvm_get_stream(struct lp_build_tgsi_context *bld_base,
3907 struct lp_build_emit_data *emit_data)
3908 {
3909 struct si_shader_context *ctx = si_shader_context(bld_base);
3910 struct tgsi_src_register src0 = emit_data->inst->Src[0].Register;
3911 LLVMValueRef imm;
3912 unsigned stream;
3913
3914 assert(src0.File == TGSI_FILE_IMMEDIATE);
3915
3916 imm = ctx->imms[src0.Index * TGSI_NUM_CHANNELS + src0.SwizzleX];
3917 stream = LLVMConstIntGetZExtValue(imm) & 0x3;
3918 return stream;
3919 }
3920
3921 /* Emit one vertex from the geometry shader */
3922 static void si_llvm_emit_vertex(
3923 const struct lp_build_tgsi_action *action,
3924 struct lp_build_tgsi_context *bld_base,
3925 struct lp_build_emit_data *emit_data)
3926 {
3927 struct si_shader_context *ctx = si_shader_context(bld_base);
3928 struct lp_build_context *uint = &bld_base->uint_bld;
3929 struct si_shader *shader = ctx->shader;
3930 struct tgsi_shader_info *info = &shader->selector->info;
3931 struct gallivm_state *gallivm = &ctx->gallivm;
3932 struct lp_build_if_state if_state;
3933 LLVMValueRef soffset = LLVMGetParam(ctx->main_fn,
3934 ctx->param_gs2vs_offset);
3935 LLVMValueRef gs_next_vertex;
3936 LLVMValueRef can_emit, kill;
3937 unsigned chan, offset;
3938 int i;
3939 unsigned stream;
3940
3941 stream = si_llvm_get_stream(bld_base, emit_data);
3942
3943 /* Write vertex attribute values to GSVS ring */
3944 gs_next_vertex = LLVMBuildLoad(gallivm->builder,
3945 ctx->gs_next_vertex[stream],
3946 "");
3947
3948 /* If this thread has already emitted the declared maximum number of
3949 * vertices, skip the write: excessive vertex emissions are not
3950 * supposed to have any effect.
3951 *
3952 * If the shader has no writes to memory, kill it instead. This skips
3953 * further memory loads and may allow LLVM to skip to the end
3954 * altogether.
3955 */
3956 can_emit = LLVMBuildICmp(gallivm->builder, LLVMIntULT, gs_next_vertex,
3957 LLVMConstInt(ctx->i32,
3958 shader->selector->gs_max_out_vertices, 0), "");
3959
3960 bool use_kill = !info->writes_memory;
3961 if (use_kill) {
3962 kill = lp_build_select(&bld_base->base, can_emit,
3963 LLVMConstReal(ctx->f32, 1.0f),
3964 LLVMConstReal(ctx->f32, -1.0f));
3965
3966 ac_build_kill(&ctx->ac, kill);
3967 } else {
3968 lp_build_if(&if_state, gallivm, can_emit);
3969 }
3970
3971 offset = 0;
3972 for (i = 0; i < info->num_outputs; i++) {
3973 LLVMValueRef *out_ptr = ctx->outputs[i];
3974
3975 for (chan = 0; chan < 4; chan++) {
3976 if (!(info->output_usagemask[i] & (1 << chan)) ||
3977 ((info->output_streams[i] >> (2 * chan)) & 3) != stream)
3978 continue;
3979
3980 LLVMValueRef out_val = LLVMBuildLoad(gallivm->builder, out_ptr[chan], "");
3981 LLVMValueRef voffset =
3982 LLVMConstInt(ctx->i32, offset *
3983 shader->selector->gs_max_out_vertices, 0);
3984 offset++;
3985
3986 voffset = lp_build_add(uint, voffset, gs_next_vertex);
3987 voffset = lp_build_mul_imm(uint, voffset, 4);
3988
3989 out_val = LLVMBuildBitCast(gallivm->builder, out_val, ctx->i32, "");
3990
3991 ac_build_buffer_store_dword(&ctx->ac,
3992 ctx->gsvs_ring[stream],
3993 out_val, 1,
3994 voffset, soffset, 0,
3995 1, 1, true, true);
3996 }
3997 }
3998
3999 gs_next_vertex = lp_build_add(uint, gs_next_vertex,
4000 ctx->i32_1);
4001
4002 LLVMBuildStore(gallivm->builder, gs_next_vertex, ctx->gs_next_vertex[stream]);
4003
4004 /* Signal vertex emission */
4005 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_EMIT | AC_SENDMSG_GS | (stream << 8),
4006 si_get_gs_wave_id(ctx));
4007 if (!use_kill)
4008 lp_build_endif(&if_state);
4009 }
4010
4011 /* Cut one primitive from the geometry shader */
4012 static void si_llvm_emit_primitive(
4013 const struct lp_build_tgsi_action *action,
4014 struct lp_build_tgsi_context *bld_base,
4015 struct lp_build_emit_data *emit_data)
4016 {
4017 struct si_shader_context *ctx = si_shader_context(bld_base);
4018 unsigned stream;
4019
4020 /* Signal primitive cut */
4021 stream = si_llvm_get_stream(bld_base, emit_data);
4022 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_CUT | AC_SENDMSG_GS | (stream << 8),
4023 si_get_gs_wave_id(ctx));
4024 }
4025
4026 static void si_llvm_emit_barrier(const struct lp_build_tgsi_action *action,
4027 struct lp_build_tgsi_context *bld_base,
4028 struct lp_build_emit_data *emit_data)
4029 {
4030 struct si_shader_context *ctx = si_shader_context(bld_base);
4031 struct gallivm_state *gallivm = &ctx->gallivm;
4032
4033 /* SI only (thanks to a hw bug workaround):
4034 * The real barrier instruction isn’t needed, because an entire patch
4035 * always fits into a single wave.
4036 */
4037 if (ctx->screen->b.chip_class == SI &&
4038 ctx->type == PIPE_SHADER_TESS_CTRL) {
4039 si_emit_waitcnt(ctx, LGKM_CNT & VM_CNT);
4040 return;
4041 }
4042
4043 lp_build_intrinsic(gallivm->builder,
4044 "llvm.amdgcn.s.barrier",
4045 ctx->voidt, NULL, 0, LP_FUNC_ATTR_CONVERGENT);
4046 }
4047
4048 static const struct lp_build_tgsi_action interp_action = {
4049 .fetch_args = interp_fetch_args,
4050 .emit = build_interp_intrinsic,
4051 };
4052
4053 static void si_create_function(struct si_shader_context *ctx,
4054 const char *name,
4055 LLVMTypeRef *returns, unsigned num_returns,
4056 struct si_function_info *fninfo,
4057 unsigned max_workgroup_size)
4058 {
4059 int i;
4060
4061 si_llvm_create_func(ctx, name, returns, num_returns,
4062 fninfo->types, fninfo->num_params);
4063 ctx->return_value = LLVMGetUndef(ctx->return_type);
4064
4065 for (i = 0; i < fninfo->num_sgpr_params; ++i) {
4066 LLVMValueRef P = LLVMGetParam(ctx->main_fn, i);
4067
4068 /* The combination of:
4069 * - ByVal
4070 * - dereferenceable
4071 * - invariant.load
4072 * allows the optimization passes to move loads and reduces
4073 * SGPR spilling significantly.
4074 */
4075 if (LLVMGetTypeKind(LLVMTypeOf(P)) == LLVMPointerTypeKind) {
4076 lp_add_function_attr(ctx->main_fn, i + 1, LP_FUNC_ATTR_BYVAL);
4077 lp_add_function_attr(ctx->main_fn, i + 1, LP_FUNC_ATTR_NOALIAS);
4078 ac_add_attr_dereferenceable(P, UINT64_MAX);
4079 } else
4080 lp_add_function_attr(ctx->main_fn, i + 1, LP_FUNC_ATTR_INREG);
4081 }
4082
4083 for (i = 0; i < fninfo->num_params; ++i) {
4084 if (fninfo->assign[i])
4085 *fninfo->assign[i] = LLVMGetParam(ctx->main_fn, i);
4086 }
4087
4088 if (max_workgroup_size) {
4089 si_llvm_add_attribute(ctx->main_fn, "amdgpu-max-work-group-size",
4090 max_workgroup_size);
4091 }
4092 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
4093 "no-signed-zeros-fp-math",
4094 "true");
4095
4096 if (ctx->screen->b.debug_flags & DBG_UNSAFE_MATH) {
4097 /* These were copied from some LLVM test. */
4098 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
4099 "less-precise-fpmad",
4100 "true");
4101 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
4102 "no-infs-fp-math",
4103 "true");
4104 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
4105 "no-nans-fp-math",
4106 "true");
4107 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
4108 "unsafe-fp-math",
4109 "true");
4110 }
4111 }
4112
4113 static void declare_streamout_params(struct si_shader_context *ctx,
4114 struct pipe_stream_output_info *so,
4115 struct si_function_info *fninfo)
4116 {
4117 int i;
4118
4119 /* Streamout SGPRs. */
4120 if (so->num_outputs) {
4121 if (ctx->type != PIPE_SHADER_TESS_EVAL)
4122 ctx->param_streamout_config = add_arg(fninfo, ARG_SGPR, ctx->ac.i32);
4123 else
4124 ctx->param_streamout_config = fninfo->num_params - 1;
4125
4126 ctx->param_streamout_write_index = add_arg(fninfo, ARG_SGPR, ctx->ac.i32);
4127 }
4128 /* A streamout buffer offset is loaded if the stride is non-zero. */
4129 for (i = 0; i < 4; i++) {
4130 if (!so->stride[i])
4131 continue;
4132
4133 ctx->param_streamout_offset[i] = add_arg(fninfo, ARG_SGPR, ctx->ac.i32);
4134 }
4135 }
4136
4137 static unsigned llvm_get_type_size(LLVMTypeRef type)
4138 {
4139 LLVMTypeKind kind = LLVMGetTypeKind(type);
4140
4141 switch (kind) {
4142 case LLVMIntegerTypeKind:
4143 return LLVMGetIntTypeWidth(type) / 8;
4144 case LLVMFloatTypeKind:
4145 return 4;
4146 case LLVMPointerTypeKind:
4147 return 8;
4148 case LLVMVectorTypeKind:
4149 return LLVMGetVectorSize(type) *
4150 llvm_get_type_size(LLVMGetElementType(type));
4151 case LLVMArrayTypeKind:
4152 return LLVMGetArrayLength(type) *
4153 llvm_get_type_size(LLVMGetElementType(type));
4154 default:
4155 assert(0);
4156 return 0;
4157 }
4158 }
4159
4160 static void declare_lds_as_pointer(struct si_shader_context *ctx)
4161 {
4162 struct gallivm_state *gallivm = &ctx->gallivm;
4163
4164 unsigned lds_size = ctx->screen->b.chip_class >= CIK ? 65536 : 32768;
4165 ctx->lds = LLVMBuildIntToPtr(gallivm->builder, ctx->i32_0,
4166 LLVMPointerType(LLVMArrayType(ctx->i32, lds_size / 4), LOCAL_ADDR_SPACE),
4167 "lds");
4168 }
4169
4170 static unsigned si_get_max_workgroup_size(const struct si_shader *shader)
4171 {
4172 switch (shader->selector->type) {
4173 case PIPE_SHADER_TESS_CTRL:
4174 /* Return this so that LLVM doesn't remove s_barrier
4175 * instructions on chips where we use s_barrier. */
4176 return shader->selector->screen->b.chip_class >= CIK ? 128 : 64;
4177
4178 case PIPE_SHADER_GEOMETRY:
4179 return shader->selector->screen->b.chip_class >= GFX9 ? 128 : 64;
4180
4181 case PIPE_SHADER_COMPUTE:
4182 break; /* see below */
4183
4184 default:
4185 return 0;
4186 }
4187
4188 const unsigned *properties = shader->selector->info.properties;
4189 unsigned max_work_group_size =
4190 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] *
4191 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT] *
4192 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH];
4193
4194 if (!max_work_group_size) {
4195 /* This is a variable group size compute shader,
4196 * compile it for the maximum possible group size.
4197 */
4198 max_work_group_size = SI_MAX_VARIABLE_THREADS_PER_BLOCK;
4199 }
4200 return max_work_group_size;
4201 }
4202
4203 static void declare_per_stage_desc_pointers(struct si_shader_context *ctx,
4204 struct si_function_info *fninfo,
4205 bool assign_params)
4206 {
4207 unsigned const_and_shader_buffers =
4208 add_arg(fninfo, ARG_SGPR,
4209 si_const_array(ctx->v4i32,
4210 SI_NUM_SHADER_BUFFERS + SI_NUM_CONST_BUFFERS));
4211 unsigned samplers_and_images =
4212 add_arg(fninfo, ARG_SGPR,
4213 si_const_array(ctx->v8i32,
4214 SI_NUM_IMAGES + SI_NUM_SAMPLERS * 2));
4215
4216 if (assign_params) {
4217 ctx->param_const_and_shader_buffers = const_and_shader_buffers;
4218 ctx->param_samplers_and_images = samplers_and_images;
4219 }
4220 }
4221
4222 static void declare_default_desc_pointers(struct si_shader_context *ctx,
4223 struct si_function_info *fninfo)
4224 {
4225 ctx->param_rw_buffers = add_arg(fninfo, ARG_SGPR,
4226 si_const_array(ctx->v4i32, SI_NUM_RW_BUFFERS));
4227 declare_per_stage_desc_pointers(ctx, fninfo, true);
4228 }
4229
4230 static void declare_vs_specific_input_sgprs(struct si_shader_context *ctx,
4231 struct si_function_info *fninfo)
4232 {
4233 ctx->param_vertex_buffers = add_arg(fninfo, ARG_SGPR,
4234 si_const_array(ctx->v4i32, SI_NUM_VERTEX_BUFFERS));
4235 add_arg_assign(fninfo, ARG_SGPR, ctx->i32, &ctx->abi.base_vertex);
4236 add_arg_assign(fninfo, ARG_SGPR, ctx->i32, &ctx->abi.start_instance);
4237 add_arg_assign(fninfo, ARG_SGPR, ctx->i32, &ctx->abi.draw_id);
4238 ctx->param_vs_state_bits = add_arg(fninfo, ARG_SGPR, ctx->i32);
4239 }
4240
4241 static void declare_vs_input_vgprs(struct si_shader_context *ctx,
4242 struct si_function_info *fninfo,
4243 unsigned *num_prolog_vgprs)
4244 {
4245 struct si_shader *shader = ctx->shader;
4246
4247 add_arg_assign(fninfo, ARG_VGPR, ctx->i32, &ctx->abi.vertex_id);
4248 if (shader->key.as_ls) {
4249 ctx->param_rel_auto_id = add_arg(fninfo, ARG_VGPR, ctx->i32);
4250 add_arg_assign(fninfo, ARG_VGPR, ctx->i32, &ctx->abi.instance_id);
4251 } else {
4252 add_arg_assign(fninfo, ARG_VGPR, ctx->i32, &ctx->abi.instance_id);
4253 ctx->param_vs_prim_id = add_arg(fninfo, ARG_VGPR, ctx->i32);
4254 }
4255 add_arg(fninfo, ARG_VGPR, ctx->i32); /* unused */
4256
4257 if (!shader->is_gs_copy_shader) {
4258 /* Vertex load indices. */
4259 ctx->param_vertex_index0 = fninfo->num_params;
4260 for (unsigned i = 0; i < shader->selector->info.num_inputs; i++)
4261 add_arg(fninfo, ARG_VGPR, ctx->i32);
4262 *num_prolog_vgprs += shader->selector->info.num_inputs;
4263 }
4264 }
4265
4266 static void declare_tes_input_vgprs(struct si_shader_context *ctx,
4267 struct si_function_info *fninfo)
4268 {
4269 ctx->param_tes_u = add_arg(fninfo, ARG_VGPR, ctx->f32);
4270 ctx->param_tes_v = add_arg(fninfo, ARG_VGPR, ctx->f32);
4271 ctx->param_tes_rel_patch_id = add_arg(fninfo, ARG_VGPR, ctx->i32);
4272 ctx->param_tes_patch_id = add_arg(fninfo, ARG_VGPR, ctx->i32);
4273 }
4274
4275 enum {
4276 /* Convenient merged shader definitions. */
4277 SI_SHADER_MERGED_VERTEX_TESSCTRL = PIPE_SHADER_TYPES,
4278 SI_SHADER_MERGED_VERTEX_OR_TESSEVAL_GEOMETRY,
4279 };
4280
4281 static void create_function(struct si_shader_context *ctx)
4282 {
4283 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
4284 struct gallivm_state *gallivm = &ctx->gallivm;
4285 struct si_shader *shader = ctx->shader;
4286 struct si_function_info fninfo;
4287 LLVMTypeRef returns[16+32*4];
4288 unsigned i, num_return_sgprs;
4289 unsigned num_returns = 0;
4290 unsigned num_prolog_vgprs = 0;
4291 unsigned type = ctx->type;
4292
4293 si_init_function_info(&fninfo);
4294
4295 /* Set MERGED shaders. */
4296 if (ctx->screen->b.chip_class >= GFX9) {
4297 if (shader->key.as_ls || type == PIPE_SHADER_TESS_CTRL)
4298 type = SI_SHADER_MERGED_VERTEX_TESSCTRL; /* LS or HS */
4299 else if (shader->key.as_es || type == PIPE_SHADER_GEOMETRY)
4300 type = SI_SHADER_MERGED_VERTEX_OR_TESSEVAL_GEOMETRY;
4301 }
4302
4303 LLVMTypeRef v3i32 = LLVMVectorType(ctx->i32, 3);
4304
4305 switch (type) {
4306 case PIPE_SHADER_VERTEX:
4307 declare_default_desc_pointers(ctx, &fninfo);
4308 declare_vs_specific_input_sgprs(ctx, &fninfo);
4309
4310 if (shader->key.as_es) {
4311 ctx->param_es2gs_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4312 } else if (shader->key.as_ls) {
4313 /* no extra parameters */
4314 } else {
4315 if (shader->is_gs_copy_shader) {
4316 fninfo.num_params = ctx->param_rw_buffers + 1;
4317 fninfo.num_sgpr_params = fninfo.num_params;
4318 }
4319
4320 /* The locations of the other parameters are assigned dynamically. */
4321 declare_streamout_params(ctx, &shader->selector->so,
4322 &fninfo);
4323 }
4324
4325 /* VGPRs */
4326 declare_vs_input_vgprs(ctx, &fninfo, &num_prolog_vgprs);
4327 break;
4328
4329 case PIPE_SHADER_TESS_CTRL: /* SI-CI-VI */
4330 declare_default_desc_pointers(ctx, &fninfo);
4331 ctx->param_tcs_offchip_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4332 ctx->param_tcs_out_lds_offsets = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4333 ctx->param_tcs_out_lds_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4334 ctx->param_vs_state_bits = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4335 ctx->param_tcs_offchip_addr_base64k = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4336 ctx->param_tcs_factor_addr_base64k = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4337 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4338 ctx->param_tcs_factor_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4339
4340 /* VGPRs */
4341 ctx->param_tcs_patch_id = add_arg(&fninfo, ARG_VGPR, ctx->i32);
4342 ctx->param_tcs_rel_ids = add_arg(&fninfo, ARG_VGPR, ctx->i32);
4343
4344 /* param_tcs_offchip_offset and param_tcs_factor_offset are
4345 * placed after the user SGPRs.
4346 */
4347 for (i = 0; i < GFX6_TCS_NUM_USER_SGPR + 2; i++)
4348 returns[num_returns++] = ctx->i32; /* SGPRs */
4349 for (i = 0; i < 5; i++)
4350 returns[num_returns++] = ctx->f32; /* VGPRs */
4351 break;
4352
4353 case SI_SHADER_MERGED_VERTEX_TESSCTRL:
4354 /* Merged stages have 8 system SGPRs at the beginning. */
4355 ctx->param_rw_buffers = /* SPI_SHADER_USER_DATA_ADDR_LO_HS */
4356 add_arg(&fninfo, ARG_SGPR, si_const_array(ctx->v4i32, SI_NUM_RW_BUFFERS));
4357 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4358 ctx->param_merged_wave_info = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4359 ctx->param_tcs_factor_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4360 ctx->param_merged_scratch_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4361 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused */
4362 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused */
4363
4364 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused */
4365 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused */
4366 declare_per_stage_desc_pointers(ctx, &fninfo,
4367 ctx->type == PIPE_SHADER_VERTEX);
4368 declare_vs_specific_input_sgprs(ctx, &fninfo);
4369
4370 ctx->param_tcs_offchip_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4371 ctx->param_tcs_out_lds_offsets = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4372 ctx->param_tcs_out_lds_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4373 ctx->param_tcs_offchip_addr_base64k = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4374 ctx->param_tcs_factor_addr_base64k = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4375 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused */
4376
4377 declare_per_stage_desc_pointers(ctx, &fninfo,
4378 ctx->type == PIPE_SHADER_TESS_CTRL);
4379
4380 /* VGPRs (first TCS, then VS) */
4381 ctx->param_tcs_patch_id = add_arg(&fninfo, ARG_VGPR, ctx->i32);
4382 ctx->param_tcs_rel_ids = add_arg(&fninfo, ARG_VGPR, ctx->i32);
4383
4384 if (ctx->type == PIPE_SHADER_VERTEX) {
4385 declare_vs_input_vgprs(ctx, &fninfo,
4386 &num_prolog_vgprs);
4387
4388 /* LS return values are inputs to the TCS main shader part. */
4389 for (i = 0; i < 8 + GFX9_TCS_NUM_USER_SGPR; i++)
4390 returns[num_returns++] = ctx->i32; /* SGPRs */
4391 for (i = 0; i < 2; i++)
4392 returns[num_returns++] = ctx->f32; /* VGPRs */
4393 } else {
4394 /* TCS return values are inputs to the TCS epilog.
4395 *
4396 * param_tcs_offchip_offset, param_tcs_factor_offset,
4397 * param_tcs_offchip_layout, and param_rw_buffers
4398 * should be passed to the epilog.
4399 */
4400 for (i = 0; i <= 8 + GFX9_SGPR_TCS_FACTOR_ADDR_BASE64K; i++)
4401 returns[num_returns++] = ctx->i32; /* SGPRs */
4402 for (i = 0; i < 5; i++)
4403 returns[num_returns++] = ctx->f32; /* VGPRs */
4404 }
4405 break;
4406
4407 case SI_SHADER_MERGED_VERTEX_OR_TESSEVAL_GEOMETRY:
4408 /* Merged stages have 8 system SGPRs at the beginning. */
4409 ctx->param_rw_buffers = /* SPI_SHADER_USER_DATA_ADDR_LO_GS */
4410 add_arg(&fninfo, ARG_SGPR, si_const_array(ctx->v4i32, SI_NUM_RW_BUFFERS));
4411 ctx->param_gs2vs_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4412 ctx->param_merged_wave_info = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4413 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4414 ctx->param_merged_scratch_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4415 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused (SPI_SHADER_PGM_LO/HI_GS << 8) */
4416 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused (SPI_SHADER_PGM_LO/HI_GS >> 24) */
4417
4418 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused */
4419 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused */
4420 declare_per_stage_desc_pointers(ctx, &fninfo,
4421 (ctx->type == PIPE_SHADER_VERTEX ||
4422 ctx->type == PIPE_SHADER_TESS_EVAL));
4423 if (ctx->type == PIPE_SHADER_VERTEX) {
4424 declare_vs_specific_input_sgprs(ctx, &fninfo);
4425 } else {
4426 /* TESS_EVAL (and also GEOMETRY):
4427 * Declare as many input SGPRs as the VS has. */
4428 ctx->param_tcs_offchip_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4429 ctx->param_tcs_offchip_addr_base64k = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4430 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused */
4431 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused */
4432 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused */
4433 ctx->param_vs_state_bits = add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused */
4434 }
4435
4436 declare_per_stage_desc_pointers(ctx, &fninfo,
4437 ctx->type == PIPE_SHADER_GEOMETRY);
4438
4439 /* VGPRs (first GS, then VS/TES) */
4440 ctx->param_gs_vtx01_offset = add_arg(&fninfo, ARG_VGPR, ctx->i32);
4441 ctx->param_gs_vtx23_offset = add_arg(&fninfo, ARG_VGPR, ctx->i32);
4442 ctx->param_gs_prim_id = add_arg(&fninfo, ARG_VGPR, ctx->i32);
4443 ctx->param_gs_instance_id = add_arg(&fninfo, ARG_VGPR, ctx->i32);
4444 ctx->param_gs_vtx45_offset = add_arg(&fninfo, ARG_VGPR, ctx->i32);
4445
4446 if (ctx->type == PIPE_SHADER_VERTEX) {
4447 declare_vs_input_vgprs(ctx, &fninfo,
4448 &num_prolog_vgprs);
4449 } else if (ctx->type == PIPE_SHADER_TESS_EVAL) {
4450 declare_tes_input_vgprs(ctx, &fninfo);
4451 }
4452
4453 if (ctx->type == PIPE_SHADER_VERTEX ||
4454 ctx->type == PIPE_SHADER_TESS_EVAL) {
4455 /* ES return values are inputs to GS. */
4456 for (i = 0; i < 8 + GFX9_GS_NUM_USER_SGPR; i++)
4457 returns[num_returns++] = ctx->i32; /* SGPRs */
4458 for (i = 0; i < 5; i++)
4459 returns[num_returns++] = ctx->f32; /* VGPRs */
4460 }
4461 break;
4462
4463 case PIPE_SHADER_TESS_EVAL:
4464 declare_default_desc_pointers(ctx, &fninfo);
4465 ctx->param_tcs_offchip_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4466 ctx->param_tcs_offchip_addr_base64k = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4467
4468 if (shader->key.as_es) {
4469 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4470 add_arg(&fninfo, ARG_SGPR, ctx->i32);
4471 ctx->param_es2gs_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4472 } else {
4473 add_arg(&fninfo, ARG_SGPR, ctx->i32);
4474 declare_streamout_params(ctx, &shader->selector->so,
4475 &fninfo);
4476 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4477 }
4478
4479 /* VGPRs */
4480 declare_tes_input_vgprs(ctx, &fninfo);
4481 break;
4482
4483 case PIPE_SHADER_GEOMETRY:
4484 declare_default_desc_pointers(ctx, &fninfo);
4485 ctx->param_gs2vs_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4486 ctx->param_gs_wave_id = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4487
4488 /* VGPRs */
4489 ctx->param_gs_vtx0_offset = add_arg(&fninfo, ARG_VGPR, ctx->i32);
4490 ctx->param_gs_vtx1_offset = add_arg(&fninfo, ARG_VGPR, ctx->i32);
4491 ctx->param_gs_prim_id = add_arg(&fninfo, ARG_VGPR, ctx->i32);
4492 ctx->param_gs_vtx2_offset = add_arg(&fninfo, ARG_VGPR, ctx->i32);
4493 ctx->param_gs_vtx3_offset = add_arg(&fninfo, ARG_VGPR, ctx->i32);
4494 ctx->param_gs_vtx4_offset = add_arg(&fninfo, ARG_VGPR, ctx->i32);
4495 ctx->param_gs_vtx5_offset = add_arg(&fninfo, ARG_VGPR, ctx->i32);
4496 ctx->param_gs_instance_id = add_arg(&fninfo, ARG_VGPR, ctx->i32);
4497 break;
4498
4499 case PIPE_SHADER_FRAGMENT:
4500 declare_default_desc_pointers(ctx, &fninfo);
4501 add_arg_checked(&fninfo, ARG_SGPR, ctx->f32, SI_PARAM_ALPHA_REF);
4502 add_arg_checked(&fninfo, ARG_SGPR, ctx->i32, SI_PARAM_PRIM_MASK);
4503
4504 add_arg_checked(&fninfo, ARG_VGPR, ctx->v2i32, SI_PARAM_PERSP_SAMPLE);
4505 add_arg_checked(&fninfo, ARG_VGPR, ctx->v2i32, SI_PARAM_PERSP_CENTER);
4506 add_arg_checked(&fninfo, ARG_VGPR, ctx->v2i32, SI_PARAM_PERSP_CENTROID);
4507 add_arg_checked(&fninfo, ARG_VGPR, v3i32, SI_PARAM_PERSP_PULL_MODEL);
4508 add_arg_checked(&fninfo, ARG_VGPR, ctx->v2i32, SI_PARAM_LINEAR_SAMPLE);
4509 add_arg_checked(&fninfo, ARG_VGPR, ctx->v2i32, SI_PARAM_LINEAR_CENTER);
4510 add_arg_checked(&fninfo, ARG_VGPR, ctx->v2i32, SI_PARAM_LINEAR_CENTROID);
4511 add_arg_checked(&fninfo, ARG_VGPR, ctx->f32, SI_PARAM_LINE_STIPPLE_TEX);
4512 add_arg_checked(&fninfo, ARG_VGPR, ctx->f32, SI_PARAM_POS_X_FLOAT);
4513 add_arg_checked(&fninfo, ARG_VGPR, ctx->f32, SI_PARAM_POS_Y_FLOAT);
4514 add_arg_checked(&fninfo, ARG_VGPR, ctx->f32, SI_PARAM_POS_Z_FLOAT);
4515 add_arg_checked(&fninfo, ARG_VGPR, ctx->f32, SI_PARAM_POS_W_FLOAT);
4516 add_arg_checked(&fninfo, ARG_VGPR, ctx->i32, SI_PARAM_FRONT_FACE);
4517 shader->info.face_vgpr_index = 20;
4518 add_arg_checked(&fninfo, ARG_VGPR, ctx->i32, SI_PARAM_ANCILLARY);
4519 add_arg_checked(&fninfo, ARG_VGPR, ctx->f32, SI_PARAM_SAMPLE_COVERAGE);
4520 add_arg_checked(&fninfo, ARG_VGPR, ctx->i32, SI_PARAM_POS_FIXED_PT);
4521
4522 /* Color inputs from the prolog. */
4523 if (shader->selector->info.colors_read) {
4524 unsigned num_color_elements =
4525 util_bitcount(shader->selector->info.colors_read);
4526
4527 assert(fninfo.num_params + num_color_elements <= ARRAY_SIZE(fninfo.types));
4528 for (i = 0; i < num_color_elements; i++)
4529 add_arg(&fninfo, ARG_VGPR, ctx->f32);
4530
4531 num_prolog_vgprs += num_color_elements;
4532 }
4533
4534 /* Outputs for the epilog. */
4535 num_return_sgprs = SI_SGPR_ALPHA_REF + 1;
4536 num_returns =
4537 num_return_sgprs +
4538 util_bitcount(shader->selector->info.colors_written) * 4 +
4539 shader->selector->info.writes_z +
4540 shader->selector->info.writes_stencil +
4541 shader->selector->info.writes_samplemask +
4542 1 /* SampleMaskIn */;
4543
4544 num_returns = MAX2(num_returns,
4545 num_return_sgprs +
4546 PS_EPILOG_SAMPLEMASK_MIN_LOC + 1);
4547
4548 for (i = 0; i < num_return_sgprs; i++)
4549 returns[i] = ctx->i32;
4550 for (; i < num_returns; i++)
4551 returns[i] = ctx->f32;
4552 break;
4553
4554 case PIPE_SHADER_COMPUTE:
4555 declare_default_desc_pointers(ctx, &fninfo);
4556 if (shader->selector->info.uses_grid_size)
4557 ctx->param_grid_size = add_arg(&fninfo, ARG_SGPR, v3i32);
4558 if (shader->selector->info.uses_block_size)
4559 ctx->param_block_size = add_arg(&fninfo, ARG_SGPR, v3i32);
4560
4561 for (i = 0; i < 3; i++) {
4562 ctx->param_block_id[i] = -1;
4563 if (shader->selector->info.uses_block_id[i])
4564 ctx->param_block_id[i] = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4565 }
4566
4567 ctx->param_thread_id = add_arg(&fninfo, ARG_VGPR, v3i32);
4568 break;
4569 default:
4570 assert(0 && "unimplemented shader");
4571 return;
4572 }
4573
4574 si_create_function(ctx, "main", returns, num_returns, &fninfo,
4575 si_get_max_workgroup_size(shader));
4576
4577 /* Reserve register locations for VGPR inputs the PS prolog may need. */
4578 if (ctx->type == PIPE_SHADER_FRAGMENT &&
4579 ctx->separate_prolog) {
4580 si_llvm_add_attribute(ctx->main_fn,
4581 "InitialPSInputAddr",
4582 S_0286D0_PERSP_SAMPLE_ENA(1) |
4583 S_0286D0_PERSP_CENTER_ENA(1) |
4584 S_0286D0_PERSP_CENTROID_ENA(1) |
4585 S_0286D0_LINEAR_SAMPLE_ENA(1) |
4586 S_0286D0_LINEAR_CENTER_ENA(1) |
4587 S_0286D0_LINEAR_CENTROID_ENA(1) |
4588 S_0286D0_FRONT_FACE_ENA(1) |
4589 S_0286D0_POS_FIXED_PT_ENA(1));
4590 }
4591
4592 shader->info.num_input_sgprs = 0;
4593 shader->info.num_input_vgprs = 0;
4594
4595 for (i = 0; i < fninfo.num_sgpr_params; ++i)
4596 shader->info.num_input_sgprs += llvm_get_type_size(fninfo.types[i]) / 4;
4597
4598 for (; i < fninfo.num_params; ++i)
4599 shader->info.num_input_vgprs += llvm_get_type_size(fninfo.types[i]) / 4;
4600
4601 assert(shader->info.num_input_vgprs >= num_prolog_vgprs);
4602 shader->info.num_input_vgprs -= num_prolog_vgprs;
4603
4604 if (!ctx->screen->has_ds_bpermute &&
4605 bld_base->info &&
4606 (bld_base->info->opcode_count[TGSI_OPCODE_DDX] > 0 ||
4607 bld_base->info->opcode_count[TGSI_OPCODE_DDY] > 0 ||
4608 bld_base->info->opcode_count[TGSI_OPCODE_DDX_FINE] > 0 ||
4609 bld_base->info->opcode_count[TGSI_OPCODE_DDY_FINE] > 0 ||
4610 bld_base->info->opcode_count[TGSI_OPCODE_INTERP_OFFSET] > 0 ||
4611 bld_base->info->opcode_count[TGSI_OPCODE_INTERP_SAMPLE] > 0))
4612 ctx->lds =
4613 LLVMAddGlobalInAddressSpace(gallivm->module,
4614 LLVMArrayType(ctx->i32, 64),
4615 "ddxy_lds",
4616 LOCAL_ADDR_SPACE);
4617
4618 if (shader->key.as_ls ||
4619 ctx->type == PIPE_SHADER_TESS_CTRL ||
4620 /* GFX9 has the ESGS ring buffer in LDS. */
4621 (ctx->screen->b.chip_class >= GFX9 &&
4622 (shader->key.as_es ||
4623 ctx->type == PIPE_SHADER_GEOMETRY)))
4624 declare_lds_as_pointer(ctx);
4625 }
4626
4627 /**
4628 * Load ESGS and GSVS ring buffer resource descriptors and save the variables
4629 * for later use.
4630 */
4631 static void preload_ring_buffers(struct si_shader_context *ctx)
4632 {
4633 struct gallivm_state *gallivm = &ctx->gallivm;
4634 LLVMBuilderRef builder = gallivm->builder;
4635
4636 LLVMValueRef buf_ptr = LLVMGetParam(ctx->main_fn,
4637 ctx->param_rw_buffers);
4638
4639 if (ctx->screen->b.chip_class <= VI &&
4640 (ctx->shader->key.as_es || ctx->type == PIPE_SHADER_GEOMETRY)) {
4641 unsigned ring =
4642 ctx->type == PIPE_SHADER_GEOMETRY ? SI_GS_RING_ESGS
4643 : SI_ES_RING_ESGS;
4644 LLVMValueRef offset = LLVMConstInt(ctx->i32, ring, 0);
4645
4646 ctx->esgs_ring =
4647 ac_build_indexed_load_const(&ctx->ac, buf_ptr, offset);
4648 }
4649
4650 if (ctx->shader->is_gs_copy_shader) {
4651 LLVMValueRef offset = LLVMConstInt(ctx->i32, SI_RING_GSVS, 0);
4652
4653 ctx->gsvs_ring[0] =
4654 ac_build_indexed_load_const(&ctx->ac, buf_ptr, offset);
4655 } else if (ctx->type == PIPE_SHADER_GEOMETRY) {
4656 const struct si_shader_selector *sel = ctx->shader->selector;
4657 LLVMValueRef offset = LLVMConstInt(ctx->i32, SI_RING_GSVS, 0);
4658 LLVMValueRef base_ring;
4659
4660 base_ring = ac_build_indexed_load_const(&ctx->ac, buf_ptr, offset);
4661
4662 /* The conceptual layout of the GSVS ring is
4663 * v0c0 .. vLv0 v0c1 .. vLc1 ..
4664 * but the real memory layout is swizzled across
4665 * threads:
4666 * t0v0c0 .. t15v0c0 t0v1c0 .. t15v1c0 ... t15vLcL
4667 * t16v0c0 ..
4668 * Override the buffer descriptor accordingly.
4669 */
4670 LLVMTypeRef v2i64 = LLVMVectorType(ctx->i64, 2);
4671 uint64_t stream_offset = 0;
4672
4673 for (unsigned stream = 0; stream < 4; ++stream) {
4674 unsigned num_components;
4675 unsigned stride;
4676 unsigned num_records;
4677 LLVMValueRef ring, tmp;
4678
4679 num_components = sel->info.num_stream_output_components[stream];
4680 if (!num_components)
4681 continue;
4682
4683 stride = 4 * num_components * sel->gs_max_out_vertices;
4684
4685 /* Limit on the stride field for <= CIK. */
4686 assert(stride < (1 << 14));
4687
4688 num_records = 64;
4689
4690 ring = LLVMBuildBitCast(builder, base_ring, v2i64, "");
4691 tmp = LLVMBuildExtractElement(builder, ring, ctx->i32_0, "");
4692 tmp = LLVMBuildAdd(builder, tmp,
4693 LLVMConstInt(ctx->i64,
4694 stream_offset, 0), "");
4695 stream_offset += stride * 64;
4696
4697 ring = LLVMBuildInsertElement(builder, ring, tmp, ctx->i32_0, "");
4698 ring = LLVMBuildBitCast(builder, ring, ctx->v4i32, "");
4699 tmp = LLVMBuildExtractElement(builder, ring, ctx->i32_1, "");
4700 tmp = LLVMBuildOr(builder, tmp,
4701 LLVMConstInt(ctx->i32,
4702 S_008F04_STRIDE(stride) |
4703 S_008F04_SWIZZLE_ENABLE(1), 0), "");
4704 ring = LLVMBuildInsertElement(builder, ring, tmp, ctx->i32_1, "");
4705 ring = LLVMBuildInsertElement(builder, ring,
4706 LLVMConstInt(ctx->i32, num_records, 0),
4707 LLVMConstInt(ctx->i32, 2, 0), "");
4708 ring = LLVMBuildInsertElement(builder, ring,
4709 LLVMConstInt(ctx->i32,
4710 S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
4711 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
4712 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
4713 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
4714 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
4715 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
4716 S_008F0C_ELEMENT_SIZE(1) | /* element_size = 4 (bytes) */
4717 S_008F0C_INDEX_STRIDE(1) | /* index_stride = 16 (elements) */
4718 S_008F0C_ADD_TID_ENABLE(1),
4719 0),
4720 LLVMConstInt(ctx->i32, 3, 0), "");
4721
4722 ctx->gsvs_ring[stream] = ring;
4723 }
4724 }
4725 }
4726
4727 static void si_llvm_emit_polygon_stipple(struct si_shader_context *ctx,
4728 LLVMValueRef param_rw_buffers,
4729 unsigned param_pos_fixed_pt)
4730 {
4731 struct gallivm_state *gallivm = &ctx->gallivm;
4732 LLVMBuilderRef builder = gallivm->builder;
4733 LLVMValueRef slot, desc, offset, row, bit, address[2];
4734
4735 /* Use the fixed-point gl_FragCoord input.
4736 * Since the stipple pattern is 32x32 and it repeats, just get 5 bits
4737 * per coordinate to get the repeating effect.
4738 */
4739 address[0] = unpack_param(ctx, param_pos_fixed_pt, 0, 5);
4740 address[1] = unpack_param(ctx, param_pos_fixed_pt, 16, 5);
4741
4742 /* Load the buffer descriptor. */
4743 slot = LLVMConstInt(ctx->i32, SI_PS_CONST_POLY_STIPPLE, 0);
4744 desc = ac_build_indexed_load_const(&ctx->ac, param_rw_buffers, slot);
4745
4746 /* The stipple pattern is 32x32, each row has 32 bits. */
4747 offset = LLVMBuildMul(builder, address[1],
4748 LLVMConstInt(ctx->i32, 4, 0), "");
4749 row = buffer_load_const(ctx, desc, offset);
4750 row = LLVMBuildBitCast(builder, row, ctx->i32, "");
4751 bit = LLVMBuildLShr(builder, row, address[0], "");
4752 bit = LLVMBuildTrunc(builder, bit, ctx->i1, "");
4753
4754 /* The intrinsic kills the thread if arg < 0. */
4755 bit = LLVMBuildSelect(builder, bit, LLVMConstReal(ctx->f32, 0),
4756 LLVMConstReal(ctx->f32, -1), "");
4757 ac_build_kill(&ctx->ac, bit);
4758 }
4759
4760 void si_shader_binary_read_config(struct ac_shader_binary *binary,
4761 struct si_shader_config *conf,
4762 unsigned symbol_offset)
4763 {
4764 unsigned i;
4765 const unsigned char *config =
4766 ac_shader_binary_config_start(binary, symbol_offset);
4767 bool really_needs_scratch = false;
4768
4769 /* LLVM adds SGPR spills to the scratch size.
4770 * Find out if we really need the scratch buffer.
4771 */
4772 for (i = 0; i < binary->reloc_count; i++) {
4773 const struct ac_shader_reloc *reloc = &binary->relocs[i];
4774
4775 if (!strcmp(scratch_rsrc_dword0_symbol, reloc->name) ||
4776 !strcmp(scratch_rsrc_dword1_symbol, reloc->name)) {
4777 really_needs_scratch = true;
4778 break;
4779 }
4780 }
4781
4782 /* XXX: We may be able to emit some of these values directly rather than
4783 * extracting fields to be emitted later.
4784 */
4785
4786 for (i = 0; i < binary->config_size_per_symbol; i+= 8) {
4787 unsigned reg = util_le32_to_cpu(*(uint32_t*)(config + i));
4788 unsigned value = util_le32_to_cpu(*(uint32_t*)(config + i + 4));
4789 switch (reg) {
4790 case R_00B028_SPI_SHADER_PGM_RSRC1_PS:
4791 case R_00B128_SPI_SHADER_PGM_RSRC1_VS:
4792 case R_00B228_SPI_SHADER_PGM_RSRC1_GS:
4793 case R_00B428_SPI_SHADER_PGM_RSRC1_HS:
4794 case R_00B848_COMPUTE_PGM_RSRC1:
4795 conf->num_sgprs = MAX2(conf->num_sgprs, (G_00B028_SGPRS(value) + 1) * 8);
4796 conf->num_vgprs = MAX2(conf->num_vgprs, (G_00B028_VGPRS(value) + 1) * 4);
4797 conf->float_mode = G_00B028_FLOAT_MODE(value);
4798 conf->rsrc1 = value;
4799 break;
4800 case R_00B02C_SPI_SHADER_PGM_RSRC2_PS:
4801 conf->lds_size = MAX2(conf->lds_size, G_00B02C_EXTRA_LDS_SIZE(value));
4802 break;
4803 case R_00B84C_COMPUTE_PGM_RSRC2:
4804 conf->lds_size = MAX2(conf->lds_size, G_00B84C_LDS_SIZE(value));
4805 conf->rsrc2 = value;
4806 break;
4807 case R_0286CC_SPI_PS_INPUT_ENA:
4808 conf->spi_ps_input_ena = value;
4809 break;
4810 case R_0286D0_SPI_PS_INPUT_ADDR:
4811 conf->spi_ps_input_addr = value;
4812 break;
4813 case R_0286E8_SPI_TMPRING_SIZE:
4814 case R_00B860_COMPUTE_TMPRING_SIZE:
4815 /* WAVESIZE is in units of 256 dwords. */
4816 if (really_needs_scratch)
4817 conf->scratch_bytes_per_wave =
4818 G_00B860_WAVESIZE(value) * 256 * 4;
4819 break;
4820 case 0x4: /* SPILLED_SGPRS */
4821 conf->spilled_sgprs = value;
4822 break;
4823 case 0x8: /* SPILLED_VGPRS */
4824 conf->spilled_vgprs = value;
4825 break;
4826 default:
4827 {
4828 static bool printed;
4829
4830 if (!printed) {
4831 fprintf(stderr, "Warning: LLVM emitted unknown "
4832 "config register: 0x%x\n", reg);
4833 printed = true;
4834 }
4835 }
4836 break;
4837 }
4838 }
4839
4840 if (!conf->spi_ps_input_addr)
4841 conf->spi_ps_input_addr = conf->spi_ps_input_ena;
4842 }
4843
4844 void si_shader_apply_scratch_relocs(struct si_shader *shader,
4845 uint64_t scratch_va)
4846 {
4847 unsigned i;
4848 uint32_t scratch_rsrc_dword0 = scratch_va;
4849 uint32_t scratch_rsrc_dword1 =
4850 S_008F04_BASE_ADDRESS_HI(scratch_va >> 32);
4851
4852 /* Enable scratch coalescing. */
4853 scratch_rsrc_dword1 |= S_008F04_SWIZZLE_ENABLE(1);
4854
4855 for (i = 0 ; i < shader->binary.reloc_count; i++) {
4856 const struct ac_shader_reloc *reloc =
4857 &shader->binary.relocs[i];
4858 if (!strcmp(scratch_rsrc_dword0_symbol, reloc->name)) {
4859 util_memcpy_cpu_to_le32(shader->binary.code + reloc->offset,
4860 &scratch_rsrc_dword0, 4);
4861 } else if (!strcmp(scratch_rsrc_dword1_symbol, reloc->name)) {
4862 util_memcpy_cpu_to_le32(shader->binary.code + reloc->offset,
4863 &scratch_rsrc_dword1, 4);
4864 }
4865 }
4866 }
4867
4868 static unsigned si_get_shader_binary_size(const struct si_shader *shader)
4869 {
4870 unsigned size = shader->binary.code_size;
4871
4872 if (shader->prolog)
4873 size += shader->prolog->binary.code_size;
4874 if (shader->previous_stage)
4875 size += shader->previous_stage->binary.code_size;
4876 if (shader->prolog2)
4877 size += shader->prolog2->binary.code_size;
4878 if (shader->epilog)
4879 size += shader->epilog->binary.code_size;
4880 return size;
4881 }
4882
4883 int si_shader_binary_upload(struct si_screen *sscreen, struct si_shader *shader)
4884 {
4885 const struct ac_shader_binary *prolog =
4886 shader->prolog ? &shader->prolog->binary : NULL;
4887 const struct ac_shader_binary *previous_stage =
4888 shader->previous_stage ? &shader->previous_stage->binary : NULL;
4889 const struct ac_shader_binary *prolog2 =
4890 shader->prolog2 ? &shader->prolog2->binary : NULL;
4891 const struct ac_shader_binary *epilog =
4892 shader->epilog ? &shader->epilog->binary : NULL;
4893 const struct ac_shader_binary *mainb = &shader->binary;
4894 unsigned bo_size = si_get_shader_binary_size(shader) +
4895 (!epilog ? mainb->rodata_size : 0);
4896 unsigned char *ptr;
4897
4898 assert(!prolog || !prolog->rodata_size);
4899 assert(!previous_stage || !previous_stage->rodata_size);
4900 assert(!prolog2 || !prolog2->rodata_size);
4901 assert((!prolog && !previous_stage && !prolog2 && !epilog) ||
4902 !mainb->rodata_size);
4903 assert(!epilog || !epilog->rodata_size);
4904
4905 r600_resource_reference(&shader->bo, NULL);
4906 shader->bo = (struct r600_resource*)
4907 pipe_buffer_create(&sscreen->b.b, 0,
4908 PIPE_USAGE_IMMUTABLE,
4909 align(bo_size, SI_CPDMA_ALIGNMENT));
4910 if (!shader->bo)
4911 return -ENOMEM;
4912
4913 /* Upload. */
4914 ptr = sscreen->b.ws->buffer_map(shader->bo->buf, NULL,
4915 PIPE_TRANSFER_READ_WRITE |
4916 PIPE_TRANSFER_UNSYNCHRONIZED);
4917
4918 /* Don't use util_memcpy_cpu_to_le32. LLVM binaries are
4919 * endian-independent. */
4920 if (prolog) {
4921 memcpy(ptr, prolog->code, prolog->code_size);
4922 ptr += prolog->code_size;
4923 }
4924 if (previous_stage) {
4925 memcpy(ptr, previous_stage->code, previous_stage->code_size);
4926 ptr += previous_stage->code_size;
4927 }
4928 if (prolog2) {
4929 memcpy(ptr, prolog2->code, prolog2->code_size);
4930 ptr += prolog2->code_size;
4931 }
4932
4933 memcpy(ptr, mainb->code, mainb->code_size);
4934 ptr += mainb->code_size;
4935
4936 if (epilog)
4937 memcpy(ptr, epilog->code, epilog->code_size);
4938 else if (mainb->rodata_size > 0)
4939 memcpy(ptr, mainb->rodata, mainb->rodata_size);
4940
4941 sscreen->b.ws->buffer_unmap(shader->bo->buf);
4942 return 0;
4943 }
4944
4945 static void si_shader_dump_disassembly(const struct ac_shader_binary *binary,
4946 struct pipe_debug_callback *debug,
4947 const char *name, FILE *file)
4948 {
4949 char *line, *p;
4950 unsigned i, count;
4951
4952 if (binary->disasm_string) {
4953 fprintf(file, "Shader %s disassembly:\n", name);
4954 fprintf(file, "%s", binary->disasm_string);
4955
4956 if (debug && debug->debug_message) {
4957 /* Very long debug messages are cut off, so send the
4958 * disassembly one line at a time. This causes more
4959 * overhead, but on the plus side it simplifies
4960 * parsing of resulting logs.
4961 */
4962 pipe_debug_message(debug, SHADER_INFO,
4963 "Shader Disassembly Begin");
4964
4965 line = binary->disasm_string;
4966 while (*line) {
4967 p = util_strchrnul(line, '\n');
4968 count = p - line;
4969
4970 if (count) {
4971 pipe_debug_message(debug, SHADER_INFO,
4972 "%.*s", count, line);
4973 }
4974
4975 if (!*p)
4976 break;
4977 line = p + 1;
4978 }
4979
4980 pipe_debug_message(debug, SHADER_INFO,
4981 "Shader Disassembly End");
4982 }
4983 } else {
4984 fprintf(file, "Shader %s binary:\n", name);
4985 for (i = 0; i < binary->code_size; i += 4) {
4986 fprintf(file, "@0x%x: %02x%02x%02x%02x\n", i,
4987 binary->code[i + 3], binary->code[i + 2],
4988 binary->code[i + 1], binary->code[i]);
4989 }
4990 }
4991 }
4992
4993 static void si_shader_dump_stats(struct si_screen *sscreen,
4994 const struct si_shader *shader,
4995 struct pipe_debug_callback *debug,
4996 unsigned processor,
4997 FILE *file,
4998 bool check_debug_option)
4999 {
5000 const struct si_shader_config *conf = &shader->config;
5001 unsigned num_inputs = shader->selector ? shader->selector->info.num_inputs : 0;
5002 unsigned code_size = si_get_shader_binary_size(shader);
5003 unsigned lds_increment = sscreen->b.chip_class >= CIK ? 512 : 256;
5004 unsigned lds_per_wave = 0;
5005 unsigned max_simd_waves = 10;
5006
5007 /* Compute LDS usage for PS. */
5008 switch (processor) {
5009 case PIPE_SHADER_FRAGMENT:
5010 /* The minimum usage per wave is (num_inputs * 48). The maximum
5011 * usage is (num_inputs * 48 * 16).
5012 * We can get anything in between and it varies between waves.
5013 *
5014 * The 48 bytes per input for a single primitive is equal to
5015 * 4 bytes/component * 4 components/input * 3 points.
5016 *
5017 * Other stages don't know the size at compile time or don't
5018 * allocate LDS per wave, but instead they do it per thread group.
5019 */
5020 lds_per_wave = conf->lds_size * lds_increment +
5021 align(num_inputs * 48, lds_increment);
5022 break;
5023 case PIPE_SHADER_COMPUTE:
5024 if (shader->selector) {
5025 unsigned max_workgroup_size =
5026 si_get_max_workgroup_size(shader);
5027 lds_per_wave = (conf->lds_size * lds_increment) /
5028 DIV_ROUND_UP(max_workgroup_size, 64);
5029 }
5030 break;
5031 }
5032
5033 /* Compute the per-SIMD wave counts. */
5034 if (conf->num_sgprs) {
5035 if (sscreen->b.chip_class >= VI)
5036 max_simd_waves = MIN2(max_simd_waves, 800 / conf->num_sgprs);
5037 else
5038 max_simd_waves = MIN2(max_simd_waves, 512 / conf->num_sgprs);
5039 }
5040
5041 if (conf->num_vgprs)
5042 max_simd_waves = MIN2(max_simd_waves, 256 / conf->num_vgprs);
5043
5044 /* LDS is 64KB per CU (4 SIMDs), which is 16KB per SIMD (usage above
5045 * 16KB makes some SIMDs unoccupied). */
5046 if (lds_per_wave)
5047 max_simd_waves = MIN2(max_simd_waves, 16384 / lds_per_wave);
5048
5049 if (!check_debug_option ||
5050 r600_can_dump_shader(&sscreen->b, processor)) {
5051 if (processor == PIPE_SHADER_FRAGMENT) {
5052 fprintf(file, "*** SHADER CONFIG ***\n"
5053 "SPI_PS_INPUT_ADDR = 0x%04x\n"
5054 "SPI_PS_INPUT_ENA = 0x%04x\n",
5055 conf->spi_ps_input_addr, conf->spi_ps_input_ena);
5056 }
5057
5058 fprintf(file, "*** SHADER STATS ***\n"
5059 "SGPRS: %d\n"
5060 "VGPRS: %d\n"
5061 "Spilled SGPRs: %d\n"
5062 "Spilled VGPRs: %d\n"
5063 "Private memory VGPRs: %d\n"
5064 "Code Size: %d bytes\n"
5065 "LDS: %d blocks\n"
5066 "Scratch: %d bytes per wave\n"
5067 "Max Waves: %d\n"
5068 "********************\n\n\n",
5069 conf->num_sgprs, conf->num_vgprs,
5070 conf->spilled_sgprs, conf->spilled_vgprs,
5071 conf->private_mem_vgprs, code_size,
5072 conf->lds_size, conf->scratch_bytes_per_wave,
5073 max_simd_waves);
5074 }
5075
5076 pipe_debug_message(debug, SHADER_INFO,
5077 "Shader Stats: SGPRS: %d VGPRS: %d Code Size: %d "
5078 "LDS: %d Scratch: %d Max Waves: %d Spilled SGPRs: %d "
5079 "Spilled VGPRs: %d PrivMem VGPRs: %d",
5080 conf->num_sgprs, conf->num_vgprs, code_size,
5081 conf->lds_size, conf->scratch_bytes_per_wave,
5082 max_simd_waves, conf->spilled_sgprs,
5083 conf->spilled_vgprs, conf->private_mem_vgprs);
5084 }
5085
5086 const char *si_get_shader_name(const struct si_shader *shader, unsigned processor)
5087 {
5088 switch (processor) {
5089 case PIPE_SHADER_VERTEX:
5090 if (shader->key.as_es)
5091 return "Vertex Shader as ES";
5092 else if (shader->key.as_ls)
5093 return "Vertex Shader as LS";
5094 else
5095 return "Vertex Shader as VS";
5096 case PIPE_SHADER_TESS_CTRL:
5097 return "Tessellation Control Shader";
5098 case PIPE_SHADER_TESS_EVAL:
5099 if (shader->key.as_es)
5100 return "Tessellation Evaluation Shader as ES";
5101 else
5102 return "Tessellation Evaluation Shader as VS";
5103 case PIPE_SHADER_GEOMETRY:
5104 if (shader->is_gs_copy_shader)
5105 return "GS Copy Shader as VS";
5106 else
5107 return "Geometry Shader";
5108 case PIPE_SHADER_FRAGMENT:
5109 return "Pixel Shader";
5110 case PIPE_SHADER_COMPUTE:
5111 return "Compute Shader";
5112 default:
5113 return "Unknown Shader";
5114 }
5115 }
5116
5117 void si_shader_dump(struct si_screen *sscreen, const struct si_shader *shader,
5118 struct pipe_debug_callback *debug, unsigned processor,
5119 FILE *file, bool check_debug_option)
5120 {
5121 if (!check_debug_option ||
5122 r600_can_dump_shader(&sscreen->b, processor))
5123 si_dump_shader_key(processor, shader, file);
5124
5125 if (!check_debug_option && shader->binary.llvm_ir_string) {
5126 if (shader->previous_stage &&
5127 shader->previous_stage->binary.llvm_ir_string) {
5128 fprintf(file, "\n%s - previous stage - LLVM IR:\n\n",
5129 si_get_shader_name(shader, processor));
5130 fprintf(file, "%s\n", shader->previous_stage->binary.llvm_ir_string);
5131 }
5132
5133 fprintf(file, "\n%s - main shader part - LLVM IR:\n\n",
5134 si_get_shader_name(shader, processor));
5135 fprintf(file, "%s\n", shader->binary.llvm_ir_string);
5136 }
5137
5138 if (!check_debug_option ||
5139 (r600_can_dump_shader(&sscreen->b, processor) &&
5140 !(sscreen->b.debug_flags & DBG_NO_ASM))) {
5141 fprintf(file, "\n%s:\n", si_get_shader_name(shader, processor));
5142
5143 if (shader->prolog)
5144 si_shader_dump_disassembly(&shader->prolog->binary,
5145 debug, "prolog", file);
5146 if (shader->previous_stage)
5147 si_shader_dump_disassembly(&shader->previous_stage->binary,
5148 debug, "previous stage", file);
5149 if (shader->prolog2)
5150 si_shader_dump_disassembly(&shader->prolog2->binary,
5151 debug, "prolog2", file);
5152
5153 si_shader_dump_disassembly(&shader->binary, debug, "main", file);
5154
5155 if (shader->epilog)
5156 si_shader_dump_disassembly(&shader->epilog->binary,
5157 debug, "epilog", file);
5158 fprintf(file, "\n");
5159 }
5160
5161 si_shader_dump_stats(sscreen, shader, debug, processor, file,
5162 check_debug_option);
5163 }
5164
5165 static int si_compile_llvm(struct si_screen *sscreen,
5166 struct ac_shader_binary *binary,
5167 struct si_shader_config *conf,
5168 LLVMTargetMachineRef tm,
5169 LLVMModuleRef mod,
5170 struct pipe_debug_callback *debug,
5171 unsigned processor,
5172 const char *name)
5173 {
5174 int r = 0;
5175 unsigned count = p_atomic_inc_return(&sscreen->b.num_compilations);
5176
5177 if (r600_can_dump_shader(&sscreen->b, processor)) {
5178 fprintf(stderr, "radeonsi: Compiling shader %d\n", count);
5179
5180 if (!(sscreen->b.debug_flags & (DBG_NO_IR | DBG_PREOPT_IR))) {
5181 fprintf(stderr, "%s LLVM IR:\n\n", name);
5182 ac_dump_module(mod);
5183 fprintf(stderr, "\n");
5184 }
5185 }
5186
5187 if (sscreen->record_llvm_ir) {
5188 char *ir = LLVMPrintModuleToString(mod);
5189 binary->llvm_ir_string = strdup(ir);
5190 LLVMDisposeMessage(ir);
5191 }
5192
5193 if (!si_replace_shader(count, binary)) {
5194 r = si_llvm_compile(mod, binary, tm, debug);
5195 if (r)
5196 return r;
5197 }
5198
5199 si_shader_binary_read_config(binary, conf, 0);
5200
5201 /* Enable 64-bit and 16-bit denormals, because there is no performance
5202 * cost.
5203 *
5204 * If denormals are enabled, all floating-point output modifiers are
5205 * ignored.
5206 *
5207 * Don't enable denormals for 32-bit floats, because:
5208 * - Floating-point output modifiers would be ignored by the hw.
5209 * - Some opcodes don't support denormals, such as v_mad_f32. We would
5210 * have to stop using those.
5211 * - SI & CI would be very slow.
5212 */
5213 conf->float_mode |= V_00B028_FP_64_DENORMS;
5214
5215 FREE(binary->config);
5216 FREE(binary->global_symbol_offsets);
5217 binary->config = NULL;
5218 binary->global_symbol_offsets = NULL;
5219
5220 /* Some shaders can't have rodata because their binaries can be
5221 * concatenated.
5222 */
5223 if (binary->rodata_size &&
5224 (processor == PIPE_SHADER_VERTEX ||
5225 processor == PIPE_SHADER_TESS_CTRL ||
5226 processor == PIPE_SHADER_TESS_EVAL ||
5227 processor == PIPE_SHADER_FRAGMENT)) {
5228 fprintf(stderr, "radeonsi: The shader can't have rodata.");
5229 return -EINVAL;
5230 }
5231
5232 return r;
5233 }
5234
5235 static void si_llvm_build_ret(struct si_shader_context *ctx, LLVMValueRef ret)
5236 {
5237 if (LLVMGetTypeKind(LLVMTypeOf(ret)) == LLVMVoidTypeKind)
5238 LLVMBuildRetVoid(ctx->gallivm.builder);
5239 else
5240 LLVMBuildRet(ctx->gallivm.builder, ret);
5241 }
5242
5243 /* Generate code for the hardware VS shader stage to go with a geometry shader */
5244 struct si_shader *
5245 si_generate_gs_copy_shader(struct si_screen *sscreen,
5246 LLVMTargetMachineRef tm,
5247 struct si_shader_selector *gs_selector,
5248 struct pipe_debug_callback *debug)
5249 {
5250 struct si_shader_context ctx;
5251 struct si_shader *shader;
5252 struct gallivm_state *gallivm = &ctx.gallivm;
5253 LLVMBuilderRef builder;
5254 struct lp_build_tgsi_context *bld_base = &ctx.bld_base;
5255 struct lp_build_context *uint = &bld_base->uint_bld;
5256 struct si_shader_output_values *outputs;
5257 struct tgsi_shader_info *gsinfo = &gs_selector->info;
5258 int i, r;
5259
5260 outputs = MALLOC(gsinfo->num_outputs * sizeof(outputs[0]));
5261
5262 if (!outputs)
5263 return NULL;
5264
5265 shader = CALLOC_STRUCT(si_shader);
5266 if (!shader) {
5267 FREE(outputs);
5268 return NULL;
5269 }
5270
5271
5272 shader->selector = gs_selector;
5273 shader->is_gs_copy_shader = true;
5274
5275 si_init_shader_ctx(&ctx, sscreen, tm);
5276 ctx.shader = shader;
5277 ctx.type = PIPE_SHADER_VERTEX;
5278
5279 builder = gallivm->builder;
5280
5281 create_function(&ctx);
5282 preload_ring_buffers(&ctx);
5283
5284 LLVMValueRef voffset =
5285 lp_build_mul_imm(uint, ctx.abi.vertex_id, 4);
5286
5287 /* Fetch the vertex stream ID.*/
5288 LLVMValueRef stream_id;
5289
5290 if (gs_selector->so.num_outputs)
5291 stream_id = unpack_param(&ctx, ctx.param_streamout_config, 24, 2);
5292 else
5293 stream_id = ctx.i32_0;
5294
5295 /* Fill in output information. */
5296 for (i = 0; i < gsinfo->num_outputs; ++i) {
5297 outputs[i].semantic_name = gsinfo->output_semantic_name[i];
5298 outputs[i].semantic_index = gsinfo->output_semantic_index[i];
5299
5300 for (int chan = 0; chan < 4; chan++) {
5301 outputs[i].vertex_stream[chan] =
5302 (gsinfo->output_streams[i] >> (2 * chan)) & 3;
5303 }
5304 }
5305
5306 LLVMBasicBlockRef end_bb;
5307 LLVMValueRef switch_inst;
5308
5309 end_bb = LLVMAppendBasicBlockInContext(gallivm->context, ctx.main_fn, "end");
5310 switch_inst = LLVMBuildSwitch(builder, stream_id, end_bb, 4);
5311
5312 for (int stream = 0; stream < 4; stream++) {
5313 LLVMBasicBlockRef bb;
5314 unsigned offset;
5315
5316 if (!gsinfo->num_stream_output_components[stream])
5317 continue;
5318
5319 if (stream > 0 && !gs_selector->so.num_outputs)
5320 continue;
5321
5322 bb = LLVMInsertBasicBlockInContext(gallivm->context, end_bb, "out");
5323 LLVMAddCase(switch_inst, LLVMConstInt(ctx.i32, stream, 0), bb);
5324 LLVMPositionBuilderAtEnd(builder, bb);
5325
5326 /* Fetch vertex data from GSVS ring */
5327 offset = 0;
5328 for (i = 0; i < gsinfo->num_outputs; ++i) {
5329 for (unsigned chan = 0; chan < 4; chan++) {
5330 if (!(gsinfo->output_usagemask[i] & (1 << chan)) ||
5331 outputs[i].vertex_stream[chan] != stream) {
5332 outputs[i].values[chan] = ctx.bld_base.base.undef;
5333 continue;
5334 }
5335
5336 LLVMValueRef soffset = LLVMConstInt(ctx.i32,
5337 offset * gs_selector->gs_max_out_vertices * 16 * 4, 0);
5338 offset++;
5339
5340 outputs[i].values[chan] =
5341 ac_build_buffer_load(&ctx.ac,
5342 ctx.gsvs_ring[0], 1,
5343 ctx.i32_0, voffset,
5344 soffset, 0, 1, 1,
5345 true, false);
5346 }
5347 }
5348
5349 /* Streamout and exports. */
5350 if (gs_selector->so.num_outputs) {
5351 si_llvm_emit_streamout(&ctx, outputs,
5352 gsinfo->num_outputs,
5353 stream);
5354 }
5355
5356 if (stream == 0)
5357 si_llvm_export_vs(bld_base, outputs, gsinfo->num_outputs);
5358
5359 LLVMBuildBr(builder, end_bb);
5360 }
5361
5362 LLVMPositionBuilderAtEnd(builder, end_bb);
5363
5364 LLVMBuildRetVoid(gallivm->builder);
5365
5366 ctx.type = PIPE_SHADER_GEOMETRY; /* override for shader dumping */
5367 si_llvm_optimize_module(&ctx);
5368
5369 r = si_compile_llvm(sscreen, &ctx.shader->binary,
5370 &ctx.shader->config, ctx.tm,
5371 ctx.gallivm.module,
5372 debug, PIPE_SHADER_GEOMETRY,
5373 "GS Copy Shader");
5374 if (!r) {
5375 if (r600_can_dump_shader(&sscreen->b, PIPE_SHADER_GEOMETRY))
5376 fprintf(stderr, "GS Copy Shader:\n");
5377 si_shader_dump(sscreen, ctx.shader, debug,
5378 PIPE_SHADER_GEOMETRY, stderr, true);
5379 r = si_shader_binary_upload(sscreen, ctx.shader);
5380 }
5381
5382 si_llvm_dispose(&ctx);
5383
5384 FREE(outputs);
5385
5386 if (r != 0) {
5387 FREE(shader);
5388 shader = NULL;
5389 }
5390 return shader;
5391 }
5392
5393 static void si_dump_shader_key_vs(const struct si_shader_key *key,
5394 const struct si_vs_prolog_bits *prolog,
5395 const char *prefix, FILE *f)
5396 {
5397 fprintf(f, " %s.instance_divisor_is_one = %u\n",
5398 prefix, prolog->instance_divisor_is_one);
5399 fprintf(f, " %s.instance_divisor_is_fetched = %u\n",
5400 prefix, prolog->instance_divisor_is_fetched);
5401
5402 fprintf(f, " mono.vs.fix_fetch = {");
5403 for (int i = 0; i < SI_MAX_ATTRIBS; i++)
5404 fprintf(f, !i ? "%u" : ", %u", key->mono.vs_fix_fetch[i]);
5405 fprintf(f, "}\n");
5406 }
5407
5408 static void si_dump_shader_key(unsigned processor, const struct si_shader *shader,
5409 FILE *f)
5410 {
5411 const struct si_shader_key *key = &shader->key;
5412
5413 fprintf(f, "SHADER KEY\n");
5414
5415 switch (processor) {
5416 case PIPE_SHADER_VERTEX:
5417 si_dump_shader_key_vs(key, &key->part.vs.prolog,
5418 "part.vs.prolog", f);
5419 fprintf(f, " as_es = %u\n", key->as_es);
5420 fprintf(f, " as_ls = %u\n", key->as_ls);
5421 fprintf(f, " mono.u.vs_export_prim_id = %u\n",
5422 key->mono.u.vs_export_prim_id);
5423 break;
5424
5425 case PIPE_SHADER_TESS_CTRL:
5426 if (shader->selector->screen->b.chip_class >= GFX9) {
5427 si_dump_shader_key_vs(key, &key->part.tcs.ls_prolog,
5428 "part.tcs.ls_prolog", f);
5429 }
5430 fprintf(f, " part.tcs.epilog.prim_mode = %u\n", key->part.tcs.epilog.prim_mode);
5431 fprintf(f, " mono.u.ff_tcs_inputs_to_copy = 0x%"PRIx64"\n", key->mono.u.ff_tcs_inputs_to_copy);
5432 break;
5433
5434 case PIPE_SHADER_TESS_EVAL:
5435 fprintf(f, " as_es = %u\n", key->as_es);
5436 fprintf(f, " mono.u.vs_export_prim_id = %u\n",
5437 key->mono.u.vs_export_prim_id);
5438 break;
5439
5440 case PIPE_SHADER_GEOMETRY:
5441 if (shader->is_gs_copy_shader)
5442 break;
5443
5444 if (shader->selector->screen->b.chip_class >= GFX9 &&
5445 key->part.gs.es->type == PIPE_SHADER_VERTEX) {
5446 si_dump_shader_key_vs(key, &key->part.gs.vs_prolog,
5447 "part.gs.vs_prolog", f);
5448 }
5449 fprintf(f, " part.gs.prolog.tri_strip_adj_fix = %u\n", key->part.gs.prolog.tri_strip_adj_fix);
5450 break;
5451
5452 case PIPE_SHADER_COMPUTE:
5453 break;
5454
5455 case PIPE_SHADER_FRAGMENT:
5456 fprintf(f, " part.ps.prolog.color_two_side = %u\n", key->part.ps.prolog.color_two_side);
5457 fprintf(f, " part.ps.prolog.flatshade_colors = %u\n", key->part.ps.prolog.flatshade_colors);
5458 fprintf(f, " part.ps.prolog.poly_stipple = %u\n", key->part.ps.prolog.poly_stipple);
5459 fprintf(f, " part.ps.prolog.force_persp_sample_interp = %u\n", key->part.ps.prolog.force_persp_sample_interp);
5460 fprintf(f, " part.ps.prolog.force_linear_sample_interp = %u\n", key->part.ps.prolog.force_linear_sample_interp);
5461 fprintf(f, " part.ps.prolog.force_persp_center_interp = %u\n", key->part.ps.prolog.force_persp_center_interp);
5462 fprintf(f, " part.ps.prolog.force_linear_center_interp = %u\n", key->part.ps.prolog.force_linear_center_interp);
5463 fprintf(f, " part.ps.prolog.bc_optimize_for_persp = %u\n", key->part.ps.prolog.bc_optimize_for_persp);
5464 fprintf(f, " part.ps.prolog.bc_optimize_for_linear = %u\n", key->part.ps.prolog.bc_optimize_for_linear);
5465 fprintf(f, " part.ps.epilog.spi_shader_col_format = 0x%x\n", key->part.ps.epilog.spi_shader_col_format);
5466 fprintf(f, " part.ps.epilog.color_is_int8 = 0x%X\n", key->part.ps.epilog.color_is_int8);
5467 fprintf(f, " part.ps.epilog.color_is_int10 = 0x%X\n", key->part.ps.epilog.color_is_int10);
5468 fprintf(f, " part.ps.epilog.last_cbuf = %u\n", key->part.ps.epilog.last_cbuf);
5469 fprintf(f, " part.ps.epilog.alpha_func = %u\n", key->part.ps.epilog.alpha_func);
5470 fprintf(f, " part.ps.epilog.alpha_to_one = %u\n", key->part.ps.epilog.alpha_to_one);
5471 fprintf(f, " part.ps.epilog.poly_line_smoothing = %u\n", key->part.ps.epilog.poly_line_smoothing);
5472 fprintf(f, " part.ps.epilog.clamp_color = %u\n", key->part.ps.epilog.clamp_color);
5473 break;
5474
5475 default:
5476 assert(0);
5477 }
5478
5479 if ((processor == PIPE_SHADER_GEOMETRY ||
5480 processor == PIPE_SHADER_TESS_EVAL ||
5481 processor == PIPE_SHADER_VERTEX) &&
5482 !key->as_es && !key->as_ls) {
5483 fprintf(f, " opt.kill_outputs = 0x%"PRIx64"\n", key->opt.kill_outputs);
5484 fprintf(f, " opt.clip_disable = %u\n", key->opt.clip_disable);
5485 }
5486 }
5487
5488 static void si_init_shader_ctx(struct si_shader_context *ctx,
5489 struct si_screen *sscreen,
5490 LLVMTargetMachineRef tm)
5491 {
5492 struct lp_build_tgsi_context *bld_base;
5493
5494 si_llvm_context_init(ctx, sscreen, tm);
5495
5496 bld_base = &ctx->bld_base;
5497 bld_base->emit_fetch_funcs[TGSI_FILE_CONSTANT] = fetch_constant;
5498
5499 bld_base->op_actions[TGSI_OPCODE_INTERP_CENTROID] = interp_action;
5500 bld_base->op_actions[TGSI_OPCODE_INTERP_SAMPLE] = interp_action;
5501 bld_base->op_actions[TGSI_OPCODE_INTERP_OFFSET] = interp_action;
5502
5503 bld_base->op_actions[TGSI_OPCODE_MEMBAR].emit = membar_emit;
5504
5505 bld_base->op_actions[TGSI_OPCODE_CLOCK].emit = clock_emit;
5506
5507 bld_base->op_actions[TGSI_OPCODE_DDX].emit = si_llvm_emit_ddxy;
5508 bld_base->op_actions[TGSI_OPCODE_DDY].emit = si_llvm_emit_ddxy;
5509 bld_base->op_actions[TGSI_OPCODE_DDX_FINE].emit = si_llvm_emit_ddxy;
5510 bld_base->op_actions[TGSI_OPCODE_DDY_FINE].emit = si_llvm_emit_ddxy;
5511
5512 bld_base->op_actions[TGSI_OPCODE_VOTE_ALL].emit = vote_all_emit;
5513 bld_base->op_actions[TGSI_OPCODE_VOTE_ANY].emit = vote_any_emit;
5514 bld_base->op_actions[TGSI_OPCODE_VOTE_EQ].emit = vote_eq_emit;
5515 bld_base->op_actions[TGSI_OPCODE_BALLOT].emit = ballot_emit;
5516 bld_base->op_actions[TGSI_OPCODE_READ_FIRST].intr_name = "llvm.amdgcn.readfirstlane";
5517 bld_base->op_actions[TGSI_OPCODE_READ_FIRST].emit = read_lane_emit;
5518 bld_base->op_actions[TGSI_OPCODE_READ_INVOC].intr_name = "llvm.amdgcn.readlane";
5519 bld_base->op_actions[TGSI_OPCODE_READ_INVOC].fetch_args = read_invoc_fetch_args;
5520 bld_base->op_actions[TGSI_OPCODE_READ_INVOC].emit = read_lane_emit;
5521
5522 bld_base->op_actions[TGSI_OPCODE_EMIT].emit = si_llvm_emit_vertex;
5523 bld_base->op_actions[TGSI_OPCODE_ENDPRIM].emit = si_llvm_emit_primitive;
5524 bld_base->op_actions[TGSI_OPCODE_BARRIER].emit = si_llvm_emit_barrier;
5525 }
5526
5527 static void si_optimize_vs_outputs(struct si_shader_context *ctx)
5528 {
5529 struct si_shader *shader = ctx->shader;
5530 struct tgsi_shader_info *info = &shader->selector->info;
5531
5532 if ((ctx->type != PIPE_SHADER_VERTEX &&
5533 ctx->type != PIPE_SHADER_TESS_EVAL) ||
5534 shader->key.as_ls ||
5535 shader->key.as_es)
5536 return;
5537
5538 ac_optimize_vs_outputs(&ctx->ac,
5539 ctx->main_fn,
5540 shader->info.vs_output_param_offset,
5541 info->num_outputs,
5542 &shader->info.nr_param_exports);
5543 }
5544
5545 static void si_count_scratch_private_memory(struct si_shader_context *ctx)
5546 {
5547 ctx->shader->config.private_mem_vgprs = 0;
5548
5549 /* Process all LLVM instructions. */
5550 LLVMBasicBlockRef bb = LLVMGetFirstBasicBlock(ctx->main_fn);
5551 while (bb) {
5552 LLVMValueRef next = LLVMGetFirstInstruction(bb);
5553
5554 while (next) {
5555 LLVMValueRef inst = next;
5556 next = LLVMGetNextInstruction(next);
5557
5558 if (LLVMGetInstructionOpcode(inst) != LLVMAlloca)
5559 continue;
5560
5561 LLVMTypeRef type = LLVMGetElementType(LLVMTypeOf(inst));
5562 /* No idea why LLVM aligns allocas to 4 elements. */
5563 unsigned alignment = LLVMGetAlignment(inst);
5564 unsigned dw_size = align(llvm_get_type_size(type) / 4, alignment);
5565 ctx->shader->config.private_mem_vgprs += dw_size;
5566 }
5567 bb = LLVMGetNextBasicBlock(bb);
5568 }
5569 }
5570
5571 static void si_init_exec_full_mask(struct si_shader_context *ctx)
5572 {
5573 LLVMValueRef full_mask = LLVMConstInt(ctx->i64, ~0ull, 0);
5574 lp_build_intrinsic(ctx->gallivm.builder,
5575 "llvm.amdgcn.init.exec", ctx->voidt,
5576 &full_mask, 1, LP_FUNC_ATTR_CONVERGENT);
5577 }
5578
5579 static void si_init_exec_from_input(struct si_shader_context *ctx,
5580 unsigned param, unsigned bitoffset)
5581 {
5582 LLVMValueRef args[] = {
5583 LLVMGetParam(ctx->main_fn, param),
5584 LLVMConstInt(ctx->i32, bitoffset, 0),
5585 };
5586 lp_build_intrinsic(ctx->gallivm.builder,
5587 "llvm.amdgcn.init.exec.from.input",
5588 ctx->voidt, args, 2, LP_FUNC_ATTR_CONVERGENT);
5589 }
5590
5591 static bool si_compile_tgsi_main(struct si_shader_context *ctx,
5592 bool is_monolithic)
5593 {
5594 struct si_shader *shader = ctx->shader;
5595 struct si_shader_selector *sel = shader->selector;
5596 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
5597
5598 // TODO clean all this up!
5599 switch (ctx->type) {
5600 case PIPE_SHADER_VERTEX:
5601 ctx->load_input = declare_input_vs;
5602 if (shader->key.as_ls)
5603 bld_base->emit_epilogue = si_llvm_emit_ls_epilogue;
5604 else if (shader->key.as_es)
5605 bld_base->emit_epilogue = si_llvm_emit_es_epilogue;
5606 else {
5607 ctx->abi.emit_outputs = si_llvm_emit_vs_epilogue;
5608 bld_base->emit_epilogue = si_tgsi_emit_epilogue;
5609 }
5610 break;
5611 case PIPE_SHADER_TESS_CTRL:
5612 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_tcs;
5613 bld_base->emit_fetch_funcs[TGSI_FILE_OUTPUT] = fetch_output_tcs;
5614 bld_base->emit_store = store_output_tcs;
5615 bld_base->emit_epilogue = si_llvm_emit_tcs_epilogue;
5616 break;
5617 case PIPE_SHADER_TESS_EVAL:
5618 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_tes;
5619 if (shader->key.as_es)
5620 bld_base->emit_epilogue = si_llvm_emit_es_epilogue;
5621 else {
5622 ctx->abi.emit_outputs = si_llvm_emit_vs_epilogue;
5623 bld_base->emit_epilogue = si_tgsi_emit_epilogue;
5624 }
5625 break;
5626 case PIPE_SHADER_GEOMETRY:
5627 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_gs;
5628 bld_base->emit_epilogue = si_llvm_emit_gs_epilogue;
5629 break;
5630 case PIPE_SHADER_FRAGMENT:
5631 ctx->load_input = declare_input_fs;
5632 bld_base->emit_epilogue = si_llvm_return_fs_outputs;
5633 break;
5634 case PIPE_SHADER_COMPUTE:
5635 ctx->declare_memory_region = declare_compute_memory;
5636 break;
5637 default:
5638 assert(!"Unsupported shader type");
5639 return false;
5640 }
5641
5642 ctx->abi.load_ubo = load_ubo;
5643
5644 create_function(ctx);
5645 preload_ring_buffers(ctx);
5646
5647 /* For GFX9 merged shaders:
5648 * - Set EXEC for the first shader. If the prolog is present, set
5649 * EXEC there instead.
5650 * - Add a barrier before the second shader.
5651 * - In the second shader, reset EXEC to ~0 and wrap the main part in
5652 * an if-statement. This is required for correctness in geometry
5653 * shaders, to ensure that empty GS waves do not send GS_EMIT and
5654 * GS_CUT messages.
5655 *
5656 * For monolithic merged shaders, the first shader is wrapped in an
5657 * if-block together with its prolog in si_build_wrapper_function.
5658 */
5659 if (ctx->screen->b.chip_class >= GFX9) {
5660 if (!is_monolithic &&
5661 sel->info.num_instructions > 1 && /* not empty shader */
5662 (shader->key.as_es || shader->key.as_ls) &&
5663 (ctx->type == PIPE_SHADER_TESS_EVAL ||
5664 (ctx->type == PIPE_SHADER_VERTEX &&
5665 !sel->vs_needs_prolog))) {
5666 si_init_exec_from_input(ctx,
5667 ctx->param_merged_wave_info, 0);
5668 } else if (ctx->type == PIPE_SHADER_TESS_CTRL ||
5669 ctx->type == PIPE_SHADER_GEOMETRY) {
5670 if (!is_monolithic)
5671 si_init_exec_full_mask(ctx);
5672
5673 /* The barrier must execute for all shaders in a
5674 * threadgroup.
5675 */
5676 si_llvm_emit_barrier(NULL, bld_base, NULL);
5677
5678 LLVMValueRef num_threads = unpack_param(ctx, ctx->param_merged_wave_info, 8, 8);
5679 LLVMValueRef ena =
5680 LLVMBuildICmp(ctx->ac.builder, LLVMIntULT,
5681 ac_get_thread_id(&ctx->ac), num_threads, "");
5682 lp_build_if(&ctx->merged_wrap_if_state, &ctx->gallivm, ena);
5683 }
5684 }
5685
5686 if (ctx->type == PIPE_SHADER_GEOMETRY) {
5687 int i;
5688 for (i = 0; i < 4; i++) {
5689 ctx->gs_next_vertex[i] =
5690 lp_build_alloca(&ctx->gallivm,
5691 ctx->i32, "");
5692 }
5693 }
5694
5695 if (ctx->type == PIPE_SHADER_FRAGMENT && sel->info.uses_kill &&
5696 ctx->screen->b.debug_flags & DBG_FS_CORRECT_DERIVS_AFTER_KILL) {
5697 /* This is initialized to 0.0 = not kill. */
5698 ctx->postponed_kill = lp_build_alloca(&ctx->gallivm, ctx->f32, "");
5699 }
5700
5701 if (sel->tokens) {
5702 if (!lp_build_tgsi_llvm(bld_base, sel->tokens)) {
5703 fprintf(stderr, "Failed to translate shader from TGSI to LLVM\n");
5704 return false;
5705 }
5706 } else {
5707 if (!si_nir_build_llvm(ctx, sel->nir)) {
5708 fprintf(stderr, "Failed to translate shader from NIR to LLVM\n");
5709 return false;
5710 }
5711 }
5712
5713 si_llvm_build_ret(ctx, ctx->return_value);
5714 return true;
5715 }
5716
5717 /**
5718 * Compute the VS prolog key, which contains all the information needed to
5719 * build the VS prolog function, and set shader->info bits where needed.
5720 *
5721 * \param info Shader info of the vertex shader.
5722 * \param num_input_sgprs Number of input SGPRs for the vertex shader.
5723 * \param prolog_key Key of the VS prolog
5724 * \param shader_out The vertex shader, or the next shader if merging LS+HS or ES+GS.
5725 * \param key Output shader part key.
5726 */
5727 static void si_get_vs_prolog_key(const struct tgsi_shader_info *info,
5728 unsigned num_input_sgprs,
5729 const struct si_vs_prolog_bits *prolog_key,
5730 struct si_shader *shader_out,
5731 union si_shader_part_key *key)
5732 {
5733 memset(key, 0, sizeof(*key));
5734 key->vs_prolog.states = *prolog_key;
5735 key->vs_prolog.num_input_sgprs = num_input_sgprs;
5736 key->vs_prolog.last_input = MAX2(1, info->num_inputs) - 1;
5737 key->vs_prolog.as_ls = shader_out->key.as_ls;
5738
5739 if (shader_out->selector->type == PIPE_SHADER_TESS_CTRL) {
5740 key->vs_prolog.as_ls = 1;
5741 key->vs_prolog.num_merged_next_stage_vgprs = 2;
5742 } else if (shader_out->selector->type == PIPE_SHADER_GEOMETRY) {
5743 key->vs_prolog.num_merged_next_stage_vgprs = 5;
5744 }
5745
5746 /* Enable loading the InstanceID VGPR. */
5747 uint16_t input_mask = u_bit_consecutive(0, info->num_inputs);
5748
5749 if ((key->vs_prolog.states.instance_divisor_is_one |
5750 key->vs_prolog.states.instance_divisor_is_fetched) & input_mask)
5751 shader_out->info.uses_instanceid = true;
5752 }
5753
5754 /**
5755 * Compute the PS prolog key, which contains all the information needed to
5756 * build the PS prolog function, and set related bits in shader->config.
5757 */
5758 static void si_get_ps_prolog_key(struct si_shader *shader,
5759 union si_shader_part_key *key,
5760 bool separate_prolog)
5761 {
5762 struct tgsi_shader_info *info = &shader->selector->info;
5763
5764 memset(key, 0, sizeof(*key));
5765 key->ps_prolog.states = shader->key.part.ps.prolog;
5766 key->ps_prolog.colors_read = info->colors_read;
5767 key->ps_prolog.num_input_sgprs = shader->info.num_input_sgprs;
5768 key->ps_prolog.num_input_vgprs = shader->info.num_input_vgprs;
5769 key->ps_prolog.wqm = info->uses_derivatives &&
5770 (key->ps_prolog.colors_read ||
5771 key->ps_prolog.states.force_persp_sample_interp ||
5772 key->ps_prolog.states.force_linear_sample_interp ||
5773 key->ps_prolog.states.force_persp_center_interp ||
5774 key->ps_prolog.states.force_linear_center_interp ||
5775 key->ps_prolog.states.bc_optimize_for_persp ||
5776 key->ps_prolog.states.bc_optimize_for_linear);
5777
5778 if (info->colors_read) {
5779 unsigned *color = shader->selector->color_attr_index;
5780
5781 if (shader->key.part.ps.prolog.color_two_side) {
5782 /* BCOLORs are stored after the last input. */
5783 key->ps_prolog.num_interp_inputs = info->num_inputs;
5784 key->ps_prolog.face_vgpr_index = shader->info.face_vgpr_index;
5785 shader->config.spi_ps_input_ena |= S_0286CC_FRONT_FACE_ENA(1);
5786 }
5787
5788 for (unsigned i = 0; i < 2; i++) {
5789 unsigned interp = info->input_interpolate[color[i]];
5790 unsigned location = info->input_interpolate_loc[color[i]];
5791
5792 if (!(info->colors_read & (0xf << i*4)))
5793 continue;
5794
5795 key->ps_prolog.color_attr_index[i] = color[i];
5796
5797 if (shader->key.part.ps.prolog.flatshade_colors &&
5798 interp == TGSI_INTERPOLATE_COLOR)
5799 interp = TGSI_INTERPOLATE_CONSTANT;
5800
5801 switch (interp) {
5802 case TGSI_INTERPOLATE_CONSTANT:
5803 key->ps_prolog.color_interp_vgpr_index[i] = -1;
5804 break;
5805 case TGSI_INTERPOLATE_PERSPECTIVE:
5806 case TGSI_INTERPOLATE_COLOR:
5807 /* Force the interpolation location for colors here. */
5808 if (shader->key.part.ps.prolog.force_persp_sample_interp)
5809 location = TGSI_INTERPOLATE_LOC_SAMPLE;
5810 if (shader->key.part.ps.prolog.force_persp_center_interp)
5811 location = TGSI_INTERPOLATE_LOC_CENTER;
5812
5813 switch (location) {
5814 case TGSI_INTERPOLATE_LOC_SAMPLE:
5815 key->ps_prolog.color_interp_vgpr_index[i] = 0;
5816 shader->config.spi_ps_input_ena |=
5817 S_0286CC_PERSP_SAMPLE_ENA(1);
5818 break;
5819 case TGSI_INTERPOLATE_LOC_CENTER:
5820 key->ps_prolog.color_interp_vgpr_index[i] = 2;
5821 shader->config.spi_ps_input_ena |=
5822 S_0286CC_PERSP_CENTER_ENA(1);
5823 break;
5824 case TGSI_INTERPOLATE_LOC_CENTROID:
5825 key->ps_prolog.color_interp_vgpr_index[i] = 4;
5826 shader->config.spi_ps_input_ena |=
5827 S_0286CC_PERSP_CENTROID_ENA(1);
5828 break;
5829 default:
5830 assert(0);
5831 }
5832 break;
5833 case TGSI_INTERPOLATE_LINEAR:
5834 /* Force the interpolation location for colors here. */
5835 if (shader->key.part.ps.prolog.force_linear_sample_interp)
5836 location = TGSI_INTERPOLATE_LOC_SAMPLE;
5837 if (shader->key.part.ps.prolog.force_linear_center_interp)
5838 location = TGSI_INTERPOLATE_LOC_CENTER;
5839
5840 /* The VGPR assignment for non-monolithic shaders
5841 * works because InitialPSInputAddr is set on the
5842 * main shader and PERSP_PULL_MODEL is never used.
5843 */
5844 switch (location) {
5845 case TGSI_INTERPOLATE_LOC_SAMPLE:
5846 key->ps_prolog.color_interp_vgpr_index[i] =
5847 separate_prolog ? 6 : 9;
5848 shader->config.spi_ps_input_ena |=
5849 S_0286CC_LINEAR_SAMPLE_ENA(1);
5850 break;
5851 case TGSI_INTERPOLATE_LOC_CENTER:
5852 key->ps_prolog.color_interp_vgpr_index[i] =
5853 separate_prolog ? 8 : 11;
5854 shader->config.spi_ps_input_ena |=
5855 S_0286CC_LINEAR_CENTER_ENA(1);
5856 break;
5857 case TGSI_INTERPOLATE_LOC_CENTROID:
5858 key->ps_prolog.color_interp_vgpr_index[i] =
5859 separate_prolog ? 10 : 13;
5860 shader->config.spi_ps_input_ena |=
5861 S_0286CC_LINEAR_CENTROID_ENA(1);
5862 break;
5863 default:
5864 assert(0);
5865 }
5866 break;
5867 default:
5868 assert(0);
5869 }
5870 }
5871 }
5872 }
5873
5874 /**
5875 * Check whether a PS prolog is required based on the key.
5876 */
5877 static bool si_need_ps_prolog(const union si_shader_part_key *key)
5878 {
5879 return key->ps_prolog.colors_read ||
5880 key->ps_prolog.states.force_persp_sample_interp ||
5881 key->ps_prolog.states.force_linear_sample_interp ||
5882 key->ps_prolog.states.force_persp_center_interp ||
5883 key->ps_prolog.states.force_linear_center_interp ||
5884 key->ps_prolog.states.bc_optimize_for_persp ||
5885 key->ps_prolog.states.bc_optimize_for_linear ||
5886 key->ps_prolog.states.poly_stipple;
5887 }
5888
5889 /**
5890 * Compute the PS epilog key, which contains all the information needed to
5891 * build the PS epilog function.
5892 */
5893 static void si_get_ps_epilog_key(struct si_shader *shader,
5894 union si_shader_part_key *key)
5895 {
5896 struct tgsi_shader_info *info = &shader->selector->info;
5897 memset(key, 0, sizeof(*key));
5898 key->ps_epilog.colors_written = info->colors_written;
5899 key->ps_epilog.writes_z = info->writes_z;
5900 key->ps_epilog.writes_stencil = info->writes_stencil;
5901 key->ps_epilog.writes_samplemask = info->writes_samplemask;
5902 key->ps_epilog.states = shader->key.part.ps.epilog;
5903 }
5904
5905 /**
5906 * Build the GS prolog function. Rotate the input vertices for triangle strips
5907 * with adjacency.
5908 */
5909 static void si_build_gs_prolog_function(struct si_shader_context *ctx,
5910 union si_shader_part_key *key)
5911 {
5912 unsigned num_sgprs, num_vgprs;
5913 struct gallivm_state *gallivm = &ctx->gallivm;
5914 struct si_function_info fninfo;
5915 LLVMBuilderRef builder = gallivm->builder;
5916 LLVMTypeRef returns[48];
5917 LLVMValueRef func, ret;
5918
5919 si_init_function_info(&fninfo);
5920
5921 if (ctx->screen->b.chip_class >= GFX9) {
5922 num_sgprs = 8 + GFX9_GS_NUM_USER_SGPR;
5923 num_vgprs = 5; /* ES inputs are not needed by GS */
5924 } else {
5925 num_sgprs = GFX6_GS_NUM_USER_SGPR + 2;
5926 num_vgprs = 8;
5927 }
5928
5929 for (unsigned i = 0; i < num_sgprs; ++i) {
5930 add_arg(&fninfo, ARG_SGPR, ctx->i32);
5931 returns[i] = ctx->i32;
5932 }
5933
5934 for (unsigned i = 0; i < num_vgprs; ++i) {
5935 add_arg(&fninfo, ARG_VGPR, ctx->i32);
5936 returns[num_sgprs + i] = ctx->f32;
5937 }
5938
5939 /* Create the function. */
5940 si_create_function(ctx, "gs_prolog", returns, num_sgprs + num_vgprs,
5941 &fninfo, 0);
5942 func = ctx->main_fn;
5943
5944 /* Set the full EXEC mask for the prolog, because we are only fiddling
5945 * with registers here. The main shader part will set the correct EXEC
5946 * mask.
5947 */
5948 if (ctx->screen->b.chip_class >= GFX9 && !key->gs_prolog.is_monolithic)
5949 si_init_exec_full_mask(ctx);
5950
5951 /* Copy inputs to outputs. This should be no-op, as the registers match,
5952 * but it will prevent the compiler from overwriting them unintentionally.
5953 */
5954 ret = ctx->return_value;
5955 for (unsigned i = 0; i < num_sgprs; i++) {
5956 LLVMValueRef p = LLVMGetParam(func, i);
5957 ret = LLVMBuildInsertValue(builder, ret, p, i, "");
5958 }
5959 for (unsigned i = 0; i < num_vgprs; i++) {
5960 LLVMValueRef p = LLVMGetParam(func, num_sgprs + i);
5961 p = LLVMBuildBitCast(builder, p, ctx->f32, "");
5962 ret = LLVMBuildInsertValue(builder, ret, p, num_sgprs + i, "");
5963 }
5964
5965 if (key->gs_prolog.states.tri_strip_adj_fix) {
5966 /* Remap the input vertices for every other primitive. */
5967 const unsigned gfx6_vtx_params[6] = {
5968 num_sgprs,
5969 num_sgprs + 1,
5970 num_sgprs + 3,
5971 num_sgprs + 4,
5972 num_sgprs + 5,
5973 num_sgprs + 6
5974 };
5975 const unsigned gfx9_vtx_params[3] = {
5976 num_sgprs,
5977 num_sgprs + 1,
5978 num_sgprs + 4,
5979 };
5980 LLVMValueRef vtx_in[6], vtx_out[6];
5981 LLVMValueRef prim_id, rotate;
5982
5983 if (ctx->screen->b.chip_class >= GFX9) {
5984 for (unsigned i = 0; i < 3; i++) {
5985 vtx_in[i*2] = unpack_param(ctx, gfx9_vtx_params[i], 0, 16);
5986 vtx_in[i*2+1] = unpack_param(ctx, gfx9_vtx_params[i], 16, 16);
5987 }
5988 } else {
5989 for (unsigned i = 0; i < 6; i++)
5990 vtx_in[i] = LLVMGetParam(func, gfx6_vtx_params[i]);
5991 }
5992
5993 prim_id = LLVMGetParam(func, num_sgprs + 2);
5994 rotate = LLVMBuildTrunc(builder, prim_id, ctx->i1, "");
5995
5996 for (unsigned i = 0; i < 6; ++i) {
5997 LLVMValueRef base, rotated;
5998 base = vtx_in[i];
5999 rotated = vtx_in[(i + 4) % 6];
6000 vtx_out[i] = LLVMBuildSelect(builder, rotate, rotated, base, "");
6001 }
6002
6003 if (ctx->screen->b.chip_class >= GFX9) {
6004 for (unsigned i = 0; i < 3; i++) {
6005 LLVMValueRef hi, out;
6006
6007 hi = LLVMBuildShl(builder, vtx_out[i*2+1],
6008 LLVMConstInt(ctx->i32, 16, 0), "");
6009 out = LLVMBuildOr(builder, vtx_out[i*2], hi, "");
6010 out = LLVMBuildBitCast(builder, out, ctx->f32, "");
6011 ret = LLVMBuildInsertValue(builder, ret, out,
6012 gfx9_vtx_params[i], "");
6013 }
6014 } else {
6015 for (unsigned i = 0; i < 6; i++) {
6016 LLVMValueRef out;
6017
6018 out = LLVMBuildBitCast(builder, vtx_out[i], ctx->f32, "");
6019 ret = LLVMBuildInsertValue(builder, ret, out,
6020 gfx6_vtx_params[i], "");
6021 }
6022 }
6023 }
6024
6025 LLVMBuildRet(builder, ret);
6026 }
6027
6028 /**
6029 * Given a list of shader part functions, build a wrapper function that
6030 * runs them in sequence to form a monolithic shader.
6031 */
6032 static void si_build_wrapper_function(struct si_shader_context *ctx,
6033 LLVMValueRef *parts,
6034 unsigned num_parts,
6035 unsigned main_part,
6036 unsigned next_shader_first_part)
6037 {
6038 struct gallivm_state *gallivm = &ctx->gallivm;
6039 LLVMBuilderRef builder = ctx->gallivm.builder;
6040 /* PS epilog has one arg per color component; gfx9 merged shader
6041 * prologs need to forward 32 user SGPRs.
6042 */
6043 struct si_function_info fninfo;
6044 LLVMValueRef initial[64], out[64];
6045 LLVMTypeRef function_type;
6046 unsigned num_first_params;
6047 unsigned num_out, initial_num_out;
6048 MAYBE_UNUSED unsigned num_out_sgpr; /* used in debug checks */
6049 MAYBE_UNUSED unsigned initial_num_out_sgpr; /* used in debug checks */
6050 unsigned num_sgprs, num_vgprs;
6051 unsigned gprs;
6052 struct lp_build_if_state if_state;
6053
6054 si_init_function_info(&fninfo);
6055
6056 for (unsigned i = 0; i < num_parts; ++i) {
6057 lp_add_function_attr(parts[i], -1, LP_FUNC_ATTR_ALWAYSINLINE);
6058 LLVMSetLinkage(parts[i], LLVMPrivateLinkage);
6059 }
6060
6061 /* The parameters of the wrapper function correspond to those of the
6062 * first part in terms of SGPRs and VGPRs, but we use the types of the
6063 * main part to get the right types. This is relevant for the
6064 * dereferenceable attribute on descriptor table pointers.
6065 */
6066 num_sgprs = 0;
6067 num_vgprs = 0;
6068
6069 function_type = LLVMGetElementType(LLVMTypeOf(parts[0]));
6070 num_first_params = LLVMCountParamTypes(function_type);
6071
6072 for (unsigned i = 0; i < num_first_params; ++i) {
6073 LLVMValueRef param = LLVMGetParam(parts[0], i);
6074
6075 if (ac_is_sgpr_param(param)) {
6076 assert(num_vgprs == 0);
6077 num_sgprs += llvm_get_type_size(LLVMTypeOf(param)) / 4;
6078 } else {
6079 num_vgprs += llvm_get_type_size(LLVMTypeOf(param)) / 4;
6080 }
6081 }
6082
6083 gprs = 0;
6084 while (gprs < num_sgprs + num_vgprs) {
6085 LLVMValueRef param = LLVMGetParam(parts[main_part], fninfo.num_params);
6086 LLVMTypeRef type = LLVMTypeOf(param);
6087 unsigned size = llvm_get_type_size(type) / 4;
6088
6089 add_arg(&fninfo, gprs < num_sgprs ? ARG_SGPR : ARG_VGPR, type);
6090
6091 assert(ac_is_sgpr_param(param) == (gprs < num_sgprs));
6092 assert(gprs + size <= num_sgprs + num_vgprs &&
6093 (gprs >= num_sgprs || gprs + size <= num_sgprs));
6094
6095 gprs += size;
6096 }
6097
6098 si_create_function(ctx, "wrapper", NULL, 0, &fninfo,
6099 si_get_max_workgroup_size(ctx->shader));
6100
6101 if (is_merged_shader(ctx->shader))
6102 si_init_exec_full_mask(ctx);
6103
6104 /* Record the arguments of the function as if they were an output of
6105 * a previous part.
6106 */
6107 num_out = 0;
6108 num_out_sgpr = 0;
6109
6110 for (unsigned i = 0; i < fninfo.num_params; ++i) {
6111 LLVMValueRef param = LLVMGetParam(ctx->main_fn, i);
6112 LLVMTypeRef param_type = LLVMTypeOf(param);
6113 LLVMTypeRef out_type = i < fninfo.num_sgpr_params ? ctx->i32 : ctx->f32;
6114 unsigned size = llvm_get_type_size(param_type) / 4;
6115
6116 if (size == 1) {
6117 if (param_type != out_type)
6118 param = LLVMBuildBitCast(builder, param, out_type, "");
6119 out[num_out++] = param;
6120 } else {
6121 LLVMTypeRef vector_type = LLVMVectorType(out_type, size);
6122
6123 if (LLVMGetTypeKind(param_type) == LLVMPointerTypeKind) {
6124 param = LLVMBuildPtrToInt(builder, param, ctx->i64, "");
6125 param_type = ctx->i64;
6126 }
6127
6128 if (param_type != vector_type)
6129 param = LLVMBuildBitCast(builder, param, vector_type, "");
6130
6131 for (unsigned j = 0; j < size; ++j)
6132 out[num_out++] = LLVMBuildExtractElement(
6133 builder, param, LLVMConstInt(ctx->i32, j, 0), "");
6134 }
6135
6136 if (i < fninfo.num_sgpr_params)
6137 num_out_sgpr = num_out;
6138 }
6139
6140 memcpy(initial, out, sizeof(out));
6141 initial_num_out = num_out;
6142 initial_num_out_sgpr = num_out_sgpr;
6143
6144 /* Now chain the parts. */
6145 for (unsigned part = 0; part < num_parts; ++part) {
6146 LLVMValueRef in[48];
6147 LLVMValueRef ret;
6148 LLVMTypeRef ret_type;
6149 unsigned out_idx = 0;
6150 unsigned num_params = LLVMCountParams(parts[part]);
6151
6152 /* Merged shaders are executed conditionally depending
6153 * on the number of enabled threads passed in the input SGPRs. */
6154 if (is_merged_shader(ctx->shader) && part == 0) {
6155 LLVMValueRef ena, count = initial[3];
6156
6157 count = LLVMBuildAnd(builder, count,
6158 LLVMConstInt(ctx->i32, 0x7f, 0), "");
6159 ena = LLVMBuildICmp(builder, LLVMIntULT,
6160 ac_get_thread_id(&ctx->ac), count, "");
6161 lp_build_if(&if_state, &ctx->gallivm, ena);
6162 }
6163
6164 /* Derive arguments for the next part from outputs of the
6165 * previous one.
6166 */
6167 for (unsigned param_idx = 0; param_idx < num_params; ++param_idx) {
6168 LLVMValueRef param;
6169 LLVMTypeRef param_type;
6170 bool is_sgpr;
6171 unsigned param_size;
6172 LLVMValueRef arg = NULL;
6173
6174 param = LLVMGetParam(parts[part], param_idx);
6175 param_type = LLVMTypeOf(param);
6176 param_size = llvm_get_type_size(param_type) / 4;
6177 is_sgpr = ac_is_sgpr_param(param);
6178
6179 if (is_sgpr) {
6180 #if HAVE_LLVM < 0x0400
6181 LLVMRemoveAttribute(param, LLVMByValAttribute);
6182 #else
6183 unsigned kind_id = LLVMGetEnumAttributeKindForName("byval", 5);
6184 LLVMRemoveEnumAttributeAtIndex(parts[part], param_idx + 1, kind_id);
6185 #endif
6186 lp_add_function_attr(parts[part], param_idx + 1, LP_FUNC_ATTR_INREG);
6187 }
6188
6189 assert(out_idx + param_size <= (is_sgpr ? num_out_sgpr : num_out));
6190 assert(is_sgpr || out_idx >= num_out_sgpr);
6191
6192 if (param_size == 1)
6193 arg = out[out_idx];
6194 else
6195 arg = lp_build_gather_values(gallivm, &out[out_idx], param_size);
6196
6197 if (LLVMTypeOf(arg) != param_type) {
6198 if (LLVMGetTypeKind(param_type) == LLVMPointerTypeKind) {
6199 arg = LLVMBuildBitCast(builder, arg, ctx->i64, "");
6200 arg = LLVMBuildIntToPtr(builder, arg, param_type, "");
6201 } else {
6202 arg = LLVMBuildBitCast(builder, arg, param_type, "");
6203 }
6204 }
6205
6206 in[param_idx] = arg;
6207 out_idx += param_size;
6208 }
6209
6210 ret = LLVMBuildCall(builder, parts[part], in, num_params, "");
6211
6212 if (is_merged_shader(ctx->shader) &&
6213 part + 1 == next_shader_first_part) {
6214 lp_build_endif(&if_state);
6215
6216 /* The second half of the merged shader should use
6217 * the inputs from the toplevel (wrapper) function,
6218 * not the return value from the last call.
6219 *
6220 * That's because the last call was executed condi-
6221 * tionally, so we can't consume it in the main
6222 * block.
6223 */
6224 memcpy(out, initial, sizeof(initial));
6225 num_out = initial_num_out;
6226 num_out_sgpr = initial_num_out_sgpr;
6227 continue;
6228 }
6229
6230 /* Extract the returned GPRs. */
6231 ret_type = LLVMTypeOf(ret);
6232 num_out = 0;
6233 num_out_sgpr = 0;
6234
6235 if (LLVMGetTypeKind(ret_type) != LLVMVoidTypeKind) {
6236 assert(LLVMGetTypeKind(ret_type) == LLVMStructTypeKind);
6237
6238 unsigned ret_size = LLVMCountStructElementTypes(ret_type);
6239
6240 for (unsigned i = 0; i < ret_size; ++i) {
6241 LLVMValueRef val =
6242 LLVMBuildExtractValue(builder, ret, i, "");
6243
6244 assert(num_out < ARRAY_SIZE(out));
6245 out[num_out++] = val;
6246
6247 if (LLVMTypeOf(val) == ctx->i32) {
6248 assert(num_out_sgpr + 1 == num_out);
6249 num_out_sgpr = num_out;
6250 }
6251 }
6252 }
6253 }
6254
6255 LLVMBuildRetVoid(builder);
6256 }
6257
6258 int si_compile_tgsi_shader(struct si_screen *sscreen,
6259 LLVMTargetMachineRef tm,
6260 struct si_shader *shader,
6261 bool is_monolithic,
6262 struct pipe_debug_callback *debug)
6263 {
6264 struct si_shader_selector *sel = shader->selector;
6265 struct si_shader_context ctx;
6266 int r = -1;
6267
6268 /* Dump TGSI code before doing TGSI->LLVM conversion in case the
6269 * conversion fails. */
6270 if (r600_can_dump_shader(&sscreen->b, sel->info.processor) &&
6271 !(sscreen->b.debug_flags & DBG_NO_TGSI)) {
6272 if (sel->tokens)
6273 tgsi_dump(sel->tokens, 0);
6274 else
6275 nir_print_shader(sel->nir, stderr);
6276 si_dump_streamout(&sel->so);
6277 }
6278
6279 si_init_shader_ctx(&ctx, sscreen, tm);
6280 si_llvm_context_set_tgsi(&ctx, shader);
6281 ctx.separate_prolog = !is_monolithic;
6282
6283 memset(shader->info.vs_output_param_offset, AC_EXP_PARAM_UNDEFINED,
6284 sizeof(shader->info.vs_output_param_offset));
6285
6286 shader->info.uses_instanceid = sel->info.uses_instanceid;
6287
6288 ctx.load_system_value = declare_system_value;
6289
6290 if (!si_compile_tgsi_main(&ctx, is_monolithic)) {
6291 si_llvm_dispose(&ctx);
6292 return -1;
6293 }
6294
6295 if (is_monolithic && ctx.type == PIPE_SHADER_VERTEX) {
6296 LLVMValueRef parts[2];
6297 bool need_prolog = sel->vs_needs_prolog;
6298
6299 parts[1] = ctx.main_fn;
6300
6301 if (need_prolog) {
6302 union si_shader_part_key prolog_key;
6303 si_get_vs_prolog_key(&sel->info,
6304 shader->info.num_input_sgprs,
6305 &shader->key.part.vs.prolog,
6306 shader, &prolog_key);
6307 si_build_vs_prolog_function(&ctx, &prolog_key);
6308 parts[0] = ctx.main_fn;
6309 }
6310
6311 si_build_wrapper_function(&ctx, parts + !need_prolog,
6312 1 + need_prolog, need_prolog, 0);
6313 } else if (is_monolithic && ctx.type == PIPE_SHADER_TESS_CTRL) {
6314 if (sscreen->b.chip_class >= GFX9) {
6315 struct si_shader_selector *ls = shader->key.part.tcs.ls;
6316 LLVMValueRef parts[4];
6317
6318 /* TCS main part */
6319 parts[2] = ctx.main_fn;
6320
6321 /* TCS epilog */
6322 union si_shader_part_key tcs_epilog_key;
6323 memset(&tcs_epilog_key, 0, sizeof(tcs_epilog_key));
6324 tcs_epilog_key.tcs_epilog.states = shader->key.part.tcs.epilog;
6325 si_build_tcs_epilog_function(&ctx, &tcs_epilog_key);
6326 parts[3] = ctx.main_fn;
6327
6328 /* VS prolog */
6329 if (ls->vs_needs_prolog) {
6330 union si_shader_part_key vs_prolog_key;
6331 si_get_vs_prolog_key(&ls->info,
6332 shader->info.num_input_sgprs,
6333 &shader->key.part.tcs.ls_prolog,
6334 shader, &vs_prolog_key);
6335 vs_prolog_key.vs_prolog.is_monolithic = true;
6336 si_build_vs_prolog_function(&ctx, &vs_prolog_key);
6337 parts[0] = ctx.main_fn;
6338 }
6339
6340 /* VS as LS main part */
6341 struct si_shader shader_ls = {};
6342 shader_ls.selector = ls;
6343 shader_ls.key.as_ls = 1;
6344 shader_ls.key.mono = shader->key.mono;
6345 shader_ls.key.opt = shader->key.opt;
6346 si_llvm_context_set_tgsi(&ctx, &shader_ls);
6347
6348 if (!si_compile_tgsi_main(&ctx, true)) {
6349 si_llvm_dispose(&ctx);
6350 return -1;
6351 }
6352 shader->info.uses_instanceid |= ls->info.uses_instanceid;
6353 parts[1] = ctx.main_fn;
6354
6355 /* Reset the shader context. */
6356 ctx.shader = shader;
6357 ctx.type = PIPE_SHADER_TESS_CTRL;
6358
6359 si_build_wrapper_function(&ctx,
6360 parts + !ls->vs_needs_prolog,
6361 4 - !ls->vs_needs_prolog, 0,
6362 ls->vs_needs_prolog ? 2 : 1);
6363 } else {
6364 LLVMValueRef parts[2];
6365 union si_shader_part_key epilog_key;
6366
6367 parts[0] = ctx.main_fn;
6368
6369 memset(&epilog_key, 0, sizeof(epilog_key));
6370 epilog_key.tcs_epilog.states = shader->key.part.tcs.epilog;
6371 si_build_tcs_epilog_function(&ctx, &epilog_key);
6372 parts[1] = ctx.main_fn;
6373
6374 si_build_wrapper_function(&ctx, parts, 2, 0, 0);
6375 }
6376 } else if (is_monolithic && ctx.type == PIPE_SHADER_GEOMETRY) {
6377 if (ctx.screen->b.chip_class >= GFX9) {
6378 struct si_shader_selector *es = shader->key.part.gs.es;
6379 LLVMValueRef es_prolog = NULL;
6380 LLVMValueRef es_main = NULL;
6381 LLVMValueRef gs_prolog = NULL;
6382 LLVMValueRef gs_main = ctx.main_fn;
6383
6384 /* GS prolog */
6385 union si_shader_part_key gs_prolog_key;
6386 memset(&gs_prolog_key, 0, sizeof(gs_prolog_key));
6387 gs_prolog_key.gs_prolog.states = shader->key.part.gs.prolog;
6388 gs_prolog_key.gs_prolog.is_monolithic = true;
6389 si_build_gs_prolog_function(&ctx, &gs_prolog_key);
6390 gs_prolog = ctx.main_fn;
6391
6392 /* ES prolog */
6393 if (es->vs_needs_prolog) {
6394 union si_shader_part_key vs_prolog_key;
6395 si_get_vs_prolog_key(&es->info,
6396 shader->info.num_input_sgprs,
6397 &shader->key.part.tcs.ls_prolog,
6398 shader, &vs_prolog_key);
6399 vs_prolog_key.vs_prolog.is_monolithic = true;
6400 si_build_vs_prolog_function(&ctx, &vs_prolog_key);
6401 es_prolog = ctx.main_fn;
6402 }
6403
6404 /* ES main part */
6405 struct si_shader shader_es = {};
6406 shader_es.selector = es;
6407 shader_es.key.as_es = 1;
6408 shader_es.key.mono = shader->key.mono;
6409 shader_es.key.opt = shader->key.opt;
6410 si_llvm_context_set_tgsi(&ctx, &shader_es);
6411
6412 if (!si_compile_tgsi_main(&ctx, true)) {
6413 si_llvm_dispose(&ctx);
6414 return -1;
6415 }
6416 shader->info.uses_instanceid |= es->info.uses_instanceid;
6417 es_main = ctx.main_fn;
6418
6419 /* Reset the shader context. */
6420 ctx.shader = shader;
6421 ctx.type = PIPE_SHADER_GEOMETRY;
6422
6423 /* Prepare the array of shader parts. */
6424 LLVMValueRef parts[4];
6425 unsigned num_parts = 0, main_part, next_first_part;
6426
6427 if (es_prolog)
6428 parts[num_parts++] = es_prolog;
6429
6430 parts[main_part = num_parts++] = es_main;
6431 parts[next_first_part = num_parts++] = gs_prolog;
6432 parts[num_parts++] = gs_main;
6433
6434 si_build_wrapper_function(&ctx, parts, num_parts,
6435 main_part, next_first_part);
6436 } else {
6437 LLVMValueRef parts[2];
6438 union si_shader_part_key prolog_key;
6439
6440 parts[1] = ctx.main_fn;
6441
6442 memset(&prolog_key, 0, sizeof(prolog_key));
6443 prolog_key.gs_prolog.states = shader->key.part.gs.prolog;
6444 si_build_gs_prolog_function(&ctx, &prolog_key);
6445 parts[0] = ctx.main_fn;
6446
6447 si_build_wrapper_function(&ctx, parts, 2, 1, 0);
6448 }
6449 } else if (is_monolithic && ctx.type == PIPE_SHADER_FRAGMENT) {
6450 LLVMValueRef parts[3];
6451 union si_shader_part_key prolog_key;
6452 union si_shader_part_key epilog_key;
6453 bool need_prolog;
6454
6455 si_get_ps_prolog_key(shader, &prolog_key, false);
6456 need_prolog = si_need_ps_prolog(&prolog_key);
6457
6458 parts[need_prolog ? 1 : 0] = ctx.main_fn;
6459
6460 if (need_prolog) {
6461 si_build_ps_prolog_function(&ctx, &prolog_key);
6462 parts[0] = ctx.main_fn;
6463 }
6464
6465 si_get_ps_epilog_key(shader, &epilog_key);
6466 si_build_ps_epilog_function(&ctx, &epilog_key);
6467 parts[need_prolog ? 2 : 1] = ctx.main_fn;
6468
6469 si_build_wrapper_function(&ctx, parts, need_prolog ? 3 : 2,
6470 need_prolog ? 1 : 0, 0);
6471 }
6472
6473 si_llvm_optimize_module(&ctx);
6474
6475 /* Post-optimization transformations and analysis. */
6476 si_optimize_vs_outputs(&ctx);
6477
6478 if ((debug && debug->debug_message) ||
6479 r600_can_dump_shader(&sscreen->b, ctx.type))
6480 si_count_scratch_private_memory(&ctx);
6481
6482 /* Compile to bytecode. */
6483 r = si_compile_llvm(sscreen, &shader->binary, &shader->config, tm,
6484 ctx.gallivm.module, debug, ctx.type, "TGSI shader");
6485 si_llvm_dispose(&ctx);
6486 if (r) {
6487 fprintf(stderr, "LLVM failed to compile shader\n");
6488 return r;
6489 }
6490
6491 /* Validate SGPR and VGPR usage for compute to detect compiler bugs.
6492 * LLVM 3.9svn has this bug.
6493 */
6494 if (sel->type == PIPE_SHADER_COMPUTE) {
6495 unsigned wave_size = 64;
6496 unsigned max_vgprs = 256;
6497 unsigned max_sgprs = sscreen->b.chip_class >= VI ? 800 : 512;
6498 unsigned max_sgprs_per_wave = 128;
6499 unsigned max_block_threads = si_get_max_workgroup_size(shader);
6500 unsigned min_waves_per_cu = DIV_ROUND_UP(max_block_threads, wave_size);
6501 unsigned min_waves_per_simd = DIV_ROUND_UP(min_waves_per_cu, 4);
6502
6503 max_vgprs = max_vgprs / min_waves_per_simd;
6504 max_sgprs = MIN2(max_sgprs / min_waves_per_simd, max_sgprs_per_wave);
6505
6506 if (shader->config.num_sgprs > max_sgprs ||
6507 shader->config.num_vgprs > max_vgprs) {
6508 fprintf(stderr, "LLVM failed to compile a shader correctly: "
6509 "SGPR:VGPR usage is %u:%u, but the hw limit is %u:%u\n",
6510 shader->config.num_sgprs, shader->config.num_vgprs,
6511 max_sgprs, max_vgprs);
6512
6513 /* Just terminate the process, because dependent
6514 * shaders can hang due to bad input data, but use
6515 * the env var to allow shader-db to work.
6516 */
6517 if (!debug_get_bool_option("SI_PASS_BAD_SHADERS", false))
6518 abort();
6519 }
6520 }
6521
6522 /* Add the scratch offset to input SGPRs. */
6523 if (shader->config.scratch_bytes_per_wave && !is_merged_shader(shader))
6524 shader->info.num_input_sgprs += 1; /* scratch byte offset */
6525
6526 /* Calculate the number of fragment input VGPRs. */
6527 if (ctx.type == PIPE_SHADER_FRAGMENT) {
6528 shader->info.num_input_vgprs = 0;
6529 shader->info.face_vgpr_index = -1;
6530
6531 if (G_0286CC_PERSP_SAMPLE_ENA(shader->config.spi_ps_input_addr))
6532 shader->info.num_input_vgprs += 2;
6533 if (G_0286CC_PERSP_CENTER_ENA(shader->config.spi_ps_input_addr))
6534 shader->info.num_input_vgprs += 2;
6535 if (G_0286CC_PERSP_CENTROID_ENA(shader->config.spi_ps_input_addr))
6536 shader->info.num_input_vgprs += 2;
6537 if (G_0286CC_PERSP_PULL_MODEL_ENA(shader->config.spi_ps_input_addr))
6538 shader->info.num_input_vgprs += 3;
6539 if (G_0286CC_LINEAR_SAMPLE_ENA(shader->config.spi_ps_input_addr))
6540 shader->info.num_input_vgprs += 2;
6541 if (G_0286CC_LINEAR_CENTER_ENA(shader->config.spi_ps_input_addr))
6542 shader->info.num_input_vgprs += 2;
6543 if (G_0286CC_LINEAR_CENTROID_ENA(shader->config.spi_ps_input_addr))
6544 shader->info.num_input_vgprs += 2;
6545 if (G_0286CC_LINE_STIPPLE_TEX_ENA(shader->config.spi_ps_input_addr))
6546 shader->info.num_input_vgprs += 1;
6547 if (G_0286CC_POS_X_FLOAT_ENA(shader->config.spi_ps_input_addr))
6548 shader->info.num_input_vgprs += 1;
6549 if (G_0286CC_POS_Y_FLOAT_ENA(shader->config.spi_ps_input_addr))
6550 shader->info.num_input_vgprs += 1;
6551 if (G_0286CC_POS_Z_FLOAT_ENA(shader->config.spi_ps_input_addr))
6552 shader->info.num_input_vgprs += 1;
6553 if (G_0286CC_POS_W_FLOAT_ENA(shader->config.spi_ps_input_addr))
6554 shader->info.num_input_vgprs += 1;
6555 if (G_0286CC_FRONT_FACE_ENA(shader->config.spi_ps_input_addr)) {
6556 shader->info.face_vgpr_index = shader->info.num_input_vgprs;
6557 shader->info.num_input_vgprs += 1;
6558 }
6559 if (G_0286CC_ANCILLARY_ENA(shader->config.spi_ps_input_addr))
6560 shader->info.num_input_vgprs += 1;
6561 if (G_0286CC_SAMPLE_COVERAGE_ENA(shader->config.spi_ps_input_addr))
6562 shader->info.num_input_vgprs += 1;
6563 if (G_0286CC_POS_FIXED_PT_ENA(shader->config.spi_ps_input_addr))
6564 shader->info.num_input_vgprs += 1;
6565 }
6566
6567 return 0;
6568 }
6569
6570 /**
6571 * Create, compile and return a shader part (prolog or epilog).
6572 *
6573 * \param sscreen screen
6574 * \param list list of shader parts of the same category
6575 * \param type shader type
6576 * \param key shader part key
6577 * \param prolog whether the part being requested is a prolog
6578 * \param tm LLVM target machine
6579 * \param debug debug callback
6580 * \param build the callback responsible for building the main function
6581 * \return non-NULL on success
6582 */
6583 static struct si_shader_part *
6584 si_get_shader_part(struct si_screen *sscreen,
6585 struct si_shader_part **list,
6586 enum pipe_shader_type type,
6587 bool prolog,
6588 union si_shader_part_key *key,
6589 LLVMTargetMachineRef tm,
6590 struct pipe_debug_callback *debug,
6591 void (*build)(struct si_shader_context *,
6592 union si_shader_part_key *),
6593 const char *name)
6594 {
6595 struct si_shader_part *result;
6596
6597 mtx_lock(&sscreen->shader_parts_mutex);
6598
6599 /* Find existing. */
6600 for (result = *list; result; result = result->next) {
6601 if (memcmp(&result->key, key, sizeof(*key)) == 0) {
6602 mtx_unlock(&sscreen->shader_parts_mutex);
6603 return result;
6604 }
6605 }
6606
6607 /* Compile a new one. */
6608 result = CALLOC_STRUCT(si_shader_part);
6609 result->key = *key;
6610
6611 struct si_shader shader = {};
6612 struct si_shader_context ctx;
6613 struct gallivm_state *gallivm = &ctx.gallivm;
6614
6615 si_init_shader_ctx(&ctx, sscreen, tm);
6616 ctx.shader = &shader;
6617 ctx.type = type;
6618
6619 switch (type) {
6620 case PIPE_SHADER_VERTEX:
6621 break;
6622 case PIPE_SHADER_TESS_CTRL:
6623 assert(!prolog);
6624 shader.key.part.tcs.epilog = key->tcs_epilog.states;
6625 break;
6626 case PIPE_SHADER_GEOMETRY:
6627 assert(prolog);
6628 break;
6629 case PIPE_SHADER_FRAGMENT:
6630 if (prolog)
6631 shader.key.part.ps.prolog = key->ps_prolog.states;
6632 else
6633 shader.key.part.ps.epilog = key->ps_epilog.states;
6634 break;
6635 default:
6636 unreachable("bad shader part");
6637 }
6638
6639 build(&ctx, key);
6640
6641 /* Compile. */
6642 si_llvm_optimize_module(&ctx);
6643
6644 if (si_compile_llvm(sscreen, &result->binary, &result->config, tm,
6645 gallivm->module, debug, ctx.type, name)) {
6646 FREE(result);
6647 result = NULL;
6648 goto out;
6649 }
6650
6651 result->next = *list;
6652 *list = result;
6653
6654 out:
6655 si_llvm_dispose(&ctx);
6656 mtx_unlock(&sscreen->shader_parts_mutex);
6657 return result;
6658 }
6659
6660 static LLVMValueRef si_prolog_get_rw_buffers(struct si_shader_context *ctx)
6661 {
6662 struct gallivm_state *gallivm = &ctx->gallivm;
6663 LLVMValueRef ptr[2], list;
6664
6665 /* Get the pointer to rw buffers. */
6666 ptr[0] = LLVMGetParam(ctx->main_fn, SI_SGPR_RW_BUFFERS);
6667 ptr[1] = LLVMGetParam(ctx->main_fn, SI_SGPR_RW_BUFFERS_HI);
6668 list = lp_build_gather_values(gallivm, ptr, 2);
6669 list = LLVMBuildBitCast(gallivm->builder, list, ctx->i64, "");
6670 list = LLVMBuildIntToPtr(gallivm->builder, list,
6671 si_const_array(ctx->v4i32, SI_NUM_RW_BUFFERS), "");
6672 return list;
6673 }
6674
6675 /**
6676 * Build the vertex shader prolog function.
6677 *
6678 * The inputs are the same as VS (a lot of SGPRs and 4 VGPR system values).
6679 * All inputs are returned unmodified. The vertex load indices are
6680 * stored after them, which will be used by the API VS for fetching inputs.
6681 *
6682 * For example, the expected outputs for instance_divisors[] = {0, 1, 2} are:
6683 * input_v0,
6684 * input_v1,
6685 * input_v2,
6686 * input_v3,
6687 * (VertexID + BaseVertex),
6688 * (InstanceID + StartInstance),
6689 * (InstanceID / 2 + StartInstance)
6690 */
6691 static void si_build_vs_prolog_function(struct si_shader_context *ctx,
6692 union si_shader_part_key *key)
6693 {
6694 struct gallivm_state *gallivm = &ctx->gallivm;
6695 struct si_function_info fninfo;
6696 LLVMTypeRef *returns;
6697 LLVMValueRef ret, func;
6698 int num_returns, i;
6699 unsigned first_vs_vgpr = key->vs_prolog.num_input_sgprs +
6700 key->vs_prolog.num_merged_next_stage_vgprs;
6701 unsigned num_input_vgprs = key->vs_prolog.num_merged_next_stage_vgprs + 4;
6702 unsigned num_all_input_regs = key->vs_prolog.num_input_sgprs +
6703 num_input_vgprs;
6704 unsigned user_sgpr_base = key->vs_prolog.num_merged_next_stage_vgprs ? 8 : 0;
6705
6706 si_init_function_info(&fninfo);
6707
6708 /* 4 preloaded VGPRs + vertex load indices as prolog outputs */
6709 returns = alloca((num_all_input_regs + key->vs_prolog.last_input + 1) *
6710 sizeof(LLVMTypeRef));
6711 num_returns = 0;
6712
6713 /* Declare input and output SGPRs. */
6714 for (i = 0; i < key->vs_prolog.num_input_sgprs; i++) {
6715 add_arg(&fninfo, ARG_SGPR, ctx->i32);
6716 returns[num_returns++] = ctx->i32;
6717 }
6718
6719 /* Preloaded VGPRs (outputs must be floats) */
6720 for (i = 0; i < num_input_vgprs; i++) {
6721 add_arg(&fninfo, ARG_VGPR, ctx->i32);
6722 returns[num_returns++] = ctx->f32;
6723 }
6724
6725 fninfo.assign[first_vs_vgpr] = &ctx->abi.vertex_id;
6726 fninfo.assign[first_vs_vgpr + (key->vs_prolog.as_ls ? 2 : 1)] = &ctx->abi.instance_id;
6727
6728 /* Vertex load indices. */
6729 for (i = 0; i <= key->vs_prolog.last_input; i++)
6730 returns[num_returns++] = ctx->f32;
6731
6732 /* Create the function. */
6733 si_create_function(ctx, "vs_prolog", returns, num_returns, &fninfo, 0);
6734 func = ctx->main_fn;
6735
6736 if (key->vs_prolog.num_merged_next_stage_vgprs &&
6737 !key->vs_prolog.is_monolithic)
6738 si_init_exec_from_input(ctx, 3, 0);
6739
6740 /* Copy inputs to outputs. This should be no-op, as the registers match,
6741 * but it will prevent the compiler from overwriting them unintentionally.
6742 */
6743 ret = ctx->return_value;
6744 for (i = 0; i < key->vs_prolog.num_input_sgprs; i++) {
6745 LLVMValueRef p = LLVMGetParam(func, i);
6746 ret = LLVMBuildInsertValue(gallivm->builder, ret, p, i, "");
6747 }
6748 for (; i < fninfo.num_params; i++) {
6749 LLVMValueRef p = LLVMGetParam(func, i);
6750 p = LLVMBuildBitCast(gallivm->builder, p, ctx->f32, "");
6751 ret = LLVMBuildInsertValue(gallivm->builder, ret, p, i, "");
6752 }
6753
6754 /* Compute vertex load indices from instance divisors. */
6755 LLVMValueRef instance_divisor_constbuf = NULL;
6756
6757 if (key->vs_prolog.states.instance_divisor_is_fetched) {
6758 LLVMValueRef list = si_prolog_get_rw_buffers(ctx);
6759 LLVMValueRef buf_index =
6760 LLVMConstInt(ctx->i32, SI_VS_CONST_INSTANCE_DIVISORS, 0);
6761 instance_divisor_constbuf =
6762 ac_build_indexed_load_const(&ctx->ac, list, buf_index);
6763 }
6764
6765 for (i = 0; i <= key->vs_prolog.last_input; i++) {
6766 bool divisor_is_one =
6767 key->vs_prolog.states.instance_divisor_is_one & (1u << i);
6768 bool divisor_is_fetched =
6769 key->vs_prolog.states.instance_divisor_is_fetched & (1u << i);
6770 LLVMValueRef index;
6771
6772 if (divisor_is_one || divisor_is_fetched) {
6773 LLVMValueRef divisor = ctx->i32_1;
6774
6775 if (divisor_is_fetched) {
6776 divisor = buffer_load_const(ctx, instance_divisor_constbuf,
6777 LLVMConstInt(ctx->i32, i * 4, 0));
6778 divisor = LLVMBuildBitCast(gallivm->builder, divisor,
6779 ctx->i32, "");
6780 }
6781
6782 /* InstanceID / Divisor + StartInstance */
6783 index = get_instance_index_for_fetch(ctx,
6784 user_sgpr_base +
6785 SI_SGPR_START_INSTANCE,
6786 divisor);
6787 } else {
6788 /* VertexID + BaseVertex */
6789 index = LLVMBuildAdd(gallivm->builder,
6790 ctx->abi.vertex_id,
6791 LLVMGetParam(func, user_sgpr_base +
6792 SI_SGPR_BASE_VERTEX), "");
6793 }
6794
6795 index = LLVMBuildBitCast(gallivm->builder, index, ctx->f32, "");
6796 ret = LLVMBuildInsertValue(gallivm->builder, ret, index,
6797 fninfo.num_params + i, "");
6798 }
6799
6800 si_llvm_build_ret(ctx, ret);
6801 }
6802
6803 static bool si_get_vs_prolog(struct si_screen *sscreen,
6804 LLVMTargetMachineRef tm,
6805 struct si_shader *shader,
6806 struct pipe_debug_callback *debug,
6807 struct si_shader *main_part,
6808 const struct si_vs_prolog_bits *key)
6809 {
6810 struct si_shader_selector *vs = main_part->selector;
6811
6812 /* The prolog is a no-op if there are no inputs. */
6813 if (!vs->vs_needs_prolog)
6814 return true;
6815
6816 /* Get the prolog. */
6817 union si_shader_part_key prolog_key;
6818 si_get_vs_prolog_key(&vs->info, main_part->info.num_input_sgprs,
6819 key, shader, &prolog_key);
6820
6821 shader->prolog =
6822 si_get_shader_part(sscreen, &sscreen->vs_prologs,
6823 PIPE_SHADER_VERTEX, true, &prolog_key, tm,
6824 debug, si_build_vs_prolog_function,
6825 "Vertex Shader Prolog");
6826 return shader->prolog != NULL;
6827 }
6828
6829 /**
6830 * Select and compile (or reuse) vertex shader parts (prolog & epilog).
6831 */
6832 static bool si_shader_select_vs_parts(struct si_screen *sscreen,
6833 LLVMTargetMachineRef tm,
6834 struct si_shader *shader,
6835 struct pipe_debug_callback *debug)
6836 {
6837 return si_get_vs_prolog(sscreen, tm, shader, debug, shader,
6838 &shader->key.part.vs.prolog);
6839 }
6840
6841 /**
6842 * Compile the TCS epilog function. This writes tesselation factors to memory
6843 * based on the output primitive type of the tesselator (determined by TES).
6844 */
6845 static void si_build_tcs_epilog_function(struct si_shader_context *ctx,
6846 union si_shader_part_key *key)
6847 {
6848 struct gallivm_state *gallivm = &ctx->gallivm;
6849 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
6850 struct si_function_info fninfo;
6851 LLVMValueRef func;
6852
6853 si_init_function_info(&fninfo);
6854
6855 if (ctx->screen->b.chip_class >= GFX9) {
6856 add_arg(&fninfo, ARG_SGPR, ctx->i64);
6857 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
6858 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* wave info */
6859 ctx->param_tcs_factor_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
6860 add_arg(&fninfo, ARG_SGPR, ctx->i32);
6861 add_arg(&fninfo, ARG_SGPR, ctx->i32);
6862 add_arg(&fninfo, ARG_SGPR, ctx->i32);
6863 add_arg(&fninfo, ARG_SGPR, ctx->i64);
6864 add_arg(&fninfo, ARG_SGPR, ctx->i64);
6865 add_arg(&fninfo, ARG_SGPR, ctx->i64);
6866 add_arg(&fninfo, ARG_SGPR, ctx->i64);
6867 add_arg(&fninfo, ARG_SGPR, ctx->i32);
6868 add_arg(&fninfo, ARG_SGPR, ctx->i32);
6869 add_arg(&fninfo, ARG_SGPR, ctx->i32);
6870 add_arg(&fninfo, ARG_SGPR, ctx->i32);
6871 ctx->param_tcs_offchip_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
6872 add_arg(&fninfo, ARG_SGPR, ctx->i32);
6873 add_arg(&fninfo, ARG_SGPR, ctx->i32);
6874 ctx->param_tcs_offchip_addr_base64k = add_arg(&fninfo, ARG_SGPR, ctx->i32);
6875 ctx->param_tcs_factor_addr_base64k = add_arg(&fninfo, ARG_SGPR, ctx->i32);
6876 } else {
6877 add_arg(&fninfo, ARG_SGPR, ctx->i64);
6878 add_arg(&fninfo, ARG_SGPR, ctx->i64);
6879 add_arg(&fninfo, ARG_SGPR, ctx->i64);
6880 ctx->param_tcs_offchip_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
6881 add_arg(&fninfo, ARG_SGPR, ctx->i32);
6882 add_arg(&fninfo, ARG_SGPR, ctx->i32);
6883 add_arg(&fninfo, ARG_SGPR, ctx->i32);
6884 ctx->param_tcs_offchip_addr_base64k = add_arg(&fninfo, ARG_SGPR, ctx->i32);
6885 ctx->param_tcs_factor_addr_base64k = add_arg(&fninfo, ARG_SGPR, ctx->i32);
6886 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
6887 ctx->param_tcs_factor_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
6888 }
6889
6890 add_arg(&fninfo, ARG_VGPR, ctx->i32); /* VGPR gap */
6891 add_arg(&fninfo, ARG_VGPR, ctx->i32); /* VGPR gap */
6892 unsigned tess_factors_idx =
6893 add_arg(&fninfo, ARG_VGPR, ctx->i32); /* patch index within the wave (REL_PATCH_ID) */
6894 add_arg(&fninfo, ARG_VGPR, ctx->i32); /* invocation ID within the patch */
6895 add_arg(&fninfo, ARG_VGPR, ctx->i32); /* LDS offset where tess factors should be loaded from */
6896
6897 /* Create the function. */
6898 si_create_function(ctx, "tcs_epilog", NULL, 0, &fninfo,
6899 ctx->screen->b.chip_class >= CIK ? 128 : 64);
6900 declare_lds_as_pointer(ctx);
6901 func = ctx->main_fn;
6902
6903 si_write_tess_factors(bld_base,
6904 LLVMGetParam(func, tess_factors_idx),
6905 LLVMGetParam(func, tess_factors_idx + 1),
6906 LLVMGetParam(func, tess_factors_idx + 2));
6907
6908 LLVMBuildRetVoid(gallivm->builder);
6909 }
6910
6911 /**
6912 * Select and compile (or reuse) TCS parts (epilog).
6913 */
6914 static bool si_shader_select_tcs_parts(struct si_screen *sscreen,
6915 LLVMTargetMachineRef tm,
6916 struct si_shader *shader,
6917 struct pipe_debug_callback *debug)
6918 {
6919 if (sscreen->b.chip_class >= GFX9) {
6920 struct si_shader *ls_main_part =
6921 shader->key.part.tcs.ls->main_shader_part_ls;
6922
6923 if (!si_get_vs_prolog(sscreen, tm, shader, debug, ls_main_part,
6924 &shader->key.part.tcs.ls_prolog))
6925 return false;
6926
6927 shader->previous_stage = ls_main_part;
6928 }
6929
6930 /* Get the epilog. */
6931 union si_shader_part_key epilog_key;
6932 memset(&epilog_key, 0, sizeof(epilog_key));
6933 epilog_key.tcs_epilog.states = shader->key.part.tcs.epilog;
6934
6935 shader->epilog = si_get_shader_part(sscreen, &sscreen->tcs_epilogs,
6936 PIPE_SHADER_TESS_CTRL, false,
6937 &epilog_key, tm, debug,
6938 si_build_tcs_epilog_function,
6939 "Tessellation Control Shader Epilog");
6940 return shader->epilog != NULL;
6941 }
6942
6943 /**
6944 * Select and compile (or reuse) GS parts (prolog).
6945 */
6946 static bool si_shader_select_gs_parts(struct si_screen *sscreen,
6947 LLVMTargetMachineRef tm,
6948 struct si_shader *shader,
6949 struct pipe_debug_callback *debug)
6950 {
6951 if (sscreen->b.chip_class >= GFX9) {
6952 struct si_shader *es_main_part =
6953 shader->key.part.gs.es->main_shader_part_es;
6954
6955 if (shader->key.part.gs.es->type == PIPE_SHADER_VERTEX &&
6956 !si_get_vs_prolog(sscreen, tm, shader, debug, es_main_part,
6957 &shader->key.part.gs.vs_prolog))
6958 return false;
6959
6960 shader->previous_stage = es_main_part;
6961 }
6962
6963 if (!shader->key.part.gs.prolog.tri_strip_adj_fix)
6964 return true;
6965
6966 union si_shader_part_key prolog_key;
6967 memset(&prolog_key, 0, sizeof(prolog_key));
6968 prolog_key.gs_prolog.states = shader->key.part.gs.prolog;
6969
6970 shader->prolog2 = si_get_shader_part(sscreen, &sscreen->gs_prologs,
6971 PIPE_SHADER_GEOMETRY, true,
6972 &prolog_key, tm, debug,
6973 si_build_gs_prolog_function,
6974 "Geometry Shader Prolog");
6975 return shader->prolog2 != NULL;
6976 }
6977
6978 /**
6979 * Build the pixel shader prolog function. This handles:
6980 * - two-side color selection and interpolation
6981 * - overriding interpolation parameters for the API PS
6982 * - polygon stippling
6983 *
6984 * All preloaded SGPRs and VGPRs are passed through unmodified unless they are
6985 * overriden by other states. (e.g. per-sample interpolation)
6986 * Interpolated colors are stored after the preloaded VGPRs.
6987 */
6988 static void si_build_ps_prolog_function(struct si_shader_context *ctx,
6989 union si_shader_part_key *key)
6990 {
6991 struct gallivm_state *gallivm = &ctx->gallivm;
6992 struct si_function_info fninfo;
6993 LLVMValueRef ret, func;
6994 int num_returns, i, num_color_channels;
6995
6996 assert(si_need_ps_prolog(key));
6997
6998 si_init_function_info(&fninfo);
6999
7000 /* Declare inputs. */
7001 for (i = 0; i < key->ps_prolog.num_input_sgprs; i++)
7002 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7003
7004 for (i = 0; i < key->ps_prolog.num_input_vgprs; i++)
7005 add_arg(&fninfo, ARG_VGPR, ctx->f32);
7006
7007 /* Declare outputs (same as inputs + add colors if needed) */
7008 num_returns = fninfo.num_params;
7009 num_color_channels = util_bitcount(key->ps_prolog.colors_read);
7010 for (i = 0; i < num_color_channels; i++)
7011 fninfo.types[num_returns++] = ctx->f32;
7012
7013 /* Create the function. */
7014 si_create_function(ctx, "ps_prolog", fninfo.types, num_returns,
7015 &fninfo, 0);
7016 func = ctx->main_fn;
7017
7018 /* Copy inputs to outputs. This should be no-op, as the registers match,
7019 * but it will prevent the compiler from overwriting them unintentionally.
7020 */
7021 ret = ctx->return_value;
7022 for (i = 0; i < fninfo.num_params; i++) {
7023 LLVMValueRef p = LLVMGetParam(func, i);
7024 ret = LLVMBuildInsertValue(gallivm->builder, ret, p, i, "");
7025 }
7026
7027 /* Polygon stippling. */
7028 if (key->ps_prolog.states.poly_stipple) {
7029 /* POS_FIXED_PT is always last. */
7030 unsigned pos = key->ps_prolog.num_input_sgprs +
7031 key->ps_prolog.num_input_vgprs - 1;
7032 LLVMValueRef list = si_prolog_get_rw_buffers(ctx);
7033
7034 si_llvm_emit_polygon_stipple(ctx, list, pos);
7035 }
7036
7037 if (key->ps_prolog.states.bc_optimize_for_persp ||
7038 key->ps_prolog.states.bc_optimize_for_linear) {
7039 unsigned i, base = key->ps_prolog.num_input_sgprs;
7040 LLVMValueRef center[2], centroid[2], tmp, bc_optimize;
7041
7042 /* The shader should do: if (PRIM_MASK[31]) CENTROID = CENTER;
7043 * The hw doesn't compute CENTROID if the whole wave only
7044 * contains fully-covered quads.
7045 *
7046 * PRIM_MASK is after user SGPRs.
7047 */
7048 bc_optimize = LLVMGetParam(func, SI_PS_NUM_USER_SGPR);
7049 bc_optimize = LLVMBuildLShr(gallivm->builder, bc_optimize,
7050 LLVMConstInt(ctx->i32, 31, 0), "");
7051 bc_optimize = LLVMBuildTrunc(gallivm->builder, bc_optimize,
7052 ctx->i1, "");
7053
7054 if (key->ps_prolog.states.bc_optimize_for_persp) {
7055 /* Read PERSP_CENTER. */
7056 for (i = 0; i < 2; i++)
7057 center[i] = LLVMGetParam(func, base + 2 + i);
7058 /* Read PERSP_CENTROID. */
7059 for (i = 0; i < 2; i++)
7060 centroid[i] = LLVMGetParam(func, base + 4 + i);
7061 /* Select PERSP_CENTROID. */
7062 for (i = 0; i < 2; i++) {
7063 tmp = LLVMBuildSelect(gallivm->builder, bc_optimize,
7064 center[i], centroid[i], "");
7065 ret = LLVMBuildInsertValue(gallivm->builder, ret,
7066 tmp, base + 4 + i, "");
7067 }
7068 }
7069 if (key->ps_prolog.states.bc_optimize_for_linear) {
7070 /* Read LINEAR_CENTER. */
7071 for (i = 0; i < 2; i++)
7072 center[i] = LLVMGetParam(func, base + 8 + i);
7073 /* Read LINEAR_CENTROID. */
7074 for (i = 0; i < 2; i++)
7075 centroid[i] = LLVMGetParam(func, base + 10 + i);
7076 /* Select LINEAR_CENTROID. */
7077 for (i = 0; i < 2; i++) {
7078 tmp = LLVMBuildSelect(gallivm->builder, bc_optimize,
7079 center[i], centroid[i], "");
7080 ret = LLVMBuildInsertValue(gallivm->builder, ret,
7081 tmp, base + 10 + i, "");
7082 }
7083 }
7084 }
7085
7086 /* Force per-sample interpolation. */
7087 if (key->ps_prolog.states.force_persp_sample_interp) {
7088 unsigned i, base = key->ps_prolog.num_input_sgprs;
7089 LLVMValueRef persp_sample[2];
7090
7091 /* Read PERSP_SAMPLE. */
7092 for (i = 0; i < 2; i++)
7093 persp_sample[i] = LLVMGetParam(func, base + i);
7094 /* Overwrite PERSP_CENTER. */
7095 for (i = 0; i < 2; i++)
7096 ret = LLVMBuildInsertValue(gallivm->builder, ret,
7097 persp_sample[i], base + 2 + i, "");
7098 /* Overwrite PERSP_CENTROID. */
7099 for (i = 0; i < 2; i++)
7100 ret = LLVMBuildInsertValue(gallivm->builder, ret,
7101 persp_sample[i], base + 4 + i, "");
7102 }
7103 if (key->ps_prolog.states.force_linear_sample_interp) {
7104 unsigned i, base = key->ps_prolog.num_input_sgprs;
7105 LLVMValueRef linear_sample[2];
7106
7107 /* Read LINEAR_SAMPLE. */
7108 for (i = 0; i < 2; i++)
7109 linear_sample[i] = LLVMGetParam(func, base + 6 + i);
7110 /* Overwrite LINEAR_CENTER. */
7111 for (i = 0; i < 2; i++)
7112 ret = LLVMBuildInsertValue(gallivm->builder, ret,
7113 linear_sample[i], base + 8 + i, "");
7114 /* Overwrite LINEAR_CENTROID. */
7115 for (i = 0; i < 2; i++)
7116 ret = LLVMBuildInsertValue(gallivm->builder, ret,
7117 linear_sample[i], base + 10 + i, "");
7118 }
7119
7120 /* Force center interpolation. */
7121 if (key->ps_prolog.states.force_persp_center_interp) {
7122 unsigned i, base = key->ps_prolog.num_input_sgprs;
7123 LLVMValueRef persp_center[2];
7124
7125 /* Read PERSP_CENTER. */
7126 for (i = 0; i < 2; i++)
7127 persp_center[i] = LLVMGetParam(func, base + 2 + i);
7128 /* Overwrite PERSP_SAMPLE. */
7129 for (i = 0; i < 2; i++)
7130 ret = LLVMBuildInsertValue(gallivm->builder, ret,
7131 persp_center[i], base + i, "");
7132 /* Overwrite PERSP_CENTROID. */
7133 for (i = 0; i < 2; i++)
7134 ret = LLVMBuildInsertValue(gallivm->builder, ret,
7135 persp_center[i], base + 4 + i, "");
7136 }
7137 if (key->ps_prolog.states.force_linear_center_interp) {
7138 unsigned i, base = key->ps_prolog.num_input_sgprs;
7139 LLVMValueRef linear_center[2];
7140
7141 /* Read LINEAR_CENTER. */
7142 for (i = 0; i < 2; i++)
7143 linear_center[i] = LLVMGetParam(func, base + 8 + i);
7144 /* Overwrite LINEAR_SAMPLE. */
7145 for (i = 0; i < 2; i++)
7146 ret = LLVMBuildInsertValue(gallivm->builder, ret,
7147 linear_center[i], base + 6 + i, "");
7148 /* Overwrite LINEAR_CENTROID. */
7149 for (i = 0; i < 2; i++)
7150 ret = LLVMBuildInsertValue(gallivm->builder, ret,
7151 linear_center[i], base + 10 + i, "");
7152 }
7153
7154 /* Interpolate colors. */
7155 unsigned color_out_idx = 0;
7156 for (i = 0; i < 2; i++) {
7157 unsigned writemask = (key->ps_prolog.colors_read >> (i * 4)) & 0xf;
7158 unsigned face_vgpr = key->ps_prolog.num_input_sgprs +
7159 key->ps_prolog.face_vgpr_index;
7160 LLVMValueRef interp[2], color[4];
7161 LLVMValueRef interp_ij = NULL, prim_mask = NULL, face = NULL;
7162
7163 if (!writemask)
7164 continue;
7165
7166 /* If the interpolation qualifier is not CONSTANT (-1). */
7167 if (key->ps_prolog.color_interp_vgpr_index[i] != -1) {
7168 unsigned interp_vgpr = key->ps_prolog.num_input_sgprs +
7169 key->ps_prolog.color_interp_vgpr_index[i];
7170
7171 /* Get the (i,j) updated by bc_optimize handling. */
7172 interp[0] = LLVMBuildExtractValue(gallivm->builder, ret,
7173 interp_vgpr, "");
7174 interp[1] = LLVMBuildExtractValue(gallivm->builder, ret,
7175 interp_vgpr + 1, "");
7176 interp_ij = lp_build_gather_values(gallivm, interp, 2);
7177 }
7178
7179 /* Use the absolute location of the input. */
7180 prim_mask = LLVMGetParam(func, SI_PS_NUM_USER_SGPR);
7181
7182 if (key->ps_prolog.states.color_two_side) {
7183 face = LLVMGetParam(func, face_vgpr);
7184 face = LLVMBuildBitCast(gallivm->builder, face, ctx->i32, "");
7185 }
7186
7187 interp_fs_input(ctx,
7188 key->ps_prolog.color_attr_index[i],
7189 TGSI_SEMANTIC_COLOR, i,
7190 key->ps_prolog.num_interp_inputs,
7191 key->ps_prolog.colors_read, interp_ij,
7192 prim_mask, face, color);
7193
7194 while (writemask) {
7195 unsigned chan = u_bit_scan(&writemask);
7196 ret = LLVMBuildInsertValue(gallivm->builder, ret, color[chan],
7197 fninfo.num_params + color_out_idx++, "");
7198 }
7199 }
7200
7201 /* Tell LLVM to insert WQM instruction sequence when needed. */
7202 if (key->ps_prolog.wqm) {
7203 LLVMAddTargetDependentFunctionAttr(func,
7204 "amdgpu-ps-wqm-outputs", "");
7205 }
7206
7207 si_llvm_build_ret(ctx, ret);
7208 }
7209
7210 /**
7211 * Build the pixel shader epilog function. This handles everything that must be
7212 * emulated for pixel shader exports. (alpha-test, format conversions, etc)
7213 */
7214 static void si_build_ps_epilog_function(struct si_shader_context *ctx,
7215 union si_shader_part_key *key)
7216 {
7217 struct gallivm_state *gallivm = &ctx->gallivm;
7218 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
7219 struct si_function_info fninfo;
7220 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
7221 int i;
7222 struct si_ps_exports exp = {};
7223
7224 si_init_function_info(&fninfo);
7225
7226 /* Declare input SGPRs. */
7227 ctx->param_rw_buffers = add_arg(&fninfo, ARG_SGPR, ctx->i64);
7228 ctx->param_const_and_shader_buffers = add_arg(&fninfo, ARG_SGPR, ctx->i64);
7229 ctx->param_samplers_and_images = add_arg(&fninfo, ARG_SGPR, ctx->i64);
7230 add_arg_checked(&fninfo, ARG_SGPR, ctx->f32, SI_PARAM_ALPHA_REF);
7231
7232 /* Declare input VGPRs. */
7233 unsigned required_num_params =
7234 fninfo.num_sgpr_params +
7235 util_bitcount(key->ps_epilog.colors_written) * 4 +
7236 key->ps_epilog.writes_z +
7237 key->ps_epilog.writes_stencil +
7238 key->ps_epilog.writes_samplemask;
7239
7240 required_num_params = MAX2(required_num_params,
7241 fninfo.num_sgpr_params + PS_EPILOG_SAMPLEMASK_MIN_LOC + 1);
7242
7243 while (fninfo.num_params < required_num_params)
7244 add_arg(&fninfo, ARG_VGPR, ctx->f32);
7245
7246 /* Create the function. */
7247 si_create_function(ctx, "ps_epilog", NULL, 0, &fninfo, 0);
7248 /* Disable elimination of unused inputs. */
7249 si_llvm_add_attribute(ctx->main_fn,
7250 "InitialPSInputAddr", 0xffffff);
7251
7252 /* Process colors. */
7253 unsigned vgpr = fninfo.num_sgpr_params;
7254 unsigned colors_written = key->ps_epilog.colors_written;
7255 int last_color_export = -1;
7256
7257 /* Find the last color export. */
7258 if (!key->ps_epilog.writes_z &&
7259 !key->ps_epilog.writes_stencil &&
7260 !key->ps_epilog.writes_samplemask) {
7261 unsigned spi_format = key->ps_epilog.states.spi_shader_col_format;
7262
7263 /* If last_cbuf > 0, FS_COLOR0_WRITES_ALL_CBUFS is true. */
7264 if (colors_written == 0x1 && key->ps_epilog.states.last_cbuf > 0) {
7265 /* Just set this if any of the colorbuffers are enabled. */
7266 if (spi_format &
7267 ((1ull << (4 * (key->ps_epilog.states.last_cbuf + 1))) - 1))
7268 last_color_export = 0;
7269 } else {
7270 for (i = 0; i < 8; i++)
7271 if (colors_written & (1 << i) &&
7272 (spi_format >> (i * 4)) & 0xf)
7273 last_color_export = i;
7274 }
7275 }
7276
7277 while (colors_written) {
7278 LLVMValueRef color[4];
7279 int mrt = u_bit_scan(&colors_written);
7280
7281 for (i = 0; i < 4; i++)
7282 color[i] = LLVMGetParam(ctx->main_fn, vgpr++);
7283
7284 si_export_mrt_color(bld_base, color, mrt,
7285 fninfo.num_params - 1,
7286 mrt == last_color_export, &exp);
7287 }
7288
7289 /* Process depth, stencil, samplemask. */
7290 if (key->ps_epilog.writes_z)
7291 depth = LLVMGetParam(ctx->main_fn, vgpr++);
7292 if (key->ps_epilog.writes_stencil)
7293 stencil = LLVMGetParam(ctx->main_fn, vgpr++);
7294 if (key->ps_epilog.writes_samplemask)
7295 samplemask = LLVMGetParam(ctx->main_fn, vgpr++);
7296
7297 if (depth || stencil || samplemask)
7298 si_export_mrt_z(bld_base, depth, stencil, samplemask, &exp);
7299 else if (last_color_export == -1)
7300 si_export_null(bld_base);
7301
7302 if (exp.num)
7303 si_emit_ps_exports(ctx, &exp);
7304
7305 /* Compile. */
7306 LLVMBuildRetVoid(gallivm->builder);
7307 }
7308
7309 /**
7310 * Select and compile (or reuse) pixel shader parts (prolog & epilog).
7311 */
7312 static bool si_shader_select_ps_parts(struct si_screen *sscreen,
7313 LLVMTargetMachineRef tm,
7314 struct si_shader *shader,
7315 struct pipe_debug_callback *debug)
7316 {
7317 union si_shader_part_key prolog_key;
7318 union si_shader_part_key epilog_key;
7319
7320 /* Get the prolog. */
7321 si_get_ps_prolog_key(shader, &prolog_key, true);
7322
7323 /* The prolog is a no-op if these aren't set. */
7324 if (si_need_ps_prolog(&prolog_key)) {
7325 shader->prolog =
7326 si_get_shader_part(sscreen, &sscreen->ps_prologs,
7327 PIPE_SHADER_FRAGMENT, true,
7328 &prolog_key, tm, debug,
7329 si_build_ps_prolog_function,
7330 "Fragment Shader Prolog");
7331 if (!shader->prolog)
7332 return false;
7333 }
7334
7335 /* Get the epilog. */
7336 si_get_ps_epilog_key(shader, &epilog_key);
7337
7338 shader->epilog =
7339 si_get_shader_part(sscreen, &sscreen->ps_epilogs,
7340 PIPE_SHADER_FRAGMENT, false,
7341 &epilog_key, tm, debug,
7342 si_build_ps_epilog_function,
7343 "Fragment Shader Epilog");
7344 if (!shader->epilog)
7345 return false;
7346
7347 /* Enable POS_FIXED_PT if polygon stippling is enabled. */
7348 if (shader->key.part.ps.prolog.poly_stipple) {
7349 shader->config.spi_ps_input_ena |= S_0286CC_POS_FIXED_PT_ENA(1);
7350 assert(G_0286CC_POS_FIXED_PT_ENA(shader->config.spi_ps_input_addr));
7351 }
7352
7353 /* Set up the enable bits for per-sample shading if needed. */
7354 if (shader->key.part.ps.prolog.force_persp_sample_interp &&
7355 (G_0286CC_PERSP_CENTER_ENA(shader->config.spi_ps_input_ena) ||
7356 G_0286CC_PERSP_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
7357 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_CENTER_ENA;
7358 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_CENTROID_ENA;
7359 shader->config.spi_ps_input_ena |= S_0286CC_PERSP_SAMPLE_ENA(1);
7360 }
7361 if (shader->key.part.ps.prolog.force_linear_sample_interp &&
7362 (G_0286CC_LINEAR_CENTER_ENA(shader->config.spi_ps_input_ena) ||
7363 G_0286CC_LINEAR_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
7364 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_CENTER_ENA;
7365 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_CENTROID_ENA;
7366 shader->config.spi_ps_input_ena |= S_0286CC_LINEAR_SAMPLE_ENA(1);
7367 }
7368 if (shader->key.part.ps.prolog.force_persp_center_interp &&
7369 (G_0286CC_PERSP_SAMPLE_ENA(shader->config.spi_ps_input_ena) ||
7370 G_0286CC_PERSP_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
7371 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_SAMPLE_ENA;
7372 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_CENTROID_ENA;
7373 shader->config.spi_ps_input_ena |= S_0286CC_PERSP_CENTER_ENA(1);
7374 }
7375 if (shader->key.part.ps.prolog.force_linear_center_interp &&
7376 (G_0286CC_LINEAR_SAMPLE_ENA(shader->config.spi_ps_input_ena) ||
7377 G_0286CC_LINEAR_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
7378 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_SAMPLE_ENA;
7379 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_CENTROID_ENA;
7380 shader->config.spi_ps_input_ena |= S_0286CC_LINEAR_CENTER_ENA(1);
7381 }
7382
7383 /* POW_W_FLOAT requires that one of the perspective weights is enabled. */
7384 if (G_0286CC_POS_W_FLOAT_ENA(shader->config.spi_ps_input_ena) &&
7385 !(shader->config.spi_ps_input_ena & 0xf)) {
7386 shader->config.spi_ps_input_ena |= S_0286CC_PERSP_CENTER_ENA(1);
7387 assert(G_0286CC_PERSP_CENTER_ENA(shader->config.spi_ps_input_addr));
7388 }
7389
7390 /* At least one pair of interpolation weights must be enabled. */
7391 if (!(shader->config.spi_ps_input_ena & 0x7f)) {
7392 shader->config.spi_ps_input_ena |= S_0286CC_LINEAR_CENTER_ENA(1);
7393 assert(G_0286CC_LINEAR_CENTER_ENA(shader->config.spi_ps_input_addr));
7394 }
7395
7396 /* The sample mask input is always enabled, because the API shader always
7397 * passes it through to the epilog. Disable it here if it's unused.
7398 */
7399 if (!shader->key.part.ps.epilog.poly_line_smoothing &&
7400 !shader->selector->info.reads_samplemask)
7401 shader->config.spi_ps_input_ena &= C_0286CC_SAMPLE_COVERAGE_ENA;
7402
7403 return true;
7404 }
7405
7406 void si_multiwave_lds_size_workaround(struct si_screen *sscreen,
7407 unsigned *lds_size)
7408 {
7409 /* SPI barrier management bug:
7410 * Make sure we have at least 4k of LDS in use to avoid the bug.
7411 * It applies to workgroup sizes of more than one wavefront.
7412 */
7413 if (sscreen->b.family == CHIP_BONAIRE ||
7414 sscreen->b.family == CHIP_KABINI ||
7415 sscreen->b.family == CHIP_MULLINS)
7416 *lds_size = MAX2(*lds_size, 8);
7417 }
7418
7419 static void si_fix_resource_usage(struct si_screen *sscreen,
7420 struct si_shader *shader)
7421 {
7422 unsigned min_sgprs = shader->info.num_input_sgprs + 2; /* VCC */
7423
7424 shader->config.num_sgprs = MAX2(shader->config.num_sgprs, min_sgprs);
7425
7426 if (shader->selector->type == PIPE_SHADER_COMPUTE &&
7427 si_get_max_workgroup_size(shader) > 64) {
7428 si_multiwave_lds_size_workaround(sscreen,
7429 &shader->config.lds_size);
7430 }
7431 }
7432
7433 int si_shader_create(struct si_screen *sscreen, LLVMTargetMachineRef tm,
7434 struct si_shader *shader,
7435 struct pipe_debug_callback *debug)
7436 {
7437 struct si_shader_selector *sel = shader->selector;
7438 struct si_shader *mainp = *si_get_main_shader_part(sel, &shader->key);
7439 int r;
7440
7441 /* LS, ES, VS are compiled on demand if the main part hasn't been
7442 * compiled for that stage.
7443 *
7444 * Vertex shaders are compiled on demand when a vertex fetch
7445 * workaround must be applied.
7446 */
7447 if (shader->is_monolithic) {
7448 /* Monolithic shader (compiled as a whole, has many variants,
7449 * may take a long time to compile).
7450 */
7451 r = si_compile_tgsi_shader(sscreen, tm, shader, true, debug);
7452 if (r)
7453 return r;
7454 } else {
7455 /* The shader consists of several parts:
7456 *
7457 * - the middle part is the user shader, it has 1 variant only
7458 * and it was compiled during the creation of the shader
7459 * selector
7460 * - the prolog part is inserted at the beginning
7461 * - the epilog part is inserted at the end
7462 *
7463 * The prolog and epilog have many (but simple) variants.
7464 *
7465 * Starting with gfx9, geometry and tessellation control
7466 * shaders also contain the prolog and user shader parts of
7467 * the previous shader stage.
7468 */
7469
7470 if (!mainp)
7471 return -1;
7472
7473 /* Copy the compiled TGSI shader data over. */
7474 shader->is_binary_shared = true;
7475 shader->binary = mainp->binary;
7476 shader->config = mainp->config;
7477 shader->info.num_input_sgprs = mainp->info.num_input_sgprs;
7478 shader->info.num_input_vgprs = mainp->info.num_input_vgprs;
7479 shader->info.face_vgpr_index = mainp->info.face_vgpr_index;
7480 memcpy(shader->info.vs_output_param_offset,
7481 mainp->info.vs_output_param_offset,
7482 sizeof(mainp->info.vs_output_param_offset));
7483 shader->info.uses_instanceid = mainp->info.uses_instanceid;
7484 shader->info.nr_pos_exports = mainp->info.nr_pos_exports;
7485 shader->info.nr_param_exports = mainp->info.nr_param_exports;
7486
7487 /* Select prologs and/or epilogs. */
7488 switch (sel->type) {
7489 case PIPE_SHADER_VERTEX:
7490 if (!si_shader_select_vs_parts(sscreen, tm, shader, debug))
7491 return -1;
7492 break;
7493 case PIPE_SHADER_TESS_CTRL:
7494 if (!si_shader_select_tcs_parts(sscreen, tm, shader, debug))
7495 return -1;
7496 break;
7497 case PIPE_SHADER_TESS_EVAL:
7498 break;
7499 case PIPE_SHADER_GEOMETRY:
7500 if (!si_shader_select_gs_parts(sscreen, tm, shader, debug))
7501 return -1;
7502 break;
7503 case PIPE_SHADER_FRAGMENT:
7504 if (!si_shader_select_ps_parts(sscreen, tm, shader, debug))
7505 return -1;
7506
7507 /* Make sure we have at least as many VGPRs as there
7508 * are allocated inputs.
7509 */
7510 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
7511 shader->info.num_input_vgprs);
7512 break;
7513 }
7514
7515 /* Update SGPR and VGPR counts. */
7516 if (shader->prolog) {
7517 shader->config.num_sgprs = MAX2(shader->config.num_sgprs,
7518 shader->prolog->config.num_sgprs);
7519 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
7520 shader->prolog->config.num_vgprs);
7521 }
7522 if (shader->previous_stage) {
7523 shader->config.num_sgprs = MAX2(shader->config.num_sgprs,
7524 shader->previous_stage->config.num_sgprs);
7525 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
7526 shader->previous_stage->config.num_vgprs);
7527 shader->config.spilled_sgprs =
7528 MAX2(shader->config.spilled_sgprs,
7529 shader->previous_stage->config.spilled_sgprs);
7530 shader->config.spilled_vgprs =
7531 MAX2(shader->config.spilled_vgprs,
7532 shader->previous_stage->config.spilled_vgprs);
7533 shader->config.private_mem_vgprs =
7534 MAX2(shader->config.private_mem_vgprs,
7535 shader->previous_stage->config.private_mem_vgprs);
7536 shader->config.scratch_bytes_per_wave =
7537 MAX2(shader->config.scratch_bytes_per_wave,
7538 shader->previous_stage->config.scratch_bytes_per_wave);
7539 shader->info.uses_instanceid |=
7540 shader->previous_stage->info.uses_instanceid;
7541 }
7542 if (shader->prolog2) {
7543 shader->config.num_sgprs = MAX2(shader->config.num_sgprs,
7544 shader->prolog2->config.num_sgprs);
7545 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
7546 shader->prolog2->config.num_vgprs);
7547 }
7548 if (shader->epilog) {
7549 shader->config.num_sgprs = MAX2(shader->config.num_sgprs,
7550 shader->epilog->config.num_sgprs);
7551 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
7552 shader->epilog->config.num_vgprs);
7553 }
7554 }
7555
7556 si_fix_resource_usage(sscreen, shader);
7557 si_shader_dump(sscreen, shader, debug, sel->info.processor,
7558 stderr, true);
7559
7560 /* Upload. */
7561 r = si_shader_binary_upload(sscreen, shader);
7562 if (r) {
7563 fprintf(stderr, "LLVM failed to upload shader\n");
7564 return r;
7565 }
7566
7567 return 0;
7568 }
7569
7570 void si_shader_destroy(struct si_shader *shader)
7571 {
7572 if (shader->scratch_bo)
7573 r600_resource_reference(&shader->scratch_bo, NULL);
7574
7575 r600_resource_reference(&shader->bo, NULL);
7576
7577 if (!shader->is_binary_shared)
7578 radeon_shader_binary_clean(&shader->binary);
7579
7580 free(shader->shader_log);
7581 }