2 * Copyright 2012 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 * Tom Stellard <thomas.stellard@amd.com>
25 * Michel Dänzer <michel.daenzer@amd.com>
26 * Christian König <christian.koenig@amd.com>
29 #include "gallivm/lp_bld_const.h"
30 #include "gallivm/lp_bld_gather.h"
31 #include "gallivm/lp_bld_intr.h"
32 #include "gallivm/lp_bld_logic.h"
33 #include "gallivm/lp_bld_arit.h"
34 #include "gallivm/lp_bld_bitarit.h"
35 #include "gallivm/lp_bld_flow.h"
36 #include "radeon/r600_cs.h"
37 #include "radeon/radeon_llvm.h"
38 #include "radeon/radeon_elf_util.h"
39 #include "radeon/radeon_llvm_emit.h"
40 #include "util/u_memory.h"
41 #include "util/u_pstipple.h"
42 #include "tgsi/tgsi_parse.h"
43 #include "tgsi/tgsi_util.h"
44 #include "tgsi/tgsi_dump.h"
47 #include "si_shader.h"
52 static const char *scratch_rsrc_dword0_symbol
=
53 "SCRATCH_RSRC_DWORD0";
55 static const char *scratch_rsrc_dword1_symbol
=
56 "SCRATCH_RSRC_DWORD1";
58 struct si_shader_output_values
60 LLVMValueRef values
[4];
65 struct si_shader_context
67 struct radeon_llvm_context radeon_bld
;
68 struct si_shader
*shader
;
69 struct si_screen
*screen
;
70 unsigned type
; /* TGSI_PROCESSOR_* specifies the type of shader. */
71 bool is_gs_copy_shader
;
72 int param_streamout_config
;
73 int param_streamout_write_index
;
74 int param_streamout_offset
[4];
76 int param_rel_auto_id
;
78 int param_instance_id
;
81 int param_tes_rel_patch_id
;
82 int param_tes_patch_id
;
83 int param_es2gs_offset
;
84 LLVMTargetMachineRef tm
;
85 LLVMValueRef const_md
;
86 LLVMValueRef const_buffers
[SI_NUM_CONST_BUFFERS
];
88 LLVMValueRef
*constants
[SI_NUM_CONST_BUFFERS
];
89 LLVMValueRef sampler_views
[SI_NUM_SAMPLER_VIEWS
];
90 LLVMValueRef sampler_states
[SI_NUM_SAMPLER_STATES
];
91 LLVMValueRef so_buffers
[4];
92 LLVMValueRef esgs_ring
;
93 LLVMValueRef gsvs_ring
[4];
94 LLVMValueRef gs_next_vertex
[4];
97 static struct si_shader_context
* si_shader_context(
98 struct lp_build_tgsi_context
* bld_base
)
100 return (struct si_shader_context
*)bld_base
;
104 #define PERSPECTIVE_BASE 0
105 #define LINEAR_BASE 9
107 #define SAMPLE_OFFSET 0
108 #define CENTER_OFFSET 2
109 #define CENTROID_OFSET 4
111 #define USE_SGPR_MAX_SUFFIX_LEN 5
112 #define CONST_ADDR_SPACE 2
113 #define LOCAL_ADDR_SPACE 3
114 #define USER_SGPR_ADDR_SPACE 8
118 #define SENDMSG_GS_DONE 3
120 #define SENDMSG_GS_OP_NOP (0 << 4)
121 #define SENDMSG_GS_OP_CUT (1 << 4)
122 #define SENDMSG_GS_OP_EMIT (2 << 4)
123 #define SENDMSG_GS_OP_EMIT_CUT (3 << 4)
126 * Returns a unique index for a semantic name and index. The index must be
127 * less than 64, so that a 64-bit bitmask of used inputs or outputs can be
130 unsigned si_shader_io_get_unique_index(unsigned semantic_name
, unsigned index
)
132 switch (semantic_name
) {
133 case TGSI_SEMANTIC_POSITION
:
135 case TGSI_SEMANTIC_PSIZE
:
137 case TGSI_SEMANTIC_CLIPDIST
:
140 case TGSI_SEMANTIC_GENERIC
:
144 /* same explanation as in the default statement,
145 * the only user hitting this is st/nine.
149 /* patch indices are completely separate and thus start from 0 */
150 case TGSI_SEMANTIC_TESSOUTER
:
152 case TGSI_SEMANTIC_TESSINNER
:
154 case TGSI_SEMANTIC_PATCH
:
158 /* Don't fail here. The result of this function is only used
159 * for LS, TCS, TES, and GS, where legacy GL semantics can't
160 * occur, but this function is called for all vertex shaders
161 * before it's known whether LS will be compiled or not.
168 * Get the value of a shader input parameter and extract a bitfield.
170 static LLVMValueRef
unpack_param(struct si_shader_context
*si_shader_ctx
,
171 unsigned param
, unsigned rshift
,
174 struct gallivm_state
*gallivm
= &si_shader_ctx
->radeon_bld
.gallivm
;
175 LLVMValueRef value
= LLVMGetParam(si_shader_ctx
->radeon_bld
.main_fn
,
179 value
= LLVMBuildLShr(gallivm
->builder
, value
,
180 lp_build_const_int32(gallivm
, rshift
), "");
182 if (rshift
+ bitwidth
< 32) {
183 unsigned mask
= (1 << bitwidth
) - 1;
184 value
= LLVMBuildAnd(gallivm
->builder
, value
,
185 lp_build_const_int32(gallivm
, mask
), "");
191 static LLVMValueRef
get_rel_patch_id(struct si_shader_context
*si_shader_ctx
)
193 switch (si_shader_ctx
->type
) {
194 case TGSI_PROCESSOR_TESS_CTRL
:
195 return unpack_param(si_shader_ctx
, SI_PARAM_REL_IDS
, 0, 8);
197 case TGSI_PROCESSOR_TESS_EVAL
:
198 return LLVMGetParam(si_shader_ctx
->radeon_bld
.main_fn
,
199 si_shader_ctx
->param_tes_rel_patch_id
);
207 /* Tessellation shaders pass outputs to the next shader using LDS.
209 * LS outputs = TCS inputs
210 * TCS outputs = TES inputs
213 * - TCS inputs for patch 0
214 * - TCS inputs for patch 1
215 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
217 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
218 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
219 * - TCS outputs for patch 1
220 * - Per-patch TCS outputs for patch 1
221 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
222 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
225 * All three shaders VS(LS), TCS, TES share the same LDS space.
229 get_tcs_in_patch_stride(struct si_shader_context
*si_shader_ctx
)
231 if (si_shader_ctx
->type
== TGSI_PROCESSOR_VERTEX
)
232 return unpack_param(si_shader_ctx
, SI_PARAM_LS_OUT_LAYOUT
, 0, 13);
233 else if (si_shader_ctx
->type
== TGSI_PROCESSOR_TESS_CTRL
)
234 return unpack_param(si_shader_ctx
, SI_PARAM_TCS_IN_LAYOUT
, 0, 13);
242 get_tcs_out_patch_stride(struct si_shader_context
*si_shader_ctx
)
244 return unpack_param(si_shader_ctx
, SI_PARAM_TCS_OUT_LAYOUT
, 0, 13);
248 get_tcs_out_patch0_offset(struct si_shader_context
*si_shader_ctx
)
250 return lp_build_mul_imm(&si_shader_ctx
->radeon_bld
.soa
.bld_base
.uint_bld
,
251 unpack_param(si_shader_ctx
,
252 SI_PARAM_TCS_OUT_OFFSETS
,
258 get_tcs_out_patch0_patch_data_offset(struct si_shader_context
*si_shader_ctx
)
260 return lp_build_mul_imm(&si_shader_ctx
->radeon_bld
.soa
.bld_base
.uint_bld
,
261 unpack_param(si_shader_ctx
,
262 SI_PARAM_TCS_OUT_OFFSETS
,
268 get_tcs_in_current_patch_offset(struct si_shader_context
*si_shader_ctx
)
270 struct gallivm_state
*gallivm
= &si_shader_ctx
->radeon_bld
.gallivm
;
271 LLVMValueRef patch_stride
= get_tcs_in_patch_stride(si_shader_ctx
);
272 LLVMValueRef rel_patch_id
= get_rel_patch_id(si_shader_ctx
);
274 return LLVMBuildMul(gallivm
->builder
, patch_stride
, rel_patch_id
, "");
278 get_tcs_out_current_patch_offset(struct si_shader_context
*si_shader_ctx
)
280 struct gallivm_state
*gallivm
= &si_shader_ctx
->radeon_bld
.gallivm
;
281 LLVMValueRef patch0_offset
= get_tcs_out_patch0_offset(si_shader_ctx
);
282 LLVMValueRef patch_stride
= get_tcs_out_patch_stride(si_shader_ctx
);
283 LLVMValueRef rel_patch_id
= get_rel_patch_id(si_shader_ctx
);
285 return LLVMBuildAdd(gallivm
->builder
, patch0_offset
,
286 LLVMBuildMul(gallivm
->builder
, patch_stride
,
292 get_tcs_out_current_patch_data_offset(struct si_shader_context
*si_shader_ctx
)
294 struct gallivm_state
*gallivm
= &si_shader_ctx
->radeon_bld
.gallivm
;
295 LLVMValueRef patch0_patch_data_offset
=
296 get_tcs_out_patch0_patch_data_offset(si_shader_ctx
);
297 LLVMValueRef patch_stride
= get_tcs_out_patch_stride(si_shader_ctx
);
298 LLVMValueRef rel_patch_id
= get_rel_patch_id(si_shader_ctx
);
300 return LLVMBuildAdd(gallivm
->builder
, patch0_patch_data_offset
,
301 LLVMBuildMul(gallivm
->builder
, patch_stride
,
306 static void build_indexed_store(struct si_shader_context
*si_shader_ctx
,
307 LLVMValueRef base_ptr
, LLVMValueRef index
,
310 struct lp_build_tgsi_context
*bld_base
= &si_shader_ctx
->radeon_bld
.soa
.bld_base
;
311 struct gallivm_state
*gallivm
= bld_base
->base
.gallivm
;
312 LLVMValueRef indices
[2], pointer
;
314 indices
[0] = bld_base
->uint_bld
.zero
;
317 pointer
= LLVMBuildGEP(gallivm
->builder
, base_ptr
, indices
, 2, "");
318 LLVMBuildStore(gallivm
->builder
, value
, pointer
);
322 * Build an LLVM bytecode indexed load using LLVMBuildGEP + LLVMBuildLoad.
323 * It's equivalent to doing a load from &base_ptr[index].
325 * \param base_ptr Where the array starts.
326 * \param index The element index into the array.
328 static LLVMValueRef
build_indexed_load(struct si_shader_context
*si_shader_ctx
,
329 LLVMValueRef base_ptr
, LLVMValueRef index
)
331 struct lp_build_tgsi_context
*bld_base
= &si_shader_ctx
->radeon_bld
.soa
.bld_base
;
332 struct gallivm_state
*gallivm
= bld_base
->base
.gallivm
;
333 LLVMValueRef indices
[2], pointer
;
335 indices
[0] = bld_base
->uint_bld
.zero
;
338 pointer
= LLVMBuildGEP(gallivm
->builder
, base_ptr
, indices
, 2, "");
339 return LLVMBuildLoad(gallivm
->builder
, pointer
, "");
343 * Do a load from &base_ptr[index], but also add a flag that it's loading
346 static LLVMValueRef
build_indexed_load_const(
347 struct si_shader_context
* si_shader_ctx
,
348 LLVMValueRef base_ptr
, LLVMValueRef index
)
350 LLVMValueRef result
= build_indexed_load(si_shader_ctx
, base_ptr
, index
);
351 LLVMSetMetadata(result
, 1, si_shader_ctx
->const_md
);
355 static LLVMValueRef
get_instance_index_for_fetch(
356 struct radeon_llvm_context
* radeon_bld
,
359 struct si_shader_context
*si_shader_ctx
=
360 si_shader_context(&radeon_bld
->soa
.bld_base
);
361 struct gallivm_state
* gallivm
= radeon_bld
->soa
.bld_base
.base
.gallivm
;
363 LLVMValueRef result
= LLVMGetParam(radeon_bld
->main_fn
,
364 si_shader_ctx
->param_instance_id
);
366 /* The division must be done before START_INSTANCE is added. */
368 result
= LLVMBuildUDiv(gallivm
->builder
, result
,
369 lp_build_const_int32(gallivm
, divisor
), "");
371 return LLVMBuildAdd(gallivm
->builder
, result
, LLVMGetParam(
372 radeon_bld
->main_fn
, SI_PARAM_START_INSTANCE
), "");
375 static void declare_input_vs(
376 struct radeon_llvm_context
*radeon_bld
,
377 unsigned input_index
,
378 const struct tgsi_full_declaration
*decl
)
380 struct lp_build_context
*base
= &radeon_bld
->soa
.bld_base
.base
;
381 struct gallivm_state
*gallivm
= base
->gallivm
;
382 struct si_shader_context
*si_shader_ctx
=
383 si_shader_context(&radeon_bld
->soa
.bld_base
);
384 unsigned divisor
= si_shader_ctx
->shader
->key
.vs
.instance_divisors
[input_index
];
388 LLVMValueRef t_list_ptr
;
389 LLVMValueRef t_offset
;
391 LLVMValueRef attribute_offset
;
392 LLVMValueRef buffer_index
;
393 LLVMValueRef args
[3];
394 LLVMTypeRef vec4_type
;
397 /* Load the T list */
398 t_list_ptr
= LLVMGetParam(si_shader_ctx
->radeon_bld
.main_fn
, SI_PARAM_VERTEX_BUFFERS
);
400 t_offset
= lp_build_const_int32(gallivm
, input_index
);
402 t_list
= build_indexed_load_const(si_shader_ctx
, t_list_ptr
, t_offset
);
404 /* Build the attribute offset */
405 attribute_offset
= lp_build_const_int32(gallivm
, 0);
408 /* Build index from instance ID, start instance and divisor */
409 si_shader_ctx
->shader
->uses_instanceid
= true;
410 buffer_index
= get_instance_index_for_fetch(&si_shader_ctx
->radeon_bld
, divisor
);
412 /* Load the buffer index for vertices. */
413 LLVMValueRef vertex_id
= LLVMGetParam(si_shader_ctx
->radeon_bld
.main_fn
,
414 si_shader_ctx
->param_vertex_id
);
415 LLVMValueRef base_vertex
= LLVMGetParam(radeon_bld
->main_fn
,
416 SI_PARAM_BASE_VERTEX
);
417 buffer_index
= LLVMBuildAdd(gallivm
->builder
, base_vertex
, vertex_id
, "");
420 vec4_type
= LLVMVectorType(base
->elem_type
, 4);
422 args
[1] = attribute_offset
;
423 args
[2] = buffer_index
;
424 input
= lp_build_intrinsic(gallivm
->builder
,
425 "llvm.SI.vs.load.input", vec4_type
, args
, 3,
426 LLVMReadNoneAttribute
| LLVMNoUnwindAttribute
);
428 /* Break up the vec4 into individual components */
429 for (chan
= 0; chan
< 4; chan
++) {
430 LLVMValueRef llvm_chan
= lp_build_const_int32(gallivm
, chan
);
431 /* XXX: Use a helper function for this. There is one in
433 si_shader_ctx
->radeon_bld
.inputs
[radeon_llvm_reg_index_soa(input_index
, chan
)] =
434 LLVMBuildExtractElement(gallivm
->builder
,
435 input
, llvm_chan
, "");
439 static LLVMValueRef
get_primitive_id(struct lp_build_tgsi_context
*bld_base
,
442 struct si_shader_context
*si_shader_ctx
= si_shader_context(bld_base
);
445 return bld_base
->uint_bld
.zero
;
447 switch (si_shader_ctx
->type
) {
448 case TGSI_PROCESSOR_VERTEX
:
449 return LLVMGetParam(si_shader_ctx
->radeon_bld
.main_fn
,
450 si_shader_ctx
->param_vs_prim_id
);
451 case TGSI_PROCESSOR_TESS_CTRL
:
452 return LLVMGetParam(si_shader_ctx
->radeon_bld
.main_fn
,
454 case TGSI_PROCESSOR_TESS_EVAL
:
455 return LLVMGetParam(si_shader_ctx
->radeon_bld
.main_fn
,
456 si_shader_ctx
->param_tes_patch_id
);
457 case TGSI_PROCESSOR_GEOMETRY
:
458 return LLVMGetParam(si_shader_ctx
->radeon_bld
.main_fn
,
459 SI_PARAM_PRIMITIVE_ID
);
462 return bld_base
->uint_bld
.zero
;
467 * Return the value of tgsi_ind_register for indexing.
468 * This is the indirect index with the constant offset added to it.
470 static LLVMValueRef
get_indirect_index(struct si_shader_context
*si_shader_ctx
,
471 const struct tgsi_ind_register
*ind
,
474 struct gallivm_state
*gallivm
= si_shader_ctx
->radeon_bld
.soa
.bld_base
.base
.gallivm
;
477 result
= si_shader_ctx
->radeon_bld
.soa
.addr
[ind
->Index
][ind
->Swizzle
];
478 result
= LLVMBuildLoad(gallivm
->builder
, result
, "");
479 result
= LLVMBuildAdd(gallivm
->builder
, result
,
480 lp_build_const_int32(gallivm
, rel_index
), "");
485 * Calculate a dword address given an input or output register and a stride.
487 static LLVMValueRef
get_dw_address(struct si_shader_context
*si_shader_ctx
,
488 const struct tgsi_full_dst_register
*dst
,
489 const struct tgsi_full_src_register
*src
,
490 LLVMValueRef vertex_dw_stride
,
491 LLVMValueRef base_addr
)
493 struct gallivm_state
*gallivm
= si_shader_ctx
->radeon_bld
.soa
.bld_base
.base
.gallivm
;
494 struct tgsi_shader_info
*info
= &si_shader_ctx
->shader
->selector
->info
;
495 ubyte
*name
, *index
, *array_first
;
497 struct tgsi_full_dst_register reg
;
499 /* Set the register description. The address computation is the same
500 * for sources and destinations. */
502 reg
.Register
.File
= src
->Register
.File
;
503 reg
.Register
.Index
= src
->Register
.Index
;
504 reg
.Register
.Indirect
= src
->Register
.Indirect
;
505 reg
.Register
.Dimension
= src
->Register
.Dimension
;
506 reg
.Indirect
= src
->Indirect
;
507 reg
.Dimension
= src
->Dimension
;
508 reg
.DimIndirect
= src
->DimIndirect
;
512 /* If the register is 2-dimensional (e.g. an array of vertices
513 * in a primitive), calculate the base address of the vertex. */
514 if (reg
.Register
.Dimension
) {
517 if (reg
.Dimension
.Indirect
)
518 index
= get_indirect_index(si_shader_ctx
, ®
.DimIndirect
,
519 reg
.Dimension
.Index
);
521 index
= lp_build_const_int32(gallivm
, reg
.Dimension
.Index
);
523 base_addr
= LLVMBuildAdd(gallivm
->builder
, base_addr
,
524 LLVMBuildMul(gallivm
->builder
, index
,
525 vertex_dw_stride
, ""), "");
528 /* Get information about the register. */
529 if (reg
.Register
.File
== TGSI_FILE_INPUT
) {
530 name
= info
->input_semantic_name
;
531 index
= info
->input_semantic_index
;
532 array_first
= info
->input_array_first
;
533 } else if (reg
.Register
.File
== TGSI_FILE_OUTPUT
) {
534 name
= info
->output_semantic_name
;
535 index
= info
->output_semantic_index
;
536 array_first
= info
->output_array_first
;
542 if (reg
.Register
.Indirect
) {
543 /* Add the relative address of the element. */
544 LLVMValueRef ind_index
;
546 if (reg
.Indirect
.ArrayID
)
547 first
= array_first
[reg
.Indirect
.ArrayID
];
549 first
= reg
.Register
.Index
;
551 ind_index
= get_indirect_index(si_shader_ctx
, ®
.Indirect
,
552 reg
.Register
.Index
- first
);
554 base_addr
= LLVMBuildAdd(gallivm
->builder
, base_addr
,
555 LLVMBuildMul(gallivm
->builder
, ind_index
,
556 lp_build_const_int32(gallivm
, 4), ""), "");
558 param
= si_shader_io_get_unique_index(name
[first
], index
[first
]);
560 param
= si_shader_io_get_unique_index(name
[reg
.Register
.Index
],
561 index
[reg
.Register
.Index
]);
564 /* Add the base address of the element. */
565 return LLVMBuildAdd(gallivm
->builder
, base_addr
,
566 lp_build_const_int32(gallivm
, param
* 4), "");
572 * \param type output value type
573 * \param swizzle offset (typically 0..3); it can be ~0, which loads a vec4
574 * \param dw_addr address in dwords
576 static LLVMValueRef
lds_load(struct lp_build_tgsi_context
*bld_base
,
577 enum tgsi_opcode_type type
, unsigned swizzle
,
578 LLVMValueRef dw_addr
)
580 struct si_shader_context
*si_shader_ctx
= si_shader_context(bld_base
);
581 struct gallivm_state
*gallivm
= bld_base
->base
.gallivm
;
585 LLVMValueRef values
[TGSI_NUM_CHANNELS
];
587 for (unsigned chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++)
588 values
[chan
] = lds_load(bld_base
, type
, chan
, dw_addr
);
590 return lp_build_gather_values(bld_base
->base
.gallivm
, values
,
594 dw_addr
= lp_build_add(&bld_base
->uint_bld
, dw_addr
,
595 lp_build_const_int32(gallivm
, swizzle
));
597 value
= build_indexed_load(si_shader_ctx
, si_shader_ctx
->lds
, dw_addr
);
598 if (type
== TGSI_TYPE_DOUBLE
) {
600 dw_addr
= lp_build_add(&bld_base
->uint_bld
, dw_addr
,
601 lp_build_const_int32(gallivm
, swizzle
+ 1));
602 value2
= build_indexed_load(si_shader_ctx
, si_shader_ctx
->lds
, dw_addr
);
603 return radeon_llvm_emit_fetch_double(bld_base
, value
, value2
);
606 return LLVMBuildBitCast(gallivm
->builder
, value
,
607 tgsi2llvmtype(bld_base
, type
), "");
613 * \param swizzle offset (typically 0..3)
614 * \param dw_addr address in dwords
615 * \param value value to store
617 static void lds_store(struct lp_build_tgsi_context
* bld_base
,
618 unsigned swizzle
, LLVMValueRef dw_addr
,
621 struct si_shader_context
*si_shader_ctx
= si_shader_context(bld_base
);
622 struct gallivm_state
*gallivm
= bld_base
->base
.gallivm
;
624 dw_addr
= lp_build_add(&bld_base
->uint_bld
, dw_addr
,
625 lp_build_const_int32(gallivm
, swizzle
));
627 value
= LLVMBuildBitCast(gallivm
->builder
, value
,
628 LLVMInt32TypeInContext(gallivm
->context
), "");
629 build_indexed_store(si_shader_ctx
, si_shader_ctx
->lds
,
633 static LLVMValueRef
fetch_input_tcs(
634 struct lp_build_tgsi_context
*bld_base
,
635 const struct tgsi_full_src_register
*reg
,
636 enum tgsi_opcode_type type
, unsigned swizzle
)
638 struct si_shader_context
*si_shader_ctx
= si_shader_context(bld_base
);
639 LLVMValueRef dw_addr
, stride
;
641 stride
= unpack_param(si_shader_ctx
, SI_PARAM_TCS_IN_LAYOUT
, 13, 8);
642 dw_addr
= get_tcs_in_current_patch_offset(si_shader_ctx
);
643 dw_addr
= get_dw_address(si_shader_ctx
, NULL
, reg
, stride
, dw_addr
);
645 return lds_load(bld_base
, type
, swizzle
, dw_addr
);
648 static LLVMValueRef
fetch_output_tcs(
649 struct lp_build_tgsi_context
*bld_base
,
650 const struct tgsi_full_src_register
*reg
,
651 enum tgsi_opcode_type type
, unsigned swizzle
)
653 struct si_shader_context
*si_shader_ctx
= si_shader_context(bld_base
);
654 LLVMValueRef dw_addr
, stride
;
656 if (reg
->Register
.Dimension
) {
657 stride
= unpack_param(si_shader_ctx
, SI_PARAM_TCS_OUT_LAYOUT
, 13, 8);
658 dw_addr
= get_tcs_out_current_patch_offset(si_shader_ctx
);
659 dw_addr
= get_dw_address(si_shader_ctx
, NULL
, reg
, stride
, dw_addr
);
661 dw_addr
= get_tcs_out_current_patch_data_offset(si_shader_ctx
);
662 dw_addr
= get_dw_address(si_shader_ctx
, NULL
, reg
, NULL
, dw_addr
);
665 return lds_load(bld_base
, type
, swizzle
, dw_addr
);
668 static LLVMValueRef
fetch_input_tes(
669 struct lp_build_tgsi_context
*bld_base
,
670 const struct tgsi_full_src_register
*reg
,
671 enum tgsi_opcode_type type
, unsigned swizzle
)
673 struct si_shader_context
*si_shader_ctx
= si_shader_context(bld_base
);
674 LLVMValueRef dw_addr
, stride
;
676 if (reg
->Register
.Dimension
) {
677 stride
= unpack_param(si_shader_ctx
, SI_PARAM_TCS_OUT_LAYOUT
, 13, 8);
678 dw_addr
= get_tcs_out_current_patch_offset(si_shader_ctx
);
679 dw_addr
= get_dw_address(si_shader_ctx
, NULL
, reg
, stride
, dw_addr
);
681 dw_addr
= get_tcs_out_current_patch_data_offset(si_shader_ctx
);
682 dw_addr
= get_dw_address(si_shader_ctx
, NULL
, reg
, NULL
, dw_addr
);
685 return lds_load(bld_base
, type
, swizzle
, dw_addr
);
688 static void store_output_tcs(struct lp_build_tgsi_context
* bld_base
,
689 const struct tgsi_full_instruction
* inst
,
690 const struct tgsi_opcode_info
* info
,
693 struct si_shader_context
*si_shader_ctx
= si_shader_context(bld_base
);
694 const struct tgsi_full_dst_register
*reg
= &inst
->Dst
[0];
696 LLVMValueRef dw_addr
, stride
;
698 /* Only handle per-patch and per-vertex outputs here.
699 * Vectors will be lowered to scalars and this function will be called again.
701 if (reg
->Register
.File
!= TGSI_FILE_OUTPUT
||
702 (dst
[0] && LLVMGetTypeKind(LLVMTypeOf(dst
[0])) == LLVMVectorTypeKind
)) {
703 radeon_llvm_emit_store(bld_base
, inst
, info
, dst
);
707 if (reg
->Register
.Dimension
) {
708 stride
= unpack_param(si_shader_ctx
, SI_PARAM_TCS_OUT_LAYOUT
, 13, 8);
709 dw_addr
= get_tcs_out_current_patch_offset(si_shader_ctx
);
710 dw_addr
= get_dw_address(si_shader_ctx
, reg
, NULL
, stride
, dw_addr
);
712 dw_addr
= get_tcs_out_current_patch_data_offset(si_shader_ctx
);
713 dw_addr
= get_dw_address(si_shader_ctx
, reg
, NULL
, NULL
, dw_addr
);
716 TGSI_FOR_EACH_DST0_ENABLED_CHANNEL(inst
, chan_index
) {
717 LLVMValueRef value
= dst
[chan_index
];
719 if (inst
->Instruction
.Saturate
)
720 value
= radeon_llvm_saturate(bld_base
, value
);
722 lds_store(bld_base
, chan_index
, dw_addr
, value
);
726 static LLVMValueRef
fetch_input_gs(
727 struct lp_build_tgsi_context
*bld_base
,
728 const struct tgsi_full_src_register
*reg
,
729 enum tgsi_opcode_type type
,
732 struct lp_build_context
*base
= &bld_base
->base
;
733 struct si_shader_context
*si_shader_ctx
= si_shader_context(bld_base
);
734 struct si_shader
*shader
= si_shader_ctx
->shader
;
735 struct lp_build_context
*uint
= &si_shader_ctx
->radeon_bld
.soa
.bld_base
.uint_bld
;
736 struct gallivm_state
*gallivm
= base
->gallivm
;
737 LLVMTypeRef i32
= LLVMInt32TypeInContext(gallivm
->context
);
738 LLVMValueRef vtx_offset
;
739 LLVMValueRef args
[9];
740 unsigned vtx_offset_param
;
741 struct tgsi_shader_info
*info
= &shader
->selector
->info
;
742 unsigned semantic_name
= info
->input_semantic_name
[reg
->Register
.Index
];
743 unsigned semantic_index
= info
->input_semantic_index
[reg
->Register
.Index
];
747 if (swizzle
!= ~0 && semantic_name
== TGSI_SEMANTIC_PRIMID
)
748 return get_primitive_id(bld_base
, swizzle
);
750 if (!reg
->Register
.Dimension
)
754 LLVMValueRef values
[TGSI_NUM_CHANNELS
];
756 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
757 values
[chan
] = fetch_input_gs(bld_base
, reg
, type
, chan
);
759 return lp_build_gather_values(bld_base
->base
.gallivm
, values
,
763 /* Get the vertex offset parameter */
764 vtx_offset_param
= reg
->Dimension
.Index
;
765 if (vtx_offset_param
< 2) {
766 vtx_offset_param
+= SI_PARAM_VTX0_OFFSET
;
768 assert(vtx_offset_param
< 6);
769 vtx_offset_param
+= SI_PARAM_VTX2_OFFSET
- 2;
771 vtx_offset
= lp_build_mul_imm(uint
,
772 LLVMGetParam(si_shader_ctx
->radeon_bld
.main_fn
,
776 param
= si_shader_io_get_unique_index(semantic_name
, semantic_index
);
777 args
[0] = si_shader_ctx
->esgs_ring
;
778 args
[1] = vtx_offset
;
779 args
[2] = lp_build_const_int32(gallivm
, (param
* 4 + swizzle
) * 256);
780 args
[3] = uint
->zero
;
781 args
[4] = uint
->one
; /* OFFEN */
782 args
[5] = uint
->zero
; /* IDXEN */
783 args
[6] = uint
->one
; /* GLC */
784 args
[7] = uint
->zero
; /* SLC */
785 args
[8] = uint
->zero
; /* TFE */
787 value
= lp_build_intrinsic(gallivm
->builder
,
788 "llvm.SI.buffer.load.dword.i32.i32",
790 LLVMReadOnlyAttribute
| LLVMNoUnwindAttribute
);
791 if (type
== TGSI_TYPE_DOUBLE
) {
793 args
[2] = lp_build_const_int32(gallivm
, (param
* 4 + swizzle
+ 1) * 256);
794 value2
= lp_build_intrinsic(gallivm
->builder
,
795 "llvm.SI.buffer.load.dword.i32.i32",
797 LLVMReadOnlyAttribute
| LLVMNoUnwindAttribute
);
798 return radeon_llvm_emit_fetch_double(bld_base
,
801 return LLVMBuildBitCast(gallivm
->builder
,
803 tgsi2llvmtype(bld_base
, type
), "");
806 static int lookup_interp_param_index(unsigned interpolate
, unsigned location
)
808 switch (interpolate
) {
809 case TGSI_INTERPOLATE_CONSTANT
:
812 case TGSI_INTERPOLATE_LINEAR
:
813 if (location
== TGSI_INTERPOLATE_LOC_SAMPLE
)
814 return SI_PARAM_LINEAR_SAMPLE
;
815 else if (location
== TGSI_INTERPOLATE_LOC_CENTROID
)
816 return SI_PARAM_LINEAR_CENTROID
;
818 return SI_PARAM_LINEAR_CENTER
;
820 case TGSI_INTERPOLATE_COLOR
:
821 case TGSI_INTERPOLATE_PERSPECTIVE
:
822 if (location
== TGSI_INTERPOLATE_LOC_SAMPLE
)
823 return SI_PARAM_PERSP_SAMPLE
;
824 else if (location
== TGSI_INTERPOLATE_LOC_CENTROID
)
825 return SI_PARAM_PERSP_CENTROID
;
827 return SI_PARAM_PERSP_CENTER
;
830 fprintf(stderr
, "Warning: Unhandled interpolation mode.\n");
835 /* This shouldn't be used by explicit INTERP opcodes. */
836 static LLVMValueRef
get_interp_param(struct si_shader_context
*si_shader_ctx
,
839 struct gallivm_state
*gallivm
= &si_shader_ctx
->radeon_bld
.gallivm
;
840 unsigned sample_param
= 0;
841 LLVMValueRef default_ij
, sample_ij
, force_sample
;
843 default_ij
= LLVMGetParam(si_shader_ctx
->radeon_bld
.main_fn
, param
);
845 /* If the shader doesn't use center/centroid, just return the parameter.
847 * If the shader only uses one set of (i,j), "si_emit_spi_ps_input" can
848 * switch between center/centroid and sample without shader changes.
851 case SI_PARAM_PERSP_CENTROID
:
852 case SI_PARAM_PERSP_CENTER
:
853 if (!si_shader_ctx
->shader
->selector
->forces_persample_interp_for_persp
)
856 sample_param
= SI_PARAM_PERSP_SAMPLE
;
859 case SI_PARAM_LINEAR_CENTROID
:
860 case SI_PARAM_LINEAR_CENTER
:
861 if (!si_shader_ctx
->shader
->selector
->forces_persample_interp_for_linear
)
864 sample_param
= SI_PARAM_LINEAR_SAMPLE
;
871 /* Otherwise, we have to select (i,j) based on a user data SGPR. */
872 sample_ij
= LLVMGetParam(si_shader_ctx
->radeon_bld
.main_fn
, sample_param
);
874 /* TODO: this can be done more efficiently by switching between
877 force_sample
= LLVMGetParam(si_shader_ctx
->radeon_bld
.main_fn
,
878 SI_PARAM_PS_STATE_BITS
);
879 force_sample
= LLVMBuildTrunc(gallivm
->builder
, force_sample
,
880 LLVMInt1TypeInContext(gallivm
->context
), "");
881 return LLVMBuildSelect(gallivm
->builder
, force_sample
,
882 sample_ij
, default_ij
, "");
885 static void declare_input_fs(
886 struct radeon_llvm_context
*radeon_bld
,
887 unsigned input_index
,
888 const struct tgsi_full_declaration
*decl
)
890 struct lp_build_context
*base
= &radeon_bld
->soa
.bld_base
.base
;
891 struct si_shader_context
*si_shader_ctx
=
892 si_shader_context(&radeon_bld
->soa
.bld_base
);
893 struct si_shader
*shader
= si_shader_ctx
->shader
;
894 struct lp_build_context
*uint
= &radeon_bld
->soa
.bld_base
.uint_bld
;
895 struct gallivm_state
*gallivm
= base
->gallivm
;
896 LLVMTypeRef input_type
= LLVMFloatTypeInContext(gallivm
->context
);
897 LLVMValueRef main_fn
= radeon_bld
->main_fn
;
899 LLVMValueRef interp_param
= NULL
;
900 int interp_param_idx
;
901 const char * intr_name
;
904 * [15:0] NewPrimMask (Bit mask for each quad. It is set it the
905 * quad begins a new primitive. Bit 0 always needs
907 * [32:16] ParamOffset
910 LLVMValueRef params
= LLVMGetParam(main_fn
, SI_PARAM_PRIM_MASK
);
911 LLVMValueRef attr_number
;
915 shader
->ps_input_param_offset
[input_index
] = shader
->nparam
++;
916 attr_number
= lp_build_const_int32(gallivm
,
917 shader
->ps_input_param_offset
[input_index
]);
919 shader
->ps_input_interpolate
[input_index
] = decl
->Interp
.Interpolate
;
920 interp_param_idx
= lookup_interp_param_index(decl
->Interp
.Interpolate
,
921 decl
->Interp
.Location
);
922 if (interp_param_idx
== -1)
924 else if (interp_param_idx
)
925 interp_param
= get_interp_param(si_shader_ctx
, interp_param_idx
);
927 /* fs.constant returns the param from the middle vertex, so it's not
928 * really useful for flat shading. It's meant to be used for custom
929 * interpolation (but the intrinsic can't fetch from the other two
932 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
933 * to do the right thing. The only reason we use fs.constant is that
934 * fs.interp cannot be used on integers, because they can be equal
937 intr_name
= interp_param
? "llvm.SI.fs.interp" : "llvm.SI.fs.constant";
939 if (decl
->Semantic
.Name
== TGSI_SEMANTIC_COLOR
&&
940 si_shader_ctx
->shader
->key
.ps
.color_two_side
) {
941 LLVMValueRef args
[4];
942 LLVMValueRef face
, is_face_positive
;
943 LLVMValueRef back_attr_number
=
944 lp_build_const_int32(gallivm
,
945 shader
->ps_input_param_offset
[input_index
] + 1);
947 face
= LLVMGetParam(main_fn
, SI_PARAM_FRONT_FACE
);
949 is_face_positive
= LLVMBuildICmp(gallivm
->builder
, LLVMIntNE
,
950 face
, uint
->zero
, "");
953 args
[3] = interp_param
;
954 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
955 LLVMValueRef llvm_chan
= lp_build_const_int32(gallivm
, chan
);
956 unsigned soa_index
= radeon_llvm_reg_index_soa(input_index
, chan
);
957 LLVMValueRef front
, back
;
960 args
[1] = attr_number
;
961 front
= lp_build_intrinsic(gallivm
->builder
, intr_name
,
962 input_type
, args
, args
[3] ? 4 : 3,
963 LLVMReadNoneAttribute
| LLVMNoUnwindAttribute
);
965 args
[1] = back_attr_number
;
966 back
= lp_build_intrinsic(gallivm
->builder
, intr_name
,
967 input_type
, args
, args
[3] ? 4 : 3,
968 LLVMReadNoneAttribute
| LLVMNoUnwindAttribute
);
970 radeon_bld
->inputs
[soa_index
] =
971 LLVMBuildSelect(gallivm
->builder
,
979 } else if (decl
->Semantic
.Name
== TGSI_SEMANTIC_FOG
) {
980 LLVMValueRef args
[4];
982 args
[0] = uint
->zero
;
983 args
[1] = attr_number
;
985 args
[3] = interp_param
;
986 radeon_bld
->inputs
[radeon_llvm_reg_index_soa(input_index
, 0)] =
987 lp_build_intrinsic(gallivm
->builder
, intr_name
,
988 input_type
, args
, args
[3] ? 4 : 3,
989 LLVMReadNoneAttribute
| LLVMNoUnwindAttribute
);
990 radeon_bld
->inputs
[radeon_llvm_reg_index_soa(input_index
, 1)] =
991 radeon_bld
->inputs
[radeon_llvm_reg_index_soa(input_index
, 2)] =
992 lp_build_const_float(gallivm
, 0.0f
);
993 radeon_bld
->inputs
[radeon_llvm_reg_index_soa(input_index
, 3)] =
994 lp_build_const_float(gallivm
, 1.0f
);
996 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
997 LLVMValueRef args
[4];
998 LLVMValueRef llvm_chan
= lp_build_const_int32(gallivm
, chan
);
999 unsigned soa_index
= radeon_llvm_reg_index_soa(input_index
, chan
);
1000 args
[0] = llvm_chan
;
1001 args
[1] = attr_number
;
1003 args
[3] = interp_param
;
1004 radeon_bld
->inputs
[soa_index
] =
1005 lp_build_intrinsic(gallivm
->builder
, intr_name
,
1006 input_type
, args
, args
[3] ? 4 : 3,
1007 LLVMReadNoneAttribute
| LLVMNoUnwindAttribute
);
1012 static LLVMValueRef
get_sample_id(struct radeon_llvm_context
*radeon_bld
)
1014 return unpack_param(si_shader_context(&radeon_bld
->soa
.bld_base
),
1015 SI_PARAM_ANCILLARY
, 8, 4);
1019 * Load a dword from a constant buffer.
1021 static LLVMValueRef
buffer_load_const(LLVMBuilderRef builder
, LLVMValueRef resource
,
1022 LLVMValueRef offset
, LLVMTypeRef return_type
)
1024 LLVMValueRef args
[2] = {resource
, offset
};
1026 return lp_build_intrinsic(builder
, "llvm.SI.load.const", return_type
, args
, 2,
1027 LLVMReadNoneAttribute
| LLVMNoUnwindAttribute
);
1030 static LLVMValueRef
load_sample_position(struct radeon_llvm_context
*radeon_bld
, LLVMValueRef sample_id
)
1032 struct si_shader_context
*si_shader_ctx
=
1033 si_shader_context(&radeon_bld
->soa
.bld_base
);
1034 struct lp_build_context
*uint_bld
= &radeon_bld
->soa
.bld_base
.uint_bld
;
1035 struct gallivm_state
*gallivm
= &radeon_bld
->gallivm
;
1036 LLVMBuilderRef builder
= gallivm
->builder
;
1037 LLVMValueRef desc
= LLVMGetParam(si_shader_ctx
->radeon_bld
.main_fn
, SI_PARAM_CONST_BUFFERS
);
1038 LLVMValueRef buf_index
= lp_build_const_int32(gallivm
, SI_DRIVER_STATE_CONST_BUF
);
1039 LLVMValueRef resource
= build_indexed_load_const(si_shader_ctx
, desc
, buf_index
);
1041 /* offset = sample_id * 8 (8 = 2 floats containing samplepos.xy) */
1042 LLVMValueRef offset0
= lp_build_mul_imm(uint_bld
, sample_id
, 8);
1043 LLVMValueRef offset1
= LLVMBuildAdd(builder
, offset0
, lp_build_const_int32(gallivm
, 4), "");
1045 LLVMValueRef pos
[4] = {
1046 buffer_load_const(builder
, resource
, offset0
, radeon_bld
->soa
.bld_base
.base
.elem_type
),
1047 buffer_load_const(builder
, resource
, offset1
, radeon_bld
->soa
.bld_base
.base
.elem_type
),
1048 lp_build_const_float(gallivm
, 0),
1049 lp_build_const_float(gallivm
, 0)
1052 return lp_build_gather_values(gallivm
, pos
, 4);
1055 static void declare_system_value(
1056 struct radeon_llvm_context
* radeon_bld
,
1058 const struct tgsi_full_declaration
*decl
)
1060 struct si_shader_context
*si_shader_ctx
=
1061 si_shader_context(&radeon_bld
->soa
.bld_base
);
1062 struct lp_build_context
*bld
= &radeon_bld
->soa
.bld_base
.base
;
1063 struct lp_build_context
*uint_bld
= &radeon_bld
->soa
.bld_base
.uint_bld
;
1064 struct gallivm_state
*gallivm
= &radeon_bld
->gallivm
;
1065 LLVMValueRef value
= 0;
1067 switch (decl
->Semantic
.Name
) {
1068 case TGSI_SEMANTIC_INSTANCEID
:
1069 value
= LLVMGetParam(radeon_bld
->main_fn
,
1070 si_shader_ctx
->param_instance_id
);
1073 case TGSI_SEMANTIC_VERTEXID
:
1074 value
= LLVMBuildAdd(gallivm
->builder
,
1075 LLVMGetParam(radeon_bld
->main_fn
,
1076 si_shader_ctx
->param_vertex_id
),
1077 LLVMGetParam(radeon_bld
->main_fn
,
1078 SI_PARAM_BASE_VERTEX
), "");
1081 case TGSI_SEMANTIC_VERTEXID_NOBASE
:
1082 value
= LLVMGetParam(radeon_bld
->main_fn
,
1083 si_shader_ctx
->param_vertex_id
);
1086 case TGSI_SEMANTIC_BASEVERTEX
:
1087 value
= LLVMGetParam(radeon_bld
->main_fn
,
1088 SI_PARAM_BASE_VERTEX
);
1091 case TGSI_SEMANTIC_INVOCATIONID
:
1092 if (si_shader_ctx
->type
== TGSI_PROCESSOR_TESS_CTRL
)
1093 value
= unpack_param(si_shader_ctx
, SI_PARAM_REL_IDS
, 8, 5);
1094 else if (si_shader_ctx
->type
== TGSI_PROCESSOR_GEOMETRY
)
1095 value
= LLVMGetParam(radeon_bld
->main_fn
,
1096 SI_PARAM_GS_INSTANCE_ID
);
1098 assert(!"INVOCATIONID not implemented");
1101 case TGSI_SEMANTIC_POSITION
:
1103 LLVMValueRef pos
[4] = {
1104 LLVMGetParam(radeon_bld
->main_fn
, SI_PARAM_POS_X_FLOAT
),
1105 LLVMGetParam(radeon_bld
->main_fn
, SI_PARAM_POS_Y_FLOAT
),
1106 LLVMGetParam(radeon_bld
->main_fn
, SI_PARAM_POS_Z_FLOAT
),
1107 lp_build_emit_llvm_unary(&radeon_bld
->soa
.bld_base
, TGSI_OPCODE_RCP
,
1108 LLVMGetParam(radeon_bld
->main_fn
,
1109 SI_PARAM_POS_W_FLOAT
)),
1111 value
= lp_build_gather_values(gallivm
, pos
, 4);
1115 case TGSI_SEMANTIC_FACE
:
1116 value
= LLVMGetParam(radeon_bld
->main_fn
, SI_PARAM_FRONT_FACE
);
1119 case TGSI_SEMANTIC_SAMPLEID
:
1120 value
= get_sample_id(radeon_bld
);
1123 case TGSI_SEMANTIC_SAMPLEPOS
: {
1124 LLVMValueRef pos
[4] = {
1125 LLVMGetParam(radeon_bld
->main_fn
, SI_PARAM_POS_X_FLOAT
),
1126 LLVMGetParam(radeon_bld
->main_fn
, SI_PARAM_POS_Y_FLOAT
),
1127 lp_build_const_float(gallivm
, 0),
1128 lp_build_const_float(gallivm
, 0)
1130 pos
[0] = lp_build_emit_llvm_unary(&radeon_bld
->soa
.bld_base
,
1131 TGSI_OPCODE_FRC
, pos
[0]);
1132 pos
[1] = lp_build_emit_llvm_unary(&radeon_bld
->soa
.bld_base
,
1133 TGSI_OPCODE_FRC
, pos
[1]);
1134 value
= lp_build_gather_values(gallivm
, pos
, 4);
1138 case TGSI_SEMANTIC_SAMPLEMASK
:
1139 /* Smoothing isn't MSAA in GL, but it's MSAA in hardware.
1140 * Therefore, force gl_SampleMaskIn to 1 for GL. */
1141 if (si_shader_ctx
->shader
->key
.ps
.poly_line_smoothing
)
1142 value
= uint_bld
->one
;
1144 value
= LLVMGetParam(radeon_bld
->main_fn
, SI_PARAM_SAMPLE_COVERAGE
);
1147 case TGSI_SEMANTIC_TESSCOORD
:
1149 LLVMValueRef coord
[4] = {
1150 LLVMGetParam(radeon_bld
->main_fn
, si_shader_ctx
->param_tes_u
),
1151 LLVMGetParam(radeon_bld
->main_fn
, si_shader_ctx
->param_tes_v
),
1156 /* For triangles, the vector should be (u, v, 1-u-v). */
1157 if (si_shader_ctx
->shader
->selector
->info
.properties
[TGSI_PROPERTY_TES_PRIM_MODE
] ==
1158 PIPE_PRIM_TRIANGLES
)
1159 coord
[2] = lp_build_sub(bld
, bld
->one
,
1160 lp_build_add(bld
, coord
[0], coord
[1]));
1162 value
= lp_build_gather_values(gallivm
, coord
, 4);
1166 case TGSI_SEMANTIC_VERTICESIN
:
1167 value
= unpack_param(si_shader_ctx
, SI_PARAM_TCS_OUT_LAYOUT
, 26, 6);
1170 case TGSI_SEMANTIC_TESSINNER
:
1171 case TGSI_SEMANTIC_TESSOUTER
:
1173 LLVMValueRef dw_addr
;
1174 int param
= si_shader_io_get_unique_index(decl
->Semantic
.Name
, 0);
1176 dw_addr
= get_tcs_out_current_patch_data_offset(si_shader_ctx
);
1177 dw_addr
= LLVMBuildAdd(gallivm
->builder
, dw_addr
,
1178 lp_build_const_int32(gallivm
, param
* 4), "");
1180 value
= lds_load(&radeon_bld
->soa
.bld_base
, TGSI_TYPE_FLOAT
,
1185 case TGSI_SEMANTIC_PRIMID
:
1186 value
= get_primitive_id(&radeon_bld
->soa
.bld_base
, 0);
1190 assert(!"unknown system value");
1194 radeon_bld
->system_values
[index
] = value
;
1197 static LLVMValueRef
fetch_constant(
1198 struct lp_build_tgsi_context
* bld_base
,
1199 const struct tgsi_full_src_register
*reg
,
1200 enum tgsi_opcode_type type
,
1203 struct si_shader_context
*si_shader_ctx
= si_shader_context(bld_base
);
1204 struct lp_build_context
* base
= &bld_base
->base
;
1205 const struct tgsi_ind_register
*ireg
= ®
->Indirect
;
1208 LLVMValueRef addr
, bufp
;
1209 LLVMValueRef result
;
1211 if (swizzle
== LP_CHAN_ALL
) {
1213 LLVMValueRef values
[4];
1214 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; ++chan
)
1215 values
[chan
] = fetch_constant(bld_base
, reg
, type
, chan
);
1217 return lp_build_gather_values(bld_base
->base
.gallivm
, values
, 4);
1220 buf
= reg
->Register
.Dimension
? reg
->Dimension
.Index
: 0;
1221 idx
= reg
->Register
.Index
* 4 + swizzle
;
1223 if (!reg
->Register
.Indirect
&& !reg
->Dimension
.Indirect
) {
1224 if (type
!= TGSI_TYPE_DOUBLE
)
1225 return bitcast(bld_base
, type
, si_shader_ctx
->constants
[buf
][idx
]);
1227 return radeon_llvm_emit_fetch_double(bld_base
,
1228 si_shader_ctx
->constants
[buf
][idx
],
1229 si_shader_ctx
->constants
[buf
][idx
+ 1]);
1233 if (reg
->Register
.Dimension
&& reg
->Dimension
.Indirect
) {
1234 LLVMValueRef ptr
= LLVMGetParam(si_shader_ctx
->radeon_bld
.main_fn
, SI_PARAM_CONST_BUFFERS
);
1236 index
= get_indirect_index(si_shader_ctx
, ®
->DimIndirect
,
1237 reg
->Dimension
.Index
);
1238 bufp
= build_indexed_load_const(si_shader_ctx
, ptr
, index
);
1240 bufp
= si_shader_ctx
->const_buffers
[buf
];
1242 addr
= si_shader_ctx
->radeon_bld
.soa
.addr
[ireg
->Index
][ireg
->Swizzle
];
1243 addr
= LLVMBuildLoad(base
->gallivm
->builder
, addr
, "load addr reg");
1244 addr
= lp_build_mul_imm(&bld_base
->uint_bld
, addr
, 16);
1245 addr
= lp_build_add(&bld_base
->uint_bld
, addr
,
1246 lp_build_const_int32(base
->gallivm
, idx
* 4));
1248 result
= buffer_load_const(base
->gallivm
->builder
, bufp
,
1249 addr
, bld_base
->base
.elem_type
);
1251 if (type
!= TGSI_TYPE_DOUBLE
)
1252 result
= bitcast(bld_base
, type
, result
);
1254 LLVMValueRef addr2
, result2
;
1255 addr2
= si_shader_ctx
->radeon_bld
.soa
.addr
[ireg
->Index
][ireg
->Swizzle
+ 1];
1256 addr2
= LLVMBuildLoad(base
->gallivm
->builder
, addr2
, "load addr reg2");
1257 addr2
= lp_build_mul_imm(&bld_base
->uint_bld
, addr2
, 16);
1258 addr2
= lp_build_add(&bld_base
->uint_bld
, addr2
,
1259 lp_build_const_int32(base
->gallivm
, idx
* 4));
1261 result2
= buffer_load_const(base
->gallivm
->builder
, si_shader_ctx
->const_buffers
[buf
],
1262 addr2
, bld_base
->base
.elem_type
);
1264 result
= radeon_llvm_emit_fetch_double(bld_base
,
1270 /* Upper 16 bits must be zero. */
1271 static LLVMValueRef
si_llvm_pack_two_int16(struct gallivm_state
*gallivm
,
1272 LLVMValueRef val
[2])
1274 return LLVMBuildOr(gallivm
->builder
, val
[0],
1275 LLVMBuildShl(gallivm
->builder
, val
[1],
1276 lp_build_const_int32(gallivm
, 16),
1280 /* Upper 16 bits are ignored and will be dropped. */
1281 static LLVMValueRef
si_llvm_pack_two_int32_as_int16(struct gallivm_state
*gallivm
,
1282 LLVMValueRef val
[2])
1284 LLVMValueRef v
[2] = {
1285 LLVMBuildAnd(gallivm
->builder
, val
[0],
1286 lp_build_const_int32(gallivm
, 0xffff), ""),
1289 return si_llvm_pack_two_int16(gallivm
, v
);
1292 /* Initialize arguments for the shader export intrinsic */
1293 static void si_llvm_init_export_args(struct lp_build_tgsi_context
*bld_base
,
1294 LLVMValueRef
*values
,
1298 struct si_shader_context
*si_shader_ctx
= si_shader_context(bld_base
);
1299 struct lp_build_context
*uint
=
1300 &si_shader_ctx
->radeon_bld
.soa
.bld_base
.uint_bld
;
1301 struct lp_build_context
*base
= &bld_base
->base
;
1302 struct gallivm_state
*gallivm
= base
->gallivm
;
1303 LLVMBuilderRef builder
= base
->gallivm
->builder
;
1304 LLVMValueRef val
[4];
1305 unsigned spi_shader_col_format
= V_028714_SPI_SHADER_32_ABGR
;
1309 /* Default is 0xf. Adjusted below depending on the format. */
1310 args
[0] = lp_build_const_int32(base
->gallivm
, 0xf); /* writemask */
1312 /* Specify whether the EXEC mask represents the valid mask */
1313 args
[1] = uint
->zero
;
1315 /* Specify whether this is the last export */
1316 args
[2] = uint
->zero
;
1318 /* Specify the target we are exporting */
1319 args
[3] = lp_build_const_int32(base
->gallivm
, target
);
1321 if (si_shader_ctx
->type
== TGSI_PROCESSOR_FRAGMENT
) {
1322 const union si_shader_key
*key
= &si_shader_ctx
->shader
->key
;
1323 unsigned col_formats
= key
->ps
.spi_shader_col_format
;
1324 int cbuf
= target
- V_008DFC_SQ_EXP_MRT
;
1326 assert(cbuf
>= 0 && cbuf
< 8);
1327 spi_shader_col_format
= (col_formats
>> (cbuf
* 4)) & 0xf;
1328 is_int8
= (key
->ps
.color_is_int8
>> cbuf
) & 0x1;
1331 args
[4] = uint
->zero
; /* COMPR flag */
1332 args
[5] = base
->undef
;
1333 args
[6] = base
->undef
;
1334 args
[7] = base
->undef
;
1335 args
[8] = base
->undef
;
1337 switch (spi_shader_col_format
) {
1338 case V_028714_SPI_SHADER_ZERO
:
1339 args
[0] = uint
->zero
; /* writemask */
1340 args
[3] = lp_build_const_int32(base
->gallivm
, V_008DFC_SQ_EXP_NULL
);
1343 case V_028714_SPI_SHADER_32_R
:
1344 args
[0] = uint
->one
; /* writemask */
1345 args
[5] = values
[0];
1348 case V_028714_SPI_SHADER_32_GR
:
1349 args
[0] = lp_build_const_int32(base
->gallivm
, 0x3); /* writemask */
1350 args
[5] = values
[0];
1351 args
[6] = values
[1];
1354 case V_028714_SPI_SHADER_32_AR
:
1355 args
[0] = lp_build_const_int32(base
->gallivm
, 0x9); /* writemask */
1356 args
[5] = values
[0];
1357 args
[8] = values
[3];
1360 case V_028714_SPI_SHADER_FP16_ABGR
:
1361 args
[4] = uint
->one
; /* COMPR flag */
1363 for (chan
= 0; chan
< 2; chan
++) {
1364 LLVMValueRef pack_args
[2] = {
1366 values
[2 * chan
+ 1]
1368 LLVMValueRef packed
;
1370 packed
= lp_build_intrinsic(base
->gallivm
->builder
,
1372 uint
->elem_type
, pack_args
, 2,
1373 LLVMReadNoneAttribute
| LLVMNoUnwindAttribute
);
1375 LLVMBuildBitCast(base
->gallivm
->builder
,
1376 packed
, base
->elem_type
, "");
1380 case V_028714_SPI_SHADER_UNORM16_ABGR
:
1381 for (chan
= 0; chan
< 4; chan
++) {
1382 val
[chan
] = radeon_llvm_saturate(bld_base
, values
[chan
]);
1383 val
[chan
] = LLVMBuildFMul(builder
, val
[chan
],
1384 lp_build_const_float(gallivm
, 65535), "");
1385 val
[chan
] = LLVMBuildFAdd(builder
, val
[chan
],
1386 lp_build_const_float(gallivm
, 0.5), "");
1387 val
[chan
] = LLVMBuildFPToUI(builder
, val
[chan
],
1388 uint
->elem_type
, "");
1391 args
[4] = uint
->one
; /* COMPR flag */
1392 args
[5] = bitcast(bld_base
, TGSI_TYPE_FLOAT
,
1393 si_llvm_pack_two_int16(gallivm
, val
));
1394 args
[6] = bitcast(bld_base
, TGSI_TYPE_FLOAT
,
1395 si_llvm_pack_two_int16(gallivm
, val
+2));
1398 case V_028714_SPI_SHADER_SNORM16_ABGR
:
1399 for (chan
= 0; chan
< 4; chan
++) {
1400 /* Clamp between [-1, 1]. */
1401 val
[chan
] = lp_build_emit_llvm_binary(bld_base
, TGSI_OPCODE_MIN
,
1403 lp_build_const_float(gallivm
, 1));
1404 val
[chan
] = lp_build_emit_llvm_binary(bld_base
, TGSI_OPCODE_MAX
,
1406 lp_build_const_float(gallivm
, -1));
1407 /* Convert to a signed integer in [-32767, 32767]. */
1408 val
[chan
] = LLVMBuildFMul(builder
, val
[chan
],
1409 lp_build_const_float(gallivm
, 32767), "");
1410 /* If positive, add 0.5, else add -0.5. */
1411 val
[chan
] = LLVMBuildFAdd(builder
, val
[chan
],
1412 LLVMBuildSelect(builder
,
1413 LLVMBuildFCmp(builder
, LLVMRealOGE
,
1414 val
[chan
], base
->zero
, ""),
1415 lp_build_const_float(gallivm
, 0.5),
1416 lp_build_const_float(gallivm
, -0.5), ""), "");
1417 val
[chan
] = LLVMBuildFPToSI(builder
, val
[chan
], uint
->elem_type
, "");
1420 args
[4] = uint
->one
; /* COMPR flag */
1421 args
[5] = bitcast(bld_base
, TGSI_TYPE_FLOAT
,
1422 si_llvm_pack_two_int32_as_int16(gallivm
, val
));
1423 args
[6] = bitcast(bld_base
, TGSI_TYPE_FLOAT
,
1424 si_llvm_pack_two_int32_as_int16(gallivm
, val
+2));
1427 case V_028714_SPI_SHADER_UINT16_ABGR
: {
1428 LLVMValueRef max
= lp_build_const_int32(gallivm
, is_int8
?
1431 for (chan
= 0; chan
< 4; chan
++) {
1432 val
[chan
] = bitcast(bld_base
, TGSI_TYPE_UNSIGNED
, values
[chan
]);
1433 val
[chan
] = lp_build_emit_llvm_binary(bld_base
, TGSI_OPCODE_UMIN
,
1437 args
[4] = uint
->one
; /* COMPR flag */
1438 args
[5] = bitcast(bld_base
, TGSI_TYPE_FLOAT
,
1439 si_llvm_pack_two_int16(gallivm
, val
));
1440 args
[6] = bitcast(bld_base
, TGSI_TYPE_FLOAT
,
1441 si_llvm_pack_two_int16(gallivm
, val
+2));
1445 case V_028714_SPI_SHADER_SINT16_ABGR
: {
1446 LLVMValueRef max
= lp_build_const_int32(gallivm
, is_int8
?
1448 LLVMValueRef min
= lp_build_const_int32(gallivm
, is_int8
?
1451 for (chan
= 0; chan
< 4; chan
++) {
1452 val
[chan
] = bitcast(bld_base
, TGSI_TYPE_UNSIGNED
, values
[chan
]);
1453 val
[chan
] = lp_build_emit_llvm_binary(bld_base
,
1456 val
[chan
] = lp_build_emit_llvm_binary(bld_base
,
1461 args
[4] = uint
->one
; /* COMPR flag */
1462 args
[5] = bitcast(bld_base
, TGSI_TYPE_FLOAT
,
1463 si_llvm_pack_two_int32_as_int16(gallivm
, val
));
1464 args
[6] = bitcast(bld_base
, TGSI_TYPE_FLOAT
,
1465 si_llvm_pack_two_int32_as_int16(gallivm
, val
+2));
1469 case V_028714_SPI_SHADER_32_ABGR
:
1470 memcpy(&args
[5], values
, sizeof(values
[0]) * 4);
1475 static void si_alpha_test(struct lp_build_tgsi_context
*bld_base
,
1478 struct si_shader_context
*si_shader_ctx
= si_shader_context(bld_base
);
1479 struct gallivm_state
*gallivm
= bld_base
->base
.gallivm
;
1481 if (si_shader_ctx
->shader
->key
.ps
.alpha_func
!= PIPE_FUNC_NEVER
) {
1482 LLVMValueRef alpha_ref
= LLVMGetParam(si_shader_ctx
->radeon_bld
.main_fn
,
1483 SI_PARAM_ALPHA_REF
);
1485 LLVMValueRef alpha_pass
=
1486 lp_build_cmp(&bld_base
->base
,
1487 si_shader_ctx
->shader
->key
.ps
.alpha_func
,
1490 lp_build_select(&bld_base
->base
,
1492 lp_build_const_float(gallivm
, 1.0f
),
1493 lp_build_const_float(gallivm
, -1.0f
));
1495 lp_build_intrinsic(gallivm
->builder
,
1497 LLVMVoidTypeInContext(gallivm
->context
),
1500 lp_build_intrinsic(gallivm
->builder
,
1502 LLVMVoidTypeInContext(gallivm
->context
),
1507 static LLVMValueRef
si_scale_alpha_by_sample_mask(struct lp_build_tgsi_context
*bld_base
,
1510 struct si_shader_context
*si_shader_ctx
= si_shader_context(bld_base
);
1511 struct gallivm_state
*gallivm
= bld_base
->base
.gallivm
;
1512 LLVMValueRef coverage
;
1514 /* alpha = alpha * popcount(coverage) / SI_NUM_SMOOTH_AA_SAMPLES */
1515 coverage
= LLVMGetParam(si_shader_ctx
->radeon_bld
.main_fn
,
1516 SI_PARAM_SAMPLE_COVERAGE
);
1517 coverage
= bitcast(bld_base
, TGSI_TYPE_SIGNED
, coverage
);
1519 coverage
= lp_build_intrinsic(gallivm
->builder
, "llvm.ctpop.i32",
1520 bld_base
->int_bld
.elem_type
,
1521 &coverage
, 1, LLVMReadNoneAttribute
);
1523 coverage
= LLVMBuildUIToFP(gallivm
->builder
, coverage
,
1524 bld_base
->base
.elem_type
, "");
1526 coverage
= LLVMBuildFMul(gallivm
->builder
, coverage
,
1527 lp_build_const_float(gallivm
,
1528 1.0 / SI_NUM_SMOOTH_AA_SAMPLES
), "");
1530 return LLVMBuildFMul(gallivm
->builder
, alpha
, coverage
, "");
1533 static void si_llvm_emit_clipvertex(struct lp_build_tgsi_context
* bld_base
,
1534 LLVMValueRef (*pos
)[9], LLVMValueRef
*out_elts
)
1536 struct si_shader_context
*si_shader_ctx
= si_shader_context(bld_base
);
1537 struct lp_build_context
*base
= &bld_base
->base
;
1538 struct lp_build_context
*uint
= &si_shader_ctx
->radeon_bld
.soa
.bld_base
.uint_bld
;
1541 unsigned const_chan
;
1542 LLVMValueRef base_elt
;
1543 LLVMValueRef ptr
= LLVMGetParam(si_shader_ctx
->radeon_bld
.main_fn
, SI_PARAM_CONST_BUFFERS
);
1544 LLVMValueRef constbuf_index
= lp_build_const_int32(base
->gallivm
, SI_DRIVER_STATE_CONST_BUF
);
1545 LLVMValueRef const_resource
= build_indexed_load_const(si_shader_ctx
, ptr
, constbuf_index
);
1547 for (reg_index
= 0; reg_index
< 2; reg_index
++) {
1548 LLVMValueRef
*args
= pos
[2 + reg_index
];
1553 args
[8] = lp_build_const_float(base
->gallivm
, 0.0f
);
1555 /* Compute dot products of position and user clip plane vectors */
1556 for (chan
= 0; chan
< TGSI_NUM_CHANNELS
; chan
++) {
1557 for (const_chan
= 0; const_chan
< TGSI_NUM_CHANNELS
; const_chan
++) {
1558 args
[1] = lp_build_const_int32(base
->gallivm
,
1559 ((reg_index
* 4 + chan
) * 4 +
1561 base_elt
= buffer_load_const(base
->gallivm
->builder
, const_resource
,
1562 args
[1], base
->elem_type
);
1564 lp_build_add(base
, args
[5 + chan
],
1565 lp_build_mul(base
, base_elt
,
1566 out_elts
[const_chan
]));
1570 args
[0] = lp_build_const_int32(base
->gallivm
, 0xf);
1571 args
[1] = uint
->zero
;
1572 args
[2] = uint
->zero
;
1573 args
[3] = lp_build_const_int32(base
->gallivm
,
1574 V_008DFC_SQ_EXP_POS
+ 2 + reg_index
);
1575 args
[4] = uint
->zero
;
1579 static void si_dump_streamout(struct pipe_stream_output_info
*so
)
1583 if (so
->num_outputs
)
1584 fprintf(stderr
, "STREAMOUT\n");
1586 for (i
= 0; i
< so
->num_outputs
; i
++) {
1587 unsigned mask
= ((1 << so
->output
[i
].num_components
) - 1) <<
1588 so
->output
[i
].start_component
;
1589 fprintf(stderr
, " %i: BUF%i[%i..%i] <- OUT[%i].%s%s%s%s\n",
1590 i
, so
->output
[i
].output_buffer
,
1591 so
->output
[i
].dst_offset
, so
->output
[i
].dst_offset
+ so
->output
[i
].num_components
- 1,
1592 so
->output
[i
].register_index
,
1593 mask
& 1 ? "x" : "",
1594 mask
& 2 ? "y" : "",
1595 mask
& 4 ? "z" : "",
1596 mask
& 8 ? "w" : "");
1600 /* TBUFFER_STORE_FORMAT_{X,XY,XYZ,XYZW} <- the suffix is selected by num_channels=1..4.
1601 * The type of vdata must be one of i32 (num_channels=1), v2i32 (num_channels=2),
1602 * or v4i32 (num_channels=3,4). */
1603 static void build_tbuffer_store(struct si_shader_context
*shader
,
1606 unsigned num_channels
,
1608 LLVMValueRef soffset
,
1609 unsigned inst_offset
,
1618 struct gallivm_state
*gallivm
= &shader
->radeon_bld
.gallivm
;
1619 LLVMTypeRef i32
= LLVMInt32TypeInContext(gallivm
->context
);
1620 LLVMValueRef args
[] = {
1623 LLVMConstInt(i32
, num_channels
, 0),
1626 LLVMConstInt(i32
, inst_offset
, 0),
1627 LLVMConstInt(i32
, dfmt
, 0),
1628 LLVMConstInt(i32
, nfmt
, 0),
1629 LLVMConstInt(i32
, offen
, 0),
1630 LLVMConstInt(i32
, idxen
, 0),
1631 LLVMConstInt(i32
, glc
, 0),
1632 LLVMConstInt(i32
, slc
, 0),
1633 LLVMConstInt(i32
, tfe
, 0)
1636 /* The instruction offset field has 12 bits */
1637 assert(offen
|| inst_offset
< (1 << 12));
1639 /* The intrinsic is overloaded, we need to add a type suffix for overloading to work. */
1640 unsigned func
= CLAMP(num_channels
, 1, 3) - 1;
1641 const char *types
[] = {"i32", "v2i32", "v4i32"};
1643 snprintf(name
, sizeof(name
), "llvm.SI.tbuffer.store.%s", types
[func
]);
1645 lp_build_intrinsic(gallivm
->builder
, name
,
1646 LLVMVoidTypeInContext(gallivm
->context
),
1647 args
, Elements(args
), 0);
1650 static void build_tbuffer_store_dwords(struct si_shader_context
*shader
,
1653 unsigned num_channels
,
1655 LLVMValueRef soffset
,
1656 unsigned inst_offset
)
1658 static unsigned dfmt
[] = {
1659 V_008F0C_BUF_DATA_FORMAT_32
,
1660 V_008F0C_BUF_DATA_FORMAT_32_32
,
1661 V_008F0C_BUF_DATA_FORMAT_32_32_32
,
1662 V_008F0C_BUF_DATA_FORMAT_32_32_32_32
1664 assert(num_channels
>= 1 && num_channels
<= 4);
1666 build_tbuffer_store(shader
, rsrc
, vdata
, num_channels
, vaddr
, soffset
,
1667 inst_offset
, dfmt
[num_channels
-1],
1668 V_008F0C_BUF_NUM_FORMAT_UINT
, 1, 0, 1, 1, 0);
1671 /* On SI, the vertex shader is responsible for writing streamout data
1673 static void si_llvm_emit_streamout(struct si_shader_context
*shader
,
1674 struct si_shader_output_values
*outputs
,
1677 struct pipe_stream_output_info
*so
= &shader
->shader
->selector
->so
;
1678 struct gallivm_state
*gallivm
= &shader
->radeon_bld
.gallivm
;
1679 LLVMBuilderRef builder
= gallivm
->builder
;
1681 struct lp_build_if_state if_ctx
;
1683 LLVMTypeRef i32
= LLVMInt32TypeInContext(gallivm
->context
);
1685 /* Get bits [22:16], i.e. (so_param >> 16) & 127; */
1686 LLVMValueRef so_vtx_count
=
1687 unpack_param(shader
, shader
->param_streamout_config
, 16, 7);
1689 LLVMValueRef tid
= lp_build_intrinsic(builder
, "llvm.SI.tid", i32
,
1690 NULL
, 0, LLVMReadNoneAttribute
);
1692 /* can_emit = tid < so_vtx_count; */
1693 LLVMValueRef can_emit
=
1694 LLVMBuildICmp(builder
, LLVMIntULT
, tid
, so_vtx_count
, "");
1696 LLVMValueRef stream_id
=
1697 unpack_param(shader
, shader
->param_streamout_config
, 24, 2);
1699 /* Emit the streamout code conditionally. This actually avoids
1700 * out-of-bounds buffer access. The hw tells us via the SGPR
1701 * (so_vtx_count) which threads are allowed to emit streamout data. */
1702 lp_build_if(&if_ctx
, gallivm
, can_emit
);
1704 /* The buffer offset is computed as follows:
1705 * ByteOffset = streamout_offset[buffer_id]*4 +
1706 * (streamout_write_index + thread_id)*stride[buffer_id] +
1710 LLVMValueRef so_write_index
=
1711 LLVMGetParam(shader
->radeon_bld
.main_fn
,
1712 shader
->param_streamout_write_index
);
1714 /* Compute (streamout_write_index + thread_id). */
1715 so_write_index
= LLVMBuildAdd(builder
, so_write_index
, tid
, "");
1717 /* Compute the write offset for each enabled buffer. */
1718 LLVMValueRef so_write_offset
[4] = {};
1719 for (i
= 0; i
< 4; i
++) {
1723 LLVMValueRef so_offset
= LLVMGetParam(shader
->radeon_bld
.main_fn
,
1724 shader
->param_streamout_offset
[i
]);
1725 so_offset
= LLVMBuildMul(builder
, so_offset
, LLVMConstInt(i32
, 4, 0), "");
1727 so_write_offset
[i
] = LLVMBuildMul(builder
, so_write_index
,
1728 LLVMConstInt(i32
, so
->stride
[i
]*4, 0), "");
1729 so_write_offset
[i
] = LLVMBuildAdd(builder
, so_write_offset
[i
], so_offset
, "");
1732 /* Write streamout data. */
1733 for (i
= 0; i
< so
->num_outputs
; i
++) {
1734 unsigned buf_idx
= so
->output
[i
].output_buffer
;
1735 unsigned reg
= so
->output
[i
].register_index
;
1736 unsigned start
= so
->output
[i
].start_component
;
1737 unsigned num_comps
= so
->output
[i
].num_components
;
1738 unsigned stream
= so
->output
[i
].stream
;
1739 LLVMValueRef out
[4];
1740 struct lp_build_if_state if_ctx_stream
;
1742 assert(num_comps
&& num_comps
<= 4);
1743 if (!num_comps
|| num_comps
> 4)
1749 /* Load the output as int. */
1750 for (j
= 0; j
< num_comps
; j
++) {
1751 out
[j
] = LLVMBuildBitCast(builder
,
1752 outputs
[reg
].values
[start
+j
],
1756 /* Pack the output. */
1757 LLVMValueRef vdata
= NULL
;
1759 switch (num_comps
) {
1760 case 1: /* as i32 */
1763 case 2: /* as v2i32 */
1764 case 3: /* as v4i32 (aligned to 4) */
1765 case 4: /* as v4i32 */
1766 vdata
= LLVMGetUndef(LLVMVectorType(i32
, util_next_power_of_two(num_comps
)));
1767 for (j
= 0; j
< num_comps
; j
++) {
1768 vdata
= LLVMBuildInsertElement(builder
, vdata
, out
[j
],
1769 LLVMConstInt(i32
, j
, 0), "");
1774 LLVMValueRef can_emit_stream
=
1775 LLVMBuildICmp(builder
, LLVMIntEQ
,
1777 lp_build_const_int32(gallivm
, stream
), "");
1779 lp_build_if(&if_ctx_stream
, gallivm
, can_emit_stream
);
1780 build_tbuffer_store_dwords(shader
, shader
->so_buffers
[buf_idx
],
1782 so_write_offset
[buf_idx
],
1783 LLVMConstInt(i32
, 0, 0),
1784 so
->output
[i
].dst_offset
*4);
1785 lp_build_endif(&if_ctx_stream
);
1788 lp_build_endif(&if_ctx
);
1792 /* Generate export instructions for hardware VS shader stage */
1793 static void si_llvm_export_vs(struct lp_build_tgsi_context
*bld_base
,
1794 struct si_shader_output_values
*outputs
,
1797 struct si_shader_context
* si_shader_ctx
= si_shader_context(bld_base
);
1798 struct si_shader
* shader
= si_shader_ctx
->shader
;
1799 struct lp_build_context
* base
= &bld_base
->base
;
1800 struct lp_build_context
* uint
=
1801 &si_shader_ctx
->radeon_bld
.soa
.bld_base
.uint_bld
;
1802 LLVMValueRef args
[9];
1803 LLVMValueRef pos_args
[4][9] = { { 0 } };
1804 LLVMValueRef psize_value
= NULL
, edgeflag_value
= NULL
, layer_value
= NULL
, viewport_index_value
= NULL
;
1805 unsigned semantic_name
, semantic_index
;
1807 unsigned param_count
= 0;
1811 if (outputs
&& si_shader_ctx
->shader
->selector
->so
.num_outputs
) {
1812 si_llvm_emit_streamout(si_shader_ctx
, outputs
, noutput
);
1815 for (i
= 0; i
< noutput
; i
++) {
1816 semantic_name
= outputs
[i
].name
;
1817 semantic_index
= outputs
[i
].sid
;
1820 /* Select the correct target */
1821 switch(semantic_name
) {
1822 case TGSI_SEMANTIC_PSIZE
:
1823 psize_value
= outputs
[i
].values
[0];
1825 case TGSI_SEMANTIC_EDGEFLAG
:
1826 edgeflag_value
= outputs
[i
].values
[0];
1828 case TGSI_SEMANTIC_LAYER
:
1829 layer_value
= outputs
[i
].values
[0];
1830 semantic_name
= TGSI_SEMANTIC_GENERIC
;
1831 goto handle_semantic
;
1832 case TGSI_SEMANTIC_VIEWPORT_INDEX
:
1833 viewport_index_value
= outputs
[i
].values
[0];
1834 semantic_name
= TGSI_SEMANTIC_GENERIC
;
1835 goto handle_semantic
;
1836 case TGSI_SEMANTIC_POSITION
:
1837 target
= V_008DFC_SQ_EXP_POS
;
1839 case TGSI_SEMANTIC_COLOR
:
1840 case TGSI_SEMANTIC_BCOLOR
:
1841 target
= V_008DFC_SQ_EXP_PARAM
+ param_count
;
1842 shader
->vs_output_param_offset
[i
] = param_count
;
1845 case TGSI_SEMANTIC_CLIPDIST
:
1846 target
= V_008DFC_SQ_EXP_POS
+ 2 + semantic_index
;
1848 case TGSI_SEMANTIC_CLIPVERTEX
:
1849 si_llvm_emit_clipvertex(bld_base
, pos_args
, outputs
[i
].values
);
1851 case TGSI_SEMANTIC_PRIMID
:
1852 case TGSI_SEMANTIC_FOG
:
1853 case TGSI_SEMANTIC_TEXCOORD
:
1854 case TGSI_SEMANTIC_GENERIC
:
1855 target
= V_008DFC_SQ_EXP_PARAM
+ param_count
;
1856 shader
->vs_output_param_offset
[i
] = param_count
;
1862 "Warning: SI unhandled vs output type:%d\n",
1866 si_llvm_init_export_args(bld_base
, outputs
[i
].values
, target
, args
);
1868 if (target
>= V_008DFC_SQ_EXP_POS
&&
1869 target
<= (V_008DFC_SQ_EXP_POS
+ 3)) {
1870 memcpy(pos_args
[target
- V_008DFC_SQ_EXP_POS
],
1871 args
, sizeof(args
));
1873 lp_build_intrinsic(base
->gallivm
->builder
,
1875 LLVMVoidTypeInContext(base
->gallivm
->context
),
1879 if (semantic_name
== TGSI_SEMANTIC_CLIPDIST
) {
1880 semantic_name
= TGSI_SEMANTIC_GENERIC
;
1881 goto handle_semantic
;
1885 shader
->nr_param_exports
= param_count
;
1887 /* We need to add the position output manually if it's missing. */
1888 if (!pos_args
[0][0]) {
1889 pos_args
[0][0] = lp_build_const_int32(base
->gallivm
, 0xf); /* writemask */
1890 pos_args
[0][1] = uint
->zero
; /* EXEC mask */
1891 pos_args
[0][2] = uint
->zero
; /* last export? */
1892 pos_args
[0][3] = lp_build_const_int32(base
->gallivm
, V_008DFC_SQ_EXP_POS
);
1893 pos_args
[0][4] = uint
->zero
; /* COMPR flag */
1894 pos_args
[0][5] = base
->zero
; /* X */
1895 pos_args
[0][6] = base
->zero
; /* Y */
1896 pos_args
[0][7] = base
->zero
; /* Z */
1897 pos_args
[0][8] = base
->one
; /* W */
1900 /* Write the misc vector (point size, edgeflag, layer, viewport). */
1901 if (shader
->selector
->info
.writes_psize
||
1902 shader
->selector
->info
.writes_edgeflag
||
1903 shader
->selector
->info
.writes_viewport_index
||
1904 shader
->selector
->info
.writes_layer
) {
1905 pos_args
[1][0] = lp_build_const_int32(base
->gallivm
, /* writemask */
1906 shader
->selector
->info
.writes_psize
|
1907 (shader
->selector
->info
.writes_edgeflag
<< 1) |
1908 (shader
->selector
->info
.writes_layer
<< 2) |
1909 (shader
->selector
->info
.writes_viewport_index
<< 3));
1910 pos_args
[1][1] = uint
->zero
; /* EXEC mask */
1911 pos_args
[1][2] = uint
->zero
; /* last export? */
1912 pos_args
[1][3] = lp_build_const_int32(base
->gallivm
, V_008DFC_SQ_EXP_POS
+ 1);
1913 pos_args
[1][4] = uint
->zero
; /* COMPR flag */
1914 pos_args
[1][5] = base
->zero
; /* X */
1915 pos_args
[1][6] = base
->zero
; /* Y */
1916 pos_args
[1][7] = base
->zero
; /* Z */
1917 pos_args
[1][8] = base
->zero
; /* W */
1919 if (shader
->selector
->info
.writes_psize
)
1920 pos_args
[1][5] = psize_value
;
1922 if (shader
->selector
->info
.writes_edgeflag
) {
1923 /* The output is a float, but the hw expects an integer
1924 * with the first bit containing the edge flag. */
1925 edgeflag_value
= LLVMBuildFPToUI(base
->gallivm
->builder
,
1927 bld_base
->uint_bld
.elem_type
, "");
1928 edgeflag_value
= lp_build_min(&bld_base
->int_bld
,
1930 bld_base
->int_bld
.one
);
1932 /* The LLVM intrinsic expects a float. */
1933 pos_args
[1][6] = LLVMBuildBitCast(base
->gallivm
->builder
,
1935 base
->elem_type
, "");
1938 if (shader
->selector
->info
.writes_layer
)
1939 pos_args
[1][7] = layer_value
;
1941 if (shader
->selector
->info
.writes_viewport_index
)
1942 pos_args
[1][8] = viewport_index_value
;
1945 for (i
= 0; i
< 4; i
++)
1947 shader
->nr_pos_exports
++;
1950 for (i
= 0; i
< 4; i
++) {
1951 if (!pos_args
[i
][0])
1954 /* Specify the target we are exporting */
1955 pos_args
[i
][3] = lp_build_const_int32(base
->gallivm
, V_008DFC_SQ_EXP_POS
+ pos_idx
++);
1957 if (pos_idx
== shader
->nr_pos_exports
)
1958 /* Specify that this is the last export */
1959 pos_args
[i
][2] = uint
->one
;
1961 lp_build_intrinsic(base
->gallivm
->builder
,
1963 LLVMVoidTypeInContext(base
->gallivm
->context
),
1968 /* This only writes the tessellation factor levels. */
1969 static void si_llvm_emit_tcs_epilogue(struct lp_build_tgsi_context
*bld_base
)
1971 struct si_shader_context
*si_shader_ctx
= si_shader_context(bld_base
);
1972 struct gallivm_state
*gallivm
= bld_base
->base
.gallivm
;
1973 struct si_shader
*shader
= si_shader_ctx
->shader
;
1974 unsigned tess_inner_index
, tess_outer_index
;
1975 LLVMValueRef lds_base
, lds_inner
, lds_outer
;
1976 LLVMValueRef tf_base
, rel_patch_id
, byteoffset
, buffer
, rw_buffers
;
1977 LLVMValueRef out
[6], vec0
, vec1
, invocation_id
;
1978 unsigned stride
, outer_comps
, inner_comps
, i
;
1979 struct lp_build_if_state if_ctx
;
1981 invocation_id
= unpack_param(si_shader_ctx
, SI_PARAM_REL_IDS
, 8, 5);
1983 /* Do this only for invocation 0, because the tess levels are per-patch,
1986 * This can't jump, because invocation 0 executes this. It should
1987 * at least mask out the loads and stores for other invocations.
1989 lp_build_if(&if_ctx
, gallivm
,
1990 LLVMBuildICmp(gallivm
->builder
, LLVMIntEQ
,
1991 invocation_id
, bld_base
->uint_bld
.zero
, ""));
1993 /* Determine the layout of one tess factor element in the buffer. */
1994 switch (shader
->key
.tcs
.prim_mode
) {
1995 case PIPE_PRIM_LINES
:
1996 stride
= 2; /* 2 dwords, 1 vec2 store */
2000 case PIPE_PRIM_TRIANGLES
:
2001 stride
= 4; /* 4 dwords, 1 vec4 store */
2005 case PIPE_PRIM_QUADS
:
2006 stride
= 6; /* 6 dwords, 2 stores (vec4 + vec2) */
2015 /* Load tess_inner and tess_outer from LDS.
2016 * Any invocation can write them, so we can't get them from a temporary.
2018 tess_inner_index
= si_shader_io_get_unique_index(TGSI_SEMANTIC_TESSINNER
, 0);
2019 tess_outer_index
= si_shader_io_get_unique_index(TGSI_SEMANTIC_TESSOUTER
, 0);
2021 lds_base
= get_tcs_out_current_patch_data_offset(si_shader_ctx
);
2022 lds_inner
= LLVMBuildAdd(gallivm
->builder
, lds_base
,
2023 lp_build_const_int32(gallivm
,
2024 tess_inner_index
* 4), "");
2025 lds_outer
= LLVMBuildAdd(gallivm
->builder
, lds_base
,
2026 lp_build_const_int32(gallivm
,
2027 tess_outer_index
* 4), "");
2029 for (i
= 0; i
< outer_comps
; i
++)
2030 out
[i
] = lds_load(bld_base
, TGSI_TYPE_SIGNED
, i
, lds_outer
);
2031 for (i
= 0; i
< inner_comps
; i
++)
2032 out
[outer_comps
+i
] = lds_load(bld_base
, TGSI_TYPE_SIGNED
, i
, lds_inner
);
2034 /* Convert the outputs to vectors for stores. */
2035 vec0
= lp_build_gather_values(gallivm
, out
, MIN2(stride
, 4));
2039 vec1
= lp_build_gather_values(gallivm
, out
+4, stride
- 4);
2041 /* Get the buffer. */
2042 rw_buffers
= LLVMGetParam(si_shader_ctx
->radeon_bld
.main_fn
,
2043 SI_PARAM_RW_BUFFERS
);
2044 buffer
= build_indexed_load_const(si_shader_ctx
, rw_buffers
,
2045 lp_build_const_int32(gallivm
, SI_RING_TESS_FACTOR
));
2047 /* Get the offset. */
2048 tf_base
= LLVMGetParam(si_shader_ctx
->radeon_bld
.main_fn
,
2049 SI_PARAM_TESS_FACTOR_OFFSET
);
2050 rel_patch_id
= get_rel_patch_id(si_shader_ctx
);
2051 byteoffset
= LLVMBuildMul(gallivm
->builder
, rel_patch_id
,
2052 lp_build_const_int32(gallivm
, 4 * stride
), "");
2054 /* Store the outputs. */
2055 build_tbuffer_store_dwords(si_shader_ctx
, buffer
, vec0
,
2056 MIN2(stride
, 4), byteoffset
, tf_base
, 0);
2058 build_tbuffer_store_dwords(si_shader_ctx
, buffer
, vec1
,
2059 stride
- 4, byteoffset
, tf_base
, 16);
2060 lp_build_endif(&if_ctx
);
2063 static void si_llvm_emit_ls_epilogue(struct lp_build_tgsi_context
* bld_base
)
2065 struct si_shader_context
*si_shader_ctx
= si_shader_context(bld_base
);
2066 struct si_shader
*shader
= si_shader_ctx
->shader
;
2067 struct tgsi_shader_info
*info
= &shader
->selector
->info
;
2068 struct gallivm_state
*gallivm
= bld_base
->base
.gallivm
;
2070 LLVMValueRef vertex_id
= LLVMGetParam(si_shader_ctx
->radeon_bld
.main_fn
,
2071 si_shader_ctx
->param_rel_auto_id
);
2072 LLVMValueRef vertex_dw_stride
=
2073 unpack_param(si_shader_ctx
, SI_PARAM_LS_OUT_LAYOUT
, 13, 8);
2074 LLVMValueRef base_dw_addr
= LLVMBuildMul(gallivm
->builder
, vertex_id
,
2075 vertex_dw_stride
, "");
2077 /* Write outputs to LDS. The next shader (TCS aka HS) will read
2078 * its inputs from it. */
2079 for (i
= 0; i
< info
->num_outputs
; i
++) {
2080 LLVMValueRef
*out_ptr
= si_shader_ctx
->radeon_bld
.soa
.outputs
[i
];
2081 unsigned name
= info
->output_semantic_name
[i
];
2082 unsigned index
= info
->output_semantic_index
[i
];
2083 int param
= si_shader_io_get_unique_index(name
, index
);
2084 LLVMValueRef dw_addr
= LLVMBuildAdd(gallivm
->builder
, base_dw_addr
,
2085 lp_build_const_int32(gallivm
, param
* 4), "");
2087 for (chan
= 0; chan
< 4; chan
++) {
2088 lds_store(bld_base
, chan
, dw_addr
,
2089 LLVMBuildLoad(gallivm
->builder
, out_ptr
[chan
], ""));
2094 static void si_llvm_emit_es_epilogue(struct lp_build_tgsi_context
* bld_base
)
2096 struct si_shader_context
*si_shader_ctx
= si_shader_context(bld_base
);
2097 struct gallivm_state
*gallivm
= bld_base
->base
.gallivm
;
2098 struct si_shader
*es
= si_shader_ctx
->shader
;
2099 struct tgsi_shader_info
*info
= &es
->selector
->info
;
2100 LLVMTypeRef i32
= LLVMInt32TypeInContext(gallivm
->context
);
2101 LLVMValueRef soffset
= LLVMGetParam(si_shader_ctx
->radeon_bld
.main_fn
,
2102 si_shader_ctx
->param_es2gs_offset
);
2106 for (i
= 0; i
< info
->num_outputs
; i
++) {
2107 LLVMValueRef
*out_ptr
=
2108 si_shader_ctx
->radeon_bld
.soa
.outputs
[i
];
2111 if (info
->output_semantic_name
[i
] == TGSI_SEMANTIC_VIEWPORT_INDEX
||
2112 info
->output_semantic_name
[i
] == TGSI_SEMANTIC_LAYER
)
2115 param_index
= si_shader_io_get_unique_index(info
->output_semantic_name
[i
],
2116 info
->output_semantic_index
[i
]);
2118 for (chan
= 0; chan
< 4; chan
++) {
2119 LLVMValueRef out_val
= LLVMBuildLoad(gallivm
->builder
, out_ptr
[chan
], "");
2120 out_val
= LLVMBuildBitCast(gallivm
->builder
, out_val
, i32
, "");
2122 build_tbuffer_store(si_shader_ctx
,
2123 si_shader_ctx
->esgs_ring
,
2125 LLVMGetUndef(i32
), soffset
,
2126 (4 * param_index
+ chan
) * 4,
2127 V_008F0C_BUF_DATA_FORMAT_32
,
2128 V_008F0C_BUF_NUM_FORMAT_UINT
,
2134 static void si_llvm_emit_gs_epilogue(struct lp_build_tgsi_context
*bld_base
)
2136 struct si_shader_context
*si_shader_ctx
= si_shader_context(bld_base
);
2137 struct gallivm_state
*gallivm
= bld_base
->base
.gallivm
;
2138 LLVMValueRef args
[2];
2140 args
[0] = lp_build_const_int32(gallivm
, SENDMSG_GS_OP_NOP
| SENDMSG_GS_DONE
);
2141 args
[1] = LLVMGetParam(si_shader_ctx
->radeon_bld
.main_fn
, SI_PARAM_GS_WAVE_ID
);
2142 lp_build_intrinsic(gallivm
->builder
, "llvm.SI.sendmsg",
2143 LLVMVoidTypeInContext(gallivm
->context
), args
, 2,
2144 LLVMNoUnwindAttribute
);
2147 static void si_llvm_emit_vs_epilogue(struct lp_build_tgsi_context
* bld_base
)
2149 struct si_shader_context
*si_shader_ctx
= si_shader_context(bld_base
);
2150 struct gallivm_state
*gallivm
= bld_base
->base
.gallivm
;
2151 struct tgsi_shader_info
*info
= &si_shader_ctx
->shader
->selector
->info
;
2152 struct si_shader_output_values
*outputs
= NULL
;
2155 outputs
= MALLOC((info
->num_outputs
+ 1) * sizeof(outputs
[0]));
2157 /* Vertex color clamping.
2159 * This uses a state constant loaded in a user data SGPR and
2160 * an IF statement is added that clamps all colors if the constant
2163 if (si_shader_ctx
->type
== TGSI_PROCESSOR_VERTEX
&&
2164 !si_shader_ctx
->is_gs_copy_shader
) {
2165 struct lp_build_if_state if_ctx
;
2166 LLVMValueRef cond
= NULL
;
2167 LLVMValueRef addr
, val
;
2169 for (i
= 0; i
< info
->num_outputs
; i
++) {
2170 if (info
->output_semantic_name
[i
] != TGSI_SEMANTIC_COLOR
&&
2171 info
->output_semantic_name
[i
] != TGSI_SEMANTIC_BCOLOR
)
2174 /* We've found a color. */
2176 /* The state is in the first bit of the user SGPR. */
2177 cond
= LLVMGetParam(si_shader_ctx
->radeon_bld
.main_fn
,
2178 SI_PARAM_VS_STATE_BITS
);
2179 cond
= LLVMBuildTrunc(gallivm
->builder
, cond
,
2180 LLVMInt1TypeInContext(gallivm
->context
), "");
2181 lp_build_if(&if_ctx
, gallivm
, cond
);
2184 for (j
= 0; j
< 4; j
++) {
2185 addr
= si_shader_ctx
->radeon_bld
.soa
.outputs
[i
][j
];
2186 val
= LLVMBuildLoad(gallivm
->builder
, addr
, "");
2187 val
= radeon_llvm_saturate(bld_base
, val
);
2188 LLVMBuildStore(gallivm
->builder
, val
, addr
);
2193 lp_build_endif(&if_ctx
);
2196 for (i
= 0; i
< info
->num_outputs
; i
++) {
2197 outputs
[i
].name
= info
->output_semantic_name
[i
];
2198 outputs
[i
].sid
= info
->output_semantic_index
[i
];
2200 for (j
= 0; j
< 4; j
++)
2201 outputs
[i
].values
[j
] =
2202 LLVMBuildLoad(gallivm
->builder
,
2203 si_shader_ctx
->radeon_bld
.soa
.outputs
[i
][j
],
2207 /* Export PrimitiveID when PS needs it. */
2208 if (si_vs_exports_prim_id(si_shader_ctx
->shader
)) {
2209 outputs
[i
].name
= TGSI_SEMANTIC_PRIMID
;
2211 outputs
[i
].values
[0] = bitcast(bld_base
, TGSI_TYPE_FLOAT
,
2212 get_primitive_id(bld_base
, 0));
2213 outputs
[i
].values
[1] = bld_base
->base
.undef
;
2214 outputs
[i
].values
[2] = bld_base
->base
.undef
;
2215 outputs
[i
].values
[3] = bld_base
->base
.undef
;
2219 si_llvm_export_vs(bld_base
, outputs
, i
);
2223 static void si_export_mrt_z(struct lp_build_tgsi_context
*bld_base
,
2224 LLVMValueRef depth
, LLVMValueRef stencil
,
2225 LLVMValueRef samplemask
)
2227 struct si_screen
*sscreen
= si_shader_context(bld_base
)->screen
;
2228 struct lp_build_context
*base
= &bld_base
->base
;
2229 struct lp_build_context
*uint
= &bld_base
->uint_bld
;
2230 LLVMValueRef args
[9];
2233 assert(depth
|| stencil
|| samplemask
);
2235 args
[1] = uint
->one
; /* whether the EXEC mask is valid */
2236 args
[2] = uint
->one
; /* DONE bit */
2238 /* Specify the target we are exporting */
2239 args
[3] = lp_build_const_int32(base
->gallivm
, V_008DFC_SQ_EXP_MRTZ
);
2241 args
[4] = uint
->zero
; /* COMP flag */
2242 args
[5] = base
->undef
; /* R, depth */
2243 args
[6] = base
->undef
; /* G, stencil test value[0:7], stencil op value[8:15] */
2244 args
[7] = base
->undef
; /* B, sample mask */
2245 args
[8] = base
->undef
; /* A, alpha to mask */
2258 args
[7] = samplemask
;
2262 /* SI (except OLAND) has a bug that it only looks
2263 * at the X writemask component. */
2264 if (sscreen
->b
.chip_class
== SI
&&
2265 sscreen
->b
.family
!= CHIP_OLAND
)
2268 /* Specify which components to enable */
2269 args
[0] = lp_build_const_int32(base
->gallivm
, mask
);
2271 lp_build_intrinsic(base
->gallivm
->builder
, "llvm.SI.export",
2272 LLVMVoidTypeInContext(base
->gallivm
->context
),
2276 static void si_export_mrt_color(struct lp_build_tgsi_context
*bld_base
,
2277 LLVMValueRef
*color
, unsigned index
,
2280 struct si_shader_context
*si_shader_ctx
= si_shader_context(bld_base
);
2281 struct lp_build_context
*base
= &bld_base
->base
;
2282 LLVMValueRef args
[9];
2286 if (si_shader_ctx
->shader
->key
.ps
.clamp_color
)
2287 for (i
= 0; i
< 4; i
++)
2288 color
[i
] = radeon_llvm_saturate(bld_base
, color
[i
]);
2291 if (si_shader_ctx
->shader
->key
.ps
.alpha_to_one
)
2292 color
[3] = base
->one
;
2296 si_shader_ctx
->shader
->key
.ps
.alpha_func
!= PIPE_FUNC_ALWAYS
)
2297 si_alpha_test(bld_base
, color
[3]);
2299 /* Line & polygon smoothing */
2300 if (si_shader_ctx
->shader
->key
.ps
.poly_line_smoothing
)
2301 color
[3] = si_scale_alpha_by_sample_mask(bld_base
, color
[3]);
2303 /* If last_cbuf > 0, FS_COLOR0_WRITES_ALL_CBUFS is true. */
2305 si_shader_ctx
->shader
->key
.ps
.last_cbuf
> 0) {
2306 for (int c
= 1; c
<= si_shader_ctx
->shader
->key
.ps
.last_cbuf
; c
++) {
2307 si_llvm_init_export_args(bld_base
, color
,
2308 V_008DFC_SQ_EXP_MRT
+ c
, args
);
2309 lp_build_intrinsic(base
->gallivm
->builder
, "llvm.SI.export",
2310 LLVMVoidTypeInContext(base
->gallivm
->context
),
2316 si_llvm_init_export_args(bld_base
, color
, V_008DFC_SQ_EXP_MRT
+ index
,
2319 args
[1] = bld_base
->uint_bld
.one
; /* whether the EXEC mask is valid */
2320 args
[2] = bld_base
->uint_bld
.one
; /* DONE bit */
2322 lp_build_intrinsic(base
->gallivm
->builder
, "llvm.SI.export",
2323 LLVMVoidTypeInContext(base
->gallivm
->context
),
2327 static void si_export_null(struct lp_build_tgsi_context
*bld_base
)
2329 struct lp_build_context
*base
= &bld_base
->base
;
2330 struct lp_build_context
*uint
= &bld_base
->uint_bld
;
2331 LLVMValueRef args
[9];
2333 args
[0] = lp_build_const_int32(base
->gallivm
, 0x0); /* enabled channels */
2334 args
[1] = uint
->one
; /* whether the EXEC mask is valid */
2335 args
[2] = uint
->one
; /* DONE bit */
2336 args
[3] = lp_build_const_int32(base
->gallivm
, V_008DFC_SQ_EXP_NULL
);
2337 args
[4] = uint
->zero
; /* COMPR flag (0 = 32-bit export) */
2338 args
[5] = uint
->undef
; /* R */
2339 args
[6] = uint
->undef
; /* G */
2340 args
[7] = uint
->undef
; /* B */
2341 args
[8] = uint
->undef
; /* A */
2343 lp_build_intrinsic(base
->gallivm
->builder
, "llvm.SI.export",
2344 LLVMVoidTypeInContext(base
->gallivm
->context
),
2348 static void si_llvm_emit_fs_epilogue(struct lp_build_tgsi_context
* bld_base
)
2350 struct si_shader_context
* si_shader_ctx
= si_shader_context(bld_base
);
2351 struct si_shader
* shader
= si_shader_ctx
->shader
;
2352 struct lp_build_context
* base
= &bld_base
->base
;
2353 struct tgsi_shader_info
*info
= &shader
->selector
->info
;
2354 LLVMBuilderRef builder
= base
->gallivm
->builder
;
2355 LLVMValueRef depth
= NULL
, stencil
= NULL
, samplemask
= NULL
;
2356 int last_color_export
= -1;
2359 /* If there are no outputs, add a dummy export. */
2360 if (!info
->num_outputs
) {
2361 si_export_null(bld_base
);
2365 /* Determine the last export. If MRTZ is present, it's always last.
2366 * Otherwise, find the last color export.
2368 if (!info
->writes_z
&& !info
->writes_stencil
&& !info
->writes_samplemask
)
2369 for (i
= 0; i
< info
->num_outputs
; i
++)
2370 if (info
->output_semantic_name
[i
] == TGSI_SEMANTIC_COLOR
)
2371 last_color_export
= i
;
2373 for (i
= 0; i
< info
->num_outputs
; i
++) {
2374 unsigned semantic_name
= info
->output_semantic_name
[i
];
2375 unsigned semantic_index
= info
->output_semantic_index
[i
];
2377 LLVMValueRef color
[4] = {};
2379 /* Select the correct target */
2380 switch (semantic_name
) {
2381 case TGSI_SEMANTIC_POSITION
:
2382 depth
= LLVMBuildLoad(builder
,
2383 si_shader_ctx
->radeon_bld
.soa
.outputs
[i
][2], "");
2385 case TGSI_SEMANTIC_STENCIL
:
2386 stencil
= LLVMBuildLoad(builder
,
2387 si_shader_ctx
->radeon_bld
.soa
.outputs
[i
][1], "");
2389 case TGSI_SEMANTIC_SAMPLEMASK
:
2390 samplemask
= LLVMBuildLoad(builder
,
2391 si_shader_ctx
->radeon_bld
.soa
.outputs
[i
][0], "");
2393 case TGSI_SEMANTIC_COLOR
:
2394 for (j
= 0; j
< 4; j
++)
2395 color
[j
] = LLVMBuildLoad(builder
,
2396 si_shader_ctx
->radeon_bld
.soa
.outputs
[i
][j
], "");
2398 si_export_mrt_color(bld_base
, color
, semantic_index
,
2399 last_color_export
== i
);
2403 "Warning: SI unhandled fs output type:%d\n",
2408 if (depth
|| stencil
|| samplemask
)
2409 si_export_mrt_z(bld_base
, depth
, stencil
, samplemask
);
2412 static void build_tex_intrinsic(const struct lp_build_tgsi_action
* action
,
2413 struct lp_build_tgsi_context
* bld_base
,
2414 struct lp_build_emit_data
* emit_data
);
2416 static bool tgsi_is_array_sampler(unsigned target
)
2418 return target
== TGSI_TEXTURE_1D_ARRAY
||
2419 target
== TGSI_TEXTURE_SHADOW1D_ARRAY
||
2420 target
== TGSI_TEXTURE_2D_ARRAY
||
2421 target
== TGSI_TEXTURE_SHADOW2D_ARRAY
||
2422 target
== TGSI_TEXTURE_CUBE_ARRAY
||
2423 target
== TGSI_TEXTURE_SHADOWCUBE_ARRAY
||
2424 target
== TGSI_TEXTURE_2D_ARRAY_MSAA
;
2427 static void set_tex_fetch_args(struct gallivm_state
*gallivm
,
2428 struct lp_build_emit_data
*emit_data
,
2429 unsigned opcode
, unsigned target
,
2430 LLVMValueRef res_ptr
, LLVMValueRef samp_ptr
,
2431 LLVMValueRef
*param
, unsigned count
,
2435 unsigned is_rect
= target
== TGSI_TEXTURE_RECT
;
2436 LLVMTypeRef i32
= LLVMInt32TypeInContext(gallivm
->context
);
2438 /* Pad to power of two vector */
2439 while (count
< util_next_power_of_two(count
))
2440 param
[count
++] = LLVMGetUndef(i32
);
2442 /* Texture coordinates. */
2444 emit_data
->args
[0] = lp_build_gather_values(gallivm
, param
, count
);
2446 emit_data
->args
[0] = param
[0];
2449 emit_data
->args
[1] = res_ptr
;
2452 if (opcode
== TGSI_OPCODE_TXF
|| opcode
== TGSI_OPCODE_TXQ
)
2453 emit_data
->dst_type
= LLVMVectorType(i32
, 4);
2455 emit_data
->dst_type
= LLVMVectorType(
2456 LLVMFloatTypeInContext(gallivm
->context
), 4);
2458 emit_data
->args
[num_args
++] = samp_ptr
;
2461 emit_data
->args
[num_args
++] = lp_build_const_int32(gallivm
, dmask
);
2462 emit_data
->args
[num_args
++] = lp_build_const_int32(gallivm
, is_rect
); /* unorm */
2463 emit_data
->args
[num_args
++] = lp_build_const_int32(gallivm
, 0); /* r128 */
2464 emit_data
->args
[num_args
++] = lp_build_const_int32(gallivm
,
2465 tgsi_is_array_sampler(target
)); /* da */
2466 emit_data
->args
[num_args
++] = lp_build_const_int32(gallivm
, 0); /* glc */
2467 emit_data
->args
[num_args
++] = lp_build_const_int32(gallivm
, 0); /* slc */
2468 emit_data
->args
[num_args
++] = lp_build_const_int32(gallivm
, 0); /* tfe */
2469 emit_data
->args
[num_args
++] = lp_build_const_int32(gallivm
, 0); /* lwe */
2471 emit_data
->arg_count
= num_args
;
2474 static const struct lp_build_tgsi_action tex_action
;
2476 static void tex_fetch_ptrs(
2477 struct lp_build_tgsi_context
* bld_base
,
2478 struct lp_build_emit_data
* emit_data
,
2479 LLVMValueRef
*res_ptr
, LLVMValueRef
*samp_ptr
, LLVMValueRef
*fmask_ptr
)
2481 struct si_shader_context
*si_shader_ctx
= si_shader_context(bld_base
);
2482 struct gallivm_state
*gallivm
= bld_base
->base
.gallivm
;
2483 const struct tgsi_full_instruction
* inst
= emit_data
->inst
;
2484 unsigned target
= inst
->Texture
.Texture
;
2485 unsigned sampler_src
;
2486 unsigned sampler_index
;
2488 sampler_src
= emit_data
->inst
->Instruction
.NumSrcRegs
- 1;
2489 sampler_index
= emit_data
->inst
->Src
[sampler_src
].Register
.Index
;
2491 if (emit_data
->inst
->Src
[sampler_src
].Register
.Indirect
) {
2492 const struct tgsi_full_src_register
*reg
= &emit_data
->inst
->Src
[sampler_src
];
2493 LLVMValueRef ind_index
;
2495 ind_index
= get_indirect_index(si_shader_ctx
, ®
->Indirect
, reg
->Register
.Index
);
2497 *res_ptr
= LLVMGetParam(si_shader_ctx
->radeon_bld
.main_fn
, SI_PARAM_SAMPLER_VIEWS
);
2498 *res_ptr
= build_indexed_load_const(si_shader_ctx
, *res_ptr
, ind_index
);
2500 *samp_ptr
= LLVMGetParam(si_shader_ctx
->radeon_bld
.main_fn
, SI_PARAM_SAMPLER_STATES
);
2501 *samp_ptr
= build_indexed_load_const(si_shader_ctx
, *samp_ptr
, ind_index
);
2503 if (target
== TGSI_TEXTURE_2D_MSAA
||
2504 target
== TGSI_TEXTURE_2D_ARRAY_MSAA
) {
2505 ind_index
= LLVMBuildAdd(gallivm
->builder
, ind_index
,
2506 lp_build_const_int32(gallivm
,
2507 SI_FMASK_TEX_OFFSET
), "");
2508 *fmask_ptr
= LLVMGetParam(si_shader_ctx
->radeon_bld
.main_fn
, SI_PARAM_SAMPLER_VIEWS
);
2509 *fmask_ptr
= build_indexed_load_const(si_shader_ctx
, *fmask_ptr
, ind_index
);
2512 *res_ptr
= si_shader_ctx
->sampler_views
[sampler_index
];
2513 *samp_ptr
= si_shader_ctx
->sampler_states
[sampler_index
];
2514 *fmask_ptr
= si_shader_ctx
->sampler_views
[SI_FMASK_TEX_OFFSET
+ sampler_index
];
2518 static void tex_fetch_args(
2519 struct lp_build_tgsi_context
* bld_base
,
2520 struct lp_build_emit_data
* emit_data
)
2522 struct si_shader_context
*si_shader_ctx
= si_shader_context(bld_base
);
2523 struct gallivm_state
*gallivm
= bld_base
->base
.gallivm
;
2524 LLVMBuilderRef builder
= gallivm
->builder
;
2525 const struct tgsi_full_instruction
* inst
= emit_data
->inst
;
2526 unsigned opcode
= inst
->Instruction
.Opcode
;
2527 unsigned target
= inst
->Texture
.Texture
;
2528 LLVMValueRef coords
[5], derivs
[6];
2529 LLVMValueRef address
[16];
2531 unsigned num_coords
= tgsi_util_get_texture_coord_dim(target
, &ref_pos
);
2534 unsigned num_deriv_channels
= 0;
2535 bool has_offset
= inst
->Texture
.NumOffsets
> 0;
2536 LLVMValueRef res_ptr
, samp_ptr
, fmask_ptr
= NULL
;
2537 LLVMTypeRef i32
= LLVMInt32TypeInContext(gallivm
->context
);
2538 unsigned dmask
= 0xf;
2540 tex_fetch_ptrs(bld_base
, emit_data
, &res_ptr
, &samp_ptr
, &fmask_ptr
);
2542 if (opcode
== TGSI_OPCODE_TXQ
) {
2543 if (target
== TGSI_TEXTURE_BUFFER
) {
2544 LLVMTypeRef v8i32
= LLVMVectorType(i32
, 8);
2546 /* Read the size from the buffer descriptor directly. */
2547 LLVMValueRef res
= LLVMBuildBitCast(builder
, res_ptr
, v8i32
, "");
2548 LLVMValueRef size
= LLVMBuildExtractElement(builder
, res
,
2549 lp_build_const_int32(gallivm
, 6), "");
2551 if (si_shader_ctx
->screen
->b
.chip_class
>= VI
) {
2552 /* On VI, the descriptor contains the size in bytes,
2553 * but TXQ must return the size in elements.
2554 * The stride is always non-zero for resources using TXQ.
2556 LLVMValueRef stride
=
2557 LLVMBuildExtractElement(builder
, res
,
2558 lp_build_const_int32(gallivm
, 5), "");
2559 stride
= LLVMBuildLShr(builder
, stride
,
2560 lp_build_const_int32(gallivm
, 16), "");
2561 stride
= LLVMBuildAnd(builder
, stride
,
2562 lp_build_const_int32(gallivm
, 0x3FFF), "");
2564 size
= LLVMBuildUDiv(builder
, size
, stride
, "");
2567 emit_data
->args
[0] = size
;
2571 /* Textures - set the mip level. */
2572 address
[count
++] = lp_build_emit_fetch(bld_base
, inst
, 0, TGSI_CHAN_X
);
2574 set_tex_fetch_args(gallivm
, emit_data
, opcode
, target
, res_ptr
,
2575 NULL
, address
, count
, 0xf);
2579 if (target
== TGSI_TEXTURE_BUFFER
) {
2580 LLVMTypeRef i128
= LLVMIntTypeInContext(gallivm
->context
, 128);
2581 LLVMTypeRef v2i128
= LLVMVectorType(i128
, 2);
2582 LLVMTypeRef i8
= LLVMInt8TypeInContext(gallivm
->context
);
2583 LLVMTypeRef v16i8
= LLVMVectorType(i8
, 16);
2585 /* Bitcast and truncate v8i32 to v16i8. */
2586 LLVMValueRef res
= res_ptr
;
2587 res
= LLVMBuildBitCast(gallivm
->builder
, res
, v2i128
, "");
2588 res
= LLVMBuildExtractElement(gallivm
->builder
, res
, bld_base
->uint_bld
.one
, "");
2589 res
= LLVMBuildBitCast(gallivm
->builder
, res
, v16i8
, "");
2591 emit_data
->dst_type
= LLVMVectorType(bld_base
->base
.elem_type
, 4);
2592 emit_data
->args
[0] = res
;
2593 emit_data
->args
[1] = bld_base
->uint_bld
.zero
;
2594 emit_data
->args
[2] = lp_build_emit_fetch(bld_base
, emit_data
->inst
, 0, TGSI_CHAN_X
);
2595 emit_data
->arg_count
= 3;
2599 /* Fetch and project texture coordinates */
2600 coords
[3] = lp_build_emit_fetch(bld_base
, emit_data
->inst
, 0, TGSI_CHAN_W
);
2601 for (chan
= 0; chan
< 3; chan
++ ) {
2602 coords
[chan
] = lp_build_emit_fetch(bld_base
,
2605 if (opcode
== TGSI_OPCODE_TXP
)
2606 coords
[chan
] = lp_build_emit_llvm_binary(bld_base
,
2612 if (opcode
== TGSI_OPCODE_TXP
)
2613 coords
[3] = bld_base
->base
.one
;
2616 if (has_offset
&& opcode
!= TGSI_OPCODE_TXF
) {
2617 /* The offsets are six-bit signed integers packed like this:
2618 * X=[5:0], Y=[13:8], and Z=[21:16].
2620 LLVMValueRef offset
[3], pack
;
2622 assert(inst
->Texture
.NumOffsets
== 1);
2624 for (chan
= 0; chan
< 3; chan
++) {
2625 offset
[chan
] = lp_build_emit_fetch_texoffset(bld_base
,
2626 emit_data
->inst
, 0, chan
);
2627 offset
[chan
] = LLVMBuildAnd(gallivm
->builder
, offset
[chan
],
2628 lp_build_const_int32(gallivm
, 0x3f), "");
2630 offset
[chan
] = LLVMBuildShl(gallivm
->builder
, offset
[chan
],
2631 lp_build_const_int32(gallivm
, chan
*8), "");
2634 pack
= LLVMBuildOr(gallivm
->builder
, offset
[0], offset
[1], "");
2635 pack
= LLVMBuildOr(gallivm
->builder
, pack
, offset
[2], "");
2636 address
[count
++] = pack
;
2639 /* Pack LOD bias value */
2640 if (opcode
== TGSI_OPCODE_TXB
)
2641 address
[count
++] = coords
[3];
2642 if (opcode
== TGSI_OPCODE_TXB2
)
2643 address
[count
++] = lp_build_emit_fetch(bld_base
, inst
, 1, TGSI_CHAN_X
);
2645 /* Pack depth comparison value */
2646 if (tgsi_is_shadow_target(target
) && opcode
!= TGSI_OPCODE_LODQ
) {
2647 if (target
== TGSI_TEXTURE_SHADOWCUBE_ARRAY
) {
2648 address
[count
++] = lp_build_emit_fetch(bld_base
, inst
, 1, TGSI_CHAN_X
);
2650 assert(ref_pos
>= 0);
2651 address
[count
++] = coords
[ref_pos
];
2655 /* Pack user derivatives */
2656 if (opcode
== TGSI_OPCODE_TXD
) {
2657 int param
, num_src_deriv_channels
;
2660 case TGSI_TEXTURE_3D
:
2661 num_src_deriv_channels
= 3;
2662 num_deriv_channels
= 3;
2664 case TGSI_TEXTURE_2D
:
2665 case TGSI_TEXTURE_SHADOW2D
:
2666 case TGSI_TEXTURE_RECT
:
2667 case TGSI_TEXTURE_SHADOWRECT
:
2668 case TGSI_TEXTURE_2D_ARRAY
:
2669 case TGSI_TEXTURE_SHADOW2D_ARRAY
:
2670 num_src_deriv_channels
= 2;
2671 num_deriv_channels
= 2;
2673 case TGSI_TEXTURE_CUBE
:
2674 case TGSI_TEXTURE_SHADOWCUBE
:
2675 case TGSI_TEXTURE_CUBE_ARRAY
:
2676 case TGSI_TEXTURE_SHADOWCUBE_ARRAY
:
2677 /* Cube derivatives will be converted to 2D. */
2678 num_src_deriv_channels
= 3;
2679 num_deriv_channels
= 2;
2681 case TGSI_TEXTURE_1D
:
2682 case TGSI_TEXTURE_SHADOW1D
:
2683 case TGSI_TEXTURE_1D_ARRAY
:
2684 case TGSI_TEXTURE_SHADOW1D_ARRAY
:
2685 num_src_deriv_channels
= 1;
2686 num_deriv_channels
= 1;
2689 unreachable("invalid target");
2692 for (param
= 0; param
< 2; param
++)
2693 for (chan
= 0; chan
< num_src_deriv_channels
; chan
++)
2694 derivs
[param
* num_src_deriv_channels
+ chan
] =
2695 lp_build_emit_fetch(bld_base
, inst
, param
+1, chan
);
2698 if (target
== TGSI_TEXTURE_CUBE
||
2699 target
== TGSI_TEXTURE_CUBE_ARRAY
||
2700 target
== TGSI_TEXTURE_SHADOWCUBE
||
2701 target
== TGSI_TEXTURE_SHADOWCUBE_ARRAY
)
2702 radeon_llvm_emit_prepare_cube_coords(bld_base
, emit_data
, coords
, derivs
);
2704 if (opcode
== TGSI_OPCODE_TXD
)
2705 for (int i
= 0; i
< num_deriv_channels
* 2; i
++)
2706 address
[count
++] = derivs
[i
];
2708 /* Pack texture coordinates */
2709 address
[count
++] = coords
[0];
2711 address
[count
++] = coords
[1];
2713 address
[count
++] = coords
[2];
2715 /* Pack LOD or sample index */
2716 if (opcode
== TGSI_OPCODE_TXL
|| opcode
== TGSI_OPCODE_TXF
)
2717 address
[count
++] = coords
[3];
2718 else if (opcode
== TGSI_OPCODE_TXL2
)
2719 address
[count
++] = lp_build_emit_fetch(bld_base
, inst
, 1, TGSI_CHAN_X
);
2722 assert(!"Cannot handle more than 16 texture address parameters");
2726 for (chan
= 0; chan
< count
; chan
++ ) {
2727 address
[chan
] = LLVMBuildBitCast(gallivm
->builder
,
2728 address
[chan
], i32
, "");
2731 /* Adjust the sample index according to FMASK.
2733 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
2734 * which is the identity mapping. Each nibble says which physical sample
2735 * should be fetched to get that sample.
2737 * For example, 0x11111100 means there are only 2 samples stored and
2738 * the second sample covers 3/4 of the pixel. When reading samples 0
2739 * and 1, return physical sample 0 (determined by the first two 0s
2740 * in FMASK), otherwise return physical sample 1.
2742 * The sample index should be adjusted as follows:
2743 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
2745 if (target
== TGSI_TEXTURE_2D_MSAA
||
2746 target
== TGSI_TEXTURE_2D_ARRAY_MSAA
) {
2747 struct lp_build_context
*uint_bld
= &bld_base
->uint_bld
;
2748 struct lp_build_emit_data txf_emit_data
= *emit_data
;
2749 LLVMValueRef txf_address
[4];
2750 unsigned txf_count
= count
;
2751 struct tgsi_full_instruction inst
= {};
2753 memcpy(txf_address
, address
, sizeof(txf_address
));
2755 if (target
== TGSI_TEXTURE_2D_MSAA
) {
2756 txf_address
[2] = bld_base
->uint_bld
.zero
;
2758 txf_address
[3] = bld_base
->uint_bld
.zero
;
2760 /* Read FMASK using TXF. */
2761 inst
.Instruction
.Opcode
= TGSI_OPCODE_TXF
;
2762 inst
.Texture
.Texture
= target
;
2763 txf_emit_data
.inst
= &inst
;
2764 txf_emit_data
.chan
= 0;
2765 set_tex_fetch_args(gallivm
, &txf_emit_data
, TGSI_OPCODE_TXF
,
2766 target
, fmask_ptr
, NULL
,
2767 txf_address
, txf_count
, 0xf);
2768 build_tex_intrinsic(&tex_action
, bld_base
, &txf_emit_data
);
2770 /* Initialize some constants. */
2771 LLVMValueRef four
= LLVMConstInt(uint_bld
->elem_type
, 4, 0);
2772 LLVMValueRef F
= LLVMConstInt(uint_bld
->elem_type
, 0xF, 0);
2774 /* Apply the formula. */
2775 LLVMValueRef fmask
=
2776 LLVMBuildExtractElement(gallivm
->builder
,
2777 txf_emit_data
.output
[0],
2778 uint_bld
->zero
, "");
2780 unsigned sample_chan
= target
== TGSI_TEXTURE_2D_MSAA
? 2 : 3;
2782 LLVMValueRef sample_index4
=
2783 LLVMBuildMul(gallivm
->builder
, address
[sample_chan
], four
, "");
2785 LLVMValueRef shifted_fmask
=
2786 LLVMBuildLShr(gallivm
->builder
, fmask
, sample_index4
, "");
2788 LLVMValueRef final_sample
=
2789 LLVMBuildAnd(gallivm
->builder
, shifted_fmask
, F
, "");
2791 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
2792 * resource descriptor is 0 (invalid),
2794 LLVMValueRef fmask_desc
=
2795 LLVMBuildBitCast(gallivm
->builder
, fmask_ptr
,
2796 LLVMVectorType(uint_bld
->elem_type
, 8), "");
2798 LLVMValueRef fmask_word1
=
2799 LLVMBuildExtractElement(gallivm
->builder
, fmask_desc
,
2802 LLVMValueRef word1_is_nonzero
=
2803 LLVMBuildICmp(gallivm
->builder
, LLVMIntNE
,
2804 fmask_word1
, uint_bld
->zero
, "");
2806 /* Replace the MSAA sample index. */
2807 address
[sample_chan
] =
2808 LLVMBuildSelect(gallivm
->builder
, word1_is_nonzero
,
2809 final_sample
, address
[sample_chan
], "");
2812 if (opcode
== TGSI_OPCODE_TXF
) {
2813 /* add tex offsets */
2814 if (inst
->Texture
.NumOffsets
) {
2815 struct lp_build_context
*uint_bld
= &bld_base
->uint_bld
;
2816 struct lp_build_tgsi_soa_context
*bld
= lp_soa_context(bld_base
);
2817 const struct tgsi_texture_offset
* off
= inst
->TexOffsets
;
2819 assert(inst
->Texture
.NumOffsets
== 1);
2822 case TGSI_TEXTURE_3D
:
2823 address
[2] = lp_build_add(uint_bld
, address
[2],
2824 bld
->immediates
[off
->Index
][off
->SwizzleZ
]);
2826 case TGSI_TEXTURE_2D
:
2827 case TGSI_TEXTURE_SHADOW2D
:
2828 case TGSI_TEXTURE_RECT
:
2829 case TGSI_TEXTURE_SHADOWRECT
:
2830 case TGSI_TEXTURE_2D_ARRAY
:
2831 case TGSI_TEXTURE_SHADOW2D_ARRAY
:
2833 lp_build_add(uint_bld
, address
[1],
2834 bld
->immediates
[off
->Index
][off
->SwizzleY
]);
2836 case TGSI_TEXTURE_1D
:
2837 case TGSI_TEXTURE_SHADOW1D
:
2838 case TGSI_TEXTURE_1D_ARRAY
:
2839 case TGSI_TEXTURE_SHADOW1D_ARRAY
:
2841 lp_build_add(uint_bld
, address
[0],
2842 bld
->immediates
[off
->Index
][off
->SwizzleX
]);
2844 /* texture offsets do not apply to other texture targets */
2849 if (opcode
== TGSI_OPCODE_TG4
) {
2850 unsigned gather_comp
= 0;
2852 /* DMASK was repurposed for GATHER4. 4 components are always
2853 * returned and DMASK works like a swizzle - it selects
2854 * the component to fetch. The only valid DMASK values are
2855 * 1=red, 2=green, 4=blue, 8=alpha. (e.g. 1 returns
2856 * (red,red,red,red) etc.) The ISA document doesn't mention
2860 /* Get the component index from src1.x for Gather4. */
2861 if (!tgsi_is_shadow_target(target
)) {
2862 LLVMValueRef (*imms
)[4] = lp_soa_context(bld_base
)->immediates
;
2863 LLVMValueRef comp_imm
;
2864 struct tgsi_src_register src1
= inst
->Src
[1].Register
;
2866 assert(src1
.File
== TGSI_FILE_IMMEDIATE
);
2868 comp_imm
= imms
[src1
.Index
][src1
.SwizzleX
];
2869 gather_comp
= LLVMConstIntGetZExtValue(comp_imm
);
2870 gather_comp
= CLAMP(gather_comp
, 0, 3);
2873 dmask
= 1 << gather_comp
;
2876 set_tex_fetch_args(gallivm
, emit_data
, opcode
, target
, res_ptr
,
2877 samp_ptr
, address
, count
, dmask
);
2880 static void build_tex_intrinsic(const struct lp_build_tgsi_action
* action
,
2881 struct lp_build_tgsi_context
* bld_base
,
2882 struct lp_build_emit_data
* emit_data
)
2884 struct lp_build_context
* base
= &bld_base
->base
;
2885 unsigned opcode
= emit_data
->inst
->Instruction
.Opcode
;
2886 unsigned target
= emit_data
->inst
->Texture
.Texture
;
2887 char intr_name
[127];
2888 bool has_offset
= emit_data
->inst
->Texture
.NumOffsets
> 0;
2889 bool is_shadow
= tgsi_is_shadow_target(target
);
2891 const char *name
= "llvm.SI.image.sample";
2892 const char *infix
= "";
2894 if (opcode
== TGSI_OPCODE_TXQ
&& target
== TGSI_TEXTURE_BUFFER
) {
2895 /* Just return the buffer size. */
2896 emit_data
->output
[emit_data
->chan
] = emit_data
->args
[0];
2900 if (target
== TGSI_TEXTURE_BUFFER
) {
2901 emit_data
->output
[emit_data
->chan
] = lp_build_intrinsic(
2902 base
->gallivm
->builder
,
2903 "llvm.SI.vs.load.input", emit_data
->dst_type
,
2904 emit_data
->args
, emit_data
->arg_count
,
2905 LLVMReadNoneAttribute
| LLVMNoUnwindAttribute
);
2910 case TGSI_OPCODE_TXF
:
2911 name
= target
== TGSI_TEXTURE_2D_MSAA
||
2912 target
== TGSI_TEXTURE_2D_ARRAY_MSAA
?
2913 "llvm.SI.image.load" :
2914 "llvm.SI.image.load.mip";
2918 case TGSI_OPCODE_TXQ
:
2919 name
= "llvm.SI.getresinfo";
2923 case TGSI_OPCODE_LODQ
:
2924 name
= "llvm.SI.getlod";
2928 case TGSI_OPCODE_TEX
:
2929 case TGSI_OPCODE_TEX2
:
2930 case TGSI_OPCODE_TXP
:
2932 case TGSI_OPCODE_TXB
:
2933 case TGSI_OPCODE_TXB2
:
2936 case TGSI_OPCODE_TXL
:
2937 case TGSI_OPCODE_TXL2
:
2940 case TGSI_OPCODE_TXD
:
2943 case TGSI_OPCODE_TG4
:
2944 name
= "llvm.SI.gather4";
2951 if (LLVMGetTypeKind(LLVMTypeOf(emit_data
->args
[0])) == LLVMVectorTypeKind
)
2952 sprintf(type
, ".v%ui32",
2953 LLVMGetVectorSize(LLVMTypeOf(emit_data
->args
[0])));
2955 strcpy(type
, ".i32");
2957 /* Add the type and suffixes .c, .o if needed. */
2958 sprintf(intr_name
, "%s%s%s%s%s",
2959 name
, is_shadow
? ".c" : "", infix
,
2960 has_offset
? ".o" : "", type
);
2962 emit_data
->output
[emit_data
->chan
] = lp_build_intrinsic(
2963 base
->gallivm
->builder
, intr_name
, emit_data
->dst_type
,
2964 emit_data
->args
, emit_data
->arg_count
,
2965 LLVMReadNoneAttribute
| LLVMNoUnwindAttribute
);
2967 /* Divide the number of layers by 6 to get the number of cubes. */
2968 if (opcode
== TGSI_OPCODE_TXQ
&&
2969 (target
== TGSI_TEXTURE_CUBE_ARRAY
||
2970 target
== TGSI_TEXTURE_SHADOWCUBE_ARRAY
)) {
2971 LLVMBuilderRef builder
= bld_base
->base
.gallivm
->builder
;
2972 LLVMValueRef two
= lp_build_const_int32(bld_base
->base
.gallivm
, 2);
2973 LLVMValueRef six
= lp_build_const_int32(bld_base
->base
.gallivm
, 6);
2975 LLVMValueRef v4
= emit_data
->output
[emit_data
->chan
];
2976 LLVMValueRef z
= LLVMBuildExtractElement(builder
, v4
, two
, "");
2977 z
= LLVMBuildSDiv(builder
, z
, six
, "");
2979 emit_data
->output
[emit_data
->chan
] =
2980 LLVMBuildInsertElement(builder
, v4
, z
, two
, "");
2984 static void si_llvm_emit_txqs(
2985 const struct lp_build_tgsi_action
* action
,
2986 struct lp_build_tgsi_context
* bld_base
,
2987 struct lp_build_emit_data
* emit_data
)
2989 struct gallivm_state
*gallivm
= bld_base
->base
.gallivm
;
2990 LLVMBuilderRef builder
= gallivm
->builder
;
2991 LLVMTypeRef i32
= LLVMInt32TypeInContext(gallivm
->context
);
2992 LLVMTypeRef v8i32
= LLVMVectorType(i32
, 8);
2993 LLVMValueRef res
, samples
;
2994 LLVMValueRef res_ptr
, samp_ptr
, fmask_ptr
= NULL
;
2996 tex_fetch_ptrs(bld_base
, emit_data
, &res_ptr
, &samp_ptr
, &fmask_ptr
);
2999 /* Read the samples from the descriptor directly. */
3000 res
= LLVMBuildBitCast(builder
, res_ptr
, v8i32
, "");
3001 samples
= LLVMBuildExtractElement(
3003 lp_build_const_int32(gallivm
, 3), "");
3004 samples
= LLVMBuildLShr(builder
, samples
,
3005 lp_build_const_int32(gallivm
, 16), "");
3006 samples
= LLVMBuildAnd(builder
, samples
,
3007 lp_build_const_int32(gallivm
, 0xf), "");
3008 samples
= LLVMBuildShl(builder
, lp_build_const_int32(gallivm
, 1),
3011 emit_data
->output
[emit_data
->chan
] = samples
;
3015 * SI implements derivatives using the local data store (LDS)
3016 * All writes to the LDS happen in all executing threads at
3017 * the same time. TID is the Thread ID for the current
3018 * thread and is a value between 0 and 63, representing
3019 * the thread's position in the wavefront.
3021 * For the pixel shader threads are grouped into quads of four pixels.
3022 * The TIDs of the pixels of a quad are:
3030 * So, masking the TID with 0xfffffffc yields the TID of the top left pixel
3031 * of the quad, masking with 0xfffffffd yields the TID of the top pixel of
3032 * the current pixel's column, and masking with 0xfffffffe yields the TID
3033 * of the left pixel of the current pixel's row.
3035 * Adding 1 yields the TID of the pixel to the right of the left pixel, and
3036 * adding 2 yields the TID of the pixel below the top pixel.
3038 /* masks for thread ID. */
3039 #define TID_MASK_TOP_LEFT 0xfffffffc
3040 #define TID_MASK_TOP 0xfffffffd
3041 #define TID_MASK_LEFT 0xfffffffe
3043 static void si_llvm_emit_ddxy(
3044 const struct lp_build_tgsi_action
* action
,
3045 struct lp_build_tgsi_context
* bld_base
,
3046 struct lp_build_emit_data
* emit_data
)
3048 struct si_shader_context
*si_shader_ctx
= si_shader_context(bld_base
);
3049 struct gallivm_state
*gallivm
= bld_base
->base
.gallivm
;
3050 struct lp_build_context
* base
= &bld_base
->base
;
3051 const struct tgsi_full_instruction
*inst
= emit_data
->inst
;
3052 unsigned opcode
= inst
->Instruction
.Opcode
;
3053 LLVMValueRef indices
[2];
3054 LLVMValueRef store_ptr
, load_ptr0
, load_ptr1
;
3055 LLVMValueRef tl
, trbl
, result
[4];
3057 unsigned swizzle
[4];
3062 i32
= LLVMInt32TypeInContext(gallivm
->context
);
3064 indices
[0] = bld_base
->uint_bld
.zero
;
3065 indices
[1] = lp_build_intrinsic(gallivm
->builder
, "llvm.SI.tid", i32
,
3066 NULL
, 0, LLVMReadNoneAttribute
);
3067 store_ptr
= LLVMBuildGEP(gallivm
->builder
, si_shader_ctx
->lds
,
3070 if (opcode
== TGSI_OPCODE_DDX_FINE
)
3071 mask
= TID_MASK_LEFT
;
3072 else if (opcode
== TGSI_OPCODE_DDY_FINE
)
3073 mask
= TID_MASK_TOP
;
3075 mask
= TID_MASK_TOP_LEFT
;
3077 indices
[1] = LLVMBuildAnd(gallivm
->builder
, indices
[1],
3078 lp_build_const_int32(gallivm
, mask
), "");
3079 load_ptr0
= LLVMBuildGEP(gallivm
->builder
, si_shader_ctx
->lds
,
3082 /* for DDX we want to next X pixel, DDY next Y pixel. */
3083 idx
= (opcode
== TGSI_OPCODE_DDX
|| opcode
== TGSI_OPCODE_DDX_FINE
) ? 1 : 2;
3084 indices
[1] = LLVMBuildAdd(gallivm
->builder
, indices
[1],
3085 lp_build_const_int32(gallivm
, idx
), "");
3086 load_ptr1
= LLVMBuildGEP(gallivm
->builder
, si_shader_ctx
->lds
,
3089 for (c
= 0; c
< 4; ++c
) {
3092 swizzle
[c
] = tgsi_util_get_full_src_register_swizzle(&inst
->Src
[0], c
);
3093 for (i
= 0; i
< c
; ++i
) {
3094 if (swizzle
[i
] == swizzle
[c
]) {
3095 result
[c
] = result
[i
];
3102 LLVMBuildStore(gallivm
->builder
,
3103 LLVMBuildBitCast(gallivm
->builder
,
3104 lp_build_emit_fetch(bld_base
, inst
, 0, c
),
3108 tl
= LLVMBuildLoad(gallivm
->builder
, load_ptr0
, "");
3109 tl
= LLVMBuildBitCast(gallivm
->builder
, tl
, base
->elem_type
, "");
3111 trbl
= LLVMBuildLoad(gallivm
->builder
, load_ptr1
, "");
3112 trbl
= LLVMBuildBitCast(gallivm
->builder
, trbl
, base
->elem_type
, "");
3114 result
[c
] = LLVMBuildFSub(gallivm
->builder
, trbl
, tl
, "");
3117 emit_data
->output
[0] = lp_build_gather_values(gallivm
, result
, 4);
3121 * this takes an I,J coordinate pair,
3122 * and works out the X and Y derivatives.
3123 * it returns DDX(I), DDX(J), DDY(I), DDY(J).
3125 static LLVMValueRef
si_llvm_emit_ddxy_interp(
3126 struct lp_build_tgsi_context
*bld_base
,
3127 LLVMValueRef interp_ij
)
3129 struct si_shader_context
*si_shader_ctx
= si_shader_context(bld_base
);
3130 struct gallivm_state
*gallivm
= bld_base
->base
.gallivm
;
3131 struct lp_build_context
*base
= &bld_base
->base
;
3132 LLVMValueRef indices
[2];
3133 LLVMValueRef store_ptr
, load_ptr_x
, load_ptr_y
, load_ptr_ddx
, load_ptr_ddy
, temp
, temp2
;
3134 LLVMValueRef tl
, tr
, bl
, result
[4];
3138 i32
= LLVMInt32TypeInContext(gallivm
->context
);
3140 indices
[0] = bld_base
->uint_bld
.zero
;
3141 indices
[1] = lp_build_intrinsic(gallivm
->builder
, "llvm.SI.tid", i32
,
3142 NULL
, 0, LLVMReadNoneAttribute
);
3143 store_ptr
= LLVMBuildGEP(gallivm
->builder
, si_shader_ctx
->lds
,
3146 temp
= LLVMBuildAnd(gallivm
->builder
, indices
[1],
3147 lp_build_const_int32(gallivm
, TID_MASK_LEFT
), "");
3149 temp2
= LLVMBuildAnd(gallivm
->builder
, indices
[1],
3150 lp_build_const_int32(gallivm
, TID_MASK_TOP
), "");
3153 load_ptr_x
= LLVMBuildGEP(gallivm
->builder
, si_shader_ctx
->lds
,
3157 load_ptr_y
= LLVMBuildGEP(gallivm
->builder
, si_shader_ctx
->lds
,
3160 indices
[1] = LLVMBuildAdd(gallivm
->builder
, temp
,
3161 lp_build_const_int32(gallivm
, 1), "");
3162 load_ptr_ddx
= LLVMBuildGEP(gallivm
->builder
, si_shader_ctx
->lds
,
3165 indices
[1] = LLVMBuildAdd(gallivm
->builder
, temp2
,
3166 lp_build_const_int32(gallivm
, 2), "");
3167 load_ptr_ddy
= LLVMBuildGEP(gallivm
->builder
, si_shader_ctx
->lds
,
3170 for (c
= 0; c
< 2; ++c
) {
3171 LLVMValueRef store_val
;
3172 LLVMValueRef c_ll
= lp_build_const_int32(gallivm
, c
);
3174 store_val
= LLVMBuildExtractElement(gallivm
->builder
,
3175 interp_ij
, c_ll
, "");
3176 LLVMBuildStore(gallivm
->builder
,
3180 tl
= LLVMBuildLoad(gallivm
->builder
, load_ptr_x
, "");
3181 tl
= LLVMBuildBitCast(gallivm
->builder
, tl
, base
->elem_type
, "");
3183 tr
= LLVMBuildLoad(gallivm
->builder
, load_ptr_ddx
, "");
3184 tr
= LLVMBuildBitCast(gallivm
->builder
, tr
, base
->elem_type
, "");
3186 result
[c
] = LLVMBuildFSub(gallivm
->builder
, tr
, tl
, "");
3188 tl
= LLVMBuildLoad(gallivm
->builder
, load_ptr_y
, "");
3189 tl
= LLVMBuildBitCast(gallivm
->builder
, tl
, base
->elem_type
, "");
3191 bl
= LLVMBuildLoad(gallivm
->builder
, load_ptr_ddy
, "");
3192 bl
= LLVMBuildBitCast(gallivm
->builder
, bl
, base
->elem_type
, "");
3194 result
[c
+ 2] = LLVMBuildFSub(gallivm
->builder
, bl
, tl
, "");
3197 return lp_build_gather_values(gallivm
, result
, 4);
3200 static void interp_fetch_args(
3201 struct lp_build_tgsi_context
*bld_base
,
3202 struct lp_build_emit_data
*emit_data
)
3204 struct si_shader_context
*si_shader_ctx
= si_shader_context(bld_base
);
3205 struct gallivm_state
*gallivm
= bld_base
->base
.gallivm
;
3206 const struct tgsi_full_instruction
*inst
= emit_data
->inst
;
3208 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_INTERP_OFFSET
) {
3209 /* offset is in second src, first two channels */
3210 emit_data
->args
[0] = lp_build_emit_fetch(bld_base
,
3213 emit_data
->args
[1] = lp_build_emit_fetch(bld_base
,
3216 emit_data
->arg_count
= 2;
3217 } else if (inst
->Instruction
.Opcode
== TGSI_OPCODE_INTERP_SAMPLE
) {
3218 LLVMValueRef sample_position
;
3219 LLVMValueRef sample_id
;
3220 LLVMValueRef halfval
= lp_build_const_float(gallivm
, 0.5f
);
3222 /* fetch sample ID, then fetch its sample position,
3223 * and place into first two channels.
3225 sample_id
= lp_build_emit_fetch(bld_base
,
3226 emit_data
->inst
, 1, TGSI_CHAN_X
);
3227 sample_id
= LLVMBuildBitCast(gallivm
->builder
, sample_id
,
3228 LLVMInt32TypeInContext(gallivm
->context
),
3230 sample_position
= load_sample_position(&si_shader_ctx
->radeon_bld
, sample_id
);
3232 emit_data
->args
[0] = LLVMBuildExtractElement(gallivm
->builder
,
3234 lp_build_const_int32(gallivm
, 0), "");
3236 emit_data
->args
[0] = LLVMBuildFSub(gallivm
->builder
, emit_data
->args
[0], halfval
, "");
3237 emit_data
->args
[1] = LLVMBuildExtractElement(gallivm
->builder
,
3239 lp_build_const_int32(gallivm
, 1), "");
3240 emit_data
->args
[1] = LLVMBuildFSub(gallivm
->builder
, emit_data
->args
[1], halfval
, "");
3241 emit_data
->arg_count
= 2;
3245 static void build_interp_intrinsic(const struct lp_build_tgsi_action
*action
,
3246 struct lp_build_tgsi_context
*bld_base
,
3247 struct lp_build_emit_data
*emit_data
)
3249 struct si_shader_context
*si_shader_ctx
= si_shader_context(bld_base
);
3250 struct si_shader
*shader
= si_shader_ctx
->shader
;
3251 struct gallivm_state
*gallivm
= bld_base
->base
.gallivm
;
3252 LLVMValueRef interp_param
;
3253 const struct tgsi_full_instruction
*inst
= emit_data
->inst
;
3254 const char *intr_name
;
3258 LLVMValueRef attr_number
;
3259 LLVMTypeRef input_type
= LLVMFloatTypeInContext(gallivm
->context
);
3260 LLVMValueRef params
= LLVMGetParam(si_shader_ctx
->radeon_bld
.main_fn
, SI_PARAM_PRIM_MASK
);
3261 int interp_param_idx
;
3264 assert(inst
->Src
[0].Register
.File
== TGSI_FILE_INPUT
);
3265 input_index
= inst
->Src
[0].Register
.Index
;
3267 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_INTERP_OFFSET
||
3268 inst
->Instruction
.Opcode
== TGSI_OPCODE_INTERP_SAMPLE
)
3269 location
= TGSI_INTERPOLATE_LOC_CENTER
;
3271 location
= TGSI_INTERPOLATE_LOC_CENTROID
;
3273 interp_param_idx
= lookup_interp_param_index(shader
->ps_input_interpolate
[input_index
],
3275 if (interp_param_idx
== -1)
3277 else if (interp_param_idx
)
3278 interp_param
= LLVMGetParam(si_shader_ctx
->radeon_bld
.main_fn
, interp_param_idx
);
3280 interp_param
= NULL
;
3282 attr_number
= lp_build_const_int32(gallivm
,
3283 shader
->ps_input_param_offset
[input_index
]);
3285 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_INTERP_OFFSET
||
3286 inst
->Instruction
.Opcode
== TGSI_OPCODE_INTERP_SAMPLE
) {
3287 LLVMValueRef ij_out
[2];
3288 LLVMValueRef ddxy_out
= si_llvm_emit_ddxy_interp(bld_base
, interp_param
);
3291 * take the I then J parameters, and the DDX/Y for it, and
3292 * calculate the IJ inputs for the interpolator.
3293 * temp1 = ddx * offset/sample.x + I;
3294 * interp_param.I = ddy * offset/sample.y + temp1;
3295 * temp1 = ddx * offset/sample.x + J;
3296 * interp_param.J = ddy * offset/sample.y + temp1;
3298 for (i
= 0; i
< 2; i
++) {
3299 LLVMValueRef ix_ll
= lp_build_const_int32(gallivm
, i
);
3300 LLVMValueRef iy_ll
= lp_build_const_int32(gallivm
, i
+ 2);
3301 LLVMValueRef ddx_el
= LLVMBuildExtractElement(gallivm
->builder
,
3302 ddxy_out
, ix_ll
, "");
3303 LLVMValueRef ddy_el
= LLVMBuildExtractElement(gallivm
->builder
,
3304 ddxy_out
, iy_ll
, "");
3305 LLVMValueRef interp_el
= LLVMBuildExtractElement(gallivm
->builder
,
3306 interp_param
, ix_ll
, "");
3307 LLVMValueRef temp1
, temp2
;
3309 interp_el
= LLVMBuildBitCast(gallivm
->builder
, interp_el
,
3310 LLVMFloatTypeInContext(gallivm
->context
), "");
3312 temp1
= LLVMBuildFMul(gallivm
->builder
, ddx_el
, emit_data
->args
[0], "");
3314 temp1
= LLVMBuildFAdd(gallivm
->builder
, temp1
, interp_el
, "");
3316 temp2
= LLVMBuildFMul(gallivm
->builder
, ddy_el
, emit_data
->args
[1], "");
3318 temp2
= LLVMBuildFAdd(gallivm
->builder
, temp2
, temp1
, "");
3320 ij_out
[i
] = LLVMBuildBitCast(gallivm
->builder
,
3322 LLVMIntTypeInContext(gallivm
->context
, 32), "");
3324 interp_param
= lp_build_gather_values(bld_base
->base
.gallivm
, ij_out
, 2);
3327 intr_name
= interp_param
? "llvm.SI.fs.interp" : "llvm.SI.fs.constant";
3328 for (chan
= 0; chan
< 2; chan
++) {
3329 LLVMValueRef args
[4];
3330 LLVMValueRef llvm_chan
;
3333 schan
= tgsi_util_get_full_src_register_swizzle(&inst
->Src
[0], chan
);
3334 llvm_chan
= lp_build_const_int32(gallivm
, schan
);
3336 args
[0] = llvm_chan
;
3337 args
[1] = attr_number
;
3339 args
[3] = interp_param
;
3341 emit_data
->output
[chan
] =
3342 lp_build_intrinsic(gallivm
->builder
, intr_name
,
3343 input_type
, args
, args
[3] ? 4 : 3,
3344 LLVMReadNoneAttribute
| LLVMNoUnwindAttribute
);
3348 static unsigned si_llvm_get_stream(struct lp_build_tgsi_context
*bld_base
,
3349 struct lp_build_emit_data
*emit_data
)
3351 LLVMValueRef (*imms
)[4] = lp_soa_context(bld_base
)->immediates
;
3352 struct tgsi_src_register src0
= emit_data
->inst
->Src
[0].Register
;
3355 assert(src0
.File
== TGSI_FILE_IMMEDIATE
);
3357 stream
= LLVMConstIntGetZExtValue(imms
[src0
.Index
][src0
.SwizzleX
]) & 0x3;
3361 /* Emit one vertex from the geometry shader */
3362 static void si_llvm_emit_vertex(
3363 const struct lp_build_tgsi_action
*action
,
3364 struct lp_build_tgsi_context
*bld_base
,
3365 struct lp_build_emit_data
*emit_data
)
3367 struct si_shader_context
*si_shader_ctx
= si_shader_context(bld_base
);
3368 struct lp_build_context
*uint
= &bld_base
->uint_bld
;
3369 struct si_shader
*shader
= si_shader_ctx
->shader
;
3370 struct tgsi_shader_info
*info
= &shader
->selector
->info
;
3371 struct gallivm_state
*gallivm
= bld_base
->base
.gallivm
;
3372 LLVMTypeRef i32
= LLVMInt32TypeInContext(gallivm
->context
);
3373 LLVMValueRef soffset
= LLVMGetParam(si_shader_ctx
->radeon_bld
.main_fn
,
3374 SI_PARAM_GS2VS_OFFSET
);
3375 LLVMValueRef gs_next_vertex
;
3376 LLVMValueRef can_emit
, kill
;
3377 LLVMValueRef args
[2];
3382 stream
= si_llvm_get_stream(bld_base
, emit_data
);
3384 /* Write vertex attribute values to GSVS ring */
3385 gs_next_vertex
= LLVMBuildLoad(gallivm
->builder
,
3386 si_shader_ctx
->gs_next_vertex
[stream
],
3389 /* If this thread has already emitted the declared maximum number of
3390 * vertices, kill it: excessive vertex emissions are not supposed to
3391 * have any effect, and GS threads have no externally observable
3392 * effects other than emitting vertices.
3394 can_emit
= LLVMBuildICmp(gallivm
->builder
, LLVMIntULE
, gs_next_vertex
,
3395 lp_build_const_int32(gallivm
,
3396 shader
->selector
->gs_max_out_vertices
), "");
3397 kill
= lp_build_select(&bld_base
->base
, can_emit
,
3398 lp_build_const_float(gallivm
, 1.0f
),
3399 lp_build_const_float(gallivm
, -1.0f
));
3401 lp_build_intrinsic(gallivm
->builder
, "llvm.AMDGPU.kill",
3402 LLVMVoidTypeInContext(gallivm
->context
), &kill
, 1, 0);
3404 for (i
= 0; i
< info
->num_outputs
; i
++) {
3405 LLVMValueRef
*out_ptr
=
3406 si_shader_ctx
->radeon_bld
.soa
.outputs
[i
];
3408 for (chan
= 0; chan
< 4; chan
++) {
3409 LLVMValueRef out_val
= LLVMBuildLoad(gallivm
->builder
, out_ptr
[chan
], "");
3410 LLVMValueRef voffset
=
3411 lp_build_const_int32(gallivm
, (i
* 4 + chan
) *
3412 shader
->selector
->gs_max_out_vertices
);
3414 voffset
= lp_build_add(uint
, voffset
, gs_next_vertex
);
3415 voffset
= lp_build_mul_imm(uint
, voffset
, 4);
3417 out_val
= LLVMBuildBitCast(gallivm
->builder
, out_val
, i32
, "");
3419 build_tbuffer_store(si_shader_ctx
,
3420 si_shader_ctx
->gsvs_ring
[stream
],
3422 voffset
, soffset
, 0,
3423 V_008F0C_BUF_DATA_FORMAT_32
,
3424 V_008F0C_BUF_NUM_FORMAT_UINT
,
3428 gs_next_vertex
= lp_build_add(uint
, gs_next_vertex
,
3429 lp_build_const_int32(gallivm
, 1));
3431 LLVMBuildStore(gallivm
->builder
, gs_next_vertex
, si_shader_ctx
->gs_next_vertex
[stream
]);
3433 /* Signal vertex emission */
3434 args
[0] = lp_build_const_int32(gallivm
, SENDMSG_GS_OP_EMIT
| SENDMSG_GS
| (stream
<< 8));
3435 args
[1] = LLVMGetParam(si_shader_ctx
->radeon_bld
.main_fn
, SI_PARAM_GS_WAVE_ID
);
3436 lp_build_intrinsic(gallivm
->builder
, "llvm.SI.sendmsg",
3437 LLVMVoidTypeInContext(gallivm
->context
), args
, 2,
3438 LLVMNoUnwindAttribute
);
3441 /* Cut one primitive from the geometry shader */
3442 static void si_llvm_emit_primitive(
3443 const struct lp_build_tgsi_action
*action
,
3444 struct lp_build_tgsi_context
*bld_base
,
3445 struct lp_build_emit_data
*emit_data
)
3447 struct si_shader_context
*si_shader_ctx
= si_shader_context(bld_base
);
3448 struct gallivm_state
*gallivm
= bld_base
->base
.gallivm
;
3449 LLVMValueRef args
[2];
3452 /* Signal primitive cut */
3453 stream
= si_llvm_get_stream(bld_base
, emit_data
);
3454 args
[0] = lp_build_const_int32(gallivm
, SENDMSG_GS_OP_CUT
| SENDMSG_GS
| (stream
<< 8));
3455 args
[1] = LLVMGetParam(si_shader_ctx
->radeon_bld
.main_fn
, SI_PARAM_GS_WAVE_ID
);
3456 lp_build_intrinsic(gallivm
->builder
, "llvm.SI.sendmsg",
3457 LLVMVoidTypeInContext(gallivm
->context
), args
, 2,
3458 LLVMNoUnwindAttribute
);
3461 static void si_llvm_emit_barrier(const struct lp_build_tgsi_action
*action
,
3462 struct lp_build_tgsi_context
*bld_base
,
3463 struct lp_build_emit_data
*emit_data
)
3465 struct gallivm_state
*gallivm
= bld_base
->base
.gallivm
;
3467 lp_build_intrinsic(gallivm
->builder
, "llvm.AMDGPU.barrier.local",
3468 LLVMVoidTypeInContext(gallivm
->context
), NULL
, 0,
3469 LLVMNoUnwindAttribute
);
3472 static const struct lp_build_tgsi_action tex_action
= {
3473 .fetch_args
= tex_fetch_args
,
3474 .emit
= build_tex_intrinsic
,
3477 static const struct lp_build_tgsi_action interp_action
= {
3478 .fetch_args
= interp_fetch_args
,
3479 .emit
= build_interp_intrinsic
,
3482 static void create_meta_data(struct si_shader_context
*si_shader_ctx
)
3484 struct gallivm_state
*gallivm
= si_shader_ctx
->radeon_bld
.soa
.bld_base
.base
.gallivm
;
3485 LLVMValueRef args
[3];
3487 args
[0] = LLVMMDStringInContext(gallivm
->context
, "const", 5);
3489 args
[2] = lp_build_const_int32(gallivm
, 1);
3491 si_shader_ctx
->const_md
= LLVMMDNodeInContext(gallivm
->context
, args
, 3);
3494 static LLVMTypeRef
const_array(LLVMTypeRef elem_type
, int num_elements
)
3496 return LLVMPointerType(LLVMArrayType(elem_type
, num_elements
),
3500 static void declare_streamout_params(struct si_shader_context
*si_shader_ctx
,
3501 struct pipe_stream_output_info
*so
,
3502 LLVMTypeRef
*params
, LLVMTypeRef i32
,
3503 unsigned *num_params
)
3507 /* Streamout SGPRs. */
3508 if (so
->num_outputs
) {
3509 params
[si_shader_ctx
->param_streamout_config
= (*num_params
)++] = i32
;
3510 params
[si_shader_ctx
->param_streamout_write_index
= (*num_params
)++] = i32
;
3512 /* A streamout buffer offset is loaded if the stride is non-zero. */
3513 for (i
= 0; i
< 4; i
++) {
3517 params
[si_shader_ctx
->param_streamout_offset
[i
] = (*num_params
)++] = i32
;
3521 static void create_function(struct si_shader_context
*si_shader_ctx
)
3523 struct lp_build_tgsi_context
*bld_base
= &si_shader_ctx
->radeon_bld
.soa
.bld_base
;
3524 struct gallivm_state
*gallivm
= bld_base
->base
.gallivm
;
3525 struct si_shader
*shader
= si_shader_ctx
->shader
;
3526 LLVMTypeRef params
[SI_NUM_PARAMS
], f32
, i8
, i32
, v2i32
, v3i32
, v16i8
, v4i32
, v8i32
;
3527 unsigned i
, last_array_pointer
, last_sgpr
, num_params
;
3529 i8
= LLVMInt8TypeInContext(gallivm
->context
);
3530 i32
= LLVMInt32TypeInContext(gallivm
->context
);
3531 f32
= LLVMFloatTypeInContext(gallivm
->context
);
3532 v2i32
= LLVMVectorType(i32
, 2);
3533 v3i32
= LLVMVectorType(i32
, 3);
3534 v4i32
= LLVMVectorType(i32
, 4);
3535 v8i32
= LLVMVectorType(i32
, 8);
3536 v16i8
= LLVMVectorType(i8
, 16);
3538 params
[SI_PARAM_RW_BUFFERS
] = const_array(v16i8
, SI_NUM_RW_BUFFERS
);
3539 params
[SI_PARAM_CONST_BUFFERS
] = const_array(v16i8
, SI_NUM_CONST_BUFFERS
);
3540 params
[SI_PARAM_SAMPLER_STATES
] = const_array(v4i32
, SI_NUM_SAMPLER_STATES
);
3541 params
[SI_PARAM_SAMPLER_VIEWS
] = const_array(v8i32
, SI_NUM_SAMPLER_VIEWS
);
3542 last_array_pointer
= SI_PARAM_SAMPLER_VIEWS
;
3544 switch (si_shader_ctx
->type
) {
3545 case TGSI_PROCESSOR_VERTEX
:
3546 params
[SI_PARAM_VERTEX_BUFFERS
] = const_array(v16i8
, SI_NUM_VERTEX_BUFFERS
);
3547 last_array_pointer
= SI_PARAM_VERTEX_BUFFERS
;
3548 params
[SI_PARAM_BASE_VERTEX
] = i32
;
3549 params
[SI_PARAM_START_INSTANCE
] = i32
;
3550 num_params
= SI_PARAM_START_INSTANCE
+1;
3552 if (shader
->key
.vs
.as_es
) {
3553 params
[si_shader_ctx
->param_es2gs_offset
= num_params
++] = i32
;
3554 } else if (shader
->key
.vs
.as_ls
) {
3555 params
[SI_PARAM_LS_OUT_LAYOUT
] = i32
;
3556 num_params
= SI_PARAM_LS_OUT_LAYOUT
+1;
3558 if (si_shader_ctx
->is_gs_copy_shader
) {
3559 last_array_pointer
= SI_PARAM_CONST_BUFFERS
;
3560 num_params
= SI_PARAM_CONST_BUFFERS
+1;
3562 params
[SI_PARAM_VS_STATE_BITS
] = i32
;
3563 num_params
= SI_PARAM_VS_STATE_BITS
+1;
3566 /* The locations of the other parameters are assigned dynamically. */
3567 declare_streamout_params(si_shader_ctx
, &shader
->selector
->so
,
3568 params
, i32
, &num_params
);
3571 last_sgpr
= num_params
-1;
3574 params
[si_shader_ctx
->param_vertex_id
= num_params
++] = i32
;
3575 params
[si_shader_ctx
->param_rel_auto_id
= num_params
++] = i32
;
3576 params
[si_shader_ctx
->param_vs_prim_id
= num_params
++] = i32
;
3577 params
[si_shader_ctx
->param_instance_id
= num_params
++] = i32
;
3580 case TGSI_PROCESSOR_TESS_CTRL
:
3581 params
[SI_PARAM_TCS_OUT_OFFSETS
] = i32
;
3582 params
[SI_PARAM_TCS_OUT_LAYOUT
] = i32
;
3583 params
[SI_PARAM_TCS_IN_LAYOUT
] = i32
;
3584 params
[SI_PARAM_TESS_FACTOR_OFFSET
] = i32
;
3585 last_sgpr
= SI_PARAM_TESS_FACTOR_OFFSET
;
3588 params
[SI_PARAM_PATCH_ID
] = i32
;
3589 params
[SI_PARAM_REL_IDS
] = i32
;
3590 num_params
= SI_PARAM_REL_IDS
+1;
3593 case TGSI_PROCESSOR_TESS_EVAL
:
3594 params
[SI_PARAM_TCS_OUT_OFFSETS
] = i32
;
3595 params
[SI_PARAM_TCS_OUT_LAYOUT
] = i32
;
3596 num_params
= SI_PARAM_TCS_OUT_LAYOUT
+1;
3598 if (shader
->key
.tes
.as_es
) {
3599 params
[si_shader_ctx
->param_es2gs_offset
= num_params
++] = i32
;
3601 declare_streamout_params(si_shader_ctx
, &shader
->selector
->so
,
3602 params
, i32
, &num_params
);
3604 last_sgpr
= num_params
- 1;
3607 params
[si_shader_ctx
->param_tes_u
= num_params
++] = f32
;
3608 params
[si_shader_ctx
->param_tes_v
= num_params
++] = f32
;
3609 params
[si_shader_ctx
->param_tes_rel_patch_id
= num_params
++] = i32
;
3610 params
[si_shader_ctx
->param_tes_patch_id
= num_params
++] = i32
;
3613 case TGSI_PROCESSOR_GEOMETRY
:
3614 params
[SI_PARAM_GS2VS_OFFSET
] = i32
;
3615 params
[SI_PARAM_GS_WAVE_ID
] = i32
;
3616 last_sgpr
= SI_PARAM_GS_WAVE_ID
;
3619 params
[SI_PARAM_VTX0_OFFSET
] = i32
;
3620 params
[SI_PARAM_VTX1_OFFSET
] = i32
;
3621 params
[SI_PARAM_PRIMITIVE_ID
] = i32
;
3622 params
[SI_PARAM_VTX2_OFFSET
] = i32
;
3623 params
[SI_PARAM_VTX3_OFFSET
] = i32
;
3624 params
[SI_PARAM_VTX4_OFFSET
] = i32
;
3625 params
[SI_PARAM_VTX5_OFFSET
] = i32
;
3626 params
[SI_PARAM_GS_INSTANCE_ID
] = i32
;
3627 num_params
= SI_PARAM_GS_INSTANCE_ID
+1;
3630 case TGSI_PROCESSOR_FRAGMENT
:
3631 params
[SI_PARAM_ALPHA_REF
] = f32
;
3632 params
[SI_PARAM_PS_STATE_BITS
] = i32
;
3633 params
[SI_PARAM_PRIM_MASK
] = i32
;
3634 last_sgpr
= SI_PARAM_PRIM_MASK
;
3635 params
[SI_PARAM_PERSP_SAMPLE
] = v2i32
;
3636 params
[SI_PARAM_PERSP_CENTER
] = v2i32
;
3637 params
[SI_PARAM_PERSP_CENTROID
] = v2i32
;
3638 params
[SI_PARAM_PERSP_PULL_MODEL
] = v3i32
;
3639 params
[SI_PARAM_LINEAR_SAMPLE
] = v2i32
;
3640 params
[SI_PARAM_LINEAR_CENTER
] = v2i32
;
3641 params
[SI_PARAM_LINEAR_CENTROID
] = v2i32
;
3642 params
[SI_PARAM_LINE_STIPPLE_TEX
] = f32
;
3643 params
[SI_PARAM_POS_X_FLOAT
] = f32
;
3644 params
[SI_PARAM_POS_Y_FLOAT
] = f32
;
3645 params
[SI_PARAM_POS_Z_FLOAT
] = f32
;
3646 params
[SI_PARAM_POS_W_FLOAT
] = f32
;
3647 params
[SI_PARAM_FRONT_FACE
] = i32
;
3648 params
[SI_PARAM_ANCILLARY
] = i32
;
3649 params
[SI_PARAM_SAMPLE_COVERAGE
] = f32
;
3650 params
[SI_PARAM_POS_FIXED_PT
] = f32
;
3651 num_params
= SI_PARAM_POS_FIXED_PT
+1;
3655 assert(0 && "unimplemented shader");
3659 assert(num_params
<= Elements(params
));
3660 radeon_llvm_create_func(&si_shader_ctx
->radeon_bld
, params
, num_params
);
3661 radeon_llvm_shader_type(si_shader_ctx
->radeon_bld
.main_fn
, si_shader_ctx
->type
);
3663 if (shader
->dx10_clamp_mode
)
3664 LLVMAddTargetDependentFunctionAttr(si_shader_ctx
->radeon_bld
.main_fn
,
3665 "enable-no-nans-fp-math", "true");
3667 for (i
= 0; i
<= last_sgpr
; ++i
) {
3668 LLVMValueRef P
= LLVMGetParam(si_shader_ctx
->radeon_bld
.main_fn
, i
);
3670 /* We tell llvm that array inputs are passed by value to allow Sinking pass
3671 * to move load. Inputs are constant so this is fine. */
3672 if (i
<= last_array_pointer
)
3673 LLVMAddAttribute(P
, LLVMByValAttribute
);
3675 LLVMAddAttribute(P
, LLVMInRegAttribute
);
3678 if (bld_base
->info
&&
3679 (bld_base
->info
->opcode_count
[TGSI_OPCODE_DDX
] > 0 ||
3680 bld_base
->info
->opcode_count
[TGSI_OPCODE_DDY
] > 0 ||
3681 bld_base
->info
->opcode_count
[TGSI_OPCODE_DDX_FINE
] > 0 ||
3682 bld_base
->info
->opcode_count
[TGSI_OPCODE_DDY_FINE
] > 0 ||
3683 bld_base
->info
->opcode_count
[TGSI_OPCODE_INTERP_OFFSET
] > 0 ||
3684 bld_base
->info
->opcode_count
[TGSI_OPCODE_INTERP_SAMPLE
] > 0))
3685 si_shader_ctx
->lds
=
3686 LLVMAddGlobalInAddressSpace(gallivm
->module
,
3687 LLVMArrayType(i32
, 64),
3691 if ((si_shader_ctx
->type
== TGSI_PROCESSOR_VERTEX
&& shader
->key
.vs
.as_ls
) ||
3692 si_shader_ctx
->type
== TGSI_PROCESSOR_TESS_CTRL
||
3693 si_shader_ctx
->type
== TGSI_PROCESSOR_TESS_EVAL
) {
3694 /* This is the upper bound, maximum is 32 inputs times 32 vertices */
3695 unsigned vertex_data_dw_size
= 32*32*4;
3696 unsigned patch_data_dw_size
= 32*4;
3697 /* The formula is: TCS inputs + TCS outputs + TCS patch outputs. */
3698 unsigned patch_dw_size
= vertex_data_dw_size
*2 + patch_data_dw_size
;
3699 unsigned lds_dwords
= patch_dw_size
;
3701 /* The actual size is computed outside of the shader to reduce
3702 * the number of shader variants. */
3703 si_shader_ctx
->lds
=
3704 LLVMAddGlobalInAddressSpace(gallivm
->module
,
3705 LLVMArrayType(i32
, lds_dwords
),
3711 static void preload_constants(struct si_shader_context
*si_shader_ctx
)
3713 struct lp_build_tgsi_context
* bld_base
= &si_shader_ctx
->radeon_bld
.soa
.bld_base
;
3714 struct gallivm_state
* gallivm
= bld_base
->base
.gallivm
;
3715 const struct tgsi_shader_info
* info
= bld_base
->info
;
3717 LLVMValueRef ptr
= LLVMGetParam(si_shader_ctx
->radeon_bld
.main_fn
, SI_PARAM_CONST_BUFFERS
);
3719 for (buf
= 0; buf
< SI_NUM_CONST_BUFFERS
; buf
++) {
3720 unsigned i
, num_const
= info
->const_file_max
[buf
] + 1;
3725 /* Allocate space for the constant values */
3726 si_shader_ctx
->constants
[buf
] = CALLOC(num_const
* 4, sizeof(LLVMValueRef
));
3728 /* Load the resource descriptor */
3729 si_shader_ctx
->const_buffers
[buf
] =
3730 build_indexed_load_const(si_shader_ctx
, ptr
, lp_build_const_int32(gallivm
, buf
));
3732 /* Load the constants, we rely on the code sinking to do the rest */
3733 for (i
= 0; i
< num_const
* 4; ++i
) {
3734 si_shader_ctx
->constants
[buf
][i
] =
3735 buffer_load_const(gallivm
->builder
,
3736 si_shader_ctx
->const_buffers
[buf
],
3737 lp_build_const_int32(gallivm
, i
* 4),
3738 bld_base
->base
.elem_type
);
3743 static void preload_samplers(struct si_shader_context
*si_shader_ctx
)
3745 struct lp_build_tgsi_context
* bld_base
= &si_shader_ctx
->radeon_bld
.soa
.bld_base
;
3746 struct gallivm_state
* gallivm
= bld_base
->base
.gallivm
;
3747 const struct tgsi_shader_info
* info
= bld_base
->info
;
3749 unsigned i
, num_samplers
= info
->file_max
[TGSI_FILE_SAMPLER
] + 1;
3751 LLVMValueRef res_ptr
, samp_ptr
;
3752 LLVMValueRef offset
;
3754 if (num_samplers
== 0)
3757 res_ptr
= LLVMGetParam(si_shader_ctx
->radeon_bld
.main_fn
, SI_PARAM_SAMPLER_VIEWS
);
3758 samp_ptr
= LLVMGetParam(si_shader_ctx
->radeon_bld
.main_fn
, SI_PARAM_SAMPLER_STATES
);
3760 /* Load the resources and samplers, we rely on the code sinking to do the rest */
3761 for (i
= 0; i
< num_samplers
; ++i
) {
3763 offset
= lp_build_const_int32(gallivm
, i
);
3764 si_shader_ctx
->sampler_views
[i
] = build_indexed_load_const(si_shader_ctx
, res_ptr
, offset
);
3767 offset
= lp_build_const_int32(gallivm
, i
);
3768 si_shader_ctx
->sampler_states
[i
] = build_indexed_load_const(si_shader_ctx
, samp_ptr
, offset
);
3770 /* FMASK resource */
3771 if (info
->is_msaa_sampler
[i
]) {
3772 offset
= lp_build_const_int32(gallivm
, SI_FMASK_TEX_OFFSET
+ i
);
3773 si_shader_ctx
->sampler_views
[SI_FMASK_TEX_OFFSET
+ i
] =
3774 build_indexed_load_const(si_shader_ctx
, res_ptr
, offset
);
3779 static void preload_streamout_buffers(struct si_shader_context
*si_shader_ctx
)
3781 struct lp_build_tgsi_context
* bld_base
= &si_shader_ctx
->radeon_bld
.soa
.bld_base
;
3782 struct gallivm_state
* gallivm
= bld_base
->base
.gallivm
;
3785 /* Streamout can only be used if the shader is compiled as VS. */
3786 if (!si_shader_ctx
->shader
->selector
->so
.num_outputs
||
3787 (si_shader_ctx
->type
== TGSI_PROCESSOR_VERTEX
&&
3788 (si_shader_ctx
->shader
->key
.vs
.as_es
||
3789 si_shader_ctx
->shader
->key
.vs
.as_ls
)) ||
3790 (si_shader_ctx
->type
== TGSI_PROCESSOR_TESS_EVAL
&&
3791 si_shader_ctx
->shader
->key
.tes
.as_es
))
3794 LLVMValueRef buf_ptr
= LLVMGetParam(si_shader_ctx
->radeon_bld
.main_fn
,
3795 SI_PARAM_RW_BUFFERS
);
3797 /* Load the resources, we rely on the code sinking to do the rest */
3798 for (i
= 0; i
< 4; ++i
) {
3799 if (si_shader_ctx
->shader
->selector
->so
.stride
[i
]) {
3800 LLVMValueRef offset
= lp_build_const_int32(gallivm
,
3801 SI_SO_BUF_OFFSET
+ i
);
3803 si_shader_ctx
->so_buffers
[i
] = build_indexed_load_const(si_shader_ctx
, buf_ptr
, offset
);
3809 * Load ESGS and GSVS ring buffer resource descriptors and save the variables
3812 static void preload_ring_buffers(struct si_shader_context
*si_shader_ctx
)
3814 struct gallivm_state
*gallivm
=
3815 si_shader_ctx
->radeon_bld
.soa
.bld_base
.base
.gallivm
;
3817 LLVMValueRef buf_ptr
= LLVMGetParam(si_shader_ctx
->radeon_bld
.main_fn
,
3818 SI_PARAM_RW_BUFFERS
);
3820 if ((si_shader_ctx
->type
== TGSI_PROCESSOR_VERTEX
&&
3821 si_shader_ctx
->shader
->key
.vs
.as_es
) ||
3822 (si_shader_ctx
->type
== TGSI_PROCESSOR_TESS_EVAL
&&
3823 si_shader_ctx
->shader
->key
.tes
.as_es
) ||
3824 si_shader_ctx
->type
== TGSI_PROCESSOR_GEOMETRY
) {
3825 LLVMValueRef offset
= lp_build_const_int32(gallivm
, SI_RING_ESGS
);
3827 si_shader_ctx
->esgs_ring
=
3828 build_indexed_load_const(si_shader_ctx
, buf_ptr
, offset
);
3831 if (si_shader_ctx
->is_gs_copy_shader
) {
3832 LLVMValueRef offset
= lp_build_const_int32(gallivm
, SI_RING_GSVS
);
3834 si_shader_ctx
->gsvs_ring
[0] =
3835 build_indexed_load_const(si_shader_ctx
, buf_ptr
, offset
);
3837 if (si_shader_ctx
->type
== TGSI_PROCESSOR_GEOMETRY
) {
3839 for (i
= 0; i
< 4; i
++) {
3840 LLVMValueRef offset
= lp_build_const_int32(gallivm
, SI_RING_GSVS
+ i
);
3842 si_shader_ctx
->gsvs_ring
[i
] =
3843 build_indexed_load_const(si_shader_ctx
, buf_ptr
, offset
);
3848 void si_shader_binary_read_config(struct radeon_shader_binary
*binary
,
3849 struct si_shader_config
*conf
,
3850 unsigned symbol_offset
)
3853 const unsigned char *config
=
3854 radeon_shader_binary_config_start(binary
, symbol_offset
);
3856 /* XXX: We may be able to emit some of these values directly rather than
3857 * extracting fields to be emitted later.
3860 for (i
= 0; i
< binary
->config_size_per_symbol
; i
+= 8) {
3861 unsigned reg
= util_le32_to_cpu(*(uint32_t*)(config
+ i
));
3862 unsigned value
= util_le32_to_cpu(*(uint32_t*)(config
+ i
+ 4));
3864 case R_00B028_SPI_SHADER_PGM_RSRC1_PS
:
3865 case R_00B128_SPI_SHADER_PGM_RSRC1_VS
:
3866 case R_00B228_SPI_SHADER_PGM_RSRC1_GS
:
3867 case R_00B848_COMPUTE_PGM_RSRC1
:
3868 conf
->num_sgprs
= MAX2(conf
->num_sgprs
, (G_00B028_SGPRS(value
) + 1) * 8);
3869 conf
->num_vgprs
= MAX2(conf
->num_vgprs
, (G_00B028_VGPRS(value
) + 1) * 4);
3870 conf
->float_mode
= G_00B028_FLOAT_MODE(value
);
3871 conf
->rsrc1
= value
;
3873 case R_00B02C_SPI_SHADER_PGM_RSRC2_PS
:
3874 conf
->lds_size
= MAX2(conf
->lds_size
, G_00B02C_EXTRA_LDS_SIZE(value
));
3876 case R_00B84C_COMPUTE_PGM_RSRC2
:
3877 conf
->lds_size
= MAX2(conf
->lds_size
, G_00B84C_LDS_SIZE(value
));
3878 conf
->rsrc2
= value
;
3880 case R_0286CC_SPI_PS_INPUT_ENA
:
3881 conf
->spi_ps_input_ena
= value
;
3883 case R_0286D0_SPI_PS_INPUT_ADDR
:
3884 /* Not used yet, but will be in the future */
3886 case R_0286E8_SPI_TMPRING_SIZE
:
3887 case R_00B860_COMPUTE_TMPRING_SIZE
:
3888 /* WAVESIZE is in units of 256 dwords. */
3889 conf
->scratch_bytes_per_wave
=
3890 G_00B860_WAVESIZE(value
) * 256 * 4 * 1;
3894 static bool printed
;
3897 fprintf(stderr
, "Warning: LLVM emitted unknown "
3898 "config register: 0x%x\n", reg
);
3907 void si_shader_apply_scratch_relocs(struct si_context
*sctx
,
3908 struct si_shader
*shader
,
3909 uint64_t scratch_va
)
3912 uint32_t scratch_rsrc_dword0
= scratch_va
;
3913 uint32_t scratch_rsrc_dword1
=
3914 S_008F04_BASE_ADDRESS_HI(scratch_va
>> 32)
3915 | S_008F04_STRIDE(shader
->config
.scratch_bytes_per_wave
/ 64);
3917 for (i
= 0 ; i
< shader
->binary
.reloc_count
; i
++) {
3918 const struct radeon_shader_reloc
*reloc
=
3919 &shader
->binary
.relocs
[i
];
3920 if (!strcmp(scratch_rsrc_dword0_symbol
, reloc
->name
)) {
3921 util_memcpy_cpu_to_le32(shader
->binary
.code
+ reloc
->offset
,
3922 &scratch_rsrc_dword0
, 4);
3923 } else if (!strcmp(scratch_rsrc_dword1_symbol
, reloc
->name
)) {
3924 util_memcpy_cpu_to_le32(shader
->binary
.code
+ reloc
->offset
,
3925 &scratch_rsrc_dword1
, 4);
3930 int si_shader_binary_upload(struct si_screen
*sscreen
, struct si_shader
*shader
)
3932 const struct radeon_shader_binary
*binary
= &shader
->binary
;
3933 unsigned code_size
= binary
->code_size
+ binary
->rodata_size
;
3936 r600_resource_reference(&shader
->bo
, NULL
);
3937 shader
->bo
= si_resource_create_custom(&sscreen
->b
.b
,
3938 PIPE_USAGE_IMMUTABLE
,
3943 ptr
= sscreen
->b
.ws
->buffer_map(shader
->bo
->buf
, NULL
,
3944 PIPE_TRANSFER_READ_WRITE
);
3945 util_memcpy_cpu_to_le32(ptr
, binary
->code
, binary
->code_size
);
3946 if (binary
->rodata_size
> 0) {
3947 ptr
+= binary
->code_size
;
3948 util_memcpy_cpu_to_le32(ptr
, binary
->rodata
,
3949 binary
->rodata_size
);
3952 sscreen
->b
.ws
->buffer_unmap(shader
->bo
->buf
);
3956 static void si_shader_dump_disassembly(const struct radeon_shader_binary
*binary
,
3957 struct pipe_debug_callback
*debug
)
3962 if (binary
->disasm_string
) {
3963 fprintf(stderr
, "\nShader Disassembly:\n\n");
3964 fprintf(stderr
, "%s\n", binary
->disasm_string
);
3966 if (debug
&& debug
->debug_message
) {
3967 /* Very long debug messages are cut off, so send the
3968 * disassembly one line at a time. This causes more
3969 * overhead, but on the plus side it simplifies
3970 * parsing of resulting logs.
3972 pipe_debug_message(debug
, SHADER_INFO
,
3973 "Shader Disassembly Begin");
3975 line
= binary
->disasm_string
;
3977 p
= strchrnul(line
, '\n');
3981 pipe_debug_message(debug
, SHADER_INFO
,
3982 "%.*s", count
, line
);
3990 pipe_debug_message(debug
, SHADER_INFO
,
3991 "Shader Disassembly End");
3994 fprintf(stderr
, "SI CODE:\n");
3995 for (i
= 0; i
< binary
->code_size
; i
+= 4) {
3996 fprintf(stderr
, "@0x%x: %02x%02x%02x%02x\n", i
,
3997 binary
->code
[i
+ 3], binary
->code
[i
+ 2],
3998 binary
->code
[i
+ 1], binary
->code
[i
]);
4003 static void si_shader_dump_stats(struct si_screen
*sscreen
,
4004 struct si_shader_config
*conf
,
4005 unsigned num_inputs
,
4007 struct pipe_debug_callback
*debug
,
4010 unsigned lds_increment
= sscreen
->b
.chip_class
>= CIK
? 512 : 256;
4011 unsigned lds_per_wave
= 0;
4012 unsigned max_simd_waves
= 10;
4014 /* Compute LDS usage for PS. */
4015 if (processor
== TGSI_PROCESSOR_FRAGMENT
) {
4016 /* The minimum usage per wave is (num_inputs * 36). The maximum
4017 * usage is (num_inputs * 36 * 16).
4018 * We can get anything in between and it varies between waves.
4020 * Other stages don't know the size at compile time or don't
4021 * allocate LDS per wave, but instead they do it per thread group.
4023 lds_per_wave
= conf
->lds_size
* lds_increment
+
4024 align(num_inputs
* 36, lds_increment
);
4027 /* Compute the per-SIMD wave counts. */
4028 if (conf
->num_sgprs
) {
4029 if (sscreen
->b
.chip_class
>= VI
)
4030 max_simd_waves
= MIN2(max_simd_waves
, 800 / conf
->num_sgprs
);
4032 max_simd_waves
= MIN2(max_simd_waves
, 512 / conf
->num_sgprs
);
4035 if (conf
->num_vgprs
)
4036 max_simd_waves
= MIN2(max_simd_waves
, 256 / conf
->num_vgprs
);
4038 /* LDS is 64KB per CU (4 SIMDs), divided into 16KB blocks per SIMD
4042 max_simd_waves
= MIN2(max_simd_waves
, 16384 / lds_per_wave
);
4044 if (r600_can_dump_shader(&sscreen
->b
, processor
)) {
4045 fprintf(stderr
, "*** SHADER STATS ***\n"
4048 "Code Size: %d bytes\n"
4050 "Scratch: %d bytes per wave\n"
4052 "********************\n",
4053 conf
->num_sgprs
, conf
->num_vgprs
, code_size
,
4054 conf
->lds_size
, conf
->scratch_bytes_per_wave
,
4058 pipe_debug_message(debug
, SHADER_INFO
,
4059 "Shader Stats: SGPRS: %d VGPRS: %d Code Size: %d "
4060 "LDS: %d Scratch: %d Max Waves: %d",
4061 conf
->num_sgprs
, conf
->num_vgprs
, code_size
,
4062 conf
->lds_size
, conf
->scratch_bytes_per_wave
,
4066 void si_shader_dump(struct si_screen
*sscreen
, struct si_shader
*shader
,
4067 struct pipe_debug_callback
*debug
, unsigned processor
)
4069 if (r600_can_dump_shader(&sscreen
->b
, processor
))
4070 if (!(sscreen
->b
.debug_flags
& DBG_NO_ASM
))
4071 si_shader_dump_disassembly(&shader
->binary
, debug
);
4073 si_shader_dump_stats(sscreen
, &shader
->config
,
4074 shader
->selector
->info
.num_inputs
,
4075 shader
->binary
.code_size
, debug
, processor
);
4078 int si_compile_llvm(struct si_screen
*sscreen
,
4079 struct radeon_shader_binary
*binary
,
4080 struct si_shader_config
*conf
,
4081 LLVMTargetMachineRef tm
,
4083 struct pipe_debug_callback
*debug
,
4087 unsigned count
= p_atomic_inc_return(&sscreen
->b
.num_compilations
);
4089 if (r600_can_dump_shader(&sscreen
->b
, processor
)) {
4090 fprintf(stderr
, "radeonsi: Compiling shader %d\n", count
);
4092 if (!(sscreen
->b
.debug_flags
& DBG_NO_IR
))
4093 LLVMDumpModule(mod
);
4096 if (!si_replace_shader(count
, binary
)) {
4097 r
= radeon_llvm_compile(mod
, binary
,
4098 r600_get_llvm_processor_name(sscreen
->b
.family
), tm
,
4104 si_shader_binary_read_config(binary
, conf
, 0);
4106 FREE(binary
->config
);
4107 FREE(binary
->global_symbol_offsets
);
4108 binary
->config
= NULL
;
4109 binary
->global_symbol_offsets
= NULL
;
4113 /* Generate code for the hardware VS shader stage to go with a geometry shader */
4114 static int si_generate_gs_copy_shader(struct si_screen
*sscreen
,
4115 struct si_shader_context
*si_shader_ctx
,
4116 struct si_shader
*gs
, bool dump
,
4117 struct pipe_debug_callback
*debug
)
4119 struct gallivm_state
*gallivm
= &si_shader_ctx
->radeon_bld
.gallivm
;
4120 struct lp_build_tgsi_context
*bld_base
= &si_shader_ctx
->radeon_bld
.soa
.bld_base
;
4121 struct lp_build_context
*base
= &bld_base
->base
;
4122 struct lp_build_context
*uint
= &bld_base
->uint_bld
;
4123 struct si_shader_output_values
*outputs
;
4124 struct tgsi_shader_info
*gsinfo
= &gs
->selector
->info
;
4125 LLVMValueRef args
[9];
4128 outputs
= MALLOC(gsinfo
->num_outputs
* sizeof(outputs
[0]));
4130 si_shader_ctx
->type
= TGSI_PROCESSOR_VERTEX
;
4131 si_shader_ctx
->is_gs_copy_shader
= true;
4133 radeon_llvm_context_init(&si_shader_ctx
->radeon_bld
);
4135 create_meta_data(si_shader_ctx
);
4136 create_function(si_shader_ctx
);
4137 preload_streamout_buffers(si_shader_ctx
);
4138 preload_ring_buffers(si_shader_ctx
);
4140 args
[0] = si_shader_ctx
->gsvs_ring
[0];
4141 args
[1] = lp_build_mul_imm(uint
,
4142 LLVMGetParam(si_shader_ctx
->radeon_bld
.main_fn
,
4143 si_shader_ctx
->param_vertex_id
),
4145 args
[3] = uint
->zero
;
4146 args
[4] = uint
->one
; /* OFFEN */
4147 args
[5] = uint
->zero
; /* IDXEN */
4148 args
[6] = uint
->one
; /* GLC */
4149 args
[7] = uint
->one
; /* SLC */
4150 args
[8] = uint
->zero
; /* TFE */
4152 /* Fetch vertex data from GSVS ring */
4153 for (i
= 0; i
< gsinfo
->num_outputs
; ++i
) {
4156 outputs
[i
].name
= gsinfo
->output_semantic_name
[i
];
4157 outputs
[i
].sid
= gsinfo
->output_semantic_index
[i
];
4159 for (chan
= 0; chan
< 4; chan
++) {
4160 args
[2] = lp_build_const_int32(gallivm
,
4162 gs
->selector
->gs_max_out_vertices
* 16 * 4);
4164 outputs
[i
].values
[chan
] =
4165 LLVMBuildBitCast(gallivm
->builder
,
4166 lp_build_intrinsic(gallivm
->builder
,
4167 "llvm.SI.buffer.load.dword.i32.i32",
4168 LLVMInt32TypeInContext(gallivm
->context
),
4170 LLVMReadOnlyAttribute
| LLVMNoUnwindAttribute
),
4171 base
->elem_type
, "");
4175 si_llvm_export_vs(bld_base
, outputs
, gsinfo
->num_outputs
);
4177 radeon_llvm_finalize_module(&si_shader_ctx
->radeon_bld
);
4180 fprintf(stderr
, "Copy Vertex Shader for Geometry Shader:\n\n");
4182 r
= si_compile_llvm(sscreen
, &si_shader_ctx
->shader
->binary
,
4183 &si_shader_ctx
->shader
->config
, si_shader_ctx
->tm
,
4184 bld_base
->base
.gallivm
->module
,
4185 debug
, TGSI_PROCESSOR_GEOMETRY
);
4187 si_shader_dump(sscreen
, si_shader_ctx
->shader
, debug
,
4188 TGSI_PROCESSOR_GEOMETRY
);
4189 r
= si_shader_binary_upload(sscreen
, si_shader_ctx
->shader
);
4192 radeon_llvm_dispose(&si_shader_ctx
->radeon_bld
);
4198 void si_dump_shader_key(unsigned shader
, union si_shader_key
*key
, FILE *f
)
4202 fprintf(f
, "SHADER KEY\n");
4205 case PIPE_SHADER_VERTEX
:
4206 fprintf(f
, " instance_divisors = {");
4207 for (i
= 0; i
< Elements(key
->vs
.instance_divisors
); i
++)
4208 fprintf(f
, !i
? "%u" : ", %u",
4209 key
->vs
.instance_divisors
[i
]);
4211 fprintf(f
, " as_es = %u\n", key
->vs
.as_es
);
4212 fprintf(f
, " as_ls = %u\n", key
->vs
.as_ls
);
4213 fprintf(f
, " export_prim_id = %u\n", key
->vs
.export_prim_id
);
4216 case PIPE_SHADER_TESS_CTRL
:
4217 fprintf(f
, " prim_mode = %u\n", key
->tcs
.prim_mode
);
4220 case PIPE_SHADER_TESS_EVAL
:
4221 fprintf(f
, " as_es = %u\n", key
->tes
.as_es
);
4222 fprintf(f
, " export_prim_id = %u\n", key
->tes
.export_prim_id
);
4225 case PIPE_SHADER_GEOMETRY
:
4228 case PIPE_SHADER_FRAGMENT
:
4229 fprintf(f
, " spi_shader_col_format = 0x%x\n", key
->ps
.spi_shader_col_format
);
4230 fprintf(f
, " last_cbuf = %u\n", key
->ps
.last_cbuf
);
4231 fprintf(f
, " color_two_side = %u\n", key
->ps
.color_two_side
);
4232 fprintf(f
, " alpha_func = %u\n", key
->ps
.alpha_func
);
4233 fprintf(f
, " alpha_to_one = %u\n", key
->ps
.alpha_to_one
);
4234 fprintf(f
, " poly_stipple = %u\n", key
->ps
.poly_stipple
);
4235 fprintf(f
, " clamp_color = %u\n", key
->ps
.clamp_color
);
4243 int si_shader_create(struct si_screen
*sscreen
, LLVMTargetMachineRef tm
,
4244 struct si_shader
*shader
,
4245 struct pipe_debug_callback
*debug
)
4247 struct si_shader_selector
*sel
= shader
->selector
;
4248 struct tgsi_token
*tokens
= sel
->tokens
;
4249 struct si_shader_context si_shader_ctx
;
4250 struct lp_build_tgsi_context
* bld_base
;
4251 struct tgsi_shader_info stipple_shader_info
;
4254 bool poly_stipple
= sel
->type
== PIPE_SHADER_FRAGMENT
&&
4255 shader
->key
.ps
.poly_stipple
;
4256 bool dump
= r600_can_dump_shader(&sscreen
->b
, sel
->info
.processor
);
4259 tokens
= util_pstipple_create_fragment_shader(tokens
, NULL
,
4260 SI_POLY_STIPPLE_SAMPLER
,
4261 TGSI_FILE_SYSTEM_VALUE
);
4262 tgsi_scan_shader(tokens
, &stipple_shader_info
);
4265 /* Dump TGSI code before doing TGSI->LLVM conversion in case the
4266 * conversion fails. */
4267 if (dump
&& !(sscreen
->b
.debug_flags
& DBG_NO_TGSI
)) {
4268 si_dump_shader_key(sel
->type
, &shader
->key
, stderr
);
4269 tgsi_dump(tokens
, 0);
4270 si_dump_streamout(&sel
->so
);
4273 assert(shader
->nparam
== 0);
4275 memset(&si_shader_ctx
, 0, sizeof(si_shader_ctx
));
4276 radeon_llvm_context_init(&si_shader_ctx
.radeon_bld
);
4277 bld_base
= &si_shader_ctx
.radeon_bld
.soa
.bld_base
;
4279 if (sel
->type
!= PIPE_SHADER_COMPUTE
)
4280 shader
->dx10_clamp_mode
= true;
4282 shader
->uses_instanceid
= sel
->info
.uses_instanceid
;
4283 bld_base
->info
= poly_stipple
? &stipple_shader_info
: &sel
->info
;
4284 bld_base
->emit_fetch_funcs
[TGSI_FILE_CONSTANT
] = fetch_constant
;
4286 bld_base
->op_actions
[TGSI_OPCODE_INTERP_CENTROID
] = interp_action
;
4287 bld_base
->op_actions
[TGSI_OPCODE_INTERP_SAMPLE
] = interp_action
;
4288 bld_base
->op_actions
[TGSI_OPCODE_INTERP_OFFSET
] = interp_action
;
4290 bld_base
->op_actions
[TGSI_OPCODE_TEX
] = tex_action
;
4291 bld_base
->op_actions
[TGSI_OPCODE_TEX2
] = tex_action
;
4292 bld_base
->op_actions
[TGSI_OPCODE_TXB
] = tex_action
;
4293 bld_base
->op_actions
[TGSI_OPCODE_TXB2
] = tex_action
;
4294 bld_base
->op_actions
[TGSI_OPCODE_TXD
] = tex_action
;
4295 bld_base
->op_actions
[TGSI_OPCODE_TXF
] = tex_action
;
4296 bld_base
->op_actions
[TGSI_OPCODE_TXL
] = tex_action
;
4297 bld_base
->op_actions
[TGSI_OPCODE_TXL2
] = tex_action
;
4298 bld_base
->op_actions
[TGSI_OPCODE_TXP
] = tex_action
;
4299 bld_base
->op_actions
[TGSI_OPCODE_TXQ
] = tex_action
;
4300 bld_base
->op_actions
[TGSI_OPCODE_TG4
] = tex_action
;
4301 bld_base
->op_actions
[TGSI_OPCODE_LODQ
] = tex_action
;
4302 bld_base
->op_actions
[TGSI_OPCODE_TXQS
].emit
= si_llvm_emit_txqs
;
4304 bld_base
->op_actions
[TGSI_OPCODE_DDX
].emit
= si_llvm_emit_ddxy
;
4305 bld_base
->op_actions
[TGSI_OPCODE_DDY
].emit
= si_llvm_emit_ddxy
;
4306 bld_base
->op_actions
[TGSI_OPCODE_DDX_FINE
].emit
= si_llvm_emit_ddxy
;
4307 bld_base
->op_actions
[TGSI_OPCODE_DDY_FINE
].emit
= si_llvm_emit_ddxy
;
4309 bld_base
->op_actions
[TGSI_OPCODE_EMIT
].emit
= si_llvm_emit_vertex
;
4310 bld_base
->op_actions
[TGSI_OPCODE_ENDPRIM
].emit
= si_llvm_emit_primitive
;
4311 bld_base
->op_actions
[TGSI_OPCODE_BARRIER
].emit
= si_llvm_emit_barrier
;
4313 if (HAVE_LLVM
>= 0x0306) {
4314 bld_base
->op_actions
[TGSI_OPCODE_MAX
].emit
= build_tgsi_intrinsic_nomem
;
4315 bld_base
->op_actions
[TGSI_OPCODE_MAX
].intr_name
= "llvm.maxnum.f32";
4316 bld_base
->op_actions
[TGSI_OPCODE_MIN
].emit
= build_tgsi_intrinsic_nomem
;
4317 bld_base
->op_actions
[TGSI_OPCODE_MIN
].intr_name
= "llvm.minnum.f32";
4320 si_shader_ctx
.radeon_bld
.load_system_value
= declare_system_value
;
4321 si_shader_ctx
.shader
= shader
;
4322 si_shader_ctx
.type
= tgsi_get_processor_type(tokens
);
4323 si_shader_ctx
.screen
= sscreen
;
4324 si_shader_ctx
.tm
= tm
;
4326 switch (si_shader_ctx
.type
) {
4327 case TGSI_PROCESSOR_VERTEX
:
4328 si_shader_ctx
.radeon_bld
.load_input
= declare_input_vs
;
4329 if (shader
->key
.vs
.as_ls
)
4330 bld_base
->emit_epilogue
= si_llvm_emit_ls_epilogue
;
4331 else if (shader
->key
.vs
.as_es
)
4332 bld_base
->emit_epilogue
= si_llvm_emit_es_epilogue
;
4334 bld_base
->emit_epilogue
= si_llvm_emit_vs_epilogue
;
4336 case TGSI_PROCESSOR_TESS_CTRL
:
4337 bld_base
->emit_fetch_funcs
[TGSI_FILE_INPUT
] = fetch_input_tcs
;
4338 bld_base
->emit_fetch_funcs
[TGSI_FILE_OUTPUT
] = fetch_output_tcs
;
4339 bld_base
->emit_store
= store_output_tcs
;
4340 bld_base
->emit_epilogue
= si_llvm_emit_tcs_epilogue
;
4342 case TGSI_PROCESSOR_TESS_EVAL
:
4343 bld_base
->emit_fetch_funcs
[TGSI_FILE_INPUT
] = fetch_input_tes
;
4344 if (shader
->key
.tes
.as_es
)
4345 bld_base
->emit_epilogue
= si_llvm_emit_es_epilogue
;
4347 bld_base
->emit_epilogue
= si_llvm_emit_vs_epilogue
;
4349 case TGSI_PROCESSOR_GEOMETRY
:
4350 bld_base
->emit_fetch_funcs
[TGSI_FILE_INPUT
] = fetch_input_gs
;
4351 bld_base
->emit_epilogue
= si_llvm_emit_gs_epilogue
;
4353 case TGSI_PROCESSOR_FRAGMENT
:
4354 si_shader_ctx
.radeon_bld
.load_input
= declare_input_fs
;
4355 bld_base
->emit_epilogue
= si_llvm_emit_fs_epilogue
;
4358 assert(!"Unsupported shader type");
4362 create_meta_data(&si_shader_ctx
);
4363 create_function(&si_shader_ctx
);
4364 preload_constants(&si_shader_ctx
);
4365 preload_samplers(&si_shader_ctx
);
4366 preload_streamout_buffers(&si_shader_ctx
);
4367 preload_ring_buffers(&si_shader_ctx
);
4369 if (si_shader_ctx
.type
== TGSI_PROCESSOR_GEOMETRY
) {
4371 for (i
= 0; i
< 4; i
++) {
4372 si_shader_ctx
.gs_next_vertex
[i
] =
4373 lp_build_alloca(bld_base
->base
.gallivm
,
4374 bld_base
->uint_bld
.elem_type
, "");
4378 if (!lp_build_tgsi_llvm(bld_base
, tokens
)) {
4379 fprintf(stderr
, "Failed to translate shader from TGSI to LLVM\n");
4383 radeon_llvm_finalize_module(&si_shader_ctx
.radeon_bld
);
4385 mod
= bld_base
->base
.gallivm
->module
;
4386 r
= si_compile_llvm(sscreen
, &shader
->binary
, &shader
->config
, tm
,
4387 mod
, debug
, si_shader_ctx
.type
);
4389 fprintf(stderr
, "LLVM failed to compile shader\n");
4393 si_shader_dump(sscreen
, shader
, debug
, si_shader_ctx
.type
);
4395 r
= si_shader_binary_upload(sscreen
, shader
);
4397 fprintf(stderr
, "LLVM failed to upload shader\n");
4401 radeon_llvm_dispose(&si_shader_ctx
.radeon_bld
);
4403 if (si_shader_ctx
.type
== TGSI_PROCESSOR_GEOMETRY
) {
4404 shader
->gs_copy_shader
= CALLOC_STRUCT(si_shader
);
4405 shader
->gs_copy_shader
->selector
= shader
->selector
;
4406 shader
->gs_copy_shader
->key
= shader
->key
;
4407 si_shader_ctx
.shader
= shader
->gs_copy_shader
;
4408 if ((r
= si_generate_gs_copy_shader(sscreen
, &si_shader_ctx
,
4409 shader
, dump
, debug
))) {
4410 free(shader
->gs_copy_shader
);
4411 shader
->gs_copy_shader
= NULL
;
4417 for (int i
= 0; i
< SI_NUM_CONST_BUFFERS
; i
++)
4418 FREE(si_shader_ctx
.constants
[i
]);
4420 tgsi_free_tokens(tokens
);
4424 void si_shader_destroy_binary(struct radeon_shader_binary
*binary
)
4427 FREE(binary
->rodata
);
4428 FREE(binary
->relocs
);
4429 FREE(binary
->disasm_string
);
4432 void si_shader_destroy(struct si_shader
*shader
)
4434 if (shader
->gs_copy_shader
) {
4435 si_shader_destroy(shader
->gs_copy_shader
);
4436 FREE(shader
->gs_copy_shader
);
4439 if (shader
->scratch_bo
)
4440 r600_resource_reference(&shader
->scratch_bo
, NULL
);
4442 r600_resource_reference(&shader
->bo
, NULL
);
4443 si_shader_destroy_binary(&shader
->binary
);