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ac/nir,radeonsi: add ac_shader_abi::load_ubo
[mesa.git] / src / gallium / drivers / radeonsi / si_shader.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Tom Stellard <thomas.stellard@amd.com>
25 * Michel Dänzer <michel.daenzer@amd.com>
26 * Christian König <christian.koenig@amd.com>
27 */
28
29 #include "gallivm/lp_bld_const.h"
30 #include "gallivm/lp_bld_gather.h"
31 #include "gallivm/lp_bld_intr.h"
32 #include "gallivm/lp_bld_logic.h"
33 #include "gallivm/lp_bld_arit.h"
34 #include "gallivm/lp_bld_flow.h"
35 #include "gallivm/lp_bld_misc.h"
36 #include "util/u_memory.h"
37 #include "util/u_string.h"
38 #include "tgsi/tgsi_build.h"
39 #include "tgsi/tgsi_util.h"
40 #include "tgsi/tgsi_dump.h"
41
42 #include "ac_binary.h"
43 #include "ac_llvm_util.h"
44 #include "ac_exp_param.h"
45 #include "si_shader_internal.h"
46 #include "si_pipe.h"
47 #include "sid.h"
48
49 #include "compiler/nir/nir.h"
50
51 static const char *scratch_rsrc_dword0_symbol =
52 "SCRATCH_RSRC_DWORD0";
53
54 static const char *scratch_rsrc_dword1_symbol =
55 "SCRATCH_RSRC_DWORD1";
56
57 struct si_shader_output_values
58 {
59 LLVMValueRef values[4];
60 unsigned semantic_name;
61 unsigned semantic_index;
62 ubyte vertex_stream[4];
63 };
64
65 /**
66 * Used to collect types and other info about arguments of the LLVM function
67 * before the function is created.
68 */
69 struct si_function_info {
70 LLVMTypeRef types[100];
71 LLVMValueRef *assign[100];
72 unsigned num_sgpr_params;
73 unsigned num_params;
74 };
75
76 enum si_arg_regfile {
77 ARG_SGPR,
78 ARG_VGPR
79 };
80
81 static void si_init_shader_ctx(struct si_shader_context *ctx,
82 struct si_screen *sscreen,
83 LLVMTargetMachineRef tm);
84
85 static void si_llvm_emit_barrier(const struct lp_build_tgsi_action *action,
86 struct lp_build_tgsi_context *bld_base,
87 struct lp_build_emit_data *emit_data);
88
89 static void si_dump_shader_key(unsigned processor, const struct si_shader *shader,
90 FILE *f);
91
92 static unsigned llvm_get_type_size(LLVMTypeRef type);
93
94 static void si_build_vs_prolog_function(struct si_shader_context *ctx,
95 union si_shader_part_key *key);
96 static void si_build_tcs_epilog_function(struct si_shader_context *ctx,
97 union si_shader_part_key *key);
98 static void si_build_ps_prolog_function(struct si_shader_context *ctx,
99 union si_shader_part_key *key);
100 static void si_build_ps_epilog_function(struct si_shader_context *ctx,
101 union si_shader_part_key *key);
102
103 /* Ideally pass the sample mask input to the PS epilog as v13, which
104 * is its usual location, so that the shader doesn't have to add v_mov.
105 */
106 #define PS_EPILOG_SAMPLEMASK_MIN_LOC 13
107
108 enum {
109 CONST_ADDR_SPACE = 2,
110 LOCAL_ADDR_SPACE = 3,
111 };
112
113 static bool is_merged_shader(struct si_shader *shader)
114 {
115 if (shader->selector->screen->b.chip_class <= VI)
116 return false;
117
118 return shader->key.as_ls ||
119 shader->key.as_es ||
120 shader->selector->type == PIPE_SHADER_TESS_CTRL ||
121 shader->selector->type == PIPE_SHADER_GEOMETRY;
122 }
123
124 static void si_init_function_info(struct si_function_info *fninfo)
125 {
126 fninfo->num_params = 0;
127 fninfo->num_sgpr_params = 0;
128 }
129
130 static unsigned add_arg_assign(struct si_function_info *fninfo,
131 enum si_arg_regfile regfile, LLVMTypeRef type,
132 LLVMValueRef *assign)
133 {
134 assert(regfile != ARG_SGPR || fninfo->num_sgpr_params == fninfo->num_params);
135
136 unsigned idx = fninfo->num_params++;
137 assert(idx < ARRAY_SIZE(fninfo->types));
138
139 if (regfile == ARG_SGPR)
140 fninfo->num_sgpr_params = fninfo->num_params;
141
142 fninfo->types[idx] = type;
143 fninfo->assign[idx] = assign;
144 return idx;
145 }
146
147 static unsigned add_arg(struct si_function_info *fninfo,
148 enum si_arg_regfile regfile, LLVMTypeRef type)
149 {
150 return add_arg_assign(fninfo, regfile, type, NULL);
151 }
152
153 static void add_arg_checked(struct si_function_info *fninfo,
154 enum si_arg_regfile regfile, LLVMTypeRef type,
155 unsigned idx)
156 {
157 MAYBE_UNUSED unsigned actual = add_arg(fninfo, regfile, type);
158 assert(actual == idx);
159 }
160
161 /**
162 * Returns a unique index for a per-patch semantic name and index. The index
163 * must be less than 32, so that a 32-bit bitmask of used inputs or outputs
164 * can be calculated.
165 */
166 unsigned si_shader_io_get_unique_index_patch(unsigned semantic_name, unsigned index)
167 {
168 switch (semantic_name) {
169 case TGSI_SEMANTIC_TESSOUTER:
170 return 0;
171 case TGSI_SEMANTIC_TESSINNER:
172 return 1;
173 case TGSI_SEMANTIC_PATCH:
174 assert(index < 30);
175 return 2 + index;
176
177 default:
178 assert(!"invalid semantic name");
179 return 0;
180 }
181 }
182
183 /**
184 * Returns a unique index for a semantic name and index. The index must be
185 * less than 64, so that a 64-bit bitmask of used inputs or outputs can be
186 * calculated.
187 */
188 unsigned si_shader_io_get_unique_index(unsigned semantic_name, unsigned index)
189 {
190 switch (semantic_name) {
191 case TGSI_SEMANTIC_POSITION:
192 return 0;
193 case TGSI_SEMANTIC_GENERIC:
194 /* Since some shader stages use the the highest used IO index
195 * to determine the size to allocate for inputs/outputs
196 * (in LDS, tess and GS rings). GENERIC should be placed right
197 * after POSITION to make that size as small as possible.
198 */
199 if (index < SI_MAX_IO_GENERIC)
200 return 1 + index;
201
202 assert(!"invalid generic index");
203 return 0;
204 case TGSI_SEMANTIC_PSIZE:
205 return SI_MAX_IO_GENERIC + 1;
206 case TGSI_SEMANTIC_CLIPDIST:
207 assert(index <= 1);
208 return SI_MAX_IO_GENERIC + 2 + index;
209 case TGSI_SEMANTIC_FOG:
210 return SI_MAX_IO_GENERIC + 4;
211 case TGSI_SEMANTIC_LAYER:
212 return SI_MAX_IO_GENERIC + 5;
213 case TGSI_SEMANTIC_VIEWPORT_INDEX:
214 return SI_MAX_IO_GENERIC + 6;
215 case TGSI_SEMANTIC_PRIMID:
216 return SI_MAX_IO_GENERIC + 7;
217 case TGSI_SEMANTIC_COLOR: /* these alias */
218 case TGSI_SEMANTIC_BCOLOR:
219 assert(index < 2);
220 return SI_MAX_IO_GENERIC + 8 + index;
221 case TGSI_SEMANTIC_TEXCOORD:
222 assert(index < 8);
223 assert(SI_MAX_IO_GENERIC + 10 + index < 64);
224 return SI_MAX_IO_GENERIC + 10 + index;
225 default:
226 assert(!"invalid semantic name");
227 return 0;
228 }
229 }
230
231 /**
232 * Helper function that builds an LLVM IR PHI node and immediately adds
233 * incoming edges.
234 */
235 static LLVMValueRef
236 build_phi(struct ac_llvm_context *ctx, LLVMTypeRef type,
237 unsigned count_incoming, LLVMValueRef *values,
238 LLVMBasicBlockRef *blocks)
239 {
240 LLVMValueRef phi = LLVMBuildPhi(ctx->builder, type, "");
241 LLVMAddIncoming(phi, values, blocks, count_incoming);
242 return phi;
243 }
244
245 /**
246 * Get the value of a shader input parameter and extract a bitfield.
247 */
248 static LLVMValueRef unpack_param(struct si_shader_context *ctx,
249 unsigned param, unsigned rshift,
250 unsigned bitwidth)
251 {
252 struct gallivm_state *gallivm = &ctx->gallivm;
253 LLVMValueRef value = LLVMGetParam(ctx->main_fn,
254 param);
255
256 if (LLVMGetTypeKind(LLVMTypeOf(value)) == LLVMFloatTypeKind)
257 value = bitcast(&ctx->bld_base,
258 TGSI_TYPE_UNSIGNED, value);
259
260 if (rshift)
261 value = LLVMBuildLShr(gallivm->builder, value,
262 LLVMConstInt(ctx->i32, rshift, 0), "");
263
264 if (rshift + bitwidth < 32) {
265 unsigned mask = (1 << bitwidth) - 1;
266 value = LLVMBuildAnd(gallivm->builder, value,
267 LLVMConstInt(ctx->i32, mask, 0), "");
268 }
269
270 return value;
271 }
272
273 static LLVMValueRef get_rel_patch_id(struct si_shader_context *ctx)
274 {
275 switch (ctx->type) {
276 case PIPE_SHADER_TESS_CTRL:
277 return unpack_param(ctx, ctx->param_tcs_rel_ids, 0, 8);
278
279 case PIPE_SHADER_TESS_EVAL:
280 return LLVMGetParam(ctx->main_fn,
281 ctx->param_tes_rel_patch_id);
282
283 default:
284 assert(0);
285 return NULL;
286 }
287 }
288
289 /* Tessellation shaders pass outputs to the next shader using LDS.
290 *
291 * LS outputs = TCS inputs
292 * TCS outputs = TES inputs
293 *
294 * The LDS layout is:
295 * - TCS inputs for patch 0
296 * - TCS inputs for patch 1
297 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
298 * - ...
299 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
300 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
301 * - TCS outputs for patch 1
302 * - Per-patch TCS outputs for patch 1
303 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
304 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
305 * - ...
306 *
307 * All three shaders VS(LS), TCS, TES share the same LDS space.
308 */
309
310 static LLVMValueRef
311 get_tcs_in_patch_stride(struct si_shader_context *ctx)
312 {
313 return unpack_param(ctx, ctx->param_vs_state_bits, 8, 13);
314 }
315
316 static LLVMValueRef
317 get_tcs_out_patch_stride(struct si_shader_context *ctx)
318 {
319 return unpack_param(ctx, ctx->param_tcs_out_lds_layout, 0, 13);
320 }
321
322 static LLVMValueRef
323 get_tcs_out_patch0_offset(struct si_shader_context *ctx)
324 {
325 return lp_build_mul_imm(&ctx->bld_base.uint_bld,
326 unpack_param(ctx,
327 ctx->param_tcs_out_lds_offsets,
328 0, 16),
329 4);
330 }
331
332 static LLVMValueRef
333 get_tcs_out_patch0_patch_data_offset(struct si_shader_context *ctx)
334 {
335 return lp_build_mul_imm(&ctx->bld_base.uint_bld,
336 unpack_param(ctx,
337 ctx->param_tcs_out_lds_offsets,
338 16, 16),
339 4);
340 }
341
342 static LLVMValueRef
343 get_tcs_in_current_patch_offset(struct si_shader_context *ctx)
344 {
345 struct gallivm_state *gallivm = &ctx->gallivm;
346 LLVMValueRef patch_stride = get_tcs_in_patch_stride(ctx);
347 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
348
349 return LLVMBuildMul(gallivm->builder, patch_stride, rel_patch_id, "");
350 }
351
352 static LLVMValueRef
353 get_tcs_out_current_patch_offset(struct si_shader_context *ctx)
354 {
355 struct gallivm_state *gallivm = &ctx->gallivm;
356 LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(ctx);
357 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
358 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
359
360 return LLVMBuildAdd(gallivm->builder, patch0_offset,
361 LLVMBuildMul(gallivm->builder, patch_stride,
362 rel_patch_id, ""),
363 "");
364 }
365
366 static LLVMValueRef
367 get_tcs_out_current_patch_data_offset(struct si_shader_context *ctx)
368 {
369 struct gallivm_state *gallivm = &ctx->gallivm;
370 LLVMValueRef patch0_patch_data_offset =
371 get_tcs_out_patch0_patch_data_offset(ctx);
372 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
373 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
374
375 return LLVMBuildAdd(gallivm->builder, patch0_patch_data_offset,
376 LLVMBuildMul(gallivm->builder, patch_stride,
377 rel_patch_id, ""),
378 "");
379 }
380
381 static LLVMValueRef get_instance_index_for_fetch(
382 struct si_shader_context *ctx,
383 unsigned param_start_instance, LLVMValueRef divisor)
384 {
385 struct gallivm_state *gallivm = &ctx->gallivm;
386
387 LLVMValueRef result = ctx->abi.instance_id;
388
389 /* The division must be done before START_INSTANCE is added. */
390 if (divisor != ctx->i32_1)
391 result = LLVMBuildUDiv(gallivm->builder, result, divisor, "");
392
393 return LLVMBuildAdd(gallivm->builder, result,
394 LLVMGetParam(ctx->main_fn, param_start_instance), "");
395 }
396
397 /* Bitcast <4 x float> to <2 x double>, extract the component, and convert
398 * to float. */
399 static LLVMValueRef extract_double_to_float(struct si_shader_context *ctx,
400 LLVMValueRef vec4,
401 unsigned double_index)
402 {
403 LLVMBuilderRef builder = ctx->gallivm.builder;
404 LLVMTypeRef f64 = LLVMDoubleTypeInContext(ctx->gallivm.context);
405 LLVMValueRef dvec2 = LLVMBuildBitCast(builder, vec4,
406 LLVMVectorType(f64, 2), "");
407 LLVMValueRef index = LLVMConstInt(ctx->i32, double_index, 0);
408 LLVMValueRef value = LLVMBuildExtractElement(builder, dvec2, index, "");
409 return LLVMBuildFPTrunc(builder, value, ctx->f32, "");
410 }
411
412 static void declare_input_vs(
413 struct si_shader_context *ctx,
414 unsigned input_index,
415 const struct tgsi_full_declaration *decl,
416 LLVMValueRef out[4])
417 {
418 struct gallivm_state *gallivm = &ctx->gallivm;
419
420 unsigned chan;
421 unsigned fix_fetch;
422 unsigned num_fetches;
423 unsigned fetch_stride;
424
425 LLVMValueRef t_list_ptr;
426 LLVMValueRef t_offset;
427 LLVMValueRef t_list;
428 LLVMValueRef vertex_index;
429 LLVMValueRef input[3];
430
431 /* Load the T list */
432 t_list_ptr = LLVMGetParam(ctx->main_fn, ctx->param_vertex_buffers);
433
434 t_offset = LLVMConstInt(ctx->i32, input_index, 0);
435
436 t_list = ac_build_indexed_load_const(&ctx->ac, t_list_ptr, t_offset);
437
438 vertex_index = LLVMGetParam(ctx->main_fn,
439 ctx->param_vertex_index0 +
440 input_index);
441
442 fix_fetch = ctx->shader->key.mono.vs_fix_fetch[input_index];
443
444 /* Do multiple loads for special formats. */
445 switch (fix_fetch) {
446 case SI_FIX_FETCH_RGB_64_FLOAT:
447 num_fetches = 3; /* 3 2-dword loads */
448 fetch_stride = 8;
449 break;
450 case SI_FIX_FETCH_RGBA_64_FLOAT:
451 num_fetches = 2; /* 2 4-dword loads */
452 fetch_stride = 16;
453 break;
454 case SI_FIX_FETCH_RGB_8:
455 case SI_FIX_FETCH_RGB_8_INT:
456 num_fetches = 3;
457 fetch_stride = 1;
458 break;
459 case SI_FIX_FETCH_RGB_16:
460 case SI_FIX_FETCH_RGB_16_INT:
461 num_fetches = 3;
462 fetch_stride = 2;
463 break;
464 default:
465 num_fetches = 1;
466 fetch_stride = 0;
467 }
468
469 for (unsigned i = 0; i < num_fetches; i++) {
470 LLVMValueRef voffset = LLVMConstInt(ctx->i32, fetch_stride * i, 0);
471
472 input[i] = ac_build_buffer_load_format(&ctx->ac, t_list,
473 vertex_index, voffset,
474 true);
475 }
476
477 /* Break up the vec4 into individual components */
478 for (chan = 0; chan < 4; chan++) {
479 LLVMValueRef llvm_chan = LLVMConstInt(ctx->i32, chan, 0);
480 out[chan] = LLVMBuildExtractElement(gallivm->builder,
481 input[0], llvm_chan, "");
482 }
483
484 switch (fix_fetch) {
485 case SI_FIX_FETCH_A2_SNORM:
486 case SI_FIX_FETCH_A2_SSCALED:
487 case SI_FIX_FETCH_A2_SINT: {
488 /* The hardware returns an unsigned value; convert it to a
489 * signed one.
490 */
491 LLVMValueRef tmp = out[3];
492 LLVMValueRef c30 = LLVMConstInt(ctx->i32, 30, 0);
493
494 /* First, recover the sign-extended signed integer value. */
495 if (fix_fetch == SI_FIX_FETCH_A2_SSCALED)
496 tmp = LLVMBuildFPToUI(gallivm->builder, tmp, ctx->i32, "");
497 else
498 tmp = LLVMBuildBitCast(gallivm->builder, tmp, ctx->i32, "");
499
500 /* For the integer-like cases, do a natural sign extension.
501 *
502 * For the SNORM case, the values are 0.0, 0.333, 0.666, 1.0
503 * and happen to contain 0, 1, 2, 3 as the two LSBs of the
504 * exponent.
505 */
506 tmp = LLVMBuildShl(gallivm->builder, tmp,
507 fix_fetch == SI_FIX_FETCH_A2_SNORM ?
508 LLVMConstInt(ctx->i32, 7, 0) : c30, "");
509 tmp = LLVMBuildAShr(gallivm->builder, tmp, c30, "");
510
511 /* Convert back to the right type. */
512 if (fix_fetch == SI_FIX_FETCH_A2_SNORM) {
513 LLVMValueRef clamp;
514 LLVMValueRef neg_one = LLVMConstReal(ctx->f32, -1.0);
515 tmp = LLVMBuildSIToFP(gallivm->builder, tmp, ctx->f32, "");
516 clamp = LLVMBuildFCmp(gallivm->builder, LLVMRealULT, tmp, neg_one, "");
517 tmp = LLVMBuildSelect(gallivm->builder, clamp, neg_one, tmp, "");
518 } else if (fix_fetch == SI_FIX_FETCH_A2_SSCALED) {
519 tmp = LLVMBuildSIToFP(gallivm->builder, tmp, ctx->f32, "");
520 }
521
522 out[3] = tmp;
523 break;
524 }
525 case SI_FIX_FETCH_RGBA_32_UNORM:
526 case SI_FIX_FETCH_RGBX_32_UNORM:
527 for (chan = 0; chan < 4; chan++) {
528 out[chan] = LLVMBuildBitCast(gallivm->builder, out[chan],
529 ctx->i32, "");
530 out[chan] = LLVMBuildUIToFP(gallivm->builder,
531 out[chan], ctx->f32, "");
532 out[chan] = LLVMBuildFMul(gallivm->builder, out[chan],
533 LLVMConstReal(ctx->f32, 1.0 / UINT_MAX), "");
534 }
535 /* RGBX UINT returns 1 in alpha, which would be rounded to 0 by normalizing. */
536 if (fix_fetch == SI_FIX_FETCH_RGBX_32_UNORM)
537 out[3] = LLVMConstReal(ctx->f32, 1);
538 break;
539 case SI_FIX_FETCH_RGBA_32_SNORM:
540 case SI_FIX_FETCH_RGBX_32_SNORM:
541 case SI_FIX_FETCH_RGBA_32_FIXED:
542 case SI_FIX_FETCH_RGBX_32_FIXED: {
543 double scale;
544 if (fix_fetch >= SI_FIX_FETCH_RGBA_32_FIXED)
545 scale = 1.0 / 0x10000;
546 else
547 scale = 1.0 / INT_MAX;
548
549 for (chan = 0; chan < 4; chan++) {
550 out[chan] = LLVMBuildBitCast(gallivm->builder, out[chan],
551 ctx->i32, "");
552 out[chan] = LLVMBuildSIToFP(gallivm->builder,
553 out[chan], ctx->f32, "");
554 out[chan] = LLVMBuildFMul(gallivm->builder, out[chan],
555 LLVMConstReal(ctx->f32, scale), "");
556 }
557 /* RGBX SINT returns 1 in alpha, which would be rounded to 0 by normalizing. */
558 if (fix_fetch == SI_FIX_FETCH_RGBX_32_SNORM ||
559 fix_fetch == SI_FIX_FETCH_RGBX_32_FIXED)
560 out[3] = LLVMConstReal(ctx->f32, 1);
561 break;
562 }
563 case SI_FIX_FETCH_RGBA_32_USCALED:
564 for (chan = 0; chan < 4; chan++) {
565 out[chan] = LLVMBuildBitCast(gallivm->builder, out[chan],
566 ctx->i32, "");
567 out[chan] = LLVMBuildUIToFP(gallivm->builder,
568 out[chan], ctx->f32, "");
569 }
570 break;
571 case SI_FIX_FETCH_RGBA_32_SSCALED:
572 for (chan = 0; chan < 4; chan++) {
573 out[chan] = LLVMBuildBitCast(gallivm->builder, out[chan],
574 ctx->i32, "");
575 out[chan] = LLVMBuildSIToFP(gallivm->builder,
576 out[chan], ctx->f32, "");
577 }
578 break;
579 case SI_FIX_FETCH_RG_64_FLOAT:
580 for (chan = 0; chan < 2; chan++)
581 out[chan] = extract_double_to_float(ctx, input[0], chan);
582
583 out[2] = LLVMConstReal(ctx->f32, 0);
584 out[3] = LLVMConstReal(ctx->f32, 1);
585 break;
586 case SI_FIX_FETCH_RGB_64_FLOAT:
587 for (chan = 0; chan < 3; chan++)
588 out[chan] = extract_double_to_float(ctx, input[chan], 0);
589
590 out[3] = LLVMConstReal(ctx->f32, 1);
591 break;
592 case SI_FIX_FETCH_RGBA_64_FLOAT:
593 for (chan = 0; chan < 4; chan++) {
594 out[chan] = extract_double_to_float(ctx, input[chan / 2],
595 chan % 2);
596 }
597 break;
598 case SI_FIX_FETCH_RGB_8:
599 case SI_FIX_FETCH_RGB_8_INT:
600 case SI_FIX_FETCH_RGB_16:
601 case SI_FIX_FETCH_RGB_16_INT:
602 for (chan = 0; chan < 3; chan++) {
603 out[chan] = LLVMBuildExtractElement(gallivm->builder,
604 input[chan],
605 ctx->i32_0, "");
606 }
607 if (fix_fetch == SI_FIX_FETCH_RGB_8 ||
608 fix_fetch == SI_FIX_FETCH_RGB_16) {
609 out[3] = LLVMConstReal(ctx->f32, 1);
610 } else {
611 out[3] = LLVMBuildBitCast(gallivm->builder, ctx->i32_1,
612 ctx->f32, "");
613 }
614 break;
615 }
616 }
617
618
619 static LLVMValueRef get_primitive_id(struct si_shader_context *ctx,
620 unsigned swizzle)
621 {
622 if (swizzle > 0)
623 return ctx->i32_0;
624
625 switch (ctx->type) {
626 case PIPE_SHADER_VERTEX:
627 return LLVMGetParam(ctx->main_fn,
628 ctx->param_vs_prim_id);
629 case PIPE_SHADER_TESS_CTRL:
630 return LLVMGetParam(ctx->main_fn,
631 ctx->param_tcs_patch_id);
632 case PIPE_SHADER_TESS_EVAL:
633 return LLVMGetParam(ctx->main_fn,
634 ctx->param_tes_patch_id);
635 case PIPE_SHADER_GEOMETRY:
636 return LLVMGetParam(ctx->main_fn,
637 ctx->param_gs_prim_id);
638 default:
639 assert(0);
640 return ctx->i32_0;
641 }
642 }
643
644 /**
645 * Return the value of tgsi_ind_register for indexing.
646 * This is the indirect index with the constant offset added to it.
647 */
648 static LLVMValueRef get_indirect_index(struct si_shader_context *ctx,
649 const struct tgsi_ind_register *ind,
650 int rel_index)
651 {
652 struct gallivm_state *gallivm = &ctx->gallivm;
653 LLVMValueRef result;
654
655 result = ctx->addrs[ind->Index][ind->Swizzle];
656 result = LLVMBuildLoad(gallivm->builder, result, "");
657 result = LLVMBuildAdd(gallivm->builder, result,
658 LLVMConstInt(ctx->i32, rel_index, 0), "");
659 return result;
660 }
661
662 /**
663 * Like get_indirect_index, but restricts the return value to a (possibly
664 * undefined) value inside [0..num).
665 */
666 LLVMValueRef si_get_bounded_indirect_index(struct si_shader_context *ctx,
667 const struct tgsi_ind_register *ind,
668 int rel_index, unsigned num)
669 {
670 LLVMValueRef result = get_indirect_index(ctx, ind, rel_index);
671
672 return si_llvm_bound_index(ctx, result, num);
673 }
674
675
676 /**
677 * Calculate a dword address given an input or output register and a stride.
678 */
679 static LLVMValueRef get_dw_address(struct si_shader_context *ctx,
680 const struct tgsi_full_dst_register *dst,
681 const struct tgsi_full_src_register *src,
682 LLVMValueRef vertex_dw_stride,
683 LLVMValueRef base_addr)
684 {
685 struct gallivm_state *gallivm = &ctx->gallivm;
686 struct tgsi_shader_info *info = &ctx->shader->selector->info;
687 ubyte *name, *index, *array_first;
688 int first, param;
689 struct tgsi_full_dst_register reg;
690
691 /* Set the register description. The address computation is the same
692 * for sources and destinations. */
693 if (src) {
694 reg.Register.File = src->Register.File;
695 reg.Register.Index = src->Register.Index;
696 reg.Register.Indirect = src->Register.Indirect;
697 reg.Register.Dimension = src->Register.Dimension;
698 reg.Indirect = src->Indirect;
699 reg.Dimension = src->Dimension;
700 reg.DimIndirect = src->DimIndirect;
701 } else
702 reg = *dst;
703
704 /* If the register is 2-dimensional (e.g. an array of vertices
705 * in a primitive), calculate the base address of the vertex. */
706 if (reg.Register.Dimension) {
707 LLVMValueRef index;
708
709 if (reg.Dimension.Indirect)
710 index = get_indirect_index(ctx, &reg.DimIndirect,
711 reg.Dimension.Index);
712 else
713 index = LLVMConstInt(ctx->i32, reg.Dimension.Index, 0);
714
715 base_addr = LLVMBuildAdd(gallivm->builder, base_addr,
716 LLVMBuildMul(gallivm->builder, index,
717 vertex_dw_stride, ""), "");
718 }
719
720 /* Get information about the register. */
721 if (reg.Register.File == TGSI_FILE_INPUT) {
722 name = info->input_semantic_name;
723 index = info->input_semantic_index;
724 array_first = info->input_array_first;
725 } else if (reg.Register.File == TGSI_FILE_OUTPUT) {
726 name = info->output_semantic_name;
727 index = info->output_semantic_index;
728 array_first = info->output_array_first;
729 } else {
730 assert(0);
731 return NULL;
732 }
733
734 if (reg.Register.Indirect) {
735 /* Add the relative address of the element. */
736 LLVMValueRef ind_index;
737
738 if (reg.Indirect.ArrayID)
739 first = array_first[reg.Indirect.ArrayID];
740 else
741 first = reg.Register.Index;
742
743 ind_index = get_indirect_index(ctx, &reg.Indirect,
744 reg.Register.Index - first);
745
746 base_addr = LLVMBuildAdd(gallivm->builder, base_addr,
747 LLVMBuildMul(gallivm->builder, ind_index,
748 LLVMConstInt(ctx->i32, 4, 0), ""), "");
749
750 param = reg.Register.Dimension ?
751 si_shader_io_get_unique_index(name[first], index[first]) :
752 si_shader_io_get_unique_index_patch(name[first], index[first]);
753 } else {
754 param = reg.Register.Dimension ?
755 si_shader_io_get_unique_index(name[reg.Register.Index],
756 index[reg.Register.Index]) :
757 si_shader_io_get_unique_index_patch(name[reg.Register.Index],
758 index[reg.Register.Index]);
759 }
760
761 /* Add the base address of the element. */
762 return LLVMBuildAdd(gallivm->builder, base_addr,
763 LLVMConstInt(ctx->i32, param * 4, 0), "");
764 }
765
766 /* The offchip buffer layout for TCS->TES is
767 *
768 * - attribute 0 of patch 0 vertex 0
769 * - attribute 0 of patch 0 vertex 1
770 * - attribute 0 of patch 0 vertex 2
771 * ...
772 * - attribute 0 of patch 1 vertex 0
773 * - attribute 0 of patch 1 vertex 1
774 * ...
775 * - attribute 1 of patch 0 vertex 0
776 * - attribute 1 of patch 0 vertex 1
777 * ...
778 * - per patch attribute 0 of patch 0
779 * - per patch attribute 0 of patch 1
780 * ...
781 *
782 * Note that every attribute has 4 components.
783 */
784 static LLVMValueRef get_tcs_tes_buffer_address(struct si_shader_context *ctx,
785 LLVMValueRef rel_patch_id,
786 LLVMValueRef vertex_index,
787 LLVMValueRef param_index)
788 {
789 struct gallivm_state *gallivm = &ctx->gallivm;
790 LLVMValueRef base_addr, vertices_per_patch, num_patches, total_vertices;
791 LLVMValueRef param_stride, constant16;
792
793 vertices_per_patch = unpack_param(ctx, ctx->param_tcs_offchip_layout, 6, 6);
794 num_patches = unpack_param(ctx, ctx->param_tcs_offchip_layout, 0, 6);
795 total_vertices = LLVMBuildMul(gallivm->builder, vertices_per_patch,
796 num_patches, "");
797
798 constant16 = LLVMConstInt(ctx->i32, 16, 0);
799 if (vertex_index) {
800 base_addr = LLVMBuildMul(gallivm->builder, rel_patch_id,
801 vertices_per_patch, "");
802
803 base_addr = LLVMBuildAdd(gallivm->builder, base_addr,
804 vertex_index, "");
805
806 param_stride = total_vertices;
807 } else {
808 base_addr = rel_patch_id;
809 param_stride = num_patches;
810 }
811
812 base_addr = LLVMBuildAdd(gallivm->builder, base_addr,
813 LLVMBuildMul(gallivm->builder, param_index,
814 param_stride, ""), "");
815
816 base_addr = LLVMBuildMul(gallivm->builder, base_addr, constant16, "");
817
818 if (!vertex_index) {
819 LLVMValueRef patch_data_offset =
820 unpack_param(ctx, ctx->param_tcs_offchip_layout, 12, 20);
821
822 base_addr = LLVMBuildAdd(gallivm->builder, base_addr,
823 patch_data_offset, "");
824 }
825 return base_addr;
826 }
827
828 static LLVMValueRef get_tcs_tes_buffer_address_from_reg(
829 struct si_shader_context *ctx,
830 const struct tgsi_full_dst_register *dst,
831 const struct tgsi_full_src_register *src)
832 {
833 struct gallivm_state *gallivm = &ctx->gallivm;
834 struct tgsi_shader_info *info = &ctx->shader->selector->info;
835 ubyte *name, *index, *array_first;
836 struct tgsi_full_src_register reg;
837 LLVMValueRef vertex_index = NULL;
838 LLVMValueRef param_index = NULL;
839 unsigned param_index_base, param_base;
840
841 reg = src ? *src : tgsi_full_src_register_from_dst(dst);
842
843 if (reg.Register.Dimension) {
844
845 if (reg.Dimension.Indirect)
846 vertex_index = get_indirect_index(ctx, &reg.DimIndirect,
847 reg.Dimension.Index);
848 else
849 vertex_index = LLVMConstInt(ctx->i32, reg.Dimension.Index, 0);
850 }
851
852 /* Get information about the register. */
853 if (reg.Register.File == TGSI_FILE_INPUT) {
854 name = info->input_semantic_name;
855 index = info->input_semantic_index;
856 array_first = info->input_array_first;
857 } else if (reg.Register.File == TGSI_FILE_OUTPUT) {
858 name = info->output_semantic_name;
859 index = info->output_semantic_index;
860 array_first = info->output_array_first;
861 } else {
862 assert(0);
863 return NULL;
864 }
865
866 if (reg.Register.Indirect) {
867 if (reg.Indirect.ArrayID)
868 param_base = array_first[reg.Indirect.ArrayID];
869 else
870 param_base = reg.Register.Index;
871
872 param_index = get_indirect_index(ctx, &reg.Indirect,
873 reg.Register.Index - param_base);
874
875 } else {
876 param_base = reg.Register.Index;
877 param_index = ctx->i32_0;
878 }
879
880 param_index_base = reg.Register.Dimension ?
881 si_shader_io_get_unique_index(name[param_base], index[param_base]) :
882 si_shader_io_get_unique_index_patch(name[param_base], index[param_base]);
883
884 param_index = LLVMBuildAdd(gallivm->builder, param_index,
885 LLVMConstInt(ctx->i32, param_index_base, 0),
886 "");
887
888 return get_tcs_tes_buffer_address(ctx, get_rel_patch_id(ctx),
889 vertex_index, param_index);
890 }
891
892 static LLVMValueRef buffer_load(struct lp_build_tgsi_context *bld_base,
893 enum tgsi_opcode_type type, unsigned swizzle,
894 LLVMValueRef buffer, LLVMValueRef offset,
895 LLVMValueRef base, bool can_speculate)
896 {
897 struct si_shader_context *ctx = si_shader_context(bld_base);
898 struct gallivm_state *gallivm = &ctx->gallivm;
899 LLVMValueRef value, value2;
900 LLVMTypeRef llvm_type = tgsi2llvmtype(bld_base, type);
901 LLVMTypeRef vec_type = LLVMVectorType(llvm_type, 4);
902
903 if (swizzle == ~0) {
904 value = ac_build_buffer_load(&ctx->ac, buffer, 4, NULL, base, offset,
905 0, 1, 0, can_speculate, false);
906
907 return LLVMBuildBitCast(gallivm->builder, value, vec_type, "");
908 }
909
910 if (!tgsi_type_is_64bit(type)) {
911 value = ac_build_buffer_load(&ctx->ac, buffer, 4, NULL, base, offset,
912 0, 1, 0, can_speculate, false);
913
914 value = LLVMBuildBitCast(gallivm->builder, value, vec_type, "");
915 return LLVMBuildExtractElement(gallivm->builder, value,
916 LLVMConstInt(ctx->i32, swizzle, 0), "");
917 }
918
919 value = ac_build_buffer_load(&ctx->ac, buffer, 1, NULL, base, offset,
920 swizzle * 4, 1, 0, can_speculate, false);
921
922 value2 = ac_build_buffer_load(&ctx->ac, buffer, 1, NULL, base, offset,
923 swizzle * 4 + 4, 1, 0, can_speculate, false);
924
925 return si_llvm_emit_fetch_64bit(bld_base, type, value, value2);
926 }
927
928 /**
929 * Load from LDS.
930 *
931 * \param type output value type
932 * \param swizzle offset (typically 0..3); it can be ~0, which loads a vec4
933 * \param dw_addr address in dwords
934 */
935 static LLVMValueRef lds_load(struct lp_build_tgsi_context *bld_base,
936 enum tgsi_opcode_type type, unsigned swizzle,
937 LLVMValueRef dw_addr)
938 {
939 struct si_shader_context *ctx = si_shader_context(bld_base);
940 struct gallivm_state *gallivm = &ctx->gallivm;
941 LLVMValueRef value;
942
943 if (swizzle == ~0) {
944 LLVMValueRef values[TGSI_NUM_CHANNELS];
945
946 for (unsigned chan = 0; chan < TGSI_NUM_CHANNELS; chan++)
947 values[chan] = lds_load(bld_base, type, chan, dw_addr);
948
949 return lp_build_gather_values(gallivm, values,
950 TGSI_NUM_CHANNELS);
951 }
952
953 dw_addr = lp_build_add(&bld_base->uint_bld, dw_addr,
954 LLVMConstInt(ctx->i32, swizzle, 0));
955
956 value = ac_build_indexed_load(&ctx->ac, ctx->lds, dw_addr, false);
957 if (tgsi_type_is_64bit(type)) {
958 LLVMValueRef value2;
959 dw_addr = lp_build_add(&bld_base->uint_bld, dw_addr,
960 ctx->i32_1);
961 value2 = ac_build_indexed_load(&ctx->ac, ctx->lds, dw_addr, false);
962 return si_llvm_emit_fetch_64bit(bld_base, type, value, value2);
963 }
964
965 return LLVMBuildBitCast(gallivm->builder, value,
966 tgsi2llvmtype(bld_base, type), "");
967 }
968
969 /**
970 * Store to LDS.
971 *
972 * \param swizzle offset (typically 0..3)
973 * \param dw_addr address in dwords
974 * \param value value to store
975 */
976 static void lds_store(struct lp_build_tgsi_context *bld_base,
977 unsigned dw_offset_imm, LLVMValueRef dw_addr,
978 LLVMValueRef value)
979 {
980 struct si_shader_context *ctx = si_shader_context(bld_base);
981 struct gallivm_state *gallivm = &ctx->gallivm;
982
983 dw_addr = lp_build_add(&bld_base->uint_bld, dw_addr,
984 LLVMConstInt(ctx->i32, dw_offset_imm, 0));
985
986 value = LLVMBuildBitCast(gallivm->builder, value, ctx->i32, "");
987 ac_build_indexed_store(&ctx->ac, ctx->lds,
988 dw_addr, value);
989 }
990
991 static LLVMValueRef desc_from_addr_base64k(struct si_shader_context *ctx,
992 unsigned param)
993 {
994 LLVMBuilderRef builder = ctx->gallivm.builder;
995
996 LLVMValueRef addr = LLVMGetParam(ctx->main_fn, param);
997 addr = LLVMBuildZExt(builder, addr, ctx->i64, "");
998 addr = LLVMBuildShl(builder, addr, LLVMConstInt(ctx->i64, 16, 0), "");
999
1000 uint64_t desc2 = 0xffffffff;
1001 uint64_t desc3 = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1002 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1003 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1004 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1005 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1006 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
1007 LLVMValueRef hi = LLVMConstInt(ctx->i64, desc2 | (desc3 << 32), 0);
1008
1009 LLVMValueRef desc = LLVMGetUndef(LLVMVectorType(ctx->i64, 2));
1010 desc = LLVMBuildInsertElement(builder, desc, addr, ctx->i32_0, "");
1011 desc = LLVMBuildInsertElement(builder, desc, hi, ctx->i32_1, "");
1012 return LLVMBuildBitCast(builder, desc, ctx->v4i32, "");
1013 }
1014
1015 static LLVMValueRef fetch_input_tcs(
1016 struct lp_build_tgsi_context *bld_base,
1017 const struct tgsi_full_src_register *reg,
1018 enum tgsi_opcode_type type, unsigned swizzle)
1019 {
1020 struct si_shader_context *ctx = si_shader_context(bld_base);
1021 LLVMValueRef dw_addr, stride;
1022
1023 stride = unpack_param(ctx, ctx->param_vs_state_bits, 24, 8);
1024 dw_addr = get_tcs_in_current_patch_offset(ctx);
1025 dw_addr = get_dw_address(ctx, NULL, reg, stride, dw_addr);
1026
1027 return lds_load(bld_base, type, swizzle, dw_addr);
1028 }
1029
1030 static LLVMValueRef fetch_output_tcs(
1031 struct lp_build_tgsi_context *bld_base,
1032 const struct tgsi_full_src_register *reg,
1033 enum tgsi_opcode_type type, unsigned swizzle)
1034 {
1035 struct si_shader_context *ctx = si_shader_context(bld_base);
1036 LLVMValueRef dw_addr, stride;
1037
1038 if (reg->Register.Dimension) {
1039 stride = unpack_param(ctx, ctx->param_tcs_out_lds_layout, 13, 8);
1040 dw_addr = get_tcs_out_current_patch_offset(ctx);
1041 dw_addr = get_dw_address(ctx, NULL, reg, stride, dw_addr);
1042 } else {
1043 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1044 dw_addr = get_dw_address(ctx, NULL, reg, NULL, dw_addr);
1045 }
1046
1047 return lds_load(bld_base, type, swizzle, dw_addr);
1048 }
1049
1050 static LLVMValueRef fetch_input_tes(
1051 struct lp_build_tgsi_context *bld_base,
1052 const struct tgsi_full_src_register *reg,
1053 enum tgsi_opcode_type type, unsigned swizzle)
1054 {
1055 struct si_shader_context *ctx = si_shader_context(bld_base);
1056 LLVMValueRef buffer, base, addr;
1057
1058 buffer = desc_from_addr_base64k(ctx, ctx->param_tcs_offchip_addr_base64k);
1059
1060 base = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
1061 addr = get_tcs_tes_buffer_address_from_reg(ctx, NULL, reg);
1062
1063 return buffer_load(bld_base, type, swizzle, buffer, base, addr, true);
1064 }
1065
1066 static void store_output_tcs(struct lp_build_tgsi_context *bld_base,
1067 const struct tgsi_full_instruction *inst,
1068 const struct tgsi_opcode_info *info,
1069 LLVMValueRef dst[4])
1070 {
1071 struct si_shader_context *ctx = si_shader_context(bld_base);
1072 struct gallivm_state *gallivm = &ctx->gallivm;
1073 const struct tgsi_full_dst_register *reg = &inst->Dst[0];
1074 const struct tgsi_shader_info *sh_info = &ctx->shader->selector->info;
1075 unsigned chan_index;
1076 LLVMValueRef dw_addr, stride;
1077 LLVMValueRef buffer, base, buf_addr;
1078 LLVMValueRef values[4];
1079 bool skip_lds_store;
1080 bool is_tess_factor = false;
1081
1082 /* Only handle per-patch and per-vertex outputs here.
1083 * Vectors will be lowered to scalars and this function will be called again.
1084 */
1085 if (reg->Register.File != TGSI_FILE_OUTPUT ||
1086 (dst[0] && LLVMGetTypeKind(LLVMTypeOf(dst[0])) == LLVMVectorTypeKind)) {
1087 si_llvm_emit_store(bld_base, inst, info, dst);
1088 return;
1089 }
1090
1091 if (reg->Register.Dimension) {
1092 stride = unpack_param(ctx, ctx->param_tcs_out_lds_layout, 13, 8);
1093 dw_addr = get_tcs_out_current_patch_offset(ctx);
1094 dw_addr = get_dw_address(ctx, reg, NULL, stride, dw_addr);
1095 skip_lds_store = !sh_info->reads_pervertex_outputs;
1096 } else {
1097 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1098 dw_addr = get_dw_address(ctx, reg, NULL, NULL, dw_addr);
1099 skip_lds_store = !sh_info->reads_perpatch_outputs;
1100
1101 if (!reg->Register.Indirect) {
1102 int name = sh_info->output_semantic_name[reg->Register.Index];
1103
1104 /* Always write tess factors into LDS for the TCS epilog. */
1105 if (name == TGSI_SEMANTIC_TESSINNER ||
1106 name == TGSI_SEMANTIC_TESSOUTER) {
1107 skip_lds_store = false;
1108 is_tess_factor = true;
1109 }
1110 }
1111 }
1112
1113 buffer = desc_from_addr_base64k(ctx, ctx->param_tcs_offchip_addr_base64k);
1114
1115 base = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
1116 buf_addr = get_tcs_tes_buffer_address_from_reg(ctx, reg, NULL);
1117
1118
1119 TGSI_FOR_EACH_DST0_ENABLED_CHANNEL(inst, chan_index) {
1120 LLVMValueRef value = dst[chan_index];
1121
1122 if (inst->Instruction.Saturate)
1123 value = ac_build_clamp(&ctx->ac, value);
1124
1125 /* Skip LDS stores if there is no LDS read of this output. */
1126 if (!skip_lds_store)
1127 lds_store(bld_base, chan_index, dw_addr, value);
1128
1129 value = LLVMBuildBitCast(gallivm->builder, value, ctx->i32, "");
1130 values[chan_index] = value;
1131
1132 if (inst->Dst[0].Register.WriteMask != 0xF && !is_tess_factor) {
1133 ac_build_buffer_store_dword(&ctx->ac, buffer, value, 1,
1134 buf_addr, base,
1135 4 * chan_index, 1, 0, true, false);
1136 }
1137 }
1138
1139 if (inst->Dst[0].Register.WriteMask == 0xF && !is_tess_factor) {
1140 LLVMValueRef value = lp_build_gather_values(gallivm,
1141 values, 4);
1142 ac_build_buffer_store_dword(&ctx->ac, buffer, value, 4, buf_addr,
1143 base, 0, 1, 0, true, false);
1144 }
1145 }
1146
1147 static LLVMValueRef fetch_input_gs(
1148 struct lp_build_tgsi_context *bld_base,
1149 const struct tgsi_full_src_register *reg,
1150 enum tgsi_opcode_type type,
1151 unsigned swizzle)
1152 {
1153 struct si_shader_context *ctx = si_shader_context(bld_base);
1154 struct si_shader *shader = ctx->shader;
1155 struct lp_build_context *uint = &ctx->bld_base.uint_bld;
1156 struct gallivm_state *gallivm = &ctx->gallivm;
1157 LLVMValueRef vtx_offset, soffset;
1158 struct tgsi_shader_info *info = &shader->selector->info;
1159 unsigned semantic_name = info->input_semantic_name[reg->Register.Index];
1160 unsigned semantic_index = info->input_semantic_index[reg->Register.Index];
1161 unsigned param;
1162 LLVMValueRef value;
1163
1164 if (swizzle != ~0 && semantic_name == TGSI_SEMANTIC_PRIMID)
1165 return get_primitive_id(ctx, swizzle);
1166
1167 if (!reg->Register.Dimension)
1168 return NULL;
1169
1170 param = si_shader_io_get_unique_index(semantic_name, semantic_index);
1171
1172 /* GFX9 has the ESGS ring in LDS. */
1173 if (ctx->screen->b.chip_class >= GFX9) {
1174 unsigned index = reg->Dimension.Index;
1175
1176 switch (index / 2) {
1177 case 0:
1178 vtx_offset = unpack_param(ctx, ctx->param_gs_vtx01_offset,
1179 index % 2 ? 16 : 0, 16);
1180 break;
1181 case 1:
1182 vtx_offset = unpack_param(ctx, ctx->param_gs_vtx23_offset,
1183 index % 2 ? 16 : 0, 16);
1184 break;
1185 case 2:
1186 vtx_offset = unpack_param(ctx, ctx->param_gs_vtx45_offset,
1187 index % 2 ? 16 : 0, 16);
1188 break;
1189 default:
1190 assert(0);
1191 return NULL;
1192 }
1193
1194 vtx_offset = LLVMBuildAdd(gallivm->builder, vtx_offset,
1195 LLVMConstInt(ctx->i32, param * 4, 0), "");
1196 return lds_load(bld_base, type, swizzle, vtx_offset);
1197 }
1198
1199 /* GFX6: input load from the ESGS ring in memory. */
1200 if (swizzle == ~0) {
1201 LLVMValueRef values[TGSI_NUM_CHANNELS];
1202 unsigned chan;
1203 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1204 values[chan] = fetch_input_gs(bld_base, reg, type, chan);
1205 }
1206 return lp_build_gather_values(gallivm, values,
1207 TGSI_NUM_CHANNELS);
1208 }
1209
1210 /* Get the vertex offset parameter on GFX6. */
1211 unsigned vtx_offset_param = reg->Dimension.Index;
1212 if (vtx_offset_param < 2) {
1213 vtx_offset_param += ctx->param_gs_vtx0_offset;
1214 } else {
1215 assert(vtx_offset_param < 6);
1216 vtx_offset_param += ctx->param_gs_vtx2_offset - 2;
1217 }
1218 vtx_offset = lp_build_mul_imm(uint,
1219 LLVMGetParam(ctx->main_fn,
1220 vtx_offset_param),
1221 4);
1222
1223 soffset = LLVMConstInt(ctx->i32, (param * 4 + swizzle) * 256, 0);
1224
1225 value = ac_build_buffer_load(&ctx->ac, ctx->esgs_ring, 1, ctx->i32_0,
1226 vtx_offset, soffset, 0, 1, 0, true, false);
1227 if (tgsi_type_is_64bit(type)) {
1228 LLVMValueRef value2;
1229 soffset = LLVMConstInt(ctx->i32, (param * 4 + swizzle + 1) * 256, 0);
1230
1231 value2 = ac_build_buffer_load(&ctx->ac, ctx->esgs_ring, 1,
1232 ctx->i32_0, vtx_offset, soffset,
1233 0, 1, 0, true, false);
1234 return si_llvm_emit_fetch_64bit(bld_base, type,
1235 value, value2);
1236 }
1237 return LLVMBuildBitCast(gallivm->builder,
1238 value,
1239 tgsi2llvmtype(bld_base, type), "");
1240 }
1241
1242 static int lookup_interp_param_index(unsigned interpolate, unsigned location)
1243 {
1244 switch (interpolate) {
1245 case TGSI_INTERPOLATE_CONSTANT:
1246 return 0;
1247
1248 case TGSI_INTERPOLATE_LINEAR:
1249 if (location == TGSI_INTERPOLATE_LOC_SAMPLE)
1250 return SI_PARAM_LINEAR_SAMPLE;
1251 else if (location == TGSI_INTERPOLATE_LOC_CENTROID)
1252 return SI_PARAM_LINEAR_CENTROID;
1253 else
1254 return SI_PARAM_LINEAR_CENTER;
1255 break;
1256 case TGSI_INTERPOLATE_COLOR:
1257 case TGSI_INTERPOLATE_PERSPECTIVE:
1258 if (location == TGSI_INTERPOLATE_LOC_SAMPLE)
1259 return SI_PARAM_PERSP_SAMPLE;
1260 else if (location == TGSI_INTERPOLATE_LOC_CENTROID)
1261 return SI_PARAM_PERSP_CENTROID;
1262 else
1263 return SI_PARAM_PERSP_CENTER;
1264 break;
1265 default:
1266 fprintf(stderr, "Warning: Unhandled interpolation mode.\n");
1267 return -1;
1268 }
1269 }
1270
1271 static LLVMValueRef si_build_fs_interp(struct si_shader_context *ctx,
1272 unsigned attr_index, unsigned chan,
1273 LLVMValueRef prim_mask,
1274 LLVMValueRef i, LLVMValueRef j)
1275 {
1276 if (i || j) {
1277 return ac_build_fs_interp(&ctx->ac,
1278 LLVMConstInt(ctx->i32, chan, 0),
1279 LLVMConstInt(ctx->i32, attr_index, 0),
1280 prim_mask, i, j);
1281 }
1282 return ac_build_fs_interp_mov(&ctx->ac,
1283 LLVMConstInt(ctx->i32, 2, 0), /* P0 */
1284 LLVMConstInt(ctx->i32, chan, 0),
1285 LLVMConstInt(ctx->i32, attr_index, 0),
1286 prim_mask);
1287 }
1288
1289 /**
1290 * Interpolate a fragment shader input.
1291 *
1292 * @param ctx context
1293 * @param input_index index of the input in hardware
1294 * @param semantic_name TGSI_SEMANTIC_*
1295 * @param semantic_index semantic index
1296 * @param num_interp_inputs number of all interpolated inputs (= BCOLOR offset)
1297 * @param colors_read_mask color components read (4 bits for each color, 8 bits in total)
1298 * @param interp_param interpolation weights (i,j)
1299 * @param prim_mask SI_PARAM_PRIM_MASK
1300 * @param face SI_PARAM_FRONT_FACE
1301 * @param result the return value (4 components)
1302 */
1303 static void interp_fs_input(struct si_shader_context *ctx,
1304 unsigned input_index,
1305 unsigned semantic_name,
1306 unsigned semantic_index,
1307 unsigned num_interp_inputs,
1308 unsigned colors_read_mask,
1309 LLVMValueRef interp_param,
1310 LLVMValueRef prim_mask,
1311 LLVMValueRef face,
1312 LLVMValueRef result[4])
1313 {
1314 struct gallivm_state *gallivm = &ctx->gallivm;
1315 LLVMValueRef i = NULL, j = NULL;
1316 unsigned chan;
1317
1318 /* fs.constant returns the param from the middle vertex, so it's not
1319 * really useful for flat shading. It's meant to be used for custom
1320 * interpolation (but the intrinsic can't fetch from the other two
1321 * vertices).
1322 *
1323 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
1324 * to do the right thing. The only reason we use fs.constant is that
1325 * fs.interp cannot be used on integers, because they can be equal
1326 * to NaN.
1327 *
1328 * When interp is false we will use fs.constant or for newer llvm,
1329 * amdgcn.interp.mov.
1330 */
1331 bool interp = interp_param != NULL;
1332
1333 if (interp) {
1334 interp_param = LLVMBuildBitCast(gallivm->builder, interp_param,
1335 LLVMVectorType(ctx->f32, 2), "");
1336
1337 i = LLVMBuildExtractElement(gallivm->builder, interp_param,
1338 ctx->i32_0, "");
1339 j = LLVMBuildExtractElement(gallivm->builder, interp_param,
1340 ctx->i32_1, "");
1341 }
1342
1343 if (semantic_name == TGSI_SEMANTIC_COLOR &&
1344 ctx->shader->key.part.ps.prolog.color_two_side) {
1345 LLVMValueRef is_face_positive;
1346
1347 /* If BCOLOR0 is used, BCOLOR1 is at offset "num_inputs + 1",
1348 * otherwise it's at offset "num_inputs".
1349 */
1350 unsigned back_attr_offset = num_interp_inputs;
1351 if (semantic_index == 1 && colors_read_mask & 0xf)
1352 back_attr_offset += 1;
1353
1354 is_face_positive = LLVMBuildICmp(gallivm->builder, LLVMIntNE,
1355 face, ctx->i32_0, "");
1356
1357 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1358 LLVMValueRef front, back;
1359
1360 front = si_build_fs_interp(ctx,
1361 input_index, chan,
1362 prim_mask, i, j);
1363 back = si_build_fs_interp(ctx,
1364 back_attr_offset, chan,
1365 prim_mask, i, j);
1366
1367 result[chan] = LLVMBuildSelect(gallivm->builder,
1368 is_face_positive,
1369 front,
1370 back,
1371 "");
1372 }
1373 } else if (semantic_name == TGSI_SEMANTIC_FOG) {
1374 result[0] = si_build_fs_interp(ctx, input_index,
1375 0, prim_mask, i, j);
1376 result[1] =
1377 result[2] = LLVMConstReal(ctx->f32, 0.0f);
1378 result[3] = LLVMConstReal(ctx->f32, 1.0f);
1379 } else {
1380 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1381 result[chan] = si_build_fs_interp(ctx,
1382 input_index, chan,
1383 prim_mask, i, j);
1384 }
1385 }
1386 }
1387
1388 static void declare_input_fs(
1389 struct si_shader_context *ctx,
1390 unsigned input_index,
1391 const struct tgsi_full_declaration *decl,
1392 LLVMValueRef out[4])
1393 {
1394 struct lp_build_context *base = &ctx->bld_base.base;
1395 struct si_shader *shader = ctx->shader;
1396 LLVMValueRef main_fn = ctx->main_fn;
1397 LLVMValueRef interp_param = NULL;
1398 int interp_param_idx;
1399
1400 /* Get colors from input VGPRs (set by the prolog). */
1401 if (decl->Semantic.Name == TGSI_SEMANTIC_COLOR) {
1402 unsigned i = decl->Semantic.Index;
1403 unsigned colors_read = shader->selector->info.colors_read;
1404 unsigned mask = colors_read >> (i * 4);
1405 unsigned offset = SI_PARAM_POS_FIXED_PT + 1 +
1406 (i ? util_bitcount(colors_read & 0xf) : 0);
1407
1408 out[0] = mask & 0x1 ? LLVMGetParam(main_fn, offset++) : base->undef;
1409 out[1] = mask & 0x2 ? LLVMGetParam(main_fn, offset++) : base->undef;
1410 out[2] = mask & 0x4 ? LLVMGetParam(main_fn, offset++) : base->undef;
1411 out[3] = mask & 0x8 ? LLVMGetParam(main_fn, offset++) : base->undef;
1412 return;
1413 }
1414
1415 interp_param_idx = lookup_interp_param_index(decl->Interp.Interpolate,
1416 decl->Interp.Location);
1417 if (interp_param_idx == -1)
1418 return;
1419 else if (interp_param_idx) {
1420 interp_param = LLVMGetParam(ctx->main_fn, interp_param_idx);
1421 }
1422
1423 interp_fs_input(ctx, input_index, decl->Semantic.Name,
1424 decl->Semantic.Index, 0, /* this param is unused */
1425 shader->selector->info.colors_read, interp_param,
1426 LLVMGetParam(main_fn, SI_PARAM_PRIM_MASK),
1427 LLVMGetParam(main_fn, SI_PARAM_FRONT_FACE),
1428 &out[0]);
1429 }
1430
1431 static LLVMValueRef get_sample_id(struct si_shader_context *ctx)
1432 {
1433 return unpack_param(ctx, SI_PARAM_ANCILLARY, 8, 4);
1434 }
1435
1436
1437 /**
1438 * Load a dword from a constant buffer.
1439 */
1440 static LLVMValueRef buffer_load_const(struct si_shader_context *ctx,
1441 LLVMValueRef resource,
1442 LLVMValueRef offset)
1443 {
1444 return ac_build_buffer_load(&ctx->ac, resource, 1, NULL, offset, NULL,
1445 0, 0, 0, true, true);
1446 }
1447
1448 static LLVMValueRef load_sample_position(struct si_shader_context *ctx, LLVMValueRef sample_id)
1449 {
1450 struct lp_build_context *uint_bld = &ctx->bld_base.uint_bld;
1451 struct gallivm_state *gallivm = &ctx->gallivm;
1452 LLVMBuilderRef builder = gallivm->builder;
1453 LLVMValueRef desc = LLVMGetParam(ctx->main_fn, ctx->param_rw_buffers);
1454 LLVMValueRef buf_index = LLVMConstInt(ctx->i32, SI_PS_CONST_SAMPLE_POSITIONS, 0);
1455 LLVMValueRef resource = ac_build_indexed_load_const(&ctx->ac, desc, buf_index);
1456
1457 /* offset = sample_id * 8 (8 = 2 floats containing samplepos.xy) */
1458 LLVMValueRef offset0 = lp_build_mul_imm(uint_bld, sample_id, 8);
1459 LLVMValueRef offset1 = LLVMBuildAdd(builder, offset0, LLVMConstInt(ctx->i32, 4, 0), "");
1460
1461 LLVMValueRef pos[4] = {
1462 buffer_load_const(ctx, resource, offset0),
1463 buffer_load_const(ctx, resource, offset1),
1464 LLVMConstReal(ctx->f32, 0),
1465 LLVMConstReal(ctx->f32, 0)
1466 };
1467
1468 return lp_build_gather_values(gallivm, pos, 4);
1469 }
1470
1471 static void declare_system_value(struct si_shader_context *ctx,
1472 unsigned index,
1473 const struct tgsi_full_declaration *decl)
1474 {
1475 struct lp_build_context *bld = &ctx->bld_base.base;
1476 struct gallivm_state *gallivm = &ctx->gallivm;
1477 LLVMValueRef value = 0;
1478
1479 assert(index < RADEON_LLVM_MAX_SYSTEM_VALUES);
1480
1481 switch (decl->Semantic.Name) {
1482 case TGSI_SEMANTIC_INSTANCEID:
1483 value = ctx->abi.instance_id;
1484 break;
1485
1486 case TGSI_SEMANTIC_VERTEXID:
1487 value = LLVMBuildAdd(gallivm->builder,
1488 ctx->abi.vertex_id,
1489 ctx->abi.base_vertex, "");
1490 break;
1491
1492 case TGSI_SEMANTIC_VERTEXID_NOBASE:
1493 /* Unused. Clarify the meaning in indexed vs. non-indexed
1494 * draws if this is ever used again. */
1495 assert(false);
1496 break;
1497
1498 case TGSI_SEMANTIC_BASEVERTEX:
1499 {
1500 /* For non-indexed draws, the base vertex set by the driver
1501 * (for direct draws) or the CP (for indirect draws) is the
1502 * first vertex ID, but GLSL expects 0 to be returned.
1503 */
1504 LLVMValueRef vs_state = LLVMGetParam(ctx->main_fn, ctx->param_vs_state_bits);
1505 LLVMValueRef indexed;
1506
1507 indexed = LLVMBuildLShr(gallivm->builder, vs_state, ctx->i32_1, "");
1508 indexed = LLVMBuildTrunc(gallivm->builder, indexed, ctx->i1, "");
1509
1510 value = LLVMBuildSelect(gallivm->builder, indexed,
1511 ctx->abi.base_vertex, ctx->i32_0, "");
1512 break;
1513 }
1514
1515 case TGSI_SEMANTIC_BASEINSTANCE:
1516 value = ctx->abi.start_instance;
1517 break;
1518
1519 case TGSI_SEMANTIC_DRAWID:
1520 value = ctx->abi.draw_id;
1521 break;
1522
1523 case TGSI_SEMANTIC_INVOCATIONID:
1524 if (ctx->type == PIPE_SHADER_TESS_CTRL)
1525 value = unpack_param(ctx, ctx->param_tcs_rel_ids, 8, 5);
1526 else if (ctx->type == PIPE_SHADER_GEOMETRY)
1527 value = LLVMGetParam(ctx->main_fn,
1528 ctx->param_gs_instance_id);
1529 else
1530 assert(!"INVOCATIONID not implemented");
1531 break;
1532
1533 case TGSI_SEMANTIC_POSITION:
1534 {
1535 LLVMValueRef pos[4] = {
1536 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_X_FLOAT),
1537 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_Y_FLOAT),
1538 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_Z_FLOAT),
1539 lp_build_emit_llvm_unary(&ctx->bld_base, TGSI_OPCODE_RCP,
1540 LLVMGetParam(ctx->main_fn,
1541 SI_PARAM_POS_W_FLOAT)),
1542 };
1543 value = lp_build_gather_values(gallivm, pos, 4);
1544 break;
1545 }
1546
1547 case TGSI_SEMANTIC_FACE:
1548 value = LLVMGetParam(ctx->main_fn, SI_PARAM_FRONT_FACE);
1549 break;
1550
1551 case TGSI_SEMANTIC_SAMPLEID:
1552 value = get_sample_id(ctx);
1553 break;
1554
1555 case TGSI_SEMANTIC_SAMPLEPOS: {
1556 LLVMValueRef pos[4] = {
1557 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_X_FLOAT),
1558 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_Y_FLOAT),
1559 LLVMConstReal(ctx->f32, 0),
1560 LLVMConstReal(ctx->f32, 0)
1561 };
1562 pos[0] = lp_build_emit_llvm_unary(&ctx->bld_base,
1563 TGSI_OPCODE_FRC, pos[0]);
1564 pos[1] = lp_build_emit_llvm_unary(&ctx->bld_base,
1565 TGSI_OPCODE_FRC, pos[1]);
1566 value = lp_build_gather_values(gallivm, pos, 4);
1567 break;
1568 }
1569
1570 case TGSI_SEMANTIC_SAMPLEMASK:
1571 /* This can only occur with the OpenGL Core profile, which
1572 * doesn't support smoothing.
1573 */
1574 value = LLVMGetParam(ctx->main_fn, SI_PARAM_SAMPLE_COVERAGE);
1575 break;
1576
1577 case TGSI_SEMANTIC_TESSCOORD:
1578 {
1579 LLVMValueRef coord[4] = {
1580 LLVMGetParam(ctx->main_fn, ctx->param_tes_u),
1581 LLVMGetParam(ctx->main_fn, ctx->param_tes_v),
1582 bld->zero,
1583 bld->zero
1584 };
1585
1586 /* For triangles, the vector should be (u, v, 1-u-v). */
1587 if (ctx->shader->selector->info.properties[TGSI_PROPERTY_TES_PRIM_MODE] ==
1588 PIPE_PRIM_TRIANGLES)
1589 coord[2] = lp_build_sub(bld, bld->one,
1590 lp_build_add(bld, coord[0], coord[1]));
1591
1592 value = lp_build_gather_values(gallivm, coord, 4);
1593 break;
1594 }
1595
1596 case TGSI_SEMANTIC_VERTICESIN:
1597 if (ctx->type == PIPE_SHADER_TESS_CTRL)
1598 value = unpack_param(ctx, ctx->param_tcs_out_lds_layout, 26, 6);
1599 else if (ctx->type == PIPE_SHADER_TESS_EVAL)
1600 value = unpack_param(ctx, ctx->param_tcs_offchip_layout, 6, 6);
1601 else
1602 assert(!"invalid shader stage for TGSI_SEMANTIC_VERTICESIN");
1603 break;
1604
1605 case TGSI_SEMANTIC_TESSINNER:
1606 case TGSI_SEMANTIC_TESSOUTER:
1607 {
1608 LLVMValueRef buffer, base, addr;
1609 int param = si_shader_io_get_unique_index_patch(decl->Semantic.Name, 0);
1610
1611 buffer = desc_from_addr_base64k(ctx, ctx->param_tcs_offchip_addr_base64k);
1612
1613 base = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
1614 addr = get_tcs_tes_buffer_address(ctx, get_rel_patch_id(ctx), NULL,
1615 LLVMConstInt(ctx->i32, param, 0));
1616
1617 value = buffer_load(&ctx->bld_base, TGSI_TYPE_FLOAT,
1618 ~0, buffer, base, addr, true);
1619
1620 break;
1621 }
1622
1623 case TGSI_SEMANTIC_DEFAULT_TESSOUTER_SI:
1624 case TGSI_SEMANTIC_DEFAULT_TESSINNER_SI:
1625 {
1626 LLVMValueRef buf, slot, val[4];
1627 int i, offset;
1628
1629 slot = LLVMConstInt(ctx->i32, SI_HS_CONST_DEFAULT_TESS_LEVELS, 0);
1630 buf = LLVMGetParam(ctx->main_fn, ctx->param_rw_buffers);
1631 buf = ac_build_indexed_load_const(&ctx->ac, buf, slot);
1632 offset = decl->Semantic.Name == TGSI_SEMANTIC_DEFAULT_TESSINNER_SI ? 4 : 0;
1633
1634 for (i = 0; i < 4; i++)
1635 val[i] = buffer_load_const(ctx, buf,
1636 LLVMConstInt(ctx->i32, (offset + i) * 4, 0));
1637 value = lp_build_gather_values(gallivm, val, 4);
1638 break;
1639 }
1640
1641 case TGSI_SEMANTIC_PRIMID:
1642 value = get_primitive_id(ctx, 0);
1643 break;
1644
1645 case TGSI_SEMANTIC_GRID_SIZE:
1646 value = LLVMGetParam(ctx->main_fn, ctx->param_grid_size);
1647 break;
1648
1649 case TGSI_SEMANTIC_BLOCK_SIZE:
1650 {
1651 LLVMValueRef values[3];
1652 unsigned i;
1653 unsigned *properties = ctx->shader->selector->info.properties;
1654
1655 if (properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] != 0) {
1656 unsigned sizes[3] = {
1657 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH],
1658 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT],
1659 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH]
1660 };
1661
1662 for (i = 0; i < 3; ++i)
1663 values[i] = LLVMConstInt(ctx->i32, sizes[i], 0);
1664
1665 value = lp_build_gather_values(gallivm, values, 3);
1666 } else {
1667 value = LLVMGetParam(ctx->main_fn, ctx->param_block_size);
1668 }
1669 break;
1670 }
1671
1672 case TGSI_SEMANTIC_BLOCK_ID:
1673 {
1674 LLVMValueRef values[3];
1675
1676 for (int i = 0; i < 3; i++) {
1677 values[i] = ctx->i32_0;
1678 if (ctx->param_block_id[i] >= 0) {
1679 values[i] = LLVMGetParam(ctx->main_fn,
1680 ctx->param_block_id[i]);
1681 }
1682 }
1683 value = lp_build_gather_values(gallivm, values, 3);
1684 break;
1685 }
1686
1687 case TGSI_SEMANTIC_THREAD_ID:
1688 value = LLVMGetParam(ctx->main_fn, ctx->param_thread_id);
1689 break;
1690
1691 case TGSI_SEMANTIC_HELPER_INVOCATION:
1692 value = lp_build_intrinsic(gallivm->builder,
1693 "llvm.amdgcn.ps.live",
1694 ctx->i1, NULL, 0,
1695 LP_FUNC_ATTR_READNONE);
1696 value = LLVMBuildNot(gallivm->builder, value, "");
1697 value = LLVMBuildSExt(gallivm->builder, value, ctx->i32, "");
1698 break;
1699
1700 case TGSI_SEMANTIC_SUBGROUP_SIZE:
1701 value = LLVMConstInt(ctx->i32, 64, 0);
1702 break;
1703
1704 case TGSI_SEMANTIC_SUBGROUP_INVOCATION:
1705 value = ac_get_thread_id(&ctx->ac);
1706 break;
1707
1708 case TGSI_SEMANTIC_SUBGROUP_EQ_MASK:
1709 {
1710 LLVMValueRef id = ac_get_thread_id(&ctx->ac);
1711 id = LLVMBuildZExt(gallivm->builder, id, ctx->i64, "");
1712 value = LLVMBuildShl(gallivm->builder, LLVMConstInt(ctx->i64, 1, 0), id, "");
1713 value = LLVMBuildBitCast(gallivm->builder, value, ctx->v2i32, "");
1714 break;
1715 }
1716
1717 case TGSI_SEMANTIC_SUBGROUP_GE_MASK:
1718 case TGSI_SEMANTIC_SUBGROUP_GT_MASK:
1719 case TGSI_SEMANTIC_SUBGROUP_LE_MASK:
1720 case TGSI_SEMANTIC_SUBGROUP_LT_MASK:
1721 {
1722 LLVMValueRef id = ac_get_thread_id(&ctx->ac);
1723 if (decl->Semantic.Name == TGSI_SEMANTIC_SUBGROUP_GT_MASK ||
1724 decl->Semantic.Name == TGSI_SEMANTIC_SUBGROUP_LE_MASK) {
1725 /* All bits set except LSB */
1726 value = LLVMConstInt(ctx->i64, -2, 0);
1727 } else {
1728 /* All bits set */
1729 value = LLVMConstInt(ctx->i64, -1, 0);
1730 }
1731 id = LLVMBuildZExt(gallivm->builder, id, ctx->i64, "");
1732 value = LLVMBuildShl(gallivm->builder, value, id, "");
1733 if (decl->Semantic.Name == TGSI_SEMANTIC_SUBGROUP_LE_MASK ||
1734 decl->Semantic.Name == TGSI_SEMANTIC_SUBGROUP_LT_MASK)
1735 value = LLVMBuildNot(gallivm->builder, value, "");
1736 value = LLVMBuildBitCast(gallivm->builder, value, ctx->v2i32, "");
1737 break;
1738 }
1739
1740 default:
1741 assert(!"unknown system value");
1742 return;
1743 }
1744
1745 ctx->system_values[index] = value;
1746 }
1747
1748 static void declare_compute_memory(struct si_shader_context *ctx,
1749 const struct tgsi_full_declaration *decl)
1750 {
1751 struct si_shader_selector *sel = ctx->shader->selector;
1752 struct gallivm_state *gallivm = &ctx->gallivm;
1753
1754 LLVMTypeRef i8p = LLVMPointerType(ctx->i8, LOCAL_ADDR_SPACE);
1755 LLVMValueRef var;
1756
1757 assert(decl->Declaration.MemType == TGSI_MEMORY_TYPE_SHARED);
1758 assert(decl->Range.First == decl->Range.Last);
1759 assert(!ctx->shared_memory);
1760
1761 var = LLVMAddGlobalInAddressSpace(gallivm->module,
1762 LLVMArrayType(ctx->i8, sel->local_size),
1763 "compute_lds",
1764 LOCAL_ADDR_SPACE);
1765 LLVMSetAlignment(var, 4);
1766
1767 ctx->shared_memory = LLVMBuildBitCast(gallivm->builder, var, i8p, "");
1768 }
1769
1770 static LLVMValueRef load_const_buffer_desc(struct si_shader_context *ctx, int i)
1771 {
1772 LLVMValueRef list_ptr = LLVMGetParam(ctx->main_fn,
1773 ctx->param_const_and_shader_buffers);
1774
1775 return ac_build_indexed_load_const(&ctx->ac, list_ptr,
1776 LLVMConstInt(ctx->i32, si_get_constbuf_slot(i), 0));
1777 }
1778
1779 static LLVMValueRef load_ubo(struct ac_shader_abi *abi, LLVMValueRef index)
1780 {
1781 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1782 LLVMValueRef ptr = LLVMGetParam(ctx->main_fn, ctx->param_const_and_shader_buffers);
1783
1784 index = si_llvm_bound_index(ctx, index, ctx->num_const_buffers);
1785 index = LLVMBuildAdd(ctx->gallivm.builder, index,
1786 LLVMConstInt(ctx->i32, SI_NUM_SHADER_BUFFERS, 0), "");
1787
1788 return ac_build_indexed_load_const(&ctx->ac, ptr, index);
1789 }
1790
1791 static LLVMValueRef fetch_constant(
1792 struct lp_build_tgsi_context *bld_base,
1793 const struct tgsi_full_src_register *reg,
1794 enum tgsi_opcode_type type,
1795 unsigned swizzle)
1796 {
1797 struct si_shader_context *ctx = si_shader_context(bld_base);
1798 struct lp_build_context *base = &bld_base->base;
1799 const struct tgsi_ind_register *ireg = &reg->Indirect;
1800 unsigned buf, idx;
1801
1802 LLVMValueRef addr, bufp;
1803 LLVMValueRef result;
1804
1805 if (swizzle == LP_CHAN_ALL) {
1806 unsigned chan;
1807 LLVMValueRef values[4];
1808 for (chan = 0; chan < TGSI_NUM_CHANNELS; ++chan)
1809 values[chan] = fetch_constant(bld_base, reg, type, chan);
1810
1811 return lp_build_gather_values(&ctx->gallivm, values, 4);
1812 }
1813
1814 buf = reg->Register.Dimension ? reg->Dimension.Index : 0;
1815 idx = reg->Register.Index * 4 + swizzle;
1816
1817 if (reg->Register.Dimension && reg->Dimension.Indirect) {
1818 LLVMValueRef ptr = LLVMGetParam(ctx->main_fn, ctx->param_const_and_shader_buffers);
1819 LLVMValueRef index;
1820 index = si_get_bounded_indirect_index(ctx, &reg->DimIndirect,
1821 reg->Dimension.Index,
1822 ctx->num_const_buffers);
1823 index = LLVMBuildAdd(ctx->gallivm.builder, index,
1824 LLVMConstInt(ctx->i32, SI_NUM_SHADER_BUFFERS, 0), "");
1825 bufp = ac_build_indexed_load_const(&ctx->ac, ptr, index);
1826 } else
1827 bufp = load_const_buffer_desc(ctx, buf);
1828
1829 if (reg->Register.Indirect) {
1830 addr = ctx->addrs[ireg->Index][ireg->Swizzle];
1831 addr = LLVMBuildLoad(base->gallivm->builder, addr, "load addr reg");
1832 addr = lp_build_mul_imm(&bld_base->uint_bld, addr, 16);
1833 addr = lp_build_add(&bld_base->uint_bld, addr,
1834 LLVMConstInt(ctx->i32, idx * 4, 0));
1835 } else {
1836 addr = LLVMConstInt(ctx->i32, idx * 4, 0);
1837 }
1838
1839 result = buffer_load_const(ctx, bufp, addr);
1840
1841 if (!tgsi_type_is_64bit(type))
1842 result = bitcast(bld_base, type, result);
1843 else {
1844 LLVMValueRef addr2, result2;
1845
1846 addr2 = lp_build_add(&bld_base->uint_bld, addr,
1847 LLVMConstInt(ctx->i32, 4, 0));
1848 result2 = buffer_load_const(ctx, bufp, addr2);
1849
1850 result = si_llvm_emit_fetch_64bit(bld_base, type,
1851 result, result2);
1852 }
1853 return result;
1854 }
1855
1856 /* Upper 16 bits must be zero. */
1857 static LLVMValueRef si_llvm_pack_two_int16(struct si_shader_context *ctx,
1858 LLVMValueRef val[2])
1859 {
1860 return LLVMBuildOr(ctx->gallivm.builder, val[0],
1861 LLVMBuildShl(ctx->gallivm.builder, val[1],
1862 LLVMConstInt(ctx->i32, 16, 0),
1863 ""), "");
1864 }
1865
1866 /* Upper 16 bits are ignored and will be dropped. */
1867 static LLVMValueRef si_llvm_pack_two_int32_as_int16(struct si_shader_context *ctx,
1868 LLVMValueRef val[2])
1869 {
1870 LLVMValueRef v[2] = {
1871 LLVMBuildAnd(ctx->gallivm.builder, val[0],
1872 LLVMConstInt(ctx->i32, 0xffff, 0), ""),
1873 val[1],
1874 };
1875 return si_llvm_pack_two_int16(ctx, v);
1876 }
1877
1878 /* Initialize arguments for the shader export intrinsic */
1879 static void si_llvm_init_export_args(struct lp_build_tgsi_context *bld_base,
1880 LLVMValueRef *values,
1881 unsigned target,
1882 struct ac_export_args *args)
1883 {
1884 struct si_shader_context *ctx = si_shader_context(bld_base);
1885 struct lp_build_context *base = &bld_base->base;
1886 LLVMBuilderRef builder = ctx->gallivm.builder;
1887 LLVMValueRef val[4];
1888 unsigned spi_shader_col_format = V_028714_SPI_SHADER_32_ABGR;
1889 unsigned chan;
1890 bool is_int8, is_int10;
1891
1892 /* Default is 0xf. Adjusted below depending on the format. */
1893 args->enabled_channels = 0xf; /* writemask */
1894
1895 /* Specify whether the EXEC mask represents the valid mask */
1896 args->valid_mask = 0;
1897
1898 /* Specify whether this is the last export */
1899 args->done = 0;
1900
1901 /* Specify the target we are exporting */
1902 args->target = target;
1903
1904 if (ctx->type == PIPE_SHADER_FRAGMENT) {
1905 const struct si_shader_key *key = &ctx->shader->key;
1906 unsigned col_formats = key->part.ps.epilog.spi_shader_col_format;
1907 int cbuf = target - V_008DFC_SQ_EXP_MRT;
1908
1909 assert(cbuf >= 0 && cbuf < 8);
1910 spi_shader_col_format = (col_formats >> (cbuf * 4)) & 0xf;
1911 is_int8 = (key->part.ps.epilog.color_is_int8 >> cbuf) & 0x1;
1912 is_int10 = (key->part.ps.epilog.color_is_int10 >> cbuf) & 0x1;
1913 }
1914
1915 args->compr = false;
1916 args->out[0] = base->undef;
1917 args->out[1] = base->undef;
1918 args->out[2] = base->undef;
1919 args->out[3] = base->undef;
1920
1921 switch (spi_shader_col_format) {
1922 case V_028714_SPI_SHADER_ZERO:
1923 args->enabled_channels = 0; /* writemask */
1924 args->target = V_008DFC_SQ_EXP_NULL;
1925 break;
1926
1927 case V_028714_SPI_SHADER_32_R:
1928 args->enabled_channels = 1; /* writemask */
1929 args->out[0] = values[0];
1930 break;
1931
1932 case V_028714_SPI_SHADER_32_GR:
1933 args->enabled_channels = 0x3; /* writemask */
1934 args->out[0] = values[0];
1935 args->out[1] = values[1];
1936 break;
1937
1938 case V_028714_SPI_SHADER_32_AR:
1939 args->enabled_channels = 0x9; /* writemask */
1940 args->out[0] = values[0];
1941 args->out[3] = values[3];
1942 break;
1943
1944 case V_028714_SPI_SHADER_FP16_ABGR:
1945 args->compr = 1; /* COMPR flag */
1946
1947 for (chan = 0; chan < 2; chan++) {
1948 LLVMValueRef pack_args[2] = {
1949 values[2 * chan],
1950 values[2 * chan + 1]
1951 };
1952 LLVMValueRef packed;
1953
1954 packed = ac_build_cvt_pkrtz_f16(&ctx->ac, pack_args);
1955 args->out[chan] =
1956 LLVMBuildBitCast(ctx->gallivm.builder,
1957 packed, ctx->f32, "");
1958 }
1959 break;
1960
1961 case V_028714_SPI_SHADER_UNORM16_ABGR:
1962 for (chan = 0; chan < 4; chan++) {
1963 val[chan] = ac_build_clamp(&ctx->ac, values[chan]);
1964 val[chan] = LLVMBuildFMul(builder, val[chan],
1965 LLVMConstReal(ctx->f32, 65535), "");
1966 val[chan] = LLVMBuildFAdd(builder, val[chan],
1967 LLVMConstReal(ctx->f32, 0.5), "");
1968 val[chan] = LLVMBuildFPToUI(builder, val[chan],
1969 ctx->i32, "");
1970 }
1971
1972 args->compr = 1; /* COMPR flag */
1973 args->out[0] = bitcast(bld_base, TGSI_TYPE_FLOAT,
1974 si_llvm_pack_two_int16(ctx, val));
1975 args->out[1] = bitcast(bld_base, TGSI_TYPE_FLOAT,
1976 si_llvm_pack_two_int16(ctx, val+2));
1977 break;
1978
1979 case V_028714_SPI_SHADER_SNORM16_ABGR:
1980 for (chan = 0; chan < 4; chan++) {
1981 /* Clamp between [-1, 1]. */
1982 val[chan] = lp_build_emit_llvm_binary(bld_base, TGSI_OPCODE_MIN,
1983 values[chan],
1984 LLVMConstReal(ctx->f32, 1));
1985 val[chan] = lp_build_emit_llvm_binary(bld_base, TGSI_OPCODE_MAX,
1986 val[chan],
1987 LLVMConstReal(ctx->f32, -1));
1988 /* Convert to a signed integer in [-32767, 32767]. */
1989 val[chan] = LLVMBuildFMul(builder, val[chan],
1990 LLVMConstReal(ctx->f32, 32767), "");
1991 /* If positive, add 0.5, else add -0.5. */
1992 val[chan] = LLVMBuildFAdd(builder, val[chan],
1993 LLVMBuildSelect(builder,
1994 LLVMBuildFCmp(builder, LLVMRealOGE,
1995 val[chan], base->zero, ""),
1996 LLVMConstReal(ctx->f32, 0.5),
1997 LLVMConstReal(ctx->f32, -0.5), ""), "");
1998 val[chan] = LLVMBuildFPToSI(builder, val[chan], ctx->i32, "");
1999 }
2000
2001 args->compr = 1; /* COMPR flag */
2002 args->out[0] = bitcast(bld_base, TGSI_TYPE_FLOAT,
2003 si_llvm_pack_two_int32_as_int16(ctx, val));
2004 args->out[1] = bitcast(bld_base, TGSI_TYPE_FLOAT,
2005 si_llvm_pack_two_int32_as_int16(ctx, val+2));
2006 break;
2007
2008 case V_028714_SPI_SHADER_UINT16_ABGR: {
2009 LLVMValueRef max_rgb = LLVMConstInt(ctx->i32,
2010 is_int8 ? 255 : is_int10 ? 1023 : 65535, 0);
2011 LLVMValueRef max_alpha =
2012 !is_int10 ? max_rgb : LLVMConstInt(ctx->i32, 3, 0);
2013
2014 /* Clamp. */
2015 for (chan = 0; chan < 4; chan++) {
2016 val[chan] = bitcast(bld_base, TGSI_TYPE_UNSIGNED, values[chan]);
2017 val[chan] = lp_build_emit_llvm_binary(bld_base, TGSI_OPCODE_UMIN,
2018 val[chan],
2019 chan == 3 ? max_alpha : max_rgb);
2020 }
2021
2022 args->compr = 1; /* COMPR flag */
2023 args->out[0] = bitcast(bld_base, TGSI_TYPE_FLOAT,
2024 si_llvm_pack_two_int16(ctx, val));
2025 args->out[1] = bitcast(bld_base, TGSI_TYPE_FLOAT,
2026 si_llvm_pack_two_int16(ctx, val+2));
2027 break;
2028 }
2029
2030 case V_028714_SPI_SHADER_SINT16_ABGR: {
2031 LLVMValueRef max_rgb = LLVMConstInt(ctx->i32,
2032 is_int8 ? 127 : is_int10 ? 511 : 32767, 0);
2033 LLVMValueRef min_rgb = LLVMConstInt(ctx->i32,
2034 is_int8 ? -128 : is_int10 ? -512 : -32768, 0);
2035 LLVMValueRef max_alpha =
2036 !is_int10 ? max_rgb : ctx->i32_1;
2037 LLVMValueRef min_alpha =
2038 !is_int10 ? min_rgb : LLVMConstInt(ctx->i32, -2, 0);
2039
2040 /* Clamp. */
2041 for (chan = 0; chan < 4; chan++) {
2042 val[chan] = bitcast(bld_base, TGSI_TYPE_UNSIGNED, values[chan]);
2043 val[chan] = lp_build_emit_llvm_binary(bld_base,
2044 TGSI_OPCODE_IMIN,
2045 val[chan], chan == 3 ? max_alpha : max_rgb);
2046 val[chan] = lp_build_emit_llvm_binary(bld_base,
2047 TGSI_OPCODE_IMAX,
2048 val[chan], chan == 3 ? min_alpha : min_rgb);
2049 }
2050
2051 args->compr = 1; /* COMPR flag */
2052 args->out[0] = bitcast(bld_base, TGSI_TYPE_FLOAT,
2053 si_llvm_pack_two_int32_as_int16(ctx, val));
2054 args->out[1] = bitcast(bld_base, TGSI_TYPE_FLOAT,
2055 si_llvm_pack_two_int32_as_int16(ctx, val+2));
2056 break;
2057 }
2058
2059 case V_028714_SPI_SHADER_32_ABGR:
2060 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
2061 break;
2062 }
2063 }
2064
2065 static void si_alpha_test(struct lp_build_tgsi_context *bld_base,
2066 LLVMValueRef alpha)
2067 {
2068 struct si_shader_context *ctx = si_shader_context(bld_base);
2069
2070 if (ctx->shader->key.part.ps.epilog.alpha_func != PIPE_FUNC_NEVER) {
2071 LLVMValueRef alpha_ref = LLVMGetParam(ctx->main_fn,
2072 SI_PARAM_ALPHA_REF);
2073
2074 LLVMValueRef alpha_pass =
2075 lp_build_cmp(&bld_base->base,
2076 ctx->shader->key.part.ps.epilog.alpha_func,
2077 alpha, alpha_ref);
2078 LLVMValueRef arg =
2079 lp_build_select(&bld_base->base,
2080 alpha_pass,
2081 LLVMConstReal(ctx->f32, 1.0f),
2082 LLVMConstReal(ctx->f32, -1.0f));
2083
2084 ac_build_kill(&ctx->ac, arg);
2085 } else {
2086 ac_build_kill(&ctx->ac, NULL);
2087 }
2088 }
2089
2090 static LLVMValueRef si_scale_alpha_by_sample_mask(struct lp_build_tgsi_context *bld_base,
2091 LLVMValueRef alpha,
2092 unsigned samplemask_param)
2093 {
2094 struct si_shader_context *ctx = si_shader_context(bld_base);
2095 struct gallivm_state *gallivm = &ctx->gallivm;
2096 LLVMValueRef coverage;
2097
2098 /* alpha = alpha * popcount(coverage) / SI_NUM_SMOOTH_AA_SAMPLES */
2099 coverage = LLVMGetParam(ctx->main_fn,
2100 samplemask_param);
2101 coverage = bitcast(bld_base, TGSI_TYPE_SIGNED, coverage);
2102
2103 coverage = lp_build_intrinsic(gallivm->builder, "llvm.ctpop.i32",
2104 ctx->i32,
2105 &coverage, 1, LP_FUNC_ATTR_READNONE);
2106
2107 coverage = LLVMBuildUIToFP(gallivm->builder, coverage,
2108 ctx->f32, "");
2109
2110 coverage = LLVMBuildFMul(gallivm->builder, coverage,
2111 LLVMConstReal(ctx->f32,
2112 1.0 / SI_NUM_SMOOTH_AA_SAMPLES), "");
2113
2114 return LLVMBuildFMul(gallivm->builder, alpha, coverage, "");
2115 }
2116
2117 static void si_llvm_emit_clipvertex(struct lp_build_tgsi_context *bld_base,
2118 struct ac_export_args *pos, LLVMValueRef *out_elts)
2119 {
2120 struct si_shader_context *ctx = si_shader_context(bld_base);
2121 struct lp_build_context *base = &bld_base->base;
2122 unsigned reg_index;
2123 unsigned chan;
2124 unsigned const_chan;
2125 LLVMValueRef base_elt;
2126 LLVMValueRef ptr = LLVMGetParam(ctx->main_fn, ctx->param_rw_buffers);
2127 LLVMValueRef constbuf_index = LLVMConstInt(ctx->i32,
2128 SI_VS_CONST_CLIP_PLANES, 0);
2129 LLVMValueRef const_resource = ac_build_indexed_load_const(&ctx->ac, ptr, constbuf_index);
2130
2131 for (reg_index = 0; reg_index < 2; reg_index ++) {
2132 struct ac_export_args *args = &pos[2 + reg_index];
2133
2134 args->out[0] =
2135 args->out[1] =
2136 args->out[2] =
2137 args->out[3] = LLVMConstReal(ctx->f32, 0.0f);
2138
2139 /* Compute dot products of position and user clip plane vectors */
2140 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2141 for (const_chan = 0; const_chan < TGSI_NUM_CHANNELS; const_chan++) {
2142 LLVMValueRef addr =
2143 LLVMConstInt(ctx->i32, ((reg_index * 4 + chan) * 4 +
2144 const_chan) * 4, 0);
2145 base_elt = buffer_load_const(ctx, const_resource,
2146 addr);
2147 args->out[chan] =
2148 lp_build_add(base, args->out[chan],
2149 lp_build_mul(base, base_elt,
2150 out_elts[const_chan]));
2151 }
2152 }
2153
2154 args->enabled_channels = 0xf;
2155 args->valid_mask = 0;
2156 args->done = 0;
2157 args->target = V_008DFC_SQ_EXP_POS + 2 + reg_index;
2158 args->compr = 0;
2159 }
2160 }
2161
2162 static void si_dump_streamout(struct pipe_stream_output_info *so)
2163 {
2164 unsigned i;
2165
2166 if (so->num_outputs)
2167 fprintf(stderr, "STREAMOUT\n");
2168
2169 for (i = 0; i < so->num_outputs; i++) {
2170 unsigned mask = ((1 << so->output[i].num_components) - 1) <<
2171 so->output[i].start_component;
2172 fprintf(stderr, " %i: BUF%i[%i..%i] <- OUT[%i].%s%s%s%s\n",
2173 i, so->output[i].output_buffer,
2174 so->output[i].dst_offset, so->output[i].dst_offset + so->output[i].num_components - 1,
2175 so->output[i].register_index,
2176 mask & 1 ? "x" : "",
2177 mask & 2 ? "y" : "",
2178 mask & 4 ? "z" : "",
2179 mask & 8 ? "w" : "");
2180 }
2181 }
2182
2183 static void emit_streamout_output(struct si_shader_context *ctx,
2184 LLVMValueRef const *so_buffers,
2185 LLVMValueRef const *so_write_offsets,
2186 struct pipe_stream_output *stream_out,
2187 struct si_shader_output_values *shader_out)
2188 {
2189 struct gallivm_state *gallivm = &ctx->gallivm;
2190 LLVMBuilderRef builder = gallivm->builder;
2191 unsigned buf_idx = stream_out->output_buffer;
2192 unsigned start = stream_out->start_component;
2193 unsigned num_comps = stream_out->num_components;
2194 LLVMValueRef out[4];
2195
2196 assert(num_comps && num_comps <= 4);
2197 if (!num_comps || num_comps > 4)
2198 return;
2199
2200 /* Load the output as int. */
2201 for (int j = 0; j < num_comps; j++) {
2202 assert(stream_out->stream == shader_out->vertex_stream[start + j]);
2203
2204 out[j] = LLVMBuildBitCast(builder,
2205 shader_out->values[start + j],
2206 ctx->i32, "");
2207 }
2208
2209 /* Pack the output. */
2210 LLVMValueRef vdata = NULL;
2211
2212 switch (num_comps) {
2213 case 1: /* as i32 */
2214 vdata = out[0];
2215 break;
2216 case 2: /* as v2i32 */
2217 case 3: /* as v4i32 (aligned to 4) */
2218 case 4: /* as v4i32 */
2219 vdata = LLVMGetUndef(LLVMVectorType(ctx->i32, util_next_power_of_two(num_comps)));
2220 for (int j = 0; j < num_comps; j++) {
2221 vdata = LLVMBuildInsertElement(builder, vdata, out[j],
2222 LLVMConstInt(ctx->i32, j, 0), "");
2223 }
2224 break;
2225 }
2226
2227 ac_build_buffer_store_dword(&ctx->ac, so_buffers[buf_idx],
2228 vdata, num_comps,
2229 so_write_offsets[buf_idx],
2230 ctx->i32_0,
2231 stream_out->dst_offset * 4, 1, 1, true, false);
2232 }
2233
2234 /**
2235 * Write streamout data to buffers for vertex stream @p stream (different
2236 * vertex streams can occur for GS copy shaders).
2237 */
2238 static void si_llvm_emit_streamout(struct si_shader_context *ctx,
2239 struct si_shader_output_values *outputs,
2240 unsigned noutput, unsigned stream)
2241 {
2242 struct si_shader_selector *sel = ctx->shader->selector;
2243 struct pipe_stream_output_info *so = &sel->so;
2244 struct gallivm_state *gallivm = &ctx->gallivm;
2245 LLVMBuilderRef builder = gallivm->builder;
2246 int i;
2247 struct lp_build_if_state if_ctx;
2248
2249 /* Get bits [22:16], i.e. (so_param >> 16) & 127; */
2250 LLVMValueRef so_vtx_count =
2251 unpack_param(ctx, ctx->param_streamout_config, 16, 7);
2252
2253 LLVMValueRef tid = ac_get_thread_id(&ctx->ac);
2254
2255 /* can_emit = tid < so_vtx_count; */
2256 LLVMValueRef can_emit =
2257 LLVMBuildICmp(builder, LLVMIntULT, tid, so_vtx_count, "");
2258
2259 /* Emit the streamout code conditionally. This actually avoids
2260 * out-of-bounds buffer access. The hw tells us via the SGPR
2261 * (so_vtx_count) which threads are allowed to emit streamout data. */
2262 lp_build_if(&if_ctx, gallivm, can_emit);
2263 {
2264 /* The buffer offset is computed as follows:
2265 * ByteOffset = streamout_offset[buffer_id]*4 +
2266 * (streamout_write_index + thread_id)*stride[buffer_id] +
2267 * attrib_offset
2268 */
2269
2270 LLVMValueRef so_write_index =
2271 LLVMGetParam(ctx->main_fn,
2272 ctx->param_streamout_write_index);
2273
2274 /* Compute (streamout_write_index + thread_id). */
2275 so_write_index = LLVMBuildAdd(builder, so_write_index, tid, "");
2276
2277 /* Load the descriptor and compute the write offset for each
2278 * enabled buffer. */
2279 LLVMValueRef so_write_offset[4] = {};
2280 LLVMValueRef so_buffers[4];
2281 LLVMValueRef buf_ptr = LLVMGetParam(ctx->main_fn,
2282 ctx->param_rw_buffers);
2283
2284 for (i = 0; i < 4; i++) {
2285 if (!so->stride[i])
2286 continue;
2287
2288 LLVMValueRef offset = LLVMConstInt(ctx->i32,
2289 SI_VS_STREAMOUT_BUF0 + i, 0);
2290
2291 so_buffers[i] = ac_build_indexed_load_const(&ctx->ac, buf_ptr, offset);
2292
2293 LLVMValueRef so_offset = LLVMGetParam(ctx->main_fn,
2294 ctx->param_streamout_offset[i]);
2295 so_offset = LLVMBuildMul(builder, so_offset, LLVMConstInt(ctx->i32, 4, 0), "");
2296
2297 so_write_offset[i] = LLVMBuildMul(builder, so_write_index,
2298 LLVMConstInt(ctx->i32, so->stride[i]*4, 0), "");
2299 so_write_offset[i] = LLVMBuildAdd(builder, so_write_offset[i], so_offset, "");
2300 }
2301
2302 /* Write streamout data. */
2303 for (i = 0; i < so->num_outputs; i++) {
2304 unsigned reg = so->output[i].register_index;
2305
2306 if (reg >= noutput)
2307 continue;
2308
2309 if (stream != so->output[i].stream)
2310 continue;
2311
2312 emit_streamout_output(ctx, so_buffers, so_write_offset,
2313 &so->output[i], &outputs[reg]);
2314 }
2315 }
2316 lp_build_endif(&if_ctx);
2317 }
2318
2319 static void si_export_param(struct si_shader_context *ctx, unsigned index,
2320 LLVMValueRef *values)
2321 {
2322 struct ac_export_args args;
2323
2324 si_llvm_init_export_args(&ctx->bld_base, values,
2325 V_008DFC_SQ_EXP_PARAM + index, &args);
2326 ac_build_export(&ctx->ac, &args);
2327 }
2328
2329 static void si_build_param_exports(struct si_shader_context *ctx,
2330 struct si_shader_output_values *outputs,
2331 unsigned noutput)
2332 {
2333 struct si_shader *shader = ctx->shader;
2334 unsigned param_count = 0;
2335
2336 for (unsigned i = 0; i < noutput; i++) {
2337 unsigned semantic_name = outputs[i].semantic_name;
2338 unsigned semantic_index = outputs[i].semantic_index;
2339
2340 if (outputs[i].vertex_stream[0] != 0 &&
2341 outputs[i].vertex_stream[1] != 0 &&
2342 outputs[i].vertex_stream[2] != 0 &&
2343 outputs[i].vertex_stream[3] != 0)
2344 continue;
2345
2346 switch (semantic_name) {
2347 case TGSI_SEMANTIC_LAYER:
2348 case TGSI_SEMANTIC_VIEWPORT_INDEX:
2349 case TGSI_SEMANTIC_CLIPDIST:
2350 case TGSI_SEMANTIC_COLOR:
2351 case TGSI_SEMANTIC_BCOLOR:
2352 case TGSI_SEMANTIC_PRIMID:
2353 case TGSI_SEMANTIC_FOG:
2354 case TGSI_SEMANTIC_TEXCOORD:
2355 case TGSI_SEMANTIC_GENERIC:
2356 break;
2357 default:
2358 continue;
2359 }
2360
2361 if ((semantic_name != TGSI_SEMANTIC_GENERIC ||
2362 semantic_index < SI_MAX_IO_GENERIC) &&
2363 shader->key.opt.kill_outputs &
2364 (1ull << si_shader_io_get_unique_index(semantic_name, semantic_index)))
2365 continue;
2366
2367 si_export_param(ctx, param_count, outputs[i].values);
2368
2369 assert(i < ARRAY_SIZE(shader->info.vs_output_param_offset));
2370 shader->info.vs_output_param_offset[i] = param_count++;
2371 }
2372
2373 shader->info.nr_param_exports = param_count;
2374 }
2375
2376 /* Generate export instructions for hardware VS shader stage */
2377 static void si_llvm_export_vs(struct lp_build_tgsi_context *bld_base,
2378 struct si_shader_output_values *outputs,
2379 unsigned noutput)
2380 {
2381 struct si_shader_context *ctx = si_shader_context(bld_base);
2382 struct si_shader *shader = ctx->shader;
2383 struct lp_build_context *base = &bld_base->base;
2384 struct ac_export_args pos_args[4] = {};
2385 LLVMValueRef psize_value = NULL, edgeflag_value = NULL, layer_value = NULL, viewport_index_value = NULL;
2386 unsigned pos_idx;
2387 int i;
2388
2389 /* Build position exports. */
2390 for (i = 0; i < noutput; i++) {
2391 switch (outputs[i].semantic_name) {
2392 case TGSI_SEMANTIC_POSITION:
2393 si_llvm_init_export_args(bld_base, outputs[i].values,
2394 V_008DFC_SQ_EXP_POS, &pos_args[0]);
2395 break;
2396 case TGSI_SEMANTIC_PSIZE:
2397 psize_value = outputs[i].values[0];
2398 break;
2399 case TGSI_SEMANTIC_LAYER:
2400 layer_value = outputs[i].values[0];
2401 break;
2402 case TGSI_SEMANTIC_VIEWPORT_INDEX:
2403 viewport_index_value = outputs[i].values[0];
2404 break;
2405 case TGSI_SEMANTIC_EDGEFLAG:
2406 edgeflag_value = outputs[i].values[0];
2407 break;
2408 case TGSI_SEMANTIC_CLIPDIST:
2409 if (!shader->key.opt.clip_disable) {
2410 unsigned index = 2 + outputs[i].semantic_index;
2411 si_llvm_init_export_args(bld_base, outputs[i].values,
2412 V_008DFC_SQ_EXP_POS + index,
2413 &pos_args[index]);
2414 }
2415 break;
2416 case TGSI_SEMANTIC_CLIPVERTEX:
2417 if (!shader->key.opt.clip_disable) {
2418 si_llvm_emit_clipvertex(bld_base, pos_args,
2419 outputs[i].values);
2420 }
2421 break;
2422 }
2423 }
2424
2425 /* We need to add the position output manually if it's missing. */
2426 if (!pos_args[0].out[0]) {
2427 pos_args[0].enabled_channels = 0xf; /* writemask */
2428 pos_args[0].valid_mask = 0; /* EXEC mask */
2429 pos_args[0].done = 0; /* last export? */
2430 pos_args[0].target = V_008DFC_SQ_EXP_POS;
2431 pos_args[0].compr = 0; /* COMPR flag */
2432 pos_args[0].out[0] = base->zero; /* X */
2433 pos_args[0].out[1] = base->zero; /* Y */
2434 pos_args[0].out[2] = base->zero; /* Z */
2435 pos_args[0].out[3] = base->one; /* W */
2436 }
2437
2438 /* Write the misc vector (point size, edgeflag, layer, viewport). */
2439 if (shader->selector->info.writes_psize ||
2440 shader->selector->info.writes_edgeflag ||
2441 shader->selector->info.writes_viewport_index ||
2442 shader->selector->info.writes_layer) {
2443 pos_args[1].enabled_channels = shader->selector->info.writes_psize |
2444 (shader->selector->info.writes_edgeflag << 1) |
2445 (shader->selector->info.writes_layer << 2);
2446
2447 pos_args[1].valid_mask = 0; /* EXEC mask */
2448 pos_args[1].done = 0; /* last export? */
2449 pos_args[1].target = V_008DFC_SQ_EXP_POS + 1;
2450 pos_args[1].compr = 0; /* COMPR flag */
2451 pos_args[1].out[0] = base->zero; /* X */
2452 pos_args[1].out[1] = base->zero; /* Y */
2453 pos_args[1].out[2] = base->zero; /* Z */
2454 pos_args[1].out[3] = base->zero; /* W */
2455
2456 if (shader->selector->info.writes_psize)
2457 pos_args[1].out[0] = psize_value;
2458
2459 if (shader->selector->info.writes_edgeflag) {
2460 /* The output is a float, but the hw expects an integer
2461 * with the first bit containing the edge flag. */
2462 edgeflag_value = LLVMBuildFPToUI(ctx->gallivm.builder,
2463 edgeflag_value,
2464 ctx->i32, "");
2465 edgeflag_value = lp_build_min(&bld_base->int_bld,
2466 edgeflag_value,
2467 ctx->i32_1);
2468
2469 /* The LLVM intrinsic expects a float. */
2470 pos_args[1].out[1] = LLVMBuildBitCast(ctx->gallivm.builder,
2471 edgeflag_value,
2472 ctx->f32, "");
2473 }
2474
2475 if (ctx->screen->b.chip_class >= GFX9) {
2476 /* GFX9 has the layer in out.z[10:0] and the viewport
2477 * index in out.z[19:16].
2478 */
2479 if (shader->selector->info.writes_layer)
2480 pos_args[1].out[2] = layer_value;
2481
2482 if (shader->selector->info.writes_viewport_index) {
2483 LLVMValueRef v = viewport_index_value;
2484
2485 v = bitcast(bld_base, TGSI_TYPE_UNSIGNED, v);
2486 v = LLVMBuildShl(ctx->gallivm.builder, v,
2487 LLVMConstInt(ctx->i32, 16, 0), "");
2488 v = LLVMBuildOr(ctx->gallivm.builder, v,
2489 bitcast(bld_base, TGSI_TYPE_UNSIGNED,
2490 pos_args[1].out[2]), "");
2491 pos_args[1].out[2] = bitcast(bld_base, TGSI_TYPE_FLOAT, v);
2492 pos_args[1].enabled_channels |= 1 << 2;
2493 }
2494 } else {
2495 if (shader->selector->info.writes_layer)
2496 pos_args[1].out[2] = layer_value;
2497
2498 if (shader->selector->info.writes_viewport_index) {
2499 pos_args[1].out[3] = viewport_index_value;
2500 pos_args[1].enabled_channels |= 1 << 3;
2501 }
2502 }
2503 }
2504
2505 for (i = 0; i < 4; i++)
2506 if (pos_args[i].out[0])
2507 shader->info.nr_pos_exports++;
2508
2509 pos_idx = 0;
2510 for (i = 0; i < 4; i++) {
2511 if (!pos_args[i].out[0])
2512 continue;
2513
2514 /* Specify the target we are exporting */
2515 pos_args[i].target = V_008DFC_SQ_EXP_POS + pos_idx++;
2516
2517 if (pos_idx == shader->info.nr_pos_exports)
2518 /* Specify that this is the last export */
2519 pos_args[i].done = 1;
2520
2521 ac_build_export(&ctx->ac, &pos_args[i]);
2522 }
2523
2524 /* Build parameter exports. */
2525 si_build_param_exports(ctx, outputs, noutput);
2526 }
2527
2528 /**
2529 * Forward all outputs from the vertex shader to the TES. This is only used
2530 * for the fixed function TCS.
2531 */
2532 static void si_copy_tcs_inputs(struct lp_build_tgsi_context *bld_base)
2533 {
2534 struct si_shader_context *ctx = si_shader_context(bld_base);
2535 struct gallivm_state *gallivm = &ctx->gallivm;
2536 LLVMValueRef invocation_id, buffer, buffer_offset;
2537 LLVMValueRef lds_vertex_stride, lds_vertex_offset, lds_base;
2538 uint64_t inputs;
2539
2540 invocation_id = unpack_param(ctx, ctx->param_tcs_rel_ids, 8, 5);
2541 buffer = desc_from_addr_base64k(ctx, ctx->param_tcs_offchip_addr_base64k);
2542 buffer_offset = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
2543
2544 lds_vertex_stride = unpack_param(ctx, ctx->param_vs_state_bits, 24, 8);
2545 lds_vertex_offset = LLVMBuildMul(gallivm->builder, invocation_id,
2546 lds_vertex_stride, "");
2547 lds_base = get_tcs_in_current_patch_offset(ctx);
2548 lds_base = LLVMBuildAdd(gallivm->builder, lds_base, lds_vertex_offset, "");
2549
2550 inputs = ctx->shader->key.mono.u.ff_tcs_inputs_to_copy;
2551 while (inputs) {
2552 unsigned i = u_bit_scan64(&inputs);
2553
2554 LLVMValueRef lds_ptr = LLVMBuildAdd(gallivm->builder, lds_base,
2555 LLVMConstInt(ctx->i32, 4 * i, 0),
2556 "");
2557
2558 LLVMValueRef buffer_addr = get_tcs_tes_buffer_address(ctx,
2559 get_rel_patch_id(ctx),
2560 invocation_id,
2561 LLVMConstInt(ctx->i32, i, 0));
2562
2563 LLVMValueRef value = lds_load(bld_base, TGSI_TYPE_SIGNED, ~0,
2564 lds_ptr);
2565
2566 ac_build_buffer_store_dword(&ctx->ac, buffer, value, 4, buffer_addr,
2567 buffer_offset, 0, 1, 0, true, false);
2568 }
2569 }
2570
2571 static void si_write_tess_factors(struct lp_build_tgsi_context *bld_base,
2572 LLVMValueRef rel_patch_id,
2573 LLVMValueRef invocation_id,
2574 LLVMValueRef tcs_out_current_patch_data_offset)
2575 {
2576 struct si_shader_context *ctx = si_shader_context(bld_base);
2577 struct gallivm_state *gallivm = &ctx->gallivm;
2578 struct si_shader *shader = ctx->shader;
2579 unsigned tess_inner_index, tess_outer_index;
2580 LLVMValueRef lds_base, lds_inner, lds_outer, byteoffset, buffer;
2581 LLVMValueRef out[6], vec0, vec1, tf_base, inner[4], outer[4];
2582 unsigned stride, outer_comps, inner_comps, i, offset;
2583 struct lp_build_if_state if_ctx, inner_if_ctx;
2584
2585 si_llvm_emit_barrier(NULL, bld_base, NULL);
2586
2587 /* Do this only for invocation 0, because the tess levels are per-patch,
2588 * not per-vertex.
2589 *
2590 * This can't jump, because invocation 0 executes this. It should
2591 * at least mask out the loads and stores for other invocations.
2592 */
2593 lp_build_if(&if_ctx, gallivm,
2594 LLVMBuildICmp(gallivm->builder, LLVMIntEQ,
2595 invocation_id, ctx->i32_0, ""));
2596
2597 /* Determine the layout of one tess factor element in the buffer. */
2598 switch (shader->key.part.tcs.epilog.prim_mode) {
2599 case PIPE_PRIM_LINES:
2600 stride = 2; /* 2 dwords, 1 vec2 store */
2601 outer_comps = 2;
2602 inner_comps = 0;
2603 break;
2604 case PIPE_PRIM_TRIANGLES:
2605 stride = 4; /* 4 dwords, 1 vec4 store */
2606 outer_comps = 3;
2607 inner_comps = 1;
2608 break;
2609 case PIPE_PRIM_QUADS:
2610 stride = 6; /* 6 dwords, 2 stores (vec4 + vec2) */
2611 outer_comps = 4;
2612 inner_comps = 2;
2613 break;
2614 default:
2615 assert(0);
2616 return;
2617 }
2618
2619 /* Load tess_inner and tess_outer from LDS.
2620 * Any invocation can write them, so we can't get them from a temporary.
2621 */
2622 tess_inner_index = si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSINNER, 0);
2623 tess_outer_index = si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSOUTER, 0);
2624
2625 lds_base = tcs_out_current_patch_data_offset;
2626 lds_inner = LLVMBuildAdd(gallivm->builder, lds_base,
2627 LLVMConstInt(ctx->i32,
2628 tess_inner_index * 4, 0), "");
2629 lds_outer = LLVMBuildAdd(gallivm->builder, lds_base,
2630 LLVMConstInt(ctx->i32,
2631 tess_outer_index * 4, 0), "");
2632
2633 for (i = 0; i < 4; i++) {
2634 inner[i] = LLVMGetUndef(ctx->i32);
2635 outer[i] = LLVMGetUndef(ctx->i32);
2636 }
2637
2638 if (shader->key.part.tcs.epilog.prim_mode == PIPE_PRIM_LINES) {
2639 /* For isolines, the hardware expects tess factors in the
2640 * reverse order from what GLSL / TGSI specify.
2641 */
2642 outer[0] = out[1] = lds_load(bld_base, TGSI_TYPE_SIGNED, 0, lds_outer);
2643 outer[1] = out[0] = lds_load(bld_base, TGSI_TYPE_SIGNED, 1, lds_outer);
2644 } else {
2645 for (i = 0; i < outer_comps; i++) {
2646 outer[i] = out[i] =
2647 lds_load(bld_base, TGSI_TYPE_SIGNED, i, lds_outer);
2648 }
2649 for (i = 0; i < inner_comps; i++) {
2650 inner[i] = out[outer_comps+i] =
2651 lds_load(bld_base, TGSI_TYPE_SIGNED, i, lds_inner);
2652 }
2653 }
2654
2655 /* Convert the outputs to vectors for stores. */
2656 vec0 = lp_build_gather_values(gallivm, out, MIN2(stride, 4));
2657 vec1 = NULL;
2658
2659 if (stride > 4)
2660 vec1 = lp_build_gather_values(gallivm, out+4, stride - 4);
2661
2662 /* Get the buffer. */
2663 buffer = desc_from_addr_base64k(ctx, ctx->param_tcs_factor_addr_base64k);
2664
2665 /* Get the offset. */
2666 tf_base = LLVMGetParam(ctx->main_fn,
2667 ctx->param_tcs_factor_offset);
2668 byteoffset = LLVMBuildMul(gallivm->builder, rel_patch_id,
2669 LLVMConstInt(ctx->i32, 4 * stride, 0), "");
2670
2671 lp_build_if(&inner_if_ctx, gallivm,
2672 LLVMBuildICmp(gallivm->builder, LLVMIntEQ,
2673 rel_patch_id, ctx->i32_0, ""));
2674
2675 /* Store the dynamic HS control word. */
2676 offset = 0;
2677 if (ctx->screen->b.chip_class <= VI) {
2678 ac_build_buffer_store_dword(&ctx->ac, buffer,
2679 LLVMConstInt(ctx->i32, 0x80000000, 0),
2680 1, ctx->i32_0, tf_base,
2681 offset, 1, 0, true, false);
2682 offset += 4;
2683 }
2684
2685 lp_build_endif(&inner_if_ctx);
2686
2687 /* Store the tessellation factors. */
2688 ac_build_buffer_store_dword(&ctx->ac, buffer, vec0,
2689 MIN2(stride, 4), byteoffset, tf_base,
2690 offset, 1, 0, true, false);
2691 offset += 16;
2692 if (vec1)
2693 ac_build_buffer_store_dword(&ctx->ac, buffer, vec1,
2694 stride - 4, byteoffset, tf_base,
2695 offset, 1, 0, true, false);
2696
2697 /* Store the tess factors into the offchip buffer if TES reads them. */
2698 if (shader->key.part.tcs.epilog.tes_reads_tess_factors) {
2699 LLVMValueRef buf, base, inner_vec, outer_vec, tf_outer_offset;
2700 LLVMValueRef tf_inner_offset;
2701 unsigned param_outer, param_inner;
2702
2703 buf = desc_from_addr_base64k(ctx, ctx->param_tcs_offchip_addr_base64k);
2704 base = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
2705
2706 param_outer = si_shader_io_get_unique_index_patch(
2707 TGSI_SEMANTIC_TESSOUTER, 0);
2708 tf_outer_offset = get_tcs_tes_buffer_address(ctx, rel_patch_id, NULL,
2709 LLVMConstInt(ctx->i32, param_outer, 0));
2710
2711 outer_vec = lp_build_gather_values(gallivm, outer,
2712 util_next_power_of_two(outer_comps));
2713
2714 ac_build_buffer_store_dword(&ctx->ac, buf, outer_vec,
2715 outer_comps, tf_outer_offset,
2716 base, 0, 1, 0, true, false);
2717 if (inner_comps) {
2718 param_inner = si_shader_io_get_unique_index_patch(
2719 TGSI_SEMANTIC_TESSINNER, 0);
2720 tf_inner_offset = get_tcs_tes_buffer_address(ctx, rel_patch_id, NULL,
2721 LLVMConstInt(ctx->i32, param_inner, 0));
2722
2723 inner_vec = inner_comps == 1 ? inner[0] :
2724 lp_build_gather_values(gallivm, inner, inner_comps);
2725 ac_build_buffer_store_dword(&ctx->ac, buf, inner_vec,
2726 inner_comps, tf_inner_offset,
2727 base, 0, 1, 0, true, false);
2728 }
2729 }
2730
2731 lp_build_endif(&if_ctx);
2732 }
2733
2734 static LLVMValueRef
2735 si_insert_input_ret(struct si_shader_context *ctx, LLVMValueRef ret,
2736 unsigned param, unsigned return_index)
2737 {
2738 return LLVMBuildInsertValue(ctx->gallivm.builder, ret,
2739 LLVMGetParam(ctx->main_fn, param),
2740 return_index, "");
2741 }
2742
2743 static LLVMValueRef
2744 si_insert_input_ret_float(struct si_shader_context *ctx, LLVMValueRef ret,
2745 unsigned param, unsigned return_index)
2746 {
2747 LLVMBuilderRef builder = ctx->gallivm.builder;
2748 LLVMValueRef p = LLVMGetParam(ctx->main_fn, param);
2749
2750 return LLVMBuildInsertValue(builder, ret,
2751 LLVMBuildBitCast(builder, p, ctx->f32, ""),
2752 return_index, "");
2753 }
2754
2755 static LLVMValueRef
2756 si_insert_input_ptr_as_2xi32(struct si_shader_context *ctx, LLVMValueRef ret,
2757 unsigned param, unsigned return_index)
2758 {
2759 LLVMBuilderRef builder = ctx->gallivm.builder;
2760 LLVMValueRef ptr, lo, hi;
2761
2762 ptr = LLVMGetParam(ctx->main_fn, param);
2763 ptr = LLVMBuildPtrToInt(builder, ptr, ctx->i64, "");
2764 ptr = LLVMBuildBitCast(builder, ptr, ctx->v2i32, "");
2765 lo = LLVMBuildExtractElement(builder, ptr, ctx->i32_0, "");
2766 hi = LLVMBuildExtractElement(builder, ptr, ctx->i32_1, "");
2767 ret = LLVMBuildInsertValue(builder, ret, lo, return_index, "");
2768 return LLVMBuildInsertValue(builder, ret, hi, return_index + 1, "");
2769 }
2770
2771 /* This only writes the tessellation factor levels. */
2772 static void si_llvm_emit_tcs_epilogue(struct lp_build_tgsi_context *bld_base)
2773 {
2774 struct si_shader_context *ctx = si_shader_context(bld_base);
2775 LLVMBuilderRef builder = ctx->gallivm.builder;
2776 LLVMValueRef rel_patch_id, invocation_id, tf_lds_offset;
2777
2778 si_copy_tcs_inputs(bld_base);
2779
2780 rel_patch_id = get_rel_patch_id(ctx);
2781 invocation_id = unpack_param(ctx, ctx->param_tcs_rel_ids, 8, 5);
2782 tf_lds_offset = get_tcs_out_current_patch_data_offset(ctx);
2783
2784 if (ctx->screen->b.chip_class >= GFX9) {
2785 LLVMBasicBlockRef blocks[2] = {
2786 LLVMGetInsertBlock(builder),
2787 ctx->merged_wrap_if_state.entry_block
2788 };
2789 LLVMValueRef values[2];
2790
2791 lp_build_endif(&ctx->merged_wrap_if_state);
2792
2793 values[0] = rel_patch_id;
2794 values[1] = LLVMGetUndef(ctx->i32);
2795 rel_patch_id = build_phi(&ctx->ac, ctx->i32, 2, values, blocks);
2796
2797 values[0] = tf_lds_offset;
2798 values[1] = LLVMGetUndef(ctx->i32);
2799 tf_lds_offset = build_phi(&ctx->ac, ctx->i32, 2, values, blocks);
2800
2801 values[0] = invocation_id;
2802 values[1] = ctx->i32_1; /* cause the epilog to skip threads */
2803 invocation_id = build_phi(&ctx->ac, ctx->i32, 2, values, blocks);
2804 }
2805
2806 /* Return epilog parameters from this function. */
2807 LLVMValueRef ret = ctx->return_value;
2808 unsigned vgpr;
2809
2810 if (ctx->screen->b.chip_class >= GFX9) {
2811 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_layout,
2812 8 + GFX9_SGPR_TCS_OFFCHIP_LAYOUT);
2813 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_addr_base64k,
2814 8 + GFX9_SGPR_TCS_OFFCHIP_ADDR_BASE64K);
2815 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_factor_addr_base64k,
2816 8 + GFX9_SGPR_TCS_FACTOR_ADDR_BASE64K);
2817 /* Tess offchip and tess factor offsets are at the beginning. */
2818 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_offset, 2);
2819 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_factor_offset, 4);
2820 vgpr = 8 + GFX9_SGPR_TCS_FACTOR_ADDR_BASE64K + 1;
2821 } else {
2822 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_layout,
2823 GFX6_SGPR_TCS_OFFCHIP_LAYOUT);
2824 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_addr_base64k,
2825 GFX6_SGPR_TCS_OFFCHIP_ADDR_BASE64K);
2826 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_factor_addr_base64k,
2827 GFX6_SGPR_TCS_FACTOR_ADDR_BASE64K);
2828 /* Tess offchip and tess factor offsets are after user SGPRs. */
2829 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_offset,
2830 GFX6_TCS_NUM_USER_SGPR);
2831 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_factor_offset,
2832 GFX6_TCS_NUM_USER_SGPR + 1);
2833 vgpr = GFX6_TCS_NUM_USER_SGPR + 2;
2834 }
2835
2836 /* VGPRs */
2837 rel_patch_id = bitcast(bld_base, TGSI_TYPE_FLOAT, rel_patch_id);
2838 invocation_id = bitcast(bld_base, TGSI_TYPE_FLOAT, invocation_id);
2839 tf_lds_offset = bitcast(bld_base, TGSI_TYPE_FLOAT, tf_lds_offset);
2840
2841 /* Leave a hole corresponding to the two input VGPRs. This ensures that
2842 * the invocation_id output does not alias the param_tcs_rel_ids input,
2843 * which saves a V_MOV on gfx9.
2844 */
2845 vgpr += 2;
2846
2847 ret = LLVMBuildInsertValue(builder, ret, rel_patch_id, vgpr++, "");
2848 ret = LLVMBuildInsertValue(builder, ret, invocation_id, vgpr++, "");
2849 ret = LLVMBuildInsertValue(builder, ret, tf_lds_offset, vgpr++, "");
2850 ctx->return_value = ret;
2851 }
2852
2853 /* Pass TCS inputs from LS to TCS on GFX9. */
2854 static void si_set_ls_return_value_for_tcs(struct si_shader_context *ctx)
2855 {
2856 LLVMValueRef ret = ctx->return_value;
2857
2858 ret = si_insert_input_ptr_as_2xi32(ctx, ret, ctx->param_rw_buffers, 0);
2859 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_offset, 2);
2860 ret = si_insert_input_ret(ctx, ret, ctx->param_merged_wave_info, 3);
2861 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_factor_offset, 4);
2862 ret = si_insert_input_ret(ctx, ret, ctx->param_merged_scratch_offset, 5);
2863
2864 ret = si_insert_input_ret(ctx, ret, ctx->param_vs_state_bits,
2865 8 + SI_SGPR_VS_STATE_BITS);
2866 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_layout,
2867 8 + GFX9_SGPR_TCS_OFFCHIP_LAYOUT);
2868 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_out_lds_offsets,
2869 8 + GFX9_SGPR_TCS_OUT_OFFSETS);
2870 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_out_lds_layout,
2871 8 + GFX9_SGPR_TCS_OUT_LAYOUT);
2872 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_addr_base64k,
2873 8 + GFX9_SGPR_TCS_OFFCHIP_ADDR_BASE64K);
2874 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_factor_addr_base64k,
2875 8 + GFX9_SGPR_TCS_FACTOR_ADDR_BASE64K);
2876
2877 unsigned desc_param = ctx->param_tcs_factor_addr_base64k + 2;
2878 ret = si_insert_input_ptr_as_2xi32(ctx, ret, desc_param,
2879 8 + GFX9_SGPR_TCS_CONST_AND_SHADER_BUFFERS);
2880 ret = si_insert_input_ptr_as_2xi32(ctx, ret, desc_param + 1,
2881 8 + GFX9_SGPR_TCS_SAMPLERS_AND_IMAGES);
2882
2883 unsigned vgpr = 8 + GFX9_TCS_NUM_USER_SGPR;
2884 ret = si_insert_input_ret_float(ctx, ret,
2885 ctx->param_tcs_patch_id, vgpr++);
2886 ret = si_insert_input_ret_float(ctx, ret,
2887 ctx->param_tcs_rel_ids, vgpr++);
2888 ctx->return_value = ret;
2889 }
2890
2891 /* Pass GS inputs from ES to GS on GFX9. */
2892 static void si_set_es_return_value_for_gs(struct si_shader_context *ctx)
2893 {
2894 LLVMValueRef ret = ctx->return_value;
2895
2896 ret = si_insert_input_ptr_as_2xi32(ctx, ret, ctx->param_rw_buffers, 0);
2897 ret = si_insert_input_ret(ctx, ret, ctx->param_gs2vs_offset, 2);
2898 ret = si_insert_input_ret(ctx, ret, ctx->param_merged_wave_info, 3);
2899
2900 ret = si_insert_input_ret(ctx, ret, ctx->param_merged_scratch_offset, 5);
2901
2902 unsigned desc_param = ctx->param_vs_state_bits + 1;
2903 ret = si_insert_input_ptr_as_2xi32(ctx, ret, desc_param,
2904 8 + GFX9_SGPR_GS_CONST_AND_SHADER_BUFFERS);
2905 ret = si_insert_input_ptr_as_2xi32(ctx, ret, desc_param + 1,
2906 8 + GFX9_SGPR_GS_SAMPLERS_AND_IMAGES);
2907
2908 unsigned vgpr = 8 + GFX9_GS_NUM_USER_SGPR;
2909 for (unsigned i = 0; i < 5; i++) {
2910 unsigned param = ctx->param_gs_vtx01_offset + i;
2911 ret = si_insert_input_ret_float(ctx, ret, param, vgpr++);
2912 }
2913 ctx->return_value = ret;
2914 }
2915
2916 static void si_llvm_emit_ls_epilogue(struct lp_build_tgsi_context *bld_base)
2917 {
2918 struct si_shader_context *ctx = si_shader_context(bld_base);
2919 struct si_shader *shader = ctx->shader;
2920 struct tgsi_shader_info *info = &shader->selector->info;
2921 struct gallivm_state *gallivm = &ctx->gallivm;
2922 unsigned i, chan;
2923 LLVMValueRef vertex_id = LLVMGetParam(ctx->main_fn,
2924 ctx->param_rel_auto_id);
2925 LLVMValueRef vertex_dw_stride =
2926 unpack_param(ctx, ctx->param_vs_state_bits, 24, 8);
2927 LLVMValueRef base_dw_addr = LLVMBuildMul(gallivm->builder, vertex_id,
2928 vertex_dw_stride, "");
2929
2930 /* Write outputs to LDS. The next shader (TCS aka HS) will read
2931 * its inputs from it. */
2932 for (i = 0; i < info->num_outputs; i++) {
2933 LLVMValueRef *out_ptr = ctx->outputs[i];
2934 unsigned name = info->output_semantic_name[i];
2935 unsigned index = info->output_semantic_index[i];
2936
2937 /* The ARB_shader_viewport_layer_array spec contains the
2938 * following issue:
2939 *
2940 * 2) What happens if gl_ViewportIndex or gl_Layer is
2941 * written in the vertex shader and a geometry shader is
2942 * present?
2943 *
2944 * RESOLVED: The value written by the last vertex processing
2945 * stage is used. If the last vertex processing stage
2946 * (vertex, tessellation evaluation or geometry) does not
2947 * statically assign to gl_ViewportIndex or gl_Layer, index
2948 * or layer zero is assumed.
2949 *
2950 * So writes to those outputs in VS-as-LS are simply ignored.
2951 */
2952 if (name == TGSI_SEMANTIC_LAYER ||
2953 name == TGSI_SEMANTIC_VIEWPORT_INDEX)
2954 continue;
2955
2956 int param = si_shader_io_get_unique_index(name, index);
2957 LLVMValueRef dw_addr = LLVMBuildAdd(gallivm->builder, base_dw_addr,
2958 LLVMConstInt(ctx->i32, param * 4, 0), "");
2959
2960 for (chan = 0; chan < 4; chan++) {
2961 lds_store(bld_base, chan, dw_addr,
2962 LLVMBuildLoad(gallivm->builder, out_ptr[chan], ""));
2963 }
2964 }
2965
2966 if (ctx->screen->b.chip_class >= GFX9)
2967 si_set_ls_return_value_for_tcs(ctx);
2968 }
2969
2970 static void si_llvm_emit_es_epilogue(struct lp_build_tgsi_context *bld_base)
2971 {
2972 struct si_shader_context *ctx = si_shader_context(bld_base);
2973 struct gallivm_state *gallivm = &ctx->gallivm;
2974 struct si_shader *es = ctx->shader;
2975 struct tgsi_shader_info *info = &es->selector->info;
2976 LLVMValueRef soffset = LLVMGetParam(ctx->main_fn,
2977 ctx->param_es2gs_offset);
2978 LLVMValueRef lds_base = NULL;
2979 unsigned chan;
2980 int i;
2981
2982 if (ctx->screen->b.chip_class >= GFX9 && info->num_outputs) {
2983 unsigned itemsize_dw = es->selector->esgs_itemsize / 4;
2984 LLVMValueRef vertex_idx = ac_get_thread_id(&ctx->ac);
2985 LLVMValueRef wave_idx = unpack_param(ctx, ctx->param_merged_wave_info, 24, 4);
2986 vertex_idx = LLVMBuildOr(gallivm->builder, vertex_idx,
2987 LLVMBuildMul(gallivm->builder, wave_idx,
2988 LLVMConstInt(ctx->i32, 64, false), ""), "");
2989 lds_base = LLVMBuildMul(gallivm->builder, vertex_idx,
2990 LLVMConstInt(ctx->i32, itemsize_dw, 0), "");
2991 }
2992
2993 for (i = 0; i < info->num_outputs; i++) {
2994 LLVMValueRef *out_ptr = ctx->outputs[i];
2995 int param;
2996
2997 if (info->output_semantic_name[i] == TGSI_SEMANTIC_VIEWPORT_INDEX ||
2998 info->output_semantic_name[i] == TGSI_SEMANTIC_LAYER)
2999 continue;
3000
3001 param = si_shader_io_get_unique_index(info->output_semantic_name[i],
3002 info->output_semantic_index[i]);
3003
3004 for (chan = 0; chan < 4; chan++) {
3005 LLVMValueRef out_val = LLVMBuildLoad(gallivm->builder, out_ptr[chan], "");
3006 out_val = LLVMBuildBitCast(gallivm->builder, out_val, ctx->i32, "");
3007
3008 /* GFX9 has the ESGS ring in LDS. */
3009 if (ctx->screen->b.chip_class >= GFX9) {
3010 lds_store(bld_base, param * 4 + chan, lds_base, out_val);
3011 continue;
3012 }
3013
3014 ac_build_buffer_store_dword(&ctx->ac,
3015 ctx->esgs_ring,
3016 out_val, 1, NULL, soffset,
3017 (4 * param + chan) * 4,
3018 1, 1, true, true);
3019 }
3020 }
3021
3022 if (ctx->screen->b.chip_class >= GFX9)
3023 si_set_es_return_value_for_gs(ctx);
3024 }
3025
3026 static LLVMValueRef si_get_gs_wave_id(struct si_shader_context *ctx)
3027 {
3028 if (ctx->screen->b.chip_class >= GFX9)
3029 return unpack_param(ctx, ctx->param_merged_wave_info, 16, 8);
3030 else
3031 return LLVMGetParam(ctx->main_fn, ctx->param_gs_wave_id);
3032 }
3033
3034 static void si_llvm_emit_gs_epilogue(struct lp_build_tgsi_context *bld_base)
3035 {
3036 struct si_shader_context *ctx = si_shader_context(bld_base);
3037
3038 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_NOP | AC_SENDMSG_GS_DONE,
3039 si_get_gs_wave_id(ctx));
3040
3041 if (ctx->screen->b.chip_class >= GFX9)
3042 lp_build_endif(&ctx->merged_wrap_if_state);
3043 }
3044
3045 static void si_llvm_emit_vs_epilogue(struct ac_shader_abi *abi,
3046 unsigned max_outputs,
3047 LLVMValueRef *addrs)
3048 {
3049 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
3050 struct gallivm_state *gallivm = &ctx->gallivm;
3051 struct tgsi_shader_info *info = &ctx->shader->selector->info;
3052 struct si_shader_output_values *outputs = NULL;
3053 int i,j;
3054
3055 assert(!ctx->shader->is_gs_copy_shader);
3056 assert(info->num_outputs <= max_outputs);
3057
3058 outputs = MALLOC((info->num_outputs + 1) * sizeof(outputs[0]));
3059
3060 /* Vertex color clamping.
3061 *
3062 * This uses a state constant loaded in a user data SGPR and
3063 * an IF statement is added that clamps all colors if the constant
3064 * is true.
3065 */
3066 if (ctx->type == PIPE_SHADER_VERTEX) {
3067 struct lp_build_if_state if_ctx;
3068 LLVMValueRef cond = NULL;
3069 LLVMValueRef addr, val;
3070
3071 for (i = 0; i < info->num_outputs; i++) {
3072 if (info->output_semantic_name[i] != TGSI_SEMANTIC_COLOR &&
3073 info->output_semantic_name[i] != TGSI_SEMANTIC_BCOLOR)
3074 continue;
3075
3076 /* We've found a color. */
3077 if (!cond) {
3078 /* The state is in the first bit of the user SGPR. */
3079 cond = LLVMGetParam(ctx->main_fn,
3080 ctx->param_vs_state_bits);
3081 cond = LLVMBuildTrunc(gallivm->builder, cond,
3082 ctx->i1, "");
3083 lp_build_if(&if_ctx, gallivm, cond);
3084 }
3085
3086 for (j = 0; j < 4; j++) {
3087 addr = addrs[4 * i + j];
3088 val = LLVMBuildLoad(gallivm->builder, addr, "");
3089 val = ac_build_clamp(&ctx->ac, val);
3090 LLVMBuildStore(gallivm->builder, val, addr);
3091 }
3092 }
3093
3094 if (cond)
3095 lp_build_endif(&if_ctx);
3096 }
3097
3098 for (i = 0; i < info->num_outputs; i++) {
3099 outputs[i].semantic_name = info->output_semantic_name[i];
3100 outputs[i].semantic_index = info->output_semantic_index[i];
3101
3102 for (j = 0; j < 4; j++) {
3103 outputs[i].values[j] =
3104 LLVMBuildLoad(gallivm->builder,
3105 addrs[4 * i + j],
3106 "");
3107 outputs[i].vertex_stream[j] =
3108 (info->output_streams[i] >> (2 * j)) & 3;
3109 }
3110 }
3111
3112 if (ctx->shader->selector->so.num_outputs)
3113 si_llvm_emit_streamout(ctx, outputs, i, 0);
3114
3115 /* Export PrimitiveID. */
3116 if (ctx->shader->key.mono.u.vs_export_prim_id) {
3117 outputs[i].semantic_name = TGSI_SEMANTIC_PRIMID;
3118 outputs[i].semantic_index = 0;
3119 outputs[i].values[0] = LLVMBuildBitCast(gallivm->builder,
3120 get_primitive_id(ctx, 0), ctx->f32, "");
3121 for (j = 1; j < 4; j++)
3122 outputs[i].values[j] = LLVMConstReal(ctx->f32, 0);
3123
3124 memset(outputs[i].vertex_stream, 0,
3125 sizeof(outputs[i].vertex_stream));
3126 i++;
3127 }
3128
3129 si_llvm_export_vs(&ctx->bld_base, outputs, i);
3130 FREE(outputs);
3131 }
3132
3133 static void si_tgsi_emit_epilogue(struct lp_build_tgsi_context *bld_base)
3134 {
3135 struct si_shader_context *ctx = si_shader_context(bld_base);
3136
3137 ctx->abi.emit_outputs(&ctx->abi, RADEON_LLVM_MAX_OUTPUTS,
3138 &ctx->outputs[0][0]);
3139 }
3140
3141 struct si_ps_exports {
3142 unsigned num;
3143 struct ac_export_args args[10];
3144 };
3145
3146 unsigned si_get_spi_shader_z_format(bool writes_z, bool writes_stencil,
3147 bool writes_samplemask)
3148 {
3149 if (writes_z) {
3150 /* Z needs 32 bits. */
3151 if (writes_samplemask)
3152 return V_028710_SPI_SHADER_32_ABGR;
3153 else if (writes_stencil)
3154 return V_028710_SPI_SHADER_32_GR;
3155 else
3156 return V_028710_SPI_SHADER_32_R;
3157 } else if (writes_stencil || writes_samplemask) {
3158 /* Both stencil and sample mask need only 16 bits. */
3159 return V_028710_SPI_SHADER_UINT16_ABGR;
3160 } else {
3161 return V_028710_SPI_SHADER_ZERO;
3162 }
3163 }
3164
3165 static void si_export_mrt_z(struct lp_build_tgsi_context *bld_base,
3166 LLVMValueRef depth, LLVMValueRef stencil,
3167 LLVMValueRef samplemask, struct si_ps_exports *exp)
3168 {
3169 struct si_shader_context *ctx = si_shader_context(bld_base);
3170 struct lp_build_context *base = &bld_base->base;
3171 struct ac_export_args args;
3172 unsigned mask = 0;
3173 unsigned format = si_get_spi_shader_z_format(depth != NULL,
3174 stencil != NULL,
3175 samplemask != NULL);
3176
3177 assert(depth || stencil || samplemask);
3178
3179 args.valid_mask = 1; /* whether the EXEC mask is valid */
3180 args.done = 1; /* DONE bit */
3181
3182 /* Specify the target we are exporting */
3183 args.target = V_008DFC_SQ_EXP_MRTZ;
3184
3185 args.compr = 0; /* COMP flag */
3186 args.out[0] = base->undef; /* R, depth */
3187 args.out[1] = base->undef; /* G, stencil test value[0:7], stencil op value[8:15] */
3188 args.out[2] = base->undef; /* B, sample mask */
3189 args.out[3] = base->undef; /* A, alpha to mask */
3190
3191 if (format == V_028710_SPI_SHADER_UINT16_ABGR) {
3192 assert(!depth);
3193 args.compr = 1; /* COMPR flag */
3194
3195 if (stencil) {
3196 /* Stencil should be in X[23:16]. */
3197 stencil = bitcast(bld_base, TGSI_TYPE_UNSIGNED, stencil);
3198 stencil = LLVMBuildShl(ctx->gallivm.builder, stencil,
3199 LLVMConstInt(ctx->i32, 16, 0), "");
3200 args.out[0] = bitcast(bld_base, TGSI_TYPE_FLOAT, stencil);
3201 mask |= 0x3;
3202 }
3203 if (samplemask) {
3204 /* SampleMask should be in Y[15:0]. */
3205 args.out[1] = samplemask;
3206 mask |= 0xc;
3207 }
3208 } else {
3209 if (depth) {
3210 args.out[0] = depth;
3211 mask |= 0x1;
3212 }
3213 if (stencil) {
3214 args.out[1] = stencil;
3215 mask |= 0x2;
3216 }
3217 if (samplemask) {
3218 args.out[2] = samplemask;
3219 mask |= 0x4;
3220 }
3221 }
3222
3223 /* SI (except OLAND and HAINAN) has a bug that it only looks
3224 * at the X writemask component. */
3225 if (ctx->screen->b.chip_class == SI &&
3226 ctx->screen->b.family != CHIP_OLAND &&
3227 ctx->screen->b.family != CHIP_HAINAN)
3228 mask |= 0x1;
3229
3230 /* Specify which components to enable */
3231 args.enabled_channels = mask;
3232
3233 memcpy(&exp->args[exp->num++], &args, sizeof(args));
3234 }
3235
3236 static void si_export_mrt_color(struct lp_build_tgsi_context *bld_base,
3237 LLVMValueRef *color, unsigned index,
3238 unsigned samplemask_param,
3239 bool is_last, struct si_ps_exports *exp)
3240 {
3241 struct si_shader_context *ctx = si_shader_context(bld_base);
3242 struct lp_build_context *base = &bld_base->base;
3243 int i;
3244
3245 /* Clamp color */
3246 if (ctx->shader->key.part.ps.epilog.clamp_color)
3247 for (i = 0; i < 4; i++)
3248 color[i] = ac_build_clamp(&ctx->ac, color[i]);
3249
3250 /* Alpha to one */
3251 if (ctx->shader->key.part.ps.epilog.alpha_to_one)
3252 color[3] = base->one;
3253
3254 /* Alpha test */
3255 if (index == 0 &&
3256 ctx->shader->key.part.ps.epilog.alpha_func != PIPE_FUNC_ALWAYS)
3257 si_alpha_test(bld_base, color[3]);
3258
3259 /* Line & polygon smoothing */
3260 if (ctx->shader->key.part.ps.epilog.poly_line_smoothing)
3261 color[3] = si_scale_alpha_by_sample_mask(bld_base, color[3],
3262 samplemask_param);
3263
3264 /* If last_cbuf > 0, FS_COLOR0_WRITES_ALL_CBUFS is true. */
3265 if (ctx->shader->key.part.ps.epilog.last_cbuf > 0) {
3266 struct ac_export_args args[8];
3267 int c, last = -1;
3268
3269 /* Get the export arguments, also find out what the last one is. */
3270 for (c = 0; c <= ctx->shader->key.part.ps.epilog.last_cbuf; c++) {
3271 si_llvm_init_export_args(bld_base, color,
3272 V_008DFC_SQ_EXP_MRT + c, &args[c]);
3273 if (args[c].enabled_channels)
3274 last = c;
3275 }
3276
3277 /* Emit all exports. */
3278 for (c = 0; c <= ctx->shader->key.part.ps.epilog.last_cbuf; c++) {
3279 if (is_last && last == c) {
3280 args[c].valid_mask = 1; /* whether the EXEC mask is valid */
3281 args[c].done = 1; /* DONE bit */
3282 } else if (!args[c].enabled_channels)
3283 continue; /* unnecessary NULL export */
3284
3285 memcpy(&exp->args[exp->num++], &args[c], sizeof(args[c]));
3286 }
3287 } else {
3288 struct ac_export_args args;
3289
3290 /* Export */
3291 si_llvm_init_export_args(bld_base, color, V_008DFC_SQ_EXP_MRT + index,
3292 &args);
3293 if (is_last) {
3294 args.valid_mask = 1; /* whether the EXEC mask is valid */
3295 args.done = 1; /* DONE bit */
3296 } else if (!args.enabled_channels)
3297 return; /* unnecessary NULL export */
3298
3299 memcpy(&exp->args[exp->num++], &args, sizeof(args));
3300 }
3301 }
3302
3303 static void si_emit_ps_exports(struct si_shader_context *ctx,
3304 struct si_ps_exports *exp)
3305 {
3306 for (unsigned i = 0; i < exp->num; i++)
3307 ac_build_export(&ctx->ac, &exp->args[i]);
3308 }
3309
3310 static void si_export_null(struct lp_build_tgsi_context *bld_base)
3311 {
3312 struct si_shader_context *ctx = si_shader_context(bld_base);
3313 struct lp_build_context *base = &bld_base->base;
3314 struct ac_export_args args;
3315
3316 args.enabled_channels = 0x0; /* enabled channels */
3317 args.valid_mask = 1; /* whether the EXEC mask is valid */
3318 args.done = 1; /* DONE bit */
3319 args.target = V_008DFC_SQ_EXP_NULL;
3320 args.compr = 0; /* COMPR flag (0 = 32-bit export) */
3321 args.out[0] = base->undef; /* R */
3322 args.out[1] = base->undef; /* G */
3323 args.out[2] = base->undef; /* B */
3324 args.out[3] = base->undef; /* A */
3325
3326 ac_build_export(&ctx->ac, &args);
3327 }
3328
3329 /**
3330 * Return PS outputs in this order:
3331 *
3332 * v[0:3] = color0.xyzw
3333 * v[4:7] = color1.xyzw
3334 * ...
3335 * vN+0 = Depth
3336 * vN+1 = Stencil
3337 * vN+2 = SampleMask
3338 * vN+3 = SampleMaskIn (used for OpenGL smoothing)
3339 *
3340 * The alpha-ref SGPR is returned via its original location.
3341 */
3342 static void si_llvm_return_fs_outputs(struct lp_build_tgsi_context *bld_base)
3343 {
3344 struct si_shader_context *ctx = si_shader_context(bld_base);
3345 struct si_shader *shader = ctx->shader;
3346 struct tgsi_shader_info *info = &shader->selector->info;
3347 LLVMBuilderRef builder = ctx->gallivm.builder;
3348 unsigned i, j, first_vgpr, vgpr;
3349
3350 LLVMValueRef color[8][4] = {};
3351 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
3352 LLVMValueRef ret;
3353
3354 if (ctx->postponed_kill)
3355 ac_build_kill(&ctx->ac, LLVMBuildLoad(builder, ctx->postponed_kill, ""));
3356
3357 /* Read the output values. */
3358 for (i = 0; i < info->num_outputs; i++) {
3359 unsigned semantic_name = info->output_semantic_name[i];
3360 unsigned semantic_index = info->output_semantic_index[i];
3361
3362 switch (semantic_name) {
3363 case TGSI_SEMANTIC_COLOR:
3364 assert(semantic_index < 8);
3365 for (j = 0; j < 4; j++) {
3366 LLVMValueRef ptr = ctx->outputs[i][j];
3367 LLVMValueRef result = LLVMBuildLoad(builder, ptr, "");
3368 color[semantic_index][j] = result;
3369 }
3370 break;
3371 case TGSI_SEMANTIC_POSITION:
3372 depth = LLVMBuildLoad(builder,
3373 ctx->outputs[i][2], "");
3374 break;
3375 case TGSI_SEMANTIC_STENCIL:
3376 stencil = LLVMBuildLoad(builder,
3377 ctx->outputs[i][1], "");
3378 break;
3379 case TGSI_SEMANTIC_SAMPLEMASK:
3380 samplemask = LLVMBuildLoad(builder,
3381 ctx->outputs[i][0], "");
3382 break;
3383 default:
3384 fprintf(stderr, "Warning: SI unhandled fs output type:%d\n",
3385 semantic_name);
3386 }
3387 }
3388
3389 /* Fill the return structure. */
3390 ret = ctx->return_value;
3391
3392 /* Set SGPRs. */
3393 ret = LLVMBuildInsertValue(builder, ret,
3394 bitcast(bld_base, TGSI_TYPE_SIGNED,
3395 LLVMGetParam(ctx->main_fn,
3396 SI_PARAM_ALPHA_REF)),
3397 SI_SGPR_ALPHA_REF, "");
3398
3399 /* Set VGPRs */
3400 first_vgpr = vgpr = SI_SGPR_ALPHA_REF + 1;
3401 for (i = 0; i < ARRAY_SIZE(color); i++) {
3402 if (!color[i][0])
3403 continue;
3404
3405 for (j = 0; j < 4; j++)
3406 ret = LLVMBuildInsertValue(builder, ret, color[i][j], vgpr++, "");
3407 }
3408 if (depth)
3409 ret = LLVMBuildInsertValue(builder, ret, depth, vgpr++, "");
3410 if (stencil)
3411 ret = LLVMBuildInsertValue(builder, ret, stencil, vgpr++, "");
3412 if (samplemask)
3413 ret = LLVMBuildInsertValue(builder, ret, samplemask, vgpr++, "");
3414
3415 /* Add the input sample mask for smoothing at the end. */
3416 if (vgpr < first_vgpr + PS_EPILOG_SAMPLEMASK_MIN_LOC)
3417 vgpr = first_vgpr + PS_EPILOG_SAMPLEMASK_MIN_LOC;
3418 ret = LLVMBuildInsertValue(builder, ret,
3419 LLVMGetParam(ctx->main_fn,
3420 SI_PARAM_SAMPLE_COVERAGE), vgpr++, "");
3421
3422 ctx->return_value = ret;
3423 }
3424
3425 /* Prevent optimizations (at least of memory accesses) across the current
3426 * point in the program by emitting empty inline assembly that is marked as
3427 * having side effects.
3428 *
3429 * Optionally, a value can be passed through the inline assembly to prevent
3430 * LLVM from hoisting calls to ReadNone functions.
3431 */
3432 static void emit_optimization_barrier(struct si_shader_context *ctx,
3433 LLVMValueRef *pvgpr)
3434 {
3435 static int counter = 0;
3436
3437 LLVMBuilderRef builder = ctx->gallivm.builder;
3438 char code[16];
3439
3440 snprintf(code, sizeof(code), "; %d", p_atomic_inc_return(&counter));
3441
3442 if (!pvgpr) {
3443 LLVMTypeRef ftype = LLVMFunctionType(ctx->voidt, NULL, 0, false);
3444 LLVMValueRef inlineasm = LLVMConstInlineAsm(ftype, code, "", true, false);
3445 LLVMBuildCall(builder, inlineasm, NULL, 0, "");
3446 } else {
3447 LLVMTypeRef ftype = LLVMFunctionType(ctx->i32, &ctx->i32, 1, false);
3448 LLVMValueRef inlineasm = LLVMConstInlineAsm(ftype, code, "=v,0", true, false);
3449 LLVMValueRef vgpr = *pvgpr;
3450 LLVMTypeRef vgpr_type = LLVMTypeOf(vgpr);
3451 unsigned vgpr_size = llvm_get_type_size(vgpr_type);
3452 LLVMValueRef vgpr0;
3453
3454 assert(vgpr_size % 4 == 0);
3455
3456 vgpr = LLVMBuildBitCast(builder, vgpr, LLVMVectorType(ctx->i32, vgpr_size / 4), "");
3457 vgpr0 = LLVMBuildExtractElement(builder, vgpr, ctx->i32_0, "");
3458 vgpr0 = LLVMBuildCall(builder, inlineasm, &vgpr0, 1, "");
3459 vgpr = LLVMBuildInsertElement(builder, vgpr, vgpr0, ctx->i32_0, "");
3460 vgpr = LLVMBuildBitCast(builder, vgpr, vgpr_type, "");
3461
3462 *pvgpr = vgpr;
3463 }
3464 }
3465
3466 void si_emit_waitcnt(struct si_shader_context *ctx, unsigned simm16)
3467 {
3468 struct gallivm_state *gallivm = &ctx->gallivm;
3469 LLVMBuilderRef builder = gallivm->builder;
3470 LLVMValueRef args[1] = {
3471 LLVMConstInt(ctx->i32, simm16, 0)
3472 };
3473 lp_build_intrinsic(builder, "llvm.amdgcn.s.waitcnt",
3474 ctx->voidt, args, 1, 0);
3475 }
3476
3477 static void membar_emit(
3478 const struct lp_build_tgsi_action *action,
3479 struct lp_build_tgsi_context *bld_base,
3480 struct lp_build_emit_data *emit_data)
3481 {
3482 struct si_shader_context *ctx = si_shader_context(bld_base);
3483 LLVMValueRef src0 = lp_build_emit_fetch(bld_base, emit_data->inst, 0, 0);
3484 unsigned flags = LLVMConstIntGetZExtValue(src0);
3485 unsigned waitcnt = NOOP_WAITCNT;
3486
3487 if (flags & TGSI_MEMBAR_THREAD_GROUP)
3488 waitcnt &= VM_CNT & LGKM_CNT;
3489
3490 if (flags & (TGSI_MEMBAR_ATOMIC_BUFFER |
3491 TGSI_MEMBAR_SHADER_BUFFER |
3492 TGSI_MEMBAR_SHADER_IMAGE))
3493 waitcnt &= VM_CNT;
3494
3495 if (flags & TGSI_MEMBAR_SHARED)
3496 waitcnt &= LGKM_CNT;
3497
3498 if (waitcnt != NOOP_WAITCNT)
3499 si_emit_waitcnt(ctx, waitcnt);
3500 }
3501
3502 static void clock_emit(
3503 const struct lp_build_tgsi_action *action,
3504 struct lp_build_tgsi_context *bld_base,
3505 struct lp_build_emit_data *emit_data)
3506 {
3507 struct si_shader_context *ctx = si_shader_context(bld_base);
3508 struct gallivm_state *gallivm = &ctx->gallivm;
3509 LLVMValueRef tmp;
3510
3511 tmp = lp_build_intrinsic(gallivm->builder, "llvm.readcyclecounter",
3512 ctx->i64, NULL, 0, 0);
3513 tmp = LLVMBuildBitCast(gallivm->builder, tmp, ctx->v2i32, "");
3514
3515 emit_data->output[0] =
3516 LLVMBuildExtractElement(gallivm->builder, tmp, ctx->i32_0, "");
3517 emit_data->output[1] =
3518 LLVMBuildExtractElement(gallivm->builder, tmp, ctx->i32_1, "");
3519 }
3520
3521 LLVMTypeRef si_const_array(LLVMTypeRef elem_type, int num_elements)
3522 {
3523 return LLVMPointerType(LLVMArrayType(elem_type, num_elements),
3524 CONST_ADDR_SPACE);
3525 }
3526
3527 static void si_llvm_emit_ddxy(
3528 const struct lp_build_tgsi_action *action,
3529 struct lp_build_tgsi_context *bld_base,
3530 struct lp_build_emit_data *emit_data)
3531 {
3532 struct si_shader_context *ctx = si_shader_context(bld_base);
3533 struct gallivm_state *gallivm = &ctx->gallivm;
3534 unsigned opcode = emit_data->info->opcode;
3535 LLVMValueRef val;
3536 int idx;
3537 unsigned mask;
3538
3539 if (opcode == TGSI_OPCODE_DDX_FINE)
3540 mask = AC_TID_MASK_LEFT;
3541 else if (opcode == TGSI_OPCODE_DDY_FINE)
3542 mask = AC_TID_MASK_TOP;
3543 else
3544 mask = AC_TID_MASK_TOP_LEFT;
3545
3546 /* for DDX we want to next X pixel, DDY next Y pixel. */
3547 idx = (opcode == TGSI_OPCODE_DDX || opcode == TGSI_OPCODE_DDX_FINE) ? 1 : 2;
3548
3549 val = LLVMBuildBitCast(gallivm->builder, emit_data->args[0], ctx->i32, "");
3550 val = ac_build_ddxy(&ctx->ac, ctx->screen->has_ds_bpermute,
3551 mask, idx, ctx->lds, val);
3552 emit_data->output[emit_data->chan] = val;
3553 }
3554
3555 /*
3556 * this takes an I,J coordinate pair,
3557 * and works out the X and Y derivatives.
3558 * it returns DDX(I), DDX(J), DDY(I), DDY(J).
3559 */
3560 static LLVMValueRef si_llvm_emit_ddxy_interp(
3561 struct lp_build_tgsi_context *bld_base,
3562 LLVMValueRef interp_ij)
3563 {
3564 struct si_shader_context *ctx = si_shader_context(bld_base);
3565 struct gallivm_state *gallivm = &ctx->gallivm;
3566 LLVMValueRef result[4], a;
3567 unsigned i;
3568
3569 for (i = 0; i < 2; i++) {
3570 a = LLVMBuildExtractElement(gallivm->builder, interp_ij,
3571 LLVMConstInt(ctx->i32, i, 0), "");
3572 result[i] = lp_build_emit_llvm_unary(bld_base, TGSI_OPCODE_DDX, a);
3573 result[2+i] = lp_build_emit_llvm_unary(bld_base, TGSI_OPCODE_DDY, a);
3574 }
3575
3576 return lp_build_gather_values(gallivm, result, 4);
3577 }
3578
3579 static void interp_fetch_args(
3580 struct lp_build_tgsi_context *bld_base,
3581 struct lp_build_emit_data *emit_data)
3582 {
3583 struct si_shader_context *ctx = si_shader_context(bld_base);
3584 struct gallivm_state *gallivm = &ctx->gallivm;
3585 const struct tgsi_full_instruction *inst = emit_data->inst;
3586
3587 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET) {
3588 /* offset is in second src, first two channels */
3589 emit_data->args[0] = lp_build_emit_fetch(bld_base,
3590 emit_data->inst, 1,
3591 TGSI_CHAN_X);
3592 emit_data->args[1] = lp_build_emit_fetch(bld_base,
3593 emit_data->inst, 1,
3594 TGSI_CHAN_Y);
3595 emit_data->arg_count = 2;
3596 } else if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
3597 LLVMValueRef sample_position;
3598 LLVMValueRef sample_id;
3599 LLVMValueRef halfval = LLVMConstReal(ctx->f32, 0.5f);
3600
3601 /* fetch sample ID, then fetch its sample position,
3602 * and place into first two channels.
3603 */
3604 sample_id = lp_build_emit_fetch(bld_base,
3605 emit_data->inst, 1, TGSI_CHAN_X);
3606 sample_id = LLVMBuildBitCast(gallivm->builder, sample_id,
3607 ctx->i32, "");
3608 sample_position = load_sample_position(ctx, sample_id);
3609
3610 emit_data->args[0] = LLVMBuildExtractElement(gallivm->builder,
3611 sample_position,
3612 ctx->i32_0, "");
3613
3614 emit_data->args[0] = LLVMBuildFSub(gallivm->builder, emit_data->args[0], halfval, "");
3615 emit_data->args[1] = LLVMBuildExtractElement(gallivm->builder,
3616 sample_position,
3617 ctx->i32_1, "");
3618 emit_data->args[1] = LLVMBuildFSub(gallivm->builder, emit_data->args[1], halfval, "");
3619 emit_data->arg_count = 2;
3620 }
3621 }
3622
3623 static void build_interp_intrinsic(const struct lp_build_tgsi_action *action,
3624 struct lp_build_tgsi_context *bld_base,
3625 struct lp_build_emit_data *emit_data)
3626 {
3627 struct si_shader_context *ctx = si_shader_context(bld_base);
3628 struct si_shader *shader = ctx->shader;
3629 struct gallivm_state *gallivm = &ctx->gallivm;
3630 const struct tgsi_shader_info *info = &shader->selector->info;
3631 LLVMValueRef interp_param;
3632 const struct tgsi_full_instruction *inst = emit_data->inst;
3633 const struct tgsi_full_src_register *input = &inst->Src[0];
3634 int input_base, input_array_size;
3635 int chan;
3636 int i;
3637 LLVMValueRef prim_mask = LLVMGetParam(ctx->main_fn, SI_PARAM_PRIM_MASK);
3638 LLVMValueRef array_idx;
3639 int interp_param_idx;
3640 unsigned interp;
3641 unsigned location;
3642
3643 assert(input->Register.File == TGSI_FILE_INPUT);
3644
3645 if (input->Register.Indirect) {
3646 unsigned array_id = input->Indirect.ArrayID;
3647
3648 if (array_id) {
3649 input_base = info->input_array_first[array_id];
3650 input_array_size = info->input_array_last[array_id] - input_base + 1;
3651 } else {
3652 input_base = inst->Src[0].Register.Index;
3653 input_array_size = info->num_inputs - input_base;
3654 }
3655
3656 array_idx = get_indirect_index(ctx, &input->Indirect,
3657 input->Register.Index - input_base);
3658 } else {
3659 input_base = inst->Src[0].Register.Index;
3660 input_array_size = 1;
3661 array_idx = ctx->i32_0;
3662 }
3663
3664 interp = shader->selector->info.input_interpolate[input_base];
3665
3666 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
3667 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE)
3668 location = TGSI_INTERPOLATE_LOC_CENTER;
3669 else
3670 location = TGSI_INTERPOLATE_LOC_CENTROID;
3671
3672 interp_param_idx = lookup_interp_param_index(interp, location);
3673 if (interp_param_idx == -1)
3674 return;
3675 else if (interp_param_idx)
3676 interp_param = LLVMGetParam(ctx->main_fn, interp_param_idx);
3677 else
3678 interp_param = NULL;
3679
3680 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
3681 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
3682 LLVMValueRef ij_out[2];
3683 LLVMValueRef ddxy_out = si_llvm_emit_ddxy_interp(bld_base, interp_param);
3684
3685 /*
3686 * take the I then J parameters, and the DDX/Y for it, and
3687 * calculate the IJ inputs for the interpolator.
3688 * temp1 = ddx * offset/sample.x + I;
3689 * interp_param.I = ddy * offset/sample.y + temp1;
3690 * temp1 = ddx * offset/sample.x + J;
3691 * interp_param.J = ddy * offset/sample.y + temp1;
3692 */
3693 for (i = 0; i < 2; i++) {
3694 LLVMValueRef ix_ll = LLVMConstInt(ctx->i32, i, 0);
3695 LLVMValueRef iy_ll = LLVMConstInt(ctx->i32, i + 2, 0);
3696 LLVMValueRef ddx_el = LLVMBuildExtractElement(gallivm->builder,
3697 ddxy_out, ix_ll, "");
3698 LLVMValueRef ddy_el = LLVMBuildExtractElement(gallivm->builder,
3699 ddxy_out, iy_ll, "");
3700 LLVMValueRef interp_el = LLVMBuildExtractElement(gallivm->builder,
3701 interp_param, ix_ll, "");
3702 LLVMValueRef temp1, temp2;
3703
3704 interp_el = LLVMBuildBitCast(gallivm->builder, interp_el,
3705 ctx->f32, "");
3706
3707 temp1 = LLVMBuildFMul(gallivm->builder, ddx_el, emit_data->args[0], "");
3708
3709 temp1 = LLVMBuildFAdd(gallivm->builder, temp1, interp_el, "");
3710
3711 temp2 = LLVMBuildFMul(gallivm->builder, ddy_el, emit_data->args[1], "");
3712
3713 ij_out[i] = LLVMBuildFAdd(gallivm->builder, temp2, temp1, "");
3714 }
3715 interp_param = lp_build_gather_values(gallivm, ij_out, 2);
3716 }
3717
3718 if (interp_param) {
3719 interp_param = LLVMBuildBitCast(gallivm->builder,
3720 interp_param, LLVMVectorType(ctx->f32, 2), "");
3721 }
3722
3723 for (chan = 0; chan < 4; chan++) {
3724 LLVMValueRef gather = LLVMGetUndef(LLVMVectorType(ctx->f32, input_array_size));
3725 unsigned schan = tgsi_util_get_full_src_register_swizzle(&inst->Src[0], chan);
3726
3727 for (unsigned idx = 0; idx < input_array_size; ++idx) {
3728 LLVMValueRef v, i = NULL, j = NULL;
3729
3730 if (interp_param) {
3731 interp_param = LLVMBuildBitCast(gallivm->builder,
3732 interp_param, LLVMVectorType(ctx->f32, 2), "");
3733 i = LLVMBuildExtractElement(
3734 gallivm->builder, interp_param, ctx->i32_0, "");
3735 j = LLVMBuildExtractElement(
3736 gallivm->builder, interp_param, ctx->i32_1, "");
3737 }
3738 v = si_build_fs_interp(ctx, input_base + idx, schan,
3739 prim_mask, i, j);
3740
3741 gather = LLVMBuildInsertElement(gallivm->builder,
3742 gather, v, LLVMConstInt(ctx->i32, idx, false), "");
3743 }
3744
3745 emit_data->output[chan] = LLVMBuildExtractElement(
3746 gallivm->builder, gather, array_idx, "");
3747 }
3748 }
3749
3750 static LLVMValueRef si_emit_ballot(struct si_shader_context *ctx,
3751 LLVMValueRef value)
3752 {
3753 struct gallivm_state *gallivm = &ctx->gallivm;
3754 LLVMValueRef args[3] = {
3755 value,
3756 ctx->i32_0,
3757 LLVMConstInt(ctx->i32, LLVMIntNE, 0)
3758 };
3759
3760 /* We currently have no other way to prevent LLVM from lifting the icmp
3761 * calls to a dominating basic block.
3762 */
3763 emit_optimization_barrier(ctx, &args[0]);
3764
3765 if (LLVMTypeOf(args[0]) != ctx->i32)
3766 args[0] = LLVMBuildBitCast(gallivm->builder, args[0], ctx->i32, "");
3767
3768 return lp_build_intrinsic(gallivm->builder,
3769 "llvm.amdgcn.icmp.i32",
3770 ctx->i64, args, 3,
3771 LP_FUNC_ATTR_NOUNWIND |
3772 LP_FUNC_ATTR_READNONE |
3773 LP_FUNC_ATTR_CONVERGENT);
3774 }
3775
3776 static void vote_all_emit(
3777 const struct lp_build_tgsi_action *action,
3778 struct lp_build_tgsi_context *bld_base,
3779 struct lp_build_emit_data *emit_data)
3780 {
3781 struct si_shader_context *ctx = si_shader_context(bld_base);
3782 struct gallivm_state *gallivm = &ctx->gallivm;
3783 LLVMValueRef active_set, vote_set;
3784 LLVMValueRef tmp;
3785
3786 active_set = si_emit_ballot(ctx, ctx->i32_1);
3787 vote_set = si_emit_ballot(ctx, emit_data->args[0]);
3788
3789 tmp = LLVMBuildICmp(gallivm->builder, LLVMIntEQ, vote_set, active_set, "");
3790 emit_data->output[emit_data->chan] =
3791 LLVMBuildSExt(gallivm->builder, tmp, ctx->i32, "");
3792 }
3793
3794 static void vote_any_emit(
3795 const struct lp_build_tgsi_action *action,
3796 struct lp_build_tgsi_context *bld_base,
3797 struct lp_build_emit_data *emit_data)
3798 {
3799 struct si_shader_context *ctx = si_shader_context(bld_base);
3800 struct gallivm_state *gallivm = &ctx->gallivm;
3801 LLVMValueRef vote_set;
3802 LLVMValueRef tmp;
3803
3804 vote_set = si_emit_ballot(ctx, emit_data->args[0]);
3805
3806 tmp = LLVMBuildICmp(gallivm->builder, LLVMIntNE,
3807 vote_set, LLVMConstInt(ctx->i64, 0, 0), "");
3808 emit_data->output[emit_data->chan] =
3809 LLVMBuildSExt(gallivm->builder, tmp, ctx->i32, "");
3810 }
3811
3812 static void vote_eq_emit(
3813 const struct lp_build_tgsi_action *action,
3814 struct lp_build_tgsi_context *bld_base,
3815 struct lp_build_emit_data *emit_data)
3816 {
3817 struct si_shader_context *ctx = si_shader_context(bld_base);
3818 struct gallivm_state *gallivm = &ctx->gallivm;
3819 LLVMValueRef active_set, vote_set;
3820 LLVMValueRef all, none, tmp;
3821
3822 active_set = si_emit_ballot(ctx, ctx->i32_1);
3823 vote_set = si_emit_ballot(ctx, emit_data->args[0]);
3824
3825 all = LLVMBuildICmp(gallivm->builder, LLVMIntEQ, vote_set, active_set, "");
3826 none = LLVMBuildICmp(gallivm->builder, LLVMIntEQ,
3827 vote_set, LLVMConstInt(ctx->i64, 0, 0), "");
3828 tmp = LLVMBuildOr(gallivm->builder, all, none, "");
3829 emit_data->output[emit_data->chan] =
3830 LLVMBuildSExt(gallivm->builder, tmp, ctx->i32, "");
3831 }
3832
3833 static void ballot_emit(
3834 const struct lp_build_tgsi_action *action,
3835 struct lp_build_tgsi_context *bld_base,
3836 struct lp_build_emit_data *emit_data)
3837 {
3838 struct si_shader_context *ctx = si_shader_context(bld_base);
3839 LLVMBuilderRef builder = ctx->gallivm.builder;
3840 LLVMValueRef tmp;
3841
3842 tmp = lp_build_emit_fetch(bld_base, emit_data->inst, 0, TGSI_CHAN_X);
3843 tmp = si_emit_ballot(ctx, tmp);
3844 tmp = LLVMBuildBitCast(builder, tmp, ctx->v2i32, "");
3845
3846 emit_data->output[0] = LLVMBuildExtractElement(builder, tmp, ctx->i32_0, "");
3847 emit_data->output[1] = LLVMBuildExtractElement(builder, tmp, ctx->i32_1, "");
3848 }
3849
3850 static void read_invoc_fetch_args(
3851 struct lp_build_tgsi_context *bld_base,
3852 struct lp_build_emit_data *emit_data)
3853 {
3854 emit_data->args[0] = lp_build_emit_fetch(bld_base, emit_data->inst,
3855 0, emit_data->src_chan);
3856
3857 /* Always read the source invocation (= lane) from the X channel. */
3858 emit_data->args[1] = lp_build_emit_fetch(bld_base, emit_data->inst,
3859 1, TGSI_CHAN_X);
3860 emit_data->arg_count = 2;
3861 }
3862
3863 static void read_lane_emit(
3864 const struct lp_build_tgsi_action *action,
3865 struct lp_build_tgsi_context *bld_base,
3866 struct lp_build_emit_data *emit_data)
3867 {
3868 struct si_shader_context *ctx = si_shader_context(bld_base);
3869 LLVMBuilderRef builder = ctx->gallivm.builder;
3870
3871 /* We currently have no other way to prevent LLVM from lifting the icmp
3872 * calls to a dominating basic block.
3873 */
3874 emit_optimization_barrier(ctx, &emit_data->args[0]);
3875
3876 for (unsigned i = 0; i < emit_data->arg_count; ++i) {
3877 emit_data->args[i] = LLVMBuildBitCast(builder, emit_data->args[i],
3878 ctx->i32, "");
3879 }
3880
3881 emit_data->output[emit_data->chan] =
3882 ac_build_intrinsic(&ctx->ac, action->intr_name,
3883 ctx->i32, emit_data->args, emit_data->arg_count,
3884 AC_FUNC_ATTR_READNONE |
3885 AC_FUNC_ATTR_CONVERGENT);
3886 }
3887
3888 static unsigned si_llvm_get_stream(struct lp_build_tgsi_context *bld_base,
3889 struct lp_build_emit_data *emit_data)
3890 {
3891 struct si_shader_context *ctx = si_shader_context(bld_base);
3892 struct tgsi_src_register src0 = emit_data->inst->Src[0].Register;
3893 LLVMValueRef imm;
3894 unsigned stream;
3895
3896 assert(src0.File == TGSI_FILE_IMMEDIATE);
3897
3898 imm = ctx->imms[src0.Index * TGSI_NUM_CHANNELS + src0.SwizzleX];
3899 stream = LLVMConstIntGetZExtValue(imm) & 0x3;
3900 return stream;
3901 }
3902
3903 /* Emit one vertex from the geometry shader */
3904 static void si_llvm_emit_vertex(
3905 const struct lp_build_tgsi_action *action,
3906 struct lp_build_tgsi_context *bld_base,
3907 struct lp_build_emit_data *emit_data)
3908 {
3909 struct si_shader_context *ctx = si_shader_context(bld_base);
3910 struct lp_build_context *uint = &bld_base->uint_bld;
3911 struct si_shader *shader = ctx->shader;
3912 struct tgsi_shader_info *info = &shader->selector->info;
3913 struct gallivm_state *gallivm = &ctx->gallivm;
3914 struct lp_build_if_state if_state;
3915 LLVMValueRef soffset = LLVMGetParam(ctx->main_fn,
3916 ctx->param_gs2vs_offset);
3917 LLVMValueRef gs_next_vertex;
3918 LLVMValueRef can_emit, kill;
3919 unsigned chan, offset;
3920 int i;
3921 unsigned stream;
3922
3923 stream = si_llvm_get_stream(bld_base, emit_data);
3924
3925 /* Write vertex attribute values to GSVS ring */
3926 gs_next_vertex = LLVMBuildLoad(gallivm->builder,
3927 ctx->gs_next_vertex[stream],
3928 "");
3929
3930 /* If this thread has already emitted the declared maximum number of
3931 * vertices, skip the write: excessive vertex emissions are not
3932 * supposed to have any effect.
3933 *
3934 * If the shader has no writes to memory, kill it instead. This skips
3935 * further memory loads and may allow LLVM to skip to the end
3936 * altogether.
3937 */
3938 can_emit = LLVMBuildICmp(gallivm->builder, LLVMIntULT, gs_next_vertex,
3939 LLVMConstInt(ctx->i32,
3940 shader->selector->gs_max_out_vertices, 0), "");
3941
3942 bool use_kill = !info->writes_memory;
3943 if (use_kill) {
3944 kill = lp_build_select(&bld_base->base, can_emit,
3945 LLVMConstReal(ctx->f32, 1.0f),
3946 LLVMConstReal(ctx->f32, -1.0f));
3947
3948 ac_build_kill(&ctx->ac, kill);
3949 } else {
3950 lp_build_if(&if_state, gallivm, can_emit);
3951 }
3952
3953 offset = 0;
3954 for (i = 0; i < info->num_outputs; i++) {
3955 LLVMValueRef *out_ptr = ctx->outputs[i];
3956
3957 for (chan = 0; chan < 4; chan++) {
3958 if (!(info->output_usagemask[i] & (1 << chan)) ||
3959 ((info->output_streams[i] >> (2 * chan)) & 3) != stream)
3960 continue;
3961
3962 LLVMValueRef out_val = LLVMBuildLoad(gallivm->builder, out_ptr[chan], "");
3963 LLVMValueRef voffset =
3964 LLVMConstInt(ctx->i32, offset *
3965 shader->selector->gs_max_out_vertices, 0);
3966 offset++;
3967
3968 voffset = lp_build_add(uint, voffset, gs_next_vertex);
3969 voffset = lp_build_mul_imm(uint, voffset, 4);
3970
3971 out_val = LLVMBuildBitCast(gallivm->builder, out_val, ctx->i32, "");
3972
3973 ac_build_buffer_store_dword(&ctx->ac,
3974 ctx->gsvs_ring[stream],
3975 out_val, 1,
3976 voffset, soffset, 0,
3977 1, 1, true, true);
3978 }
3979 }
3980
3981 gs_next_vertex = lp_build_add(uint, gs_next_vertex,
3982 ctx->i32_1);
3983
3984 LLVMBuildStore(gallivm->builder, gs_next_vertex, ctx->gs_next_vertex[stream]);
3985
3986 /* Signal vertex emission */
3987 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_EMIT | AC_SENDMSG_GS | (stream << 8),
3988 si_get_gs_wave_id(ctx));
3989 if (!use_kill)
3990 lp_build_endif(&if_state);
3991 }
3992
3993 /* Cut one primitive from the geometry shader */
3994 static void si_llvm_emit_primitive(
3995 const struct lp_build_tgsi_action *action,
3996 struct lp_build_tgsi_context *bld_base,
3997 struct lp_build_emit_data *emit_data)
3998 {
3999 struct si_shader_context *ctx = si_shader_context(bld_base);
4000 unsigned stream;
4001
4002 /* Signal primitive cut */
4003 stream = si_llvm_get_stream(bld_base, emit_data);
4004 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_CUT | AC_SENDMSG_GS | (stream << 8),
4005 si_get_gs_wave_id(ctx));
4006 }
4007
4008 static void si_llvm_emit_barrier(const struct lp_build_tgsi_action *action,
4009 struct lp_build_tgsi_context *bld_base,
4010 struct lp_build_emit_data *emit_data)
4011 {
4012 struct si_shader_context *ctx = si_shader_context(bld_base);
4013 struct gallivm_state *gallivm = &ctx->gallivm;
4014
4015 /* SI only (thanks to a hw bug workaround):
4016 * The real barrier instruction isn’t needed, because an entire patch
4017 * always fits into a single wave.
4018 */
4019 if (ctx->screen->b.chip_class == SI &&
4020 ctx->type == PIPE_SHADER_TESS_CTRL) {
4021 si_emit_waitcnt(ctx, LGKM_CNT & VM_CNT);
4022 return;
4023 }
4024
4025 lp_build_intrinsic(gallivm->builder,
4026 "llvm.amdgcn.s.barrier",
4027 ctx->voidt, NULL, 0, LP_FUNC_ATTR_CONVERGENT);
4028 }
4029
4030 static const struct lp_build_tgsi_action interp_action = {
4031 .fetch_args = interp_fetch_args,
4032 .emit = build_interp_intrinsic,
4033 };
4034
4035 static void si_create_function(struct si_shader_context *ctx,
4036 const char *name,
4037 LLVMTypeRef *returns, unsigned num_returns,
4038 struct si_function_info *fninfo,
4039 unsigned max_workgroup_size)
4040 {
4041 int i;
4042
4043 si_llvm_create_func(ctx, name, returns, num_returns,
4044 fninfo->types, fninfo->num_params);
4045 ctx->return_value = LLVMGetUndef(ctx->return_type);
4046
4047 for (i = 0; i < fninfo->num_sgpr_params; ++i) {
4048 LLVMValueRef P = LLVMGetParam(ctx->main_fn, i);
4049
4050 /* The combination of:
4051 * - ByVal
4052 * - dereferenceable
4053 * - invariant.load
4054 * allows the optimization passes to move loads and reduces
4055 * SGPR spilling significantly.
4056 */
4057 if (LLVMGetTypeKind(LLVMTypeOf(P)) == LLVMPointerTypeKind) {
4058 lp_add_function_attr(ctx->main_fn, i + 1, LP_FUNC_ATTR_BYVAL);
4059 lp_add_function_attr(ctx->main_fn, i + 1, LP_FUNC_ATTR_NOALIAS);
4060 ac_add_attr_dereferenceable(P, UINT64_MAX);
4061 } else
4062 lp_add_function_attr(ctx->main_fn, i + 1, LP_FUNC_ATTR_INREG);
4063 }
4064
4065 for (i = 0; i < fninfo->num_params; ++i) {
4066 if (fninfo->assign[i])
4067 *fninfo->assign[i] = LLVMGetParam(ctx->main_fn, i);
4068 }
4069
4070 if (max_workgroup_size) {
4071 si_llvm_add_attribute(ctx->main_fn, "amdgpu-max-work-group-size",
4072 max_workgroup_size);
4073 }
4074 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
4075 "no-signed-zeros-fp-math",
4076 "true");
4077
4078 if (ctx->screen->b.debug_flags & DBG_UNSAFE_MATH) {
4079 /* These were copied from some LLVM test. */
4080 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
4081 "less-precise-fpmad",
4082 "true");
4083 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
4084 "no-infs-fp-math",
4085 "true");
4086 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
4087 "no-nans-fp-math",
4088 "true");
4089 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
4090 "unsafe-fp-math",
4091 "true");
4092 }
4093 }
4094
4095 static void declare_streamout_params(struct si_shader_context *ctx,
4096 struct pipe_stream_output_info *so,
4097 struct si_function_info *fninfo)
4098 {
4099 int i;
4100
4101 /* Streamout SGPRs. */
4102 if (so->num_outputs) {
4103 if (ctx->type != PIPE_SHADER_TESS_EVAL)
4104 ctx->param_streamout_config = add_arg(fninfo, ARG_SGPR, ctx->ac.i32);
4105 else
4106 ctx->param_streamout_config = fninfo->num_params - 1;
4107
4108 ctx->param_streamout_write_index = add_arg(fninfo, ARG_SGPR, ctx->ac.i32);
4109 }
4110 /* A streamout buffer offset is loaded if the stride is non-zero. */
4111 for (i = 0; i < 4; i++) {
4112 if (!so->stride[i])
4113 continue;
4114
4115 ctx->param_streamout_offset[i] = add_arg(fninfo, ARG_SGPR, ctx->ac.i32);
4116 }
4117 }
4118
4119 static unsigned llvm_get_type_size(LLVMTypeRef type)
4120 {
4121 LLVMTypeKind kind = LLVMGetTypeKind(type);
4122
4123 switch (kind) {
4124 case LLVMIntegerTypeKind:
4125 return LLVMGetIntTypeWidth(type) / 8;
4126 case LLVMFloatTypeKind:
4127 return 4;
4128 case LLVMPointerTypeKind:
4129 return 8;
4130 case LLVMVectorTypeKind:
4131 return LLVMGetVectorSize(type) *
4132 llvm_get_type_size(LLVMGetElementType(type));
4133 case LLVMArrayTypeKind:
4134 return LLVMGetArrayLength(type) *
4135 llvm_get_type_size(LLVMGetElementType(type));
4136 default:
4137 assert(0);
4138 return 0;
4139 }
4140 }
4141
4142 static void declare_lds_as_pointer(struct si_shader_context *ctx)
4143 {
4144 struct gallivm_state *gallivm = &ctx->gallivm;
4145
4146 unsigned lds_size = ctx->screen->b.chip_class >= CIK ? 65536 : 32768;
4147 ctx->lds = LLVMBuildIntToPtr(gallivm->builder, ctx->i32_0,
4148 LLVMPointerType(LLVMArrayType(ctx->i32, lds_size / 4), LOCAL_ADDR_SPACE),
4149 "lds");
4150 }
4151
4152 static unsigned si_get_max_workgroup_size(const struct si_shader *shader)
4153 {
4154 switch (shader->selector->type) {
4155 case PIPE_SHADER_TESS_CTRL:
4156 /* Return this so that LLVM doesn't remove s_barrier
4157 * instructions on chips where we use s_barrier. */
4158 return shader->selector->screen->b.chip_class >= CIK ? 128 : 64;
4159
4160 case PIPE_SHADER_GEOMETRY:
4161 return shader->selector->screen->b.chip_class >= GFX9 ? 128 : 64;
4162
4163 case PIPE_SHADER_COMPUTE:
4164 break; /* see below */
4165
4166 default:
4167 return 0;
4168 }
4169
4170 const unsigned *properties = shader->selector->info.properties;
4171 unsigned max_work_group_size =
4172 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] *
4173 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT] *
4174 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH];
4175
4176 if (!max_work_group_size) {
4177 /* This is a variable group size compute shader,
4178 * compile it for the maximum possible group size.
4179 */
4180 max_work_group_size = SI_MAX_VARIABLE_THREADS_PER_BLOCK;
4181 }
4182 return max_work_group_size;
4183 }
4184
4185 static void declare_per_stage_desc_pointers(struct si_shader_context *ctx,
4186 struct si_function_info *fninfo,
4187 bool assign_params)
4188 {
4189 unsigned const_and_shader_buffers =
4190 add_arg(fninfo, ARG_SGPR,
4191 si_const_array(ctx->v4i32,
4192 SI_NUM_SHADER_BUFFERS + SI_NUM_CONST_BUFFERS));
4193 unsigned samplers_and_images =
4194 add_arg(fninfo, ARG_SGPR,
4195 si_const_array(ctx->v8i32,
4196 SI_NUM_IMAGES + SI_NUM_SAMPLERS * 2));
4197
4198 if (assign_params) {
4199 ctx->param_const_and_shader_buffers = const_and_shader_buffers;
4200 ctx->param_samplers_and_images = samplers_and_images;
4201 }
4202 }
4203
4204 static void declare_default_desc_pointers(struct si_shader_context *ctx,
4205 struct si_function_info *fninfo)
4206 {
4207 ctx->param_rw_buffers = add_arg(fninfo, ARG_SGPR,
4208 si_const_array(ctx->v4i32, SI_NUM_RW_BUFFERS));
4209 declare_per_stage_desc_pointers(ctx, fninfo, true);
4210 }
4211
4212 static void declare_vs_specific_input_sgprs(struct si_shader_context *ctx,
4213 struct si_function_info *fninfo)
4214 {
4215 ctx->param_vertex_buffers = add_arg(fninfo, ARG_SGPR,
4216 si_const_array(ctx->v4i32, SI_NUM_VERTEX_BUFFERS));
4217 add_arg_assign(fninfo, ARG_SGPR, ctx->i32, &ctx->abi.base_vertex);
4218 add_arg_assign(fninfo, ARG_SGPR, ctx->i32, &ctx->abi.start_instance);
4219 add_arg_assign(fninfo, ARG_SGPR, ctx->i32, &ctx->abi.draw_id);
4220 ctx->param_vs_state_bits = add_arg(fninfo, ARG_SGPR, ctx->i32);
4221 }
4222
4223 static void declare_vs_input_vgprs(struct si_shader_context *ctx,
4224 struct si_function_info *fninfo,
4225 unsigned *num_prolog_vgprs)
4226 {
4227 struct si_shader *shader = ctx->shader;
4228
4229 add_arg_assign(fninfo, ARG_VGPR, ctx->i32, &ctx->abi.vertex_id);
4230 if (shader->key.as_ls) {
4231 ctx->param_rel_auto_id = add_arg(fninfo, ARG_VGPR, ctx->i32);
4232 add_arg_assign(fninfo, ARG_VGPR, ctx->i32, &ctx->abi.instance_id);
4233 } else {
4234 add_arg_assign(fninfo, ARG_VGPR, ctx->i32, &ctx->abi.instance_id);
4235 ctx->param_vs_prim_id = add_arg(fninfo, ARG_VGPR, ctx->i32);
4236 }
4237 add_arg(fninfo, ARG_VGPR, ctx->i32); /* unused */
4238
4239 if (!shader->is_gs_copy_shader) {
4240 /* Vertex load indices. */
4241 ctx->param_vertex_index0 = fninfo->num_params;
4242 for (unsigned i = 0; i < shader->selector->info.num_inputs; i++)
4243 add_arg(fninfo, ARG_VGPR, ctx->i32);
4244 *num_prolog_vgprs += shader->selector->info.num_inputs;
4245 }
4246 }
4247
4248 static void declare_tes_input_vgprs(struct si_shader_context *ctx,
4249 struct si_function_info *fninfo)
4250 {
4251 ctx->param_tes_u = add_arg(fninfo, ARG_VGPR, ctx->f32);
4252 ctx->param_tes_v = add_arg(fninfo, ARG_VGPR, ctx->f32);
4253 ctx->param_tes_rel_patch_id = add_arg(fninfo, ARG_VGPR, ctx->i32);
4254 ctx->param_tes_patch_id = add_arg(fninfo, ARG_VGPR, ctx->i32);
4255 }
4256
4257 enum {
4258 /* Convenient merged shader definitions. */
4259 SI_SHADER_MERGED_VERTEX_TESSCTRL = PIPE_SHADER_TYPES,
4260 SI_SHADER_MERGED_VERTEX_OR_TESSEVAL_GEOMETRY,
4261 };
4262
4263 static void create_function(struct si_shader_context *ctx)
4264 {
4265 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
4266 struct gallivm_state *gallivm = &ctx->gallivm;
4267 struct si_shader *shader = ctx->shader;
4268 struct si_function_info fninfo;
4269 LLVMTypeRef returns[16+32*4];
4270 unsigned i, num_return_sgprs;
4271 unsigned num_returns = 0;
4272 unsigned num_prolog_vgprs = 0;
4273 unsigned type = ctx->type;
4274
4275 si_init_function_info(&fninfo);
4276
4277 /* Set MERGED shaders. */
4278 if (ctx->screen->b.chip_class >= GFX9) {
4279 if (shader->key.as_ls || type == PIPE_SHADER_TESS_CTRL)
4280 type = SI_SHADER_MERGED_VERTEX_TESSCTRL; /* LS or HS */
4281 else if (shader->key.as_es || type == PIPE_SHADER_GEOMETRY)
4282 type = SI_SHADER_MERGED_VERTEX_OR_TESSEVAL_GEOMETRY;
4283 }
4284
4285 LLVMTypeRef v3i32 = LLVMVectorType(ctx->i32, 3);
4286
4287 switch (type) {
4288 case PIPE_SHADER_VERTEX:
4289 declare_default_desc_pointers(ctx, &fninfo);
4290 declare_vs_specific_input_sgprs(ctx, &fninfo);
4291
4292 if (shader->key.as_es) {
4293 ctx->param_es2gs_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4294 } else if (shader->key.as_ls) {
4295 /* no extra parameters */
4296 } else {
4297 if (shader->is_gs_copy_shader) {
4298 fninfo.num_params = ctx->param_rw_buffers + 1;
4299 fninfo.num_sgpr_params = fninfo.num_params;
4300 }
4301
4302 /* The locations of the other parameters are assigned dynamically. */
4303 declare_streamout_params(ctx, &shader->selector->so,
4304 &fninfo);
4305 }
4306
4307 /* VGPRs */
4308 declare_vs_input_vgprs(ctx, &fninfo, &num_prolog_vgprs);
4309 break;
4310
4311 case PIPE_SHADER_TESS_CTRL: /* SI-CI-VI */
4312 declare_default_desc_pointers(ctx, &fninfo);
4313 ctx->param_tcs_offchip_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4314 ctx->param_tcs_out_lds_offsets = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4315 ctx->param_tcs_out_lds_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4316 ctx->param_vs_state_bits = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4317 ctx->param_tcs_offchip_addr_base64k = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4318 ctx->param_tcs_factor_addr_base64k = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4319 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4320 ctx->param_tcs_factor_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4321
4322 /* VGPRs */
4323 ctx->param_tcs_patch_id = add_arg(&fninfo, ARG_VGPR, ctx->i32);
4324 ctx->param_tcs_rel_ids = add_arg(&fninfo, ARG_VGPR, ctx->i32);
4325
4326 /* param_tcs_offchip_offset and param_tcs_factor_offset are
4327 * placed after the user SGPRs.
4328 */
4329 for (i = 0; i < GFX6_TCS_NUM_USER_SGPR + 2; i++)
4330 returns[num_returns++] = ctx->i32; /* SGPRs */
4331 for (i = 0; i < 5; i++)
4332 returns[num_returns++] = ctx->f32; /* VGPRs */
4333 break;
4334
4335 case SI_SHADER_MERGED_VERTEX_TESSCTRL:
4336 /* Merged stages have 8 system SGPRs at the beginning. */
4337 ctx->param_rw_buffers = /* SPI_SHADER_USER_DATA_ADDR_LO_HS */
4338 add_arg(&fninfo, ARG_SGPR, si_const_array(ctx->v4i32, SI_NUM_RW_BUFFERS));
4339 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4340 ctx->param_merged_wave_info = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4341 ctx->param_tcs_factor_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4342 ctx->param_merged_scratch_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4343 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused */
4344 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused */
4345
4346 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused */
4347 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused */
4348 declare_per_stage_desc_pointers(ctx, &fninfo,
4349 ctx->type == PIPE_SHADER_VERTEX);
4350 declare_vs_specific_input_sgprs(ctx, &fninfo);
4351
4352 ctx->param_tcs_offchip_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4353 ctx->param_tcs_out_lds_offsets = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4354 ctx->param_tcs_out_lds_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4355 ctx->param_tcs_offchip_addr_base64k = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4356 ctx->param_tcs_factor_addr_base64k = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4357 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused */
4358
4359 declare_per_stage_desc_pointers(ctx, &fninfo,
4360 ctx->type == PIPE_SHADER_TESS_CTRL);
4361
4362 /* VGPRs (first TCS, then VS) */
4363 ctx->param_tcs_patch_id = add_arg(&fninfo, ARG_VGPR, ctx->i32);
4364 ctx->param_tcs_rel_ids = add_arg(&fninfo, ARG_VGPR, ctx->i32);
4365
4366 if (ctx->type == PIPE_SHADER_VERTEX) {
4367 declare_vs_input_vgprs(ctx, &fninfo,
4368 &num_prolog_vgprs);
4369
4370 /* LS return values are inputs to the TCS main shader part. */
4371 for (i = 0; i < 8 + GFX9_TCS_NUM_USER_SGPR; i++)
4372 returns[num_returns++] = ctx->i32; /* SGPRs */
4373 for (i = 0; i < 2; i++)
4374 returns[num_returns++] = ctx->f32; /* VGPRs */
4375 } else {
4376 /* TCS return values are inputs to the TCS epilog.
4377 *
4378 * param_tcs_offchip_offset, param_tcs_factor_offset,
4379 * param_tcs_offchip_layout, and param_rw_buffers
4380 * should be passed to the epilog.
4381 */
4382 for (i = 0; i <= 8 + GFX9_SGPR_TCS_FACTOR_ADDR_BASE64K; i++)
4383 returns[num_returns++] = ctx->i32; /* SGPRs */
4384 for (i = 0; i < 5; i++)
4385 returns[num_returns++] = ctx->f32; /* VGPRs */
4386 }
4387 break;
4388
4389 case SI_SHADER_MERGED_VERTEX_OR_TESSEVAL_GEOMETRY:
4390 /* Merged stages have 8 system SGPRs at the beginning. */
4391 ctx->param_rw_buffers = /* SPI_SHADER_USER_DATA_ADDR_LO_GS */
4392 add_arg(&fninfo, ARG_SGPR, si_const_array(ctx->v4i32, SI_NUM_RW_BUFFERS));
4393 ctx->param_gs2vs_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4394 ctx->param_merged_wave_info = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4395 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4396 ctx->param_merged_scratch_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4397 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused (SPI_SHADER_PGM_LO/HI_GS << 8) */
4398 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused (SPI_SHADER_PGM_LO/HI_GS >> 24) */
4399
4400 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused */
4401 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused */
4402 declare_per_stage_desc_pointers(ctx, &fninfo,
4403 (ctx->type == PIPE_SHADER_VERTEX ||
4404 ctx->type == PIPE_SHADER_TESS_EVAL));
4405 if (ctx->type == PIPE_SHADER_VERTEX) {
4406 declare_vs_specific_input_sgprs(ctx, &fninfo);
4407 } else {
4408 /* TESS_EVAL (and also GEOMETRY):
4409 * Declare as many input SGPRs as the VS has. */
4410 ctx->param_tcs_offchip_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4411 ctx->param_tcs_offchip_addr_base64k = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4412 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused */
4413 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused */
4414 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused */
4415 ctx->param_vs_state_bits = add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused */
4416 }
4417
4418 declare_per_stage_desc_pointers(ctx, &fninfo,
4419 ctx->type == PIPE_SHADER_GEOMETRY);
4420
4421 /* VGPRs (first GS, then VS/TES) */
4422 ctx->param_gs_vtx01_offset = add_arg(&fninfo, ARG_VGPR, ctx->i32);
4423 ctx->param_gs_vtx23_offset = add_arg(&fninfo, ARG_VGPR, ctx->i32);
4424 ctx->param_gs_prim_id = add_arg(&fninfo, ARG_VGPR, ctx->i32);
4425 ctx->param_gs_instance_id = add_arg(&fninfo, ARG_VGPR, ctx->i32);
4426 ctx->param_gs_vtx45_offset = add_arg(&fninfo, ARG_VGPR, ctx->i32);
4427
4428 if (ctx->type == PIPE_SHADER_VERTEX) {
4429 declare_vs_input_vgprs(ctx, &fninfo,
4430 &num_prolog_vgprs);
4431 } else if (ctx->type == PIPE_SHADER_TESS_EVAL) {
4432 declare_tes_input_vgprs(ctx, &fninfo);
4433 }
4434
4435 if (ctx->type == PIPE_SHADER_VERTEX ||
4436 ctx->type == PIPE_SHADER_TESS_EVAL) {
4437 /* ES return values are inputs to GS. */
4438 for (i = 0; i < 8 + GFX9_GS_NUM_USER_SGPR; i++)
4439 returns[num_returns++] = ctx->i32; /* SGPRs */
4440 for (i = 0; i < 5; i++)
4441 returns[num_returns++] = ctx->f32; /* VGPRs */
4442 }
4443 break;
4444
4445 case PIPE_SHADER_TESS_EVAL:
4446 declare_default_desc_pointers(ctx, &fninfo);
4447 ctx->param_tcs_offchip_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4448 ctx->param_tcs_offchip_addr_base64k = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4449
4450 if (shader->key.as_es) {
4451 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4452 add_arg(&fninfo, ARG_SGPR, ctx->i32);
4453 ctx->param_es2gs_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4454 } else {
4455 add_arg(&fninfo, ARG_SGPR, ctx->i32);
4456 declare_streamout_params(ctx, &shader->selector->so,
4457 &fninfo);
4458 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4459 }
4460
4461 /* VGPRs */
4462 declare_tes_input_vgprs(ctx, &fninfo);
4463 break;
4464
4465 case PIPE_SHADER_GEOMETRY:
4466 declare_default_desc_pointers(ctx, &fninfo);
4467 ctx->param_gs2vs_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4468 ctx->param_gs_wave_id = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4469
4470 /* VGPRs */
4471 ctx->param_gs_vtx0_offset = add_arg(&fninfo, ARG_VGPR, ctx->i32);
4472 ctx->param_gs_vtx1_offset = add_arg(&fninfo, ARG_VGPR, ctx->i32);
4473 ctx->param_gs_prim_id = add_arg(&fninfo, ARG_VGPR, ctx->i32);
4474 ctx->param_gs_vtx2_offset = add_arg(&fninfo, ARG_VGPR, ctx->i32);
4475 ctx->param_gs_vtx3_offset = add_arg(&fninfo, ARG_VGPR, ctx->i32);
4476 ctx->param_gs_vtx4_offset = add_arg(&fninfo, ARG_VGPR, ctx->i32);
4477 ctx->param_gs_vtx5_offset = add_arg(&fninfo, ARG_VGPR, ctx->i32);
4478 ctx->param_gs_instance_id = add_arg(&fninfo, ARG_VGPR, ctx->i32);
4479 break;
4480
4481 case PIPE_SHADER_FRAGMENT:
4482 declare_default_desc_pointers(ctx, &fninfo);
4483 add_arg_checked(&fninfo, ARG_SGPR, ctx->f32, SI_PARAM_ALPHA_REF);
4484 add_arg_checked(&fninfo, ARG_SGPR, ctx->i32, SI_PARAM_PRIM_MASK);
4485
4486 add_arg_checked(&fninfo, ARG_VGPR, ctx->v2i32, SI_PARAM_PERSP_SAMPLE);
4487 add_arg_checked(&fninfo, ARG_VGPR, ctx->v2i32, SI_PARAM_PERSP_CENTER);
4488 add_arg_checked(&fninfo, ARG_VGPR, ctx->v2i32, SI_PARAM_PERSP_CENTROID);
4489 add_arg_checked(&fninfo, ARG_VGPR, v3i32, SI_PARAM_PERSP_PULL_MODEL);
4490 add_arg_checked(&fninfo, ARG_VGPR, ctx->v2i32, SI_PARAM_LINEAR_SAMPLE);
4491 add_arg_checked(&fninfo, ARG_VGPR, ctx->v2i32, SI_PARAM_LINEAR_CENTER);
4492 add_arg_checked(&fninfo, ARG_VGPR, ctx->v2i32, SI_PARAM_LINEAR_CENTROID);
4493 add_arg_checked(&fninfo, ARG_VGPR, ctx->f32, SI_PARAM_LINE_STIPPLE_TEX);
4494 add_arg_checked(&fninfo, ARG_VGPR, ctx->f32, SI_PARAM_POS_X_FLOAT);
4495 add_arg_checked(&fninfo, ARG_VGPR, ctx->f32, SI_PARAM_POS_Y_FLOAT);
4496 add_arg_checked(&fninfo, ARG_VGPR, ctx->f32, SI_PARAM_POS_Z_FLOAT);
4497 add_arg_checked(&fninfo, ARG_VGPR, ctx->f32, SI_PARAM_POS_W_FLOAT);
4498 add_arg_checked(&fninfo, ARG_VGPR, ctx->i32, SI_PARAM_FRONT_FACE);
4499 shader->info.face_vgpr_index = 20;
4500 add_arg_checked(&fninfo, ARG_VGPR, ctx->i32, SI_PARAM_ANCILLARY);
4501 add_arg_checked(&fninfo, ARG_VGPR, ctx->f32, SI_PARAM_SAMPLE_COVERAGE);
4502 add_arg_checked(&fninfo, ARG_VGPR, ctx->i32, SI_PARAM_POS_FIXED_PT);
4503
4504 /* Color inputs from the prolog. */
4505 if (shader->selector->info.colors_read) {
4506 unsigned num_color_elements =
4507 util_bitcount(shader->selector->info.colors_read);
4508
4509 assert(fninfo.num_params + num_color_elements <= ARRAY_SIZE(fninfo.types));
4510 for (i = 0; i < num_color_elements; i++)
4511 add_arg(&fninfo, ARG_VGPR, ctx->f32);
4512
4513 num_prolog_vgprs += num_color_elements;
4514 }
4515
4516 /* Outputs for the epilog. */
4517 num_return_sgprs = SI_SGPR_ALPHA_REF + 1;
4518 num_returns =
4519 num_return_sgprs +
4520 util_bitcount(shader->selector->info.colors_written) * 4 +
4521 shader->selector->info.writes_z +
4522 shader->selector->info.writes_stencil +
4523 shader->selector->info.writes_samplemask +
4524 1 /* SampleMaskIn */;
4525
4526 num_returns = MAX2(num_returns,
4527 num_return_sgprs +
4528 PS_EPILOG_SAMPLEMASK_MIN_LOC + 1);
4529
4530 for (i = 0; i < num_return_sgprs; i++)
4531 returns[i] = ctx->i32;
4532 for (; i < num_returns; i++)
4533 returns[i] = ctx->f32;
4534 break;
4535
4536 case PIPE_SHADER_COMPUTE:
4537 declare_default_desc_pointers(ctx, &fninfo);
4538 if (shader->selector->info.uses_grid_size)
4539 ctx->param_grid_size = add_arg(&fninfo, ARG_SGPR, v3i32);
4540 if (shader->selector->info.uses_block_size)
4541 ctx->param_block_size = add_arg(&fninfo, ARG_SGPR, v3i32);
4542
4543 for (i = 0; i < 3; i++) {
4544 ctx->param_block_id[i] = -1;
4545 if (shader->selector->info.uses_block_id[i])
4546 ctx->param_block_id[i] = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4547 }
4548
4549 ctx->param_thread_id = add_arg(&fninfo, ARG_VGPR, v3i32);
4550 break;
4551 default:
4552 assert(0 && "unimplemented shader");
4553 return;
4554 }
4555
4556 si_create_function(ctx, "main", returns, num_returns, &fninfo,
4557 si_get_max_workgroup_size(shader));
4558
4559 /* Reserve register locations for VGPR inputs the PS prolog may need. */
4560 if (ctx->type == PIPE_SHADER_FRAGMENT &&
4561 ctx->separate_prolog) {
4562 si_llvm_add_attribute(ctx->main_fn,
4563 "InitialPSInputAddr",
4564 S_0286D0_PERSP_SAMPLE_ENA(1) |
4565 S_0286D0_PERSP_CENTER_ENA(1) |
4566 S_0286D0_PERSP_CENTROID_ENA(1) |
4567 S_0286D0_LINEAR_SAMPLE_ENA(1) |
4568 S_0286D0_LINEAR_CENTER_ENA(1) |
4569 S_0286D0_LINEAR_CENTROID_ENA(1) |
4570 S_0286D0_FRONT_FACE_ENA(1) |
4571 S_0286D0_POS_FIXED_PT_ENA(1));
4572 }
4573
4574 shader->info.num_input_sgprs = 0;
4575 shader->info.num_input_vgprs = 0;
4576
4577 for (i = 0; i < fninfo.num_sgpr_params; ++i)
4578 shader->info.num_input_sgprs += llvm_get_type_size(fninfo.types[i]) / 4;
4579
4580 for (; i < fninfo.num_params; ++i)
4581 shader->info.num_input_vgprs += llvm_get_type_size(fninfo.types[i]) / 4;
4582
4583 assert(shader->info.num_input_vgprs >= num_prolog_vgprs);
4584 shader->info.num_input_vgprs -= num_prolog_vgprs;
4585
4586 if (!ctx->screen->has_ds_bpermute &&
4587 bld_base->info &&
4588 (bld_base->info->opcode_count[TGSI_OPCODE_DDX] > 0 ||
4589 bld_base->info->opcode_count[TGSI_OPCODE_DDY] > 0 ||
4590 bld_base->info->opcode_count[TGSI_OPCODE_DDX_FINE] > 0 ||
4591 bld_base->info->opcode_count[TGSI_OPCODE_DDY_FINE] > 0 ||
4592 bld_base->info->opcode_count[TGSI_OPCODE_INTERP_OFFSET] > 0 ||
4593 bld_base->info->opcode_count[TGSI_OPCODE_INTERP_SAMPLE] > 0))
4594 ctx->lds =
4595 LLVMAddGlobalInAddressSpace(gallivm->module,
4596 LLVMArrayType(ctx->i32, 64),
4597 "ddxy_lds",
4598 LOCAL_ADDR_SPACE);
4599
4600 if (shader->key.as_ls ||
4601 ctx->type == PIPE_SHADER_TESS_CTRL ||
4602 /* GFX9 has the ESGS ring buffer in LDS. */
4603 (ctx->screen->b.chip_class >= GFX9 &&
4604 (shader->key.as_es ||
4605 ctx->type == PIPE_SHADER_GEOMETRY)))
4606 declare_lds_as_pointer(ctx);
4607 }
4608
4609 /**
4610 * Load ESGS and GSVS ring buffer resource descriptors and save the variables
4611 * for later use.
4612 */
4613 static void preload_ring_buffers(struct si_shader_context *ctx)
4614 {
4615 struct gallivm_state *gallivm = &ctx->gallivm;
4616 LLVMBuilderRef builder = gallivm->builder;
4617
4618 LLVMValueRef buf_ptr = LLVMGetParam(ctx->main_fn,
4619 ctx->param_rw_buffers);
4620
4621 if (ctx->screen->b.chip_class <= VI &&
4622 (ctx->shader->key.as_es || ctx->type == PIPE_SHADER_GEOMETRY)) {
4623 unsigned ring =
4624 ctx->type == PIPE_SHADER_GEOMETRY ? SI_GS_RING_ESGS
4625 : SI_ES_RING_ESGS;
4626 LLVMValueRef offset = LLVMConstInt(ctx->i32, ring, 0);
4627
4628 ctx->esgs_ring =
4629 ac_build_indexed_load_const(&ctx->ac, buf_ptr, offset);
4630 }
4631
4632 if (ctx->shader->is_gs_copy_shader) {
4633 LLVMValueRef offset = LLVMConstInt(ctx->i32, SI_RING_GSVS, 0);
4634
4635 ctx->gsvs_ring[0] =
4636 ac_build_indexed_load_const(&ctx->ac, buf_ptr, offset);
4637 } else if (ctx->type == PIPE_SHADER_GEOMETRY) {
4638 const struct si_shader_selector *sel = ctx->shader->selector;
4639 LLVMValueRef offset = LLVMConstInt(ctx->i32, SI_RING_GSVS, 0);
4640 LLVMValueRef base_ring;
4641
4642 base_ring = ac_build_indexed_load_const(&ctx->ac, buf_ptr, offset);
4643
4644 /* The conceptual layout of the GSVS ring is
4645 * v0c0 .. vLv0 v0c1 .. vLc1 ..
4646 * but the real memory layout is swizzled across
4647 * threads:
4648 * t0v0c0 .. t15v0c0 t0v1c0 .. t15v1c0 ... t15vLcL
4649 * t16v0c0 ..
4650 * Override the buffer descriptor accordingly.
4651 */
4652 LLVMTypeRef v2i64 = LLVMVectorType(ctx->i64, 2);
4653 uint64_t stream_offset = 0;
4654
4655 for (unsigned stream = 0; stream < 4; ++stream) {
4656 unsigned num_components;
4657 unsigned stride;
4658 unsigned num_records;
4659 LLVMValueRef ring, tmp;
4660
4661 num_components = sel->info.num_stream_output_components[stream];
4662 if (!num_components)
4663 continue;
4664
4665 stride = 4 * num_components * sel->gs_max_out_vertices;
4666
4667 /* Limit on the stride field for <= CIK. */
4668 assert(stride < (1 << 14));
4669
4670 num_records = 64;
4671
4672 ring = LLVMBuildBitCast(builder, base_ring, v2i64, "");
4673 tmp = LLVMBuildExtractElement(builder, ring, ctx->i32_0, "");
4674 tmp = LLVMBuildAdd(builder, tmp,
4675 LLVMConstInt(ctx->i64,
4676 stream_offset, 0), "");
4677 stream_offset += stride * 64;
4678
4679 ring = LLVMBuildInsertElement(builder, ring, tmp, ctx->i32_0, "");
4680 ring = LLVMBuildBitCast(builder, ring, ctx->v4i32, "");
4681 tmp = LLVMBuildExtractElement(builder, ring, ctx->i32_1, "");
4682 tmp = LLVMBuildOr(builder, tmp,
4683 LLVMConstInt(ctx->i32,
4684 S_008F04_STRIDE(stride) |
4685 S_008F04_SWIZZLE_ENABLE(1), 0), "");
4686 ring = LLVMBuildInsertElement(builder, ring, tmp, ctx->i32_1, "");
4687 ring = LLVMBuildInsertElement(builder, ring,
4688 LLVMConstInt(ctx->i32, num_records, 0),
4689 LLVMConstInt(ctx->i32, 2, 0), "");
4690 ring = LLVMBuildInsertElement(builder, ring,
4691 LLVMConstInt(ctx->i32,
4692 S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
4693 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
4694 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
4695 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
4696 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
4697 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
4698 S_008F0C_ELEMENT_SIZE(1) | /* element_size = 4 (bytes) */
4699 S_008F0C_INDEX_STRIDE(1) | /* index_stride = 16 (elements) */
4700 S_008F0C_ADD_TID_ENABLE(1),
4701 0),
4702 LLVMConstInt(ctx->i32, 3, 0), "");
4703
4704 ctx->gsvs_ring[stream] = ring;
4705 }
4706 }
4707 }
4708
4709 static void si_llvm_emit_polygon_stipple(struct si_shader_context *ctx,
4710 LLVMValueRef param_rw_buffers,
4711 unsigned param_pos_fixed_pt)
4712 {
4713 struct gallivm_state *gallivm = &ctx->gallivm;
4714 LLVMBuilderRef builder = gallivm->builder;
4715 LLVMValueRef slot, desc, offset, row, bit, address[2];
4716
4717 /* Use the fixed-point gl_FragCoord input.
4718 * Since the stipple pattern is 32x32 and it repeats, just get 5 bits
4719 * per coordinate to get the repeating effect.
4720 */
4721 address[0] = unpack_param(ctx, param_pos_fixed_pt, 0, 5);
4722 address[1] = unpack_param(ctx, param_pos_fixed_pt, 16, 5);
4723
4724 /* Load the buffer descriptor. */
4725 slot = LLVMConstInt(ctx->i32, SI_PS_CONST_POLY_STIPPLE, 0);
4726 desc = ac_build_indexed_load_const(&ctx->ac, param_rw_buffers, slot);
4727
4728 /* The stipple pattern is 32x32, each row has 32 bits. */
4729 offset = LLVMBuildMul(builder, address[1],
4730 LLVMConstInt(ctx->i32, 4, 0), "");
4731 row = buffer_load_const(ctx, desc, offset);
4732 row = LLVMBuildBitCast(builder, row, ctx->i32, "");
4733 bit = LLVMBuildLShr(builder, row, address[0], "");
4734 bit = LLVMBuildTrunc(builder, bit, ctx->i1, "");
4735
4736 /* The intrinsic kills the thread if arg < 0. */
4737 bit = LLVMBuildSelect(builder, bit, LLVMConstReal(ctx->f32, 0),
4738 LLVMConstReal(ctx->f32, -1), "");
4739 ac_build_kill(&ctx->ac, bit);
4740 }
4741
4742 void si_shader_binary_read_config(struct ac_shader_binary *binary,
4743 struct si_shader_config *conf,
4744 unsigned symbol_offset)
4745 {
4746 unsigned i;
4747 const unsigned char *config =
4748 ac_shader_binary_config_start(binary, symbol_offset);
4749 bool really_needs_scratch = false;
4750
4751 /* LLVM adds SGPR spills to the scratch size.
4752 * Find out if we really need the scratch buffer.
4753 */
4754 for (i = 0; i < binary->reloc_count; i++) {
4755 const struct ac_shader_reloc *reloc = &binary->relocs[i];
4756
4757 if (!strcmp(scratch_rsrc_dword0_symbol, reloc->name) ||
4758 !strcmp(scratch_rsrc_dword1_symbol, reloc->name)) {
4759 really_needs_scratch = true;
4760 break;
4761 }
4762 }
4763
4764 /* XXX: We may be able to emit some of these values directly rather than
4765 * extracting fields to be emitted later.
4766 */
4767
4768 for (i = 0; i < binary->config_size_per_symbol; i+= 8) {
4769 unsigned reg = util_le32_to_cpu(*(uint32_t*)(config + i));
4770 unsigned value = util_le32_to_cpu(*(uint32_t*)(config + i + 4));
4771 switch (reg) {
4772 case R_00B028_SPI_SHADER_PGM_RSRC1_PS:
4773 case R_00B128_SPI_SHADER_PGM_RSRC1_VS:
4774 case R_00B228_SPI_SHADER_PGM_RSRC1_GS:
4775 case R_00B428_SPI_SHADER_PGM_RSRC1_HS:
4776 case R_00B848_COMPUTE_PGM_RSRC1:
4777 conf->num_sgprs = MAX2(conf->num_sgprs, (G_00B028_SGPRS(value) + 1) * 8);
4778 conf->num_vgprs = MAX2(conf->num_vgprs, (G_00B028_VGPRS(value) + 1) * 4);
4779 conf->float_mode = G_00B028_FLOAT_MODE(value);
4780 conf->rsrc1 = value;
4781 break;
4782 case R_00B02C_SPI_SHADER_PGM_RSRC2_PS:
4783 conf->lds_size = MAX2(conf->lds_size, G_00B02C_EXTRA_LDS_SIZE(value));
4784 break;
4785 case R_00B84C_COMPUTE_PGM_RSRC2:
4786 conf->lds_size = MAX2(conf->lds_size, G_00B84C_LDS_SIZE(value));
4787 conf->rsrc2 = value;
4788 break;
4789 case R_0286CC_SPI_PS_INPUT_ENA:
4790 conf->spi_ps_input_ena = value;
4791 break;
4792 case R_0286D0_SPI_PS_INPUT_ADDR:
4793 conf->spi_ps_input_addr = value;
4794 break;
4795 case R_0286E8_SPI_TMPRING_SIZE:
4796 case R_00B860_COMPUTE_TMPRING_SIZE:
4797 /* WAVESIZE is in units of 256 dwords. */
4798 if (really_needs_scratch)
4799 conf->scratch_bytes_per_wave =
4800 G_00B860_WAVESIZE(value) * 256 * 4;
4801 break;
4802 case 0x4: /* SPILLED_SGPRS */
4803 conf->spilled_sgprs = value;
4804 break;
4805 case 0x8: /* SPILLED_VGPRS */
4806 conf->spilled_vgprs = value;
4807 break;
4808 default:
4809 {
4810 static bool printed;
4811
4812 if (!printed) {
4813 fprintf(stderr, "Warning: LLVM emitted unknown "
4814 "config register: 0x%x\n", reg);
4815 printed = true;
4816 }
4817 }
4818 break;
4819 }
4820 }
4821
4822 if (!conf->spi_ps_input_addr)
4823 conf->spi_ps_input_addr = conf->spi_ps_input_ena;
4824 }
4825
4826 void si_shader_apply_scratch_relocs(struct si_shader *shader,
4827 uint64_t scratch_va)
4828 {
4829 unsigned i;
4830 uint32_t scratch_rsrc_dword0 = scratch_va;
4831 uint32_t scratch_rsrc_dword1 =
4832 S_008F04_BASE_ADDRESS_HI(scratch_va >> 32);
4833
4834 /* Enable scratch coalescing. */
4835 scratch_rsrc_dword1 |= S_008F04_SWIZZLE_ENABLE(1);
4836
4837 for (i = 0 ; i < shader->binary.reloc_count; i++) {
4838 const struct ac_shader_reloc *reloc =
4839 &shader->binary.relocs[i];
4840 if (!strcmp(scratch_rsrc_dword0_symbol, reloc->name)) {
4841 util_memcpy_cpu_to_le32(shader->binary.code + reloc->offset,
4842 &scratch_rsrc_dword0, 4);
4843 } else if (!strcmp(scratch_rsrc_dword1_symbol, reloc->name)) {
4844 util_memcpy_cpu_to_le32(shader->binary.code + reloc->offset,
4845 &scratch_rsrc_dword1, 4);
4846 }
4847 }
4848 }
4849
4850 static unsigned si_get_shader_binary_size(const struct si_shader *shader)
4851 {
4852 unsigned size = shader->binary.code_size;
4853
4854 if (shader->prolog)
4855 size += shader->prolog->binary.code_size;
4856 if (shader->previous_stage)
4857 size += shader->previous_stage->binary.code_size;
4858 if (shader->prolog2)
4859 size += shader->prolog2->binary.code_size;
4860 if (shader->epilog)
4861 size += shader->epilog->binary.code_size;
4862 return size;
4863 }
4864
4865 int si_shader_binary_upload(struct si_screen *sscreen, struct si_shader *shader)
4866 {
4867 const struct ac_shader_binary *prolog =
4868 shader->prolog ? &shader->prolog->binary : NULL;
4869 const struct ac_shader_binary *previous_stage =
4870 shader->previous_stage ? &shader->previous_stage->binary : NULL;
4871 const struct ac_shader_binary *prolog2 =
4872 shader->prolog2 ? &shader->prolog2->binary : NULL;
4873 const struct ac_shader_binary *epilog =
4874 shader->epilog ? &shader->epilog->binary : NULL;
4875 const struct ac_shader_binary *mainb = &shader->binary;
4876 unsigned bo_size = si_get_shader_binary_size(shader) +
4877 (!epilog ? mainb->rodata_size : 0);
4878 unsigned char *ptr;
4879
4880 assert(!prolog || !prolog->rodata_size);
4881 assert(!previous_stage || !previous_stage->rodata_size);
4882 assert(!prolog2 || !prolog2->rodata_size);
4883 assert((!prolog && !previous_stage && !prolog2 && !epilog) ||
4884 !mainb->rodata_size);
4885 assert(!epilog || !epilog->rodata_size);
4886
4887 r600_resource_reference(&shader->bo, NULL);
4888 shader->bo = (struct r600_resource*)
4889 pipe_buffer_create(&sscreen->b.b, 0,
4890 PIPE_USAGE_IMMUTABLE,
4891 align(bo_size, SI_CPDMA_ALIGNMENT));
4892 if (!shader->bo)
4893 return -ENOMEM;
4894
4895 /* Upload. */
4896 ptr = sscreen->b.ws->buffer_map(shader->bo->buf, NULL,
4897 PIPE_TRANSFER_READ_WRITE |
4898 PIPE_TRANSFER_UNSYNCHRONIZED);
4899
4900 /* Don't use util_memcpy_cpu_to_le32. LLVM binaries are
4901 * endian-independent. */
4902 if (prolog) {
4903 memcpy(ptr, prolog->code, prolog->code_size);
4904 ptr += prolog->code_size;
4905 }
4906 if (previous_stage) {
4907 memcpy(ptr, previous_stage->code, previous_stage->code_size);
4908 ptr += previous_stage->code_size;
4909 }
4910 if (prolog2) {
4911 memcpy(ptr, prolog2->code, prolog2->code_size);
4912 ptr += prolog2->code_size;
4913 }
4914
4915 memcpy(ptr, mainb->code, mainb->code_size);
4916 ptr += mainb->code_size;
4917
4918 if (epilog)
4919 memcpy(ptr, epilog->code, epilog->code_size);
4920 else if (mainb->rodata_size > 0)
4921 memcpy(ptr, mainb->rodata, mainb->rodata_size);
4922
4923 sscreen->b.ws->buffer_unmap(shader->bo->buf);
4924 return 0;
4925 }
4926
4927 static void si_shader_dump_disassembly(const struct ac_shader_binary *binary,
4928 struct pipe_debug_callback *debug,
4929 const char *name, FILE *file)
4930 {
4931 char *line, *p;
4932 unsigned i, count;
4933
4934 if (binary->disasm_string) {
4935 fprintf(file, "Shader %s disassembly:\n", name);
4936 fprintf(file, "%s", binary->disasm_string);
4937
4938 if (debug && debug->debug_message) {
4939 /* Very long debug messages are cut off, so send the
4940 * disassembly one line at a time. This causes more
4941 * overhead, but on the plus side it simplifies
4942 * parsing of resulting logs.
4943 */
4944 pipe_debug_message(debug, SHADER_INFO,
4945 "Shader Disassembly Begin");
4946
4947 line = binary->disasm_string;
4948 while (*line) {
4949 p = util_strchrnul(line, '\n');
4950 count = p - line;
4951
4952 if (count) {
4953 pipe_debug_message(debug, SHADER_INFO,
4954 "%.*s", count, line);
4955 }
4956
4957 if (!*p)
4958 break;
4959 line = p + 1;
4960 }
4961
4962 pipe_debug_message(debug, SHADER_INFO,
4963 "Shader Disassembly End");
4964 }
4965 } else {
4966 fprintf(file, "Shader %s binary:\n", name);
4967 for (i = 0; i < binary->code_size; i += 4) {
4968 fprintf(file, "@0x%x: %02x%02x%02x%02x\n", i,
4969 binary->code[i + 3], binary->code[i + 2],
4970 binary->code[i + 1], binary->code[i]);
4971 }
4972 }
4973 }
4974
4975 static void si_shader_dump_stats(struct si_screen *sscreen,
4976 const struct si_shader *shader,
4977 struct pipe_debug_callback *debug,
4978 unsigned processor,
4979 FILE *file,
4980 bool check_debug_option)
4981 {
4982 const struct si_shader_config *conf = &shader->config;
4983 unsigned num_inputs = shader->selector ? shader->selector->info.num_inputs : 0;
4984 unsigned code_size = si_get_shader_binary_size(shader);
4985 unsigned lds_increment = sscreen->b.chip_class >= CIK ? 512 : 256;
4986 unsigned lds_per_wave = 0;
4987 unsigned max_simd_waves = 10;
4988
4989 /* Compute LDS usage for PS. */
4990 switch (processor) {
4991 case PIPE_SHADER_FRAGMENT:
4992 /* The minimum usage per wave is (num_inputs * 48). The maximum
4993 * usage is (num_inputs * 48 * 16).
4994 * We can get anything in between and it varies between waves.
4995 *
4996 * The 48 bytes per input for a single primitive is equal to
4997 * 4 bytes/component * 4 components/input * 3 points.
4998 *
4999 * Other stages don't know the size at compile time or don't
5000 * allocate LDS per wave, but instead they do it per thread group.
5001 */
5002 lds_per_wave = conf->lds_size * lds_increment +
5003 align(num_inputs * 48, lds_increment);
5004 break;
5005 case PIPE_SHADER_COMPUTE:
5006 if (shader->selector) {
5007 unsigned max_workgroup_size =
5008 si_get_max_workgroup_size(shader);
5009 lds_per_wave = (conf->lds_size * lds_increment) /
5010 DIV_ROUND_UP(max_workgroup_size, 64);
5011 }
5012 break;
5013 }
5014
5015 /* Compute the per-SIMD wave counts. */
5016 if (conf->num_sgprs) {
5017 if (sscreen->b.chip_class >= VI)
5018 max_simd_waves = MIN2(max_simd_waves, 800 / conf->num_sgprs);
5019 else
5020 max_simd_waves = MIN2(max_simd_waves, 512 / conf->num_sgprs);
5021 }
5022
5023 if (conf->num_vgprs)
5024 max_simd_waves = MIN2(max_simd_waves, 256 / conf->num_vgprs);
5025
5026 /* LDS is 64KB per CU (4 SIMDs), which is 16KB per SIMD (usage above
5027 * 16KB makes some SIMDs unoccupied). */
5028 if (lds_per_wave)
5029 max_simd_waves = MIN2(max_simd_waves, 16384 / lds_per_wave);
5030
5031 if (!check_debug_option ||
5032 r600_can_dump_shader(&sscreen->b, processor)) {
5033 if (processor == PIPE_SHADER_FRAGMENT) {
5034 fprintf(file, "*** SHADER CONFIG ***\n"
5035 "SPI_PS_INPUT_ADDR = 0x%04x\n"
5036 "SPI_PS_INPUT_ENA = 0x%04x\n",
5037 conf->spi_ps_input_addr, conf->spi_ps_input_ena);
5038 }
5039
5040 fprintf(file, "*** SHADER STATS ***\n"
5041 "SGPRS: %d\n"
5042 "VGPRS: %d\n"
5043 "Spilled SGPRs: %d\n"
5044 "Spilled VGPRs: %d\n"
5045 "Private memory VGPRs: %d\n"
5046 "Code Size: %d bytes\n"
5047 "LDS: %d blocks\n"
5048 "Scratch: %d bytes per wave\n"
5049 "Max Waves: %d\n"
5050 "********************\n\n\n",
5051 conf->num_sgprs, conf->num_vgprs,
5052 conf->spilled_sgprs, conf->spilled_vgprs,
5053 conf->private_mem_vgprs, code_size,
5054 conf->lds_size, conf->scratch_bytes_per_wave,
5055 max_simd_waves);
5056 }
5057
5058 pipe_debug_message(debug, SHADER_INFO,
5059 "Shader Stats: SGPRS: %d VGPRS: %d Code Size: %d "
5060 "LDS: %d Scratch: %d Max Waves: %d Spilled SGPRs: %d "
5061 "Spilled VGPRs: %d PrivMem VGPRs: %d",
5062 conf->num_sgprs, conf->num_vgprs, code_size,
5063 conf->lds_size, conf->scratch_bytes_per_wave,
5064 max_simd_waves, conf->spilled_sgprs,
5065 conf->spilled_vgprs, conf->private_mem_vgprs);
5066 }
5067
5068 const char *si_get_shader_name(const struct si_shader *shader, unsigned processor)
5069 {
5070 switch (processor) {
5071 case PIPE_SHADER_VERTEX:
5072 if (shader->key.as_es)
5073 return "Vertex Shader as ES";
5074 else if (shader->key.as_ls)
5075 return "Vertex Shader as LS";
5076 else
5077 return "Vertex Shader as VS";
5078 case PIPE_SHADER_TESS_CTRL:
5079 return "Tessellation Control Shader";
5080 case PIPE_SHADER_TESS_EVAL:
5081 if (shader->key.as_es)
5082 return "Tessellation Evaluation Shader as ES";
5083 else
5084 return "Tessellation Evaluation Shader as VS";
5085 case PIPE_SHADER_GEOMETRY:
5086 if (shader->is_gs_copy_shader)
5087 return "GS Copy Shader as VS";
5088 else
5089 return "Geometry Shader";
5090 case PIPE_SHADER_FRAGMENT:
5091 return "Pixel Shader";
5092 case PIPE_SHADER_COMPUTE:
5093 return "Compute Shader";
5094 default:
5095 return "Unknown Shader";
5096 }
5097 }
5098
5099 void si_shader_dump(struct si_screen *sscreen, const struct si_shader *shader,
5100 struct pipe_debug_callback *debug, unsigned processor,
5101 FILE *file, bool check_debug_option)
5102 {
5103 if (!check_debug_option ||
5104 r600_can_dump_shader(&sscreen->b, processor))
5105 si_dump_shader_key(processor, shader, file);
5106
5107 if (!check_debug_option && shader->binary.llvm_ir_string) {
5108 if (shader->previous_stage &&
5109 shader->previous_stage->binary.llvm_ir_string) {
5110 fprintf(file, "\n%s - previous stage - LLVM IR:\n\n",
5111 si_get_shader_name(shader, processor));
5112 fprintf(file, "%s\n", shader->previous_stage->binary.llvm_ir_string);
5113 }
5114
5115 fprintf(file, "\n%s - main shader part - LLVM IR:\n\n",
5116 si_get_shader_name(shader, processor));
5117 fprintf(file, "%s\n", shader->binary.llvm_ir_string);
5118 }
5119
5120 if (!check_debug_option ||
5121 (r600_can_dump_shader(&sscreen->b, processor) &&
5122 !(sscreen->b.debug_flags & DBG_NO_ASM))) {
5123 fprintf(file, "\n%s:\n", si_get_shader_name(shader, processor));
5124
5125 if (shader->prolog)
5126 si_shader_dump_disassembly(&shader->prolog->binary,
5127 debug, "prolog", file);
5128 if (shader->previous_stage)
5129 si_shader_dump_disassembly(&shader->previous_stage->binary,
5130 debug, "previous stage", file);
5131 if (shader->prolog2)
5132 si_shader_dump_disassembly(&shader->prolog2->binary,
5133 debug, "prolog2", file);
5134
5135 si_shader_dump_disassembly(&shader->binary, debug, "main", file);
5136
5137 if (shader->epilog)
5138 si_shader_dump_disassembly(&shader->epilog->binary,
5139 debug, "epilog", file);
5140 fprintf(file, "\n");
5141 }
5142
5143 si_shader_dump_stats(sscreen, shader, debug, processor, file,
5144 check_debug_option);
5145 }
5146
5147 static int si_compile_llvm(struct si_screen *sscreen,
5148 struct ac_shader_binary *binary,
5149 struct si_shader_config *conf,
5150 LLVMTargetMachineRef tm,
5151 LLVMModuleRef mod,
5152 struct pipe_debug_callback *debug,
5153 unsigned processor,
5154 const char *name)
5155 {
5156 int r = 0;
5157 unsigned count = p_atomic_inc_return(&sscreen->b.num_compilations);
5158
5159 if (r600_can_dump_shader(&sscreen->b, processor)) {
5160 fprintf(stderr, "radeonsi: Compiling shader %d\n", count);
5161
5162 if (!(sscreen->b.debug_flags & (DBG_NO_IR | DBG_PREOPT_IR))) {
5163 fprintf(stderr, "%s LLVM IR:\n\n", name);
5164 ac_dump_module(mod);
5165 fprintf(stderr, "\n");
5166 }
5167 }
5168
5169 if (sscreen->record_llvm_ir) {
5170 char *ir = LLVMPrintModuleToString(mod);
5171 binary->llvm_ir_string = strdup(ir);
5172 LLVMDisposeMessage(ir);
5173 }
5174
5175 if (!si_replace_shader(count, binary)) {
5176 r = si_llvm_compile(mod, binary, tm, debug);
5177 if (r)
5178 return r;
5179 }
5180
5181 si_shader_binary_read_config(binary, conf, 0);
5182
5183 /* Enable 64-bit and 16-bit denormals, because there is no performance
5184 * cost.
5185 *
5186 * If denormals are enabled, all floating-point output modifiers are
5187 * ignored.
5188 *
5189 * Don't enable denormals for 32-bit floats, because:
5190 * - Floating-point output modifiers would be ignored by the hw.
5191 * - Some opcodes don't support denormals, such as v_mad_f32. We would
5192 * have to stop using those.
5193 * - SI & CI would be very slow.
5194 */
5195 conf->float_mode |= V_00B028_FP_64_DENORMS;
5196
5197 FREE(binary->config);
5198 FREE(binary->global_symbol_offsets);
5199 binary->config = NULL;
5200 binary->global_symbol_offsets = NULL;
5201
5202 /* Some shaders can't have rodata because their binaries can be
5203 * concatenated.
5204 */
5205 if (binary->rodata_size &&
5206 (processor == PIPE_SHADER_VERTEX ||
5207 processor == PIPE_SHADER_TESS_CTRL ||
5208 processor == PIPE_SHADER_TESS_EVAL ||
5209 processor == PIPE_SHADER_FRAGMENT)) {
5210 fprintf(stderr, "radeonsi: The shader can't have rodata.");
5211 return -EINVAL;
5212 }
5213
5214 return r;
5215 }
5216
5217 static void si_llvm_build_ret(struct si_shader_context *ctx, LLVMValueRef ret)
5218 {
5219 if (LLVMGetTypeKind(LLVMTypeOf(ret)) == LLVMVoidTypeKind)
5220 LLVMBuildRetVoid(ctx->gallivm.builder);
5221 else
5222 LLVMBuildRet(ctx->gallivm.builder, ret);
5223 }
5224
5225 /* Generate code for the hardware VS shader stage to go with a geometry shader */
5226 struct si_shader *
5227 si_generate_gs_copy_shader(struct si_screen *sscreen,
5228 LLVMTargetMachineRef tm,
5229 struct si_shader_selector *gs_selector,
5230 struct pipe_debug_callback *debug)
5231 {
5232 struct si_shader_context ctx;
5233 struct si_shader *shader;
5234 struct gallivm_state *gallivm = &ctx.gallivm;
5235 LLVMBuilderRef builder;
5236 struct lp_build_tgsi_context *bld_base = &ctx.bld_base;
5237 struct lp_build_context *uint = &bld_base->uint_bld;
5238 struct si_shader_output_values *outputs;
5239 struct tgsi_shader_info *gsinfo = &gs_selector->info;
5240 int i, r;
5241
5242 outputs = MALLOC(gsinfo->num_outputs * sizeof(outputs[0]));
5243
5244 if (!outputs)
5245 return NULL;
5246
5247 shader = CALLOC_STRUCT(si_shader);
5248 if (!shader) {
5249 FREE(outputs);
5250 return NULL;
5251 }
5252
5253
5254 shader->selector = gs_selector;
5255 shader->is_gs_copy_shader = true;
5256
5257 si_init_shader_ctx(&ctx, sscreen, tm);
5258 ctx.shader = shader;
5259 ctx.type = PIPE_SHADER_VERTEX;
5260
5261 builder = gallivm->builder;
5262
5263 create_function(&ctx);
5264 preload_ring_buffers(&ctx);
5265
5266 LLVMValueRef voffset =
5267 lp_build_mul_imm(uint, ctx.abi.vertex_id, 4);
5268
5269 /* Fetch the vertex stream ID.*/
5270 LLVMValueRef stream_id;
5271
5272 if (gs_selector->so.num_outputs)
5273 stream_id = unpack_param(&ctx, ctx.param_streamout_config, 24, 2);
5274 else
5275 stream_id = ctx.i32_0;
5276
5277 /* Fill in output information. */
5278 for (i = 0; i < gsinfo->num_outputs; ++i) {
5279 outputs[i].semantic_name = gsinfo->output_semantic_name[i];
5280 outputs[i].semantic_index = gsinfo->output_semantic_index[i];
5281
5282 for (int chan = 0; chan < 4; chan++) {
5283 outputs[i].vertex_stream[chan] =
5284 (gsinfo->output_streams[i] >> (2 * chan)) & 3;
5285 }
5286 }
5287
5288 LLVMBasicBlockRef end_bb;
5289 LLVMValueRef switch_inst;
5290
5291 end_bb = LLVMAppendBasicBlockInContext(gallivm->context, ctx.main_fn, "end");
5292 switch_inst = LLVMBuildSwitch(builder, stream_id, end_bb, 4);
5293
5294 for (int stream = 0; stream < 4; stream++) {
5295 LLVMBasicBlockRef bb;
5296 unsigned offset;
5297
5298 if (!gsinfo->num_stream_output_components[stream])
5299 continue;
5300
5301 if (stream > 0 && !gs_selector->so.num_outputs)
5302 continue;
5303
5304 bb = LLVMInsertBasicBlockInContext(gallivm->context, end_bb, "out");
5305 LLVMAddCase(switch_inst, LLVMConstInt(ctx.i32, stream, 0), bb);
5306 LLVMPositionBuilderAtEnd(builder, bb);
5307
5308 /* Fetch vertex data from GSVS ring */
5309 offset = 0;
5310 for (i = 0; i < gsinfo->num_outputs; ++i) {
5311 for (unsigned chan = 0; chan < 4; chan++) {
5312 if (!(gsinfo->output_usagemask[i] & (1 << chan)) ||
5313 outputs[i].vertex_stream[chan] != stream) {
5314 outputs[i].values[chan] = ctx.bld_base.base.undef;
5315 continue;
5316 }
5317
5318 LLVMValueRef soffset = LLVMConstInt(ctx.i32,
5319 offset * gs_selector->gs_max_out_vertices * 16 * 4, 0);
5320 offset++;
5321
5322 outputs[i].values[chan] =
5323 ac_build_buffer_load(&ctx.ac,
5324 ctx.gsvs_ring[0], 1,
5325 ctx.i32_0, voffset,
5326 soffset, 0, 1, 1,
5327 true, false);
5328 }
5329 }
5330
5331 /* Streamout and exports. */
5332 if (gs_selector->so.num_outputs) {
5333 si_llvm_emit_streamout(&ctx, outputs,
5334 gsinfo->num_outputs,
5335 stream);
5336 }
5337
5338 if (stream == 0)
5339 si_llvm_export_vs(bld_base, outputs, gsinfo->num_outputs);
5340
5341 LLVMBuildBr(builder, end_bb);
5342 }
5343
5344 LLVMPositionBuilderAtEnd(builder, end_bb);
5345
5346 LLVMBuildRetVoid(gallivm->builder);
5347
5348 ctx.type = PIPE_SHADER_GEOMETRY; /* override for shader dumping */
5349 si_llvm_optimize_module(&ctx);
5350
5351 r = si_compile_llvm(sscreen, &ctx.shader->binary,
5352 &ctx.shader->config, ctx.tm,
5353 ctx.gallivm.module,
5354 debug, PIPE_SHADER_GEOMETRY,
5355 "GS Copy Shader");
5356 if (!r) {
5357 if (r600_can_dump_shader(&sscreen->b, PIPE_SHADER_GEOMETRY))
5358 fprintf(stderr, "GS Copy Shader:\n");
5359 si_shader_dump(sscreen, ctx.shader, debug,
5360 PIPE_SHADER_GEOMETRY, stderr, true);
5361 r = si_shader_binary_upload(sscreen, ctx.shader);
5362 }
5363
5364 si_llvm_dispose(&ctx);
5365
5366 FREE(outputs);
5367
5368 if (r != 0) {
5369 FREE(shader);
5370 shader = NULL;
5371 }
5372 return shader;
5373 }
5374
5375 static void si_dump_shader_key_vs(const struct si_shader_key *key,
5376 const struct si_vs_prolog_bits *prolog,
5377 const char *prefix, FILE *f)
5378 {
5379 fprintf(f, " %s.instance_divisor_is_one = %u\n",
5380 prefix, prolog->instance_divisor_is_one);
5381 fprintf(f, " %s.instance_divisor_is_fetched = %u\n",
5382 prefix, prolog->instance_divisor_is_fetched);
5383
5384 fprintf(f, " mono.vs.fix_fetch = {");
5385 for (int i = 0; i < SI_MAX_ATTRIBS; i++)
5386 fprintf(f, !i ? "%u" : ", %u", key->mono.vs_fix_fetch[i]);
5387 fprintf(f, "}\n");
5388 }
5389
5390 static void si_dump_shader_key(unsigned processor, const struct si_shader *shader,
5391 FILE *f)
5392 {
5393 const struct si_shader_key *key = &shader->key;
5394
5395 fprintf(f, "SHADER KEY\n");
5396
5397 switch (processor) {
5398 case PIPE_SHADER_VERTEX:
5399 si_dump_shader_key_vs(key, &key->part.vs.prolog,
5400 "part.vs.prolog", f);
5401 fprintf(f, " as_es = %u\n", key->as_es);
5402 fprintf(f, " as_ls = %u\n", key->as_ls);
5403 fprintf(f, " mono.u.vs_export_prim_id = %u\n",
5404 key->mono.u.vs_export_prim_id);
5405 break;
5406
5407 case PIPE_SHADER_TESS_CTRL:
5408 if (shader->selector->screen->b.chip_class >= GFX9) {
5409 si_dump_shader_key_vs(key, &key->part.tcs.ls_prolog,
5410 "part.tcs.ls_prolog", f);
5411 }
5412 fprintf(f, " part.tcs.epilog.prim_mode = %u\n", key->part.tcs.epilog.prim_mode);
5413 fprintf(f, " mono.u.ff_tcs_inputs_to_copy = 0x%"PRIx64"\n", key->mono.u.ff_tcs_inputs_to_copy);
5414 break;
5415
5416 case PIPE_SHADER_TESS_EVAL:
5417 fprintf(f, " as_es = %u\n", key->as_es);
5418 fprintf(f, " mono.u.vs_export_prim_id = %u\n",
5419 key->mono.u.vs_export_prim_id);
5420 break;
5421
5422 case PIPE_SHADER_GEOMETRY:
5423 if (shader->is_gs_copy_shader)
5424 break;
5425
5426 if (shader->selector->screen->b.chip_class >= GFX9 &&
5427 key->part.gs.es->type == PIPE_SHADER_VERTEX) {
5428 si_dump_shader_key_vs(key, &key->part.gs.vs_prolog,
5429 "part.gs.vs_prolog", f);
5430 }
5431 fprintf(f, " part.gs.prolog.tri_strip_adj_fix = %u\n", key->part.gs.prolog.tri_strip_adj_fix);
5432 break;
5433
5434 case PIPE_SHADER_COMPUTE:
5435 break;
5436
5437 case PIPE_SHADER_FRAGMENT:
5438 fprintf(f, " part.ps.prolog.color_two_side = %u\n", key->part.ps.prolog.color_two_side);
5439 fprintf(f, " part.ps.prolog.flatshade_colors = %u\n", key->part.ps.prolog.flatshade_colors);
5440 fprintf(f, " part.ps.prolog.poly_stipple = %u\n", key->part.ps.prolog.poly_stipple);
5441 fprintf(f, " part.ps.prolog.force_persp_sample_interp = %u\n", key->part.ps.prolog.force_persp_sample_interp);
5442 fprintf(f, " part.ps.prolog.force_linear_sample_interp = %u\n", key->part.ps.prolog.force_linear_sample_interp);
5443 fprintf(f, " part.ps.prolog.force_persp_center_interp = %u\n", key->part.ps.prolog.force_persp_center_interp);
5444 fprintf(f, " part.ps.prolog.force_linear_center_interp = %u\n", key->part.ps.prolog.force_linear_center_interp);
5445 fprintf(f, " part.ps.prolog.bc_optimize_for_persp = %u\n", key->part.ps.prolog.bc_optimize_for_persp);
5446 fprintf(f, " part.ps.prolog.bc_optimize_for_linear = %u\n", key->part.ps.prolog.bc_optimize_for_linear);
5447 fprintf(f, " part.ps.epilog.spi_shader_col_format = 0x%x\n", key->part.ps.epilog.spi_shader_col_format);
5448 fprintf(f, " part.ps.epilog.color_is_int8 = 0x%X\n", key->part.ps.epilog.color_is_int8);
5449 fprintf(f, " part.ps.epilog.color_is_int10 = 0x%X\n", key->part.ps.epilog.color_is_int10);
5450 fprintf(f, " part.ps.epilog.last_cbuf = %u\n", key->part.ps.epilog.last_cbuf);
5451 fprintf(f, " part.ps.epilog.alpha_func = %u\n", key->part.ps.epilog.alpha_func);
5452 fprintf(f, " part.ps.epilog.alpha_to_one = %u\n", key->part.ps.epilog.alpha_to_one);
5453 fprintf(f, " part.ps.epilog.poly_line_smoothing = %u\n", key->part.ps.epilog.poly_line_smoothing);
5454 fprintf(f, " part.ps.epilog.clamp_color = %u\n", key->part.ps.epilog.clamp_color);
5455 break;
5456
5457 default:
5458 assert(0);
5459 }
5460
5461 if ((processor == PIPE_SHADER_GEOMETRY ||
5462 processor == PIPE_SHADER_TESS_EVAL ||
5463 processor == PIPE_SHADER_VERTEX) &&
5464 !key->as_es && !key->as_ls) {
5465 fprintf(f, " opt.kill_outputs = 0x%"PRIx64"\n", key->opt.kill_outputs);
5466 fprintf(f, " opt.clip_disable = %u\n", key->opt.clip_disable);
5467 }
5468 }
5469
5470 static void si_init_shader_ctx(struct si_shader_context *ctx,
5471 struct si_screen *sscreen,
5472 LLVMTargetMachineRef tm)
5473 {
5474 struct lp_build_tgsi_context *bld_base;
5475
5476 si_llvm_context_init(ctx, sscreen, tm);
5477
5478 bld_base = &ctx->bld_base;
5479 bld_base->emit_fetch_funcs[TGSI_FILE_CONSTANT] = fetch_constant;
5480
5481 bld_base->op_actions[TGSI_OPCODE_INTERP_CENTROID] = interp_action;
5482 bld_base->op_actions[TGSI_OPCODE_INTERP_SAMPLE] = interp_action;
5483 bld_base->op_actions[TGSI_OPCODE_INTERP_OFFSET] = interp_action;
5484
5485 bld_base->op_actions[TGSI_OPCODE_MEMBAR].emit = membar_emit;
5486
5487 bld_base->op_actions[TGSI_OPCODE_CLOCK].emit = clock_emit;
5488
5489 bld_base->op_actions[TGSI_OPCODE_DDX].emit = si_llvm_emit_ddxy;
5490 bld_base->op_actions[TGSI_OPCODE_DDY].emit = si_llvm_emit_ddxy;
5491 bld_base->op_actions[TGSI_OPCODE_DDX_FINE].emit = si_llvm_emit_ddxy;
5492 bld_base->op_actions[TGSI_OPCODE_DDY_FINE].emit = si_llvm_emit_ddxy;
5493
5494 bld_base->op_actions[TGSI_OPCODE_VOTE_ALL].emit = vote_all_emit;
5495 bld_base->op_actions[TGSI_OPCODE_VOTE_ANY].emit = vote_any_emit;
5496 bld_base->op_actions[TGSI_OPCODE_VOTE_EQ].emit = vote_eq_emit;
5497 bld_base->op_actions[TGSI_OPCODE_BALLOT].emit = ballot_emit;
5498 bld_base->op_actions[TGSI_OPCODE_READ_FIRST].intr_name = "llvm.amdgcn.readfirstlane";
5499 bld_base->op_actions[TGSI_OPCODE_READ_FIRST].emit = read_lane_emit;
5500 bld_base->op_actions[TGSI_OPCODE_READ_INVOC].intr_name = "llvm.amdgcn.readlane";
5501 bld_base->op_actions[TGSI_OPCODE_READ_INVOC].fetch_args = read_invoc_fetch_args;
5502 bld_base->op_actions[TGSI_OPCODE_READ_INVOC].emit = read_lane_emit;
5503
5504 bld_base->op_actions[TGSI_OPCODE_EMIT].emit = si_llvm_emit_vertex;
5505 bld_base->op_actions[TGSI_OPCODE_ENDPRIM].emit = si_llvm_emit_primitive;
5506 bld_base->op_actions[TGSI_OPCODE_BARRIER].emit = si_llvm_emit_barrier;
5507 }
5508
5509 static void si_optimize_vs_outputs(struct si_shader_context *ctx)
5510 {
5511 struct si_shader *shader = ctx->shader;
5512 struct tgsi_shader_info *info = &shader->selector->info;
5513
5514 if ((ctx->type != PIPE_SHADER_VERTEX &&
5515 ctx->type != PIPE_SHADER_TESS_EVAL) ||
5516 shader->key.as_ls ||
5517 shader->key.as_es)
5518 return;
5519
5520 ac_optimize_vs_outputs(&ctx->ac,
5521 ctx->main_fn,
5522 shader->info.vs_output_param_offset,
5523 info->num_outputs,
5524 &shader->info.nr_param_exports);
5525 }
5526
5527 static void si_count_scratch_private_memory(struct si_shader_context *ctx)
5528 {
5529 ctx->shader->config.private_mem_vgprs = 0;
5530
5531 /* Process all LLVM instructions. */
5532 LLVMBasicBlockRef bb = LLVMGetFirstBasicBlock(ctx->main_fn);
5533 while (bb) {
5534 LLVMValueRef next = LLVMGetFirstInstruction(bb);
5535
5536 while (next) {
5537 LLVMValueRef inst = next;
5538 next = LLVMGetNextInstruction(next);
5539
5540 if (LLVMGetInstructionOpcode(inst) != LLVMAlloca)
5541 continue;
5542
5543 LLVMTypeRef type = LLVMGetElementType(LLVMTypeOf(inst));
5544 /* No idea why LLVM aligns allocas to 4 elements. */
5545 unsigned alignment = LLVMGetAlignment(inst);
5546 unsigned dw_size = align(llvm_get_type_size(type) / 4, alignment);
5547 ctx->shader->config.private_mem_vgprs += dw_size;
5548 }
5549 bb = LLVMGetNextBasicBlock(bb);
5550 }
5551 }
5552
5553 static void si_init_exec_full_mask(struct si_shader_context *ctx)
5554 {
5555 LLVMValueRef full_mask = LLVMConstInt(ctx->i64, ~0ull, 0);
5556 lp_build_intrinsic(ctx->gallivm.builder,
5557 "llvm.amdgcn.init.exec", ctx->voidt,
5558 &full_mask, 1, LP_FUNC_ATTR_CONVERGENT);
5559 }
5560
5561 static void si_init_exec_from_input(struct si_shader_context *ctx,
5562 unsigned param, unsigned bitoffset)
5563 {
5564 LLVMValueRef args[] = {
5565 LLVMGetParam(ctx->main_fn, param),
5566 LLVMConstInt(ctx->i32, bitoffset, 0),
5567 };
5568 lp_build_intrinsic(ctx->gallivm.builder,
5569 "llvm.amdgcn.init.exec.from.input",
5570 ctx->voidt, args, 2, LP_FUNC_ATTR_CONVERGENT);
5571 }
5572
5573 static bool si_compile_tgsi_main(struct si_shader_context *ctx,
5574 bool is_monolithic)
5575 {
5576 struct si_shader *shader = ctx->shader;
5577 struct si_shader_selector *sel = shader->selector;
5578 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
5579
5580 // TODO clean all this up!
5581 switch (ctx->type) {
5582 case PIPE_SHADER_VERTEX:
5583 ctx->load_input = declare_input_vs;
5584 if (shader->key.as_ls)
5585 bld_base->emit_epilogue = si_llvm_emit_ls_epilogue;
5586 else if (shader->key.as_es)
5587 bld_base->emit_epilogue = si_llvm_emit_es_epilogue;
5588 else {
5589 ctx->abi.emit_outputs = si_llvm_emit_vs_epilogue;
5590 bld_base->emit_epilogue = si_tgsi_emit_epilogue;
5591 }
5592 break;
5593 case PIPE_SHADER_TESS_CTRL:
5594 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_tcs;
5595 bld_base->emit_fetch_funcs[TGSI_FILE_OUTPUT] = fetch_output_tcs;
5596 bld_base->emit_store = store_output_tcs;
5597 bld_base->emit_epilogue = si_llvm_emit_tcs_epilogue;
5598 break;
5599 case PIPE_SHADER_TESS_EVAL:
5600 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_tes;
5601 if (shader->key.as_es)
5602 bld_base->emit_epilogue = si_llvm_emit_es_epilogue;
5603 else {
5604 ctx->abi.emit_outputs = si_llvm_emit_vs_epilogue;
5605 bld_base->emit_epilogue = si_tgsi_emit_epilogue;
5606 }
5607 break;
5608 case PIPE_SHADER_GEOMETRY:
5609 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_gs;
5610 bld_base->emit_epilogue = si_llvm_emit_gs_epilogue;
5611 break;
5612 case PIPE_SHADER_FRAGMENT:
5613 ctx->load_input = declare_input_fs;
5614 bld_base->emit_epilogue = si_llvm_return_fs_outputs;
5615 break;
5616 case PIPE_SHADER_COMPUTE:
5617 ctx->declare_memory_region = declare_compute_memory;
5618 break;
5619 default:
5620 assert(!"Unsupported shader type");
5621 return false;
5622 }
5623
5624 ctx->abi.load_ubo = load_ubo;
5625
5626 create_function(ctx);
5627 preload_ring_buffers(ctx);
5628
5629 /* For GFX9 merged shaders:
5630 * - Set EXEC for the first shader. If the prolog is present, set
5631 * EXEC there instead.
5632 * - Add a barrier before the second shader.
5633 * - In the second shader, reset EXEC to ~0 and wrap the main part in
5634 * an if-statement. This is required for correctness in geometry
5635 * shaders, to ensure that empty GS waves do not send GS_EMIT and
5636 * GS_CUT messages.
5637 *
5638 * For monolithic merged shaders, the first shader is wrapped in an
5639 * if-block together with its prolog in si_build_wrapper_function.
5640 */
5641 if (ctx->screen->b.chip_class >= GFX9) {
5642 if (!is_monolithic &&
5643 sel->info.num_instructions > 1 && /* not empty shader */
5644 (shader->key.as_es || shader->key.as_ls) &&
5645 (ctx->type == PIPE_SHADER_TESS_EVAL ||
5646 (ctx->type == PIPE_SHADER_VERTEX &&
5647 !sel->vs_needs_prolog))) {
5648 si_init_exec_from_input(ctx,
5649 ctx->param_merged_wave_info, 0);
5650 } else if (ctx->type == PIPE_SHADER_TESS_CTRL ||
5651 ctx->type == PIPE_SHADER_GEOMETRY) {
5652 if (!is_monolithic)
5653 si_init_exec_full_mask(ctx);
5654
5655 /* The barrier must execute for all shaders in a
5656 * threadgroup.
5657 */
5658 si_llvm_emit_barrier(NULL, bld_base, NULL);
5659
5660 LLVMValueRef num_threads = unpack_param(ctx, ctx->param_merged_wave_info, 8, 8);
5661 LLVMValueRef ena =
5662 LLVMBuildICmp(ctx->ac.builder, LLVMIntULT,
5663 ac_get_thread_id(&ctx->ac), num_threads, "");
5664 lp_build_if(&ctx->merged_wrap_if_state, &ctx->gallivm, ena);
5665 }
5666 }
5667
5668 if (ctx->type == PIPE_SHADER_GEOMETRY) {
5669 int i;
5670 for (i = 0; i < 4; i++) {
5671 ctx->gs_next_vertex[i] =
5672 lp_build_alloca(&ctx->gallivm,
5673 ctx->i32, "");
5674 }
5675 }
5676
5677 if (ctx->type == PIPE_SHADER_FRAGMENT && sel->info.uses_kill &&
5678 ctx->screen->b.debug_flags & DBG_FS_CORRECT_DERIVS_AFTER_KILL) {
5679 /* This is initialized to 0.0 = not kill. */
5680 ctx->postponed_kill = lp_build_alloca(&ctx->gallivm, ctx->f32, "");
5681 }
5682
5683 if (sel->tokens) {
5684 if (!lp_build_tgsi_llvm(bld_base, sel->tokens)) {
5685 fprintf(stderr, "Failed to translate shader from TGSI to LLVM\n");
5686 return false;
5687 }
5688 } else {
5689 if (!si_nir_build_llvm(ctx, sel->nir)) {
5690 fprintf(stderr, "Failed to translate shader from NIR to LLVM\n");
5691 return false;
5692 }
5693 }
5694
5695 si_llvm_build_ret(ctx, ctx->return_value);
5696 return true;
5697 }
5698
5699 /**
5700 * Compute the VS prolog key, which contains all the information needed to
5701 * build the VS prolog function, and set shader->info bits where needed.
5702 *
5703 * \param info Shader info of the vertex shader.
5704 * \param num_input_sgprs Number of input SGPRs for the vertex shader.
5705 * \param prolog_key Key of the VS prolog
5706 * \param shader_out The vertex shader, or the next shader if merging LS+HS or ES+GS.
5707 * \param key Output shader part key.
5708 */
5709 static void si_get_vs_prolog_key(const struct tgsi_shader_info *info,
5710 unsigned num_input_sgprs,
5711 const struct si_vs_prolog_bits *prolog_key,
5712 struct si_shader *shader_out,
5713 union si_shader_part_key *key)
5714 {
5715 memset(key, 0, sizeof(*key));
5716 key->vs_prolog.states = *prolog_key;
5717 key->vs_prolog.num_input_sgprs = num_input_sgprs;
5718 key->vs_prolog.last_input = MAX2(1, info->num_inputs) - 1;
5719 key->vs_prolog.as_ls = shader_out->key.as_ls;
5720
5721 if (shader_out->selector->type == PIPE_SHADER_TESS_CTRL) {
5722 key->vs_prolog.as_ls = 1;
5723 key->vs_prolog.num_merged_next_stage_vgprs = 2;
5724 } else if (shader_out->selector->type == PIPE_SHADER_GEOMETRY) {
5725 key->vs_prolog.num_merged_next_stage_vgprs = 5;
5726 }
5727
5728 /* Enable loading the InstanceID VGPR. */
5729 uint16_t input_mask = u_bit_consecutive(0, info->num_inputs);
5730
5731 if ((key->vs_prolog.states.instance_divisor_is_one |
5732 key->vs_prolog.states.instance_divisor_is_fetched) & input_mask)
5733 shader_out->info.uses_instanceid = true;
5734 }
5735
5736 /**
5737 * Compute the PS prolog key, which contains all the information needed to
5738 * build the PS prolog function, and set related bits in shader->config.
5739 */
5740 static void si_get_ps_prolog_key(struct si_shader *shader,
5741 union si_shader_part_key *key,
5742 bool separate_prolog)
5743 {
5744 struct tgsi_shader_info *info = &shader->selector->info;
5745
5746 memset(key, 0, sizeof(*key));
5747 key->ps_prolog.states = shader->key.part.ps.prolog;
5748 key->ps_prolog.colors_read = info->colors_read;
5749 key->ps_prolog.num_input_sgprs = shader->info.num_input_sgprs;
5750 key->ps_prolog.num_input_vgprs = shader->info.num_input_vgprs;
5751 key->ps_prolog.wqm = info->uses_derivatives &&
5752 (key->ps_prolog.colors_read ||
5753 key->ps_prolog.states.force_persp_sample_interp ||
5754 key->ps_prolog.states.force_linear_sample_interp ||
5755 key->ps_prolog.states.force_persp_center_interp ||
5756 key->ps_prolog.states.force_linear_center_interp ||
5757 key->ps_prolog.states.bc_optimize_for_persp ||
5758 key->ps_prolog.states.bc_optimize_for_linear);
5759
5760 if (info->colors_read) {
5761 unsigned *color = shader->selector->color_attr_index;
5762
5763 if (shader->key.part.ps.prolog.color_two_side) {
5764 /* BCOLORs are stored after the last input. */
5765 key->ps_prolog.num_interp_inputs = info->num_inputs;
5766 key->ps_prolog.face_vgpr_index = shader->info.face_vgpr_index;
5767 shader->config.spi_ps_input_ena |= S_0286CC_FRONT_FACE_ENA(1);
5768 }
5769
5770 for (unsigned i = 0; i < 2; i++) {
5771 unsigned interp = info->input_interpolate[color[i]];
5772 unsigned location = info->input_interpolate_loc[color[i]];
5773
5774 if (!(info->colors_read & (0xf << i*4)))
5775 continue;
5776
5777 key->ps_prolog.color_attr_index[i] = color[i];
5778
5779 if (shader->key.part.ps.prolog.flatshade_colors &&
5780 interp == TGSI_INTERPOLATE_COLOR)
5781 interp = TGSI_INTERPOLATE_CONSTANT;
5782
5783 switch (interp) {
5784 case TGSI_INTERPOLATE_CONSTANT:
5785 key->ps_prolog.color_interp_vgpr_index[i] = -1;
5786 break;
5787 case TGSI_INTERPOLATE_PERSPECTIVE:
5788 case TGSI_INTERPOLATE_COLOR:
5789 /* Force the interpolation location for colors here. */
5790 if (shader->key.part.ps.prolog.force_persp_sample_interp)
5791 location = TGSI_INTERPOLATE_LOC_SAMPLE;
5792 if (shader->key.part.ps.prolog.force_persp_center_interp)
5793 location = TGSI_INTERPOLATE_LOC_CENTER;
5794
5795 switch (location) {
5796 case TGSI_INTERPOLATE_LOC_SAMPLE:
5797 key->ps_prolog.color_interp_vgpr_index[i] = 0;
5798 shader->config.spi_ps_input_ena |=
5799 S_0286CC_PERSP_SAMPLE_ENA(1);
5800 break;
5801 case TGSI_INTERPOLATE_LOC_CENTER:
5802 key->ps_prolog.color_interp_vgpr_index[i] = 2;
5803 shader->config.spi_ps_input_ena |=
5804 S_0286CC_PERSP_CENTER_ENA(1);
5805 break;
5806 case TGSI_INTERPOLATE_LOC_CENTROID:
5807 key->ps_prolog.color_interp_vgpr_index[i] = 4;
5808 shader->config.spi_ps_input_ena |=
5809 S_0286CC_PERSP_CENTROID_ENA(1);
5810 break;
5811 default:
5812 assert(0);
5813 }
5814 break;
5815 case TGSI_INTERPOLATE_LINEAR:
5816 /* Force the interpolation location for colors here. */
5817 if (shader->key.part.ps.prolog.force_linear_sample_interp)
5818 location = TGSI_INTERPOLATE_LOC_SAMPLE;
5819 if (shader->key.part.ps.prolog.force_linear_center_interp)
5820 location = TGSI_INTERPOLATE_LOC_CENTER;
5821
5822 /* The VGPR assignment for non-monolithic shaders
5823 * works because InitialPSInputAddr is set on the
5824 * main shader and PERSP_PULL_MODEL is never used.
5825 */
5826 switch (location) {
5827 case TGSI_INTERPOLATE_LOC_SAMPLE:
5828 key->ps_prolog.color_interp_vgpr_index[i] =
5829 separate_prolog ? 6 : 9;
5830 shader->config.spi_ps_input_ena |=
5831 S_0286CC_LINEAR_SAMPLE_ENA(1);
5832 break;
5833 case TGSI_INTERPOLATE_LOC_CENTER:
5834 key->ps_prolog.color_interp_vgpr_index[i] =
5835 separate_prolog ? 8 : 11;
5836 shader->config.spi_ps_input_ena |=
5837 S_0286CC_LINEAR_CENTER_ENA(1);
5838 break;
5839 case TGSI_INTERPOLATE_LOC_CENTROID:
5840 key->ps_prolog.color_interp_vgpr_index[i] =
5841 separate_prolog ? 10 : 13;
5842 shader->config.spi_ps_input_ena |=
5843 S_0286CC_LINEAR_CENTROID_ENA(1);
5844 break;
5845 default:
5846 assert(0);
5847 }
5848 break;
5849 default:
5850 assert(0);
5851 }
5852 }
5853 }
5854 }
5855
5856 /**
5857 * Check whether a PS prolog is required based on the key.
5858 */
5859 static bool si_need_ps_prolog(const union si_shader_part_key *key)
5860 {
5861 return key->ps_prolog.colors_read ||
5862 key->ps_prolog.states.force_persp_sample_interp ||
5863 key->ps_prolog.states.force_linear_sample_interp ||
5864 key->ps_prolog.states.force_persp_center_interp ||
5865 key->ps_prolog.states.force_linear_center_interp ||
5866 key->ps_prolog.states.bc_optimize_for_persp ||
5867 key->ps_prolog.states.bc_optimize_for_linear ||
5868 key->ps_prolog.states.poly_stipple;
5869 }
5870
5871 /**
5872 * Compute the PS epilog key, which contains all the information needed to
5873 * build the PS epilog function.
5874 */
5875 static void si_get_ps_epilog_key(struct si_shader *shader,
5876 union si_shader_part_key *key)
5877 {
5878 struct tgsi_shader_info *info = &shader->selector->info;
5879 memset(key, 0, sizeof(*key));
5880 key->ps_epilog.colors_written = info->colors_written;
5881 key->ps_epilog.writes_z = info->writes_z;
5882 key->ps_epilog.writes_stencil = info->writes_stencil;
5883 key->ps_epilog.writes_samplemask = info->writes_samplemask;
5884 key->ps_epilog.states = shader->key.part.ps.epilog;
5885 }
5886
5887 /**
5888 * Build the GS prolog function. Rotate the input vertices for triangle strips
5889 * with adjacency.
5890 */
5891 static void si_build_gs_prolog_function(struct si_shader_context *ctx,
5892 union si_shader_part_key *key)
5893 {
5894 unsigned num_sgprs, num_vgprs;
5895 struct gallivm_state *gallivm = &ctx->gallivm;
5896 struct si_function_info fninfo;
5897 LLVMBuilderRef builder = gallivm->builder;
5898 LLVMTypeRef returns[48];
5899 LLVMValueRef func, ret;
5900
5901 si_init_function_info(&fninfo);
5902
5903 if (ctx->screen->b.chip_class >= GFX9) {
5904 num_sgprs = 8 + GFX9_GS_NUM_USER_SGPR;
5905 num_vgprs = 5; /* ES inputs are not needed by GS */
5906 } else {
5907 num_sgprs = GFX6_GS_NUM_USER_SGPR + 2;
5908 num_vgprs = 8;
5909 }
5910
5911 for (unsigned i = 0; i < num_sgprs; ++i) {
5912 add_arg(&fninfo, ARG_SGPR, ctx->i32);
5913 returns[i] = ctx->i32;
5914 }
5915
5916 for (unsigned i = 0; i < num_vgprs; ++i) {
5917 add_arg(&fninfo, ARG_VGPR, ctx->i32);
5918 returns[num_sgprs + i] = ctx->f32;
5919 }
5920
5921 /* Create the function. */
5922 si_create_function(ctx, "gs_prolog", returns, num_sgprs + num_vgprs,
5923 &fninfo, 0);
5924 func = ctx->main_fn;
5925
5926 /* Set the full EXEC mask for the prolog, because we are only fiddling
5927 * with registers here. The main shader part will set the correct EXEC
5928 * mask.
5929 */
5930 if (ctx->screen->b.chip_class >= GFX9 && !key->gs_prolog.is_monolithic)
5931 si_init_exec_full_mask(ctx);
5932
5933 /* Copy inputs to outputs. This should be no-op, as the registers match,
5934 * but it will prevent the compiler from overwriting them unintentionally.
5935 */
5936 ret = ctx->return_value;
5937 for (unsigned i = 0; i < num_sgprs; i++) {
5938 LLVMValueRef p = LLVMGetParam(func, i);
5939 ret = LLVMBuildInsertValue(builder, ret, p, i, "");
5940 }
5941 for (unsigned i = 0; i < num_vgprs; i++) {
5942 LLVMValueRef p = LLVMGetParam(func, num_sgprs + i);
5943 p = LLVMBuildBitCast(builder, p, ctx->f32, "");
5944 ret = LLVMBuildInsertValue(builder, ret, p, num_sgprs + i, "");
5945 }
5946
5947 if (key->gs_prolog.states.tri_strip_adj_fix) {
5948 /* Remap the input vertices for every other primitive. */
5949 const unsigned gfx6_vtx_params[6] = {
5950 num_sgprs,
5951 num_sgprs + 1,
5952 num_sgprs + 3,
5953 num_sgprs + 4,
5954 num_sgprs + 5,
5955 num_sgprs + 6
5956 };
5957 const unsigned gfx9_vtx_params[3] = {
5958 num_sgprs,
5959 num_sgprs + 1,
5960 num_sgprs + 4,
5961 };
5962 LLVMValueRef vtx_in[6], vtx_out[6];
5963 LLVMValueRef prim_id, rotate;
5964
5965 if (ctx->screen->b.chip_class >= GFX9) {
5966 for (unsigned i = 0; i < 3; i++) {
5967 vtx_in[i*2] = unpack_param(ctx, gfx9_vtx_params[i], 0, 16);
5968 vtx_in[i*2+1] = unpack_param(ctx, gfx9_vtx_params[i], 16, 16);
5969 }
5970 } else {
5971 for (unsigned i = 0; i < 6; i++)
5972 vtx_in[i] = LLVMGetParam(func, gfx6_vtx_params[i]);
5973 }
5974
5975 prim_id = LLVMGetParam(func, num_sgprs + 2);
5976 rotate = LLVMBuildTrunc(builder, prim_id, ctx->i1, "");
5977
5978 for (unsigned i = 0; i < 6; ++i) {
5979 LLVMValueRef base, rotated;
5980 base = vtx_in[i];
5981 rotated = vtx_in[(i + 4) % 6];
5982 vtx_out[i] = LLVMBuildSelect(builder, rotate, rotated, base, "");
5983 }
5984
5985 if (ctx->screen->b.chip_class >= GFX9) {
5986 for (unsigned i = 0; i < 3; i++) {
5987 LLVMValueRef hi, out;
5988
5989 hi = LLVMBuildShl(builder, vtx_out[i*2+1],
5990 LLVMConstInt(ctx->i32, 16, 0), "");
5991 out = LLVMBuildOr(builder, vtx_out[i*2], hi, "");
5992 out = LLVMBuildBitCast(builder, out, ctx->f32, "");
5993 ret = LLVMBuildInsertValue(builder, ret, out,
5994 gfx9_vtx_params[i], "");
5995 }
5996 } else {
5997 for (unsigned i = 0; i < 6; i++) {
5998 LLVMValueRef out;
5999
6000 out = LLVMBuildBitCast(builder, vtx_out[i], ctx->f32, "");
6001 ret = LLVMBuildInsertValue(builder, ret, out,
6002 gfx6_vtx_params[i], "");
6003 }
6004 }
6005 }
6006
6007 LLVMBuildRet(builder, ret);
6008 }
6009
6010 /**
6011 * Given a list of shader part functions, build a wrapper function that
6012 * runs them in sequence to form a monolithic shader.
6013 */
6014 static void si_build_wrapper_function(struct si_shader_context *ctx,
6015 LLVMValueRef *parts,
6016 unsigned num_parts,
6017 unsigned main_part,
6018 unsigned next_shader_first_part)
6019 {
6020 struct gallivm_state *gallivm = &ctx->gallivm;
6021 LLVMBuilderRef builder = ctx->gallivm.builder;
6022 /* PS epilog has one arg per color component; gfx9 merged shader
6023 * prologs need to forward 32 user SGPRs.
6024 */
6025 struct si_function_info fninfo;
6026 LLVMValueRef initial[64], out[64];
6027 LLVMTypeRef function_type;
6028 unsigned num_first_params;
6029 unsigned num_out, initial_num_out;
6030 MAYBE_UNUSED unsigned num_out_sgpr; /* used in debug checks */
6031 MAYBE_UNUSED unsigned initial_num_out_sgpr; /* used in debug checks */
6032 unsigned num_sgprs, num_vgprs;
6033 unsigned gprs;
6034 struct lp_build_if_state if_state;
6035
6036 si_init_function_info(&fninfo);
6037
6038 for (unsigned i = 0; i < num_parts; ++i) {
6039 lp_add_function_attr(parts[i], -1, LP_FUNC_ATTR_ALWAYSINLINE);
6040 LLVMSetLinkage(parts[i], LLVMPrivateLinkage);
6041 }
6042
6043 /* The parameters of the wrapper function correspond to those of the
6044 * first part in terms of SGPRs and VGPRs, but we use the types of the
6045 * main part to get the right types. This is relevant for the
6046 * dereferenceable attribute on descriptor table pointers.
6047 */
6048 num_sgprs = 0;
6049 num_vgprs = 0;
6050
6051 function_type = LLVMGetElementType(LLVMTypeOf(parts[0]));
6052 num_first_params = LLVMCountParamTypes(function_type);
6053
6054 for (unsigned i = 0; i < num_first_params; ++i) {
6055 LLVMValueRef param = LLVMGetParam(parts[0], i);
6056
6057 if (ac_is_sgpr_param(param)) {
6058 assert(num_vgprs == 0);
6059 num_sgprs += llvm_get_type_size(LLVMTypeOf(param)) / 4;
6060 } else {
6061 num_vgprs += llvm_get_type_size(LLVMTypeOf(param)) / 4;
6062 }
6063 }
6064
6065 gprs = 0;
6066 while (gprs < num_sgprs + num_vgprs) {
6067 LLVMValueRef param = LLVMGetParam(parts[main_part], fninfo.num_params);
6068 LLVMTypeRef type = LLVMTypeOf(param);
6069 unsigned size = llvm_get_type_size(type) / 4;
6070
6071 add_arg(&fninfo, gprs < num_sgprs ? ARG_SGPR : ARG_VGPR, type);
6072
6073 assert(ac_is_sgpr_param(param) == (gprs < num_sgprs));
6074 assert(gprs + size <= num_sgprs + num_vgprs &&
6075 (gprs >= num_sgprs || gprs + size <= num_sgprs));
6076
6077 gprs += size;
6078 }
6079
6080 si_create_function(ctx, "wrapper", NULL, 0, &fninfo,
6081 si_get_max_workgroup_size(ctx->shader));
6082
6083 if (is_merged_shader(ctx->shader))
6084 si_init_exec_full_mask(ctx);
6085
6086 /* Record the arguments of the function as if they were an output of
6087 * a previous part.
6088 */
6089 num_out = 0;
6090 num_out_sgpr = 0;
6091
6092 for (unsigned i = 0; i < fninfo.num_params; ++i) {
6093 LLVMValueRef param = LLVMGetParam(ctx->main_fn, i);
6094 LLVMTypeRef param_type = LLVMTypeOf(param);
6095 LLVMTypeRef out_type = i < fninfo.num_sgpr_params ? ctx->i32 : ctx->f32;
6096 unsigned size = llvm_get_type_size(param_type) / 4;
6097
6098 if (size == 1) {
6099 if (param_type != out_type)
6100 param = LLVMBuildBitCast(builder, param, out_type, "");
6101 out[num_out++] = param;
6102 } else {
6103 LLVMTypeRef vector_type = LLVMVectorType(out_type, size);
6104
6105 if (LLVMGetTypeKind(param_type) == LLVMPointerTypeKind) {
6106 param = LLVMBuildPtrToInt(builder, param, ctx->i64, "");
6107 param_type = ctx->i64;
6108 }
6109
6110 if (param_type != vector_type)
6111 param = LLVMBuildBitCast(builder, param, vector_type, "");
6112
6113 for (unsigned j = 0; j < size; ++j)
6114 out[num_out++] = LLVMBuildExtractElement(
6115 builder, param, LLVMConstInt(ctx->i32, j, 0), "");
6116 }
6117
6118 if (i < fninfo.num_sgpr_params)
6119 num_out_sgpr = num_out;
6120 }
6121
6122 memcpy(initial, out, sizeof(out));
6123 initial_num_out = num_out;
6124 initial_num_out_sgpr = num_out_sgpr;
6125
6126 /* Now chain the parts. */
6127 for (unsigned part = 0; part < num_parts; ++part) {
6128 LLVMValueRef in[48];
6129 LLVMValueRef ret;
6130 LLVMTypeRef ret_type;
6131 unsigned out_idx = 0;
6132 unsigned num_params = LLVMCountParams(parts[part]);
6133
6134 /* Merged shaders are executed conditionally depending
6135 * on the number of enabled threads passed in the input SGPRs. */
6136 if (is_merged_shader(ctx->shader) && part == 0) {
6137 LLVMValueRef ena, count = initial[3];
6138
6139 count = LLVMBuildAnd(builder, count,
6140 LLVMConstInt(ctx->i32, 0x7f, 0), "");
6141 ena = LLVMBuildICmp(builder, LLVMIntULT,
6142 ac_get_thread_id(&ctx->ac), count, "");
6143 lp_build_if(&if_state, &ctx->gallivm, ena);
6144 }
6145
6146 /* Derive arguments for the next part from outputs of the
6147 * previous one.
6148 */
6149 for (unsigned param_idx = 0; param_idx < num_params; ++param_idx) {
6150 LLVMValueRef param;
6151 LLVMTypeRef param_type;
6152 bool is_sgpr;
6153 unsigned param_size;
6154 LLVMValueRef arg = NULL;
6155
6156 param = LLVMGetParam(parts[part], param_idx);
6157 param_type = LLVMTypeOf(param);
6158 param_size = llvm_get_type_size(param_type) / 4;
6159 is_sgpr = ac_is_sgpr_param(param);
6160
6161 if (is_sgpr) {
6162 #if HAVE_LLVM < 0x0400
6163 LLVMRemoveAttribute(param, LLVMByValAttribute);
6164 #else
6165 unsigned kind_id = LLVMGetEnumAttributeKindForName("byval", 5);
6166 LLVMRemoveEnumAttributeAtIndex(parts[part], param_idx + 1, kind_id);
6167 #endif
6168 lp_add_function_attr(parts[part], param_idx + 1, LP_FUNC_ATTR_INREG);
6169 }
6170
6171 assert(out_idx + param_size <= (is_sgpr ? num_out_sgpr : num_out));
6172 assert(is_sgpr || out_idx >= num_out_sgpr);
6173
6174 if (param_size == 1)
6175 arg = out[out_idx];
6176 else
6177 arg = lp_build_gather_values(gallivm, &out[out_idx], param_size);
6178
6179 if (LLVMTypeOf(arg) != param_type) {
6180 if (LLVMGetTypeKind(param_type) == LLVMPointerTypeKind) {
6181 arg = LLVMBuildBitCast(builder, arg, ctx->i64, "");
6182 arg = LLVMBuildIntToPtr(builder, arg, param_type, "");
6183 } else {
6184 arg = LLVMBuildBitCast(builder, arg, param_type, "");
6185 }
6186 }
6187
6188 in[param_idx] = arg;
6189 out_idx += param_size;
6190 }
6191
6192 ret = LLVMBuildCall(builder, parts[part], in, num_params, "");
6193
6194 if (is_merged_shader(ctx->shader) &&
6195 part + 1 == next_shader_first_part) {
6196 lp_build_endif(&if_state);
6197
6198 /* The second half of the merged shader should use
6199 * the inputs from the toplevel (wrapper) function,
6200 * not the return value from the last call.
6201 *
6202 * That's because the last call was executed condi-
6203 * tionally, so we can't consume it in the main
6204 * block.
6205 */
6206 memcpy(out, initial, sizeof(initial));
6207 num_out = initial_num_out;
6208 num_out_sgpr = initial_num_out_sgpr;
6209 continue;
6210 }
6211
6212 /* Extract the returned GPRs. */
6213 ret_type = LLVMTypeOf(ret);
6214 num_out = 0;
6215 num_out_sgpr = 0;
6216
6217 if (LLVMGetTypeKind(ret_type) != LLVMVoidTypeKind) {
6218 assert(LLVMGetTypeKind(ret_type) == LLVMStructTypeKind);
6219
6220 unsigned ret_size = LLVMCountStructElementTypes(ret_type);
6221
6222 for (unsigned i = 0; i < ret_size; ++i) {
6223 LLVMValueRef val =
6224 LLVMBuildExtractValue(builder, ret, i, "");
6225
6226 assert(num_out < ARRAY_SIZE(out));
6227 out[num_out++] = val;
6228
6229 if (LLVMTypeOf(val) == ctx->i32) {
6230 assert(num_out_sgpr + 1 == num_out);
6231 num_out_sgpr = num_out;
6232 }
6233 }
6234 }
6235 }
6236
6237 LLVMBuildRetVoid(builder);
6238 }
6239
6240 int si_compile_tgsi_shader(struct si_screen *sscreen,
6241 LLVMTargetMachineRef tm,
6242 struct si_shader *shader,
6243 bool is_monolithic,
6244 struct pipe_debug_callback *debug)
6245 {
6246 struct si_shader_selector *sel = shader->selector;
6247 struct si_shader_context ctx;
6248 int r = -1;
6249
6250 /* Dump TGSI code before doing TGSI->LLVM conversion in case the
6251 * conversion fails. */
6252 if (r600_can_dump_shader(&sscreen->b, sel->info.processor) &&
6253 !(sscreen->b.debug_flags & DBG_NO_TGSI)) {
6254 if (sel->tokens)
6255 tgsi_dump(sel->tokens, 0);
6256 else
6257 nir_print_shader(sel->nir, stderr);
6258 si_dump_streamout(&sel->so);
6259 }
6260
6261 si_init_shader_ctx(&ctx, sscreen, tm);
6262 si_llvm_context_set_tgsi(&ctx, shader);
6263 ctx.separate_prolog = !is_monolithic;
6264
6265 memset(shader->info.vs_output_param_offset, AC_EXP_PARAM_UNDEFINED,
6266 sizeof(shader->info.vs_output_param_offset));
6267
6268 shader->info.uses_instanceid = sel->info.uses_instanceid;
6269
6270 ctx.load_system_value = declare_system_value;
6271
6272 if (!si_compile_tgsi_main(&ctx, is_monolithic)) {
6273 si_llvm_dispose(&ctx);
6274 return -1;
6275 }
6276
6277 if (is_monolithic && ctx.type == PIPE_SHADER_VERTEX) {
6278 LLVMValueRef parts[2];
6279 bool need_prolog = sel->vs_needs_prolog;
6280
6281 parts[1] = ctx.main_fn;
6282
6283 if (need_prolog) {
6284 union si_shader_part_key prolog_key;
6285 si_get_vs_prolog_key(&sel->info,
6286 shader->info.num_input_sgprs,
6287 &shader->key.part.vs.prolog,
6288 shader, &prolog_key);
6289 si_build_vs_prolog_function(&ctx, &prolog_key);
6290 parts[0] = ctx.main_fn;
6291 }
6292
6293 si_build_wrapper_function(&ctx, parts + !need_prolog,
6294 1 + need_prolog, need_prolog, 0);
6295 } else if (is_monolithic && ctx.type == PIPE_SHADER_TESS_CTRL) {
6296 if (sscreen->b.chip_class >= GFX9) {
6297 struct si_shader_selector *ls = shader->key.part.tcs.ls;
6298 LLVMValueRef parts[4];
6299
6300 /* TCS main part */
6301 parts[2] = ctx.main_fn;
6302
6303 /* TCS epilog */
6304 union si_shader_part_key tcs_epilog_key;
6305 memset(&tcs_epilog_key, 0, sizeof(tcs_epilog_key));
6306 tcs_epilog_key.tcs_epilog.states = shader->key.part.tcs.epilog;
6307 si_build_tcs_epilog_function(&ctx, &tcs_epilog_key);
6308 parts[3] = ctx.main_fn;
6309
6310 /* VS prolog */
6311 if (ls->vs_needs_prolog) {
6312 union si_shader_part_key vs_prolog_key;
6313 si_get_vs_prolog_key(&ls->info,
6314 shader->info.num_input_sgprs,
6315 &shader->key.part.tcs.ls_prolog,
6316 shader, &vs_prolog_key);
6317 vs_prolog_key.vs_prolog.is_monolithic = true;
6318 si_build_vs_prolog_function(&ctx, &vs_prolog_key);
6319 parts[0] = ctx.main_fn;
6320 }
6321
6322 /* VS as LS main part */
6323 struct si_shader shader_ls = {};
6324 shader_ls.selector = ls;
6325 shader_ls.key.as_ls = 1;
6326 shader_ls.key.mono = shader->key.mono;
6327 shader_ls.key.opt = shader->key.opt;
6328 si_llvm_context_set_tgsi(&ctx, &shader_ls);
6329
6330 if (!si_compile_tgsi_main(&ctx, true)) {
6331 si_llvm_dispose(&ctx);
6332 return -1;
6333 }
6334 shader->info.uses_instanceid |= ls->info.uses_instanceid;
6335 parts[1] = ctx.main_fn;
6336
6337 /* Reset the shader context. */
6338 ctx.shader = shader;
6339 ctx.type = PIPE_SHADER_TESS_CTRL;
6340
6341 si_build_wrapper_function(&ctx,
6342 parts + !ls->vs_needs_prolog,
6343 4 - !ls->vs_needs_prolog, 0,
6344 ls->vs_needs_prolog ? 2 : 1);
6345 } else {
6346 LLVMValueRef parts[2];
6347 union si_shader_part_key epilog_key;
6348
6349 parts[0] = ctx.main_fn;
6350
6351 memset(&epilog_key, 0, sizeof(epilog_key));
6352 epilog_key.tcs_epilog.states = shader->key.part.tcs.epilog;
6353 si_build_tcs_epilog_function(&ctx, &epilog_key);
6354 parts[1] = ctx.main_fn;
6355
6356 si_build_wrapper_function(&ctx, parts, 2, 0, 0);
6357 }
6358 } else if (is_monolithic && ctx.type == PIPE_SHADER_GEOMETRY) {
6359 if (ctx.screen->b.chip_class >= GFX9) {
6360 struct si_shader_selector *es = shader->key.part.gs.es;
6361 LLVMValueRef es_prolog = NULL;
6362 LLVMValueRef es_main = NULL;
6363 LLVMValueRef gs_prolog = NULL;
6364 LLVMValueRef gs_main = ctx.main_fn;
6365
6366 /* GS prolog */
6367 union si_shader_part_key gs_prolog_key;
6368 memset(&gs_prolog_key, 0, sizeof(gs_prolog_key));
6369 gs_prolog_key.gs_prolog.states = shader->key.part.gs.prolog;
6370 gs_prolog_key.gs_prolog.is_monolithic = true;
6371 si_build_gs_prolog_function(&ctx, &gs_prolog_key);
6372 gs_prolog = ctx.main_fn;
6373
6374 /* ES prolog */
6375 if (es->vs_needs_prolog) {
6376 union si_shader_part_key vs_prolog_key;
6377 si_get_vs_prolog_key(&es->info,
6378 shader->info.num_input_sgprs,
6379 &shader->key.part.tcs.ls_prolog,
6380 shader, &vs_prolog_key);
6381 vs_prolog_key.vs_prolog.is_monolithic = true;
6382 si_build_vs_prolog_function(&ctx, &vs_prolog_key);
6383 es_prolog = ctx.main_fn;
6384 }
6385
6386 /* ES main part */
6387 struct si_shader shader_es = {};
6388 shader_es.selector = es;
6389 shader_es.key.as_es = 1;
6390 shader_es.key.mono = shader->key.mono;
6391 shader_es.key.opt = shader->key.opt;
6392 si_llvm_context_set_tgsi(&ctx, &shader_es);
6393
6394 if (!si_compile_tgsi_main(&ctx, true)) {
6395 si_llvm_dispose(&ctx);
6396 return -1;
6397 }
6398 shader->info.uses_instanceid |= es->info.uses_instanceid;
6399 es_main = ctx.main_fn;
6400
6401 /* Reset the shader context. */
6402 ctx.shader = shader;
6403 ctx.type = PIPE_SHADER_GEOMETRY;
6404
6405 /* Prepare the array of shader parts. */
6406 LLVMValueRef parts[4];
6407 unsigned num_parts = 0, main_part, next_first_part;
6408
6409 if (es_prolog)
6410 parts[num_parts++] = es_prolog;
6411
6412 parts[main_part = num_parts++] = es_main;
6413 parts[next_first_part = num_parts++] = gs_prolog;
6414 parts[num_parts++] = gs_main;
6415
6416 si_build_wrapper_function(&ctx, parts, num_parts,
6417 main_part, next_first_part);
6418 } else {
6419 LLVMValueRef parts[2];
6420 union si_shader_part_key prolog_key;
6421
6422 parts[1] = ctx.main_fn;
6423
6424 memset(&prolog_key, 0, sizeof(prolog_key));
6425 prolog_key.gs_prolog.states = shader->key.part.gs.prolog;
6426 si_build_gs_prolog_function(&ctx, &prolog_key);
6427 parts[0] = ctx.main_fn;
6428
6429 si_build_wrapper_function(&ctx, parts, 2, 1, 0);
6430 }
6431 } else if (is_monolithic && ctx.type == PIPE_SHADER_FRAGMENT) {
6432 LLVMValueRef parts[3];
6433 union si_shader_part_key prolog_key;
6434 union si_shader_part_key epilog_key;
6435 bool need_prolog;
6436
6437 si_get_ps_prolog_key(shader, &prolog_key, false);
6438 need_prolog = si_need_ps_prolog(&prolog_key);
6439
6440 parts[need_prolog ? 1 : 0] = ctx.main_fn;
6441
6442 if (need_prolog) {
6443 si_build_ps_prolog_function(&ctx, &prolog_key);
6444 parts[0] = ctx.main_fn;
6445 }
6446
6447 si_get_ps_epilog_key(shader, &epilog_key);
6448 si_build_ps_epilog_function(&ctx, &epilog_key);
6449 parts[need_prolog ? 2 : 1] = ctx.main_fn;
6450
6451 si_build_wrapper_function(&ctx, parts, need_prolog ? 3 : 2,
6452 need_prolog ? 1 : 0, 0);
6453 }
6454
6455 si_llvm_optimize_module(&ctx);
6456
6457 /* Post-optimization transformations and analysis. */
6458 si_optimize_vs_outputs(&ctx);
6459
6460 if ((debug && debug->debug_message) ||
6461 r600_can_dump_shader(&sscreen->b, ctx.type))
6462 si_count_scratch_private_memory(&ctx);
6463
6464 /* Compile to bytecode. */
6465 r = si_compile_llvm(sscreen, &shader->binary, &shader->config, tm,
6466 ctx.gallivm.module, debug, ctx.type, "TGSI shader");
6467 si_llvm_dispose(&ctx);
6468 if (r) {
6469 fprintf(stderr, "LLVM failed to compile shader\n");
6470 return r;
6471 }
6472
6473 /* Validate SGPR and VGPR usage for compute to detect compiler bugs.
6474 * LLVM 3.9svn has this bug.
6475 */
6476 if (sel->type == PIPE_SHADER_COMPUTE) {
6477 unsigned wave_size = 64;
6478 unsigned max_vgprs = 256;
6479 unsigned max_sgprs = sscreen->b.chip_class >= VI ? 800 : 512;
6480 unsigned max_sgprs_per_wave = 128;
6481 unsigned max_block_threads = si_get_max_workgroup_size(shader);
6482 unsigned min_waves_per_cu = DIV_ROUND_UP(max_block_threads, wave_size);
6483 unsigned min_waves_per_simd = DIV_ROUND_UP(min_waves_per_cu, 4);
6484
6485 max_vgprs = max_vgprs / min_waves_per_simd;
6486 max_sgprs = MIN2(max_sgprs / min_waves_per_simd, max_sgprs_per_wave);
6487
6488 if (shader->config.num_sgprs > max_sgprs ||
6489 shader->config.num_vgprs > max_vgprs) {
6490 fprintf(stderr, "LLVM failed to compile a shader correctly: "
6491 "SGPR:VGPR usage is %u:%u, but the hw limit is %u:%u\n",
6492 shader->config.num_sgprs, shader->config.num_vgprs,
6493 max_sgprs, max_vgprs);
6494
6495 /* Just terminate the process, because dependent
6496 * shaders can hang due to bad input data, but use
6497 * the env var to allow shader-db to work.
6498 */
6499 if (!debug_get_bool_option("SI_PASS_BAD_SHADERS", false))
6500 abort();
6501 }
6502 }
6503
6504 /* Add the scratch offset to input SGPRs. */
6505 if (shader->config.scratch_bytes_per_wave && !is_merged_shader(shader))
6506 shader->info.num_input_sgprs += 1; /* scratch byte offset */
6507
6508 /* Calculate the number of fragment input VGPRs. */
6509 if (ctx.type == PIPE_SHADER_FRAGMENT) {
6510 shader->info.num_input_vgprs = 0;
6511 shader->info.face_vgpr_index = -1;
6512
6513 if (G_0286CC_PERSP_SAMPLE_ENA(shader->config.spi_ps_input_addr))
6514 shader->info.num_input_vgprs += 2;
6515 if (G_0286CC_PERSP_CENTER_ENA(shader->config.spi_ps_input_addr))
6516 shader->info.num_input_vgprs += 2;
6517 if (G_0286CC_PERSP_CENTROID_ENA(shader->config.spi_ps_input_addr))
6518 shader->info.num_input_vgprs += 2;
6519 if (G_0286CC_PERSP_PULL_MODEL_ENA(shader->config.spi_ps_input_addr))
6520 shader->info.num_input_vgprs += 3;
6521 if (G_0286CC_LINEAR_SAMPLE_ENA(shader->config.spi_ps_input_addr))
6522 shader->info.num_input_vgprs += 2;
6523 if (G_0286CC_LINEAR_CENTER_ENA(shader->config.spi_ps_input_addr))
6524 shader->info.num_input_vgprs += 2;
6525 if (G_0286CC_LINEAR_CENTROID_ENA(shader->config.spi_ps_input_addr))
6526 shader->info.num_input_vgprs += 2;
6527 if (G_0286CC_LINE_STIPPLE_TEX_ENA(shader->config.spi_ps_input_addr))
6528 shader->info.num_input_vgprs += 1;
6529 if (G_0286CC_POS_X_FLOAT_ENA(shader->config.spi_ps_input_addr))
6530 shader->info.num_input_vgprs += 1;
6531 if (G_0286CC_POS_Y_FLOAT_ENA(shader->config.spi_ps_input_addr))
6532 shader->info.num_input_vgprs += 1;
6533 if (G_0286CC_POS_Z_FLOAT_ENA(shader->config.spi_ps_input_addr))
6534 shader->info.num_input_vgprs += 1;
6535 if (G_0286CC_POS_W_FLOAT_ENA(shader->config.spi_ps_input_addr))
6536 shader->info.num_input_vgprs += 1;
6537 if (G_0286CC_FRONT_FACE_ENA(shader->config.spi_ps_input_addr)) {
6538 shader->info.face_vgpr_index = shader->info.num_input_vgprs;
6539 shader->info.num_input_vgprs += 1;
6540 }
6541 if (G_0286CC_ANCILLARY_ENA(shader->config.spi_ps_input_addr))
6542 shader->info.num_input_vgprs += 1;
6543 if (G_0286CC_SAMPLE_COVERAGE_ENA(shader->config.spi_ps_input_addr))
6544 shader->info.num_input_vgprs += 1;
6545 if (G_0286CC_POS_FIXED_PT_ENA(shader->config.spi_ps_input_addr))
6546 shader->info.num_input_vgprs += 1;
6547 }
6548
6549 return 0;
6550 }
6551
6552 /**
6553 * Create, compile and return a shader part (prolog or epilog).
6554 *
6555 * \param sscreen screen
6556 * \param list list of shader parts of the same category
6557 * \param type shader type
6558 * \param key shader part key
6559 * \param prolog whether the part being requested is a prolog
6560 * \param tm LLVM target machine
6561 * \param debug debug callback
6562 * \param build the callback responsible for building the main function
6563 * \return non-NULL on success
6564 */
6565 static struct si_shader_part *
6566 si_get_shader_part(struct si_screen *sscreen,
6567 struct si_shader_part **list,
6568 enum pipe_shader_type type,
6569 bool prolog,
6570 union si_shader_part_key *key,
6571 LLVMTargetMachineRef tm,
6572 struct pipe_debug_callback *debug,
6573 void (*build)(struct si_shader_context *,
6574 union si_shader_part_key *),
6575 const char *name)
6576 {
6577 struct si_shader_part *result;
6578
6579 mtx_lock(&sscreen->shader_parts_mutex);
6580
6581 /* Find existing. */
6582 for (result = *list; result; result = result->next) {
6583 if (memcmp(&result->key, key, sizeof(*key)) == 0) {
6584 mtx_unlock(&sscreen->shader_parts_mutex);
6585 return result;
6586 }
6587 }
6588
6589 /* Compile a new one. */
6590 result = CALLOC_STRUCT(si_shader_part);
6591 result->key = *key;
6592
6593 struct si_shader shader = {};
6594 struct si_shader_context ctx;
6595 struct gallivm_state *gallivm = &ctx.gallivm;
6596
6597 si_init_shader_ctx(&ctx, sscreen, tm);
6598 ctx.shader = &shader;
6599 ctx.type = type;
6600
6601 switch (type) {
6602 case PIPE_SHADER_VERTEX:
6603 break;
6604 case PIPE_SHADER_TESS_CTRL:
6605 assert(!prolog);
6606 shader.key.part.tcs.epilog = key->tcs_epilog.states;
6607 break;
6608 case PIPE_SHADER_GEOMETRY:
6609 assert(prolog);
6610 break;
6611 case PIPE_SHADER_FRAGMENT:
6612 if (prolog)
6613 shader.key.part.ps.prolog = key->ps_prolog.states;
6614 else
6615 shader.key.part.ps.epilog = key->ps_epilog.states;
6616 break;
6617 default:
6618 unreachable("bad shader part");
6619 }
6620
6621 build(&ctx, key);
6622
6623 /* Compile. */
6624 si_llvm_optimize_module(&ctx);
6625
6626 if (si_compile_llvm(sscreen, &result->binary, &result->config, tm,
6627 gallivm->module, debug, ctx.type, name)) {
6628 FREE(result);
6629 result = NULL;
6630 goto out;
6631 }
6632
6633 result->next = *list;
6634 *list = result;
6635
6636 out:
6637 si_llvm_dispose(&ctx);
6638 mtx_unlock(&sscreen->shader_parts_mutex);
6639 return result;
6640 }
6641
6642 static LLVMValueRef si_prolog_get_rw_buffers(struct si_shader_context *ctx)
6643 {
6644 struct gallivm_state *gallivm = &ctx->gallivm;
6645 LLVMValueRef ptr[2], list;
6646
6647 /* Get the pointer to rw buffers. */
6648 ptr[0] = LLVMGetParam(ctx->main_fn, SI_SGPR_RW_BUFFERS);
6649 ptr[1] = LLVMGetParam(ctx->main_fn, SI_SGPR_RW_BUFFERS_HI);
6650 list = lp_build_gather_values(gallivm, ptr, 2);
6651 list = LLVMBuildBitCast(gallivm->builder, list, ctx->i64, "");
6652 list = LLVMBuildIntToPtr(gallivm->builder, list,
6653 si_const_array(ctx->v4i32, SI_NUM_RW_BUFFERS), "");
6654 return list;
6655 }
6656
6657 /**
6658 * Build the vertex shader prolog function.
6659 *
6660 * The inputs are the same as VS (a lot of SGPRs and 4 VGPR system values).
6661 * All inputs are returned unmodified. The vertex load indices are
6662 * stored after them, which will be used by the API VS for fetching inputs.
6663 *
6664 * For example, the expected outputs for instance_divisors[] = {0, 1, 2} are:
6665 * input_v0,
6666 * input_v1,
6667 * input_v2,
6668 * input_v3,
6669 * (VertexID + BaseVertex),
6670 * (InstanceID + StartInstance),
6671 * (InstanceID / 2 + StartInstance)
6672 */
6673 static void si_build_vs_prolog_function(struct si_shader_context *ctx,
6674 union si_shader_part_key *key)
6675 {
6676 struct gallivm_state *gallivm = &ctx->gallivm;
6677 struct si_function_info fninfo;
6678 LLVMTypeRef *returns;
6679 LLVMValueRef ret, func;
6680 int num_returns, i;
6681 unsigned first_vs_vgpr = key->vs_prolog.num_input_sgprs +
6682 key->vs_prolog.num_merged_next_stage_vgprs;
6683 unsigned num_input_vgprs = key->vs_prolog.num_merged_next_stage_vgprs + 4;
6684 unsigned num_all_input_regs = key->vs_prolog.num_input_sgprs +
6685 num_input_vgprs;
6686 unsigned user_sgpr_base = key->vs_prolog.num_merged_next_stage_vgprs ? 8 : 0;
6687
6688 si_init_function_info(&fninfo);
6689
6690 /* 4 preloaded VGPRs + vertex load indices as prolog outputs */
6691 returns = alloca((num_all_input_regs + key->vs_prolog.last_input + 1) *
6692 sizeof(LLVMTypeRef));
6693 num_returns = 0;
6694
6695 /* Declare input and output SGPRs. */
6696 for (i = 0; i < key->vs_prolog.num_input_sgprs; i++) {
6697 add_arg(&fninfo, ARG_SGPR, ctx->i32);
6698 returns[num_returns++] = ctx->i32;
6699 }
6700
6701 /* Preloaded VGPRs (outputs must be floats) */
6702 for (i = 0; i < num_input_vgprs; i++) {
6703 add_arg(&fninfo, ARG_VGPR, ctx->i32);
6704 returns[num_returns++] = ctx->f32;
6705 }
6706
6707 fninfo.assign[first_vs_vgpr] = &ctx->abi.vertex_id;
6708 fninfo.assign[first_vs_vgpr + (key->vs_prolog.as_ls ? 2 : 1)] = &ctx->abi.instance_id;
6709
6710 /* Vertex load indices. */
6711 for (i = 0; i <= key->vs_prolog.last_input; i++)
6712 returns[num_returns++] = ctx->f32;
6713
6714 /* Create the function. */
6715 si_create_function(ctx, "vs_prolog", returns, num_returns, &fninfo, 0);
6716 func = ctx->main_fn;
6717
6718 if (key->vs_prolog.num_merged_next_stage_vgprs &&
6719 !key->vs_prolog.is_monolithic)
6720 si_init_exec_from_input(ctx, 3, 0);
6721
6722 /* Copy inputs to outputs. This should be no-op, as the registers match,
6723 * but it will prevent the compiler from overwriting them unintentionally.
6724 */
6725 ret = ctx->return_value;
6726 for (i = 0; i < key->vs_prolog.num_input_sgprs; i++) {
6727 LLVMValueRef p = LLVMGetParam(func, i);
6728 ret = LLVMBuildInsertValue(gallivm->builder, ret, p, i, "");
6729 }
6730 for (; i < fninfo.num_params; i++) {
6731 LLVMValueRef p = LLVMGetParam(func, i);
6732 p = LLVMBuildBitCast(gallivm->builder, p, ctx->f32, "");
6733 ret = LLVMBuildInsertValue(gallivm->builder, ret, p, i, "");
6734 }
6735
6736 /* Compute vertex load indices from instance divisors. */
6737 LLVMValueRef instance_divisor_constbuf = NULL;
6738
6739 if (key->vs_prolog.states.instance_divisor_is_fetched) {
6740 LLVMValueRef list = si_prolog_get_rw_buffers(ctx);
6741 LLVMValueRef buf_index =
6742 LLVMConstInt(ctx->i32, SI_VS_CONST_INSTANCE_DIVISORS, 0);
6743 instance_divisor_constbuf =
6744 ac_build_indexed_load_const(&ctx->ac, list, buf_index);
6745 }
6746
6747 for (i = 0; i <= key->vs_prolog.last_input; i++) {
6748 bool divisor_is_one =
6749 key->vs_prolog.states.instance_divisor_is_one & (1u << i);
6750 bool divisor_is_fetched =
6751 key->vs_prolog.states.instance_divisor_is_fetched & (1u << i);
6752 LLVMValueRef index;
6753
6754 if (divisor_is_one || divisor_is_fetched) {
6755 LLVMValueRef divisor = ctx->i32_1;
6756
6757 if (divisor_is_fetched) {
6758 divisor = buffer_load_const(ctx, instance_divisor_constbuf,
6759 LLVMConstInt(ctx->i32, i * 4, 0));
6760 divisor = LLVMBuildBitCast(gallivm->builder, divisor,
6761 ctx->i32, "");
6762 }
6763
6764 /* InstanceID / Divisor + StartInstance */
6765 index = get_instance_index_for_fetch(ctx,
6766 user_sgpr_base +
6767 SI_SGPR_START_INSTANCE,
6768 divisor);
6769 } else {
6770 /* VertexID + BaseVertex */
6771 index = LLVMBuildAdd(gallivm->builder,
6772 ctx->abi.vertex_id,
6773 LLVMGetParam(func, user_sgpr_base +
6774 SI_SGPR_BASE_VERTEX), "");
6775 }
6776
6777 index = LLVMBuildBitCast(gallivm->builder, index, ctx->f32, "");
6778 ret = LLVMBuildInsertValue(gallivm->builder, ret, index,
6779 fninfo.num_params + i, "");
6780 }
6781
6782 si_llvm_build_ret(ctx, ret);
6783 }
6784
6785 static bool si_get_vs_prolog(struct si_screen *sscreen,
6786 LLVMTargetMachineRef tm,
6787 struct si_shader *shader,
6788 struct pipe_debug_callback *debug,
6789 struct si_shader *main_part,
6790 const struct si_vs_prolog_bits *key)
6791 {
6792 struct si_shader_selector *vs = main_part->selector;
6793
6794 /* The prolog is a no-op if there are no inputs. */
6795 if (!vs->vs_needs_prolog)
6796 return true;
6797
6798 /* Get the prolog. */
6799 union si_shader_part_key prolog_key;
6800 si_get_vs_prolog_key(&vs->info, main_part->info.num_input_sgprs,
6801 key, shader, &prolog_key);
6802
6803 shader->prolog =
6804 si_get_shader_part(sscreen, &sscreen->vs_prologs,
6805 PIPE_SHADER_VERTEX, true, &prolog_key, tm,
6806 debug, si_build_vs_prolog_function,
6807 "Vertex Shader Prolog");
6808 return shader->prolog != NULL;
6809 }
6810
6811 /**
6812 * Select and compile (or reuse) vertex shader parts (prolog & epilog).
6813 */
6814 static bool si_shader_select_vs_parts(struct si_screen *sscreen,
6815 LLVMTargetMachineRef tm,
6816 struct si_shader *shader,
6817 struct pipe_debug_callback *debug)
6818 {
6819 return si_get_vs_prolog(sscreen, tm, shader, debug, shader,
6820 &shader->key.part.vs.prolog);
6821 }
6822
6823 /**
6824 * Compile the TCS epilog function. This writes tesselation factors to memory
6825 * based on the output primitive type of the tesselator (determined by TES).
6826 */
6827 static void si_build_tcs_epilog_function(struct si_shader_context *ctx,
6828 union si_shader_part_key *key)
6829 {
6830 struct gallivm_state *gallivm = &ctx->gallivm;
6831 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
6832 struct si_function_info fninfo;
6833 LLVMValueRef func;
6834
6835 si_init_function_info(&fninfo);
6836
6837 if (ctx->screen->b.chip_class >= GFX9) {
6838 add_arg(&fninfo, ARG_SGPR, ctx->i64);
6839 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
6840 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* wave info */
6841 ctx->param_tcs_factor_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
6842 add_arg(&fninfo, ARG_SGPR, ctx->i32);
6843 add_arg(&fninfo, ARG_SGPR, ctx->i32);
6844 add_arg(&fninfo, ARG_SGPR, ctx->i32);
6845 add_arg(&fninfo, ARG_SGPR, ctx->i64);
6846 add_arg(&fninfo, ARG_SGPR, ctx->i64);
6847 add_arg(&fninfo, ARG_SGPR, ctx->i64);
6848 add_arg(&fninfo, ARG_SGPR, ctx->i64);
6849 add_arg(&fninfo, ARG_SGPR, ctx->i32);
6850 add_arg(&fninfo, ARG_SGPR, ctx->i32);
6851 add_arg(&fninfo, ARG_SGPR, ctx->i32);
6852 add_arg(&fninfo, ARG_SGPR, ctx->i32);
6853 ctx->param_tcs_offchip_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
6854 add_arg(&fninfo, ARG_SGPR, ctx->i32);
6855 add_arg(&fninfo, ARG_SGPR, ctx->i32);
6856 ctx->param_tcs_offchip_addr_base64k = add_arg(&fninfo, ARG_SGPR, ctx->i32);
6857 ctx->param_tcs_factor_addr_base64k = add_arg(&fninfo, ARG_SGPR, ctx->i32);
6858 } else {
6859 add_arg(&fninfo, ARG_SGPR, ctx->i64);
6860 add_arg(&fninfo, ARG_SGPR, ctx->i64);
6861 add_arg(&fninfo, ARG_SGPR, ctx->i64);
6862 ctx->param_tcs_offchip_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
6863 add_arg(&fninfo, ARG_SGPR, ctx->i32);
6864 add_arg(&fninfo, ARG_SGPR, ctx->i32);
6865 add_arg(&fninfo, ARG_SGPR, ctx->i32);
6866 ctx->param_tcs_offchip_addr_base64k = add_arg(&fninfo, ARG_SGPR, ctx->i32);
6867 ctx->param_tcs_factor_addr_base64k = add_arg(&fninfo, ARG_SGPR, ctx->i32);
6868 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
6869 ctx->param_tcs_factor_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
6870 }
6871
6872 add_arg(&fninfo, ARG_VGPR, ctx->i32); /* VGPR gap */
6873 add_arg(&fninfo, ARG_VGPR, ctx->i32); /* VGPR gap */
6874 unsigned tess_factors_idx =
6875 add_arg(&fninfo, ARG_VGPR, ctx->i32); /* patch index within the wave (REL_PATCH_ID) */
6876 add_arg(&fninfo, ARG_VGPR, ctx->i32); /* invocation ID within the patch */
6877 add_arg(&fninfo, ARG_VGPR, ctx->i32); /* LDS offset where tess factors should be loaded from */
6878
6879 /* Create the function. */
6880 si_create_function(ctx, "tcs_epilog", NULL, 0, &fninfo,
6881 ctx->screen->b.chip_class >= CIK ? 128 : 64);
6882 declare_lds_as_pointer(ctx);
6883 func = ctx->main_fn;
6884
6885 si_write_tess_factors(bld_base,
6886 LLVMGetParam(func, tess_factors_idx),
6887 LLVMGetParam(func, tess_factors_idx + 1),
6888 LLVMGetParam(func, tess_factors_idx + 2));
6889
6890 LLVMBuildRetVoid(gallivm->builder);
6891 }
6892
6893 /**
6894 * Select and compile (or reuse) TCS parts (epilog).
6895 */
6896 static bool si_shader_select_tcs_parts(struct si_screen *sscreen,
6897 LLVMTargetMachineRef tm,
6898 struct si_shader *shader,
6899 struct pipe_debug_callback *debug)
6900 {
6901 if (sscreen->b.chip_class >= GFX9) {
6902 struct si_shader *ls_main_part =
6903 shader->key.part.tcs.ls->main_shader_part_ls;
6904
6905 if (!si_get_vs_prolog(sscreen, tm, shader, debug, ls_main_part,
6906 &shader->key.part.tcs.ls_prolog))
6907 return false;
6908
6909 shader->previous_stage = ls_main_part;
6910 }
6911
6912 /* Get the epilog. */
6913 union si_shader_part_key epilog_key;
6914 memset(&epilog_key, 0, sizeof(epilog_key));
6915 epilog_key.tcs_epilog.states = shader->key.part.tcs.epilog;
6916
6917 shader->epilog = si_get_shader_part(sscreen, &sscreen->tcs_epilogs,
6918 PIPE_SHADER_TESS_CTRL, false,
6919 &epilog_key, tm, debug,
6920 si_build_tcs_epilog_function,
6921 "Tessellation Control Shader Epilog");
6922 return shader->epilog != NULL;
6923 }
6924
6925 /**
6926 * Select and compile (or reuse) GS parts (prolog).
6927 */
6928 static bool si_shader_select_gs_parts(struct si_screen *sscreen,
6929 LLVMTargetMachineRef tm,
6930 struct si_shader *shader,
6931 struct pipe_debug_callback *debug)
6932 {
6933 if (sscreen->b.chip_class >= GFX9) {
6934 struct si_shader *es_main_part =
6935 shader->key.part.gs.es->main_shader_part_es;
6936
6937 if (shader->key.part.gs.es->type == PIPE_SHADER_VERTEX &&
6938 !si_get_vs_prolog(sscreen, tm, shader, debug, es_main_part,
6939 &shader->key.part.gs.vs_prolog))
6940 return false;
6941
6942 shader->previous_stage = es_main_part;
6943 }
6944
6945 if (!shader->key.part.gs.prolog.tri_strip_adj_fix)
6946 return true;
6947
6948 union si_shader_part_key prolog_key;
6949 memset(&prolog_key, 0, sizeof(prolog_key));
6950 prolog_key.gs_prolog.states = shader->key.part.gs.prolog;
6951
6952 shader->prolog2 = si_get_shader_part(sscreen, &sscreen->gs_prologs,
6953 PIPE_SHADER_GEOMETRY, true,
6954 &prolog_key, tm, debug,
6955 si_build_gs_prolog_function,
6956 "Geometry Shader Prolog");
6957 return shader->prolog2 != NULL;
6958 }
6959
6960 /**
6961 * Build the pixel shader prolog function. This handles:
6962 * - two-side color selection and interpolation
6963 * - overriding interpolation parameters for the API PS
6964 * - polygon stippling
6965 *
6966 * All preloaded SGPRs and VGPRs are passed through unmodified unless they are
6967 * overriden by other states. (e.g. per-sample interpolation)
6968 * Interpolated colors are stored after the preloaded VGPRs.
6969 */
6970 static void si_build_ps_prolog_function(struct si_shader_context *ctx,
6971 union si_shader_part_key *key)
6972 {
6973 struct gallivm_state *gallivm = &ctx->gallivm;
6974 struct si_function_info fninfo;
6975 LLVMValueRef ret, func;
6976 int num_returns, i, num_color_channels;
6977
6978 assert(si_need_ps_prolog(key));
6979
6980 si_init_function_info(&fninfo);
6981
6982 /* Declare inputs. */
6983 for (i = 0; i < key->ps_prolog.num_input_sgprs; i++)
6984 add_arg(&fninfo, ARG_SGPR, ctx->i32);
6985
6986 for (i = 0; i < key->ps_prolog.num_input_vgprs; i++)
6987 add_arg(&fninfo, ARG_VGPR, ctx->f32);
6988
6989 /* Declare outputs (same as inputs + add colors if needed) */
6990 num_returns = fninfo.num_params;
6991 num_color_channels = util_bitcount(key->ps_prolog.colors_read);
6992 for (i = 0; i < num_color_channels; i++)
6993 fninfo.types[num_returns++] = ctx->f32;
6994
6995 /* Create the function. */
6996 si_create_function(ctx, "ps_prolog", fninfo.types, num_returns,
6997 &fninfo, 0);
6998 func = ctx->main_fn;
6999
7000 /* Copy inputs to outputs. This should be no-op, as the registers match,
7001 * but it will prevent the compiler from overwriting them unintentionally.
7002 */
7003 ret = ctx->return_value;
7004 for (i = 0; i < fninfo.num_params; i++) {
7005 LLVMValueRef p = LLVMGetParam(func, i);
7006 ret = LLVMBuildInsertValue(gallivm->builder, ret, p, i, "");
7007 }
7008
7009 /* Polygon stippling. */
7010 if (key->ps_prolog.states.poly_stipple) {
7011 /* POS_FIXED_PT is always last. */
7012 unsigned pos = key->ps_prolog.num_input_sgprs +
7013 key->ps_prolog.num_input_vgprs - 1;
7014 LLVMValueRef list = si_prolog_get_rw_buffers(ctx);
7015
7016 si_llvm_emit_polygon_stipple(ctx, list, pos);
7017 }
7018
7019 if (key->ps_prolog.states.bc_optimize_for_persp ||
7020 key->ps_prolog.states.bc_optimize_for_linear) {
7021 unsigned i, base = key->ps_prolog.num_input_sgprs;
7022 LLVMValueRef center[2], centroid[2], tmp, bc_optimize;
7023
7024 /* The shader should do: if (PRIM_MASK[31]) CENTROID = CENTER;
7025 * The hw doesn't compute CENTROID if the whole wave only
7026 * contains fully-covered quads.
7027 *
7028 * PRIM_MASK is after user SGPRs.
7029 */
7030 bc_optimize = LLVMGetParam(func, SI_PS_NUM_USER_SGPR);
7031 bc_optimize = LLVMBuildLShr(gallivm->builder, bc_optimize,
7032 LLVMConstInt(ctx->i32, 31, 0), "");
7033 bc_optimize = LLVMBuildTrunc(gallivm->builder, bc_optimize,
7034 ctx->i1, "");
7035
7036 if (key->ps_prolog.states.bc_optimize_for_persp) {
7037 /* Read PERSP_CENTER. */
7038 for (i = 0; i < 2; i++)
7039 center[i] = LLVMGetParam(func, base + 2 + i);
7040 /* Read PERSP_CENTROID. */
7041 for (i = 0; i < 2; i++)
7042 centroid[i] = LLVMGetParam(func, base + 4 + i);
7043 /* Select PERSP_CENTROID. */
7044 for (i = 0; i < 2; i++) {
7045 tmp = LLVMBuildSelect(gallivm->builder, bc_optimize,
7046 center[i], centroid[i], "");
7047 ret = LLVMBuildInsertValue(gallivm->builder, ret,
7048 tmp, base + 4 + i, "");
7049 }
7050 }
7051 if (key->ps_prolog.states.bc_optimize_for_linear) {
7052 /* Read LINEAR_CENTER. */
7053 for (i = 0; i < 2; i++)
7054 center[i] = LLVMGetParam(func, base + 8 + i);
7055 /* Read LINEAR_CENTROID. */
7056 for (i = 0; i < 2; i++)
7057 centroid[i] = LLVMGetParam(func, base + 10 + i);
7058 /* Select LINEAR_CENTROID. */
7059 for (i = 0; i < 2; i++) {
7060 tmp = LLVMBuildSelect(gallivm->builder, bc_optimize,
7061 center[i], centroid[i], "");
7062 ret = LLVMBuildInsertValue(gallivm->builder, ret,
7063 tmp, base + 10 + i, "");
7064 }
7065 }
7066 }
7067
7068 /* Force per-sample interpolation. */
7069 if (key->ps_prolog.states.force_persp_sample_interp) {
7070 unsigned i, base = key->ps_prolog.num_input_sgprs;
7071 LLVMValueRef persp_sample[2];
7072
7073 /* Read PERSP_SAMPLE. */
7074 for (i = 0; i < 2; i++)
7075 persp_sample[i] = LLVMGetParam(func, base + i);
7076 /* Overwrite PERSP_CENTER. */
7077 for (i = 0; i < 2; i++)
7078 ret = LLVMBuildInsertValue(gallivm->builder, ret,
7079 persp_sample[i], base + 2 + i, "");
7080 /* Overwrite PERSP_CENTROID. */
7081 for (i = 0; i < 2; i++)
7082 ret = LLVMBuildInsertValue(gallivm->builder, ret,
7083 persp_sample[i], base + 4 + i, "");
7084 }
7085 if (key->ps_prolog.states.force_linear_sample_interp) {
7086 unsigned i, base = key->ps_prolog.num_input_sgprs;
7087 LLVMValueRef linear_sample[2];
7088
7089 /* Read LINEAR_SAMPLE. */
7090 for (i = 0; i < 2; i++)
7091 linear_sample[i] = LLVMGetParam(func, base + 6 + i);
7092 /* Overwrite LINEAR_CENTER. */
7093 for (i = 0; i < 2; i++)
7094 ret = LLVMBuildInsertValue(gallivm->builder, ret,
7095 linear_sample[i], base + 8 + i, "");
7096 /* Overwrite LINEAR_CENTROID. */
7097 for (i = 0; i < 2; i++)
7098 ret = LLVMBuildInsertValue(gallivm->builder, ret,
7099 linear_sample[i], base + 10 + i, "");
7100 }
7101
7102 /* Force center interpolation. */
7103 if (key->ps_prolog.states.force_persp_center_interp) {
7104 unsigned i, base = key->ps_prolog.num_input_sgprs;
7105 LLVMValueRef persp_center[2];
7106
7107 /* Read PERSP_CENTER. */
7108 for (i = 0; i < 2; i++)
7109 persp_center[i] = LLVMGetParam(func, base + 2 + i);
7110 /* Overwrite PERSP_SAMPLE. */
7111 for (i = 0; i < 2; i++)
7112 ret = LLVMBuildInsertValue(gallivm->builder, ret,
7113 persp_center[i], base + i, "");
7114 /* Overwrite PERSP_CENTROID. */
7115 for (i = 0; i < 2; i++)
7116 ret = LLVMBuildInsertValue(gallivm->builder, ret,
7117 persp_center[i], base + 4 + i, "");
7118 }
7119 if (key->ps_prolog.states.force_linear_center_interp) {
7120 unsigned i, base = key->ps_prolog.num_input_sgprs;
7121 LLVMValueRef linear_center[2];
7122
7123 /* Read LINEAR_CENTER. */
7124 for (i = 0; i < 2; i++)
7125 linear_center[i] = LLVMGetParam(func, base + 8 + i);
7126 /* Overwrite LINEAR_SAMPLE. */
7127 for (i = 0; i < 2; i++)
7128 ret = LLVMBuildInsertValue(gallivm->builder, ret,
7129 linear_center[i], base + 6 + i, "");
7130 /* Overwrite LINEAR_CENTROID. */
7131 for (i = 0; i < 2; i++)
7132 ret = LLVMBuildInsertValue(gallivm->builder, ret,
7133 linear_center[i], base + 10 + i, "");
7134 }
7135
7136 /* Interpolate colors. */
7137 unsigned color_out_idx = 0;
7138 for (i = 0; i < 2; i++) {
7139 unsigned writemask = (key->ps_prolog.colors_read >> (i * 4)) & 0xf;
7140 unsigned face_vgpr = key->ps_prolog.num_input_sgprs +
7141 key->ps_prolog.face_vgpr_index;
7142 LLVMValueRef interp[2], color[4];
7143 LLVMValueRef interp_ij = NULL, prim_mask = NULL, face = NULL;
7144
7145 if (!writemask)
7146 continue;
7147
7148 /* If the interpolation qualifier is not CONSTANT (-1). */
7149 if (key->ps_prolog.color_interp_vgpr_index[i] != -1) {
7150 unsigned interp_vgpr = key->ps_prolog.num_input_sgprs +
7151 key->ps_prolog.color_interp_vgpr_index[i];
7152
7153 /* Get the (i,j) updated by bc_optimize handling. */
7154 interp[0] = LLVMBuildExtractValue(gallivm->builder, ret,
7155 interp_vgpr, "");
7156 interp[1] = LLVMBuildExtractValue(gallivm->builder, ret,
7157 interp_vgpr + 1, "");
7158 interp_ij = lp_build_gather_values(gallivm, interp, 2);
7159 }
7160
7161 /* Use the absolute location of the input. */
7162 prim_mask = LLVMGetParam(func, SI_PS_NUM_USER_SGPR);
7163
7164 if (key->ps_prolog.states.color_two_side) {
7165 face = LLVMGetParam(func, face_vgpr);
7166 face = LLVMBuildBitCast(gallivm->builder, face, ctx->i32, "");
7167 }
7168
7169 interp_fs_input(ctx,
7170 key->ps_prolog.color_attr_index[i],
7171 TGSI_SEMANTIC_COLOR, i,
7172 key->ps_prolog.num_interp_inputs,
7173 key->ps_prolog.colors_read, interp_ij,
7174 prim_mask, face, color);
7175
7176 while (writemask) {
7177 unsigned chan = u_bit_scan(&writemask);
7178 ret = LLVMBuildInsertValue(gallivm->builder, ret, color[chan],
7179 fninfo.num_params + color_out_idx++, "");
7180 }
7181 }
7182
7183 /* Tell LLVM to insert WQM instruction sequence when needed. */
7184 if (key->ps_prolog.wqm) {
7185 LLVMAddTargetDependentFunctionAttr(func,
7186 "amdgpu-ps-wqm-outputs", "");
7187 }
7188
7189 si_llvm_build_ret(ctx, ret);
7190 }
7191
7192 /**
7193 * Build the pixel shader epilog function. This handles everything that must be
7194 * emulated for pixel shader exports. (alpha-test, format conversions, etc)
7195 */
7196 static void si_build_ps_epilog_function(struct si_shader_context *ctx,
7197 union si_shader_part_key *key)
7198 {
7199 struct gallivm_state *gallivm = &ctx->gallivm;
7200 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
7201 struct si_function_info fninfo;
7202 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
7203 int i;
7204 struct si_ps_exports exp = {};
7205
7206 si_init_function_info(&fninfo);
7207
7208 /* Declare input SGPRs. */
7209 ctx->param_rw_buffers = add_arg(&fninfo, ARG_SGPR, ctx->i64);
7210 ctx->param_const_and_shader_buffers = add_arg(&fninfo, ARG_SGPR, ctx->i64);
7211 ctx->param_samplers_and_images = add_arg(&fninfo, ARG_SGPR, ctx->i64);
7212 add_arg_checked(&fninfo, ARG_SGPR, ctx->f32, SI_PARAM_ALPHA_REF);
7213
7214 /* Declare input VGPRs. */
7215 unsigned required_num_params =
7216 fninfo.num_sgpr_params +
7217 util_bitcount(key->ps_epilog.colors_written) * 4 +
7218 key->ps_epilog.writes_z +
7219 key->ps_epilog.writes_stencil +
7220 key->ps_epilog.writes_samplemask;
7221
7222 required_num_params = MAX2(required_num_params,
7223 fninfo.num_sgpr_params + PS_EPILOG_SAMPLEMASK_MIN_LOC + 1);
7224
7225 while (fninfo.num_params < required_num_params)
7226 add_arg(&fninfo, ARG_VGPR, ctx->f32);
7227
7228 /* Create the function. */
7229 si_create_function(ctx, "ps_epilog", NULL, 0, &fninfo, 0);
7230 /* Disable elimination of unused inputs. */
7231 si_llvm_add_attribute(ctx->main_fn,
7232 "InitialPSInputAddr", 0xffffff);
7233
7234 /* Process colors. */
7235 unsigned vgpr = fninfo.num_sgpr_params;
7236 unsigned colors_written = key->ps_epilog.colors_written;
7237 int last_color_export = -1;
7238
7239 /* Find the last color export. */
7240 if (!key->ps_epilog.writes_z &&
7241 !key->ps_epilog.writes_stencil &&
7242 !key->ps_epilog.writes_samplemask) {
7243 unsigned spi_format = key->ps_epilog.states.spi_shader_col_format;
7244
7245 /* If last_cbuf > 0, FS_COLOR0_WRITES_ALL_CBUFS is true. */
7246 if (colors_written == 0x1 && key->ps_epilog.states.last_cbuf > 0) {
7247 /* Just set this if any of the colorbuffers are enabled. */
7248 if (spi_format &
7249 ((1ull << (4 * (key->ps_epilog.states.last_cbuf + 1))) - 1))
7250 last_color_export = 0;
7251 } else {
7252 for (i = 0; i < 8; i++)
7253 if (colors_written & (1 << i) &&
7254 (spi_format >> (i * 4)) & 0xf)
7255 last_color_export = i;
7256 }
7257 }
7258
7259 while (colors_written) {
7260 LLVMValueRef color[4];
7261 int mrt = u_bit_scan(&colors_written);
7262
7263 for (i = 0; i < 4; i++)
7264 color[i] = LLVMGetParam(ctx->main_fn, vgpr++);
7265
7266 si_export_mrt_color(bld_base, color, mrt,
7267 fninfo.num_params - 1,
7268 mrt == last_color_export, &exp);
7269 }
7270
7271 /* Process depth, stencil, samplemask. */
7272 if (key->ps_epilog.writes_z)
7273 depth = LLVMGetParam(ctx->main_fn, vgpr++);
7274 if (key->ps_epilog.writes_stencil)
7275 stencil = LLVMGetParam(ctx->main_fn, vgpr++);
7276 if (key->ps_epilog.writes_samplemask)
7277 samplemask = LLVMGetParam(ctx->main_fn, vgpr++);
7278
7279 if (depth || stencil || samplemask)
7280 si_export_mrt_z(bld_base, depth, stencil, samplemask, &exp);
7281 else if (last_color_export == -1)
7282 si_export_null(bld_base);
7283
7284 if (exp.num)
7285 si_emit_ps_exports(ctx, &exp);
7286
7287 /* Compile. */
7288 LLVMBuildRetVoid(gallivm->builder);
7289 }
7290
7291 /**
7292 * Select and compile (or reuse) pixel shader parts (prolog & epilog).
7293 */
7294 static bool si_shader_select_ps_parts(struct si_screen *sscreen,
7295 LLVMTargetMachineRef tm,
7296 struct si_shader *shader,
7297 struct pipe_debug_callback *debug)
7298 {
7299 union si_shader_part_key prolog_key;
7300 union si_shader_part_key epilog_key;
7301
7302 /* Get the prolog. */
7303 si_get_ps_prolog_key(shader, &prolog_key, true);
7304
7305 /* The prolog is a no-op if these aren't set. */
7306 if (si_need_ps_prolog(&prolog_key)) {
7307 shader->prolog =
7308 si_get_shader_part(sscreen, &sscreen->ps_prologs,
7309 PIPE_SHADER_FRAGMENT, true,
7310 &prolog_key, tm, debug,
7311 si_build_ps_prolog_function,
7312 "Fragment Shader Prolog");
7313 if (!shader->prolog)
7314 return false;
7315 }
7316
7317 /* Get the epilog. */
7318 si_get_ps_epilog_key(shader, &epilog_key);
7319
7320 shader->epilog =
7321 si_get_shader_part(sscreen, &sscreen->ps_epilogs,
7322 PIPE_SHADER_FRAGMENT, false,
7323 &epilog_key, tm, debug,
7324 si_build_ps_epilog_function,
7325 "Fragment Shader Epilog");
7326 if (!shader->epilog)
7327 return false;
7328
7329 /* Enable POS_FIXED_PT if polygon stippling is enabled. */
7330 if (shader->key.part.ps.prolog.poly_stipple) {
7331 shader->config.spi_ps_input_ena |= S_0286CC_POS_FIXED_PT_ENA(1);
7332 assert(G_0286CC_POS_FIXED_PT_ENA(shader->config.spi_ps_input_addr));
7333 }
7334
7335 /* Set up the enable bits for per-sample shading if needed. */
7336 if (shader->key.part.ps.prolog.force_persp_sample_interp &&
7337 (G_0286CC_PERSP_CENTER_ENA(shader->config.spi_ps_input_ena) ||
7338 G_0286CC_PERSP_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
7339 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_CENTER_ENA;
7340 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_CENTROID_ENA;
7341 shader->config.spi_ps_input_ena |= S_0286CC_PERSP_SAMPLE_ENA(1);
7342 }
7343 if (shader->key.part.ps.prolog.force_linear_sample_interp &&
7344 (G_0286CC_LINEAR_CENTER_ENA(shader->config.spi_ps_input_ena) ||
7345 G_0286CC_LINEAR_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
7346 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_CENTER_ENA;
7347 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_CENTROID_ENA;
7348 shader->config.spi_ps_input_ena |= S_0286CC_LINEAR_SAMPLE_ENA(1);
7349 }
7350 if (shader->key.part.ps.prolog.force_persp_center_interp &&
7351 (G_0286CC_PERSP_SAMPLE_ENA(shader->config.spi_ps_input_ena) ||
7352 G_0286CC_PERSP_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
7353 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_SAMPLE_ENA;
7354 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_CENTROID_ENA;
7355 shader->config.spi_ps_input_ena |= S_0286CC_PERSP_CENTER_ENA(1);
7356 }
7357 if (shader->key.part.ps.prolog.force_linear_center_interp &&
7358 (G_0286CC_LINEAR_SAMPLE_ENA(shader->config.spi_ps_input_ena) ||
7359 G_0286CC_LINEAR_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
7360 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_SAMPLE_ENA;
7361 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_CENTROID_ENA;
7362 shader->config.spi_ps_input_ena |= S_0286CC_LINEAR_CENTER_ENA(1);
7363 }
7364
7365 /* POW_W_FLOAT requires that one of the perspective weights is enabled. */
7366 if (G_0286CC_POS_W_FLOAT_ENA(shader->config.spi_ps_input_ena) &&
7367 !(shader->config.spi_ps_input_ena & 0xf)) {
7368 shader->config.spi_ps_input_ena |= S_0286CC_PERSP_CENTER_ENA(1);
7369 assert(G_0286CC_PERSP_CENTER_ENA(shader->config.spi_ps_input_addr));
7370 }
7371
7372 /* At least one pair of interpolation weights must be enabled. */
7373 if (!(shader->config.spi_ps_input_ena & 0x7f)) {
7374 shader->config.spi_ps_input_ena |= S_0286CC_LINEAR_CENTER_ENA(1);
7375 assert(G_0286CC_LINEAR_CENTER_ENA(shader->config.spi_ps_input_addr));
7376 }
7377
7378 /* The sample mask input is always enabled, because the API shader always
7379 * passes it through to the epilog. Disable it here if it's unused.
7380 */
7381 if (!shader->key.part.ps.epilog.poly_line_smoothing &&
7382 !shader->selector->info.reads_samplemask)
7383 shader->config.spi_ps_input_ena &= C_0286CC_SAMPLE_COVERAGE_ENA;
7384
7385 return true;
7386 }
7387
7388 void si_multiwave_lds_size_workaround(struct si_screen *sscreen,
7389 unsigned *lds_size)
7390 {
7391 /* SPI barrier management bug:
7392 * Make sure we have at least 4k of LDS in use to avoid the bug.
7393 * It applies to workgroup sizes of more than one wavefront.
7394 */
7395 if (sscreen->b.family == CHIP_BONAIRE ||
7396 sscreen->b.family == CHIP_KABINI ||
7397 sscreen->b.family == CHIP_MULLINS)
7398 *lds_size = MAX2(*lds_size, 8);
7399 }
7400
7401 static void si_fix_resource_usage(struct si_screen *sscreen,
7402 struct si_shader *shader)
7403 {
7404 unsigned min_sgprs = shader->info.num_input_sgprs + 2; /* VCC */
7405
7406 shader->config.num_sgprs = MAX2(shader->config.num_sgprs, min_sgprs);
7407
7408 if (shader->selector->type == PIPE_SHADER_COMPUTE &&
7409 si_get_max_workgroup_size(shader) > 64) {
7410 si_multiwave_lds_size_workaround(sscreen,
7411 &shader->config.lds_size);
7412 }
7413 }
7414
7415 int si_shader_create(struct si_screen *sscreen, LLVMTargetMachineRef tm,
7416 struct si_shader *shader,
7417 struct pipe_debug_callback *debug)
7418 {
7419 struct si_shader_selector *sel = shader->selector;
7420 struct si_shader *mainp = *si_get_main_shader_part(sel, &shader->key);
7421 int r;
7422
7423 /* LS, ES, VS are compiled on demand if the main part hasn't been
7424 * compiled for that stage.
7425 *
7426 * Vertex shaders are compiled on demand when a vertex fetch
7427 * workaround must be applied.
7428 */
7429 if (shader->is_monolithic) {
7430 /* Monolithic shader (compiled as a whole, has many variants,
7431 * may take a long time to compile).
7432 */
7433 r = si_compile_tgsi_shader(sscreen, tm, shader, true, debug);
7434 if (r)
7435 return r;
7436 } else {
7437 /* The shader consists of several parts:
7438 *
7439 * - the middle part is the user shader, it has 1 variant only
7440 * and it was compiled during the creation of the shader
7441 * selector
7442 * - the prolog part is inserted at the beginning
7443 * - the epilog part is inserted at the end
7444 *
7445 * The prolog and epilog have many (but simple) variants.
7446 *
7447 * Starting with gfx9, geometry and tessellation control
7448 * shaders also contain the prolog and user shader parts of
7449 * the previous shader stage.
7450 */
7451
7452 if (!mainp)
7453 return -1;
7454
7455 /* Copy the compiled TGSI shader data over. */
7456 shader->is_binary_shared = true;
7457 shader->binary = mainp->binary;
7458 shader->config = mainp->config;
7459 shader->info.num_input_sgprs = mainp->info.num_input_sgprs;
7460 shader->info.num_input_vgprs = mainp->info.num_input_vgprs;
7461 shader->info.face_vgpr_index = mainp->info.face_vgpr_index;
7462 memcpy(shader->info.vs_output_param_offset,
7463 mainp->info.vs_output_param_offset,
7464 sizeof(mainp->info.vs_output_param_offset));
7465 shader->info.uses_instanceid = mainp->info.uses_instanceid;
7466 shader->info.nr_pos_exports = mainp->info.nr_pos_exports;
7467 shader->info.nr_param_exports = mainp->info.nr_param_exports;
7468
7469 /* Select prologs and/or epilogs. */
7470 switch (sel->type) {
7471 case PIPE_SHADER_VERTEX:
7472 if (!si_shader_select_vs_parts(sscreen, tm, shader, debug))
7473 return -1;
7474 break;
7475 case PIPE_SHADER_TESS_CTRL:
7476 if (!si_shader_select_tcs_parts(sscreen, tm, shader, debug))
7477 return -1;
7478 break;
7479 case PIPE_SHADER_TESS_EVAL:
7480 break;
7481 case PIPE_SHADER_GEOMETRY:
7482 if (!si_shader_select_gs_parts(sscreen, tm, shader, debug))
7483 return -1;
7484 break;
7485 case PIPE_SHADER_FRAGMENT:
7486 if (!si_shader_select_ps_parts(sscreen, tm, shader, debug))
7487 return -1;
7488
7489 /* Make sure we have at least as many VGPRs as there
7490 * are allocated inputs.
7491 */
7492 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
7493 shader->info.num_input_vgprs);
7494 break;
7495 }
7496
7497 /* Update SGPR and VGPR counts. */
7498 if (shader->prolog) {
7499 shader->config.num_sgprs = MAX2(shader->config.num_sgprs,
7500 shader->prolog->config.num_sgprs);
7501 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
7502 shader->prolog->config.num_vgprs);
7503 }
7504 if (shader->previous_stage) {
7505 shader->config.num_sgprs = MAX2(shader->config.num_sgprs,
7506 shader->previous_stage->config.num_sgprs);
7507 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
7508 shader->previous_stage->config.num_vgprs);
7509 shader->config.spilled_sgprs =
7510 MAX2(shader->config.spilled_sgprs,
7511 shader->previous_stage->config.spilled_sgprs);
7512 shader->config.spilled_vgprs =
7513 MAX2(shader->config.spilled_vgprs,
7514 shader->previous_stage->config.spilled_vgprs);
7515 shader->config.private_mem_vgprs =
7516 MAX2(shader->config.private_mem_vgprs,
7517 shader->previous_stage->config.private_mem_vgprs);
7518 shader->config.scratch_bytes_per_wave =
7519 MAX2(shader->config.scratch_bytes_per_wave,
7520 shader->previous_stage->config.scratch_bytes_per_wave);
7521 shader->info.uses_instanceid |=
7522 shader->previous_stage->info.uses_instanceid;
7523 }
7524 if (shader->prolog2) {
7525 shader->config.num_sgprs = MAX2(shader->config.num_sgprs,
7526 shader->prolog2->config.num_sgprs);
7527 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
7528 shader->prolog2->config.num_vgprs);
7529 }
7530 if (shader->epilog) {
7531 shader->config.num_sgprs = MAX2(shader->config.num_sgprs,
7532 shader->epilog->config.num_sgprs);
7533 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
7534 shader->epilog->config.num_vgprs);
7535 }
7536 }
7537
7538 si_fix_resource_usage(sscreen, shader);
7539 si_shader_dump(sscreen, shader, debug, sel->info.processor,
7540 stderr, true);
7541
7542 /* Upload. */
7543 r = si_shader_binary_upload(sscreen, shader);
7544 if (r) {
7545 fprintf(stderr, "LLVM failed to upload shader\n");
7546 return r;
7547 }
7548
7549 return 0;
7550 }
7551
7552 void si_shader_destroy(struct si_shader *shader)
7553 {
7554 if (shader->scratch_bo)
7555 r600_resource_reference(&shader->scratch_bo, NULL);
7556
7557 r600_resource_reference(&shader->bo, NULL);
7558
7559 if (!shader->is_binary_shared)
7560 radeon_shader_binary_clean(&shader->binary);
7561
7562 free(shader->shader_log);
7563 }