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radeonsi: link ES-GS just like LS-HS
[mesa.git] / src / gallium / drivers / radeonsi / si_shader.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Tom Stellard <thomas.stellard@amd.com>
25 * Michel Dänzer <michel.daenzer@amd.com>
26 * Christian König <christian.koenig@amd.com>
27 */
28
29 #include "gallivm/lp_bld_const.h"
30 #include "gallivm/lp_bld_gather.h"
31 #include "gallivm/lp_bld_intr.h"
32 #include "gallivm/lp_bld_logic.h"
33 #include "gallivm/lp_bld_arit.h"
34 #include "gallivm/lp_bld_bitarit.h"
35 #include "gallivm/lp_bld_flow.h"
36 #include "radeon/r600_cs.h"
37 #include "radeon/radeon_llvm.h"
38 #include "radeon/radeon_elf_util.h"
39 #include "radeon/radeon_llvm_emit.h"
40 #include "util/u_memory.h"
41 #include "util/u_pstipple.h"
42 #include "tgsi/tgsi_parse.h"
43 #include "tgsi/tgsi_util.h"
44 #include "tgsi/tgsi_dump.h"
45
46 #include "si_pipe.h"
47 #include "si_shader.h"
48 #include "sid.h"
49
50 #include <errno.h>
51
52 static const char *scratch_rsrc_dword0_symbol =
53 "SCRATCH_RSRC_DWORD0";
54
55 static const char *scratch_rsrc_dword1_symbol =
56 "SCRATCH_RSRC_DWORD1";
57
58 struct si_shader_output_values
59 {
60 LLVMValueRef values[4];
61 unsigned name;
62 unsigned sid;
63 };
64
65 struct si_shader_context
66 {
67 struct radeon_llvm_context radeon_bld;
68 struct si_shader *shader;
69 struct si_screen *screen;
70 unsigned type; /* TGSI_PROCESSOR_* specifies the type of shader. */
71 int param_streamout_config;
72 int param_streamout_write_index;
73 int param_streamout_offset[4];
74 int param_vertex_id;
75 int param_rel_auto_id;
76 int param_vs_prim_id;
77 int param_instance_id;
78 int param_tes_u;
79 int param_tes_v;
80 int param_tes_rel_patch_id;
81 int param_tes_patch_id;
82 int param_es2gs_offset;
83 LLVMTargetMachineRef tm;
84 LLVMValueRef const_md;
85 LLVMValueRef const_resource[SI_NUM_CONST_BUFFERS];
86 LLVMValueRef lds;
87 LLVMValueRef *constants[SI_NUM_CONST_BUFFERS];
88 LLVMValueRef resources[SI_NUM_SAMPLER_VIEWS];
89 LLVMValueRef samplers[SI_NUM_SAMPLER_STATES];
90 LLVMValueRef so_buffers[4];
91 LLVMValueRef esgs_ring;
92 LLVMValueRef gsvs_ring[4];
93 LLVMValueRef gs_next_vertex[4];
94 };
95
96 static struct si_shader_context * si_shader_context(
97 struct lp_build_tgsi_context * bld_base)
98 {
99 return (struct si_shader_context *)bld_base;
100 }
101
102
103 #define PERSPECTIVE_BASE 0
104 #define LINEAR_BASE 9
105
106 #define SAMPLE_OFFSET 0
107 #define CENTER_OFFSET 2
108 #define CENTROID_OFSET 4
109
110 #define USE_SGPR_MAX_SUFFIX_LEN 5
111 #define CONST_ADDR_SPACE 2
112 #define LOCAL_ADDR_SPACE 3
113 #define USER_SGPR_ADDR_SPACE 8
114
115
116 #define SENDMSG_GS 2
117 #define SENDMSG_GS_DONE 3
118
119 #define SENDMSG_GS_OP_NOP (0 << 4)
120 #define SENDMSG_GS_OP_CUT (1 << 4)
121 #define SENDMSG_GS_OP_EMIT (2 << 4)
122 #define SENDMSG_GS_OP_EMIT_CUT (3 << 4)
123
124 /**
125 * Returns a unique index for a semantic name and index. The index must be
126 * less than 64, so that a 64-bit bitmask of used inputs or outputs can be
127 * calculated.
128 */
129 unsigned si_shader_io_get_unique_index(unsigned semantic_name, unsigned index)
130 {
131 switch (semantic_name) {
132 case TGSI_SEMANTIC_POSITION:
133 return 0;
134 case TGSI_SEMANTIC_PSIZE:
135 return 1;
136 case TGSI_SEMANTIC_CLIPDIST:
137 assert(index <= 1);
138 return 2 + index;
139 case TGSI_SEMANTIC_GENERIC:
140 if (index <= 63-4)
141 return 4 + index;
142 else
143 /* same explanation as in the default statement,
144 * the only user hitting this is st/nine.
145 */
146 return 0;
147
148 /* patch indices are completely separate and thus start from 0 */
149 case TGSI_SEMANTIC_TESSOUTER:
150 return 0;
151 case TGSI_SEMANTIC_TESSINNER:
152 return 1;
153 case TGSI_SEMANTIC_PATCH:
154 return 2 + index;
155
156 default:
157 /* Don't fail here. The result of this function is only used
158 * for LS, TCS, TES, and GS, where legacy GL semantics can't
159 * occur, but this function is called for all vertex shaders
160 * before it's known whether LS will be compiled or not.
161 */
162 return 0;
163 }
164 }
165
166 /**
167 * Given a semantic name and index of a parameter and a mask of used parameters
168 * (inputs or outputs), return the index of the parameter in the list of all
169 * used parameters.
170 *
171 * For example, assume this list of parameters:
172 * POSITION, PSIZE, GENERIC0, GENERIC2
173 * which has the mask:
174 * 11000000000101
175 * Then:
176 * querying POSITION returns 0,
177 * querying PSIZE returns 1,
178 * querying GENERIC0 returns 2,
179 * querying GENERIC2 returns 3.
180 *
181 * Which can be used as an offset to a parameter buffer in units of vec4s.
182 */
183 static int get_param_index(unsigned semantic_name, unsigned index,
184 uint64_t mask)
185 {
186 unsigned unique_index = si_shader_io_get_unique_index(semantic_name, index);
187 int i, param_index = 0;
188
189 /* If not present... */
190 if (!((1llu << unique_index) & mask))
191 return -1;
192
193 for (i = 0; mask; i++) {
194 uint64_t bit = 1llu << i;
195
196 if (bit & mask) {
197 if (i == unique_index)
198 return param_index;
199
200 mask &= ~bit;
201 param_index++;
202 }
203 }
204
205 assert(!"unreachable");
206 return -1;
207 }
208
209 /**
210 * Get the value of a shader input parameter and extract a bitfield.
211 */
212 static LLVMValueRef unpack_param(struct si_shader_context *si_shader_ctx,
213 unsigned param, unsigned rshift,
214 unsigned bitwidth)
215 {
216 struct gallivm_state *gallivm = &si_shader_ctx->radeon_bld.gallivm;
217 LLVMValueRef value = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
218 param);
219
220 if (rshift)
221 value = LLVMBuildLShr(gallivm->builder, value,
222 lp_build_const_int32(gallivm, rshift), "");
223
224 if (rshift + bitwidth < 32) {
225 unsigned mask = (1 << bitwidth) - 1;
226 value = LLVMBuildAnd(gallivm->builder, value,
227 lp_build_const_int32(gallivm, mask), "");
228 }
229
230 return value;
231 }
232
233 static LLVMValueRef get_rel_patch_id(struct si_shader_context *si_shader_ctx)
234 {
235 switch (si_shader_ctx->type) {
236 case TGSI_PROCESSOR_TESS_CTRL:
237 return unpack_param(si_shader_ctx, SI_PARAM_REL_IDS, 0, 8);
238
239 case TGSI_PROCESSOR_TESS_EVAL:
240 return LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
241 si_shader_ctx->param_tes_rel_patch_id);
242
243 default:
244 assert(0);
245 return NULL;
246 }
247 }
248
249 /* Tessellation shaders pass outputs to the next shader using LDS.
250 *
251 * LS outputs = TCS inputs
252 * TCS outputs = TES inputs
253 *
254 * The LDS layout is:
255 * - TCS inputs for patch 0
256 * - TCS inputs for patch 1
257 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
258 * - ...
259 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
260 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
261 * - TCS outputs for patch 1
262 * - Per-patch TCS outputs for patch 1
263 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
264 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
265 * - ...
266 *
267 * All three shaders VS(LS), TCS, TES share the same LDS space.
268 */
269
270 static LLVMValueRef
271 get_tcs_in_patch_stride(struct si_shader_context *si_shader_ctx)
272 {
273 if (si_shader_ctx->type == TGSI_PROCESSOR_VERTEX)
274 return unpack_param(si_shader_ctx, SI_PARAM_LS_OUT_LAYOUT, 0, 13);
275 else if (si_shader_ctx->type == TGSI_PROCESSOR_TESS_CTRL)
276 return unpack_param(si_shader_ctx, SI_PARAM_TCS_IN_LAYOUT, 0, 13);
277 else {
278 assert(0);
279 return NULL;
280 }
281 }
282
283 static LLVMValueRef
284 get_tcs_out_patch_stride(struct si_shader_context *si_shader_ctx)
285 {
286 return unpack_param(si_shader_ctx, SI_PARAM_TCS_OUT_LAYOUT, 0, 13);
287 }
288
289 static LLVMValueRef
290 get_tcs_out_patch0_offset(struct si_shader_context *si_shader_ctx)
291 {
292 return lp_build_mul_imm(&si_shader_ctx->radeon_bld.soa.bld_base.uint_bld,
293 unpack_param(si_shader_ctx,
294 SI_PARAM_TCS_OUT_OFFSETS,
295 0, 16),
296 4);
297 }
298
299 static LLVMValueRef
300 get_tcs_out_patch0_patch_data_offset(struct si_shader_context *si_shader_ctx)
301 {
302 return lp_build_mul_imm(&si_shader_ctx->radeon_bld.soa.bld_base.uint_bld,
303 unpack_param(si_shader_ctx,
304 SI_PARAM_TCS_OUT_OFFSETS,
305 16, 16),
306 4);
307 }
308
309 static LLVMValueRef
310 get_tcs_in_current_patch_offset(struct si_shader_context *si_shader_ctx)
311 {
312 struct gallivm_state *gallivm = &si_shader_ctx->radeon_bld.gallivm;
313 LLVMValueRef patch_stride = get_tcs_in_patch_stride(si_shader_ctx);
314 LLVMValueRef rel_patch_id = get_rel_patch_id(si_shader_ctx);
315
316 return LLVMBuildMul(gallivm->builder, patch_stride, rel_patch_id, "");
317 }
318
319 static LLVMValueRef
320 get_tcs_out_current_patch_offset(struct si_shader_context *si_shader_ctx)
321 {
322 struct gallivm_state *gallivm = &si_shader_ctx->radeon_bld.gallivm;
323 LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(si_shader_ctx);
324 LLVMValueRef patch_stride = get_tcs_out_patch_stride(si_shader_ctx);
325 LLVMValueRef rel_patch_id = get_rel_patch_id(si_shader_ctx);
326
327 return LLVMBuildAdd(gallivm->builder, patch0_offset,
328 LLVMBuildMul(gallivm->builder, patch_stride,
329 rel_patch_id, ""),
330 "");
331 }
332
333 static LLVMValueRef
334 get_tcs_out_current_patch_data_offset(struct si_shader_context *si_shader_ctx)
335 {
336 struct gallivm_state *gallivm = &si_shader_ctx->radeon_bld.gallivm;
337 LLVMValueRef patch0_patch_data_offset =
338 get_tcs_out_patch0_patch_data_offset(si_shader_ctx);
339 LLVMValueRef patch_stride = get_tcs_out_patch_stride(si_shader_ctx);
340 LLVMValueRef rel_patch_id = get_rel_patch_id(si_shader_ctx);
341
342 return LLVMBuildAdd(gallivm->builder, patch0_patch_data_offset,
343 LLVMBuildMul(gallivm->builder, patch_stride,
344 rel_patch_id, ""),
345 "");
346 }
347
348 static void build_indexed_store(struct si_shader_context *si_shader_ctx,
349 LLVMValueRef base_ptr, LLVMValueRef index,
350 LLVMValueRef value)
351 {
352 struct lp_build_tgsi_context *bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
353 struct gallivm_state *gallivm = bld_base->base.gallivm;
354 LLVMValueRef indices[2], pointer;
355
356 indices[0] = bld_base->uint_bld.zero;
357 indices[1] = index;
358
359 pointer = LLVMBuildGEP(gallivm->builder, base_ptr, indices, 2, "");
360 LLVMBuildStore(gallivm->builder, value, pointer);
361 }
362
363 /**
364 * Build an LLVM bytecode indexed load using LLVMBuildGEP + LLVMBuildLoad.
365 * It's equivalent to doing a load from &base_ptr[index].
366 *
367 * \param base_ptr Where the array starts.
368 * \param index The element index into the array.
369 */
370 static LLVMValueRef build_indexed_load(struct si_shader_context *si_shader_ctx,
371 LLVMValueRef base_ptr, LLVMValueRef index)
372 {
373 struct lp_build_tgsi_context *bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
374 struct gallivm_state *gallivm = bld_base->base.gallivm;
375 LLVMValueRef indices[2], pointer;
376
377 indices[0] = bld_base->uint_bld.zero;
378 indices[1] = index;
379
380 pointer = LLVMBuildGEP(gallivm->builder, base_ptr, indices, 2, "");
381 return LLVMBuildLoad(gallivm->builder, pointer, "");
382 }
383
384 /**
385 * Do a load from &base_ptr[index], but also add a flag that it's loading
386 * a constant.
387 */
388 static LLVMValueRef build_indexed_load_const(
389 struct si_shader_context * si_shader_ctx,
390 LLVMValueRef base_ptr, LLVMValueRef index)
391 {
392 LLVMValueRef result = build_indexed_load(si_shader_ctx, base_ptr, index);
393 LLVMSetMetadata(result, 1, si_shader_ctx->const_md);
394 return result;
395 }
396
397 static LLVMValueRef get_instance_index_for_fetch(
398 struct radeon_llvm_context * radeon_bld,
399 unsigned divisor)
400 {
401 struct si_shader_context *si_shader_ctx =
402 si_shader_context(&radeon_bld->soa.bld_base);
403 struct gallivm_state * gallivm = radeon_bld->soa.bld_base.base.gallivm;
404
405 LLVMValueRef result = LLVMGetParam(radeon_bld->main_fn,
406 si_shader_ctx->param_instance_id);
407
408 /* The division must be done before START_INSTANCE is added. */
409 if (divisor > 1)
410 result = LLVMBuildUDiv(gallivm->builder, result,
411 lp_build_const_int32(gallivm, divisor), "");
412
413 return LLVMBuildAdd(gallivm->builder, result, LLVMGetParam(
414 radeon_bld->main_fn, SI_PARAM_START_INSTANCE), "");
415 }
416
417 static void declare_input_vs(
418 struct radeon_llvm_context *radeon_bld,
419 unsigned input_index,
420 const struct tgsi_full_declaration *decl)
421 {
422 struct lp_build_context *base = &radeon_bld->soa.bld_base.base;
423 struct gallivm_state *gallivm = base->gallivm;
424 struct si_shader_context *si_shader_ctx =
425 si_shader_context(&radeon_bld->soa.bld_base);
426 unsigned divisor = si_shader_ctx->shader->key.vs.instance_divisors[input_index];
427
428 unsigned chan;
429
430 LLVMValueRef t_list_ptr;
431 LLVMValueRef t_offset;
432 LLVMValueRef t_list;
433 LLVMValueRef attribute_offset;
434 LLVMValueRef buffer_index;
435 LLVMValueRef args[3];
436 LLVMTypeRef vec4_type;
437 LLVMValueRef input;
438
439 /* Load the T list */
440 t_list_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_VERTEX_BUFFER);
441
442 t_offset = lp_build_const_int32(gallivm, input_index);
443
444 t_list = build_indexed_load_const(si_shader_ctx, t_list_ptr, t_offset);
445
446 /* Build the attribute offset */
447 attribute_offset = lp_build_const_int32(gallivm, 0);
448
449 if (divisor) {
450 /* Build index from instance ID, start instance and divisor */
451 si_shader_ctx->shader->uses_instanceid = true;
452 buffer_index = get_instance_index_for_fetch(&si_shader_ctx->radeon_bld, divisor);
453 } else {
454 /* Load the buffer index for vertices. */
455 LLVMValueRef vertex_id = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
456 si_shader_ctx->param_vertex_id);
457 LLVMValueRef base_vertex = LLVMGetParam(radeon_bld->main_fn,
458 SI_PARAM_BASE_VERTEX);
459 buffer_index = LLVMBuildAdd(gallivm->builder, base_vertex, vertex_id, "");
460 }
461
462 vec4_type = LLVMVectorType(base->elem_type, 4);
463 args[0] = t_list;
464 args[1] = attribute_offset;
465 args[2] = buffer_index;
466 input = lp_build_intrinsic(gallivm->builder,
467 "llvm.SI.vs.load.input", vec4_type, args, 3,
468 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
469
470 /* Break up the vec4 into individual components */
471 for (chan = 0; chan < 4; chan++) {
472 LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan);
473 /* XXX: Use a helper function for this. There is one in
474 * tgsi_llvm.c. */
475 si_shader_ctx->radeon_bld.inputs[radeon_llvm_reg_index_soa(input_index, chan)] =
476 LLVMBuildExtractElement(gallivm->builder,
477 input, llvm_chan, "");
478 }
479 }
480
481 static LLVMValueRef get_primitive_id(struct lp_build_tgsi_context *bld_base,
482 unsigned swizzle)
483 {
484 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
485
486 if (swizzle > 0)
487 return bld_base->uint_bld.zero;
488
489 switch (si_shader_ctx->type) {
490 case TGSI_PROCESSOR_VERTEX:
491 return LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
492 si_shader_ctx->param_vs_prim_id);
493 case TGSI_PROCESSOR_TESS_CTRL:
494 return LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
495 SI_PARAM_PATCH_ID);
496 case TGSI_PROCESSOR_TESS_EVAL:
497 return LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
498 si_shader_ctx->param_tes_patch_id);
499 case TGSI_PROCESSOR_GEOMETRY:
500 return LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
501 SI_PARAM_PRIMITIVE_ID);
502 default:
503 assert(0);
504 return bld_base->uint_bld.zero;
505 }
506 }
507
508 /**
509 * Return the value of tgsi_ind_register for indexing.
510 * This is the indirect index with the constant offset added to it.
511 */
512 static LLVMValueRef get_indirect_index(struct si_shader_context *si_shader_ctx,
513 const struct tgsi_ind_register *ind,
514 int rel_index)
515 {
516 struct gallivm_state *gallivm = si_shader_ctx->radeon_bld.soa.bld_base.base.gallivm;
517 LLVMValueRef result;
518
519 result = si_shader_ctx->radeon_bld.soa.addr[ind->Index][ind->Swizzle];
520 result = LLVMBuildLoad(gallivm->builder, result, "");
521 result = LLVMBuildAdd(gallivm->builder, result,
522 lp_build_const_int32(gallivm, rel_index), "");
523 return result;
524 }
525
526 /**
527 * Calculate a dword address given an input or output register and a stride.
528 */
529 static LLVMValueRef get_dw_address(struct si_shader_context *si_shader_ctx,
530 const struct tgsi_full_dst_register *dst,
531 const struct tgsi_full_src_register *src,
532 LLVMValueRef vertex_dw_stride,
533 LLVMValueRef base_addr)
534 {
535 struct gallivm_state *gallivm = si_shader_ctx->radeon_bld.soa.bld_base.base.gallivm;
536 struct tgsi_shader_info *info = &si_shader_ctx->shader->selector->info;
537 ubyte *name, *index, *array_first;
538 int first, param;
539 struct tgsi_full_dst_register reg;
540
541 /* Set the register description. The address computation is the same
542 * for sources and destinations. */
543 if (src) {
544 reg.Register.File = src->Register.File;
545 reg.Register.Index = src->Register.Index;
546 reg.Register.Indirect = src->Register.Indirect;
547 reg.Register.Dimension = src->Register.Dimension;
548 reg.Indirect = src->Indirect;
549 reg.Dimension = src->Dimension;
550 reg.DimIndirect = src->DimIndirect;
551 } else
552 reg = *dst;
553
554 /* If the register is 2-dimensional (e.g. an array of vertices
555 * in a primitive), calculate the base address of the vertex. */
556 if (reg.Register.Dimension) {
557 LLVMValueRef index;
558
559 if (reg.Dimension.Indirect)
560 index = get_indirect_index(si_shader_ctx, &reg.DimIndirect,
561 reg.Dimension.Index);
562 else
563 index = lp_build_const_int32(gallivm, reg.Dimension.Index);
564
565 base_addr = LLVMBuildAdd(gallivm->builder, base_addr,
566 LLVMBuildMul(gallivm->builder, index,
567 vertex_dw_stride, ""), "");
568 }
569
570 /* Get information about the register. */
571 if (reg.Register.File == TGSI_FILE_INPUT) {
572 name = info->input_semantic_name;
573 index = info->input_semantic_index;
574 array_first = info->input_array_first;
575 } else if (reg.Register.File == TGSI_FILE_OUTPUT) {
576 name = info->output_semantic_name;
577 index = info->output_semantic_index;
578 array_first = info->output_array_first;
579 } else {
580 assert(0);
581 return NULL;
582 }
583
584 if (reg.Register.Indirect) {
585 /* Add the relative address of the element. */
586 LLVMValueRef ind_index;
587
588 if (reg.Indirect.ArrayID)
589 first = array_first[reg.Indirect.ArrayID];
590 else
591 first = reg.Register.Index;
592
593 ind_index = get_indirect_index(si_shader_ctx, &reg.Indirect,
594 reg.Register.Index - first);
595
596 base_addr = LLVMBuildAdd(gallivm->builder, base_addr,
597 LLVMBuildMul(gallivm->builder, ind_index,
598 lp_build_const_int32(gallivm, 4), ""), "");
599
600 param = si_shader_io_get_unique_index(name[first], index[first]);
601 } else {
602 param = si_shader_io_get_unique_index(name[reg.Register.Index],
603 index[reg.Register.Index]);
604 }
605
606 /* Add the base address of the element. */
607 return LLVMBuildAdd(gallivm->builder, base_addr,
608 lp_build_const_int32(gallivm, param * 4), "");
609 }
610
611 /**
612 * Load from LDS.
613 *
614 * \param type output value type
615 * \param swizzle offset (typically 0..3); it can be ~0, which loads a vec4
616 * \param dw_addr address in dwords
617 */
618 static LLVMValueRef lds_load(struct lp_build_tgsi_context *bld_base,
619 enum tgsi_opcode_type type, unsigned swizzle,
620 LLVMValueRef dw_addr)
621 {
622 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
623 struct gallivm_state *gallivm = bld_base->base.gallivm;
624 LLVMValueRef value;
625
626 if (swizzle == ~0) {
627 LLVMValueRef values[TGSI_NUM_CHANNELS];
628
629 for (unsigned chan = 0; chan < TGSI_NUM_CHANNELS; chan++)
630 values[chan] = lds_load(bld_base, type, chan, dw_addr);
631
632 return lp_build_gather_values(bld_base->base.gallivm, values,
633 TGSI_NUM_CHANNELS);
634 }
635
636 dw_addr = lp_build_add(&bld_base->uint_bld, dw_addr,
637 lp_build_const_int32(gallivm, swizzle));
638
639 value = build_indexed_load(si_shader_ctx, si_shader_ctx->lds, dw_addr);
640 return LLVMBuildBitCast(gallivm->builder, value,
641 tgsi2llvmtype(bld_base, type), "");
642 }
643
644 /**
645 * Store to LDS.
646 *
647 * \param swizzle offset (typically 0..3)
648 * \param dw_addr address in dwords
649 * \param value value to store
650 */
651 static void lds_store(struct lp_build_tgsi_context * bld_base,
652 unsigned swizzle, LLVMValueRef dw_addr,
653 LLVMValueRef value)
654 {
655 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
656 struct gallivm_state *gallivm = bld_base->base.gallivm;
657
658 dw_addr = lp_build_add(&bld_base->uint_bld, dw_addr,
659 lp_build_const_int32(gallivm, swizzle));
660
661 value = LLVMBuildBitCast(gallivm->builder, value,
662 LLVMInt32TypeInContext(gallivm->context), "");
663 build_indexed_store(si_shader_ctx, si_shader_ctx->lds,
664 dw_addr, value);
665 }
666
667 static LLVMValueRef fetch_input_tcs(
668 struct lp_build_tgsi_context *bld_base,
669 const struct tgsi_full_src_register *reg,
670 enum tgsi_opcode_type type, unsigned swizzle)
671 {
672 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
673 LLVMValueRef dw_addr, stride;
674
675 stride = unpack_param(si_shader_ctx, SI_PARAM_TCS_IN_LAYOUT, 13, 8);
676 dw_addr = get_tcs_in_current_patch_offset(si_shader_ctx);
677 dw_addr = get_dw_address(si_shader_ctx, NULL, reg, stride, dw_addr);
678
679 return lds_load(bld_base, type, swizzle, dw_addr);
680 }
681
682 static LLVMValueRef fetch_output_tcs(
683 struct lp_build_tgsi_context *bld_base,
684 const struct tgsi_full_src_register *reg,
685 enum tgsi_opcode_type type, unsigned swizzle)
686 {
687 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
688 LLVMValueRef dw_addr, stride;
689
690 if (reg->Register.Dimension) {
691 stride = unpack_param(si_shader_ctx, SI_PARAM_TCS_OUT_LAYOUT, 13, 8);
692 dw_addr = get_tcs_out_current_patch_offset(si_shader_ctx);
693 dw_addr = get_dw_address(si_shader_ctx, NULL, reg, stride, dw_addr);
694 } else {
695 dw_addr = get_tcs_out_current_patch_data_offset(si_shader_ctx);
696 dw_addr = get_dw_address(si_shader_ctx, NULL, reg, NULL, dw_addr);
697 }
698
699 return lds_load(bld_base, type, swizzle, dw_addr);
700 }
701
702 static LLVMValueRef fetch_input_tes(
703 struct lp_build_tgsi_context *bld_base,
704 const struct tgsi_full_src_register *reg,
705 enum tgsi_opcode_type type, unsigned swizzle)
706 {
707 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
708 LLVMValueRef dw_addr, stride;
709
710 if (reg->Register.Dimension) {
711 stride = unpack_param(si_shader_ctx, SI_PARAM_TCS_OUT_LAYOUT, 13, 8);
712 dw_addr = get_tcs_out_current_patch_offset(si_shader_ctx);
713 dw_addr = get_dw_address(si_shader_ctx, NULL, reg, stride, dw_addr);
714 } else {
715 dw_addr = get_tcs_out_current_patch_data_offset(si_shader_ctx);
716 dw_addr = get_dw_address(si_shader_ctx, NULL, reg, NULL, dw_addr);
717 }
718
719 return lds_load(bld_base, type, swizzle, dw_addr);
720 }
721
722 static void store_output_tcs(struct lp_build_tgsi_context * bld_base,
723 const struct tgsi_full_instruction * inst,
724 const struct tgsi_opcode_info * info,
725 LLVMValueRef dst[4])
726 {
727 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
728 const struct tgsi_full_dst_register *reg = &inst->Dst[0];
729 unsigned chan_index;
730 LLVMValueRef dw_addr, stride;
731
732 /* Only handle per-patch and per-vertex outputs here.
733 * Vectors will be lowered to scalars and this function will be called again.
734 */
735 if (reg->Register.File != TGSI_FILE_OUTPUT ||
736 (dst[0] && LLVMGetTypeKind(LLVMTypeOf(dst[0])) == LLVMVectorTypeKind)) {
737 radeon_llvm_emit_store(bld_base, inst, info, dst);
738 return;
739 }
740
741 if (reg->Register.Dimension) {
742 stride = unpack_param(si_shader_ctx, SI_PARAM_TCS_OUT_LAYOUT, 13, 8);
743 dw_addr = get_tcs_out_current_patch_offset(si_shader_ctx);
744 dw_addr = get_dw_address(si_shader_ctx, reg, NULL, stride, dw_addr);
745 } else {
746 dw_addr = get_tcs_out_current_patch_data_offset(si_shader_ctx);
747 dw_addr = get_dw_address(si_shader_ctx, reg, NULL, NULL, dw_addr);
748 }
749
750 TGSI_FOR_EACH_DST0_ENABLED_CHANNEL(inst, chan_index) {
751 LLVMValueRef value = dst[chan_index];
752
753 if (inst->Instruction.Saturate)
754 value = radeon_llvm_saturate(bld_base, value);
755
756 lds_store(bld_base, chan_index, dw_addr, value);
757 }
758 }
759
760 static LLVMValueRef fetch_input_gs(
761 struct lp_build_tgsi_context *bld_base,
762 const struct tgsi_full_src_register *reg,
763 enum tgsi_opcode_type type,
764 unsigned swizzle)
765 {
766 struct lp_build_context *base = &bld_base->base;
767 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
768 struct si_shader *shader = si_shader_ctx->shader;
769 struct lp_build_context *uint = &si_shader_ctx->radeon_bld.soa.bld_base.uint_bld;
770 struct gallivm_state *gallivm = base->gallivm;
771 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
772 LLVMValueRef vtx_offset;
773 LLVMValueRef args[9];
774 unsigned vtx_offset_param;
775 struct tgsi_shader_info *info = &shader->selector->info;
776 unsigned semantic_name = info->input_semantic_name[reg->Register.Index];
777 unsigned semantic_index = info->input_semantic_index[reg->Register.Index];
778 unsigned param;
779
780 if (swizzle != ~0 && semantic_name == TGSI_SEMANTIC_PRIMID)
781 return get_primitive_id(bld_base, swizzle);
782
783 if (!reg->Register.Dimension)
784 return NULL;
785
786 if (swizzle == ~0) {
787 LLVMValueRef values[TGSI_NUM_CHANNELS];
788 unsigned chan;
789 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
790 values[chan] = fetch_input_gs(bld_base, reg, type, chan);
791 }
792 return lp_build_gather_values(bld_base->base.gallivm, values,
793 TGSI_NUM_CHANNELS);
794 }
795
796 /* Get the vertex offset parameter */
797 vtx_offset_param = reg->Dimension.Index;
798 if (vtx_offset_param < 2) {
799 vtx_offset_param += SI_PARAM_VTX0_OFFSET;
800 } else {
801 assert(vtx_offset_param < 6);
802 vtx_offset_param += SI_PARAM_VTX2_OFFSET - 2;
803 }
804 vtx_offset = lp_build_mul_imm(uint,
805 LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
806 vtx_offset_param),
807 4);
808
809 param = si_shader_io_get_unique_index(semantic_name, semantic_index);
810 args[0] = si_shader_ctx->esgs_ring;
811 args[1] = vtx_offset;
812 args[2] = lp_build_const_int32(gallivm, (param * 4 + swizzle) * 256);
813 args[3] = uint->zero;
814 args[4] = uint->one; /* OFFEN */
815 args[5] = uint->zero; /* IDXEN */
816 args[6] = uint->one; /* GLC */
817 args[7] = uint->zero; /* SLC */
818 args[8] = uint->zero; /* TFE */
819
820 return LLVMBuildBitCast(gallivm->builder,
821 lp_build_intrinsic(gallivm->builder,
822 "llvm.SI.buffer.load.dword.i32.i32",
823 i32, args, 9,
824 LLVMReadOnlyAttribute | LLVMNoUnwindAttribute),
825 tgsi2llvmtype(bld_base, type), "");
826 }
827
828 static int lookup_interp_param_index(unsigned interpolate, unsigned location)
829 {
830 switch (interpolate) {
831 case TGSI_INTERPOLATE_CONSTANT:
832 return 0;
833
834 case TGSI_INTERPOLATE_LINEAR:
835 if (location == TGSI_INTERPOLATE_LOC_SAMPLE)
836 return SI_PARAM_LINEAR_SAMPLE;
837 else if (location == TGSI_INTERPOLATE_LOC_CENTROID)
838 return SI_PARAM_LINEAR_CENTROID;
839 else
840 return SI_PARAM_LINEAR_CENTER;
841 break;
842 case TGSI_INTERPOLATE_COLOR:
843 case TGSI_INTERPOLATE_PERSPECTIVE:
844 if (location == TGSI_INTERPOLATE_LOC_SAMPLE)
845 return SI_PARAM_PERSP_SAMPLE;
846 else if (location == TGSI_INTERPOLATE_LOC_CENTROID)
847 return SI_PARAM_PERSP_CENTROID;
848 else
849 return SI_PARAM_PERSP_CENTER;
850 break;
851 default:
852 fprintf(stderr, "Warning: Unhandled interpolation mode.\n");
853 return -1;
854 }
855 }
856
857 /* This shouldn't be used by explicit INTERP opcodes. */
858 static LLVMValueRef get_interp_param(struct si_shader_context *si_shader_ctx,
859 unsigned param)
860 {
861 struct gallivm_state *gallivm = &si_shader_ctx->radeon_bld.gallivm;
862 unsigned sample_param = 0;
863 LLVMValueRef default_ij, sample_ij, force_sample;
864
865 default_ij = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, param);
866
867 /* If the shader doesn't use center/centroid, just return the parameter.
868 *
869 * If the shader only uses one set of (i,j), "si_emit_spi_ps_input" can
870 * switch between center/centroid and sample without shader changes.
871 */
872 switch (param) {
873 case SI_PARAM_PERSP_CENTROID:
874 case SI_PARAM_PERSP_CENTER:
875 if (!si_shader_ctx->shader->selector->forces_persample_interp_for_persp)
876 return default_ij;
877
878 sample_param = SI_PARAM_PERSP_SAMPLE;
879 break;
880
881 case SI_PARAM_LINEAR_CENTROID:
882 case SI_PARAM_LINEAR_CENTER:
883 if (!si_shader_ctx->shader->selector->forces_persample_interp_for_linear)
884 return default_ij;
885
886 sample_param = SI_PARAM_LINEAR_SAMPLE;
887 break;
888
889 default:
890 return default_ij;
891 }
892
893 /* Otherwise, we have to select (i,j) based on a user data SGPR. */
894 sample_ij = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, sample_param);
895
896 /* TODO: this can be done more efficiently by switching between
897 * 2 prologs.
898 */
899 force_sample = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
900 SI_PARAM_PS_STATE_BITS);
901 force_sample = LLVMBuildTrunc(gallivm->builder, force_sample,
902 LLVMInt1TypeInContext(gallivm->context), "");
903 return LLVMBuildSelect(gallivm->builder, force_sample,
904 sample_ij, default_ij, "");
905 }
906
907 static void declare_input_fs(
908 struct radeon_llvm_context *radeon_bld,
909 unsigned input_index,
910 const struct tgsi_full_declaration *decl)
911 {
912 struct lp_build_context *base = &radeon_bld->soa.bld_base.base;
913 struct si_shader_context *si_shader_ctx =
914 si_shader_context(&radeon_bld->soa.bld_base);
915 struct si_shader *shader = si_shader_ctx->shader;
916 struct lp_build_context *uint = &radeon_bld->soa.bld_base.uint_bld;
917 struct gallivm_state *gallivm = base->gallivm;
918 LLVMTypeRef input_type = LLVMFloatTypeInContext(gallivm->context);
919 LLVMValueRef main_fn = radeon_bld->main_fn;
920
921 LLVMValueRef interp_param = NULL;
922 int interp_param_idx;
923 const char * intr_name;
924
925 /* This value is:
926 * [15:0] NewPrimMask (Bit mask for each quad. It is set it the
927 * quad begins a new primitive. Bit 0 always needs
928 * to be unset)
929 * [32:16] ParamOffset
930 *
931 */
932 LLVMValueRef params = LLVMGetParam(main_fn, SI_PARAM_PRIM_MASK);
933 LLVMValueRef attr_number;
934
935 unsigned chan;
936
937 if (decl->Semantic.Name == TGSI_SEMANTIC_POSITION) {
938 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
939 unsigned soa_index =
940 radeon_llvm_reg_index_soa(input_index, chan);
941 radeon_bld->inputs[soa_index] =
942 LLVMGetParam(main_fn, SI_PARAM_POS_X_FLOAT + chan);
943
944 if (chan == 3)
945 /* RCP for fragcoord.w */
946 radeon_bld->inputs[soa_index] =
947 LLVMBuildFDiv(gallivm->builder,
948 lp_build_const_float(gallivm, 1.0f),
949 radeon_bld->inputs[soa_index],
950 "");
951 }
952 return;
953 }
954
955 if (decl->Semantic.Name == TGSI_SEMANTIC_FACE) {
956 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 0)] =
957 LLVMGetParam(main_fn, SI_PARAM_FRONT_FACE);
958 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 1)] =
959 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 2)] =
960 lp_build_const_float(gallivm, 0.0f);
961 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 3)] =
962 lp_build_const_float(gallivm, 1.0f);
963
964 return;
965 }
966
967 shader->ps_input_param_offset[input_index] = shader->nparam++;
968 attr_number = lp_build_const_int32(gallivm,
969 shader->ps_input_param_offset[input_index]);
970
971 shader->ps_input_interpolate[input_index] = decl->Interp.Interpolate;
972 interp_param_idx = lookup_interp_param_index(decl->Interp.Interpolate,
973 decl->Interp.Location);
974 if (interp_param_idx == -1)
975 return;
976 else if (interp_param_idx)
977 interp_param = get_interp_param(si_shader_ctx, interp_param_idx);
978
979 /* fs.constant returns the param from the middle vertex, so it's not
980 * really useful for flat shading. It's meant to be used for custom
981 * interpolation (but the intrinsic can't fetch from the other two
982 * vertices).
983 *
984 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
985 * to do the right thing. The only reason we use fs.constant is that
986 * fs.interp cannot be used on integers, because they can be equal
987 * to NaN.
988 */
989 intr_name = interp_param ? "llvm.SI.fs.interp" : "llvm.SI.fs.constant";
990
991 if (decl->Semantic.Name == TGSI_SEMANTIC_COLOR &&
992 si_shader_ctx->shader->key.ps.color_two_side) {
993 LLVMValueRef args[4];
994 LLVMValueRef face, is_face_positive;
995 LLVMValueRef back_attr_number =
996 lp_build_const_int32(gallivm,
997 shader->ps_input_param_offset[input_index] + 1);
998
999 face = LLVMGetParam(main_fn, SI_PARAM_FRONT_FACE);
1000
1001 is_face_positive = LLVMBuildFCmp(gallivm->builder,
1002 LLVMRealOGT, face,
1003 lp_build_const_float(gallivm, 0.0f),
1004 "");
1005
1006 args[2] = params;
1007 args[3] = interp_param;
1008 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1009 LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan);
1010 unsigned soa_index = radeon_llvm_reg_index_soa(input_index, chan);
1011 LLVMValueRef front, back;
1012
1013 args[0] = llvm_chan;
1014 args[1] = attr_number;
1015 front = lp_build_intrinsic(gallivm->builder, intr_name,
1016 input_type, args, args[3] ? 4 : 3,
1017 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
1018
1019 args[1] = back_attr_number;
1020 back = lp_build_intrinsic(gallivm->builder, intr_name,
1021 input_type, args, args[3] ? 4 : 3,
1022 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
1023
1024 radeon_bld->inputs[soa_index] =
1025 LLVMBuildSelect(gallivm->builder,
1026 is_face_positive,
1027 front,
1028 back,
1029 "");
1030 }
1031
1032 shader->nparam++;
1033 } else if (decl->Semantic.Name == TGSI_SEMANTIC_FOG) {
1034 LLVMValueRef args[4];
1035
1036 args[0] = uint->zero;
1037 args[1] = attr_number;
1038 args[2] = params;
1039 args[3] = interp_param;
1040 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 0)] =
1041 lp_build_intrinsic(gallivm->builder, intr_name,
1042 input_type, args, args[3] ? 4 : 3,
1043 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
1044 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 1)] =
1045 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 2)] =
1046 lp_build_const_float(gallivm, 0.0f);
1047 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 3)] =
1048 lp_build_const_float(gallivm, 1.0f);
1049 } else {
1050 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1051 LLVMValueRef args[4];
1052 LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan);
1053 unsigned soa_index = radeon_llvm_reg_index_soa(input_index, chan);
1054 args[0] = llvm_chan;
1055 args[1] = attr_number;
1056 args[2] = params;
1057 args[3] = interp_param;
1058 radeon_bld->inputs[soa_index] =
1059 lp_build_intrinsic(gallivm->builder, intr_name,
1060 input_type, args, args[3] ? 4 : 3,
1061 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
1062 }
1063 }
1064 }
1065
1066 static LLVMValueRef get_sample_id(struct radeon_llvm_context *radeon_bld)
1067 {
1068 return unpack_param(si_shader_context(&radeon_bld->soa.bld_base),
1069 SI_PARAM_ANCILLARY, 8, 4);
1070 }
1071
1072 /**
1073 * Load a dword from a constant buffer.
1074 */
1075 static LLVMValueRef buffer_load_const(LLVMBuilderRef builder, LLVMValueRef resource,
1076 LLVMValueRef offset, LLVMTypeRef return_type)
1077 {
1078 LLVMValueRef args[2] = {resource, offset};
1079
1080 return lp_build_intrinsic(builder, "llvm.SI.load.const", return_type, args, 2,
1081 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
1082 }
1083
1084 static LLVMValueRef load_sample_position(struct radeon_llvm_context *radeon_bld, LLVMValueRef sample_id)
1085 {
1086 struct si_shader_context *si_shader_ctx =
1087 si_shader_context(&radeon_bld->soa.bld_base);
1088 struct lp_build_context *uint_bld = &radeon_bld->soa.bld_base.uint_bld;
1089 struct gallivm_state *gallivm = &radeon_bld->gallivm;
1090 LLVMBuilderRef builder = gallivm->builder;
1091 LLVMValueRef desc = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_CONST);
1092 LLVMValueRef buf_index = lp_build_const_int32(gallivm, SI_DRIVER_STATE_CONST_BUF);
1093 LLVMValueRef resource = build_indexed_load_const(si_shader_ctx, desc, buf_index);
1094
1095 /* offset = sample_id * 8 (8 = 2 floats containing samplepos.xy) */
1096 LLVMValueRef offset0 = lp_build_mul_imm(uint_bld, sample_id, 8);
1097 LLVMValueRef offset1 = LLVMBuildAdd(builder, offset0, lp_build_const_int32(gallivm, 4), "");
1098
1099 LLVMValueRef pos[4] = {
1100 buffer_load_const(builder, resource, offset0, radeon_bld->soa.bld_base.base.elem_type),
1101 buffer_load_const(builder, resource, offset1, radeon_bld->soa.bld_base.base.elem_type),
1102 lp_build_const_float(gallivm, 0),
1103 lp_build_const_float(gallivm, 0)
1104 };
1105
1106 return lp_build_gather_values(gallivm, pos, 4);
1107 }
1108
1109 static void declare_system_value(
1110 struct radeon_llvm_context * radeon_bld,
1111 unsigned index,
1112 const struct tgsi_full_declaration *decl)
1113 {
1114 struct si_shader_context *si_shader_ctx =
1115 si_shader_context(&radeon_bld->soa.bld_base);
1116 struct lp_build_context *bld = &radeon_bld->soa.bld_base.base;
1117 struct lp_build_context *uint_bld = &radeon_bld->soa.bld_base.uint_bld;
1118 struct gallivm_state *gallivm = &radeon_bld->gallivm;
1119 LLVMValueRef value = 0;
1120
1121 switch (decl->Semantic.Name) {
1122 case TGSI_SEMANTIC_INSTANCEID:
1123 value = LLVMGetParam(radeon_bld->main_fn,
1124 si_shader_ctx->param_instance_id);
1125 break;
1126
1127 case TGSI_SEMANTIC_VERTEXID:
1128 value = LLVMBuildAdd(gallivm->builder,
1129 LLVMGetParam(radeon_bld->main_fn,
1130 si_shader_ctx->param_vertex_id),
1131 LLVMGetParam(radeon_bld->main_fn,
1132 SI_PARAM_BASE_VERTEX), "");
1133 break;
1134
1135 case TGSI_SEMANTIC_VERTEXID_NOBASE:
1136 value = LLVMGetParam(radeon_bld->main_fn,
1137 si_shader_ctx->param_vertex_id);
1138 break;
1139
1140 case TGSI_SEMANTIC_BASEVERTEX:
1141 value = LLVMGetParam(radeon_bld->main_fn,
1142 SI_PARAM_BASE_VERTEX);
1143 break;
1144
1145 case TGSI_SEMANTIC_INVOCATIONID:
1146 if (si_shader_ctx->type == TGSI_PROCESSOR_TESS_CTRL)
1147 value = unpack_param(si_shader_ctx, SI_PARAM_REL_IDS, 8, 5);
1148 else if (si_shader_ctx->type == TGSI_PROCESSOR_GEOMETRY)
1149 value = LLVMGetParam(radeon_bld->main_fn,
1150 SI_PARAM_GS_INSTANCE_ID);
1151 else
1152 assert(!"INVOCATIONID not implemented");
1153 break;
1154
1155 case TGSI_SEMANTIC_SAMPLEID:
1156 value = get_sample_id(radeon_bld);
1157 break;
1158
1159 case TGSI_SEMANTIC_SAMPLEPOS:
1160 value = load_sample_position(radeon_bld, get_sample_id(radeon_bld));
1161 break;
1162
1163 case TGSI_SEMANTIC_SAMPLEMASK:
1164 /* Smoothing isn't MSAA in GL, but it's MSAA in hardware.
1165 * Therefore, force gl_SampleMaskIn to 1 for GL. */
1166 if (si_shader_ctx->shader->key.ps.poly_line_smoothing)
1167 value = uint_bld->one;
1168 else
1169 value = LLVMGetParam(radeon_bld->main_fn, SI_PARAM_SAMPLE_COVERAGE);
1170 break;
1171
1172 case TGSI_SEMANTIC_TESSCOORD:
1173 {
1174 LLVMValueRef coord[4] = {
1175 LLVMGetParam(radeon_bld->main_fn, si_shader_ctx->param_tes_u),
1176 LLVMGetParam(radeon_bld->main_fn, si_shader_ctx->param_tes_v),
1177 bld->zero,
1178 bld->zero
1179 };
1180
1181 /* For triangles, the vector should be (u, v, 1-u-v). */
1182 if (si_shader_ctx->shader->selector->info.properties[TGSI_PROPERTY_TES_PRIM_MODE] ==
1183 PIPE_PRIM_TRIANGLES)
1184 coord[2] = lp_build_sub(bld, bld->one,
1185 lp_build_add(bld, coord[0], coord[1]));
1186
1187 value = lp_build_gather_values(gallivm, coord, 4);
1188 break;
1189 }
1190
1191 case TGSI_SEMANTIC_VERTICESIN:
1192 value = unpack_param(si_shader_ctx, SI_PARAM_TCS_OUT_LAYOUT, 26, 6);
1193 break;
1194
1195 case TGSI_SEMANTIC_TESSINNER:
1196 case TGSI_SEMANTIC_TESSOUTER:
1197 {
1198 LLVMValueRef dw_addr;
1199 int param = si_shader_io_get_unique_index(decl->Semantic.Name, 0);
1200
1201 dw_addr = get_tcs_out_current_patch_data_offset(si_shader_ctx);
1202 dw_addr = LLVMBuildAdd(gallivm->builder, dw_addr,
1203 lp_build_const_int32(gallivm, param * 4), "");
1204
1205 value = lds_load(&radeon_bld->soa.bld_base, TGSI_TYPE_FLOAT,
1206 ~0, dw_addr);
1207 break;
1208 }
1209
1210 case TGSI_SEMANTIC_PRIMID:
1211 value = get_primitive_id(&radeon_bld->soa.bld_base, 0);
1212 break;
1213
1214 default:
1215 assert(!"unknown system value");
1216 return;
1217 }
1218
1219 radeon_bld->system_values[index] = value;
1220 }
1221
1222 static LLVMValueRef fetch_constant(
1223 struct lp_build_tgsi_context * bld_base,
1224 const struct tgsi_full_src_register *reg,
1225 enum tgsi_opcode_type type,
1226 unsigned swizzle)
1227 {
1228 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
1229 struct lp_build_context * base = &bld_base->base;
1230 const struct tgsi_ind_register *ireg = &reg->Indirect;
1231 unsigned buf, idx;
1232
1233 LLVMValueRef addr, bufp;
1234 LLVMValueRef result;
1235
1236 if (swizzle == LP_CHAN_ALL) {
1237 unsigned chan;
1238 LLVMValueRef values[4];
1239 for (chan = 0; chan < TGSI_NUM_CHANNELS; ++chan)
1240 values[chan] = fetch_constant(bld_base, reg, type, chan);
1241
1242 return lp_build_gather_values(bld_base->base.gallivm, values, 4);
1243 }
1244
1245 buf = reg->Register.Dimension ? reg->Dimension.Index : 0;
1246 idx = reg->Register.Index * 4 + swizzle;
1247
1248 if (!reg->Register.Indirect && !reg->Dimension.Indirect) {
1249 if (type != TGSI_TYPE_DOUBLE)
1250 return bitcast(bld_base, type, si_shader_ctx->constants[buf][idx]);
1251 else {
1252 return radeon_llvm_emit_fetch_double(bld_base,
1253 si_shader_ctx->constants[buf][idx],
1254 si_shader_ctx->constants[buf][idx + 1]);
1255 }
1256 }
1257
1258 if (reg->Register.Dimension && reg->Dimension.Indirect) {
1259 LLVMValueRef ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_CONST);
1260 LLVMValueRef index;
1261 index = get_indirect_index(si_shader_ctx, &reg->DimIndirect,
1262 reg->Dimension.Index);
1263 bufp = build_indexed_load_const(si_shader_ctx, ptr, index);
1264 } else
1265 bufp = si_shader_ctx->const_resource[buf];
1266
1267 addr = si_shader_ctx->radeon_bld.soa.addr[ireg->Index][ireg->Swizzle];
1268 addr = LLVMBuildLoad(base->gallivm->builder, addr, "load addr reg");
1269 addr = lp_build_mul_imm(&bld_base->uint_bld, addr, 16);
1270 addr = lp_build_add(&bld_base->uint_bld, addr,
1271 lp_build_const_int32(base->gallivm, idx * 4));
1272
1273 result = buffer_load_const(base->gallivm->builder, bufp,
1274 addr, bld_base->base.elem_type);
1275
1276 if (type != TGSI_TYPE_DOUBLE)
1277 result = bitcast(bld_base, type, result);
1278 else {
1279 LLVMValueRef addr2, result2;
1280 addr2 = si_shader_ctx->radeon_bld.soa.addr[ireg->Index][ireg->Swizzle + 1];
1281 addr2 = LLVMBuildLoad(base->gallivm->builder, addr2, "load addr reg2");
1282 addr2 = lp_build_mul_imm(&bld_base->uint_bld, addr2, 16);
1283 addr2 = lp_build_add(&bld_base->uint_bld, addr2,
1284 lp_build_const_int32(base->gallivm, idx * 4));
1285
1286 result2 = buffer_load_const(base->gallivm->builder, si_shader_ctx->const_resource[buf],
1287 addr2, bld_base->base.elem_type);
1288
1289 result = radeon_llvm_emit_fetch_double(bld_base,
1290 result, result2);
1291 }
1292 return result;
1293 }
1294
1295 /* Initialize arguments for the shader export intrinsic */
1296 static void si_llvm_init_export_args(struct lp_build_tgsi_context *bld_base,
1297 LLVMValueRef *values,
1298 unsigned target,
1299 LLVMValueRef *args)
1300 {
1301 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
1302 struct lp_build_context *uint =
1303 &si_shader_ctx->radeon_bld.soa.bld_base.uint_bld;
1304 struct lp_build_context *base = &bld_base->base;
1305 unsigned compressed = 0;
1306 unsigned chan;
1307
1308 /* XXX: This controls which components of the output
1309 * registers actually get exported. (e.g bit 0 means export
1310 * X component, bit 1 means export Y component, etc.) I'm
1311 * hard coding this to 0xf for now. In the future, we might
1312 * want to do something else.
1313 */
1314 args[0] = lp_build_const_int32(base->gallivm, 0xf);
1315
1316 /* Specify whether the EXEC mask represents the valid mask */
1317 args[1] = uint->zero;
1318
1319 /* Specify whether this is the last export */
1320 args[2] = uint->zero;
1321
1322 /* Specify the target we are exporting */
1323 args[3] = lp_build_const_int32(base->gallivm, target);
1324
1325 if (si_shader_ctx->type == TGSI_PROCESSOR_FRAGMENT) {
1326 int cbuf = target - V_008DFC_SQ_EXP_MRT;
1327
1328 if (cbuf >= 0 && cbuf < 8) {
1329 compressed = (si_shader_ctx->shader->key.ps.export_16bpc >> cbuf) & 0x1;
1330
1331 if (compressed)
1332 si_shader_ctx->shader->spi_shader_col_format |=
1333 V_028714_SPI_SHADER_FP16_ABGR << (4 * cbuf);
1334 else
1335 si_shader_ctx->shader->spi_shader_col_format |=
1336 V_028714_SPI_SHADER_32_ABGR << (4 * cbuf);
1337
1338 si_shader_ctx->shader->cb_shader_mask |= 0xf << (4 * cbuf);
1339 }
1340 }
1341
1342 /* Set COMPR flag */
1343 args[4] = compressed ? uint->one : uint->zero;
1344
1345 if (compressed) {
1346 /* Pixel shader needs to pack output values before export */
1347 for (chan = 0; chan < 2; chan++) {
1348 LLVMValueRef pack_args[2] = {
1349 values[2 * chan],
1350 values[2 * chan + 1]
1351 };
1352 LLVMValueRef packed;
1353
1354 packed = lp_build_intrinsic(base->gallivm->builder,
1355 "llvm.SI.packf16",
1356 LLVMInt32TypeInContext(base->gallivm->context),
1357 pack_args, 2,
1358 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
1359 args[chan + 7] = args[chan + 5] =
1360 LLVMBuildBitCast(base->gallivm->builder,
1361 packed,
1362 LLVMFloatTypeInContext(base->gallivm->context),
1363 "");
1364 }
1365 } else
1366 memcpy(&args[5], values, sizeof(values[0]) * 4);
1367 }
1368
1369 /* Load from output pointers and initialize arguments for the shader export intrinsic */
1370 static void si_llvm_init_export_args_load(struct lp_build_tgsi_context *bld_base,
1371 LLVMValueRef *out_ptr,
1372 unsigned target,
1373 LLVMValueRef *args)
1374 {
1375 struct gallivm_state *gallivm = bld_base->base.gallivm;
1376 LLVMValueRef values[4];
1377 int i;
1378
1379 for (i = 0; i < 4; i++)
1380 values[i] = LLVMBuildLoad(gallivm->builder, out_ptr[i], "");
1381
1382 si_llvm_init_export_args(bld_base, values, target, args);
1383 }
1384
1385 static void si_alpha_test(struct lp_build_tgsi_context *bld_base,
1386 LLVMValueRef alpha_ptr)
1387 {
1388 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
1389 struct gallivm_state *gallivm = bld_base->base.gallivm;
1390
1391 if (si_shader_ctx->shader->key.ps.alpha_func != PIPE_FUNC_NEVER) {
1392 LLVMValueRef alpha_ref = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
1393 SI_PARAM_ALPHA_REF);
1394
1395 LLVMValueRef alpha_pass =
1396 lp_build_cmp(&bld_base->base,
1397 si_shader_ctx->shader->key.ps.alpha_func,
1398 LLVMBuildLoad(gallivm->builder, alpha_ptr, ""),
1399 alpha_ref);
1400 LLVMValueRef arg =
1401 lp_build_select(&bld_base->base,
1402 alpha_pass,
1403 lp_build_const_float(gallivm, 1.0f),
1404 lp_build_const_float(gallivm, -1.0f));
1405
1406 lp_build_intrinsic(gallivm->builder,
1407 "llvm.AMDGPU.kill",
1408 LLVMVoidTypeInContext(gallivm->context),
1409 &arg, 1, 0);
1410 } else {
1411 lp_build_intrinsic(gallivm->builder,
1412 "llvm.AMDGPU.kilp",
1413 LLVMVoidTypeInContext(gallivm->context),
1414 NULL, 0, 0);
1415 }
1416
1417 si_shader_ctx->shader->db_shader_control |= S_02880C_KILL_ENABLE(1);
1418 }
1419
1420 static void si_scale_alpha_by_sample_mask(struct lp_build_tgsi_context *bld_base,
1421 LLVMValueRef alpha_ptr)
1422 {
1423 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
1424 struct gallivm_state *gallivm = bld_base->base.gallivm;
1425 LLVMValueRef coverage, alpha;
1426
1427 /* alpha = alpha * popcount(coverage) / SI_NUM_SMOOTH_AA_SAMPLES */
1428 coverage = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
1429 SI_PARAM_SAMPLE_COVERAGE);
1430 coverage = bitcast(bld_base, TGSI_TYPE_SIGNED, coverage);
1431
1432 coverage = lp_build_intrinsic(gallivm->builder, "llvm.ctpop.i32",
1433 bld_base->int_bld.elem_type,
1434 &coverage, 1, LLVMReadNoneAttribute);
1435
1436 coverage = LLVMBuildUIToFP(gallivm->builder, coverage,
1437 bld_base->base.elem_type, "");
1438
1439 coverage = LLVMBuildFMul(gallivm->builder, coverage,
1440 lp_build_const_float(gallivm,
1441 1.0 / SI_NUM_SMOOTH_AA_SAMPLES), "");
1442
1443 alpha = LLVMBuildLoad(gallivm->builder, alpha_ptr, "");
1444 alpha = LLVMBuildFMul(gallivm->builder, alpha, coverage, "");
1445 LLVMBuildStore(gallivm->builder, alpha, alpha_ptr);
1446 }
1447
1448 static void si_llvm_emit_clipvertex(struct lp_build_tgsi_context * bld_base,
1449 LLVMValueRef (*pos)[9], LLVMValueRef *out_elts)
1450 {
1451 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
1452 struct lp_build_context *base = &bld_base->base;
1453 struct lp_build_context *uint = &si_shader_ctx->radeon_bld.soa.bld_base.uint_bld;
1454 unsigned reg_index;
1455 unsigned chan;
1456 unsigned const_chan;
1457 LLVMValueRef base_elt;
1458 LLVMValueRef ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_CONST);
1459 LLVMValueRef constbuf_index = lp_build_const_int32(base->gallivm, SI_DRIVER_STATE_CONST_BUF);
1460 LLVMValueRef const_resource = build_indexed_load_const(si_shader_ctx, ptr, constbuf_index);
1461
1462 for (reg_index = 0; reg_index < 2; reg_index ++) {
1463 LLVMValueRef *args = pos[2 + reg_index];
1464
1465 args[5] =
1466 args[6] =
1467 args[7] =
1468 args[8] = lp_build_const_float(base->gallivm, 0.0f);
1469
1470 /* Compute dot products of position and user clip plane vectors */
1471 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1472 for (const_chan = 0; const_chan < TGSI_NUM_CHANNELS; const_chan++) {
1473 args[1] = lp_build_const_int32(base->gallivm,
1474 ((reg_index * 4 + chan) * 4 +
1475 const_chan) * 4);
1476 base_elt = buffer_load_const(base->gallivm->builder, const_resource,
1477 args[1], base->elem_type);
1478 args[5 + chan] =
1479 lp_build_add(base, args[5 + chan],
1480 lp_build_mul(base, base_elt,
1481 out_elts[const_chan]));
1482 }
1483 }
1484
1485 args[0] = lp_build_const_int32(base->gallivm, 0xf);
1486 args[1] = uint->zero;
1487 args[2] = uint->zero;
1488 args[3] = lp_build_const_int32(base->gallivm,
1489 V_008DFC_SQ_EXP_POS + 2 + reg_index);
1490 args[4] = uint->zero;
1491 }
1492 }
1493
1494 static void si_dump_streamout(struct pipe_stream_output_info *so)
1495 {
1496 unsigned i;
1497
1498 if (so->num_outputs)
1499 fprintf(stderr, "STREAMOUT\n");
1500
1501 for (i = 0; i < so->num_outputs; i++) {
1502 unsigned mask = ((1 << so->output[i].num_components) - 1) <<
1503 so->output[i].start_component;
1504 fprintf(stderr, " %i: BUF%i[%i..%i] <- OUT[%i].%s%s%s%s\n",
1505 i, so->output[i].output_buffer,
1506 so->output[i].dst_offset, so->output[i].dst_offset + so->output[i].num_components - 1,
1507 so->output[i].register_index,
1508 mask & 1 ? "x" : "",
1509 mask & 2 ? "y" : "",
1510 mask & 4 ? "z" : "",
1511 mask & 8 ? "w" : "");
1512 }
1513 }
1514
1515 /* TBUFFER_STORE_FORMAT_{X,XY,XYZ,XYZW} <- the suffix is selected by num_channels=1..4.
1516 * The type of vdata must be one of i32 (num_channels=1), v2i32 (num_channels=2),
1517 * or v4i32 (num_channels=3,4). */
1518 static void build_tbuffer_store(struct si_shader_context *shader,
1519 LLVMValueRef rsrc,
1520 LLVMValueRef vdata,
1521 unsigned num_channels,
1522 LLVMValueRef vaddr,
1523 LLVMValueRef soffset,
1524 unsigned inst_offset,
1525 unsigned dfmt,
1526 unsigned nfmt,
1527 unsigned offen,
1528 unsigned idxen,
1529 unsigned glc,
1530 unsigned slc,
1531 unsigned tfe)
1532 {
1533 struct gallivm_state *gallivm = &shader->radeon_bld.gallivm;
1534 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
1535 LLVMValueRef args[] = {
1536 rsrc,
1537 vdata,
1538 LLVMConstInt(i32, num_channels, 0),
1539 vaddr,
1540 soffset,
1541 LLVMConstInt(i32, inst_offset, 0),
1542 LLVMConstInt(i32, dfmt, 0),
1543 LLVMConstInt(i32, nfmt, 0),
1544 LLVMConstInt(i32, offen, 0),
1545 LLVMConstInt(i32, idxen, 0),
1546 LLVMConstInt(i32, glc, 0),
1547 LLVMConstInt(i32, slc, 0),
1548 LLVMConstInt(i32, tfe, 0)
1549 };
1550
1551 /* The instruction offset field has 12 bits */
1552 assert(offen || inst_offset < (1 << 12));
1553
1554 /* The intrinsic is overloaded, we need to add a type suffix for overloading to work. */
1555 unsigned func = CLAMP(num_channels, 1, 3) - 1;
1556 const char *types[] = {"i32", "v2i32", "v4i32"};
1557 char name[256];
1558 snprintf(name, sizeof(name), "llvm.SI.tbuffer.store.%s", types[func]);
1559
1560 lp_build_intrinsic(gallivm->builder, name,
1561 LLVMVoidTypeInContext(gallivm->context),
1562 args, Elements(args), 0);
1563 }
1564
1565 static void build_tbuffer_store_dwords(struct si_shader_context *shader,
1566 LLVMValueRef rsrc,
1567 LLVMValueRef vdata,
1568 unsigned num_channels,
1569 LLVMValueRef vaddr,
1570 LLVMValueRef soffset,
1571 unsigned inst_offset)
1572 {
1573 static unsigned dfmt[] = {
1574 V_008F0C_BUF_DATA_FORMAT_32,
1575 V_008F0C_BUF_DATA_FORMAT_32_32,
1576 V_008F0C_BUF_DATA_FORMAT_32_32_32,
1577 V_008F0C_BUF_DATA_FORMAT_32_32_32_32
1578 };
1579 assert(num_channels >= 1 && num_channels <= 4);
1580
1581 build_tbuffer_store(shader, rsrc, vdata, num_channels, vaddr, soffset,
1582 inst_offset, dfmt[num_channels-1],
1583 V_008F0C_BUF_NUM_FORMAT_UINT, 1, 0, 1, 1, 0);
1584 }
1585
1586 /* On SI, the vertex shader is responsible for writing streamout data
1587 * to buffers. */
1588 static void si_llvm_emit_streamout(struct si_shader_context *shader,
1589 struct si_shader_output_values *outputs,
1590 unsigned noutput)
1591 {
1592 struct pipe_stream_output_info *so = &shader->shader->selector->so;
1593 struct gallivm_state *gallivm = &shader->radeon_bld.gallivm;
1594 LLVMBuilderRef builder = gallivm->builder;
1595 int i, j;
1596 struct lp_build_if_state if_ctx;
1597
1598 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
1599
1600 /* Get bits [22:16], i.e. (so_param >> 16) & 127; */
1601 LLVMValueRef so_vtx_count =
1602 unpack_param(shader, shader->param_streamout_config, 16, 7);
1603
1604 LLVMValueRef tid = lp_build_intrinsic(builder, "llvm.SI.tid", i32,
1605 NULL, 0, LLVMReadNoneAttribute);
1606
1607 /* can_emit = tid < so_vtx_count; */
1608 LLVMValueRef can_emit =
1609 LLVMBuildICmp(builder, LLVMIntULT, tid, so_vtx_count, "");
1610
1611 LLVMValueRef stream_id =
1612 unpack_param(shader, shader->param_streamout_config, 24, 2);
1613
1614 /* Emit the streamout code conditionally. This actually avoids
1615 * out-of-bounds buffer access. The hw tells us via the SGPR
1616 * (so_vtx_count) which threads are allowed to emit streamout data. */
1617 lp_build_if(&if_ctx, gallivm, can_emit);
1618 {
1619 /* The buffer offset is computed as follows:
1620 * ByteOffset = streamout_offset[buffer_id]*4 +
1621 * (streamout_write_index + thread_id)*stride[buffer_id] +
1622 * attrib_offset
1623 */
1624
1625 LLVMValueRef so_write_index =
1626 LLVMGetParam(shader->radeon_bld.main_fn,
1627 shader->param_streamout_write_index);
1628
1629 /* Compute (streamout_write_index + thread_id). */
1630 so_write_index = LLVMBuildAdd(builder, so_write_index, tid, "");
1631
1632 /* Compute the write offset for each enabled buffer. */
1633 LLVMValueRef so_write_offset[4] = {};
1634 for (i = 0; i < 4; i++) {
1635 if (!so->stride[i])
1636 continue;
1637
1638 LLVMValueRef so_offset = LLVMGetParam(shader->radeon_bld.main_fn,
1639 shader->param_streamout_offset[i]);
1640 so_offset = LLVMBuildMul(builder, so_offset, LLVMConstInt(i32, 4, 0), "");
1641
1642 so_write_offset[i] = LLVMBuildMul(builder, so_write_index,
1643 LLVMConstInt(i32, so->stride[i]*4, 0), "");
1644 so_write_offset[i] = LLVMBuildAdd(builder, so_write_offset[i], so_offset, "");
1645 }
1646
1647 /* Write streamout data. */
1648 for (i = 0; i < so->num_outputs; i++) {
1649 unsigned buf_idx = so->output[i].output_buffer;
1650 unsigned reg = so->output[i].register_index;
1651 unsigned start = so->output[i].start_component;
1652 unsigned num_comps = so->output[i].num_components;
1653 unsigned stream = so->output[i].stream;
1654 LLVMValueRef out[4];
1655 struct lp_build_if_state if_ctx_stream;
1656
1657 assert(num_comps && num_comps <= 4);
1658 if (!num_comps || num_comps > 4)
1659 continue;
1660
1661 if (reg >= noutput)
1662 continue;
1663
1664 /* Load the output as int. */
1665 for (j = 0; j < num_comps; j++) {
1666 out[j] = LLVMBuildBitCast(builder,
1667 outputs[reg].values[start+j],
1668 i32, "");
1669 }
1670
1671 /* Pack the output. */
1672 LLVMValueRef vdata = NULL;
1673
1674 switch (num_comps) {
1675 case 1: /* as i32 */
1676 vdata = out[0];
1677 break;
1678 case 2: /* as v2i32 */
1679 case 3: /* as v4i32 (aligned to 4) */
1680 case 4: /* as v4i32 */
1681 vdata = LLVMGetUndef(LLVMVectorType(i32, util_next_power_of_two(num_comps)));
1682 for (j = 0; j < num_comps; j++) {
1683 vdata = LLVMBuildInsertElement(builder, vdata, out[j],
1684 LLVMConstInt(i32, j, 0), "");
1685 }
1686 break;
1687 }
1688
1689 LLVMValueRef can_emit_stream =
1690 LLVMBuildICmp(builder, LLVMIntEQ,
1691 stream_id,
1692 lp_build_const_int32(gallivm, stream), "");
1693
1694 lp_build_if(&if_ctx_stream, gallivm, can_emit_stream);
1695 build_tbuffer_store_dwords(shader, shader->so_buffers[buf_idx],
1696 vdata, num_comps,
1697 so_write_offset[buf_idx],
1698 LLVMConstInt(i32, 0, 0),
1699 so->output[i].dst_offset*4);
1700 lp_build_endif(&if_ctx_stream);
1701 }
1702 }
1703 lp_build_endif(&if_ctx);
1704 }
1705
1706
1707 /* Generate export instructions for hardware VS shader stage */
1708 static void si_llvm_export_vs(struct lp_build_tgsi_context *bld_base,
1709 struct si_shader_output_values *outputs,
1710 unsigned noutput)
1711 {
1712 struct si_shader_context * si_shader_ctx = si_shader_context(bld_base);
1713 struct si_shader * shader = si_shader_ctx->shader;
1714 struct lp_build_context * base = &bld_base->base;
1715 struct lp_build_context * uint =
1716 &si_shader_ctx->radeon_bld.soa.bld_base.uint_bld;
1717 LLVMValueRef args[9];
1718 LLVMValueRef pos_args[4][9] = { { 0 } };
1719 LLVMValueRef psize_value = NULL, edgeflag_value = NULL, layer_value = NULL, viewport_index_value = NULL;
1720 unsigned semantic_name, semantic_index;
1721 unsigned target;
1722 unsigned param_count = 0;
1723 unsigned pos_idx;
1724 int i;
1725
1726 if (outputs && si_shader_ctx->shader->selector->so.num_outputs) {
1727 si_llvm_emit_streamout(si_shader_ctx, outputs, noutput);
1728 }
1729
1730 for (i = 0; i < noutput; i++) {
1731 semantic_name = outputs[i].name;
1732 semantic_index = outputs[i].sid;
1733
1734 handle_semantic:
1735 /* Select the correct target */
1736 switch(semantic_name) {
1737 case TGSI_SEMANTIC_PSIZE:
1738 psize_value = outputs[i].values[0];
1739 continue;
1740 case TGSI_SEMANTIC_EDGEFLAG:
1741 edgeflag_value = outputs[i].values[0];
1742 continue;
1743 case TGSI_SEMANTIC_LAYER:
1744 layer_value = outputs[i].values[0];
1745 semantic_name = TGSI_SEMANTIC_GENERIC;
1746 goto handle_semantic;
1747 case TGSI_SEMANTIC_VIEWPORT_INDEX:
1748 viewport_index_value = outputs[i].values[0];
1749 semantic_name = TGSI_SEMANTIC_GENERIC;
1750 goto handle_semantic;
1751 case TGSI_SEMANTIC_POSITION:
1752 target = V_008DFC_SQ_EXP_POS;
1753 break;
1754 case TGSI_SEMANTIC_COLOR:
1755 case TGSI_SEMANTIC_BCOLOR:
1756 target = V_008DFC_SQ_EXP_PARAM + param_count;
1757 shader->vs_output_param_offset[i] = param_count;
1758 param_count++;
1759 break;
1760 case TGSI_SEMANTIC_CLIPDIST:
1761 target = V_008DFC_SQ_EXP_POS + 2 + semantic_index;
1762 break;
1763 case TGSI_SEMANTIC_CLIPVERTEX:
1764 si_llvm_emit_clipvertex(bld_base, pos_args, outputs[i].values);
1765 continue;
1766 case TGSI_SEMANTIC_PRIMID:
1767 case TGSI_SEMANTIC_FOG:
1768 case TGSI_SEMANTIC_TEXCOORD:
1769 case TGSI_SEMANTIC_GENERIC:
1770 target = V_008DFC_SQ_EXP_PARAM + param_count;
1771 shader->vs_output_param_offset[i] = param_count;
1772 param_count++;
1773 break;
1774 default:
1775 target = 0;
1776 fprintf(stderr,
1777 "Warning: SI unhandled vs output type:%d\n",
1778 semantic_name);
1779 }
1780
1781 si_llvm_init_export_args(bld_base, outputs[i].values, target, args);
1782
1783 if (target >= V_008DFC_SQ_EXP_POS &&
1784 target <= (V_008DFC_SQ_EXP_POS + 3)) {
1785 memcpy(pos_args[target - V_008DFC_SQ_EXP_POS],
1786 args, sizeof(args));
1787 } else {
1788 lp_build_intrinsic(base->gallivm->builder,
1789 "llvm.SI.export",
1790 LLVMVoidTypeInContext(base->gallivm->context),
1791 args, 9, 0);
1792 }
1793
1794 if (semantic_name == TGSI_SEMANTIC_CLIPDIST) {
1795 semantic_name = TGSI_SEMANTIC_GENERIC;
1796 goto handle_semantic;
1797 }
1798 }
1799
1800 shader->nr_param_exports = param_count;
1801
1802 /* We need to add the position output manually if it's missing. */
1803 if (!pos_args[0][0]) {
1804 pos_args[0][0] = lp_build_const_int32(base->gallivm, 0xf); /* writemask */
1805 pos_args[0][1] = uint->zero; /* EXEC mask */
1806 pos_args[0][2] = uint->zero; /* last export? */
1807 pos_args[0][3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_POS);
1808 pos_args[0][4] = uint->zero; /* COMPR flag */
1809 pos_args[0][5] = base->zero; /* X */
1810 pos_args[0][6] = base->zero; /* Y */
1811 pos_args[0][7] = base->zero; /* Z */
1812 pos_args[0][8] = base->one; /* W */
1813 }
1814
1815 /* Write the misc vector (point size, edgeflag, layer, viewport). */
1816 if (shader->selector->info.writes_psize ||
1817 shader->selector->info.writes_edgeflag ||
1818 shader->selector->info.writes_viewport_index ||
1819 shader->selector->info.writes_layer) {
1820 pos_args[1][0] = lp_build_const_int32(base->gallivm, /* writemask */
1821 shader->selector->info.writes_psize |
1822 (shader->selector->info.writes_edgeflag << 1) |
1823 (shader->selector->info.writes_layer << 2) |
1824 (shader->selector->info.writes_viewport_index << 3));
1825 pos_args[1][1] = uint->zero; /* EXEC mask */
1826 pos_args[1][2] = uint->zero; /* last export? */
1827 pos_args[1][3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_POS + 1);
1828 pos_args[1][4] = uint->zero; /* COMPR flag */
1829 pos_args[1][5] = base->zero; /* X */
1830 pos_args[1][6] = base->zero; /* Y */
1831 pos_args[1][7] = base->zero; /* Z */
1832 pos_args[1][8] = base->zero; /* W */
1833
1834 if (shader->selector->info.writes_psize)
1835 pos_args[1][5] = psize_value;
1836
1837 if (shader->selector->info.writes_edgeflag) {
1838 /* The output is a float, but the hw expects an integer
1839 * with the first bit containing the edge flag. */
1840 edgeflag_value = LLVMBuildFPToUI(base->gallivm->builder,
1841 edgeflag_value,
1842 bld_base->uint_bld.elem_type, "");
1843 edgeflag_value = lp_build_min(&bld_base->int_bld,
1844 edgeflag_value,
1845 bld_base->int_bld.one);
1846
1847 /* The LLVM intrinsic expects a float. */
1848 pos_args[1][6] = LLVMBuildBitCast(base->gallivm->builder,
1849 edgeflag_value,
1850 base->elem_type, "");
1851 }
1852
1853 if (shader->selector->info.writes_layer)
1854 pos_args[1][7] = layer_value;
1855
1856 if (shader->selector->info.writes_viewport_index)
1857 pos_args[1][8] = viewport_index_value;
1858 }
1859
1860 for (i = 0; i < 4; i++)
1861 if (pos_args[i][0])
1862 shader->nr_pos_exports++;
1863
1864 pos_idx = 0;
1865 for (i = 0; i < 4; i++) {
1866 if (!pos_args[i][0])
1867 continue;
1868
1869 /* Specify the target we are exporting */
1870 pos_args[i][3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_POS + pos_idx++);
1871
1872 if (pos_idx == shader->nr_pos_exports)
1873 /* Specify that this is the last export */
1874 pos_args[i][2] = uint->one;
1875
1876 lp_build_intrinsic(base->gallivm->builder,
1877 "llvm.SI.export",
1878 LLVMVoidTypeInContext(base->gallivm->context),
1879 pos_args[i], 9, 0);
1880 }
1881 }
1882
1883 /* This only writes the tessellation factor levels. */
1884 static void si_llvm_emit_tcs_epilogue(struct lp_build_tgsi_context *bld_base)
1885 {
1886 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
1887 struct gallivm_state *gallivm = bld_base->base.gallivm;
1888 struct si_shader *shader = si_shader_ctx->shader;
1889 unsigned tess_inner_index, tess_outer_index;
1890 LLVMValueRef lds_base, lds_inner, lds_outer;
1891 LLVMValueRef tf_base, rel_patch_id, byteoffset, buffer, rw_buffers;
1892 LLVMValueRef out[6], vec0, vec1, invocation_id;
1893 unsigned stride, outer_comps, inner_comps, i;
1894 struct lp_build_if_state if_ctx;
1895
1896 invocation_id = unpack_param(si_shader_ctx, SI_PARAM_REL_IDS, 8, 5);
1897
1898 /* Do this only for invocation 0, because the tess levels are per-patch,
1899 * not per-vertex.
1900 *
1901 * This can't jump, because invocation 0 executes this. It should
1902 * at least mask out the loads and stores for other invocations.
1903 */
1904 lp_build_if(&if_ctx, gallivm,
1905 LLVMBuildICmp(gallivm->builder, LLVMIntEQ,
1906 invocation_id, bld_base->uint_bld.zero, ""));
1907
1908 /* Determine the layout of one tess factor element in the buffer. */
1909 switch (shader->key.tcs.prim_mode) {
1910 case PIPE_PRIM_LINES:
1911 stride = 2; /* 2 dwords, 1 vec2 store */
1912 outer_comps = 2;
1913 inner_comps = 0;
1914 break;
1915 case PIPE_PRIM_TRIANGLES:
1916 stride = 4; /* 4 dwords, 1 vec4 store */
1917 outer_comps = 3;
1918 inner_comps = 1;
1919 break;
1920 case PIPE_PRIM_QUADS:
1921 stride = 6; /* 6 dwords, 2 stores (vec4 + vec2) */
1922 outer_comps = 4;
1923 inner_comps = 2;
1924 break;
1925 default:
1926 assert(0);
1927 return;
1928 }
1929
1930 /* Load tess_inner and tess_outer from LDS.
1931 * Any invocation can write them, so we can't get them from a temporary.
1932 */
1933 tess_inner_index = si_shader_io_get_unique_index(TGSI_SEMANTIC_TESSINNER, 0);
1934 tess_outer_index = si_shader_io_get_unique_index(TGSI_SEMANTIC_TESSOUTER, 0);
1935
1936 lds_base = get_tcs_out_current_patch_data_offset(si_shader_ctx);
1937 lds_inner = LLVMBuildAdd(gallivm->builder, lds_base,
1938 lp_build_const_int32(gallivm,
1939 tess_inner_index * 4), "");
1940 lds_outer = LLVMBuildAdd(gallivm->builder, lds_base,
1941 lp_build_const_int32(gallivm,
1942 tess_outer_index * 4), "");
1943
1944 for (i = 0; i < outer_comps; i++)
1945 out[i] = lds_load(bld_base, TGSI_TYPE_SIGNED, i, lds_outer);
1946 for (i = 0; i < inner_comps; i++)
1947 out[outer_comps+i] = lds_load(bld_base, TGSI_TYPE_SIGNED, i, lds_inner);
1948
1949 /* Convert the outputs to vectors for stores. */
1950 vec0 = lp_build_gather_values(gallivm, out, MIN2(stride, 4));
1951 vec1 = NULL;
1952
1953 if (stride > 4)
1954 vec1 = lp_build_gather_values(gallivm, out+4, stride - 4);
1955
1956 /* Get the buffer. */
1957 rw_buffers = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
1958 SI_PARAM_RW_BUFFERS);
1959 buffer = build_indexed_load_const(si_shader_ctx, rw_buffers,
1960 lp_build_const_int32(gallivm, SI_RING_TESS_FACTOR));
1961
1962 /* Get the offset. */
1963 tf_base = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
1964 SI_PARAM_TESS_FACTOR_OFFSET);
1965 rel_patch_id = get_rel_patch_id(si_shader_ctx);
1966 byteoffset = LLVMBuildMul(gallivm->builder, rel_patch_id,
1967 lp_build_const_int32(gallivm, 4 * stride), "");
1968
1969 /* Store the outputs. */
1970 build_tbuffer_store_dwords(si_shader_ctx, buffer, vec0,
1971 MIN2(stride, 4), byteoffset, tf_base, 0);
1972 if (vec1)
1973 build_tbuffer_store_dwords(si_shader_ctx, buffer, vec1,
1974 stride - 4, byteoffset, tf_base, 16);
1975 lp_build_endif(&if_ctx);
1976 }
1977
1978 static void si_llvm_emit_ls_epilogue(struct lp_build_tgsi_context * bld_base)
1979 {
1980 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
1981 struct si_shader *shader = si_shader_ctx->shader;
1982 struct tgsi_shader_info *info = &shader->selector->info;
1983 struct gallivm_state *gallivm = bld_base->base.gallivm;
1984 unsigned i, chan;
1985 LLVMValueRef vertex_id = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
1986 si_shader_ctx->param_rel_auto_id);
1987 LLVMValueRef vertex_dw_stride =
1988 unpack_param(si_shader_ctx, SI_PARAM_LS_OUT_LAYOUT, 13, 8);
1989 LLVMValueRef base_dw_addr = LLVMBuildMul(gallivm->builder, vertex_id,
1990 vertex_dw_stride, "");
1991
1992 /* Write outputs to LDS. The next shader (TCS aka HS) will read
1993 * its inputs from it. */
1994 for (i = 0; i < info->num_outputs; i++) {
1995 LLVMValueRef *out_ptr = si_shader_ctx->radeon_bld.soa.outputs[i];
1996 unsigned name = info->output_semantic_name[i];
1997 unsigned index = info->output_semantic_index[i];
1998 int param = si_shader_io_get_unique_index(name, index);
1999 LLVMValueRef dw_addr = LLVMBuildAdd(gallivm->builder, base_dw_addr,
2000 lp_build_const_int32(gallivm, param * 4), "");
2001
2002 for (chan = 0; chan < 4; chan++) {
2003 lds_store(bld_base, chan, dw_addr,
2004 LLVMBuildLoad(gallivm->builder, out_ptr[chan], ""));
2005 }
2006 }
2007 }
2008
2009 static void si_llvm_emit_es_epilogue(struct lp_build_tgsi_context * bld_base)
2010 {
2011 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
2012 struct gallivm_state *gallivm = bld_base->base.gallivm;
2013 struct si_shader *es = si_shader_ctx->shader;
2014 struct tgsi_shader_info *info = &es->selector->info;
2015 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
2016 LLVMValueRef soffset = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
2017 si_shader_ctx->param_es2gs_offset);
2018 unsigned chan;
2019 int i;
2020
2021 for (i = 0; i < info->num_outputs; i++) {
2022 LLVMValueRef *out_ptr =
2023 si_shader_ctx->radeon_bld.soa.outputs[i];
2024 int param_index;
2025
2026 if (info->output_semantic_name[i] == TGSI_SEMANTIC_VIEWPORT_INDEX ||
2027 info->output_semantic_name[i] == TGSI_SEMANTIC_LAYER)
2028 continue;
2029
2030 param_index = si_shader_io_get_unique_index(info->output_semantic_name[i],
2031 info->output_semantic_index[i]);
2032
2033 for (chan = 0; chan < 4; chan++) {
2034 LLVMValueRef out_val = LLVMBuildLoad(gallivm->builder, out_ptr[chan], "");
2035 out_val = LLVMBuildBitCast(gallivm->builder, out_val, i32, "");
2036
2037 build_tbuffer_store(si_shader_ctx,
2038 si_shader_ctx->esgs_ring,
2039 out_val, 1,
2040 LLVMGetUndef(i32), soffset,
2041 (4 * param_index + chan) * 4,
2042 V_008F0C_BUF_DATA_FORMAT_32,
2043 V_008F0C_BUF_NUM_FORMAT_UINT,
2044 0, 0, 1, 1, 0);
2045 }
2046 }
2047 }
2048
2049 static void si_llvm_emit_gs_epilogue(struct lp_build_tgsi_context *bld_base)
2050 {
2051 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
2052 struct gallivm_state *gallivm = bld_base->base.gallivm;
2053 LLVMValueRef args[2];
2054
2055 args[0] = lp_build_const_int32(gallivm, SENDMSG_GS_OP_NOP | SENDMSG_GS_DONE);
2056 args[1] = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_GS_WAVE_ID);
2057 lp_build_intrinsic(gallivm->builder, "llvm.SI.sendmsg",
2058 LLVMVoidTypeInContext(gallivm->context), args, 2,
2059 LLVMNoUnwindAttribute);
2060 }
2061
2062 static void si_llvm_emit_vs_epilogue(struct lp_build_tgsi_context * bld_base)
2063 {
2064 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
2065 struct gallivm_state *gallivm = bld_base->base.gallivm;
2066 struct tgsi_shader_info *info = &si_shader_ctx->shader->selector->info;
2067 struct si_shader_output_values *outputs = NULL;
2068 int i,j;
2069
2070 outputs = MALLOC((info->num_outputs + 1) * sizeof(outputs[0]));
2071
2072 /* Vertex color clamping.
2073 *
2074 * This uses a state constant loaded in a user data SGPR and
2075 * an IF statement is added that clamps all colors if the constant
2076 * is true.
2077 */
2078 if (si_shader_ctx->type == TGSI_PROCESSOR_VERTEX &&
2079 !si_shader_ctx->shader->is_gs_copy_shader) {
2080 struct lp_build_if_state if_ctx;
2081 LLVMValueRef cond = NULL;
2082 LLVMValueRef addr, val;
2083
2084 for (i = 0; i < info->num_outputs; i++) {
2085 if (info->output_semantic_name[i] != TGSI_SEMANTIC_COLOR &&
2086 info->output_semantic_name[i] != TGSI_SEMANTIC_BCOLOR)
2087 continue;
2088
2089 /* We've found a color. */
2090 if (!cond) {
2091 /* The state is in the first bit of the user SGPR. */
2092 cond = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
2093 SI_PARAM_VS_STATE_BITS);
2094 cond = LLVMBuildTrunc(gallivm->builder, cond,
2095 LLVMInt1TypeInContext(gallivm->context), "");
2096 lp_build_if(&if_ctx, gallivm, cond);
2097 }
2098
2099 for (j = 0; j < 4; j++) {
2100 addr = si_shader_ctx->radeon_bld.soa.outputs[i][j];
2101 val = LLVMBuildLoad(gallivm->builder, addr, "");
2102 val = radeon_llvm_saturate(bld_base, val);
2103 LLVMBuildStore(gallivm->builder, val, addr);
2104 }
2105 }
2106
2107 if (cond)
2108 lp_build_endif(&if_ctx);
2109 }
2110
2111 for (i = 0; i < info->num_outputs; i++) {
2112 outputs[i].name = info->output_semantic_name[i];
2113 outputs[i].sid = info->output_semantic_index[i];
2114
2115 for (j = 0; j < 4; j++)
2116 outputs[i].values[j] =
2117 LLVMBuildLoad(gallivm->builder,
2118 si_shader_ctx->radeon_bld.soa.outputs[i][j],
2119 "");
2120 }
2121
2122 /* Export PrimitiveID when PS needs it. */
2123 if (si_vs_exports_prim_id(si_shader_ctx->shader)) {
2124 outputs[i].name = TGSI_SEMANTIC_PRIMID;
2125 outputs[i].sid = 0;
2126 outputs[i].values[0] = bitcast(bld_base, TGSI_TYPE_FLOAT,
2127 get_primitive_id(bld_base, 0));
2128 outputs[i].values[1] = bld_base->base.undef;
2129 outputs[i].values[2] = bld_base->base.undef;
2130 outputs[i].values[3] = bld_base->base.undef;
2131 i++;
2132 }
2133
2134 si_llvm_export_vs(bld_base, outputs, i);
2135 FREE(outputs);
2136 }
2137
2138 static void si_llvm_emit_fs_epilogue(struct lp_build_tgsi_context * bld_base)
2139 {
2140 struct si_shader_context * si_shader_ctx = si_shader_context(bld_base);
2141 struct si_shader * shader = si_shader_ctx->shader;
2142 struct lp_build_context * base = &bld_base->base;
2143 struct lp_build_context * uint = &bld_base->uint_bld;
2144 struct tgsi_shader_info *info = &shader->selector->info;
2145 LLVMBuilderRef builder = base->gallivm->builder;
2146 LLVMValueRef args[9];
2147 LLVMValueRef last_args[9] = { 0 };
2148 int depth_index = -1, stencil_index = -1, samplemask_index = -1;
2149 int i;
2150
2151 for (i = 0; i < info->num_outputs; i++) {
2152 unsigned semantic_name = info->output_semantic_name[i];
2153 unsigned semantic_index = info->output_semantic_index[i];
2154 unsigned target;
2155 LLVMValueRef alpha_ptr;
2156
2157 /* Select the correct target */
2158 switch (semantic_name) {
2159 case TGSI_SEMANTIC_POSITION:
2160 depth_index = i;
2161 continue;
2162 case TGSI_SEMANTIC_STENCIL:
2163 stencil_index = i;
2164 continue;
2165 case TGSI_SEMANTIC_SAMPLEMASK:
2166 samplemask_index = i;
2167 continue;
2168 case TGSI_SEMANTIC_COLOR:
2169 target = V_008DFC_SQ_EXP_MRT + semantic_index;
2170 alpha_ptr = si_shader_ctx->radeon_bld.soa.outputs[i][3];
2171
2172 if (si_shader_ctx->shader->key.ps.clamp_color) {
2173 for (int j = 0; j < 4; j++) {
2174 LLVMValueRef ptr = si_shader_ctx->radeon_bld.soa.outputs[i][j];
2175 LLVMValueRef result = LLVMBuildLoad(builder, ptr, "");
2176
2177 result = radeon_llvm_saturate(bld_base, result);
2178 LLVMBuildStore(builder, result, ptr);
2179 }
2180 }
2181
2182 if (si_shader_ctx->shader->key.ps.alpha_to_one)
2183 LLVMBuildStore(base->gallivm->builder,
2184 base->one, alpha_ptr);
2185
2186 if (semantic_index == 0 &&
2187 si_shader_ctx->shader->key.ps.alpha_func != PIPE_FUNC_ALWAYS)
2188 si_alpha_test(bld_base, alpha_ptr);
2189
2190 if (si_shader_ctx->shader->key.ps.poly_line_smoothing)
2191 si_scale_alpha_by_sample_mask(bld_base, alpha_ptr);
2192
2193 break;
2194 default:
2195 target = 0;
2196 fprintf(stderr,
2197 "Warning: SI unhandled fs output type:%d\n",
2198 semantic_name);
2199 }
2200
2201 si_llvm_init_export_args_load(bld_base,
2202 si_shader_ctx->radeon_bld.soa.outputs[i],
2203 target, args);
2204
2205 if (semantic_name == TGSI_SEMANTIC_COLOR) {
2206 /* If there is an export instruction waiting to be emitted, do so now. */
2207 if (last_args[0]) {
2208 lp_build_intrinsic(base->gallivm->builder,
2209 "llvm.SI.export",
2210 LLVMVoidTypeInContext(base->gallivm->context),
2211 last_args, 9, 0);
2212 }
2213
2214 /* This instruction will be emitted at the end of the shader. */
2215 memcpy(last_args, args, sizeof(args));
2216
2217 /* Handle FS_COLOR0_WRITES_ALL_CBUFS. */
2218 if (shader->selector->info.properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS] &&
2219 semantic_index == 0 &&
2220 si_shader_ctx->shader->key.ps.last_cbuf > 0) {
2221 for (int c = 1; c <= si_shader_ctx->shader->key.ps.last_cbuf; c++) {
2222 si_llvm_init_export_args_load(bld_base,
2223 si_shader_ctx->radeon_bld.soa.outputs[i],
2224 V_008DFC_SQ_EXP_MRT + c, args);
2225 lp_build_intrinsic(base->gallivm->builder,
2226 "llvm.SI.export",
2227 LLVMVoidTypeInContext(base->gallivm->context),
2228 args, 9, 0);
2229 }
2230 }
2231 } else {
2232 lp_build_intrinsic(base->gallivm->builder,
2233 "llvm.SI.export",
2234 LLVMVoidTypeInContext(base->gallivm->context),
2235 args, 9, 0);
2236 }
2237 }
2238
2239 if (depth_index >= 0 || stencil_index >= 0 || samplemask_index >= 0) {
2240 LLVMValueRef out_ptr;
2241 unsigned mask = 0;
2242
2243 /* Specify the target we are exporting */
2244 args[3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_MRTZ);
2245
2246 args[5] = base->zero; /* R, depth */
2247 args[6] = base->zero; /* G, stencil test value[0:7], stencil op value[8:15] */
2248 args[7] = base->zero; /* B, sample mask */
2249 args[8] = base->zero; /* A, alpha to mask */
2250
2251 if (depth_index >= 0) {
2252 out_ptr = si_shader_ctx->radeon_bld.soa.outputs[depth_index][2];
2253 args[5] = LLVMBuildLoad(base->gallivm->builder, out_ptr, "");
2254 mask |= 0x1;
2255 si_shader_ctx->shader->db_shader_control |= S_02880C_Z_EXPORT_ENABLE(1);
2256 }
2257
2258 if (stencil_index >= 0) {
2259 out_ptr = si_shader_ctx->radeon_bld.soa.outputs[stencil_index][1];
2260 args[6] = LLVMBuildLoad(base->gallivm->builder, out_ptr, "");
2261 mask |= 0x2;
2262 si_shader_ctx->shader->db_shader_control |=
2263 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(1);
2264 }
2265
2266 if (samplemask_index >= 0) {
2267 out_ptr = si_shader_ctx->radeon_bld.soa.outputs[samplemask_index][0];
2268 args[7] = LLVMBuildLoad(base->gallivm->builder, out_ptr, "");
2269 mask |= 0x4;
2270 si_shader_ctx->shader->db_shader_control |= S_02880C_MASK_EXPORT_ENABLE(1);
2271 }
2272
2273 /* SI (except OLAND) has a bug that it only looks
2274 * at the X writemask component. */
2275 if (si_shader_ctx->screen->b.chip_class == SI &&
2276 si_shader_ctx->screen->b.family != CHIP_OLAND)
2277 mask |= 0x1;
2278
2279 if (samplemask_index >= 0)
2280 si_shader_ctx->shader->spi_shader_z_format = V_028710_SPI_SHADER_32_ABGR;
2281 else if (stencil_index >= 0)
2282 si_shader_ctx->shader->spi_shader_z_format = V_028710_SPI_SHADER_32_GR;
2283 else
2284 si_shader_ctx->shader->spi_shader_z_format = V_028710_SPI_SHADER_32_R;
2285
2286 /* Specify which components to enable */
2287 args[0] = lp_build_const_int32(base->gallivm, mask);
2288
2289 args[1] =
2290 args[2] =
2291 args[4] = uint->zero;
2292
2293 if (last_args[0])
2294 lp_build_intrinsic(base->gallivm->builder,
2295 "llvm.SI.export",
2296 LLVMVoidTypeInContext(base->gallivm->context),
2297 args, 9, 0);
2298 else
2299 memcpy(last_args, args, sizeof(args));
2300 }
2301
2302 if (!last_args[0]) {
2303 /* Specify which components to enable */
2304 last_args[0] = lp_build_const_int32(base->gallivm, 0x0);
2305
2306 /* Specify the target we are exporting */
2307 last_args[3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_MRT);
2308
2309 /* Set COMPR flag to zero to export data as 32-bit */
2310 last_args[4] = uint->zero;
2311
2312 /* dummy bits */
2313 last_args[5]= uint->zero;
2314 last_args[6]= uint->zero;
2315 last_args[7]= uint->zero;
2316 last_args[8]= uint->zero;
2317 }
2318
2319 /* Specify whether the EXEC mask represents the valid mask */
2320 last_args[1] = uint->one;
2321
2322 /* Specify that this is the last export */
2323 last_args[2] = lp_build_const_int32(base->gallivm, 1);
2324
2325 lp_build_intrinsic(base->gallivm->builder,
2326 "llvm.SI.export",
2327 LLVMVoidTypeInContext(base->gallivm->context),
2328 last_args, 9, 0);
2329 }
2330
2331 static void build_tex_intrinsic(const struct lp_build_tgsi_action * action,
2332 struct lp_build_tgsi_context * bld_base,
2333 struct lp_build_emit_data * emit_data);
2334
2335 static bool tgsi_is_array_sampler(unsigned target)
2336 {
2337 return target == TGSI_TEXTURE_1D_ARRAY ||
2338 target == TGSI_TEXTURE_SHADOW1D_ARRAY ||
2339 target == TGSI_TEXTURE_2D_ARRAY ||
2340 target == TGSI_TEXTURE_SHADOW2D_ARRAY ||
2341 target == TGSI_TEXTURE_CUBE_ARRAY ||
2342 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY ||
2343 target == TGSI_TEXTURE_2D_ARRAY_MSAA;
2344 }
2345
2346 static void set_tex_fetch_args(struct gallivm_state *gallivm,
2347 struct lp_build_emit_data *emit_data,
2348 unsigned opcode, unsigned target,
2349 LLVMValueRef res_ptr, LLVMValueRef samp_ptr,
2350 LLVMValueRef *param, unsigned count,
2351 unsigned dmask)
2352 {
2353 unsigned num_args;
2354 unsigned is_rect = target == TGSI_TEXTURE_RECT;
2355 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
2356
2357 /* Pad to power of two vector */
2358 while (count < util_next_power_of_two(count))
2359 param[count++] = LLVMGetUndef(i32);
2360
2361 /* Texture coordinates. */
2362 if (count > 1)
2363 emit_data->args[0] = lp_build_gather_values(gallivm, param, count);
2364 else
2365 emit_data->args[0] = param[0];
2366
2367 /* Resource. */
2368 emit_data->args[1] = res_ptr;
2369 num_args = 2;
2370
2371 if (opcode == TGSI_OPCODE_TXF || opcode == TGSI_OPCODE_TXQ)
2372 emit_data->dst_type = LLVMVectorType(i32, 4);
2373 else {
2374 emit_data->dst_type = LLVMVectorType(
2375 LLVMFloatTypeInContext(gallivm->context), 4);
2376
2377 emit_data->args[num_args++] = samp_ptr;
2378 }
2379
2380 emit_data->args[num_args++] = lp_build_const_int32(gallivm, dmask);
2381 emit_data->args[num_args++] = lp_build_const_int32(gallivm, is_rect); /* unorm */
2382 emit_data->args[num_args++] = lp_build_const_int32(gallivm, 0); /* r128 */
2383 emit_data->args[num_args++] = lp_build_const_int32(gallivm,
2384 tgsi_is_array_sampler(target)); /* da */
2385 emit_data->args[num_args++] = lp_build_const_int32(gallivm, 0); /* glc */
2386 emit_data->args[num_args++] = lp_build_const_int32(gallivm, 0); /* slc */
2387 emit_data->args[num_args++] = lp_build_const_int32(gallivm, 0); /* tfe */
2388 emit_data->args[num_args++] = lp_build_const_int32(gallivm, 0); /* lwe */
2389
2390 emit_data->arg_count = num_args;
2391 }
2392
2393 static const struct lp_build_tgsi_action tex_action;
2394
2395 static void tex_fetch_ptrs(
2396 struct lp_build_tgsi_context * bld_base,
2397 struct lp_build_emit_data * emit_data,
2398 LLVMValueRef *res_ptr, LLVMValueRef *samp_ptr, LLVMValueRef *fmask_ptr)
2399 {
2400 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
2401 struct gallivm_state *gallivm = bld_base->base.gallivm;
2402 const struct tgsi_full_instruction * inst = emit_data->inst;
2403 unsigned target = inst->Texture.Texture;
2404 unsigned sampler_src;
2405 unsigned sampler_index;
2406
2407 sampler_src = emit_data->inst->Instruction.NumSrcRegs - 1;
2408 sampler_index = emit_data->inst->Src[sampler_src].Register.Index;
2409
2410 if (emit_data->inst->Src[sampler_src].Register.Indirect) {
2411 const struct tgsi_full_src_register *reg = &emit_data->inst->Src[sampler_src];
2412 LLVMValueRef ind_index;
2413
2414 ind_index = get_indirect_index(si_shader_ctx, &reg->Indirect, reg->Register.Index);
2415
2416 *res_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_RESOURCE);
2417 *res_ptr = build_indexed_load_const(si_shader_ctx, *res_ptr, ind_index);
2418
2419 *samp_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_SAMPLER);
2420 *samp_ptr = build_indexed_load_const(si_shader_ctx, *samp_ptr, ind_index);
2421
2422 if (target == TGSI_TEXTURE_2D_MSAA ||
2423 target == TGSI_TEXTURE_2D_ARRAY_MSAA) {
2424 ind_index = LLVMBuildAdd(gallivm->builder, ind_index,
2425 lp_build_const_int32(gallivm,
2426 SI_FMASK_TEX_OFFSET), "");
2427 *fmask_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_RESOURCE);
2428 *fmask_ptr = build_indexed_load_const(si_shader_ctx, *fmask_ptr, ind_index);
2429 }
2430 } else {
2431 *res_ptr = si_shader_ctx->resources[sampler_index];
2432 *samp_ptr = si_shader_ctx->samplers[sampler_index];
2433 *fmask_ptr = si_shader_ctx->resources[SI_FMASK_TEX_OFFSET + sampler_index];
2434 }
2435 }
2436
2437 static void tex_fetch_args(
2438 struct lp_build_tgsi_context * bld_base,
2439 struct lp_build_emit_data * emit_data)
2440 {
2441 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
2442 struct gallivm_state *gallivm = bld_base->base.gallivm;
2443 LLVMBuilderRef builder = gallivm->builder;
2444 const struct tgsi_full_instruction * inst = emit_data->inst;
2445 unsigned opcode = inst->Instruction.Opcode;
2446 unsigned target = inst->Texture.Texture;
2447 LLVMValueRef coords[5], derivs[6];
2448 LLVMValueRef address[16];
2449 int ref_pos;
2450 unsigned num_coords = tgsi_util_get_texture_coord_dim(target, &ref_pos);
2451 unsigned count = 0;
2452 unsigned chan;
2453 unsigned num_deriv_channels = 0;
2454 bool has_offset = inst->Texture.NumOffsets > 0;
2455 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL;
2456 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
2457 unsigned dmask = 0xf;
2458
2459 tex_fetch_ptrs(bld_base, emit_data, &res_ptr, &samp_ptr, &fmask_ptr);
2460
2461 if (opcode == TGSI_OPCODE_TXQ) {
2462 if (target == TGSI_TEXTURE_BUFFER) {
2463 LLVMTypeRef v8i32 = LLVMVectorType(i32, 8);
2464
2465 /* Read the size from the buffer descriptor directly. */
2466 LLVMValueRef res = LLVMBuildBitCast(builder, res_ptr, v8i32, "");
2467 LLVMValueRef size = LLVMBuildExtractElement(builder, res,
2468 lp_build_const_int32(gallivm, 6), "");
2469
2470 if (si_shader_ctx->screen->b.chip_class >= VI) {
2471 /* On VI, the descriptor contains the size in bytes,
2472 * but TXQ must return the size in elements.
2473 * The stride is always non-zero for resources using TXQ.
2474 */
2475 LLVMValueRef stride =
2476 LLVMBuildExtractElement(builder, res,
2477 lp_build_const_int32(gallivm, 5), "");
2478 stride = LLVMBuildLShr(builder, stride,
2479 lp_build_const_int32(gallivm, 16), "");
2480 stride = LLVMBuildAnd(builder, stride,
2481 lp_build_const_int32(gallivm, 0x3FFF), "");
2482
2483 size = LLVMBuildUDiv(builder, size, stride, "");
2484 }
2485
2486 emit_data->args[0] = size;
2487 return;
2488 }
2489
2490 /* Textures - set the mip level. */
2491 address[count++] = lp_build_emit_fetch(bld_base, inst, 0, TGSI_CHAN_X);
2492
2493 set_tex_fetch_args(gallivm, emit_data, opcode, target, res_ptr,
2494 NULL, address, count, 0xf);
2495 return;
2496 }
2497
2498 if (target == TGSI_TEXTURE_BUFFER) {
2499 LLVMTypeRef i128 = LLVMIntTypeInContext(gallivm->context, 128);
2500 LLVMTypeRef v2i128 = LLVMVectorType(i128, 2);
2501 LLVMTypeRef i8 = LLVMInt8TypeInContext(gallivm->context);
2502 LLVMTypeRef v16i8 = LLVMVectorType(i8, 16);
2503
2504 /* Bitcast and truncate v8i32 to v16i8. */
2505 LLVMValueRef res = res_ptr;
2506 res = LLVMBuildBitCast(gallivm->builder, res, v2i128, "");
2507 res = LLVMBuildExtractElement(gallivm->builder, res, bld_base->uint_bld.one, "");
2508 res = LLVMBuildBitCast(gallivm->builder, res, v16i8, "");
2509
2510 emit_data->dst_type = LLVMVectorType(bld_base->base.elem_type, 4);
2511 emit_data->args[0] = res;
2512 emit_data->args[1] = bld_base->uint_bld.zero;
2513 emit_data->args[2] = lp_build_emit_fetch(bld_base, emit_data->inst, 0, 0);
2514 emit_data->arg_count = 3;
2515 return;
2516 }
2517
2518 /* Fetch and project texture coordinates */
2519 coords[3] = lp_build_emit_fetch(bld_base, emit_data->inst, 0, TGSI_CHAN_W);
2520 for (chan = 0; chan < 3; chan++ ) {
2521 coords[chan] = lp_build_emit_fetch(bld_base,
2522 emit_data->inst, 0,
2523 chan);
2524 if (opcode == TGSI_OPCODE_TXP)
2525 coords[chan] = lp_build_emit_llvm_binary(bld_base,
2526 TGSI_OPCODE_DIV,
2527 coords[chan],
2528 coords[3]);
2529 }
2530
2531 if (opcode == TGSI_OPCODE_TXP)
2532 coords[3] = bld_base->base.one;
2533
2534 /* Pack offsets. */
2535 if (has_offset && opcode != TGSI_OPCODE_TXF) {
2536 /* The offsets are six-bit signed integers packed like this:
2537 * X=[5:0], Y=[13:8], and Z=[21:16].
2538 */
2539 LLVMValueRef offset[3], pack;
2540
2541 assert(inst->Texture.NumOffsets == 1);
2542
2543 for (chan = 0; chan < 3; chan++) {
2544 offset[chan] = lp_build_emit_fetch_texoffset(bld_base,
2545 emit_data->inst, 0, chan);
2546 offset[chan] = LLVMBuildAnd(gallivm->builder, offset[chan],
2547 lp_build_const_int32(gallivm, 0x3f), "");
2548 if (chan)
2549 offset[chan] = LLVMBuildShl(gallivm->builder, offset[chan],
2550 lp_build_const_int32(gallivm, chan*8), "");
2551 }
2552
2553 pack = LLVMBuildOr(gallivm->builder, offset[0], offset[1], "");
2554 pack = LLVMBuildOr(gallivm->builder, pack, offset[2], "");
2555 address[count++] = pack;
2556 }
2557
2558 /* Pack LOD bias value */
2559 if (opcode == TGSI_OPCODE_TXB)
2560 address[count++] = coords[3];
2561 if (opcode == TGSI_OPCODE_TXB2)
2562 address[count++] = lp_build_emit_fetch(bld_base, inst, 1, 0);
2563
2564 /* Pack depth comparison value */
2565 if (tgsi_is_shadow_target(target) && opcode != TGSI_OPCODE_LODQ) {
2566 if (target == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
2567 address[count++] = lp_build_emit_fetch(bld_base, inst, 1, 0);
2568 } else {
2569 assert(ref_pos >= 0);
2570 address[count++] = coords[ref_pos];
2571 }
2572 }
2573
2574 /* Pack user derivatives */
2575 if (opcode == TGSI_OPCODE_TXD) {
2576 int param, num_src_deriv_channels;
2577
2578 switch (target) {
2579 case TGSI_TEXTURE_3D:
2580 num_src_deriv_channels = 3;
2581 num_deriv_channels = 3;
2582 break;
2583 case TGSI_TEXTURE_2D:
2584 case TGSI_TEXTURE_SHADOW2D:
2585 case TGSI_TEXTURE_RECT:
2586 case TGSI_TEXTURE_SHADOWRECT:
2587 case TGSI_TEXTURE_2D_ARRAY:
2588 case TGSI_TEXTURE_SHADOW2D_ARRAY:
2589 num_src_deriv_channels = 2;
2590 num_deriv_channels = 2;
2591 break;
2592 case TGSI_TEXTURE_CUBE:
2593 case TGSI_TEXTURE_SHADOWCUBE:
2594 case TGSI_TEXTURE_CUBE_ARRAY:
2595 case TGSI_TEXTURE_SHADOWCUBE_ARRAY:
2596 /* Cube derivatives will be converted to 2D. */
2597 num_src_deriv_channels = 3;
2598 num_deriv_channels = 2;
2599 break;
2600 case TGSI_TEXTURE_1D:
2601 case TGSI_TEXTURE_SHADOW1D:
2602 case TGSI_TEXTURE_1D_ARRAY:
2603 case TGSI_TEXTURE_SHADOW1D_ARRAY:
2604 num_src_deriv_channels = 1;
2605 num_deriv_channels = 1;
2606 break;
2607 default:
2608 unreachable("invalid target");
2609 }
2610
2611 for (param = 0; param < 2; param++)
2612 for (chan = 0; chan < num_src_deriv_channels; chan++)
2613 derivs[param * num_src_deriv_channels + chan] =
2614 lp_build_emit_fetch(bld_base, inst, param+1, chan);
2615 }
2616
2617 if (target == TGSI_TEXTURE_CUBE ||
2618 target == TGSI_TEXTURE_CUBE_ARRAY ||
2619 target == TGSI_TEXTURE_SHADOWCUBE ||
2620 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY)
2621 radeon_llvm_emit_prepare_cube_coords(bld_base, emit_data, coords, derivs);
2622
2623 if (opcode == TGSI_OPCODE_TXD)
2624 for (int i = 0; i < num_deriv_channels * 2; i++)
2625 address[count++] = derivs[i];
2626
2627 /* Pack texture coordinates */
2628 address[count++] = coords[0];
2629 if (num_coords > 1)
2630 address[count++] = coords[1];
2631 if (num_coords > 2)
2632 address[count++] = coords[2];
2633
2634 /* Pack LOD or sample index */
2635 if (opcode == TGSI_OPCODE_TXL || opcode == TGSI_OPCODE_TXF)
2636 address[count++] = coords[3];
2637 else if (opcode == TGSI_OPCODE_TXL2)
2638 address[count++] = lp_build_emit_fetch(bld_base, inst, 1, 0);
2639
2640 if (count > 16) {
2641 assert(!"Cannot handle more than 16 texture address parameters");
2642 count = 16;
2643 }
2644
2645 for (chan = 0; chan < count; chan++ ) {
2646 address[chan] = LLVMBuildBitCast(gallivm->builder,
2647 address[chan], i32, "");
2648 }
2649
2650 /* Adjust the sample index according to FMASK.
2651 *
2652 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
2653 * which is the identity mapping. Each nibble says which physical sample
2654 * should be fetched to get that sample.
2655 *
2656 * For example, 0x11111100 means there are only 2 samples stored and
2657 * the second sample covers 3/4 of the pixel. When reading samples 0
2658 * and 1, return physical sample 0 (determined by the first two 0s
2659 * in FMASK), otherwise return physical sample 1.
2660 *
2661 * The sample index should be adjusted as follows:
2662 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
2663 */
2664 if (target == TGSI_TEXTURE_2D_MSAA ||
2665 target == TGSI_TEXTURE_2D_ARRAY_MSAA) {
2666 struct lp_build_context *uint_bld = &bld_base->uint_bld;
2667 struct lp_build_emit_data txf_emit_data = *emit_data;
2668 LLVMValueRef txf_address[4];
2669 unsigned txf_count = count;
2670 struct tgsi_full_instruction inst = {};
2671
2672 memcpy(txf_address, address, sizeof(txf_address));
2673
2674 if (target == TGSI_TEXTURE_2D_MSAA) {
2675 txf_address[2] = bld_base->uint_bld.zero;
2676 }
2677 txf_address[3] = bld_base->uint_bld.zero;
2678
2679 /* Read FMASK using TXF. */
2680 inst.Instruction.Opcode = TGSI_OPCODE_TXF;
2681 inst.Texture.Texture = target;
2682 txf_emit_data.inst = &inst;
2683 txf_emit_data.chan = 0;
2684 set_tex_fetch_args(gallivm, &txf_emit_data, TGSI_OPCODE_TXF,
2685 target, fmask_ptr, NULL,
2686 txf_address, txf_count, 0xf);
2687 build_tex_intrinsic(&tex_action, bld_base, &txf_emit_data);
2688
2689 /* Initialize some constants. */
2690 LLVMValueRef four = LLVMConstInt(uint_bld->elem_type, 4, 0);
2691 LLVMValueRef F = LLVMConstInt(uint_bld->elem_type, 0xF, 0);
2692
2693 /* Apply the formula. */
2694 LLVMValueRef fmask =
2695 LLVMBuildExtractElement(gallivm->builder,
2696 txf_emit_data.output[0],
2697 uint_bld->zero, "");
2698
2699 unsigned sample_chan = target == TGSI_TEXTURE_2D_MSAA ? 2 : 3;
2700
2701 LLVMValueRef sample_index4 =
2702 LLVMBuildMul(gallivm->builder, address[sample_chan], four, "");
2703
2704 LLVMValueRef shifted_fmask =
2705 LLVMBuildLShr(gallivm->builder, fmask, sample_index4, "");
2706
2707 LLVMValueRef final_sample =
2708 LLVMBuildAnd(gallivm->builder, shifted_fmask, F, "");
2709
2710 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
2711 * resource descriptor is 0 (invalid),
2712 */
2713 LLVMValueRef fmask_desc =
2714 LLVMBuildBitCast(gallivm->builder, fmask_ptr,
2715 LLVMVectorType(uint_bld->elem_type, 8), "");
2716
2717 LLVMValueRef fmask_word1 =
2718 LLVMBuildExtractElement(gallivm->builder, fmask_desc,
2719 uint_bld->one, "");
2720
2721 LLVMValueRef word1_is_nonzero =
2722 LLVMBuildICmp(gallivm->builder, LLVMIntNE,
2723 fmask_word1, uint_bld->zero, "");
2724
2725 /* Replace the MSAA sample index. */
2726 address[sample_chan] =
2727 LLVMBuildSelect(gallivm->builder, word1_is_nonzero,
2728 final_sample, address[sample_chan], "");
2729 }
2730
2731 if (opcode == TGSI_OPCODE_TXF) {
2732 /* add tex offsets */
2733 if (inst->Texture.NumOffsets) {
2734 struct lp_build_context *uint_bld = &bld_base->uint_bld;
2735 struct lp_build_tgsi_soa_context *bld = lp_soa_context(bld_base);
2736 const struct tgsi_texture_offset * off = inst->TexOffsets;
2737
2738 assert(inst->Texture.NumOffsets == 1);
2739
2740 switch (target) {
2741 case TGSI_TEXTURE_3D:
2742 address[2] = lp_build_add(uint_bld, address[2],
2743 bld->immediates[off->Index][off->SwizzleZ]);
2744 /* fall through */
2745 case TGSI_TEXTURE_2D:
2746 case TGSI_TEXTURE_SHADOW2D:
2747 case TGSI_TEXTURE_RECT:
2748 case TGSI_TEXTURE_SHADOWRECT:
2749 case TGSI_TEXTURE_2D_ARRAY:
2750 case TGSI_TEXTURE_SHADOW2D_ARRAY:
2751 address[1] =
2752 lp_build_add(uint_bld, address[1],
2753 bld->immediates[off->Index][off->SwizzleY]);
2754 /* fall through */
2755 case TGSI_TEXTURE_1D:
2756 case TGSI_TEXTURE_SHADOW1D:
2757 case TGSI_TEXTURE_1D_ARRAY:
2758 case TGSI_TEXTURE_SHADOW1D_ARRAY:
2759 address[0] =
2760 lp_build_add(uint_bld, address[0],
2761 bld->immediates[off->Index][off->SwizzleX]);
2762 break;
2763 /* texture offsets do not apply to other texture targets */
2764 }
2765 }
2766 }
2767
2768 if (opcode == TGSI_OPCODE_TG4) {
2769 unsigned gather_comp = 0;
2770
2771 /* DMASK was repurposed for GATHER4. 4 components are always
2772 * returned and DMASK works like a swizzle - it selects
2773 * the component to fetch. The only valid DMASK values are
2774 * 1=red, 2=green, 4=blue, 8=alpha. (e.g. 1 returns
2775 * (red,red,red,red) etc.) The ISA document doesn't mention
2776 * this.
2777 */
2778
2779 /* Get the component index from src1.x for Gather4. */
2780 if (!tgsi_is_shadow_target(target)) {
2781 LLVMValueRef (*imms)[4] = lp_soa_context(bld_base)->immediates;
2782 LLVMValueRef comp_imm;
2783 struct tgsi_src_register src1 = inst->Src[1].Register;
2784
2785 assert(src1.File == TGSI_FILE_IMMEDIATE);
2786
2787 comp_imm = imms[src1.Index][src1.SwizzleX];
2788 gather_comp = LLVMConstIntGetZExtValue(comp_imm);
2789 gather_comp = CLAMP(gather_comp, 0, 3);
2790 }
2791
2792 dmask = 1 << gather_comp;
2793 }
2794
2795 set_tex_fetch_args(gallivm, emit_data, opcode, target, res_ptr,
2796 samp_ptr, address, count, dmask);
2797 }
2798
2799 static void build_tex_intrinsic(const struct lp_build_tgsi_action * action,
2800 struct lp_build_tgsi_context * bld_base,
2801 struct lp_build_emit_data * emit_data)
2802 {
2803 struct lp_build_context * base = &bld_base->base;
2804 unsigned opcode = emit_data->inst->Instruction.Opcode;
2805 unsigned target = emit_data->inst->Texture.Texture;
2806 char intr_name[127];
2807 bool has_offset = emit_data->inst->Texture.NumOffsets > 0;
2808 bool is_shadow = tgsi_is_shadow_target(target);
2809 char type[64];
2810 const char *name = "llvm.SI.image.sample";
2811 const char *infix = "";
2812
2813 if (opcode == TGSI_OPCODE_TXQ && target == TGSI_TEXTURE_BUFFER) {
2814 /* Just return the buffer size. */
2815 emit_data->output[emit_data->chan] = emit_data->args[0];
2816 return;
2817 }
2818
2819 if (target == TGSI_TEXTURE_BUFFER) {
2820 emit_data->output[emit_data->chan] = lp_build_intrinsic(
2821 base->gallivm->builder,
2822 "llvm.SI.vs.load.input", emit_data->dst_type,
2823 emit_data->args, emit_data->arg_count,
2824 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
2825 return;
2826 }
2827
2828 switch (opcode) {
2829 case TGSI_OPCODE_TXF:
2830 name = target == TGSI_TEXTURE_2D_MSAA ||
2831 target == TGSI_TEXTURE_2D_ARRAY_MSAA ?
2832 "llvm.SI.image.load" :
2833 "llvm.SI.image.load.mip";
2834 is_shadow = false;
2835 has_offset = false;
2836 break;
2837 case TGSI_OPCODE_TXQ:
2838 name = "llvm.SI.getresinfo";
2839 is_shadow = false;
2840 has_offset = false;
2841 break;
2842 case TGSI_OPCODE_LODQ:
2843 name = "llvm.SI.getlod";
2844 is_shadow = false;
2845 has_offset = false;
2846 break;
2847 case TGSI_OPCODE_TEX:
2848 case TGSI_OPCODE_TEX2:
2849 case TGSI_OPCODE_TXP:
2850 break;
2851 case TGSI_OPCODE_TXB:
2852 case TGSI_OPCODE_TXB2:
2853 infix = ".b";
2854 break;
2855 case TGSI_OPCODE_TXL:
2856 case TGSI_OPCODE_TXL2:
2857 infix = ".l";
2858 break;
2859 case TGSI_OPCODE_TXD:
2860 infix = ".d";
2861 break;
2862 case TGSI_OPCODE_TG4:
2863 name = "llvm.SI.gather4";
2864 break;
2865 default:
2866 assert(0);
2867 return;
2868 }
2869
2870 if (LLVMGetTypeKind(LLVMTypeOf(emit_data->args[0])) == LLVMVectorTypeKind)
2871 sprintf(type, ".v%ui32",
2872 LLVMGetVectorSize(LLVMTypeOf(emit_data->args[0])));
2873 else
2874 strcpy(type, ".i32");
2875
2876 /* Add the type and suffixes .c, .o if needed. */
2877 sprintf(intr_name, "%s%s%s%s%s",
2878 name, is_shadow ? ".c" : "", infix,
2879 has_offset ? ".o" : "", type);
2880
2881 emit_data->output[emit_data->chan] = lp_build_intrinsic(
2882 base->gallivm->builder, intr_name, emit_data->dst_type,
2883 emit_data->args, emit_data->arg_count,
2884 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
2885
2886 /* Divide the number of layers by 6 to get the number of cubes. */
2887 if (opcode == TGSI_OPCODE_TXQ &&
2888 (target == TGSI_TEXTURE_CUBE_ARRAY ||
2889 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY)) {
2890 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
2891 LLVMValueRef two = lp_build_const_int32(bld_base->base.gallivm, 2);
2892 LLVMValueRef six = lp_build_const_int32(bld_base->base.gallivm, 6);
2893
2894 LLVMValueRef v4 = emit_data->output[emit_data->chan];
2895 LLVMValueRef z = LLVMBuildExtractElement(builder, v4, two, "");
2896 z = LLVMBuildSDiv(builder, z, six, "");
2897
2898 emit_data->output[emit_data->chan] =
2899 LLVMBuildInsertElement(builder, v4, z, two, "");
2900 }
2901 }
2902
2903 static void si_llvm_emit_txqs(
2904 const struct lp_build_tgsi_action * action,
2905 struct lp_build_tgsi_context * bld_base,
2906 struct lp_build_emit_data * emit_data)
2907 {
2908 struct gallivm_state *gallivm = bld_base->base.gallivm;
2909 LLVMBuilderRef builder = gallivm->builder;
2910 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
2911 LLVMTypeRef v8i32 = LLVMVectorType(i32, 8);
2912 LLVMValueRef res, samples;
2913 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL;
2914
2915 tex_fetch_ptrs(bld_base, emit_data, &res_ptr, &samp_ptr, &fmask_ptr);
2916
2917
2918 /* Read the samples from the descriptor directly. */
2919 res = LLVMBuildBitCast(builder, res_ptr, v8i32, "");
2920 samples = LLVMBuildExtractElement(
2921 builder, res,
2922 lp_build_const_int32(gallivm, 3), "");
2923 samples = LLVMBuildLShr(builder, samples,
2924 lp_build_const_int32(gallivm, 16), "");
2925 samples = LLVMBuildAnd(builder, samples,
2926 lp_build_const_int32(gallivm, 0xf), "");
2927 samples = LLVMBuildShl(builder, lp_build_const_int32(gallivm, 1),
2928 samples, "");
2929
2930 emit_data->output[emit_data->chan] = samples;
2931 }
2932
2933 /*
2934 * SI implements derivatives using the local data store (LDS)
2935 * All writes to the LDS happen in all executing threads at
2936 * the same time. TID is the Thread ID for the current
2937 * thread and is a value between 0 and 63, representing
2938 * the thread's position in the wavefront.
2939 *
2940 * For the pixel shader threads are grouped into quads of four pixels.
2941 * The TIDs of the pixels of a quad are:
2942 *
2943 * +------+------+
2944 * |4n + 0|4n + 1|
2945 * +------+------+
2946 * |4n + 2|4n + 3|
2947 * +------+------+
2948 *
2949 * So, masking the TID with 0xfffffffc yields the TID of the top left pixel
2950 * of the quad, masking with 0xfffffffd yields the TID of the top pixel of
2951 * the current pixel's column, and masking with 0xfffffffe yields the TID
2952 * of the left pixel of the current pixel's row.
2953 *
2954 * Adding 1 yields the TID of the pixel to the right of the left pixel, and
2955 * adding 2 yields the TID of the pixel below the top pixel.
2956 */
2957 /* masks for thread ID. */
2958 #define TID_MASK_TOP_LEFT 0xfffffffc
2959 #define TID_MASK_TOP 0xfffffffd
2960 #define TID_MASK_LEFT 0xfffffffe
2961
2962 static void si_llvm_emit_ddxy(
2963 const struct lp_build_tgsi_action * action,
2964 struct lp_build_tgsi_context * bld_base,
2965 struct lp_build_emit_data * emit_data)
2966 {
2967 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
2968 struct gallivm_state *gallivm = bld_base->base.gallivm;
2969 struct lp_build_context * base = &bld_base->base;
2970 const struct tgsi_full_instruction *inst = emit_data->inst;
2971 unsigned opcode = inst->Instruction.Opcode;
2972 LLVMValueRef indices[2];
2973 LLVMValueRef store_ptr, load_ptr0, load_ptr1;
2974 LLVMValueRef tl, trbl, result[4];
2975 LLVMTypeRef i32;
2976 unsigned swizzle[4];
2977 unsigned c;
2978 int idx;
2979 unsigned mask;
2980
2981 i32 = LLVMInt32TypeInContext(gallivm->context);
2982
2983 indices[0] = bld_base->uint_bld.zero;
2984 indices[1] = lp_build_intrinsic(gallivm->builder, "llvm.SI.tid", i32,
2985 NULL, 0, LLVMReadNoneAttribute);
2986 store_ptr = LLVMBuildGEP(gallivm->builder, si_shader_ctx->lds,
2987 indices, 2, "");
2988
2989 if (opcode == TGSI_OPCODE_DDX_FINE)
2990 mask = TID_MASK_LEFT;
2991 else if (opcode == TGSI_OPCODE_DDY_FINE)
2992 mask = TID_MASK_TOP;
2993 else
2994 mask = TID_MASK_TOP_LEFT;
2995
2996 indices[1] = LLVMBuildAnd(gallivm->builder, indices[1],
2997 lp_build_const_int32(gallivm, mask), "");
2998 load_ptr0 = LLVMBuildGEP(gallivm->builder, si_shader_ctx->lds,
2999 indices, 2, "");
3000
3001 /* for DDX we want to next X pixel, DDY next Y pixel. */
3002 idx = (opcode == TGSI_OPCODE_DDX || opcode == TGSI_OPCODE_DDX_FINE) ? 1 : 2;
3003 indices[1] = LLVMBuildAdd(gallivm->builder, indices[1],
3004 lp_build_const_int32(gallivm, idx), "");
3005 load_ptr1 = LLVMBuildGEP(gallivm->builder, si_shader_ctx->lds,
3006 indices, 2, "");
3007
3008 for (c = 0; c < 4; ++c) {
3009 unsigned i;
3010
3011 swizzle[c] = tgsi_util_get_full_src_register_swizzle(&inst->Src[0], c);
3012 for (i = 0; i < c; ++i) {
3013 if (swizzle[i] == swizzle[c]) {
3014 result[c] = result[i];
3015 break;
3016 }
3017 }
3018 if (i != c)
3019 continue;
3020
3021 LLVMBuildStore(gallivm->builder,
3022 LLVMBuildBitCast(gallivm->builder,
3023 lp_build_emit_fetch(bld_base, inst, 0, c),
3024 i32, ""),
3025 store_ptr);
3026
3027 tl = LLVMBuildLoad(gallivm->builder, load_ptr0, "");
3028 tl = LLVMBuildBitCast(gallivm->builder, tl, base->elem_type, "");
3029
3030 trbl = LLVMBuildLoad(gallivm->builder, load_ptr1, "");
3031 trbl = LLVMBuildBitCast(gallivm->builder, trbl, base->elem_type, "");
3032
3033 result[c] = LLVMBuildFSub(gallivm->builder, trbl, tl, "");
3034 }
3035
3036 emit_data->output[0] = lp_build_gather_values(gallivm, result, 4);
3037 }
3038
3039 /*
3040 * this takes an I,J coordinate pair,
3041 * and works out the X and Y derivatives.
3042 * it returns DDX(I), DDX(J), DDY(I), DDY(J).
3043 */
3044 static LLVMValueRef si_llvm_emit_ddxy_interp(
3045 struct lp_build_tgsi_context *bld_base,
3046 LLVMValueRef interp_ij)
3047 {
3048 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
3049 struct gallivm_state *gallivm = bld_base->base.gallivm;
3050 struct lp_build_context *base = &bld_base->base;
3051 LLVMValueRef indices[2];
3052 LLVMValueRef store_ptr, load_ptr_x, load_ptr_y, load_ptr_ddx, load_ptr_ddy, temp, temp2;
3053 LLVMValueRef tl, tr, bl, result[4];
3054 LLVMTypeRef i32;
3055 unsigned c;
3056
3057 i32 = LLVMInt32TypeInContext(gallivm->context);
3058
3059 indices[0] = bld_base->uint_bld.zero;
3060 indices[1] = lp_build_intrinsic(gallivm->builder, "llvm.SI.tid", i32,
3061 NULL, 0, LLVMReadNoneAttribute);
3062 store_ptr = LLVMBuildGEP(gallivm->builder, si_shader_ctx->lds,
3063 indices, 2, "");
3064
3065 temp = LLVMBuildAnd(gallivm->builder, indices[1],
3066 lp_build_const_int32(gallivm, TID_MASK_LEFT), "");
3067
3068 temp2 = LLVMBuildAnd(gallivm->builder, indices[1],
3069 lp_build_const_int32(gallivm, TID_MASK_TOP), "");
3070
3071 indices[1] = temp;
3072 load_ptr_x = LLVMBuildGEP(gallivm->builder, si_shader_ctx->lds,
3073 indices, 2, "");
3074
3075 indices[1] = temp2;
3076 load_ptr_y = LLVMBuildGEP(gallivm->builder, si_shader_ctx->lds,
3077 indices, 2, "");
3078
3079 indices[1] = LLVMBuildAdd(gallivm->builder, temp,
3080 lp_build_const_int32(gallivm, 1), "");
3081 load_ptr_ddx = LLVMBuildGEP(gallivm->builder, si_shader_ctx->lds,
3082 indices, 2, "");
3083
3084 indices[1] = LLVMBuildAdd(gallivm->builder, temp2,
3085 lp_build_const_int32(gallivm, 2), "");
3086 load_ptr_ddy = LLVMBuildGEP(gallivm->builder, si_shader_ctx->lds,
3087 indices, 2, "");
3088
3089 for (c = 0; c < 2; ++c) {
3090 LLVMValueRef store_val;
3091 LLVMValueRef c_ll = lp_build_const_int32(gallivm, c);
3092
3093 store_val = LLVMBuildExtractElement(gallivm->builder,
3094 interp_ij, c_ll, "");
3095 LLVMBuildStore(gallivm->builder,
3096 store_val,
3097 store_ptr);
3098
3099 tl = LLVMBuildLoad(gallivm->builder, load_ptr_x, "");
3100 tl = LLVMBuildBitCast(gallivm->builder, tl, base->elem_type, "");
3101
3102 tr = LLVMBuildLoad(gallivm->builder, load_ptr_ddx, "");
3103 tr = LLVMBuildBitCast(gallivm->builder, tr, base->elem_type, "");
3104
3105 result[c] = LLVMBuildFSub(gallivm->builder, tr, tl, "");
3106
3107 tl = LLVMBuildLoad(gallivm->builder, load_ptr_y, "");
3108 tl = LLVMBuildBitCast(gallivm->builder, tl, base->elem_type, "");
3109
3110 bl = LLVMBuildLoad(gallivm->builder, load_ptr_ddy, "");
3111 bl = LLVMBuildBitCast(gallivm->builder, bl, base->elem_type, "");
3112
3113 result[c + 2] = LLVMBuildFSub(gallivm->builder, bl, tl, "");
3114 }
3115
3116 return lp_build_gather_values(gallivm, result, 4);
3117 }
3118
3119 static void interp_fetch_args(
3120 struct lp_build_tgsi_context *bld_base,
3121 struct lp_build_emit_data *emit_data)
3122 {
3123 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
3124 struct gallivm_state *gallivm = bld_base->base.gallivm;
3125 const struct tgsi_full_instruction *inst = emit_data->inst;
3126
3127 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET) {
3128 /* offset is in second src, first two channels */
3129 emit_data->args[0] = lp_build_emit_fetch(bld_base,
3130 emit_data->inst, 1,
3131 0);
3132 emit_data->args[1] = lp_build_emit_fetch(bld_base,
3133 emit_data->inst, 1,
3134 1);
3135 emit_data->arg_count = 2;
3136 } else if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
3137 LLVMValueRef sample_position;
3138 LLVMValueRef sample_id;
3139 LLVMValueRef halfval = lp_build_const_float(gallivm, 0.5f);
3140
3141 /* fetch sample ID, then fetch its sample position,
3142 * and place into first two channels.
3143 */
3144 sample_id = lp_build_emit_fetch(bld_base,
3145 emit_data->inst, 1, 0);
3146 sample_id = LLVMBuildBitCast(gallivm->builder, sample_id,
3147 LLVMInt32TypeInContext(gallivm->context),
3148 "");
3149 sample_position = load_sample_position(&si_shader_ctx->radeon_bld, sample_id);
3150
3151 emit_data->args[0] = LLVMBuildExtractElement(gallivm->builder,
3152 sample_position,
3153 lp_build_const_int32(gallivm, 0), "");
3154
3155 emit_data->args[0] = LLVMBuildFSub(gallivm->builder, emit_data->args[0], halfval, "");
3156 emit_data->args[1] = LLVMBuildExtractElement(gallivm->builder,
3157 sample_position,
3158 lp_build_const_int32(gallivm, 1), "");
3159 emit_data->args[1] = LLVMBuildFSub(gallivm->builder, emit_data->args[1], halfval, "");
3160 emit_data->arg_count = 2;
3161 }
3162 }
3163
3164 static void build_interp_intrinsic(const struct lp_build_tgsi_action *action,
3165 struct lp_build_tgsi_context *bld_base,
3166 struct lp_build_emit_data *emit_data)
3167 {
3168 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
3169 struct si_shader *shader = si_shader_ctx->shader;
3170 struct gallivm_state *gallivm = bld_base->base.gallivm;
3171 LLVMValueRef interp_param;
3172 const struct tgsi_full_instruction *inst = emit_data->inst;
3173 const char *intr_name;
3174 int input_index;
3175 int chan;
3176 int i;
3177 LLVMValueRef attr_number;
3178 LLVMTypeRef input_type = LLVMFloatTypeInContext(gallivm->context);
3179 LLVMValueRef params = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_PRIM_MASK);
3180 int interp_param_idx;
3181 unsigned location;
3182
3183 assert(inst->Src[0].Register.File == TGSI_FILE_INPUT);
3184 input_index = inst->Src[0].Register.Index;
3185
3186 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
3187 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE)
3188 location = TGSI_INTERPOLATE_LOC_CENTER;
3189 else
3190 location = TGSI_INTERPOLATE_LOC_CENTROID;
3191
3192 interp_param_idx = lookup_interp_param_index(shader->ps_input_interpolate[input_index],
3193 location);
3194 if (interp_param_idx == -1)
3195 return;
3196 else if (interp_param_idx)
3197 interp_param = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, interp_param_idx);
3198 else
3199 interp_param = NULL;
3200
3201 attr_number = lp_build_const_int32(gallivm,
3202 shader->ps_input_param_offset[input_index]);
3203
3204 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
3205 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
3206 LLVMValueRef ij_out[2];
3207 LLVMValueRef ddxy_out = si_llvm_emit_ddxy_interp(bld_base, interp_param);
3208
3209 /*
3210 * take the I then J parameters, and the DDX/Y for it, and
3211 * calculate the IJ inputs for the interpolator.
3212 * temp1 = ddx * offset/sample.x + I;
3213 * interp_param.I = ddy * offset/sample.y + temp1;
3214 * temp1 = ddx * offset/sample.x + J;
3215 * interp_param.J = ddy * offset/sample.y + temp1;
3216 */
3217 for (i = 0; i < 2; i++) {
3218 LLVMValueRef ix_ll = lp_build_const_int32(gallivm, i);
3219 LLVMValueRef iy_ll = lp_build_const_int32(gallivm, i + 2);
3220 LLVMValueRef ddx_el = LLVMBuildExtractElement(gallivm->builder,
3221 ddxy_out, ix_ll, "");
3222 LLVMValueRef ddy_el = LLVMBuildExtractElement(gallivm->builder,
3223 ddxy_out, iy_ll, "");
3224 LLVMValueRef interp_el = LLVMBuildExtractElement(gallivm->builder,
3225 interp_param, ix_ll, "");
3226 LLVMValueRef temp1, temp2;
3227
3228 interp_el = LLVMBuildBitCast(gallivm->builder, interp_el,
3229 LLVMFloatTypeInContext(gallivm->context), "");
3230
3231 temp1 = LLVMBuildFMul(gallivm->builder, ddx_el, emit_data->args[0], "");
3232
3233 temp1 = LLVMBuildFAdd(gallivm->builder, temp1, interp_el, "");
3234
3235 temp2 = LLVMBuildFMul(gallivm->builder, ddy_el, emit_data->args[1], "");
3236
3237 temp2 = LLVMBuildFAdd(gallivm->builder, temp2, temp1, "");
3238
3239 ij_out[i] = LLVMBuildBitCast(gallivm->builder,
3240 temp2,
3241 LLVMIntTypeInContext(gallivm->context, 32), "");
3242 }
3243 interp_param = lp_build_gather_values(bld_base->base.gallivm, ij_out, 2);
3244 }
3245
3246 intr_name = interp_param ? "llvm.SI.fs.interp" : "llvm.SI.fs.constant";
3247 for (chan = 0; chan < 2; chan++) {
3248 LLVMValueRef args[4];
3249 LLVMValueRef llvm_chan;
3250 unsigned schan;
3251
3252 schan = tgsi_util_get_full_src_register_swizzle(&inst->Src[0], chan);
3253 llvm_chan = lp_build_const_int32(gallivm, schan);
3254
3255 args[0] = llvm_chan;
3256 args[1] = attr_number;
3257 args[2] = params;
3258 args[3] = interp_param;
3259
3260 emit_data->output[chan] =
3261 lp_build_intrinsic(gallivm->builder, intr_name,
3262 input_type, args, args[3] ? 4 : 3,
3263 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
3264 }
3265 }
3266
3267 static unsigned si_llvm_get_stream(struct lp_build_tgsi_context *bld_base,
3268 struct lp_build_emit_data *emit_data)
3269 {
3270 LLVMValueRef (*imms)[4] = lp_soa_context(bld_base)->immediates;
3271 struct tgsi_src_register src0 = emit_data->inst->Src[0].Register;
3272 unsigned stream;
3273
3274 assert(src0.File == TGSI_FILE_IMMEDIATE);
3275
3276 stream = LLVMConstIntGetZExtValue(imms[src0.Index][src0.SwizzleX]) & 0x3;
3277 return stream;
3278 }
3279
3280 /* Emit one vertex from the geometry shader */
3281 static void si_llvm_emit_vertex(
3282 const struct lp_build_tgsi_action *action,
3283 struct lp_build_tgsi_context *bld_base,
3284 struct lp_build_emit_data *emit_data)
3285 {
3286 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
3287 struct lp_build_context *uint = &bld_base->uint_bld;
3288 struct si_shader *shader = si_shader_ctx->shader;
3289 struct tgsi_shader_info *info = &shader->selector->info;
3290 struct gallivm_state *gallivm = bld_base->base.gallivm;
3291 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
3292 LLVMValueRef soffset = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
3293 SI_PARAM_GS2VS_OFFSET);
3294 LLVMValueRef gs_next_vertex;
3295 LLVMValueRef can_emit, kill;
3296 LLVMValueRef args[2];
3297 unsigned chan;
3298 int i;
3299 unsigned stream;
3300
3301 stream = si_llvm_get_stream(bld_base, emit_data);
3302
3303 /* Write vertex attribute values to GSVS ring */
3304 gs_next_vertex = LLVMBuildLoad(gallivm->builder,
3305 si_shader_ctx->gs_next_vertex[stream],
3306 "");
3307
3308 /* If this thread has already emitted the declared maximum number of
3309 * vertices, kill it: excessive vertex emissions are not supposed to
3310 * have any effect, and GS threads have no externally observable
3311 * effects other than emitting vertices.
3312 */
3313 can_emit = LLVMBuildICmp(gallivm->builder, LLVMIntULE, gs_next_vertex,
3314 lp_build_const_int32(gallivm,
3315 shader->selector->gs_max_out_vertices), "");
3316 kill = lp_build_select(&bld_base->base, can_emit,
3317 lp_build_const_float(gallivm, 1.0f),
3318 lp_build_const_float(gallivm, -1.0f));
3319
3320 lp_build_intrinsic(gallivm->builder, "llvm.AMDGPU.kill",
3321 LLVMVoidTypeInContext(gallivm->context), &kill, 1, 0);
3322
3323 for (i = 0; i < info->num_outputs; i++) {
3324 LLVMValueRef *out_ptr =
3325 si_shader_ctx->radeon_bld.soa.outputs[i];
3326
3327 for (chan = 0; chan < 4; chan++) {
3328 LLVMValueRef out_val = LLVMBuildLoad(gallivm->builder, out_ptr[chan], "");
3329 LLVMValueRef voffset =
3330 lp_build_const_int32(gallivm, (i * 4 + chan) *
3331 shader->selector->gs_max_out_vertices);
3332
3333 voffset = lp_build_add(uint, voffset, gs_next_vertex);
3334 voffset = lp_build_mul_imm(uint, voffset, 4);
3335
3336 out_val = LLVMBuildBitCast(gallivm->builder, out_val, i32, "");
3337
3338 build_tbuffer_store(si_shader_ctx,
3339 si_shader_ctx->gsvs_ring[stream],
3340 out_val, 1,
3341 voffset, soffset, 0,
3342 V_008F0C_BUF_DATA_FORMAT_32,
3343 V_008F0C_BUF_NUM_FORMAT_UINT,
3344 1, 0, 1, 1, 0);
3345 }
3346 }
3347 gs_next_vertex = lp_build_add(uint, gs_next_vertex,
3348 lp_build_const_int32(gallivm, 1));
3349
3350 LLVMBuildStore(gallivm->builder, gs_next_vertex, si_shader_ctx->gs_next_vertex[stream]);
3351
3352 /* Signal vertex emission */
3353 args[0] = lp_build_const_int32(gallivm, SENDMSG_GS_OP_EMIT | SENDMSG_GS | (stream << 8));
3354 args[1] = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_GS_WAVE_ID);
3355 lp_build_intrinsic(gallivm->builder, "llvm.SI.sendmsg",
3356 LLVMVoidTypeInContext(gallivm->context), args, 2,
3357 LLVMNoUnwindAttribute);
3358 }
3359
3360 /* Cut one primitive from the geometry shader */
3361 static void si_llvm_emit_primitive(
3362 const struct lp_build_tgsi_action *action,
3363 struct lp_build_tgsi_context *bld_base,
3364 struct lp_build_emit_data *emit_data)
3365 {
3366 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
3367 struct gallivm_state *gallivm = bld_base->base.gallivm;
3368 LLVMValueRef args[2];
3369 unsigned stream;
3370
3371 /* Signal primitive cut */
3372 stream = si_llvm_get_stream(bld_base, emit_data);
3373 args[0] = lp_build_const_int32(gallivm, SENDMSG_GS_OP_CUT | SENDMSG_GS | (stream << 8));
3374 args[1] = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_GS_WAVE_ID);
3375 lp_build_intrinsic(gallivm->builder, "llvm.SI.sendmsg",
3376 LLVMVoidTypeInContext(gallivm->context), args, 2,
3377 LLVMNoUnwindAttribute);
3378 }
3379
3380 static void si_llvm_emit_barrier(const struct lp_build_tgsi_action *action,
3381 struct lp_build_tgsi_context *bld_base,
3382 struct lp_build_emit_data *emit_data)
3383 {
3384 struct gallivm_state *gallivm = bld_base->base.gallivm;
3385
3386 lp_build_intrinsic(gallivm->builder, "llvm.AMDGPU.barrier.local",
3387 LLVMVoidTypeInContext(gallivm->context), NULL, 0,
3388 LLVMNoUnwindAttribute);
3389 }
3390
3391 static const struct lp_build_tgsi_action tex_action = {
3392 .fetch_args = tex_fetch_args,
3393 .emit = build_tex_intrinsic,
3394 };
3395
3396 static const struct lp_build_tgsi_action interp_action = {
3397 .fetch_args = interp_fetch_args,
3398 .emit = build_interp_intrinsic,
3399 };
3400
3401 static void create_meta_data(struct si_shader_context *si_shader_ctx)
3402 {
3403 struct gallivm_state *gallivm = si_shader_ctx->radeon_bld.soa.bld_base.base.gallivm;
3404 LLVMValueRef args[3];
3405
3406 args[0] = LLVMMDStringInContext(gallivm->context, "const", 5);
3407 args[1] = 0;
3408 args[2] = lp_build_const_int32(gallivm, 1);
3409
3410 si_shader_ctx->const_md = LLVMMDNodeInContext(gallivm->context, args, 3);
3411 }
3412
3413 static LLVMTypeRef const_array(LLVMTypeRef elem_type, int num_elements)
3414 {
3415 return LLVMPointerType(LLVMArrayType(elem_type, num_elements),
3416 CONST_ADDR_SPACE);
3417 }
3418
3419 static void declare_streamout_params(struct si_shader_context *si_shader_ctx,
3420 struct pipe_stream_output_info *so,
3421 LLVMTypeRef *params, LLVMTypeRef i32,
3422 unsigned *num_params)
3423 {
3424 int i;
3425
3426 /* Streamout SGPRs. */
3427 if (so->num_outputs) {
3428 params[si_shader_ctx->param_streamout_config = (*num_params)++] = i32;
3429 params[si_shader_ctx->param_streamout_write_index = (*num_params)++] = i32;
3430 }
3431 /* A streamout buffer offset is loaded if the stride is non-zero. */
3432 for (i = 0; i < 4; i++) {
3433 if (!so->stride[i])
3434 continue;
3435
3436 params[si_shader_ctx->param_streamout_offset[i] = (*num_params)++] = i32;
3437 }
3438 }
3439
3440 static void create_function(struct si_shader_context *si_shader_ctx)
3441 {
3442 struct lp_build_tgsi_context *bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
3443 struct gallivm_state *gallivm = bld_base->base.gallivm;
3444 struct si_shader *shader = si_shader_ctx->shader;
3445 LLVMTypeRef params[SI_NUM_PARAMS], f32, i8, i32, v2i32, v3i32, v16i8, v4i32, v8i32;
3446 unsigned i, last_array_pointer, last_sgpr, num_params;
3447
3448 i8 = LLVMInt8TypeInContext(gallivm->context);
3449 i32 = LLVMInt32TypeInContext(gallivm->context);
3450 f32 = LLVMFloatTypeInContext(gallivm->context);
3451 v2i32 = LLVMVectorType(i32, 2);
3452 v3i32 = LLVMVectorType(i32, 3);
3453 v4i32 = LLVMVectorType(i32, 4);
3454 v8i32 = LLVMVectorType(i32, 8);
3455 v16i8 = LLVMVectorType(i8, 16);
3456
3457 params[SI_PARAM_RW_BUFFERS] = const_array(v16i8, SI_NUM_RW_BUFFERS);
3458 params[SI_PARAM_CONST] = const_array(v16i8, SI_NUM_CONST_BUFFERS);
3459 params[SI_PARAM_SAMPLER] = const_array(v4i32, SI_NUM_SAMPLER_STATES);
3460 params[SI_PARAM_RESOURCE] = const_array(v8i32, SI_NUM_SAMPLER_VIEWS);
3461 last_array_pointer = SI_PARAM_RESOURCE;
3462
3463 switch (si_shader_ctx->type) {
3464 case TGSI_PROCESSOR_VERTEX:
3465 params[SI_PARAM_VERTEX_BUFFER] = const_array(v16i8, SI_NUM_VERTEX_BUFFERS);
3466 last_array_pointer = SI_PARAM_VERTEX_BUFFER;
3467 params[SI_PARAM_BASE_VERTEX] = i32;
3468 params[SI_PARAM_START_INSTANCE] = i32;
3469 num_params = SI_PARAM_START_INSTANCE+1;
3470
3471 if (shader->key.vs.as_es) {
3472 params[si_shader_ctx->param_es2gs_offset = num_params++] = i32;
3473 } else if (shader->key.vs.as_ls) {
3474 params[SI_PARAM_LS_OUT_LAYOUT] = i32;
3475 num_params = SI_PARAM_LS_OUT_LAYOUT+1;
3476 } else {
3477 if (shader->is_gs_copy_shader) {
3478 last_array_pointer = SI_PARAM_CONST;
3479 num_params = SI_PARAM_CONST+1;
3480 } else {
3481 params[SI_PARAM_VS_STATE_BITS] = i32;
3482 num_params = SI_PARAM_VS_STATE_BITS+1;
3483 }
3484
3485 /* The locations of the other parameters are assigned dynamically. */
3486 declare_streamout_params(si_shader_ctx, &shader->selector->so,
3487 params, i32, &num_params);
3488 }
3489
3490 last_sgpr = num_params-1;
3491
3492 /* VGPRs */
3493 params[si_shader_ctx->param_vertex_id = num_params++] = i32;
3494 params[si_shader_ctx->param_rel_auto_id = num_params++] = i32;
3495 params[si_shader_ctx->param_vs_prim_id = num_params++] = i32;
3496 params[si_shader_ctx->param_instance_id = num_params++] = i32;
3497 break;
3498
3499 case TGSI_PROCESSOR_TESS_CTRL:
3500 params[SI_PARAM_TCS_OUT_OFFSETS] = i32;
3501 params[SI_PARAM_TCS_OUT_LAYOUT] = i32;
3502 params[SI_PARAM_TCS_IN_LAYOUT] = i32;
3503 params[SI_PARAM_TESS_FACTOR_OFFSET] = i32;
3504 last_sgpr = SI_PARAM_TESS_FACTOR_OFFSET;
3505
3506 /* VGPRs */
3507 params[SI_PARAM_PATCH_ID] = i32;
3508 params[SI_PARAM_REL_IDS] = i32;
3509 num_params = SI_PARAM_REL_IDS+1;
3510 break;
3511
3512 case TGSI_PROCESSOR_TESS_EVAL:
3513 params[SI_PARAM_TCS_OUT_OFFSETS] = i32;
3514 params[SI_PARAM_TCS_OUT_LAYOUT] = i32;
3515 num_params = SI_PARAM_TCS_OUT_LAYOUT+1;
3516
3517 if (shader->key.tes.as_es) {
3518 params[si_shader_ctx->param_es2gs_offset = num_params++] = i32;
3519 } else {
3520 declare_streamout_params(si_shader_ctx, &shader->selector->so,
3521 params, i32, &num_params);
3522 }
3523 last_sgpr = num_params - 1;
3524
3525 /* VGPRs */
3526 params[si_shader_ctx->param_tes_u = num_params++] = f32;
3527 params[si_shader_ctx->param_tes_v = num_params++] = f32;
3528 params[si_shader_ctx->param_tes_rel_patch_id = num_params++] = i32;
3529 params[si_shader_ctx->param_tes_patch_id = num_params++] = i32;
3530 break;
3531
3532 case TGSI_PROCESSOR_GEOMETRY:
3533 params[SI_PARAM_GS2VS_OFFSET] = i32;
3534 params[SI_PARAM_GS_WAVE_ID] = i32;
3535 last_sgpr = SI_PARAM_GS_WAVE_ID;
3536
3537 /* VGPRs */
3538 params[SI_PARAM_VTX0_OFFSET] = i32;
3539 params[SI_PARAM_VTX1_OFFSET] = i32;
3540 params[SI_PARAM_PRIMITIVE_ID] = i32;
3541 params[SI_PARAM_VTX2_OFFSET] = i32;
3542 params[SI_PARAM_VTX3_OFFSET] = i32;
3543 params[SI_PARAM_VTX4_OFFSET] = i32;
3544 params[SI_PARAM_VTX5_OFFSET] = i32;
3545 params[SI_PARAM_GS_INSTANCE_ID] = i32;
3546 num_params = SI_PARAM_GS_INSTANCE_ID+1;
3547 break;
3548
3549 case TGSI_PROCESSOR_FRAGMENT:
3550 params[SI_PARAM_ALPHA_REF] = f32;
3551 params[SI_PARAM_PS_STATE_BITS] = i32;
3552 params[SI_PARAM_PRIM_MASK] = i32;
3553 last_sgpr = SI_PARAM_PRIM_MASK;
3554 params[SI_PARAM_PERSP_SAMPLE] = v2i32;
3555 params[SI_PARAM_PERSP_CENTER] = v2i32;
3556 params[SI_PARAM_PERSP_CENTROID] = v2i32;
3557 params[SI_PARAM_PERSP_PULL_MODEL] = v3i32;
3558 params[SI_PARAM_LINEAR_SAMPLE] = v2i32;
3559 params[SI_PARAM_LINEAR_CENTER] = v2i32;
3560 params[SI_PARAM_LINEAR_CENTROID] = v2i32;
3561 params[SI_PARAM_LINE_STIPPLE_TEX] = f32;
3562 params[SI_PARAM_POS_X_FLOAT] = f32;
3563 params[SI_PARAM_POS_Y_FLOAT] = f32;
3564 params[SI_PARAM_POS_Z_FLOAT] = f32;
3565 params[SI_PARAM_POS_W_FLOAT] = f32;
3566 params[SI_PARAM_FRONT_FACE] = f32;
3567 params[SI_PARAM_ANCILLARY] = i32;
3568 params[SI_PARAM_SAMPLE_COVERAGE] = f32;
3569 params[SI_PARAM_POS_FIXED_PT] = f32;
3570 num_params = SI_PARAM_POS_FIXED_PT+1;
3571 break;
3572
3573 default:
3574 assert(0 && "unimplemented shader");
3575 return;
3576 }
3577
3578 assert(num_params <= Elements(params));
3579 radeon_llvm_create_func(&si_shader_ctx->radeon_bld, params, num_params);
3580 radeon_llvm_shader_type(si_shader_ctx->radeon_bld.main_fn, si_shader_ctx->type);
3581
3582 if (shader->dx10_clamp_mode)
3583 LLVMAddTargetDependentFunctionAttr(si_shader_ctx->radeon_bld.main_fn,
3584 "enable-no-nans-fp-math", "true");
3585
3586 for (i = 0; i <= last_sgpr; ++i) {
3587 LLVMValueRef P = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, i);
3588
3589 /* We tell llvm that array inputs are passed by value to allow Sinking pass
3590 * to move load. Inputs are constant so this is fine. */
3591 if (i <= last_array_pointer)
3592 LLVMAddAttribute(P, LLVMByValAttribute);
3593 else
3594 LLVMAddAttribute(P, LLVMInRegAttribute);
3595 }
3596
3597 if (bld_base->info &&
3598 (bld_base->info->opcode_count[TGSI_OPCODE_DDX] > 0 ||
3599 bld_base->info->opcode_count[TGSI_OPCODE_DDY] > 0 ||
3600 bld_base->info->opcode_count[TGSI_OPCODE_DDX_FINE] > 0 ||
3601 bld_base->info->opcode_count[TGSI_OPCODE_DDY_FINE] > 0 ||
3602 bld_base->info->opcode_count[TGSI_OPCODE_INTERP_OFFSET] > 0 ||
3603 bld_base->info->opcode_count[TGSI_OPCODE_INTERP_SAMPLE] > 0))
3604 si_shader_ctx->lds =
3605 LLVMAddGlobalInAddressSpace(gallivm->module,
3606 LLVMArrayType(i32, 64),
3607 "ddxy_lds",
3608 LOCAL_ADDR_SPACE);
3609
3610 if ((si_shader_ctx->type == TGSI_PROCESSOR_VERTEX && shader->key.vs.as_ls) ||
3611 si_shader_ctx->type == TGSI_PROCESSOR_TESS_CTRL ||
3612 si_shader_ctx->type == TGSI_PROCESSOR_TESS_EVAL) {
3613 /* This is the upper bound, maximum is 32 inputs times 32 vertices */
3614 unsigned vertex_data_dw_size = 32*32*4;
3615 unsigned patch_data_dw_size = 32*4;
3616 /* The formula is: TCS inputs + TCS outputs + TCS patch outputs. */
3617 unsigned patch_dw_size = vertex_data_dw_size*2 + patch_data_dw_size;
3618 unsigned lds_dwords = patch_dw_size;
3619
3620 /* The actual size is computed outside of the shader to reduce
3621 * the number of shader variants. */
3622 si_shader_ctx->lds =
3623 LLVMAddGlobalInAddressSpace(gallivm->module,
3624 LLVMArrayType(i32, lds_dwords),
3625 "tess_lds",
3626 LOCAL_ADDR_SPACE);
3627 }
3628 }
3629
3630 static void preload_constants(struct si_shader_context *si_shader_ctx)
3631 {
3632 struct lp_build_tgsi_context * bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
3633 struct gallivm_state * gallivm = bld_base->base.gallivm;
3634 const struct tgsi_shader_info * info = bld_base->info;
3635 unsigned buf;
3636 LLVMValueRef ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_CONST);
3637
3638 for (buf = 0; buf < SI_NUM_CONST_BUFFERS; buf++) {
3639 unsigned i, num_const = info->const_file_max[buf] + 1;
3640
3641 if (num_const == 0)
3642 continue;
3643
3644 /* Allocate space for the constant values */
3645 si_shader_ctx->constants[buf] = CALLOC(num_const * 4, sizeof(LLVMValueRef));
3646
3647 /* Load the resource descriptor */
3648 si_shader_ctx->const_resource[buf] =
3649 build_indexed_load_const(si_shader_ctx, ptr, lp_build_const_int32(gallivm, buf));
3650
3651 /* Load the constants, we rely on the code sinking to do the rest */
3652 for (i = 0; i < num_const * 4; ++i) {
3653 si_shader_ctx->constants[buf][i] =
3654 buffer_load_const(gallivm->builder,
3655 si_shader_ctx->const_resource[buf],
3656 lp_build_const_int32(gallivm, i * 4),
3657 bld_base->base.elem_type);
3658 }
3659 }
3660 }
3661
3662 static void preload_samplers(struct si_shader_context *si_shader_ctx)
3663 {
3664 struct lp_build_tgsi_context * bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
3665 struct gallivm_state * gallivm = bld_base->base.gallivm;
3666 const struct tgsi_shader_info * info = bld_base->info;
3667
3668 unsigned i, num_samplers = info->file_max[TGSI_FILE_SAMPLER] + 1;
3669
3670 LLVMValueRef res_ptr, samp_ptr;
3671 LLVMValueRef offset;
3672
3673 if (num_samplers == 0)
3674 return;
3675
3676 res_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_RESOURCE);
3677 samp_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_SAMPLER);
3678
3679 /* Load the resources and samplers, we rely on the code sinking to do the rest */
3680 for (i = 0; i < num_samplers; ++i) {
3681 /* Resource */
3682 offset = lp_build_const_int32(gallivm, i);
3683 si_shader_ctx->resources[i] = build_indexed_load_const(si_shader_ctx, res_ptr, offset);
3684
3685 /* Sampler */
3686 offset = lp_build_const_int32(gallivm, i);
3687 si_shader_ctx->samplers[i] = build_indexed_load_const(si_shader_ctx, samp_ptr, offset);
3688
3689 /* FMASK resource */
3690 if (info->is_msaa_sampler[i]) {
3691 offset = lp_build_const_int32(gallivm, SI_FMASK_TEX_OFFSET + i);
3692 si_shader_ctx->resources[SI_FMASK_TEX_OFFSET + i] =
3693 build_indexed_load_const(si_shader_ctx, res_ptr, offset);
3694 }
3695 }
3696 }
3697
3698 static void preload_streamout_buffers(struct si_shader_context *si_shader_ctx)
3699 {
3700 struct lp_build_tgsi_context * bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
3701 struct gallivm_state * gallivm = bld_base->base.gallivm;
3702 unsigned i;
3703
3704 /* Streamout can only be used if the shader is compiled as VS. */
3705 if (!si_shader_ctx->shader->selector->so.num_outputs ||
3706 (si_shader_ctx->type == TGSI_PROCESSOR_VERTEX &&
3707 (si_shader_ctx->shader->key.vs.as_es ||
3708 si_shader_ctx->shader->key.vs.as_ls)) ||
3709 (si_shader_ctx->type == TGSI_PROCESSOR_TESS_EVAL &&
3710 si_shader_ctx->shader->key.tes.as_es))
3711 return;
3712
3713 LLVMValueRef buf_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
3714 SI_PARAM_RW_BUFFERS);
3715
3716 /* Load the resources, we rely on the code sinking to do the rest */
3717 for (i = 0; i < 4; ++i) {
3718 if (si_shader_ctx->shader->selector->so.stride[i]) {
3719 LLVMValueRef offset = lp_build_const_int32(gallivm,
3720 SI_SO_BUF_OFFSET + i);
3721
3722 si_shader_ctx->so_buffers[i] = build_indexed_load_const(si_shader_ctx, buf_ptr, offset);
3723 }
3724 }
3725 }
3726
3727 /**
3728 * Load ESGS and GSVS ring buffer resource descriptors and save the variables
3729 * for later use.
3730 */
3731 static void preload_ring_buffers(struct si_shader_context *si_shader_ctx)
3732 {
3733 struct gallivm_state *gallivm =
3734 si_shader_ctx->radeon_bld.soa.bld_base.base.gallivm;
3735
3736 LLVMValueRef buf_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
3737 SI_PARAM_RW_BUFFERS);
3738
3739 if ((si_shader_ctx->type == TGSI_PROCESSOR_VERTEX &&
3740 si_shader_ctx->shader->key.vs.as_es) ||
3741 (si_shader_ctx->type == TGSI_PROCESSOR_TESS_EVAL &&
3742 si_shader_ctx->shader->key.tes.as_es) ||
3743 si_shader_ctx->type == TGSI_PROCESSOR_GEOMETRY) {
3744 LLVMValueRef offset = lp_build_const_int32(gallivm, SI_RING_ESGS);
3745
3746 si_shader_ctx->esgs_ring =
3747 build_indexed_load_const(si_shader_ctx, buf_ptr, offset);
3748 }
3749
3750 if (si_shader_ctx->shader->is_gs_copy_shader) {
3751 LLVMValueRef offset = lp_build_const_int32(gallivm, SI_RING_GSVS);
3752
3753 si_shader_ctx->gsvs_ring[0] =
3754 build_indexed_load_const(si_shader_ctx, buf_ptr, offset);
3755 }
3756 if (si_shader_ctx->type == TGSI_PROCESSOR_GEOMETRY) {
3757 int i;
3758 for (i = 0; i < 4; i++) {
3759 LLVMValueRef offset = lp_build_const_int32(gallivm, SI_RING_GSVS + i);
3760
3761 si_shader_ctx->gsvs_ring[i] =
3762 build_indexed_load_const(si_shader_ctx, buf_ptr, offset);
3763 }
3764 }
3765 }
3766
3767 void si_shader_binary_read_config(const struct si_screen *sscreen,
3768 struct si_shader *shader,
3769 unsigned symbol_offset)
3770 {
3771 unsigned i;
3772 const unsigned char *config =
3773 radeon_shader_binary_config_start(&shader->binary,
3774 symbol_offset);
3775
3776 /* XXX: We may be able to emit some of these values directly rather than
3777 * extracting fields to be emitted later.
3778 */
3779
3780 for (i = 0; i < shader->binary.config_size_per_symbol; i+= 8) {
3781 unsigned reg = util_le32_to_cpu(*(uint32_t*)(config + i));
3782 unsigned value = util_le32_to_cpu(*(uint32_t*)(config + i + 4));
3783 switch (reg) {
3784 case R_00B028_SPI_SHADER_PGM_RSRC1_PS:
3785 case R_00B128_SPI_SHADER_PGM_RSRC1_VS:
3786 case R_00B228_SPI_SHADER_PGM_RSRC1_GS:
3787 case R_00B848_COMPUTE_PGM_RSRC1:
3788 shader->num_sgprs = MAX2(shader->num_sgprs, (G_00B028_SGPRS(value) + 1) * 8);
3789 shader->num_vgprs = MAX2(shader->num_vgprs, (G_00B028_VGPRS(value) + 1) * 4);
3790 shader->float_mode = G_00B028_FLOAT_MODE(value);
3791 break;
3792 case R_00B02C_SPI_SHADER_PGM_RSRC2_PS:
3793 shader->lds_size = MAX2(shader->lds_size, G_00B02C_EXTRA_LDS_SIZE(value));
3794 break;
3795 case R_00B84C_COMPUTE_PGM_RSRC2:
3796 shader->lds_size = MAX2(shader->lds_size, G_00B84C_LDS_SIZE(value));
3797 break;
3798 case R_0286CC_SPI_PS_INPUT_ENA:
3799 shader->spi_ps_input_ena = value;
3800 break;
3801 case R_0286E8_SPI_TMPRING_SIZE:
3802 case R_00B860_COMPUTE_TMPRING_SIZE:
3803 /* WAVESIZE is in units of 256 dwords. */
3804 shader->scratch_bytes_per_wave =
3805 G_00B860_WAVESIZE(value) * 256 * 4 * 1;
3806 break;
3807 default:
3808 fprintf(stderr, "Warning: Compiler emitted unknown "
3809 "config register: 0x%x\n", reg);
3810 break;
3811 }
3812 }
3813 }
3814
3815 void si_shader_apply_scratch_relocs(struct si_context *sctx,
3816 struct si_shader *shader,
3817 uint64_t scratch_va)
3818 {
3819 unsigned i;
3820 uint32_t scratch_rsrc_dword0 = scratch_va;
3821 uint32_t scratch_rsrc_dword1 =
3822 S_008F04_BASE_ADDRESS_HI(scratch_va >> 32)
3823 | S_008F04_STRIDE(shader->scratch_bytes_per_wave / 64);
3824
3825 for (i = 0 ; i < shader->binary.reloc_count; i++) {
3826 const struct radeon_shader_reloc *reloc =
3827 &shader->binary.relocs[i];
3828 if (!strcmp(scratch_rsrc_dword0_symbol, reloc->name)) {
3829 util_memcpy_cpu_to_le32(shader->binary.code + reloc->offset,
3830 &scratch_rsrc_dword0, 4);
3831 } else if (!strcmp(scratch_rsrc_dword1_symbol, reloc->name)) {
3832 util_memcpy_cpu_to_le32(shader->binary.code + reloc->offset,
3833 &scratch_rsrc_dword1, 4);
3834 }
3835 }
3836 }
3837
3838 int si_shader_binary_upload(struct si_screen *sscreen, struct si_shader *shader)
3839 {
3840 const struct radeon_shader_binary *binary = &shader->binary;
3841 unsigned code_size = binary->code_size + binary->rodata_size;
3842 unsigned char *ptr;
3843
3844 r600_resource_reference(&shader->bo, NULL);
3845 shader->bo = si_resource_create_custom(&sscreen->b.b,
3846 PIPE_USAGE_IMMUTABLE,
3847 code_size);
3848 if (!shader->bo)
3849 return -ENOMEM;
3850
3851 ptr = sscreen->b.ws->buffer_map(shader->bo->cs_buf, NULL,
3852 PIPE_TRANSFER_READ_WRITE);
3853 util_memcpy_cpu_to_le32(ptr, binary->code, binary->code_size);
3854 if (binary->rodata_size > 0) {
3855 ptr += binary->code_size;
3856 util_memcpy_cpu_to_le32(ptr, binary->rodata,
3857 binary->rodata_size);
3858 }
3859
3860 sscreen->b.ws->buffer_unmap(shader->bo->cs_buf);
3861 return 0;
3862 }
3863
3864 int si_shader_binary_read(struct si_screen *sscreen, struct si_shader *shader)
3865 {
3866 const struct radeon_shader_binary *binary = &shader->binary;
3867 unsigned i;
3868 int r;
3869 bool dump = r600_can_dump_shader(&sscreen->b,
3870 shader->selector ? shader->selector->tokens : NULL);
3871
3872 si_shader_binary_read_config(sscreen, shader, 0);
3873 r = si_shader_binary_upload(sscreen, shader);
3874 if (r)
3875 return r;
3876
3877 if (dump) {
3878 if (!(sscreen->b.debug_flags & DBG_NO_ASM)) {
3879 if (binary->disasm_string) {
3880 fprintf(stderr, "\nShader Disassembly:\n\n");
3881 fprintf(stderr, "%s\n", binary->disasm_string);
3882 } else {
3883 fprintf(stderr, "SI CODE:\n");
3884 for (i = 0; i < binary->code_size; i+=4 ) {
3885 fprintf(stderr, "@0x%x: %02x%02x%02x%02x\n", i, binary->code[i + 3],
3886 binary->code[i + 2], binary->code[i + 1],
3887 binary->code[i]);
3888 }
3889 }
3890 }
3891
3892 fprintf(stderr, "*** SHADER STATS ***\n"
3893 "SGPRS: %d\nVGPRS: %d\nCode Size: %d bytes\nLDS: %d blocks\n"
3894 "Scratch: %d bytes per wave\n********************\n",
3895 shader->num_sgprs, shader->num_vgprs, binary->code_size,
3896 shader->lds_size, shader->scratch_bytes_per_wave);
3897 }
3898 return 0;
3899 }
3900
3901 int si_compile_llvm(struct si_screen *sscreen, struct si_shader *shader,
3902 LLVMTargetMachineRef tm, LLVMModuleRef mod)
3903 {
3904 int r = 0;
3905 bool dump_asm = r600_can_dump_shader(&sscreen->b,
3906 shader->selector ? shader->selector->tokens : NULL);
3907 bool dump_ir = dump_asm && !(sscreen->b.debug_flags & DBG_NO_IR);
3908
3909 r = radeon_llvm_compile(mod, &shader->binary,
3910 r600_get_llvm_processor_name(sscreen->b.family), dump_ir, dump_asm, tm);
3911 if (r)
3912 return r;
3913
3914 r = si_shader_binary_read(sscreen, shader);
3915
3916 FREE(shader->binary.config);
3917 FREE(shader->binary.rodata);
3918 FREE(shader->binary.global_symbol_offsets);
3919 if (shader->scratch_bytes_per_wave == 0) {
3920 FREE(shader->binary.code);
3921 FREE(shader->binary.relocs);
3922 memset(&shader->binary, 0,
3923 offsetof(struct radeon_shader_binary, disasm_string));
3924 }
3925 return r;
3926 }
3927
3928 /* Generate code for the hardware VS shader stage to go with a geometry shader */
3929 static int si_generate_gs_copy_shader(struct si_screen *sscreen,
3930 struct si_shader_context *si_shader_ctx,
3931 struct si_shader *gs, bool dump)
3932 {
3933 struct gallivm_state *gallivm = &si_shader_ctx->radeon_bld.gallivm;
3934 struct lp_build_tgsi_context *bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
3935 struct lp_build_context *base = &bld_base->base;
3936 struct lp_build_context *uint = &bld_base->uint_bld;
3937 struct si_shader *shader = si_shader_ctx->shader;
3938 struct si_shader_output_values *outputs;
3939 struct tgsi_shader_info *gsinfo = &gs->selector->info;
3940 LLVMValueRef args[9];
3941 int i, r;
3942
3943 outputs = MALLOC(gsinfo->num_outputs * sizeof(outputs[0]));
3944
3945 si_shader_ctx->type = TGSI_PROCESSOR_VERTEX;
3946 shader->is_gs_copy_shader = true;
3947
3948 radeon_llvm_context_init(&si_shader_ctx->radeon_bld);
3949
3950 create_meta_data(si_shader_ctx);
3951 create_function(si_shader_ctx);
3952 preload_streamout_buffers(si_shader_ctx);
3953 preload_ring_buffers(si_shader_ctx);
3954
3955 args[0] = si_shader_ctx->gsvs_ring[0];
3956 args[1] = lp_build_mul_imm(uint,
3957 LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
3958 si_shader_ctx->param_vertex_id),
3959 4);
3960 args[3] = uint->zero;
3961 args[4] = uint->one; /* OFFEN */
3962 args[5] = uint->zero; /* IDXEN */
3963 args[6] = uint->one; /* GLC */
3964 args[7] = uint->one; /* SLC */
3965 args[8] = uint->zero; /* TFE */
3966
3967 /* Fetch vertex data from GSVS ring */
3968 for (i = 0; i < gsinfo->num_outputs; ++i) {
3969 unsigned chan;
3970
3971 outputs[i].name = gsinfo->output_semantic_name[i];
3972 outputs[i].sid = gsinfo->output_semantic_index[i];
3973
3974 for (chan = 0; chan < 4; chan++) {
3975 args[2] = lp_build_const_int32(gallivm,
3976 (i * 4 + chan) *
3977 gs->selector->gs_max_out_vertices * 16 * 4);
3978
3979 outputs[i].values[chan] =
3980 LLVMBuildBitCast(gallivm->builder,
3981 lp_build_intrinsic(gallivm->builder,
3982 "llvm.SI.buffer.load.dword.i32.i32",
3983 LLVMInt32TypeInContext(gallivm->context),
3984 args, 9,
3985 LLVMReadOnlyAttribute | LLVMNoUnwindAttribute),
3986 base->elem_type, "");
3987 }
3988 }
3989
3990 si_llvm_export_vs(bld_base, outputs, gsinfo->num_outputs);
3991
3992 radeon_llvm_finalize_module(&si_shader_ctx->radeon_bld);
3993
3994 if (dump)
3995 fprintf(stderr, "Copy Vertex Shader for Geometry Shader:\n\n");
3996
3997 r = si_compile_llvm(sscreen, si_shader_ctx->shader,
3998 si_shader_ctx->tm, bld_base->base.gallivm->module);
3999
4000 radeon_llvm_dispose(&si_shader_ctx->radeon_bld);
4001
4002 FREE(outputs);
4003 return r;
4004 }
4005
4006 void si_dump_shader_key(unsigned shader, union si_shader_key *key, FILE *f)
4007 {
4008 int i;
4009
4010 fprintf(f, "SHADER KEY\n");
4011
4012 switch (shader) {
4013 case PIPE_SHADER_VERTEX:
4014 fprintf(f, " instance_divisors = {");
4015 for (i = 0; i < Elements(key->vs.instance_divisors); i++)
4016 fprintf(f, !i ? "%u" : ", %u",
4017 key->vs.instance_divisors[i]);
4018 fprintf(f, "}\n");
4019 fprintf(f, " as_es = %u\n", key->vs.as_es);
4020 fprintf(f, " as_ls = %u\n", key->vs.as_ls);
4021 fprintf(f, " export_prim_id = %u\n", key->vs.export_prim_id);
4022 break;
4023
4024 case PIPE_SHADER_TESS_CTRL:
4025 fprintf(f, " prim_mode = %u\n", key->tcs.prim_mode);
4026 break;
4027
4028 case PIPE_SHADER_TESS_EVAL:
4029 fprintf(f, " as_es = %u\n", key->tes.as_es);
4030 fprintf(f, " export_prim_id = %u\n", key->tes.export_prim_id);
4031 break;
4032
4033 case PIPE_SHADER_GEOMETRY:
4034 break;
4035
4036 case PIPE_SHADER_FRAGMENT:
4037 fprintf(f, " export_16bpc = 0x%X\n", key->ps.export_16bpc);
4038 fprintf(f, " last_cbuf = %u\n", key->ps.last_cbuf);
4039 fprintf(f, " color_two_side = %u\n", key->ps.color_two_side);
4040 fprintf(f, " alpha_func = %u\n", key->ps.alpha_func);
4041 fprintf(f, " alpha_to_one = %u\n", key->ps.alpha_to_one);
4042 fprintf(f, " poly_stipple = %u\n", key->ps.poly_stipple);
4043 fprintf(f, " clamp_color = %u\n", key->ps.clamp_color);
4044 break;
4045
4046 default:
4047 assert(0);
4048 }
4049 }
4050
4051 int si_shader_create(struct si_screen *sscreen, LLVMTargetMachineRef tm,
4052 struct si_shader *shader)
4053 {
4054 struct si_shader_selector *sel = shader->selector;
4055 struct tgsi_token *tokens = sel->tokens;
4056 struct si_shader_context si_shader_ctx;
4057 struct lp_build_tgsi_context * bld_base;
4058 struct tgsi_shader_info stipple_shader_info;
4059 LLVMModuleRef mod;
4060 int r = 0;
4061 bool poly_stipple = sel->type == PIPE_SHADER_FRAGMENT &&
4062 shader->key.ps.poly_stipple;
4063 bool dump = r600_can_dump_shader(&sscreen->b, sel->tokens);
4064
4065 if (poly_stipple) {
4066 tokens = util_pstipple_create_fragment_shader(tokens, NULL,
4067 SI_POLY_STIPPLE_SAMPLER);
4068 tgsi_scan_shader(tokens, &stipple_shader_info);
4069 }
4070
4071 /* Dump TGSI code before doing TGSI->LLVM conversion in case the
4072 * conversion fails. */
4073 if (dump && !(sscreen->b.debug_flags & DBG_NO_TGSI)) {
4074 si_dump_shader_key(sel->type, &shader->key, stderr);
4075 tgsi_dump(tokens, 0);
4076 si_dump_streamout(&sel->so);
4077 }
4078
4079 assert(shader->nparam == 0);
4080
4081 memset(&si_shader_ctx, 0, sizeof(si_shader_ctx));
4082 radeon_llvm_context_init(&si_shader_ctx.radeon_bld);
4083 bld_base = &si_shader_ctx.radeon_bld.soa.bld_base;
4084
4085 if (sel->type != PIPE_SHADER_COMPUTE)
4086 shader->dx10_clamp_mode = true;
4087
4088 if (sel->info.uses_kill)
4089 shader->db_shader_control |= S_02880C_KILL_ENABLE(1);
4090
4091 shader->uses_instanceid = sel->info.uses_instanceid;
4092 bld_base->info = poly_stipple ? &stipple_shader_info : &sel->info;
4093 bld_base->emit_fetch_funcs[TGSI_FILE_CONSTANT] = fetch_constant;
4094
4095 bld_base->op_actions[TGSI_OPCODE_INTERP_CENTROID] = interp_action;
4096 bld_base->op_actions[TGSI_OPCODE_INTERP_SAMPLE] = interp_action;
4097 bld_base->op_actions[TGSI_OPCODE_INTERP_OFFSET] = interp_action;
4098
4099 bld_base->op_actions[TGSI_OPCODE_TEX] = tex_action;
4100 bld_base->op_actions[TGSI_OPCODE_TEX2] = tex_action;
4101 bld_base->op_actions[TGSI_OPCODE_TXB] = tex_action;
4102 bld_base->op_actions[TGSI_OPCODE_TXB2] = tex_action;
4103 bld_base->op_actions[TGSI_OPCODE_TXD] = tex_action;
4104 bld_base->op_actions[TGSI_OPCODE_TXF] = tex_action;
4105 bld_base->op_actions[TGSI_OPCODE_TXL] = tex_action;
4106 bld_base->op_actions[TGSI_OPCODE_TXL2] = tex_action;
4107 bld_base->op_actions[TGSI_OPCODE_TXP] = tex_action;
4108 bld_base->op_actions[TGSI_OPCODE_TXQ] = tex_action;
4109 bld_base->op_actions[TGSI_OPCODE_TG4] = tex_action;
4110 bld_base->op_actions[TGSI_OPCODE_LODQ] = tex_action;
4111 bld_base->op_actions[TGSI_OPCODE_TXQS].emit = si_llvm_emit_txqs;
4112
4113 bld_base->op_actions[TGSI_OPCODE_DDX].emit = si_llvm_emit_ddxy;
4114 bld_base->op_actions[TGSI_OPCODE_DDY].emit = si_llvm_emit_ddxy;
4115 bld_base->op_actions[TGSI_OPCODE_DDX_FINE].emit = si_llvm_emit_ddxy;
4116 bld_base->op_actions[TGSI_OPCODE_DDY_FINE].emit = si_llvm_emit_ddxy;
4117
4118 bld_base->op_actions[TGSI_OPCODE_EMIT].emit = si_llvm_emit_vertex;
4119 bld_base->op_actions[TGSI_OPCODE_ENDPRIM].emit = si_llvm_emit_primitive;
4120 bld_base->op_actions[TGSI_OPCODE_BARRIER].emit = si_llvm_emit_barrier;
4121
4122 if (HAVE_LLVM >= 0x0306) {
4123 bld_base->op_actions[TGSI_OPCODE_MAX].emit = build_tgsi_intrinsic_nomem;
4124 bld_base->op_actions[TGSI_OPCODE_MAX].intr_name = "llvm.maxnum.f32";
4125 bld_base->op_actions[TGSI_OPCODE_MIN].emit = build_tgsi_intrinsic_nomem;
4126 bld_base->op_actions[TGSI_OPCODE_MIN].intr_name = "llvm.minnum.f32";
4127 }
4128
4129 si_shader_ctx.radeon_bld.load_system_value = declare_system_value;
4130 si_shader_ctx.shader = shader;
4131 si_shader_ctx.type = tgsi_get_processor_type(tokens);
4132 si_shader_ctx.screen = sscreen;
4133 si_shader_ctx.tm = tm;
4134
4135 switch (si_shader_ctx.type) {
4136 case TGSI_PROCESSOR_VERTEX:
4137 si_shader_ctx.radeon_bld.load_input = declare_input_vs;
4138 if (shader->key.vs.as_ls)
4139 bld_base->emit_epilogue = si_llvm_emit_ls_epilogue;
4140 else if (shader->key.vs.as_es)
4141 bld_base->emit_epilogue = si_llvm_emit_es_epilogue;
4142 else
4143 bld_base->emit_epilogue = si_llvm_emit_vs_epilogue;
4144 break;
4145 case TGSI_PROCESSOR_TESS_CTRL:
4146 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_tcs;
4147 bld_base->emit_fetch_funcs[TGSI_FILE_OUTPUT] = fetch_output_tcs;
4148 bld_base->emit_store = store_output_tcs;
4149 bld_base->emit_epilogue = si_llvm_emit_tcs_epilogue;
4150 break;
4151 case TGSI_PROCESSOR_TESS_EVAL:
4152 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_tes;
4153 if (shader->key.tes.as_es)
4154 bld_base->emit_epilogue = si_llvm_emit_es_epilogue;
4155 else
4156 bld_base->emit_epilogue = si_llvm_emit_vs_epilogue;
4157 break;
4158 case TGSI_PROCESSOR_GEOMETRY:
4159 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_gs;
4160 bld_base->emit_epilogue = si_llvm_emit_gs_epilogue;
4161 break;
4162 case TGSI_PROCESSOR_FRAGMENT:
4163 si_shader_ctx.radeon_bld.load_input = declare_input_fs;
4164 bld_base->emit_epilogue = si_llvm_emit_fs_epilogue;
4165
4166 switch (sel->info.properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT]) {
4167 case TGSI_FS_DEPTH_LAYOUT_GREATER:
4168 shader->db_shader_control |=
4169 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_GREATER_THAN_Z);
4170 break;
4171 case TGSI_FS_DEPTH_LAYOUT_LESS:
4172 shader->db_shader_control |=
4173 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_LESS_THAN_Z);
4174 break;
4175 }
4176 break;
4177 default:
4178 assert(!"Unsupported shader type");
4179 return -1;
4180 }
4181
4182 create_meta_data(&si_shader_ctx);
4183 create_function(&si_shader_ctx);
4184 preload_constants(&si_shader_ctx);
4185 preload_samplers(&si_shader_ctx);
4186 preload_streamout_buffers(&si_shader_ctx);
4187 preload_ring_buffers(&si_shader_ctx);
4188
4189 if (si_shader_ctx.type == TGSI_PROCESSOR_GEOMETRY) {
4190 int i;
4191 for (i = 0; i < 4; i++) {
4192 si_shader_ctx.gs_next_vertex[i] =
4193 lp_build_alloca(bld_base->base.gallivm,
4194 bld_base->uint_bld.elem_type, "");
4195 }
4196 }
4197
4198 if (!lp_build_tgsi_llvm(bld_base, tokens)) {
4199 fprintf(stderr, "Failed to translate shader from TGSI to LLVM\n");
4200 goto out;
4201 }
4202
4203 radeon_llvm_finalize_module(&si_shader_ctx.radeon_bld);
4204
4205 mod = bld_base->base.gallivm->module;
4206 r = si_compile_llvm(sscreen, shader, tm, mod);
4207 if (r) {
4208 fprintf(stderr, "LLVM failed to compile shader\n");
4209 goto out;
4210 }
4211
4212 radeon_llvm_dispose(&si_shader_ctx.radeon_bld);
4213
4214 if (si_shader_ctx.type == TGSI_PROCESSOR_GEOMETRY) {
4215 shader->gs_copy_shader = CALLOC_STRUCT(si_shader);
4216 shader->gs_copy_shader->selector = shader->selector;
4217 shader->gs_copy_shader->key = shader->key;
4218 si_shader_ctx.shader = shader->gs_copy_shader;
4219 if ((r = si_generate_gs_copy_shader(sscreen, &si_shader_ctx,
4220 shader, dump))) {
4221 free(shader->gs_copy_shader);
4222 shader->gs_copy_shader = NULL;
4223 goto out;
4224 }
4225 }
4226
4227 out:
4228 for (int i = 0; i < SI_NUM_CONST_BUFFERS; i++)
4229 FREE(si_shader_ctx.constants[i]);
4230 if (poly_stipple)
4231 tgsi_free_tokens(tokens);
4232 return r;
4233 }
4234
4235 void si_shader_destroy(struct si_shader *shader)
4236 {
4237 if (shader->gs_copy_shader) {
4238 si_shader_destroy(shader->gs_copy_shader);
4239 FREE(shader->gs_copy_shader);
4240 }
4241
4242 if (shader->scratch_bo)
4243 r600_resource_reference(&shader->scratch_bo, NULL);
4244
4245 r600_resource_reference(&shader->bo, NULL);
4246
4247 FREE(shader->binary.code);
4248 FREE(shader->binary.relocs);
4249 FREE(shader->binary.disasm_string);
4250 }