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radeonsi: fix VertexID for OpenGL
[mesa.git] / src / gallium / drivers / radeonsi / si_shader.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Tom Stellard <thomas.stellard@amd.com>
25 * Michel Dänzer <michel.daenzer@amd.com>
26 * Christian König <christian.koenig@amd.com>
27 */
28
29 #include "gallivm/lp_bld_const.h"
30 #include "gallivm/lp_bld_gather.h"
31 #include "gallivm/lp_bld_intr.h"
32 #include "gallivm/lp_bld_logic.h"
33 #include "gallivm/lp_bld_arit.h"
34 #include "gallivm/lp_bld_flow.h"
35 #include "radeon/radeon_llvm.h"
36 #include "radeon/radeon_elf_util.h"
37 #include "radeon/radeon_llvm_emit.h"
38 #include "util/u_memory.h"
39 #include "tgsi/tgsi_parse.h"
40 #include "tgsi/tgsi_util.h"
41 #include "tgsi/tgsi_dump.h"
42
43 #include "si_pipe.h"
44 #include "si_shader.h"
45 #include "sid.h"
46
47 #include <errno.h>
48
49 struct si_shader_output_values
50 {
51 LLVMValueRef values[4];
52 unsigned name;
53 unsigned sid;
54 };
55
56 struct si_shader_context
57 {
58 struct radeon_llvm_context radeon_bld;
59 struct tgsi_parse_context parse;
60 struct tgsi_token * tokens;
61 struct si_shader *shader;
62 struct si_screen *screen;
63 unsigned type; /* TGSI_PROCESSOR_* specifies the type of shader. */
64 int param_streamout_config;
65 int param_streamout_write_index;
66 int param_streamout_offset[4];
67 int param_vertex_id;
68 int param_instance_id;
69 LLVMValueRef const_md;
70 LLVMValueRef const_resource[SI_NUM_CONST_BUFFERS];
71 LLVMValueRef ddxy_lds;
72 LLVMValueRef *constants[SI_NUM_CONST_BUFFERS];
73 LLVMValueRef resources[SI_NUM_SAMPLER_VIEWS];
74 LLVMValueRef samplers[SI_NUM_SAMPLER_STATES];
75 LLVMValueRef so_buffers[4];
76 LLVMValueRef esgs_ring;
77 LLVMValueRef gsvs_ring;
78 LLVMValueRef gs_next_vertex;
79 };
80
81 static struct si_shader_context * si_shader_context(
82 struct lp_build_tgsi_context * bld_base)
83 {
84 return (struct si_shader_context *)bld_base;
85 }
86
87
88 #define PERSPECTIVE_BASE 0
89 #define LINEAR_BASE 9
90
91 #define SAMPLE_OFFSET 0
92 #define CENTER_OFFSET 2
93 #define CENTROID_OFSET 4
94
95 #define USE_SGPR_MAX_SUFFIX_LEN 5
96 #define CONST_ADDR_SPACE 2
97 #define LOCAL_ADDR_SPACE 3
98 #define USER_SGPR_ADDR_SPACE 8
99
100
101 #define SENDMSG_GS 2
102 #define SENDMSG_GS_DONE 3
103
104 #define SENDMSG_GS_OP_NOP (0 << 4)
105 #define SENDMSG_GS_OP_CUT (1 << 4)
106 #define SENDMSG_GS_OP_EMIT (2 << 4)
107 #define SENDMSG_GS_OP_EMIT_CUT (3 << 4)
108
109 /**
110 * Returns a unique index for a semantic name and index. The index must be
111 * less than 64, so that a 64-bit bitmask of used inputs or outputs can be
112 * calculated.
113 */
114 unsigned si_shader_io_get_unique_index(unsigned semantic_name, unsigned index)
115 {
116 switch (semantic_name) {
117 case TGSI_SEMANTIC_POSITION:
118 return 0;
119 case TGSI_SEMANTIC_PSIZE:
120 return 1;
121 case TGSI_SEMANTIC_CLIPDIST:
122 assert(index <= 1);
123 return 2 + index;
124 case TGSI_SEMANTIC_CLIPVERTEX:
125 return 4;
126 case TGSI_SEMANTIC_COLOR:
127 assert(index <= 1);
128 return 5 + index;
129 case TGSI_SEMANTIC_BCOLOR:
130 assert(index <= 1);
131 return 7 + index;
132 case TGSI_SEMANTIC_FOG:
133 return 9;
134 case TGSI_SEMANTIC_EDGEFLAG:
135 return 10;
136 case TGSI_SEMANTIC_GENERIC:
137 assert(index <= 63-11);
138 return 11 + index;
139 default:
140 assert(0);
141 return 63;
142 }
143 }
144
145 /**
146 * Given a semantic name and index of a parameter and a mask of used parameters
147 * (inputs or outputs), return the index of the parameter in the list of all
148 * used parameters.
149 *
150 * For example, assume this list of parameters:
151 * POSITION, PSIZE, GENERIC0, GENERIC2
152 * which has the mask:
153 * 11000000000101
154 * Then:
155 * querying POSITION returns 0,
156 * querying PSIZE returns 1,
157 * querying GENERIC0 returns 2,
158 * querying GENERIC2 returns 3.
159 *
160 * Which can be used as an offset to a parameter buffer in units of vec4s.
161 */
162 static int get_param_index(unsigned semantic_name, unsigned index,
163 uint64_t mask)
164 {
165 unsigned unique_index = si_shader_io_get_unique_index(semantic_name, index);
166 int i, param_index = 0;
167
168 /* If not present... */
169 if (!((1llu << unique_index) & mask))
170 return -1;
171
172 for (i = 0; mask; i++) {
173 uint64_t bit = 1llu << i;
174
175 if (bit & mask) {
176 if (i == unique_index)
177 return param_index;
178
179 mask &= ~bit;
180 param_index++;
181 }
182 }
183
184 assert(!"unreachable");
185 return -1;
186 }
187
188 /**
189 * Build an LLVM bytecode indexed load using LLVMBuildGEP + LLVMBuildLoad.
190 * It's equivalent to doing a load from &base_ptr[index].
191 *
192 * \param base_ptr Where the array starts.
193 * \param index The element index into the array.
194 */
195 static LLVMValueRef build_indexed_load(struct si_shader_context *si_shader_ctx,
196 LLVMValueRef base_ptr, LLVMValueRef index)
197 {
198 struct lp_build_tgsi_context *bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
199 struct gallivm_state *gallivm = bld_base->base.gallivm;
200 LLVMValueRef indices[2], pointer;
201
202 indices[0] = bld_base->uint_bld.zero;
203 indices[1] = index;
204
205 pointer = LLVMBuildGEP(gallivm->builder, base_ptr, indices, 2, "");
206 return LLVMBuildLoad(gallivm->builder, pointer, "");
207 }
208
209 /**
210 * Do a load from &base_ptr[index], but also add a flag that it's loading
211 * a constant.
212 */
213 static LLVMValueRef build_indexed_load_const(
214 struct si_shader_context * si_shader_ctx,
215 LLVMValueRef base_ptr, LLVMValueRef index)
216 {
217 LLVMValueRef result = build_indexed_load(si_shader_ctx, base_ptr, index);
218 LLVMSetMetadata(result, 1, si_shader_ctx->const_md);
219 return result;
220 }
221
222 static LLVMValueRef get_instance_index_for_fetch(
223 struct radeon_llvm_context * radeon_bld,
224 unsigned divisor)
225 {
226 struct si_shader_context *si_shader_ctx =
227 si_shader_context(&radeon_bld->soa.bld_base);
228 struct gallivm_state * gallivm = radeon_bld->soa.bld_base.base.gallivm;
229
230 LLVMValueRef result = LLVMGetParam(radeon_bld->main_fn,
231 si_shader_ctx->param_instance_id);
232 result = LLVMBuildAdd(gallivm->builder, result, LLVMGetParam(
233 radeon_bld->main_fn, SI_PARAM_START_INSTANCE), "");
234
235 if (divisor > 1)
236 result = LLVMBuildUDiv(gallivm->builder, result,
237 lp_build_const_int32(gallivm, divisor), "");
238
239 return result;
240 }
241
242 static void declare_input_vs(
243 struct radeon_llvm_context *radeon_bld,
244 unsigned input_index,
245 const struct tgsi_full_declaration *decl)
246 {
247 struct lp_build_context *base = &radeon_bld->soa.bld_base.base;
248 struct gallivm_state *gallivm = base->gallivm;
249 struct si_shader_context *si_shader_ctx =
250 si_shader_context(&radeon_bld->soa.bld_base);
251 unsigned divisor = si_shader_ctx->shader->key.vs.instance_divisors[input_index];
252
253 unsigned chan;
254
255 LLVMValueRef t_list_ptr;
256 LLVMValueRef t_offset;
257 LLVMValueRef t_list;
258 LLVMValueRef attribute_offset;
259 LLVMValueRef buffer_index;
260 LLVMValueRef args[3];
261 LLVMTypeRef vec4_type;
262 LLVMValueRef input;
263
264 /* Load the T list */
265 t_list_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_VERTEX_BUFFER);
266
267 t_offset = lp_build_const_int32(gallivm, input_index);
268
269 t_list = build_indexed_load_const(si_shader_ctx, t_list_ptr, t_offset);
270
271 /* Build the attribute offset */
272 attribute_offset = lp_build_const_int32(gallivm, 0);
273
274 if (divisor) {
275 /* Build index from instance ID, start instance and divisor */
276 si_shader_ctx->shader->uses_instanceid = true;
277 buffer_index = get_instance_index_for_fetch(&si_shader_ctx->radeon_bld, divisor);
278 } else {
279 /* Load the buffer index for vertices. */
280 LLVMValueRef vertex_id = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
281 si_shader_ctx->param_vertex_id);
282 LLVMValueRef base_vertex = LLVMGetParam(radeon_bld->main_fn,
283 SI_PARAM_BASE_VERTEX);
284 buffer_index = LLVMBuildAdd(gallivm->builder, base_vertex, vertex_id, "");
285 }
286
287 vec4_type = LLVMVectorType(base->elem_type, 4);
288 args[0] = t_list;
289 args[1] = attribute_offset;
290 args[2] = buffer_index;
291 input = build_intrinsic(gallivm->builder,
292 "llvm.SI.vs.load.input", vec4_type, args, 3,
293 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
294
295 /* Break up the vec4 into individual components */
296 for (chan = 0; chan < 4; chan++) {
297 LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan);
298 /* XXX: Use a helper function for this. There is one in
299 * tgsi_llvm.c. */
300 si_shader_ctx->radeon_bld.inputs[radeon_llvm_reg_index_soa(input_index, chan)] =
301 LLVMBuildExtractElement(gallivm->builder,
302 input, llvm_chan, "");
303 }
304 }
305
306 static LLVMValueRef fetch_input_gs(
307 struct lp_build_tgsi_context *bld_base,
308 const struct tgsi_full_src_register *reg,
309 enum tgsi_opcode_type type,
310 unsigned swizzle)
311 {
312 struct lp_build_context *base = &bld_base->base;
313 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
314 struct si_shader *shader = si_shader_ctx->shader;
315 struct lp_build_context *uint = &si_shader_ctx->radeon_bld.soa.bld_base.uint_bld;
316 struct gallivm_state *gallivm = base->gallivm;
317 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
318 LLVMValueRef vtx_offset;
319 LLVMValueRef args[9];
320 unsigned vtx_offset_param;
321 struct tgsi_shader_info *info = &shader->selector->info;
322 unsigned semantic_name = info->input_semantic_name[reg->Register.Index];
323 unsigned semantic_index = info->input_semantic_index[reg->Register.Index];
324
325 if (swizzle != ~0 && semantic_name == TGSI_SEMANTIC_PRIMID) {
326 if (swizzle == 0)
327 return LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
328 SI_PARAM_PRIMITIVE_ID);
329 else
330 return uint->zero;
331 }
332
333 if (!reg->Register.Dimension)
334 return NULL;
335
336 if (swizzle == ~0) {
337 LLVMValueRef values[TGSI_NUM_CHANNELS];
338 unsigned chan;
339 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
340 values[chan] = fetch_input_gs(bld_base, reg, type, chan);
341 }
342 return lp_build_gather_values(bld_base->base.gallivm, values,
343 TGSI_NUM_CHANNELS);
344 }
345
346 /* Get the vertex offset parameter */
347 vtx_offset_param = reg->Dimension.Index;
348 if (vtx_offset_param < 2) {
349 vtx_offset_param += SI_PARAM_VTX0_OFFSET;
350 } else {
351 assert(vtx_offset_param < 6);
352 vtx_offset_param += SI_PARAM_VTX2_OFFSET - 2;
353 }
354 vtx_offset = lp_build_mul_imm(uint,
355 LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
356 vtx_offset_param),
357 4);
358
359 args[0] = si_shader_ctx->esgs_ring;
360 args[1] = vtx_offset;
361 args[2] = lp_build_const_int32(gallivm,
362 (get_param_index(semantic_name, semantic_index,
363 shader->selector->gs_used_inputs) * 4 +
364 swizzle) * 256);
365 args[3] = uint->zero;
366 args[4] = uint->one; /* OFFEN */
367 args[5] = uint->zero; /* IDXEN */
368 args[6] = uint->one; /* GLC */
369 args[7] = uint->zero; /* SLC */
370 args[8] = uint->zero; /* TFE */
371
372 return LLVMBuildBitCast(gallivm->builder,
373 build_intrinsic(gallivm->builder,
374 "llvm.SI.buffer.load.dword.i32.i32",
375 i32, args, 9,
376 LLVMReadOnlyAttribute | LLVMNoUnwindAttribute),
377 tgsi2llvmtype(bld_base, type), "");
378 }
379
380 static void declare_input_fs(
381 struct radeon_llvm_context *radeon_bld,
382 unsigned input_index,
383 const struct tgsi_full_declaration *decl)
384 {
385 struct lp_build_context *base = &radeon_bld->soa.bld_base.base;
386 struct si_shader_context *si_shader_ctx =
387 si_shader_context(&radeon_bld->soa.bld_base);
388 struct si_shader *shader = si_shader_ctx->shader;
389 struct lp_build_context *uint = &radeon_bld->soa.bld_base.uint_bld;
390 struct gallivm_state *gallivm = base->gallivm;
391 LLVMTypeRef input_type = LLVMFloatTypeInContext(gallivm->context);
392 LLVMValueRef main_fn = radeon_bld->main_fn;
393
394 LLVMValueRef interp_param;
395 const char * intr_name;
396
397 /* This value is:
398 * [15:0] NewPrimMask (Bit mask for each quad. It is set it the
399 * quad begins a new primitive. Bit 0 always needs
400 * to be unset)
401 * [32:16] ParamOffset
402 *
403 */
404 LLVMValueRef params = LLVMGetParam(main_fn, SI_PARAM_PRIM_MASK);
405 LLVMValueRef attr_number;
406
407 unsigned chan;
408
409 if (decl->Semantic.Name == TGSI_SEMANTIC_POSITION) {
410 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
411 unsigned soa_index =
412 radeon_llvm_reg_index_soa(input_index, chan);
413 radeon_bld->inputs[soa_index] =
414 LLVMGetParam(main_fn, SI_PARAM_POS_X_FLOAT + chan);
415
416 if (chan == 3)
417 /* RCP for fragcoord.w */
418 radeon_bld->inputs[soa_index] =
419 LLVMBuildFDiv(gallivm->builder,
420 lp_build_const_float(gallivm, 1.0f),
421 radeon_bld->inputs[soa_index],
422 "");
423 }
424 return;
425 }
426
427 if (decl->Semantic.Name == TGSI_SEMANTIC_FACE) {
428 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 0)] =
429 LLVMGetParam(main_fn, SI_PARAM_FRONT_FACE);
430 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 1)] =
431 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 2)] =
432 lp_build_const_float(gallivm, 0.0f);
433 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 3)] =
434 lp_build_const_float(gallivm, 1.0f);
435
436 return;
437 }
438
439 shader->ps_input_param_offset[input_index] = shader->nparam++;
440 attr_number = lp_build_const_int32(gallivm,
441 shader->ps_input_param_offset[input_index]);
442
443 switch (decl->Interp.Interpolate) {
444 case TGSI_INTERPOLATE_CONSTANT:
445 interp_param = 0;
446 break;
447 case TGSI_INTERPOLATE_LINEAR:
448 if (decl->Interp.Location == TGSI_INTERPOLATE_LOC_SAMPLE)
449 interp_param = LLVMGetParam(main_fn, SI_PARAM_LINEAR_SAMPLE);
450 else if (decl->Interp.Location == TGSI_INTERPOLATE_LOC_CENTROID)
451 interp_param = LLVMGetParam(main_fn, SI_PARAM_LINEAR_CENTROID);
452 else
453 interp_param = LLVMGetParam(main_fn, SI_PARAM_LINEAR_CENTER);
454 break;
455 case TGSI_INTERPOLATE_COLOR:
456 if (si_shader_ctx->shader->key.ps.flatshade) {
457 interp_param = 0;
458 break;
459 }
460 /* fall through to perspective */
461 case TGSI_INTERPOLATE_PERSPECTIVE:
462 if (decl->Interp.Location == TGSI_INTERPOLATE_LOC_SAMPLE)
463 interp_param = LLVMGetParam(main_fn, SI_PARAM_PERSP_SAMPLE);
464 else if (decl->Interp.Location == TGSI_INTERPOLATE_LOC_CENTROID)
465 interp_param = LLVMGetParam(main_fn, SI_PARAM_PERSP_CENTROID);
466 else
467 interp_param = LLVMGetParam(main_fn, SI_PARAM_PERSP_CENTER);
468 break;
469 default:
470 fprintf(stderr, "Warning: Unhandled interpolation mode.\n");
471 return;
472 }
473
474 intr_name = interp_param ? "llvm.SI.fs.interp" : "llvm.SI.fs.constant";
475
476 /* XXX: Could there be more than TGSI_NUM_CHANNELS (4) ? */
477 if (decl->Semantic.Name == TGSI_SEMANTIC_COLOR &&
478 si_shader_ctx->shader->key.ps.color_two_side) {
479 LLVMValueRef args[4];
480 LLVMValueRef face, is_face_positive;
481 LLVMValueRef back_attr_number =
482 lp_build_const_int32(gallivm,
483 shader->ps_input_param_offset[input_index] + 1);
484
485 face = LLVMGetParam(main_fn, SI_PARAM_FRONT_FACE);
486
487 is_face_positive = LLVMBuildFCmp(gallivm->builder,
488 LLVMRealOGT, face,
489 lp_build_const_float(gallivm, 0.0f),
490 "");
491
492 args[2] = params;
493 args[3] = interp_param;
494 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
495 LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan);
496 unsigned soa_index = radeon_llvm_reg_index_soa(input_index, chan);
497 LLVMValueRef front, back;
498
499 args[0] = llvm_chan;
500 args[1] = attr_number;
501 front = build_intrinsic(gallivm->builder, intr_name,
502 input_type, args, args[3] ? 4 : 3,
503 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
504
505 args[1] = back_attr_number;
506 back = build_intrinsic(gallivm->builder, intr_name,
507 input_type, args, args[3] ? 4 : 3,
508 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
509
510 radeon_bld->inputs[soa_index] =
511 LLVMBuildSelect(gallivm->builder,
512 is_face_positive,
513 front,
514 back,
515 "");
516 }
517
518 shader->nparam++;
519 } else if (decl->Semantic.Name == TGSI_SEMANTIC_FOG) {
520 LLVMValueRef args[4];
521
522 args[0] = uint->zero;
523 args[1] = attr_number;
524 args[2] = params;
525 args[3] = interp_param;
526 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 0)] =
527 build_intrinsic(gallivm->builder, intr_name,
528 input_type, args, args[3] ? 4 : 3,
529 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
530 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 1)] =
531 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 2)] =
532 lp_build_const_float(gallivm, 0.0f);
533 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 3)] =
534 lp_build_const_float(gallivm, 1.0f);
535 } else {
536 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
537 LLVMValueRef args[4];
538 LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan);
539 unsigned soa_index = radeon_llvm_reg_index_soa(input_index, chan);
540 args[0] = llvm_chan;
541 args[1] = attr_number;
542 args[2] = params;
543 args[3] = interp_param;
544 radeon_bld->inputs[soa_index] =
545 build_intrinsic(gallivm->builder, intr_name,
546 input_type, args, args[3] ? 4 : 3,
547 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
548 }
549 }
550 }
551
552 static LLVMValueRef get_sample_id(struct radeon_llvm_context *radeon_bld)
553 {
554 struct gallivm_state *gallivm = &radeon_bld->gallivm;
555 LLVMValueRef value = LLVMGetParam(radeon_bld->main_fn,
556 SI_PARAM_ANCILLARY);
557 value = LLVMBuildLShr(gallivm->builder, value,
558 lp_build_const_int32(gallivm, 8), "");
559 value = LLVMBuildAnd(gallivm->builder, value,
560 lp_build_const_int32(gallivm, 0xf), "");
561 return value;
562 }
563
564 /**
565 * Load a dword from a constant buffer.
566 */
567 static LLVMValueRef buffer_load_const(LLVMBuilderRef builder, LLVMValueRef resource,
568 LLVMValueRef offset, LLVMTypeRef return_type)
569 {
570 LLVMValueRef args[2] = {resource, offset};
571
572 return build_intrinsic(builder, "llvm.SI.load.const", return_type, args, 2,
573 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
574 }
575
576 static void declare_system_value(
577 struct radeon_llvm_context * radeon_bld,
578 unsigned index,
579 const struct tgsi_full_declaration *decl)
580 {
581 struct si_shader_context *si_shader_ctx =
582 si_shader_context(&radeon_bld->soa.bld_base);
583 struct lp_build_context *uint_bld = &radeon_bld->soa.bld_base.uint_bld;
584 struct gallivm_state *gallivm = &radeon_bld->gallivm;
585 LLVMValueRef value = 0;
586
587 switch (decl->Semantic.Name) {
588 case TGSI_SEMANTIC_INSTANCEID:
589 value = LLVMGetParam(radeon_bld->main_fn,
590 si_shader_ctx->param_instance_id);
591 break;
592
593 case TGSI_SEMANTIC_VERTEXID:
594 value = LLVMBuildAdd(gallivm->builder,
595 LLVMGetParam(radeon_bld->main_fn,
596 si_shader_ctx->param_vertex_id),
597 LLVMGetParam(radeon_bld->main_fn,
598 SI_PARAM_BASE_VERTEX), "");
599 break;
600
601 case TGSI_SEMANTIC_SAMPLEID:
602 value = get_sample_id(radeon_bld);
603 break;
604
605 case TGSI_SEMANTIC_SAMPLEPOS:
606 {
607 LLVMBuilderRef builder = gallivm->builder;
608 LLVMValueRef desc = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_CONST);
609 LLVMValueRef buf_index = lp_build_const_int32(gallivm, SI_DRIVER_STATE_CONST_BUF);
610 LLVMValueRef resource = build_indexed_load_const(si_shader_ctx, desc, buf_index);
611
612 /* offset = sample_id * 8 (8 = 2 floats containing samplepos.xy) */
613 LLVMValueRef offset0 = lp_build_mul_imm(uint_bld, get_sample_id(radeon_bld), 8);
614 LLVMValueRef offset1 = LLVMBuildAdd(builder, offset0, lp_build_const_int32(gallivm, 4), "");
615
616 LLVMValueRef pos[4] = {
617 buffer_load_const(builder, resource, offset0, radeon_bld->soa.bld_base.base.elem_type),
618 buffer_load_const(builder, resource, offset1, radeon_bld->soa.bld_base.base.elem_type),
619 lp_build_const_float(gallivm, 0),
620 lp_build_const_float(gallivm, 0)
621 };
622 value = lp_build_gather_values(gallivm, pos, 4);
623 break;
624 }
625
626 default:
627 assert(!"unknown system value");
628 return;
629 }
630
631 radeon_bld->system_values[index] = value;
632 }
633
634 static LLVMValueRef fetch_constant(
635 struct lp_build_tgsi_context * bld_base,
636 const struct tgsi_full_src_register *reg,
637 enum tgsi_opcode_type type,
638 unsigned swizzle)
639 {
640 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
641 struct lp_build_context * base = &bld_base->base;
642 const struct tgsi_ind_register *ireg = &reg->Indirect;
643 unsigned buf, idx;
644
645 LLVMValueRef addr;
646 LLVMValueRef result;
647
648 if (swizzle == LP_CHAN_ALL) {
649 unsigned chan;
650 LLVMValueRef values[4];
651 for (chan = 0; chan < TGSI_NUM_CHANNELS; ++chan)
652 values[chan] = fetch_constant(bld_base, reg, type, chan);
653
654 return lp_build_gather_values(bld_base->base.gallivm, values, 4);
655 }
656
657 buf = reg->Register.Dimension ? reg->Dimension.Index : 0;
658 idx = reg->Register.Index * 4 + swizzle;
659
660 if (!reg->Register.Indirect)
661 return bitcast(bld_base, type, si_shader_ctx->constants[buf][idx]);
662
663 addr = si_shader_ctx->radeon_bld.soa.addr[ireg->Index][ireg->Swizzle];
664 addr = LLVMBuildLoad(base->gallivm->builder, addr, "load addr reg");
665 addr = lp_build_mul_imm(&bld_base->uint_bld, addr, 16);
666 addr = lp_build_add(&bld_base->uint_bld, addr,
667 lp_build_const_int32(base->gallivm, idx * 4));
668
669 result = buffer_load_const(base->gallivm->builder, si_shader_ctx->const_resource[buf],
670 addr, base->elem_type);
671
672 return bitcast(bld_base, type, result);
673 }
674
675 /* Initialize arguments for the shader export intrinsic */
676 static void si_llvm_init_export_args(struct lp_build_tgsi_context *bld_base,
677 LLVMValueRef *values,
678 unsigned target,
679 LLVMValueRef *args)
680 {
681 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
682 struct lp_build_context *uint =
683 &si_shader_ctx->radeon_bld.soa.bld_base.uint_bld;
684 struct lp_build_context *base = &bld_base->base;
685 unsigned compressed = 0;
686 unsigned chan;
687
688 if (si_shader_ctx->type == TGSI_PROCESSOR_FRAGMENT) {
689 int cbuf = target - V_008DFC_SQ_EXP_MRT;
690
691 if (cbuf >= 0 && cbuf < 8) {
692 compressed = (si_shader_ctx->shader->key.ps.export_16bpc >> cbuf) & 0x1;
693
694 if (compressed)
695 si_shader_ctx->shader->spi_shader_col_format |=
696 V_028714_SPI_SHADER_FP16_ABGR << (4 * cbuf);
697 else
698 si_shader_ctx->shader->spi_shader_col_format |=
699 V_028714_SPI_SHADER_32_ABGR << (4 * cbuf);
700
701 si_shader_ctx->shader->cb_shader_mask |= 0xf << (4 * cbuf);
702 }
703 }
704
705 if (compressed) {
706 /* Pixel shader needs to pack output values before export */
707 for (chan = 0; chan < 2; chan++ ) {
708 args[0] = values[2 * chan];
709 args[1] = values[2 * chan + 1];
710 args[chan + 5] =
711 build_intrinsic(base->gallivm->builder,
712 "llvm.SI.packf16",
713 LLVMInt32TypeInContext(base->gallivm->context),
714 args, 2,
715 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
716 args[chan + 7] = args[chan + 5] =
717 LLVMBuildBitCast(base->gallivm->builder,
718 args[chan + 5],
719 LLVMFloatTypeInContext(base->gallivm->context),
720 "");
721 }
722
723 /* Set COMPR flag */
724 args[4] = uint->one;
725 } else {
726 for (chan = 0; chan < 4; chan++ )
727 /* +5 because the first output value will be
728 * the 6th argument to the intrinsic. */
729 args[chan + 5] = values[chan];
730
731 /* Clear COMPR flag */
732 args[4] = uint->zero;
733 }
734
735 /* XXX: This controls which components of the output
736 * registers actually get exported. (e.g bit 0 means export
737 * X component, bit 1 means export Y component, etc.) I'm
738 * hard coding this to 0xf for now. In the future, we might
739 * want to do something else. */
740 args[0] = lp_build_const_int32(base->gallivm, 0xf);
741
742 /* Specify whether the EXEC mask represents the valid mask */
743 args[1] = uint->zero;
744
745 /* Specify whether this is the last export */
746 args[2] = uint->zero;
747
748 /* Specify the target we are exporting */
749 args[3] = lp_build_const_int32(base->gallivm, target);
750
751 /* XXX: We probably need to keep track of the output
752 * values, so we know what we are passing to the next
753 * stage. */
754 }
755
756 /* Load from output pointers and initialize arguments for the shader export intrinsic */
757 static void si_llvm_init_export_args_load(struct lp_build_tgsi_context *bld_base,
758 LLVMValueRef *out_ptr,
759 unsigned target,
760 LLVMValueRef *args)
761 {
762 struct gallivm_state *gallivm = bld_base->base.gallivm;
763 LLVMValueRef values[4];
764 int i;
765
766 for (i = 0; i < 4; i++)
767 values[i] = LLVMBuildLoad(gallivm->builder, out_ptr[i], "");
768
769 si_llvm_init_export_args(bld_base, values, target, args);
770 }
771
772 static void si_alpha_test(struct lp_build_tgsi_context *bld_base,
773 LLVMValueRef *out_ptr)
774 {
775 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
776 struct gallivm_state *gallivm = bld_base->base.gallivm;
777
778 if (si_shader_ctx->shader->key.ps.alpha_func != PIPE_FUNC_NEVER) {
779 LLVMValueRef alpha_ref = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
780 SI_PARAM_ALPHA_REF);
781
782 LLVMValueRef alpha_pass =
783 lp_build_cmp(&bld_base->base,
784 si_shader_ctx->shader->key.ps.alpha_func,
785 LLVMBuildLoad(gallivm->builder, out_ptr[3], ""),
786 alpha_ref);
787 LLVMValueRef arg =
788 lp_build_select(&bld_base->base,
789 alpha_pass,
790 lp_build_const_float(gallivm, 1.0f),
791 lp_build_const_float(gallivm, -1.0f));
792
793 build_intrinsic(gallivm->builder,
794 "llvm.AMDGPU.kill",
795 LLVMVoidTypeInContext(gallivm->context),
796 &arg, 1, 0);
797 } else {
798 build_intrinsic(gallivm->builder,
799 "llvm.AMDGPU.kilp",
800 LLVMVoidTypeInContext(gallivm->context),
801 NULL, 0, 0);
802 }
803
804 si_shader_ctx->shader->db_shader_control |= S_02880C_KILL_ENABLE(1);
805 }
806
807 static void si_llvm_emit_clipvertex(struct lp_build_tgsi_context * bld_base,
808 LLVMValueRef (*pos)[9], LLVMValueRef *out_elts)
809 {
810 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
811 struct lp_build_context *base = &bld_base->base;
812 struct lp_build_context *uint = &si_shader_ctx->radeon_bld.soa.bld_base.uint_bld;
813 unsigned reg_index;
814 unsigned chan;
815 unsigned const_chan;
816 LLVMValueRef base_elt;
817 LLVMValueRef ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_CONST);
818 LLVMValueRef constbuf_index = lp_build_const_int32(base->gallivm, SI_DRIVER_STATE_CONST_BUF);
819 LLVMValueRef const_resource = build_indexed_load_const(si_shader_ctx, ptr, constbuf_index);
820
821 for (reg_index = 0; reg_index < 2; reg_index ++) {
822 LLVMValueRef *args = pos[2 + reg_index];
823
824 args[5] =
825 args[6] =
826 args[7] =
827 args[8] = lp_build_const_float(base->gallivm, 0.0f);
828
829 /* Compute dot products of position and user clip plane vectors */
830 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
831 for (const_chan = 0; const_chan < TGSI_NUM_CHANNELS; const_chan++) {
832 args[1] = lp_build_const_int32(base->gallivm,
833 ((reg_index * 4 + chan) * 4 +
834 const_chan) * 4);
835 base_elt = buffer_load_const(base->gallivm->builder, const_resource,
836 args[1], base->elem_type);
837 args[5 + chan] =
838 lp_build_add(base, args[5 + chan],
839 lp_build_mul(base, base_elt,
840 out_elts[const_chan]));
841 }
842 }
843
844 args[0] = lp_build_const_int32(base->gallivm, 0xf);
845 args[1] = uint->zero;
846 args[2] = uint->zero;
847 args[3] = lp_build_const_int32(base->gallivm,
848 V_008DFC_SQ_EXP_POS + 2 + reg_index);
849 args[4] = uint->zero;
850 }
851 }
852
853 static void si_dump_streamout(struct pipe_stream_output_info *so)
854 {
855 unsigned i;
856
857 if (so->num_outputs)
858 fprintf(stderr, "STREAMOUT\n");
859
860 for (i = 0; i < so->num_outputs; i++) {
861 unsigned mask = ((1 << so->output[i].num_components) - 1) <<
862 so->output[i].start_component;
863 fprintf(stderr, " %i: BUF%i[%i..%i] <- OUT[%i].%s%s%s%s\n",
864 i, so->output[i].output_buffer,
865 so->output[i].dst_offset, so->output[i].dst_offset + so->output[i].num_components - 1,
866 so->output[i].register_index,
867 mask & 1 ? "x" : "",
868 mask & 2 ? "y" : "",
869 mask & 4 ? "z" : "",
870 mask & 8 ? "w" : "");
871 }
872 }
873
874 /* TBUFFER_STORE_FORMAT_{X,XY,XYZ,XYZW} <- the suffix is selected by num_channels=1..4.
875 * The type of vdata must be one of i32 (num_channels=1), v2i32 (num_channels=2),
876 * or v4i32 (num_channels=3,4). */
877 static void build_tbuffer_store(struct si_shader_context *shader,
878 LLVMValueRef rsrc,
879 LLVMValueRef vdata,
880 unsigned num_channels,
881 LLVMValueRef vaddr,
882 LLVMValueRef soffset,
883 unsigned inst_offset,
884 unsigned dfmt,
885 unsigned nfmt,
886 unsigned offen,
887 unsigned idxen,
888 unsigned glc,
889 unsigned slc,
890 unsigned tfe)
891 {
892 struct gallivm_state *gallivm = &shader->radeon_bld.gallivm;
893 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
894 LLVMValueRef args[] = {
895 rsrc,
896 vdata,
897 LLVMConstInt(i32, num_channels, 0),
898 vaddr,
899 soffset,
900 LLVMConstInt(i32, inst_offset, 0),
901 LLVMConstInt(i32, dfmt, 0),
902 LLVMConstInt(i32, nfmt, 0),
903 LLVMConstInt(i32, offen, 0),
904 LLVMConstInt(i32, idxen, 0),
905 LLVMConstInt(i32, glc, 0),
906 LLVMConstInt(i32, slc, 0),
907 LLVMConstInt(i32, tfe, 0)
908 };
909
910 /* The instruction offset field has 12 bits */
911 assert(offen || inst_offset < (1 << 12));
912
913 /* The intrinsic is overloaded, we need to add a type suffix for overloading to work. */
914 unsigned func = CLAMP(num_channels, 1, 3) - 1;
915 const char *types[] = {"i32", "v2i32", "v4i32"};
916 char name[256];
917 snprintf(name, sizeof(name), "llvm.SI.tbuffer.store.%s", types[func]);
918
919 lp_build_intrinsic(gallivm->builder, name,
920 LLVMVoidTypeInContext(gallivm->context),
921 args, Elements(args));
922 }
923
924 static void build_streamout_store(struct si_shader_context *shader,
925 LLVMValueRef rsrc,
926 LLVMValueRef vdata,
927 unsigned num_channels,
928 LLVMValueRef vaddr,
929 LLVMValueRef soffset,
930 unsigned inst_offset)
931 {
932 static unsigned dfmt[] = {
933 V_008F0C_BUF_DATA_FORMAT_32,
934 V_008F0C_BUF_DATA_FORMAT_32_32,
935 V_008F0C_BUF_DATA_FORMAT_32_32_32,
936 V_008F0C_BUF_DATA_FORMAT_32_32_32_32
937 };
938 assert(num_channels >= 1 && num_channels <= 4);
939
940 build_tbuffer_store(shader, rsrc, vdata, num_channels, vaddr, soffset,
941 inst_offset, dfmt[num_channels-1],
942 V_008F0C_BUF_NUM_FORMAT_UINT, 1, 0, 1, 1, 0);
943 }
944
945 /* On SI, the vertex shader is responsible for writing streamout data
946 * to buffers. */
947 static void si_llvm_emit_streamout(struct si_shader_context *shader,
948 struct si_shader_output_values *outputs,
949 unsigned noutput)
950 {
951 struct pipe_stream_output_info *so = &shader->shader->selector->so;
952 struct gallivm_state *gallivm = &shader->radeon_bld.gallivm;
953 LLVMBuilderRef builder = gallivm->builder;
954 int i, j;
955 struct lp_build_if_state if_ctx;
956
957 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
958
959 LLVMValueRef so_param =
960 LLVMGetParam(shader->radeon_bld.main_fn,
961 shader->param_streamout_config);
962
963 /* Get bits [22:16], i.e. (so_param >> 16) & 127; */
964 LLVMValueRef so_vtx_count =
965 LLVMBuildAnd(builder,
966 LLVMBuildLShr(builder, so_param,
967 LLVMConstInt(i32, 16, 0), ""),
968 LLVMConstInt(i32, 127, 0), "");
969
970 LLVMValueRef tid = build_intrinsic(builder, "llvm.SI.tid", i32,
971 NULL, 0, LLVMReadNoneAttribute);
972
973 /* can_emit = tid < so_vtx_count; */
974 LLVMValueRef can_emit =
975 LLVMBuildICmp(builder, LLVMIntULT, tid, so_vtx_count, "");
976
977 /* Emit the streamout code conditionally. This actually avoids
978 * out-of-bounds buffer access. The hw tells us via the SGPR
979 * (so_vtx_count) which threads are allowed to emit streamout data. */
980 lp_build_if(&if_ctx, gallivm, can_emit);
981 {
982 /* The buffer offset is computed as follows:
983 * ByteOffset = streamout_offset[buffer_id]*4 +
984 * (streamout_write_index + thread_id)*stride[buffer_id] +
985 * attrib_offset
986 */
987
988 LLVMValueRef so_write_index =
989 LLVMGetParam(shader->radeon_bld.main_fn,
990 shader->param_streamout_write_index);
991
992 /* Compute (streamout_write_index + thread_id). */
993 so_write_index = LLVMBuildAdd(builder, so_write_index, tid, "");
994
995 /* Compute the write offset for each enabled buffer. */
996 LLVMValueRef so_write_offset[4] = {};
997 for (i = 0; i < 4; i++) {
998 if (!so->stride[i])
999 continue;
1000
1001 LLVMValueRef so_offset = LLVMGetParam(shader->radeon_bld.main_fn,
1002 shader->param_streamout_offset[i]);
1003 so_offset = LLVMBuildMul(builder, so_offset, LLVMConstInt(i32, 4, 0), "");
1004
1005 so_write_offset[i] = LLVMBuildMul(builder, so_write_index,
1006 LLVMConstInt(i32, so->stride[i]*4, 0), "");
1007 so_write_offset[i] = LLVMBuildAdd(builder, so_write_offset[i], so_offset, "");
1008 }
1009
1010 /* Write streamout data. */
1011 for (i = 0; i < so->num_outputs; i++) {
1012 unsigned buf_idx = so->output[i].output_buffer;
1013 unsigned reg = so->output[i].register_index;
1014 unsigned start = so->output[i].start_component;
1015 unsigned num_comps = so->output[i].num_components;
1016 LLVMValueRef out[4];
1017
1018 assert(num_comps && num_comps <= 4);
1019 if (!num_comps || num_comps > 4)
1020 continue;
1021
1022 if (reg >= noutput)
1023 continue;
1024
1025 /* Load the output as int. */
1026 for (j = 0; j < num_comps; j++) {
1027 out[j] = LLVMBuildBitCast(builder,
1028 outputs[reg].values[start+j],
1029 i32, "");
1030 }
1031
1032 /* Pack the output. */
1033 LLVMValueRef vdata = NULL;
1034
1035 switch (num_comps) {
1036 case 1: /* as i32 */
1037 vdata = out[0];
1038 break;
1039 case 2: /* as v2i32 */
1040 case 3: /* as v4i32 (aligned to 4) */
1041 case 4: /* as v4i32 */
1042 vdata = LLVMGetUndef(LLVMVectorType(i32, util_next_power_of_two(num_comps)));
1043 for (j = 0; j < num_comps; j++) {
1044 vdata = LLVMBuildInsertElement(builder, vdata, out[j],
1045 LLVMConstInt(i32, j, 0), "");
1046 }
1047 break;
1048 }
1049
1050 build_streamout_store(shader, shader->so_buffers[buf_idx],
1051 vdata, num_comps,
1052 so_write_offset[buf_idx],
1053 LLVMConstInt(i32, 0, 0),
1054 so->output[i].dst_offset*4);
1055 }
1056 }
1057 lp_build_endif(&if_ctx);
1058 }
1059
1060
1061 /* Generate export instructions for hardware VS shader stage */
1062 static void si_llvm_export_vs(struct lp_build_tgsi_context *bld_base,
1063 struct si_shader_output_values *outputs,
1064 unsigned noutput)
1065 {
1066 struct si_shader_context * si_shader_ctx = si_shader_context(bld_base);
1067 struct si_shader * shader = si_shader_ctx->shader;
1068 struct lp_build_context * base = &bld_base->base;
1069 struct lp_build_context * uint =
1070 &si_shader_ctx->radeon_bld.soa.bld_base.uint_bld;
1071 LLVMValueRef args[9];
1072 LLVMValueRef pos_args[4][9] = { { 0 } };
1073 LLVMValueRef psize_value = NULL, edgeflag_value = NULL, layer_value = NULL;
1074 unsigned semantic_name, semantic_index;
1075 unsigned target;
1076 unsigned param_count = 0;
1077 unsigned pos_idx;
1078 int i;
1079
1080 if (outputs && si_shader_ctx->shader->selector->so.num_outputs) {
1081 si_llvm_emit_streamout(si_shader_ctx, outputs, noutput);
1082 }
1083
1084 for (i = 0; i < noutput; i++) {
1085 semantic_name = outputs[i].name;
1086 semantic_index = outputs[i].sid;
1087
1088 handle_semantic:
1089 /* Select the correct target */
1090 switch(semantic_name) {
1091 case TGSI_SEMANTIC_PSIZE:
1092 psize_value = outputs[i].values[0];
1093 continue;
1094 case TGSI_SEMANTIC_EDGEFLAG:
1095 edgeflag_value = outputs[i].values[0];
1096 continue;
1097 case TGSI_SEMANTIC_LAYER:
1098 layer_value = outputs[i].values[0];
1099 continue;
1100 case TGSI_SEMANTIC_POSITION:
1101 target = V_008DFC_SQ_EXP_POS;
1102 break;
1103 case TGSI_SEMANTIC_COLOR:
1104 case TGSI_SEMANTIC_BCOLOR:
1105 target = V_008DFC_SQ_EXP_PARAM + param_count;
1106 shader->vs_output_param_offset[i] = param_count;
1107 param_count++;
1108 break;
1109 case TGSI_SEMANTIC_CLIPDIST:
1110 target = V_008DFC_SQ_EXP_POS + 2 + semantic_index;
1111 break;
1112 case TGSI_SEMANTIC_CLIPVERTEX:
1113 si_llvm_emit_clipvertex(bld_base, pos_args, outputs[i].values);
1114 continue;
1115 case TGSI_SEMANTIC_PRIMID:
1116 case TGSI_SEMANTIC_FOG:
1117 case TGSI_SEMANTIC_GENERIC:
1118 target = V_008DFC_SQ_EXP_PARAM + param_count;
1119 shader->vs_output_param_offset[i] = param_count;
1120 param_count++;
1121 break;
1122 default:
1123 target = 0;
1124 fprintf(stderr,
1125 "Warning: SI unhandled vs output type:%d\n",
1126 semantic_name);
1127 }
1128
1129 si_llvm_init_export_args(bld_base, outputs[i].values, target, args);
1130
1131 if (target >= V_008DFC_SQ_EXP_POS &&
1132 target <= (V_008DFC_SQ_EXP_POS + 3)) {
1133 memcpy(pos_args[target - V_008DFC_SQ_EXP_POS],
1134 args, sizeof(args));
1135 } else {
1136 lp_build_intrinsic(base->gallivm->builder,
1137 "llvm.SI.export",
1138 LLVMVoidTypeInContext(base->gallivm->context),
1139 args, 9);
1140 }
1141
1142 if (semantic_name == TGSI_SEMANTIC_CLIPDIST) {
1143 semantic_name = TGSI_SEMANTIC_GENERIC;
1144 goto handle_semantic;
1145 }
1146 }
1147
1148 /* We need to add the position output manually if it's missing. */
1149 if (!pos_args[0][0]) {
1150 pos_args[0][0] = lp_build_const_int32(base->gallivm, 0xf); /* writemask */
1151 pos_args[0][1] = uint->zero; /* EXEC mask */
1152 pos_args[0][2] = uint->zero; /* last export? */
1153 pos_args[0][3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_POS);
1154 pos_args[0][4] = uint->zero; /* COMPR flag */
1155 pos_args[0][5] = base->zero; /* X */
1156 pos_args[0][6] = base->zero; /* Y */
1157 pos_args[0][7] = base->zero; /* Z */
1158 pos_args[0][8] = base->one; /* W */
1159 }
1160
1161 /* Write the misc vector (point size, edgeflag, layer, viewport). */
1162 if (shader->selector->info.writes_psize ||
1163 shader->selector->info.writes_edgeflag ||
1164 shader->selector->info.writes_layer) {
1165 pos_args[1][0] = lp_build_const_int32(base->gallivm, /* writemask */
1166 shader->selector->info.writes_psize |
1167 (shader->selector->info.writes_edgeflag << 1) |
1168 (shader->selector->info.writes_layer << 2));
1169 pos_args[1][1] = uint->zero; /* EXEC mask */
1170 pos_args[1][2] = uint->zero; /* last export? */
1171 pos_args[1][3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_POS + 1);
1172 pos_args[1][4] = uint->zero; /* COMPR flag */
1173 pos_args[1][5] = base->zero; /* X */
1174 pos_args[1][6] = base->zero; /* Y */
1175 pos_args[1][7] = base->zero; /* Z */
1176 pos_args[1][8] = base->zero; /* W */
1177
1178 if (shader->selector->info.writes_psize)
1179 pos_args[1][5] = psize_value;
1180
1181 if (shader->selector->info.writes_edgeflag) {
1182 /* The output is a float, but the hw expects an integer
1183 * with the first bit containing the edge flag. */
1184 edgeflag_value = LLVMBuildFPToUI(base->gallivm->builder,
1185 edgeflag_value,
1186 bld_base->uint_bld.elem_type, "");
1187 edgeflag_value = lp_build_min(&bld_base->int_bld,
1188 edgeflag_value,
1189 bld_base->int_bld.one);
1190
1191 /* The LLVM intrinsic expects a float. */
1192 pos_args[1][6] = LLVMBuildBitCast(base->gallivm->builder,
1193 edgeflag_value,
1194 base->elem_type, "");
1195 }
1196
1197 if (shader->selector->info.writes_layer)
1198 pos_args[1][7] = layer_value;
1199 }
1200
1201 for (i = 0; i < 4; i++)
1202 if (pos_args[i][0])
1203 shader->nr_pos_exports++;
1204
1205 pos_idx = 0;
1206 for (i = 0; i < 4; i++) {
1207 if (!pos_args[i][0])
1208 continue;
1209
1210 /* Specify the target we are exporting */
1211 pos_args[i][3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_POS + pos_idx++);
1212
1213 if (pos_idx == shader->nr_pos_exports)
1214 /* Specify that this is the last export */
1215 pos_args[i][2] = uint->one;
1216
1217 lp_build_intrinsic(base->gallivm->builder,
1218 "llvm.SI.export",
1219 LLVMVoidTypeInContext(base->gallivm->context),
1220 pos_args[i], 9);
1221 }
1222 }
1223
1224 static void si_llvm_emit_es_epilogue(struct lp_build_tgsi_context * bld_base)
1225 {
1226 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
1227 struct gallivm_state *gallivm = bld_base->base.gallivm;
1228 struct si_shader *es = si_shader_ctx->shader;
1229 struct tgsi_shader_info *info = &es->selector->info;
1230 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
1231 LLVMValueRef soffset = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
1232 SI_PARAM_ES2GS_OFFSET);
1233 unsigned chan;
1234 int i;
1235
1236 for (i = 0; i < info->num_outputs; i++) {
1237 LLVMValueRef *out_ptr =
1238 si_shader_ctx->radeon_bld.soa.outputs[i];
1239 int param_index = get_param_index(info->output_semantic_name[i],
1240 info->output_semantic_index[i],
1241 es->key.vs.gs_used_inputs);
1242
1243 if (param_index < 0)
1244 continue;
1245
1246 for (chan = 0; chan < 4; chan++) {
1247 LLVMValueRef out_val = LLVMBuildLoad(gallivm->builder, out_ptr[chan], "");
1248 out_val = LLVMBuildBitCast(gallivm->builder, out_val, i32, "");
1249
1250 build_tbuffer_store(si_shader_ctx,
1251 si_shader_ctx->esgs_ring,
1252 out_val, 1,
1253 LLVMGetUndef(i32), soffset,
1254 (4 * param_index + chan) * 4,
1255 V_008F0C_BUF_DATA_FORMAT_32,
1256 V_008F0C_BUF_NUM_FORMAT_UINT,
1257 0, 0, 1, 1, 0);
1258 }
1259 }
1260 }
1261
1262 static void si_llvm_emit_gs_epilogue(struct lp_build_tgsi_context *bld_base)
1263 {
1264 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
1265 struct gallivm_state *gallivm = bld_base->base.gallivm;
1266 LLVMValueRef args[2];
1267
1268 args[0] = lp_build_const_int32(gallivm, SENDMSG_GS_OP_NOP | SENDMSG_GS_DONE);
1269 args[1] = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_GS_WAVE_ID);
1270 build_intrinsic(gallivm->builder, "llvm.SI.sendmsg",
1271 LLVMVoidTypeInContext(gallivm->context), args, 2,
1272 LLVMNoUnwindAttribute);
1273 }
1274
1275 static void si_llvm_emit_vs_epilogue(struct lp_build_tgsi_context * bld_base)
1276 {
1277 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
1278 struct gallivm_state *gallivm = bld_base->base.gallivm;
1279 struct tgsi_shader_info *info = &si_shader_ctx->shader->selector->info;
1280 struct si_shader_output_values *outputs = NULL;
1281 int i,j;
1282
1283 outputs = MALLOC(info->num_outputs * sizeof(outputs[0]));
1284
1285 for (i = 0; i < info->num_outputs; i++) {
1286 outputs[i].name = info->output_semantic_name[i];
1287 outputs[i].sid = info->output_semantic_index[i];
1288
1289 for (j = 0; j < 4; j++)
1290 outputs[i].values[j] =
1291 LLVMBuildLoad(gallivm->builder,
1292 si_shader_ctx->radeon_bld.soa.outputs[i][j],
1293 "");
1294 }
1295
1296 si_llvm_export_vs(bld_base, outputs, info->num_outputs);
1297 FREE(outputs);
1298 }
1299
1300 static void si_llvm_emit_fs_epilogue(struct lp_build_tgsi_context * bld_base)
1301 {
1302 struct si_shader_context * si_shader_ctx = si_shader_context(bld_base);
1303 struct si_shader * shader = si_shader_ctx->shader;
1304 struct lp_build_context * base = &bld_base->base;
1305 struct lp_build_context * uint = &bld_base->uint_bld;
1306 struct tgsi_shader_info *info = &shader->selector->info;
1307 LLVMValueRef args[9];
1308 LLVMValueRef last_args[9] = { 0 };
1309 int depth_index = -1, stencil_index = -1, samplemask_index = -1;
1310 int i;
1311
1312 for (i = 0; i < info->num_outputs; i++) {
1313 unsigned semantic_name = info->output_semantic_name[i];
1314 unsigned semantic_index = info->output_semantic_index[i];
1315 unsigned target;
1316
1317 /* Select the correct target */
1318 switch (semantic_name) {
1319 case TGSI_SEMANTIC_POSITION:
1320 depth_index = i;
1321 continue;
1322 case TGSI_SEMANTIC_STENCIL:
1323 stencil_index = i;
1324 continue;
1325 case TGSI_SEMANTIC_SAMPLEMASK:
1326 samplemask_index = i;
1327 continue;
1328 case TGSI_SEMANTIC_COLOR:
1329 target = V_008DFC_SQ_EXP_MRT + semantic_index;
1330 if (si_shader_ctx->shader->key.ps.alpha_to_one)
1331 LLVMBuildStore(bld_base->base.gallivm->builder,
1332 bld_base->base.one,
1333 si_shader_ctx->radeon_bld.soa.outputs[i][3]);
1334
1335 if (semantic_index == 0 &&
1336 si_shader_ctx->shader->key.ps.alpha_func != PIPE_FUNC_ALWAYS)
1337 si_alpha_test(bld_base,
1338 si_shader_ctx->radeon_bld.soa.outputs[i]);
1339 break;
1340 default:
1341 target = 0;
1342 fprintf(stderr,
1343 "Warning: SI unhandled fs output type:%d\n",
1344 semantic_name);
1345 }
1346
1347 si_llvm_init_export_args_load(bld_base,
1348 si_shader_ctx->radeon_bld.soa.outputs[i],
1349 target, args);
1350
1351 if (semantic_name == TGSI_SEMANTIC_COLOR) {
1352 /* If there is an export instruction waiting to be emitted, do so now. */
1353 if (last_args[0]) {
1354 lp_build_intrinsic(base->gallivm->builder,
1355 "llvm.SI.export",
1356 LLVMVoidTypeInContext(base->gallivm->context),
1357 last_args, 9);
1358 }
1359
1360 /* This instruction will be emitted at the end of the shader. */
1361 memcpy(last_args, args, sizeof(args));
1362
1363 /* Handle FS_COLOR0_WRITES_ALL_CBUFS. */
1364 if (shader->selector->info.properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS] &&
1365 semantic_index == 0 &&
1366 si_shader_ctx->shader->key.ps.last_cbuf > 0) {
1367 for (int c = 1; c <= si_shader_ctx->shader->key.ps.last_cbuf; c++) {
1368 si_llvm_init_export_args_load(bld_base,
1369 si_shader_ctx->radeon_bld.soa.outputs[i],
1370 V_008DFC_SQ_EXP_MRT + c, args);
1371 lp_build_intrinsic(base->gallivm->builder,
1372 "llvm.SI.export",
1373 LLVMVoidTypeInContext(base->gallivm->context),
1374 args, 9);
1375 }
1376 }
1377 } else {
1378 lp_build_intrinsic(base->gallivm->builder,
1379 "llvm.SI.export",
1380 LLVMVoidTypeInContext(base->gallivm->context),
1381 args, 9);
1382 }
1383 }
1384
1385 if (depth_index >= 0 || stencil_index >= 0 || samplemask_index >= 0) {
1386 LLVMValueRef out_ptr;
1387 unsigned mask = 0;
1388
1389 /* Specify the target we are exporting */
1390 args[3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_MRTZ);
1391
1392 args[5] = base->zero; /* R, depth */
1393 args[6] = base->zero; /* G, stencil test value[0:7], stencil op value[8:15] */
1394 args[7] = base->zero; /* B, sample mask */
1395 args[8] = base->zero; /* A, alpha to mask */
1396
1397 if (depth_index >= 0) {
1398 out_ptr = si_shader_ctx->radeon_bld.soa.outputs[depth_index][2];
1399 args[5] = LLVMBuildLoad(base->gallivm->builder, out_ptr, "");
1400 mask |= 0x1;
1401 si_shader_ctx->shader->db_shader_control |= S_02880C_Z_EXPORT_ENABLE(1);
1402 }
1403
1404 if (stencil_index >= 0) {
1405 out_ptr = si_shader_ctx->radeon_bld.soa.outputs[stencil_index][1];
1406 args[6] = LLVMBuildLoad(base->gallivm->builder, out_ptr, "");
1407 mask |= 0x2;
1408 si_shader_ctx->shader->db_shader_control |=
1409 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(1);
1410 }
1411
1412 if (samplemask_index >= 0) {
1413 out_ptr = si_shader_ctx->radeon_bld.soa.outputs[samplemask_index][0];
1414 args[7] = LLVMBuildLoad(base->gallivm->builder, out_ptr, "");
1415 mask |= 0x4;
1416 si_shader_ctx->shader->db_shader_control |= S_02880C_MASK_EXPORT_ENABLE(1);
1417 }
1418
1419 /* SI (except OLAND) has a bug that it only looks
1420 * at the X writemask component. */
1421 if (si_shader_ctx->screen->b.chip_class == SI &&
1422 si_shader_ctx->screen->b.family != CHIP_OLAND)
1423 mask |= 0x1;
1424
1425 if (samplemask_index >= 0)
1426 si_shader_ctx->shader->spi_shader_z_format = V_028710_SPI_SHADER_32_ABGR;
1427 else if (stencil_index >= 0)
1428 si_shader_ctx->shader->spi_shader_z_format = V_028710_SPI_SHADER_32_GR;
1429 else
1430 si_shader_ctx->shader->spi_shader_z_format = V_028710_SPI_SHADER_32_R;
1431
1432 /* Specify which components to enable */
1433 args[0] = lp_build_const_int32(base->gallivm, mask);
1434
1435 args[1] =
1436 args[2] =
1437 args[4] = uint->zero;
1438
1439 if (last_args[0])
1440 lp_build_intrinsic(base->gallivm->builder,
1441 "llvm.SI.export",
1442 LLVMVoidTypeInContext(base->gallivm->context),
1443 args, 9);
1444 else
1445 memcpy(last_args, args, sizeof(args));
1446 }
1447
1448 if (!last_args[0]) {
1449 /* Specify which components to enable */
1450 last_args[0] = lp_build_const_int32(base->gallivm, 0x0);
1451
1452 /* Specify the target we are exporting */
1453 last_args[3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_MRT);
1454
1455 /* Set COMPR flag to zero to export data as 32-bit */
1456 last_args[4] = uint->zero;
1457
1458 /* dummy bits */
1459 last_args[5]= uint->zero;
1460 last_args[6]= uint->zero;
1461 last_args[7]= uint->zero;
1462 last_args[8]= uint->zero;
1463 }
1464
1465 /* Specify whether the EXEC mask represents the valid mask */
1466 last_args[1] = uint->one;
1467
1468 /* Specify that this is the last export */
1469 last_args[2] = lp_build_const_int32(base->gallivm, 1);
1470
1471 lp_build_intrinsic(base->gallivm->builder,
1472 "llvm.SI.export",
1473 LLVMVoidTypeInContext(base->gallivm->context),
1474 last_args, 9);
1475 }
1476
1477 static void build_tex_intrinsic(const struct lp_build_tgsi_action * action,
1478 struct lp_build_tgsi_context * bld_base,
1479 struct lp_build_emit_data * emit_data);
1480
1481 static bool tgsi_is_shadow_sampler(unsigned target)
1482 {
1483 return target == TGSI_TEXTURE_SHADOW1D ||
1484 target == TGSI_TEXTURE_SHADOW1D_ARRAY ||
1485 target == TGSI_TEXTURE_SHADOW2D ||
1486 target == TGSI_TEXTURE_SHADOW2D_ARRAY ||
1487 target == TGSI_TEXTURE_SHADOWCUBE ||
1488 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY ||
1489 target == TGSI_TEXTURE_SHADOWRECT;
1490 }
1491
1492 static const struct lp_build_tgsi_action tex_action;
1493
1494 static void tex_fetch_args(
1495 struct lp_build_tgsi_context * bld_base,
1496 struct lp_build_emit_data * emit_data)
1497 {
1498 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
1499 struct gallivm_state *gallivm = bld_base->base.gallivm;
1500 const struct tgsi_full_instruction * inst = emit_data->inst;
1501 unsigned opcode = inst->Instruction.Opcode;
1502 unsigned target = inst->Texture.Texture;
1503 LLVMValueRef coords[4];
1504 LLVMValueRef address[16];
1505 int ref_pos;
1506 unsigned num_coords = tgsi_util_get_texture_coord_dim(target, &ref_pos);
1507 unsigned count = 0;
1508 unsigned chan;
1509 unsigned sampler_src = emit_data->inst->Instruction.NumSrcRegs - 1;
1510 unsigned sampler_index = emit_data->inst->Src[sampler_src].Register.Index;
1511 bool has_offset = HAVE_LLVM >= 0x0305 ? inst->Texture.NumOffsets > 0 : false;
1512
1513 if (target == TGSI_TEXTURE_BUFFER) {
1514 LLVMTypeRef i128 = LLVMIntTypeInContext(gallivm->context, 128);
1515 LLVMTypeRef v2i128 = LLVMVectorType(i128, 2);
1516 LLVMTypeRef i8 = LLVMInt8TypeInContext(gallivm->context);
1517 LLVMTypeRef v16i8 = LLVMVectorType(i8, 16);
1518
1519 /* Bitcast and truncate v8i32 to v16i8. */
1520 LLVMValueRef res = si_shader_ctx->resources[sampler_index];
1521 res = LLVMBuildBitCast(gallivm->builder, res, v2i128, "");
1522 res = LLVMBuildExtractElement(gallivm->builder, res, bld_base->uint_bld.zero, "");
1523 res = LLVMBuildBitCast(gallivm->builder, res, v16i8, "");
1524
1525 emit_data->dst_type = LLVMVectorType(bld_base->base.elem_type, 4);
1526 emit_data->args[0] = res;
1527 emit_data->args[1] = bld_base->uint_bld.zero;
1528 emit_data->args[2] = lp_build_emit_fetch(bld_base, emit_data->inst, 0, 0);
1529 emit_data->arg_count = 3;
1530 return;
1531 }
1532
1533 /* Fetch and project texture coordinates */
1534 coords[3] = lp_build_emit_fetch(bld_base, emit_data->inst, 0, TGSI_CHAN_W);
1535 for (chan = 0; chan < 3; chan++ ) {
1536 coords[chan] = lp_build_emit_fetch(bld_base,
1537 emit_data->inst, 0,
1538 chan);
1539 if (opcode == TGSI_OPCODE_TXP)
1540 coords[chan] = lp_build_emit_llvm_binary(bld_base,
1541 TGSI_OPCODE_DIV,
1542 coords[chan],
1543 coords[3]);
1544 }
1545
1546 if (opcode == TGSI_OPCODE_TXP)
1547 coords[3] = bld_base->base.one;
1548
1549 /* Pack offsets. */
1550 if (has_offset && opcode != TGSI_OPCODE_TXF) {
1551 /* The offsets are six-bit signed integers packed like this:
1552 * X=[5:0], Y=[13:8], and Z=[21:16].
1553 */
1554 LLVMValueRef offset[3], pack;
1555
1556 assert(inst->Texture.NumOffsets == 1);
1557
1558 for (chan = 0; chan < 3; chan++) {
1559 offset[chan] = lp_build_emit_fetch_texoffset(bld_base,
1560 emit_data->inst, 0, chan);
1561 offset[chan] = LLVMBuildAnd(gallivm->builder, offset[chan],
1562 lp_build_const_int32(gallivm, 0x3f), "");
1563 if (chan)
1564 offset[chan] = LLVMBuildShl(gallivm->builder, offset[chan],
1565 lp_build_const_int32(gallivm, chan*8), "");
1566 }
1567
1568 pack = LLVMBuildOr(gallivm->builder, offset[0], offset[1], "");
1569 pack = LLVMBuildOr(gallivm->builder, pack, offset[2], "");
1570 address[count++] = pack;
1571 }
1572
1573 /* Pack LOD bias value */
1574 if (opcode == TGSI_OPCODE_TXB)
1575 address[count++] = coords[3];
1576 if (opcode == TGSI_OPCODE_TXB2)
1577 address[count++] = lp_build_emit_fetch(bld_base, inst, 1, 0);
1578
1579 /* Pack depth comparison value */
1580 if (tgsi_is_shadow_sampler(target) && opcode != TGSI_OPCODE_LODQ) {
1581 if (target == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
1582 address[count++] = lp_build_emit_fetch(bld_base, inst, 1, 0);
1583 } else {
1584 assert(ref_pos >= 0);
1585 address[count++] = coords[ref_pos];
1586 }
1587 }
1588
1589 if (target == TGSI_TEXTURE_CUBE ||
1590 target == TGSI_TEXTURE_CUBE_ARRAY ||
1591 target == TGSI_TEXTURE_SHADOWCUBE ||
1592 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY)
1593 radeon_llvm_emit_prepare_cube_coords(bld_base, emit_data, coords);
1594
1595 /* Pack user derivatives */
1596 if (opcode == TGSI_OPCODE_TXD) {
1597 int num_deriv_channels, param;
1598
1599 switch (target) {
1600 case TGSI_TEXTURE_3D:
1601 num_deriv_channels = 3;
1602 break;
1603 case TGSI_TEXTURE_2D:
1604 case TGSI_TEXTURE_SHADOW2D:
1605 case TGSI_TEXTURE_RECT:
1606 case TGSI_TEXTURE_SHADOWRECT:
1607 case TGSI_TEXTURE_2D_ARRAY:
1608 case TGSI_TEXTURE_SHADOW2D_ARRAY:
1609 case TGSI_TEXTURE_CUBE:
1610 case TGSI_TEXTURE_SHADOWCUBE:
1611 case TGSI_TEXTURE_CUBE_ARRAY:
1612 case TGSI_TEXTURE_SHADOWCUBE_ARRAY:
1613 num_deriv_channels = 2;
1614 break;
1615 case TGSI_TEXTURE_1D:
1616 case TGSI_TEXTURE_SHADOW1D:
1617 case TGSI_TEXTURE_1D_ARRAY:
1618 case TGSI_TEXTURE_SHADOW1D_ARRAY:
1619 num_deriv_channels = 1;
1620 break;
1621 default:
1622 assert(0); /* no other targets are valid here */
1623 }
1624
1625 for (param = 1; param <= 2; param++)
1626 for (chan = 0; chan < num_deriv_channels; chan++)
1627 address[count++] = lp_build_emit_fetch(bld_base, inst, param, chan);
1628 }
1629
1630 /* Pack texture coordinates */
1631 address[count++] = coords[0];
1632 if (num_coords > 1)
1633 address[count++] = coords[1];
1634 if (num_coords > 2)
1635 address[count++] = coords[2];
1636
1637 /* Pack LOD or sample index */
1638 if (opcode == TGSI_OPCODE_TXL || opcode == TGSI_OPCODE_TXF)
1639 address[count++] = coords[3];
1640 else if (opcode == TGSI_OPCODE_TXL2)
1641 address[count++] = lp_build_emit_fetch(bld_base, inst, 1, 0);
1642
1643 if (count > 16) {
1644 assert(!"Cannot handle more than 16 texture address parameters");
1645 count = 16;
1646 }
1647
1648 for (chan = 0; chan < count; chan++ ) {
1649 address[chan] = LLVMBuildBitCast(gallivm->builder,
1650 address[chan],
1651 LLVMInt32TypeInContext(gallivm->context),
1652 "");
1653 }
1654
1655 /* Adjust the sample index according to FMASK.
1656 *
1657 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
1658 * which is the identity mapping. Each nibble says which physical sample
1659 * should be fetched to get that sample.
1660 *
1661 * For example, 0x11111100 means there are only 2 samples stored and
1662 * the second sample covers 3/4 of the pixel. When reading samples 0
1663 * and 1, return physical sample 0 (determined by the first two 0s
1664 * in FMASK), otherwise return physical sample 1.
1665 *
1666 * The sample index should be adjusted as follows:
1667 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
1668 */
1669 if (target == TGSI_TEXTURE_2D_MSAA ||
1670 target == TGSI_TEXTURE_2D_ARRAY_MSAA) {
1671 struct lp_build_context *uint_bld = &bld_base->uint_bld;
1672 struct lp_build_emit_data txf_emit_data = *emit_data;
1673 LLVMValueRef txf_address[4];
1674 unsigned txf_count = count;
1675 struct tgsi_full_instruction inst = {};
1676
1677 memcpy(txf_address, address, sizeof(txf_address));
1678
1679 if (target == TGSI_TEXTURE_2D_MSAA) {
1680 txf_address[2] = bld_base->uint_bld.zero;
1681 }
1682 txf_address[3] = bld_base->uint_bld.zero;
1683
1684 /* Pad to a power-of-two size. */
1685 while (txf_count < util_next_power_of_two(txf_count))
1686 txf_address[txf_count++] = LLVMGetUndef(LLVMInt32TypeInContext(gallivm->context));
1687
1688 /* Read FMASK using TXF. */
1689 inst.Instruction.Opcode = TGSI_OPCODE_TXF;
1690 inst.Texture.Texture = target == TGSI_TEXTURE_2D_MSAA ? TGSI_TEXTURE_2D : TGSI_TEXTURE_2D_ARRAY;
1691 txf_emit_data.inst = &inst;
1692 txf_emit_data.chan = 0;
1693 txf_emit_data.dst_type = LLVMVectorType(
1694 LLVMInt32TypeInContext(gallivm->context), 4);
1695 txf_emit_data.args[0] = lp_build_gather_values(gallivm, txf_address, txf_count);
1696 txf_emit_data.args[1] = si_shader_ctx->resources[SI_FMASK_TEX_OFFSET + sampler_index];
1697 txf_emit_data.args[2] = lp_build_const_int32(gallivm, inst.Texture.Texture);
1698 txf_emit_data.arg_count = 3;
1699
1700 build_tex_intrinsic(&tex_action, bld_base, &txf_emit_data);
1701
1702 /* Initialize some constants. */
1703 LLVMValueRef four = LLVMConstInt(uint_bld->elem_type, 4, 0);
1704 LLVMValueRef F = LLVMConstInt(uint_bld->elem_type, 0xF, 0);
1705
1706 /* Apply the formula. */
1707 LLVMValueRef fmask =
1708 LLVMBuildExtractElement(gallivm->builder,
1709 txf_emit_data.output[0],
1710 uint_bld->zero, "");
1711
1712 unsigned sample_chan = target == TGSI_TEXTURE_2D_MSAA ? 2 : 3;
1713
1714 LLVMValueRef sample_index4 =
1715 LLVMBuildMul(gallivm->builder, address[sample_chan], four, "");
1716
1717 LLVMValueRef shifted_fmask =
1718 LLVMBuildLShr(gallivm->builder, fmask, sample_index4, "");
1719
1720 LLVMValueRef final_sample =
1721 LLVMBuildAnd(gallivm->builder, shifted_fmask, F, "");
1722
1723 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
1724 * resource descriptor is 0 (invalid),
1725 */
1726 LLVMValueRef fmask_desc =
1727 LLVMBuildBitCast(gallivm->builder,
1728 si_shader_ctx->resources[SI_FMASK_TEX_OFFSET + sampler_index],
1729 LLVMVectorType(uint_bld->elem_type, 8), "");
1730
1731 LLVMValueRef fmask_word1 =
1732 LLVMBuildExtractElement(gallivm->builder, fmask_desc,
1733 uint_bld->one, "");
1734
1735 LLVMValueRef word1_is_nonzero =
1736 LLVMBuildICmp(gallivm->builder, LLVMIntNE,
1737 fmask_word1, uint_bld->zero, "");
1738
1739 /* Replace the MSAA sample index. */
1740 address[sample_chan] =
1741 LLVMBuildSelect(gallivm->builder, word1_is_nonzero,
1742 final_sample, address[sample_chan], "");
1743 }
1744
1745 /* Resource */
1746 emit_data->args[1] = si_shader_ctx->resources[sampler_index];
1747
1748 if (opcode == TGSI_OPCODE_TXF) {
1749 /* add tex offsets */
1750 if (inst->Texture.NumOffsets) {
1751 struct lp_build_context *uint_bld = &bld_base->uint_bld;
1752 struct lp_build_tgsi_soa_context *bld = lp_soa_context(bld_base);
1753 const struct tgsi_texture_offset * off = inst->TexOffsets;
1754
1755 assert(inst->Texture.NumOffsets == 1);
1756
1757 switch (target) {
1758 case TGSI_TEXTURE_3D:
1759 address[2] = lp_build_add(uint_bld, address[2],
1760 bld->immediates[off->Index][off->SwizzleZ]);
1761 /* fall through */
1762 case TGSI_TEXTURE_2D:
1763 case TGSI_TEXTURE_SHADOW2D:
1764 case TGSI_TEXTURE_RECT:
1765 case TGSI_TEXTURE_SHADOWRECT:
1766 case TGSI_TEXTURE_2D_ARRAY:
1767 case TGSI_TEXTURE_SHADOW2D_ARRAY:
1768 address[1] =
1769 lp_build_add(uint_bld, address[1],
1770 bld->immediates[off->Index][off->SwizzleY]);
1771 /* fall through */
1772 case TGSI_TEXTURE_1D:
1773 case TGSI_TEXTURE_SHADOW1D:
1774 case TGSI_TEXTURE_1D_ARRAY:
1775 case TGSI_TEXTURE_SHADOW1D_ARRAY:
1776 address[0] =
1777 lp_build_add(uint_bld, address[0],
1778 bld->immediates[off->Index][off->SwizzleX]);
1779 break;
1780 /* texture offsets do not apply to other texture targets */
1781 }
1782 }
1783
1784 emit_data->args[2] = lp_build_const_int32(gallivm, target);
1785 emit_data->arg_count = 3;
1786
1787 emit_data->dst_type = LLVMVectorType(
1788 LLVMInt32TypeInContext(gallivm->context),
1789 4);
1790 } else if (opcode == TGSI_OPCODE_TG4 ||
1791 opcode == TGSI_OPCODE_LODQ ||
1792 has_offset) {
1793 unsigned is_array = target == TGSI_TEXTURE_1D_ARRAY ||
1794 target == TGSI_TEXTURE_SHADOW1D_ARRAY ||
1795 target == TGSI_TEXTURE_2D_ARRAY ||
1796 target == TGSI_TEXTURE_SHADOW2D_ARRAY ||
1797 target == TGSI_TEXTURE_CUBE_ARRAY ||
1798 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY;
1799 unsigned is_rect = target == TGSI_TEXTURE_RECT;
1800 unsigned dmask = 0xf;
1801
1802 if (opcode == TGSI_OPCODE_TG4) {
1803 unsigned gather_comp = 0;
1804
1805 /* DMASK was repurposed for GATHER4. 4 components are always
1806 * returned and DMASK works like a swizzle - it selects
1807 * the component to fetch. The only valid DMASK values are
1808 * 1=red, 2=green, 4=blue, 8=alpha. (e.g. 1 returns
1809 * (red,red,red,red) etc.) The ISA document doesn't mention
1810 * this.
1811 */
1812
1813 /* Get the component index from src1.x for Gather4. */
1814 if (!tgsi_is_shadow_sampler(target)) {
1815 LLVMValueRef (*imms)[4] = lp_soa_context(bld_base)->immediates;
1816 LLVMValueRef comp_imm;
1817 struct tgsi_src_register src1 = inst->Src[1].Register;
1818
1819 assert(src1.File == TGSI_FILE_IMMEDIATE);
1820
1821 comp_imm = imms[src1.Index][src1.SwizzleX];
1822 gather_comp = LLVMConstIntGetZExtValue(comp_imm);
1823 gather_comp = CLAMP(gather_comp, 0, 3);
1824 }
1825
1826 dmask = 1 << gather_comp;
1827 }
1828
1829 emit_data->args[2] = si_shader_ctx->samplers[sampler_index];
1830 emit_data->args[3] = lp_build_const_int32(gallivm, dmask);
1831 emit_data->args[4] = lp_build_const_int32(gallivm, is_rect); /* unorm */
1832 emit_data->args[5] = lp_build_const_int32(gallivm, 0); /* r128 */
1833 emit_data->args[6] = lp_build_const_int32(gallivm, is_array); /* da */
1834 emit_data->args[7] = lp_build_const_int32(gallivm, 0); /* glc */
1835 emit_data->args[8] = lp_build_const_int32(gallivm, 0); /* slc */
1836 emit_data->args[9] = lp_build_const_int32(gallivm, 0); /* tfe */
1837 emit_data->args[10] = lp_build_const_int32(gallivm, 0); /* lwe */
1838
1839 emit_data->arg_count = 11;
1840
1841 emit_data->dst_type = LLVMVectorType(
1842 LLVMFloatTypeInContext(gallivm->context),
1843 4);
1844 } else {
1845 emit_data->args[2] = si_shader_ctx->samplers[sampler_index];
1846 emit_data->args[3] = lp_build_const_int32(gallivm, target);
1847 emit_data->arg_count = 4;
1848
1849 emit_data->dst_type = LLVMVectorType(
1850 LLVMFloatTypeInContext(gallivm->context),
1851 4);
1852 }
1853
1854 /* The fetch opcode has been converted to a 2D array fetch.
1855 * This simplifies the LLVM backend. */
1856 if (target == TGSI_TEXTURE_CUBE_ARRAY)
1857 target = TGSI_TEXTURE_2D_ARRAY;
1858 else if (target == TGSI_TEXTURE_SHADOWCUBE_ARRAY)
1859 target = TGSI_TEXTURE_SHADOW2D_ARRAY;
1860
1861 /* Pad to power of two vector */
1862 while (count < util_next_power_of_two(count))
1863 address[count++] = LLVMGetUndef(LLVMInt32TypeInContext(gallivm->context));
1864
1865 emit_data->args[0] = lp_build_gather_values(gallivm, address, count);
1866 }
1867
1868 static void build_tex_intrinsic(const struct lp_build_tgsi_action * action,
1869 struct lp_build_tgsi_context * bld_base,
1870 struct lp_build_emit_data * emit_data)
1871 {
1872 struct lp_build_context * base = &bld_base->base;
1873 unsigned opcode = emit_data->inst->Instruction.Opcode;
1874 unsigned target = emit_data->inst->Texture.Texture;
1875 char intr_name[127];
1876 bool has_offset = HAVE_LLVM >= 0x0305 ?
1877 emit_data->inst->Texture.NumOffsets > 0 : false;
1878
1879 if (target == TGSI_TEXTURE_BUFFER) {
1880 emit_data->output[emit_data->chan] = build_intrinsic(
1881 base->gallivm->builder,
1882 "llvm.SI.vs.load.input", emit_data->dst_type,
1883 emit_data->args, emit_data->arg_count,
1884 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
1885 return;
1886 }
1887
1888 if (opcode == TGSI_OPCODE_TG4 ||
1889 opcode == TGSI_OPCODE_LODQ ||
1890 (opcode != TGSI_OPCODE_TXF && has_offset)) {
1891 bool is_shadow = tgsi_is_shadow_sampler(target);
1892 const char *name = "llvm.SI.image.sample";
1893 const char *infix = "";
1894
1895 switch (opcode) {
1896 case TGSI_OPCODE_TEX:
1897 case TGSI_OPCODE_TEX2:
1898 case TGSI_OPCODE_TXP:
1899 break;
1900 case TGSI_OPCODE_TXB:
1901 case TGSI_OPCODE_TXB2:
1902 infix = ".b";
1903 break;
1904 case TGSI_OPCODE_TXL:
1905 case TGSI_OPCODE_TXL2:
1906 infix = ".l";
1907 break;
1908 case TGSI_OPCODE_TXD:
1909 infix = ".d";
1910 break;
1911 case TGSI_OPCODE_TG4:
1912 name = "llvm.SI.gather4";
1913 break;
1914 case TGSI_OPCODE_LODQ:
1915 name = "llvm.SI.getlod";
1916 is_shadow = false;
1917 has_offset = false;
1918 break;
1919 default:
1920 assert(0);
1921 return;
1922 }
1923
1924 /* Add the type and suffixes .c, .o if needed. */
1925 sprintf(intr_name, "%s%s%s%s.v%ui32", name,
1926 is_shadow ? ".c" : "", infix, has_offset ? ".o" : "",
1927 LLVMGetVectorSize(LLVMTypeOf(emit_data->args[0])));
1928
1929 emit_data->output[emit_data->chan] = build_intrinsic(
1930 base->gallivm->builder, intr_name, emit_data->dst_type,
1931 emit_data->args, emit_data->arg_count,
1932 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
1933 } else {
1934 LLVMTypeRef i8, v16i8, v32i8;
1935 const char *name;
1936
1937 switch (opcode) {
1938 case TGSI_OPCODE_TEX:
1939 case TGSI_OPCODE_TEX2:
1940 case TGSI_OPCODE_TXP:
1941 name = "llvm.SI.sample";
1942 break;
1943 case TGSI_OPCODE_TXB:
1944 case TGSI_OPCODE_TXB2:
1945 name = "llvm.SI.sampleb";
1946 break;
1947 case TGSI_OPCODE_TXD:
1948 name = "llvm.SI.sampled";
1949 break;
1950 case TGSI_OPCODE_TXF:
1951 name = "llvm.SI.imageload";
1952 break;
1953 case TGSI_OPCODE_TXL:
1954 case TGSI_OPCODE_TXL2:
1955 name = "llvm.SI.samplel";
1956 break;
1957 default:
1958 assert(0);
1959 return;
1960 }
1961
1962 i8 = LLVMInt8TypeInContext(base->gallivm->context);
1963 v16i8 = LLVMVectorType(i8, 16);
1964 v32i8 = LLVMVectorType(i8, 32);
1965
1966 emit_data->args[1] = LLVMBuildBitCast(base->gallivm->builder,
1967 emit_data->args[1], v32i8, "");
1968 if (opcode != TGSI_OPCODE_TXF) {
1969 emit_data->args[2] = LLVMBuildBitCast(base->gallivm->builder,
1970 emit_data->args[2], v16i8, "");
1971 }
1972
1973 sprintf(intr_name, "%s.v%ui32", name,
1974 LLVMGetVectorSize(LLVMTypeOf(emit_data->args[0])));
1975
1976 emit_data->output[emit_data->chan] = build_intrinsic(
1977 base->gallivm->builder, intr_name, emit_data->dst_type,
1978 emit_data->args, emit_data->arg_count,
1979 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
1980 }
1981 }
1982
1983 static void txq_fetch_args(
1984 struct lp_build_tgsi_context * bld_base,
1985 struct lp_build_emit_data * emit_data)
1986 {
1987 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
1988 const struct tgsi_full_instruction *inst = emit_data->inst;
1989 struct gallivm_state *gallivm = bld_base->base.gallivm;
1990 unsigned target = inst->Texture.Texture;
1991
1992 if (target == TGSI_TEXTURE_BUFFER) {
1993 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
1994 LLVMTypeRef v8i32 = LLVMVectorType(i32, 8);
1995
1996 /* Read the size from the buffer descriptor directly. */
1997 LLVMValueRef size = si_shader_ctx->resources[inst->Src[1].Register.Index];
1998 size = LLVMBuildBitCast(gallivm->builder, size, v8i32, "");
1999 size = LLVMBuildExtractElement(gallivm->builder, size,
2000 lp_build_const_int32(gallivm, 2), "");
2001 emit_data->args[0] = size;
2002 return;
2003 }
2004
2005 /* Mip level */
2006 emit_data->args[0] = lp_build_emit_fetch(bld_base, inst, 0, TGSI_CHAN_X);
2007
2008 /* Resource */
2009 emit_data->args[1] = si_shader_ctx->resources[inst->Src[1].Register.Index];
2010
2011 /* Texture target */
2012 if (target == TGSI_TEXTURE_CUBE_ARRAY ||
2013 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY)
2014 target = TGSI_TEXTURE_2D_ARRAY;
2015
2016 emit_data->args[2] = lp_build_const_int32(bld_base->base.gallivm,
2017 target);
2018
2019 emit_data->arg_count = 3;
2020
2021 emit_data->dst_type = LLVMVectorType(
2022 LLVMInt32TypeInContext(bld_base->base.gallivm->context),
2023 4);
2024 }
2025
2026 static void build_txq_intrinsic(const struct lp_build_tgsi_action * action,
2027 struct lp_build_tgsi_context * bld_base,
2028 struct lp_build_emit_data * emit_data)
2029 {
2030 unsigned target = emit_data->inst->Texture.Texture;
2031
2032 if (target == TGSI_TEXTURE_BUFFER) {
2033 /* Just return the buffer size. */
2034 emit_data->output[emit_data->chan] = emit_data->args[0];
2035 return;
2036 }
2037
2038 build_tgsi_intrinsic_nomem(action, bld_base, emit_data);
2039
2040 /* Divide the number of layers by 6 to get the number of cubes. */
2041 if (target == TGSI_TEXTURE_CUBE_ARRAY ||
2042 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
2043 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
2044 LLVMValueRef two = lp_build_const_int32(bld_base->base.gallivm, 2);
2045 LLVMValueRef six = lp_build_const_int32(bld_base->base.gallivm, 6);
2046
2047 LLVMValueRef v4 = emit_data->output[emit_data->chan];
2048 LLVMValueRef z = LLVMBuildExtractElement(builder, v4, two, "");
2049 z = LLVMBuildSDiv(builder, z, six, "");
2050
2051 emit_data->output[emit_data->chan] =
2052 LLVMBuildInsertElement(builder, v4, z, two, "");
2053 }
2054 }
2055
2056 static void si_llvm_emit_ddxy(
2057 const struct lp_build_tgsi_action * action,
2058 struct lp_build_tgsi_context * bld_base,
2059 struct lp_build_emit_data * emit_data)
2060 {
2061 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
2062 struct gallivm_state *gallivm = bld_base->base.gallivm;
2063 struct lp_build_context * base = &bld_base->base;
2064 const struct tgsi_full_instruction *inst = emit_data->inst;
2065 unsigned opcode = inst->Instruction.Opcode;
2066 LLVMValueRef indices[2];
2067 LLVMValueRef store_ptr, load_ptr0, load_ptr1;
2068 LLVMValueRef tl, trbl, result[4];
2069 LLVMTypeRef i32;
2070 unsigned swizzle[4];
2071 unsigned c;
2072
2073 i32 = LLVMInt32TypeInContext(gallivm->context);
2074
2075 indices[0] = bld_base->uint_bld.zero;
2076 indices[1] = build_intrinsic(gallivm->builder, "llvm.SI.tid", i32,
2077 NULL, 0, LLVMReadNoneAttribute);
2078 store_ptr = LLVMBuildGEP(gallivm->builder, si_shader_ctx->ddxy_lds,
2079 indices, 2, "");
2080
2081 indices[1] = LLVMBuildAnd(gallivm->builder, indices[1],
2082 lp_build_const_int32(gallivm, 0xfffffffc), "");
2083 load_ptr0 = LLVMBuildGEP(gallivm->builder, si_shader_ctx->ddxy_lds,
2084 indices, 2, "");
2085
2086 indices[1] = LLVMBuildAdd(gallivm->builder, indices[1],
2087 lp_build_const_int32(gallivm,
2088 opcode == TGSI_OPCODE_DDX ? 1 : 2),
2089 "");
2090 load_ptr1 = LLVMBuildGEP(gallivm->builder, si_shader_ctx->ddxy_lds,
2091 indices, 2, "");
2092
2093 for (c = 0; c < 4; ++c) {
2094 unsigned i;
2095
2096 swizzle[c] = tgsi_util_get_full_src_register_swizzle(&inst->Src[0], c);
2097 for (i = 0; i < c; ++i) {
2098 if (swizzle[i] == swizzle[c]) {
2099 result[c] = result[i];
2100 break;
2101 }
2102 }
2103 if (i != c)
2104 continue;
2105
2106 LLVMBuildStore(gallivm->builder,
2107 LLVMBuildBitCast(gallivm->builder,
2108 lp_build_emit_fetch(bld_base, inst, 0, c),
2109 i32, ""),
2110 store_ptr);
2111
2112 tl = LLVMBuildLoad(gallivm->builder, load_ptr0, "");
2113 tl = LLVMBuildBitCast(gallivm->builder, tl, base->elem_type, "");
2114
2115 trbl = LLVMBuildLoad(gallivm->builder, load_ptr1, "");
2116 trbl = LLVMBuildBitCast(gallivm->builder, trbl, base->elem_type, "");
2117
2118 result[c] = LLVMBuildFSub(gallivm->builder, trbl, tl, "");
2119 }
2120
2121 emit_data->output[0] = lp_build_gather_values(gallivm, result, 4);
2122 }
2123
2124 /* Emit one vertex from the geometry shader */
2125 static void si_llvm_emit_vertex(
2126 const struct lp_build_tgsi_action *action,
2127 struct lp_build_tgsi_context *bld_base,
2128 struct lp_build_emit_data *emit_data)
2129 {
2130 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
2131 struct lp_build_context *uint = &bld_base->uint_bld;
2132 struct si_shader *shader = si_shader_ctx->shader;
2133 struct tgsi_shader_info *info = &shader->selector->info;
2134 struct gallivm_state *gallivm = bld_base->base.gallivm;
2135 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
2136 LLVMValueRef soffset = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
2137 SI_PARAM_GS2VS_OFFSET);
2138 LLVMValueRef gs_next_vertex;
2139 LLVMValueRef can_emit, kill;
2140 LLVMValueRef args[2];
2141 unsigned chan;
2142 int i;
2143
2144 /* Write vertex attribute values to GSVS ring */
2145 gs_next_vertex = LLVMBuildLoad(gallivm->builder, si_shader_ctx->gs_next_vertex, "");
2146
2147 /* If this thread has already emitted the declared maximum number of
2148 * vertices, kill it: excessive vertex emissions are not supposed to
2149 * have any effect, and GS threads have no externally observable
2150 * effects other than emitting vertices.
2151 */
2152 can_emit = LLVMBuildICmp(gallivm->builder, LLVMIntULE, gs_next_vertex,
2153 lp_build_const_int32(gallivm,
2154 shader->selector->gs_max_out_vertices), "");
2155 kill = lp_build_select(&bld_base->base, can_emit,
2156 lp_build_const_float(gallivm, 1.0f),
2157 lp_build_const_float(gallivm, -1.0f));
2158 build_intrinsic(gallivm->builder, "llvm.AMDGPU.kill",
2159 LLVMVoidTypeInContext(gallivm->context), &kill, 1, 0);
2160
2161 for (i = 0; i < info->num_outputs; i++) {
2162 LLVMValueRef *out_ptr =
2163 si_shader_ctx->radeon_bld.soa.outputs[i];
2164
2165 for (chan = 0; chan < 4; chan++) {
2166 LLVMValueRef out_val = LLVMBuildLoad(gallivm->builder, out_ptr[chan], "");
2167 LLVMValueRef voffset =
2168 lp_build_const_int32(gallivm, (i * 4 + chan) *
2169 shader->selector->gs_max_out_vertices);
2170
2171 voffset = lp_build_add(uint, voffset, gs_next_vertex);
2172 voffset = lp_build_mul_imm(uint, voffset, 4);
2173
2174 out_val = LLVMBuildBitCast(gallivm->builder, out_val, i32, "");
2175
2176 build_tbuffer_store(si_shader_ctx,
2177 si_shader_ctx->gsvs_ring,
2178 out_val, 1,
2179 voffset, soffset, 0,
2180 V_008F0C_BUF_DATA_FORMAT_32,
2181 V_008F0C_BUF_NUM_FORMAT_UINT,
2182 1, 0, 1, 1, 0);
2183 }
2184 }
2185 gs_next_vertex = lp_build_add(uint, gs_next_vertex,
2186 lp_build_const_int32(gallivm, 1));
2187 LLVMBuildStore(gallivm->builder, gs_next_vertex, si_shader_ctx->gs_next_vertex);
2188
2189 /* Signal vertex emission */
2190 args[0] = lp_build_const_int32(gallivm, SENDMSG_GS_OP_EMIT | SENDMSG_GS);
2191 args[1] = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_GS_WAVE_ID);
2192 build_intrinsic(gallivm->builder, "llvm.SI.sendmsg",
2193 LLVMVoidTypeInContext(gallivm->context), args, 2,
2194 LLVMNoUnwindAttribute);
2195 }
2196
2197 /* Cut one primitive from the geometry shader */
2198 static void si_llvm_emit_primitive(
2199 const struct lp_build_tgsi_action *action,
2200 struct lp_build_tgsi_context *bld_base,
2201 struct lp_build_emit_data *emit_data)
2202 {
2203 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
2204 struct gallivm_state *gallivm = bld_base->base.gallivm;
2205 LLVMValueRef args[2];
2206
2207 /* Signal primitive cut */
2208 args[0] = lp_build_const_int32(gallivm, SENDMSG_GS_OP_CUT | SENDMSG_GS);
2209 args[1] = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_GS_WAVE_ID);
2210 build_intrinsic(gallivm->builder, "llvm.SI.sendmsg",
2211 LLVMVoidTypeInContext(gallivm->context), args, 2,
2212 LLVMNoUnwindAttribute);
2213 }
2214
2215 static const struct lp_build_tgsi_action tex_action = {
2216 .fetch_args = tex_fetch_args,
2217 .emit = build_tex_intrinsic,
2218 };
2219
2220 static const struct lp_build_tgsi_action txq_action = {
2221 .fetch_args = txq_fetch_args,
2222 .emit = build_txq_intrinsic,
2223 .intr_name = "llvm.SI.resinfo"
2224 };
2225
2226 static void create_meta_data(struct si_shader_context *si_shader_ctx)
2227 {
2228 struct gallivm_state *gallivm = si_shader_ctx->radeon_bld.soa.bld_base.base.gallivm;
2229 LLVMValueRef args[3];
2230
2231 args[0] = LLVMMDStringInContext(gallivm->context, "const", 5);
2232 args[1] = 0;
2233 args[2] = lp_build_const_int32(gallivm, 1);
2234
2235 si_shader_ctx->const_md = LLVMMDNodeInContext(gallivm->context, args, 3);
2236 }
2237
2238 static LLVMTypeRef const_array(LLVMTypeRef elem_type, int num_elements)
2239 {
2240 return LLVMPointerType(LLVMArrayType(elem_type, num_elements),
2241 CONST_ADDR_SPACE);
2242 }
2243
2244 static void create_function(struct si_shader_context *si_shader_ctx)
2245 {
2246 struct lp_build_tgsi_context *bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
2247 struct gallivm_state *gallivm = bld_base->base.gallivm;
2248 struct si_shader *shader = si_shader_ctx->shader;
2249 LLVMTypeRef params[SI_NUM_PARAMS], f32, i8, i32, v2i32, v3i32, v16i8, v4i32, v8i32;
2250 unsigned i, last_array_pointer, last_sgpr, num_params;
2251
2252 i8 = LLVMInt8TypeInContext(gallivm->context);
2253 i32 = LLVMInt32TypeInContext(gallivm->context);
2254 f32 = LLVMFloatTypeInContext(gallivm->context);
2255 v2i32 = LLVMVectorType(i32, 2);
2256 v3i32 = LLVMVectorType(i32, 3);
2257 v4i32 = LLVMVectorType(i32, 4);
2258 v8i32 = LLVMVectorType(i32, 8);
2259 v16i8 = LLVMVectorType(i8, 16);
2260
2261 params[SI_PARAM_RW_BUFFERS] = const_array(v16i8, SI_NUM_RW_BUFFERS);
2262 params[SI_PARAM_CONST] = const_array(v16i8, SI_NUM_CONST_BUFFERS);
2263 params[SI_PARAM_SAMPLER] = const_array(v4i32, SI_NUM_SAMPLER_STATES);
2264 params[SI_PARAM_RESOURCE] = const_array(v8i32, SI_NUM_SAMPLER_VIEWS);
2265 last_array_pointer = SI_PARAM_RESOURCE;
2266
2267 switch (si_shader_ctx->type) {
2268 case TGSI_PROCESSOR_VERTEX:
2269 params[SI_PARAM_VERTEX_BUFFER] = const_array(v16i8, SI_NUM_VERTEX_BUFFERS);
2270 last_array_pointer = SI_PARAM_VERTEX_BUFFER;
2271 params[SI_PARAM_BASE_VERTEX] = i32;
2272 params[SI_PARAM_START_INSTANCE] = i32;
2273 num_params = SI_PARAM_START_INSTANCE+1;
2274
2275 if (shader->key.vs.as_es) {
2276 params[SI_PARAM_ES2GS_OFFSET] = i32;
2277 num_params++;
2278 } else {
2279 if (shader->is_gs_copy_shader) {
2280 last_array_pointer = SI_PARAM_CONST;
2281 num_params = SI_PARAM_CONST+1;
2282 }
2283
2284 /* The locations of the other parameters are assigned dynamically. */
2285
2286 /* Streamout SGPRs. */
2287 if (shader->selector->so.num_outputs) {
2288 params[si_shader_ctx->param_streamout_config = num_params++] = i32;
2289 params[si_shader_ctx->param_streamout_write_index = num_params++] = i32;
2290 }
2291 /* A streamout buffer offset is loaded if the stride is non-zero. */
2292 for (i = 0; i < 4; i++) {
2293 if (!shader->selector->so.stride[i])
2294 continue;
2295
2296 params[si_shader_ctx->param_streamout_offset[i] = num_params++] = i32;
2297 }
2298 }
2299
2300 last_sgpr = num_params-1;
2301
2302 /* VGPRs */
2303 params[si_shader_ctx->param_vertex_id = num_params++] = i32;
2304 params[num_params++] = i32; /* unused*/
2305 params[num_params++] = i32; /* unused */
2306 params[si_shader_ctx->param_instance_id = num_params++] = i32;
2307 break;
2308
2309 case TGSI_PROCESSOR_GEOMETRY:
2310 params[SI_PARAM_GS2VS_OFFSET] = i32;
2311 params[SI_PARAM_GS_WAVE_ID] = i32;
2312 last_sgpr = SI_PARAM_GS_WAVE_ID;
2313
2314 /* VGPRs */
2315 params[SI_PARAM_VTX0_OFFSET] = i32;
2316 params[SI_PARAM_VTX1_OFFSET] = i32;
2317 params[SI_PARAM_PRIMITIVE_ID] = i32;
2318 params[SI_PARAM_VTX2_OFFSET] = i32;
2319 params[SI_PARAM_VTX3_OFFSET] = i32;
2320 params[SI_PARAM_VTX4_OFFSET] = i32;
2321 params[SI_PARAM_VTX5_OFFSET] = i32;
2322 params[SI_PARAM_GS_INSTANCE_ID] = i32;
2323 num_params = SI_PARAM_GS_INSTANCE_ID+1;
2324 break;
2325
2326 case TGSI_PROCESSOR_FRAGMENT:
2327 params[SI_PARAM_ALPHA_REF] = f32;
2328 params[SI_PARAM_PRIM_MASK] = i32;
2329 last_sgpr = SI_PARAM_PRIM_MASK;
2330 params[SI_PARAM_PERSP_SAMPLE] = v2i32;
2331 params[SI_PARAM_PERSP_CENTER] = v2i32;
2332 params[SI_PARAM_PERSP_CENTROID] = v2i32;
2333 params[SI_PARAM_PERSP_PULL_MODEL] = v3i32;
2334 params[SI_PARAM_LINEAR_SAMPLE] = v2i32;
2335 params[SI_PARAM_LINEAR_CENTER] = v2i32;
2336 params[SI_PARAM_LINEAR_CENTROID] = v2i32;
2337 params[SI_PARAM_LINE_STIPPLE_TEX] = f32;
2338 params[SI_PARAM_POS_X_FLOAT] = f32;
2339 params[SI_PARAM_POS_Y_FLOAT] = f32;
2340 params[SI_PARAM_POS_Z_FLOAT] = f32;
2341 params[SI_PARAM_POS_W_FLOAT] = f32;
2342 params[SI_PARAM_FRONT_FACE] = f32;
2343 params[SI_PARAM_ANCILLARY] = i32;
2344 params[SI_PARAM_SAMPLE_COVERAGE] = f32;
2345 params[SI_PARAM_POS_FIXED_PT] = f32;
2346 num_params = SI_PARAM_POS_FIXED_PT+1;
2347 break;
2348
2349 default:
2350 assert(0 && "unimplemented shader");
2351 return;
2352 }
2353
2354 assert(num_params <= Elements(params));
2355 radeon_llvm_create_func(&si_shader_ctx->radeon_bld, params, num_params);
2356 radeon_llvm_shader_type(si_shader_ctx->radeon_bld.main_fn, si_shader_ctx->type);
2357
2358 for (i = 0; i <= last_sgpr; ++i) {
2359 LLVMValueRef P = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, i);
2360
2361 /* We tell llvm that array inputs are passed by value to allow Sinking pass
2362 * to move load. Inputs are constant so this is fine. */
2363 if (i <= last_array_pointer)
2364 LLVMAddAttribute(P, LLVMByValAttribute);
2365 else
2366 LLVMAddAttribute(P, LLVMInRegAttribute);
2367 }
2368
2369 if (bld_base->info &&
2370 (bld_base->info->opcode_count[TGSI_OPCODE_DDX] > 0 ||
2371 bld_base->info->opcode_count[TGSI_OPCODE_DDY] > 0))
2372 si_shader_ctx->ddxy_lds =
2373 LLVMAddGlobalInAddressSpace(gallivm->module,
2374 LLVMArrayType(i32, 64),
2375 "ddxy_lds",
2376 LOCAL_ADDR_SPACE);
2377 }
2378
2379 static void preload_constants(struct si_shader_context *si_shader_ctx)
2380 {
2381 struct lp_build_tgsi_context * bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
2382 struct gallivm_state * gallivm = bld_base->base.gallivm;
2383 const struct tgsi_shader_info * info = bld_base->info;
2384 unsigned buf;
2385 LLVMValueRef ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_CONST);
2386
2387 for (buf = 0; buf < SI_NUM_CONST_BUFFERS; buf++) {
2388 unsigned i, num_const = info->const_file_max[buf] + 1;
2389
2390 if (num_const == 0)
2391 continue;
2392
2393 /* Allocate space for the constant values */
2394 si_shader_ctx->constants[buf] = CALLOC(num_const * 4, sizeof(LLVMValueRef));
2395
2396 /* Load the resource descriptor */
2397 si_shader_ctx->const_resource[buf] =
2398 build_indexed_load_const(si_shader_ctx, ptr, lp_build_const_int32(gallivm, buf));
2399
2400 /* Load the constants, we rely on the code sinking to do the rest */
2401 for (i = 0; i < num_const * 4; ++i) {
2402 si_shader_ctx->constants[buf][i] =
2403 buffer_load_const(gallivm->builder,
2404 si_shader_ctx->const_resource[buf],
2405 lp_build_const_int32(gallivm, i * 4),
2406 bld_base->base.elem_type);
2407 }
2408 }
2409 }
2410
2411 static void preload_samplers(struct si_shader_context *si_shader_ctx)
2412 {
2413 struct lp_build_tgsi_context * bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
2414 struct gallivm_state * gallivm = bld_base->base.gallivm;
2415 const struct tgsi_shader_info * info = bld_base->info;
2416
2417 unsigned i, num_samplers = info->file_max[TGSI_FILE_SAMPLER] + 1;
2418
2419 LLVMValueRef res_ptr, samp_ptr;
2420 LLVMValueRef offset;
2421
2422 if (num_samplers == 0)
2423 return;
2424
2425 res_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_RESOURCE);
2426 samp_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_SAMPLER);
2427
2428 /* Load the resources and samplers, we rely on the code sinking to do the rest */
2429 for (i = 0; i < num_samplers; ++i) {
2430 /* Resource */
2431 offset = lp_build_const_int32(gallivm, i);
2432 si_shader_ctx->resources[i] = build_indexed_load_const(si_shader_ctx, res_ptr, offset);
2433
2434 /* Sampler */
2435 offset = lp_build_const_int32(gallivm, i);
2436 si_shader_ctx->samplers[i] = build_indexed_load_const(si_shader_ctx, samp_ptr, offset);
2437
2438 /* FMASK resource */
2439 if (info->is_msaa_sampler[i]) {
2440 offset = lp_build_const_int32(gallivm, SI_FMASK_TEX_OFFSET + i);
2441 si_shader_ctx->resources[SI_FMASK_TEX_OFFSET + i] =
2442 build_indexed_load_const(si_shader_ctx, res_ptr, offset);
2443 }
2444 }
2445 }
2446
2447 static void preload_streamout_buffers(struct si_shader_context *si_shader_ctx)
2448 {
2449 struct lp_build_tgsi_context * bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
2450 struct gallivm_state * gallivm = bld_base->base.gallivm;
2451 unsigned i;
2452
2453 if (si_shader_ctx->type != TGSI_PROCESSOR_VERTEX ||
2454 si_shader_ctx->shader->key.vs.as_es ||
2455 !si_shader_ctx->shader->selector->so.num_outputs)
2456 return;
2457
2458 LLVMValueRef buf_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
2459 SI_PARAM_RW_BUFFERS);
2460
2461 /* Load the resources, we rely on the code sinking to do the rest */
2462 for (i = 0; i < 4; ++i) {
2463 if (si_shader_ctx->shader->selector->so.stride[i]) {
2464 LLVMValueRef offset = lp_build_const_int32(gallivm,
2465 SI_SO_BUF_OFFSET + i);
2466
2467 si_shader_ctx->so_buffers[i] = build_indexed_load_const(si_shader_ctx, buf_ptr, offset);
2468 }
2469 }
2470 }
2471
2472 /**
2473 * Load ESGS and GSVS ring buffer resource descriptors and save the variables
2474 * for later use.
2475 */
2476 static void preload_ring_buffers(struct si_shader_context *si_shader_ctx)
2477 {
2478 struct gallivm_state *gallivm =
2479 si_shader_ctx->radeon_bld.soa.bld_base.base.gallivm;
2480
2481 LLVMValueRef buf_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
2482 SI_PARAM_RW_BUFFERS);
2483
2484 if ((si_shader_ctx->type == TGSI_PROCESSOR_VERTEX &&
2485 si_shader_ctx->shader->key.vs.as_es) ||
2486 si_shader_ctx->type == TGSI_PROCESSOR_GEOMETRY) {
2487 LLVMValueRef offset = lp_build_const_int32(gallivm, SI_RING_ESGS);
2488
2489 si_shader_ctx->esgs_ring =
2490 build_indexed_load_const(si_shader_ctx, buf_ptr, offset);
2491 }
2492
2493 if (si_shader_ctx->type == TGSI_PROCESSOR_GEOMETRY ||
2494 si_shader_ctx->shader->is_gs_copy_shader) {
2495 LLVMValueRef offset = lp_build_const_int32(gallivm, SI_RING_GSVS);
2496
2497 si_shader_ctx->gsvs_ring =
2498 build_indexed_load_const(si_shader_ctx, buf_ptr, offset);
2499 }
2500 }
2501
2502 void si_shader_binary_read_config(const struct radeon_shader_binary *binary,
2503 struct si_shader *shader,
2504 unsigned symbol_offset)
2505 {
2506 unsigned i;
2507 const unsigned char *config =
2508 radeon_shader_binary_config_start(binary, symbol_offset);
2509
2510 /* XXX: We may be able to emit some of these values directly rather than
2511 * extracting fields to be emitted later.
2512 */
2513
2514 for (i = 0; i < binary->config_size_per_symbol; i+= 8) {
2515 unsigned reg = util_le32_to_cpu(*(uint32_t*)(config + i));
2516 unsigned value = util_le32_to_cpu(*(uint32_t*)(config + i + 4));
2517 switch (reg) {
2518 case R_00B028_SPI_SHADER_PGM_RSRC1_PS:
2519 case R_00B128_SPI_SHADER_PGM_RSRC1_VS:
2520 case R_00B228_SPI_SHADER_PGM_RSRC1_GS:
2521 case R_00B848_COMPUTE_PGM_RSRC1:
2522 shader->num_sgprs = MAX2(shader->num_sgprs, (G_00B028_SGPRS(value) + 1) * 8);
2523 shader->num_vgprs = MAX2(shader->num_vgprs, (G_00B028_VGPRS(value) + 1) * 4);
2524 break;
2525 case R_00B02C_SPI_SHADER_PGM_RSRC2_PS:
2526 shader->lds_size = MAX2(shader->lds_size, G_00B02C_EXTRA_LDS_SIZE(value));
2527 break;
2528 case R_00B84C_COMPUTE_PGM_RSRC2:
2529 shader->lds_size = MAX2(shader->lds_size, G_00B84C_LDS_SIZE(value));
2530 break;
2531 case R_0286CC_SPI_PS_INPUT_ENA:
2532 shader->spi_ps_input_ena = value;
2533 break;
2534 case R_00B860_COMPUTE_TMPRING_SIZE:
2535 /* WAVESIZE is in units of 256 dwords. */
2536 shader->scratch_bytes_per_wave =
2537 G_00B860_WAVESIZE(value) * 256 * 4 * 1;
2538 break;
2539 default:
2540 fprintf(stderr, "Warning: Compiler emitted unknown "
2541 "config register: 0x%x\n", reg);
2542 break;
2543 }
2544 }
2545 }
2546
2547 int si_shader_binary_read(struct si_screen *sscreen,
2548 struct si_shader *shader,
2549 const struct radeon_shader_binary *binary)
2550 {
2551
2552 unsigned i;
2553 unsigned code_size;
2554 unsigned char *ptr;
2555 bool dump = r600_can_dump_shader(&sscreen->b,
2556 shader->selector ? shader->selector->tokens : NULL);
2557
2558 if (dump && !binary->disassembled) {
2559 fprintf(stderr, "SI CODE:\n");
2560 for (i = 0; i < binary->code_size; i+=4 ) {
2561 fprintf(stderr, "@0x%x: %02x%02x%02x%02x\n", i, binary->code[i + 3],
2562 binary->code[i + 2], binary->code[i + 1],
2563 binary->code[i]);
2564 }
2565 }
2566
2567 si_shader_binary_read_config(binary, shader, 0);
2568
2569 /* copy new shader */
2570 code_size = binary->code_size + binary->rodata_size;
2571 r600_resource_reference(&shader->bo, NULL);
2572 shader->bo = si_resource_create_custom(&sscreen->b.b, PIPE_USAGE_IMMUTABLE,
2573 code_size);
2574 if (shader->bo == NULL) {
2575 return -ENOMEM;
2576 }
2577
2578
2579 ptr = sscreen->b.ws->buffer_map(shader->bo->cs_buf, NULL, PIPE_TRANSFER_READ_WRITE);
2580 util_memcpy_cpu_to_le32(ptr, binary->code, binary->code_size);
2581 if (binary->rodata_size > 0) {
2582 ptr += binary->code_size;
2583 util_memcpy_cpu_to_le32(ptr, binary->rodata, binary->rodata_size);
2584 }
2585
2586 sscreen->b.ws->buffer_unmap(shader->bo->cs_buf);
2587
2588 return 0;
2589 }
2590
2591 int si_compile_llvm(struct si_screen *sscreen, struct si_shader *shader,
2592 LLVMModuleRef mod)
2593 {
2594 int r = 0;
2595 struct radeon_shader_binary binary;
2596 bool dump = r600_can_dump_shader(&sscreen->b,
2597 shader->selector ? shader->selector->tokens : NULL);
2598 memset(&binary, 0, sizeof(binary));
2599 r = radeon_llvm_compile(mod, &binary,
2600 r600_get_llvm_processor_name(sscreen->b.family), dump, sscreen->tm);
2601
2602 if (r) {
2603 return r;
2604 }
2605 r = si_shader_binary_read(sscreen, shader, &binary);
2606 FREE(binary.code);
2607 FREE(binary.config);
2608 FREE(binary.rodata);
2609 return r;
2610 }
2611
2612 /* Generate code for the hardware VS shader stage to go with a geometry shader */
2613 static int si_generate_gs_copy_shader(struct si_screen *sscreen,
2614 struct si_shader_context *si_shader_ctx,
2615 struct si_shader *gs, bool dump)
2616 {
2617 struct gallivm_state *gallivm = &si_shader_ctx->radeon_bld.gallivm;
2618 struct lp_build_tgsi_context *bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
2619 struct lp_build_context *base = &bld_base->base;
2620 struct lp_build_context *uint = &bld_base->uint_bld;
2621 struct si_shader *shader = si_shader_ctx->shader;
2622 struct si_shader_output_values *outputs;
2623 struct tgsi_shader_info *gsinfo = &gs->selector->info;
2624 LLVMValueRef args[9];
2625 int i, r;
2626
2627 outputs = MALLOC(gsinfo->num_outputs * sizeof(outputs[0]));
2628
2629 si_shader_ctx->type = TGSI_PROCESSOR_VERTEX;
2630 shader->is_gs_copy_shader = true;
2631
2632 radeon_llvm_context_init(&si_shader_ctx->radeon_bld);
2633
2634 create_meta_data(si_shader_ctx);
2635 create_function(si_shader_ctx);
2636 preload_streamout_buffers(si_shader_ctx);
2637 preload_ring_buffers(si_shader_ctx);
2638
2639 args[0] = si_shader_ctx->gsvs_ring;
2640 args[1] = lp_build_mul_imm(uint,
2641 LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
2642 si_shader_ctx->param_vertex_id),
2643 4);
2644 args[3] = uint->zero;
2645 args[4] = uint->one; /* OFFEN */
2646 args[5] = uint->zero; /* IDXEN */
2647 args[6] = uint->one; /* GLC */
2648 args[7] = uint->one; /* SLC */
2649 args[8] = uint->zero; /* TFE */
2650
2651 /* Fetch vertex data from GSVS ring */
2652 for (i = 0; i < gsinfo->num_outputs; ++i) {
2653 unsigned chan;
2654
2655 outputs[i].name = gsinfo->output_semantic_name[i];
2656 outputs[i].sid = gsinfo->output_semantic_index[i];
2657
2658 for (chan = 0; chan < 4; chan++) {
2659 args[2] = lp_build_const_int32(gallivm,
2660 (i * 4 + chan) *
2661 gs->selector->gs_max_out_vertices * 16 * 4);
2662
2663 outputs[i].values[chan] =
2664 LLVMBuildBitCast(gallivm->builder,
2665 build_intrinsic(gallivm->builder,
2666 "llvm.SI.buffer.load.dword.i32.i32",
2667 LLVMInt32TypeInContext(gallivm->context),
2668 args, 9,
2669 LLVMReadOnlyAttribute | LLVMNoUnwindAttribute),
2670 base->elem_type, "");
2671 }
2672 }
2673
2674 si_llvm_export_vs(bld_base, outputs, gsinfo->num_outputs);
2675
2676 radeon_llvm_finalize_module(&si_shader_ctx->radeon_bld);
2677
2678 if (dump)
2679 fprintf(stderr, "Copy Vertex Shader for Geometry Shader:\n\n");
2680
2681 r = si_compile_llvm(sscreen, si_shader_ctx->shader,
2682 bld_base->base.gallivm->module);
2683
2684 radeon_llvm_dispose(&si_shader_ctx->radeon_bld);
2685
2686 FREE(outputs);
2687 return r;
2688 }
2689
2690 int si_shader_create(struct si_screen *sscreen, struct si_shader *shader)
2691 {
2692 struct si_shader_selector *sel = shader->selector;
2693 struct si_shader_context si_shader_ctx;
2694 struct lp_build_tgsi_context * bld_base;
2695 LLVMModuleRef mod;
2696 int r = 0;
2697 bool dump = r600_can_dump_shader(&sscreen->b, sel->tokens);
2698
2699 /* Dump TGSI code before doing TGSI->LLVM conversion in case the
2700 * conversion fails. */
2701 if (dump) {
2702 tgsi_dump(sel->tokens, 0);
2703 si_dump_streamout(&sel->so);
2704 }
2705
2706 assert(shader->nparam == 0);
2707
2708 memset(&si_shader_ctx, 0, sizeof(si_shader_ctx));
2709 radeon_llvm_context_init(&si_shader_ctx.radeon_bld);
2710 bld_base = &si_shader_ctx.radeon_bld.soa.bld_base;
2711
2712 if (sel->info.uses_kill)
2713 shader->db_shader_control |= S_02880C_KILL_ENABLE(1);
2714
2715 shader->uses_instanceid = sel->info.uses_instanceid;
2716 bld_base->info = &sel->info;
2717 bld_base->emit_fetch_funcs[TGSI_FILE_CONSTANT] = fetch_constant;
2718
2719 bld_base->op_actions[TGSI_OPCODE_TEX] = tex_action;
2720 bld_base->op_actions[TGSI_OPCODE_TEX2] = tex_action;
2721 bld_base->op_actions[TGSI_OPCODE_TXB] = tex_action;
2722 bld_base->op_actions[TGSI_OPCODE_TXB2] = tex_action;
2723 bld_base->op_actions[TGSI_OPCODE_TXD] = tex_action;
2724 bld_base->op_actions[TGSI_OPCODE_TXF] = tex_action;
2725 bld_base->op_actions[TGSI_OPCODE_TXL] = tex_action;
2726 bld_base->op_actions[TGSI_OPCODE_TXL2] = tex_action;
2727 bld_base->op_actions[TGSI_OPCODE_TXP] = tex_action;
2728 bld_base->op_actions[TGSI_OPCODE_TXQ] = txq_action;
2729 bld_base->op_actions[TGSI_OPCODE_TG4] = tex_action;
2730 bld_base->op_actions[TGSI_OPCODE_LODQ] = tex_action;
2731
2732 bld_base->op_actions[TGSI_OPCODE_DDX].emit = si_llvm_emit_ddxy;
2733 bld_base->op_actions[TGSI_OPCODE_DDY].emit = si_llvm_emit_ddxy;
2734
2735 bld_base->op_actions[TGSI_OPCODE_EMIT].emit = si_llvm_emit_vertex;
2736 bld_base->op_actions[TGSI_OPCODE_ENDPRIM].emit = si_llvm_emit_primitive;
2737
2738 if (HAVE_LLVM >= 0x0306) {
2739 bld_base->op_actions[TGSI_OPCODE_MAX].emit = build_tgsi_intrinsic_nomem;
2740 bld_base->op_actions[TGSI_OPCODE_MAX].intr_name = "llvm.maxnum.f32";
2741 bld_base->op_actions[TGSI_OPCODE_MIN].emit = build_tgsi_intrinsic_nomem;
2742 bld_base->op_actions[TGSI_OPCODE_MIN].intr_name = "llvm.minnum.f32";
2743 }
2744
2745 si_shader_ctx.radeon_bld.load_system_value = declare_system_value;
2746 si_shader_ctx.tokens = sel->tokens;
2747 tgsi_parse_init(&si_shader_ctx.parse, si_shader_ctx.tokens);
2748 si_shader_ctx.shader = shader;
2749 si_shader_ctx.type = si_shader_ctx.parse.FullHeader.Processor.Processor;
2750 si_shader_ctx.screen = sscreen;
2751
2752 switch (si_shader_ctx.type) {
2753 case TGSI_PROCESSOR_VERTEX:
2754 si_shader_ctx.radeon_bld.load_input = declare_input_vs;
2755 if (shader->key.vs.as_es) {
2756 bld_base->emit_epilogue = si_llvm_emit_es_epilogue;
2757 } else {
2758 bld_base->emit_epilogue = si_llvm_emit_vs_epilogue;
2759 }
2760 break;
2761 case TGSI_PROCESSOR_GEOMETRY:
2762 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_gs;
2763 bld_base->emit_epilogue = si_llvm_emit_gs_epilogue;
2764 break;
2765 case TGSI_PROCESSOR_FRAGMENT:
2766 si_shader_ctx.radeon_bld.load_input = declare_input_fs;
2767 bld_base->emit_epilogue = si_llvm_emit_fs_epilogue;
2768
2769 switch (sel->info.properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT]) {
2770 case TGSI_FS_DEPTH_LAYOUT_GREATER:
2771 shader->db_shader_control |=
2772 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_GREATER_THAN_Z);
2773 break;
2774 case TGSI_FS_DEPTH_LAYOUT_LESS:
2775 shader->db_shader_control |=
2776 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_LESS_THAN_Z);
2777 break;
2778 }
2779 break;
2780 default:
2781 assert(!"Unsupported shader type");
2782 return -1;
2783 }
2784
2785 create_meta_data(&si_shader_ctx);
2786 create_function(&si_shader_ctx);
2787 preload_constants(&si_shader_ctx);
2788 preload_samplers(&si_shader_ctx);
2789 preload_streamout_buffers(&si_shader_ctx);
2790 preload_ring_buffers(&si_shader_ctx);
2791
2792 if (si_shader_ctx.type == TGSI_PROCESSOR_GEOMETRY) {
2793 si_shader_ctx.gs_next_vertex =
2794 lp_build_alloca(bld_base->base.gallivm,
2795 bld_base->uint_bld.elem_type, "");
2796 }
2797
2798 if (!lp_build_tgsi_llvm(bld_base, sel->tokens)) {
2799 fprintf(stderr, "Failed to translate shader from TGSI to LLVM\n");
2800 goto out;
2801 }
2802
2803 radeon_llvm_finalize_module(&si_shader_ctx.radeon_bld);
2804
2805 mod = bld_base->base.gallivm->module;
2806 r = si_compile_llvm(sscreen, shader, mod);
2807 if (r) {
2808 fprintf(stderr, "LLVM failed to compile shader\n");
2809 goto out;
2810 }
2811
2812 radeon_llvm_dispose(&si_shader_ctx.radeon_bld);
2813
2814 if (si_shader_ctx.type == TGSI_PROCESSOR_GEOMETRY) {
2815 shader->gs_copy_shader = CALLOC_STRUCT(si_shader);
2816 shader->gs_copy_shader->selector = shader->selector;
2817 shader->gs_copy_shader->key = shader->key;
2818 si_shader_ctx.shader = shader->gs_copy_shader;
2819 if ((r = si_generate_gs_copy_shader(sscreen, &si_shader_ctx,
2820 shader, dump))) {
2821 free(shader->gs_copy_shader);
2822 shader->gs_copy_shader = NULL;
2823 goto out;
2824 }
2825 }
2826
2827 tgsi_parse_free(&si_shader_ctx.parse);
2828
2829 out:
2830 for (int i = 0; i < SI_NUM_CONST_BUFFERS; i++)
2831 FREE(si_shader_ctx.constants[i]);
2832
2833 return r;
2834 }
2835
2836 void si_shader_destroy(struct pipe_context *ctx, struct si_shader *shader)
2837 {
2838 if (shader->gs_copy_shader)
2839 si_shader_destroy(ctx, shader->gs_copy_shader);
2840
2841 r600_resource_reference(&shader->bo, NULL);
2842 r600_resource_reference(&shader->scratch_bo, NULL);
2843 }