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radeonsi: use postponed KILL only when derivatives are used
[mesa.git] / src / gallium / drivers / radeonsi / si_shader.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Tom Stellard <thomas.stellard@amd.com>
25 * Michel Dänzer <michel.daenzer@amd.com>
26 * Christian König <christian.koenig@amd.com>
27 */
28
29 #include "gallivm/lp_bld_const.h"
30 #include "gallivm/lp_bld_gather.h"
31 #include "gallivm/lp_bld_intr.h"
32 #include "gallivm/lp_bld_logic.h"
33 #include "gallivm/lp_bld_arit.h"
34 #include "gallivm/lp_bld_flow.h"
35 #include "gallivm/lp_bld_misc.h"
36 #include "util/u_memory.h"
37 #include "util/u_string.h"
38 #include "tgsi/tgsi_build.h"
39 #include "tgsi/tgsi_util.h"
40 #include "tgsi/tgsi_dump.h"
41
42 #include "ac_binary.h"
43 #include "ac_llvm_util.h"
44 #include "ac_exp_param.h"
45 #include "si_shader_internal.h"
46 #include "si_pipe.h"
47 #include "sid.h"
48
49 #include "compiler/nir/nir.h"
50
51 static const char *scratch_rsrc_dword0_symbol =
52 "SCRATCH_RSRC_DWORD0";
53
54 static const char *scratch_rsrc_dword1_symbol =
55 "SCRATCH_RSRC_DWORD1";
56
57 struct si_shader_output_values
58 {
59 LLVMValueRef values[4];
60 unsigned semantic_name;
61 unsigned semantic_index;
62 ubyte vertex_stream[4];
63 };
64
65 /**
66 * Used to collect types and other info about arguments of the LLVM function
67 * before the function is created.
68 */
69 struct si_function_info {
70 LLVMTypeRef types[100];
71 LLVMValueRef *assign[100];
72 unsigned num_sgpr_params;
73 unsigned num_params;
74 };
75
76 enum si_arg_regfile {
77 ARG_SGPR,
78 ARG_VGPR
79 };
80
81 static void si_init_shader_ctx(struct si_shader_context *ctx,
82 struct si_screen *sscreen,
83 LLVMTargetMachineRef tm);
84
85 static void si_llvm_emit_barrier(const struct lp_build_tgsi_action *action,
86 struct lp_build_tgsi_context *bld_base,
87 struct lp_build_emit_data *emit_data);
88
89 static void si_dump_shader_key(unsigned processor, const struct si_shader *shader,
90 FILE *f);
91
92 static void si_build_vs_prolog_function(struct si_shader_context *ctx,
93 union si_shader_part_key *key);
94 static void si_build_tcs_epilog_function(struct si_shader_context *ctx,
95 union si_shader_part_key *key);
96 static void si_build_ps_prolog_function(struct si_shader_context *ctx,
97 union si_shader_part_key *key);
98 static void si_build_ps_epilog_function(struct si_shader_context *ctx,
99 union si_shader_part_key *key);
100
101 /* Ideally pass the sample mask input to the PS epilog as v14, which
102 * is its usual location, so that the shader doesn't have to add v_mov.
103 */
104 #define PS_EPILOG_SAMPLEMASK_MIN_LOC 14
105
106 enum {
107 CONST_ADDR_SPACE = 2,
108 LOCAL_ADDR_SPACE = 3,
109 };
110
111 static bool is_merged_shader(struct si_shader *shader)
112 {
113 if (shader->selector->screen->b.chip_class <= VI)
114 return false;
115
116 return shader->key.as_ls ||
117 shader->key.as_es ||
118 shader->selector->type == PIPE_SHADER_TESS_CTRL ||
119 shader->selector->type == PIPE_SHADER_GEOMETRY;
120 }
121
122 static void si_init_function_info(struct si_function_info *fninfo)
123 {
124 fninfo->num_params = 0;
125 fninfo->num_sgpr_params = 0;
126 }
127
128 static unsigned add_arg_assign(struct si_function_info *fninfo,
129 enum si_arg_regfile regfile, LLVMTypeRef type,
130 LLVMValueRef *assign)
131 {
132 assert(regfile != ARG_SGPR || fninfo->num_sgpr_params == fninfo->num_params);
133
134 unsigned idx = fninfo->num_params++;
135 assert(idx < ARRAY_SIZE(fninfo->types));
136
137 if (regfile == ARG_SGPR)
138 fninfo->num_sgpr_params = fninfo->num_params;
139
140 fninfo->types[idx] = type;
141 fninfo->assign[idx] = assign;
142 return idx;
143 }
144
145 static unsigned add_arg(struct si_function_info *fninfo,
146 enum si_arg_regfile regfile, LLVMTypeRef type)
147 {
148 return add_arg_assign(fninfo, regfile, type, NULL);
149 }
150
151 static void add_arg_assign_checked(struct si_function_info *fninfo,
152 enum si_arg_regfile regfile, LLVMTypeRef type,
153 LLVMValueRef *assign, unsigned idx)
154 {
155 MAYBE_UNUSED unsigned actual = add_arg_assign(fninfo, regfile, type, assign);
156 assert(actual == idx);
157 }
158
159 static void add_arg_checked(struct si_function_info *fninfo,
160 enum si_arg_regfile regfile, LLVMTypeRef type,
161 unsigned idx)
162 {
163 add_arg_assign_checked(fninfo, regfile, type, NULL, idx);
164 }
165
166 /**
167 * Returns a unique index for a per-patch semantic name and index. The index
168 * must be less than 32, so that a 32-bit bitmask of used inputs or outputs
169 * can be calculated.
170 */
171 unsigned si_shader_io_get_unique_index_patch(unsigned semantic_name, unsigned index)
172 {
173 switch (semantic_name) {
174 case TGSI_SEMANTIC_TESSOUTER:
175 return 0;
176 case TGSI_SEMANTIC_TESSINNER:
177 return 1;
178 case TGSI_SEMANTIC_PATCH:
179 assert(index < 30);
180 return 2 + index;
181
182 default:
183 assert(!"invalid semantic name");
184 return 0;
185 }
186 }
187
188 /**
189 * Returns a unique index for a semantic name and index. The index must be
190 * less than 64, so that a 64-bit bitmask of used inputs or outputs can be
191 * calculated.
192 */
193 unsigned si_shader_io_get_unique_index(unsigned semantic_name, unsigned index)
194 {
195 switch (semantic_name) {
196 case TGSI_SEMANTIC_POSITION:
197 return 0;
198 case TGSI_SEMANTIC_GENERIC:
199 /* Since some shader stages use the the highest used IO index
200 * to determine the size to allocate for inputs/outputs
201 * (in LDS, tess and GS rings). GENERIC should be placed right
202 * after POSITION to make that size as small as possible.
203 */
204 if (index < SI_MAX_IO_GENERIC)
205 return 1 + index;
206
207 assert(!"invalid generic index");
208 return 0;
209 case TGSI_SEMANTIC_PSIZE:
210 return SI_MAX_IO_GENERIC + 1;
211 case TGSI_SEMANTIC_CLIPDIST:
212 assert(index <= 1);
213 return SI_MAX_IO_GENERIC + 2 + index;
214 case TGSI_SEMANTIC_FOG:
215 return SI_MAX_IO_GENERIC + 4;
216 case TGSI_SEMANTIC_LAYER:
217 return SI_MAX_IO_GENERIC + 5;
218 case TGSI_SEMANTIC_VIEWPORT_INDEX:
219 return SI_MAX_IO_GENERIC + 6;
220 case TGSI_SEMANTIC_PRIMID:
221 return SI_MAX_IO_GENERIC + 7;
222 case TGSI_SEMANTIC_COLOR: /* these alias */
223 case TGSI_SEMANTIC_BCOLOR:
224 assert(index < 2);
225 return SI_MAX_IO_GENERIC + 8 + index;
226 case TGSI_SEMANTIC_TEXCOORD:
227 assert(index < 8);
228 assert(SI_MAX_IO_GENERIC + 10 + index < 64);
229 return SI_MAX_IO_GENERIC + 10 + index;
230 default:
231 assert(!"invalid semantic name");
232 return 0;
233 }
234 }
235
236 /**
237 * Get the value of a shader input parameter and extract a bitfield.
238 */
239 static LLVMValueRef unpack_param(struct si_shader_context *ctx,
240 unsigned param, unsigned rshift,
241 unsigned bitwidth)
242 {
243 LLVMValueRef value = LLVMGetParam(ctx->main_fn,
244 param);
245
246 if (LLVMGetTypeKind(LLVMTypeOf(value)) == LLVMFloatTypeKind)
247 value = ac_to_integer(&ctx->ac, value);
248
249 if (rshift)
250 value = LLVMBuildLShr(ctx->ac.builder, value,
251 LLVMConstInt(ctx->i32, rshift, 0), "");
252
253 if (rshift + bitwidth < 32) {
254 unsigned mask = (1 << bitwidth) - 1;
255 value = LLVMBuildAnd(ctx->ac.builder, value,
256 LLVMConstInt(ctx->i32, mask, 0), "");
257 }
258
259 return value;
260 }
261
262 static LLVMValueRef get_rel_patch_id(struct si_shader_context *ctx)
263 {
264 switch (ctx->type) {
265 case PIPE_SHADER_TESS_CTRL:
266 return unpack_param(ctx, ctx->param_tcs_rel_ids, 0, 8);
267
268 case PIPE_SHADER_TESS_EVAL:
269 return LLVMGetParam(ctx->main_fn,
270 ctx->param_tes_rel_patch_id);
271
272 default:
273 assert(0);
274 return NULL;
275 }
276 }
277
278 /* Tessellation shaders pass outputs to the next shader using LDS.
279 *
280 * LS outputs = TCS inputs
281 * TCS outputs = TES inputs
282 *
283 * The LDS layout is:
284 * - TCS inputs for patch 0
285 * - TCS inputs for patch 1
286 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
287 * - ...
288 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
289 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
290 * - TCS outputs for patch 1
291 * - Per-patch TCS outputs for patch 1
292 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
293 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
294 * - ...
295 *
296 * All three shaders VS(LS), TCS, TES share the same LDS space.
297 */
298
299 static LLVMValueRef
300 get_tcs_in_patch_stride(struct si_shader_context *ctx)
301 {
302 return unpack_param(ctx, ctx->param_vs_state_bits, 8, 13);
303 }
304
305 static unsigned get_tcs_out_vertex_dw_stride_constant(struct si_shader_context *ctx)
306 {
307 assert(ctx->type == PIPE_SHADER_TESS_CTRL);
308
309 if (ctx->shader->key.mono.u.ff_tcs_inputs_to_copy)
310 return util_last_bit64(ctx->shader->key.mono.u.ff_tcs_inputs_to_copy) * 4;
311
312 return util_last_bit64(ctx->shader->selector->outputs_written) * 4;
313 }
314
315 static LLVMValueRef get_tcs_out_vertex_dw_stride(struct si_shader_context *ctx)
316 {
317 unsigned stride = get_tcs_out_vertex_dw_stride_constant(ctx);
318
319 return LLVMConstInt(ctx->i32, stride, 0);
320 }
321
322 static LLVMValueRef get_tcs_out_patch_stride(struct si_shader_context *ctx)
323 {
324 if (ctx->shader->key.mono.u.ff_tcs_inputs_to_copy)
325 return unpack_param(ctx, ctx->param_tcs_out_lds_layout, 0, 13);
326
327 const struct tgsi_shader_info *info = &ctx->shader->selector->info;
328 unsigned tcs_out_vertices = info->properties[TGSI_PROPERTY_TCS_VERTICES_OUT];
329 unsigned vertex_dw_stride = get_tcs_out_vertex_dw_stride_constant(ctx);
330 unsigned num_patch_outputs = util_last_bit64(ctx->shader->selector->patch_outputs_written);
331 unsigned patch_dw_stride = tcs_out_vertices * vertex_dw_stride +
332 num_patch_outputs * 4;
333 return LLVMConstInt(ctx->i32, patch_dw_stride, 0);
334 }
335
336 static LLVMValueRef
337 get_tcs_out_patch0_offset(struct si_shader_context *ctx)
338 {
339 return lp_build_mul_imm(&ctx->bld_base.uint_bld,
340 unpack_param(ctx,
341 ctx->param_tcs_out_lds_offsets,
342 0, 16),
343 4);
344 }
345
346 static LLVMValueRef
347 get_tcs_out_patch0_patch_data_offset(struct si_shader_context *ctx)
348 {
349 return lp_build_mul_imm(&ctx->bld_base.uint_bld,
350 unpack_param(ctx,
351 ctx->param_tcs_out_lds_offsets,
352 16, 16),
353 4);
354 }
355
356 static LLVMValueRef
357 get_tcs_in_current_patch_offset(struct si_shader_context *ctx)
358 {
359 LLVMValueRef patch_stride = get_tcs_in_patch_stride(ctx);
360 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
361
362 return LLVMBuildMul(ctx->ac.builder, patch_stride, rel_patch_id, "");
363 }
364
365 static LLVMValueRef
366 get_tcs_out_current_patch_offset(struct si_shader_context *ctx)
367 {
368 LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(ctx);
369 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
370 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
371
372 return LLVMBuildAdd(ctx->ac.builder, patch0_offset,
373 LLVMBuildMul(ctx->ac.builder, patch_stride,
374 rel_patch_id, ""),
375 "");
376 }
377
378 static LLVMValueRef
379 get_tcs_out_current_patch_data_offset(struct si_shader_context *ctx)
380 {
381 LLVMValueRef patch0_patch_data_offset =
382 get_tcs_out_patch0_patch_data_offset(ctx);
383 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
384 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
385
386 return LLVMBuildAdd(ctx->ac.builder, patch0_patch_data_offset,
387 LLVMBuildMul(ctx->ac.builder, patch_stride,
388 rel_patch_id, ""),
389 "");
390 }
391
392 static LLVMValueRef get_num_tcs_out_vertices(struct si_shader_context *ctx)
393 {
394 unsigned tcs_out_vertices =
395 ctx->shader->selector ?
396 ctx->shader->selector->info.properties[TGSI_PROPERTY_TCS_VERTICES_OUT] : 0;
397
398 /* If !tcs_out_vertices, it's either the fixed-func TCS or the TCS epilog. */
399 if (ctx->type == PIPE_SHADER_TESS_CTRL && tcs_out_vertices)
400 return LLVMConstInt(ctx->i32, tcs_out_vertices, 0);
401
402 return unpack_param(ctx, ctx->param_tcs_offchip_layout, 6, 6);
403 }
404
405 static LLVMValueRef get_tcs_in_vertex_dw_stride(struct si_shader_context *ctx)
406 {
407 unsigned stride;
408
409 switch (ctx->type) {
410 case PIPE_SHADER_VERTEX:
411 stride = util_last_bit64(ctx->shader->selector->outputs_written);
412 return LLVMConstInt(ctx->i32, stride * 4, 0);
413
414 case PIPE_SHADER_TESS_CTRL:
415 if (ctx->screen->b.chip_class >= GFX9 &&
416 ctx->shader->is_monolithic) {
417 stride = util_last_bit64(ctx->shader->key.part.tcs.ls->outputs_written);
418 return LLVMConstInt(ctx->i32, stride * 4, 0);
419 }
420 return unpack_param(ctx, ctx->param_vs_state_bits, 24, 8);
421
422 default:
423 assert(0);
424 return NULL;
425 }
426 }
427
428 static LLVMValueRef get_instance_index_for_fetch(
429 struct si_shader_context *ctx,
430 unsigned param_start_instance, LLVMValueRef divisor)
431 {
432 LLVMValueRef result = ctx->abi.instance_id;
433
434 /* The division must be done before START_INSTANCE is added. */
435 if (divisor != ctx->i32_1)
436 result = LLVMBuildUDiv(ctx->ac.builder, result, divisor, "");
437
438 return LLVMBuildAdd(ctx->ac.builder, result,
439 LLVMGetParam(ctx->main_fn, param_start_instance), "");
440 }
441
442 /* Bitcast <4 x float> to <2 x double>, extract the component, and convert
443 * to float. */
444 static LLVMValueRef extract_double_to_float(struct si_shader_context *ctx,
445 LLVMValueRef vec4,
446 unsigned double_index)
447 {
448 LLVMBuilderRef builder = ctx->ac.builder;
449 LLVMTypeRef f64 = LLVMDoubleTypeInContext(ctx->ac.context);
450 LLVMValueRef dvec2 = LLVMBuildBitCast(builder, vec4,
451 LLVMVectorType(f64, 2), "");
452 LLVMValueRef index = LLVMConstInt(ctx->i32, double_index, 0);
453 LLVMValueRef value = LLVMBuildExtractElement(builder, dvec2, index, "");
454 return LLVMBuildFPTrunc(builder, value, ctx->f32, "");
455 }
456
457 static LLVMValueRef unpack_sint16(struct si_shader_context *ctx,
458 LLVMValueRef i32, unsigned index)
459 {
460 assert(index <= 1);
461
462 if (index == 1)
463 return LLVMBuildAShr(ctx->ac.builder, i32,
464 LLVMConstInt(ctx->i32, 16, 0), "");
465
466 return LLVMBuildSExt(ctx->ac.builder,
467 LLVMBuildTrunc(ctx->ac.builder, i32,
468 ctx->ac.i16, ""),
469 ctx->i32, "");
470 }
471
472 void si_llvm_load_input_vs(
473 struct si_shader_context *ctx,
474 unsigned input_index,
475 LLVMValueRef out[4])
476 {
477 unsigned vs_blit_property =
478 ctx->shader->selector->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS];
479
480 if (vs_blit_property) {
481 LLVMValueRef vertex_id = ctx->abi.vertex_id;
482 LLVMValueRef sel_x1 = LLVMBuildICmp(ctx->ac.builder,
483 LLVMIntULE, vertex_id,
484 ctx->i32_1, "");
485 /* Use LLVMIntNE, because we have 3 vertices and only
486 * the middle one should use y2.
487 */
488 LLVMValueRef sel_y1 = LLVMBuildICmp(ctx->ac.builder,
489 LLVMIntNE, vertex_id,
490 ctx->i32_1, "");
491
492 if (input_index == 0) {
493 /* Position: */
494 LLVMValueRef x1y1 = LLVMGetParam(ctx->main_fn,
495 ctx->param_vs_blit_inputs);
496 LLVMValueRef x2y2 = LLVMGetParam(ctx->main_fn,
497 ctx->param_vs_blit_inputs + 1);
498
499 LLVMValueRef x1 = unpack_sint16(ctx, x1y1, 0);
500 LLVMValueRef y1 = unpack_sint16(ctx, x1y1, 1);
501 LLVMValueRef x2 = unpack_sint16(ctx, x2y2, 0);
502 LLVMValueRef y2 = unpack_sint16(ctx, x2y2, 1);
503
504 LLVMValueRef x = LLVMBuildSelect(ctx->ac.builder, sel_x1,
505 x1, x2, "");
506 LLVMValueRef y = LLVMBuildSelect(ctx->ac.builder, sel_y1,
507 y1, y2, "");
508
509 out[0] = LLVMBuildSIToFP(ctx->ac.builder, x, ctx->f32, "");
510 out[1] = LLVMBuildSIToFP(ctx->ac.builder, y, ctx->f32, "");
511 out[2] = LLVMGetParam(ctx->main_fn,
512 ctx->param_vs_blit_inputs + 2);
513 out[3] = ctx->ac.f32_1;
514 return;
515 }
516
517 /* Color or texture coordinates: */
518 assert(input_index == 1);
519
520 if (vs_blit_property == SI_VS_BLIT_SGPRS_POS_COLOR) {
521 for (int i = 0; i < 4; i++) {
522 out[i] = LLVMGetParam(ctx->main_fn,
523 ctx->param_vs_blit_inputs + 3 + i);
524 }
525 } else {
526 assert(vs_blit_property == SI_VS_BLIT_SGPRS_POS_TEXCOORD);
527 LLVMValueRef x1 = LLVMGetParam(ctx->main_fn,
528 ctx->param_vs_blit_inputs + 3);
529 LLVMValueRef y1 = LLVMGetParam(ctx->main_fn,
530 ctx->param_vs_blit_inputs + 4);
531 LLVMValueRef x2 = LLVMGetParam(ctx->main_fn,
532 ctx->param_vs_blit_inputs + 5);
533 LLVMValueRef y2 = LLVMGetParam(ctx->main_fn,
534 ctx->param_vs_blit_inputs + 6);
535
536 out[0] = LLVMBuildSelect(ctx->ac.builder, sel_x1,
537 x1, x2, "");
538 out[1] = LLVMBuildSelect(ctx->ac.builder, sel_y1,
539 y1, y2, "");
540 out[2] = LLVMGetParam(ctx->main_fn,
541 ctx->param_vs_blit_inputs + 7);
542 out[3] = LLVMGetParam(ctx->main_fn,
543 ctx->param_vs_blit_inputs + 8);
544 }
545 return;
546 }
547
548 unsigned chan;
549 unsigned fix_fetch;
550 unsigned num_fetches;
551 unsigned fetch_stride;
552
553 LLVMValueRef t_list_ptr;
554 LLVMValueRef t_offset;
555 LLVMValueRef t_list;
556 LLVMValueRef vertex_index;
557 LLVMValueRef input[3];
558
559 /* Load the T list */
560 t_list_ptr = LLVMGetParam(ctx->main_fn, ctx->param_vertex_buffers);
561
562 t_offset = LLVMConstInt(ctx->i32, input_index, 0);
563
564 t_list = ac_build_load_to_sgpr(&ctx->ac, t_list_ptr, t_offset);
565
566 vertex_index = LLVMGetParam(ctx->main_fn,
567 ctx->param_vertex_index0 +
568 input_index);
569
570 fix_fetch = ctx->shader->key.mono.vs_fix_fetch[input_index];
571
572 /* Do multiple loads for special formats. */
573 switch (fix_fetch) {
574 case SI_FIX_FETCH_RGB_64_FLOAT:
575 num_fetches = 3; /* 3 2-dword loads */
576 fetch_stride = 8;
577 break;
578 case SI_FIX_FETCH_RGBA_64_FLOAT:
579 num_fetches = 2; /* 2 4-dword loads */
580 fetch_stride = 16;
581 break;
582 case SI_FIX_FETCH_RGB_8:
583 case SI_FIX_FETCH_RGB_8_INT:
584 num_fetches = 3;
585 fetch_stride = 1;
586 break;
587 case SI_FIX_FETCH_RGB_16:
588 case SI_FIX_FETCH_RGB_16_INT:
589 num_fetches = 3;
590 fetch_stride = 2;
591 break;
592 default:
593 num_fetches = 1;
594 fetch_stride = 0;
595 }
596
597 for (unsigned i = 0; i < num_fetches; i++) {
598 LLVMValueRef voffset = LLVMConstInt(ctx->i32, fetch_stride * i, 0);
599
600 input[i] = ac_build_buffer_load_format(&ctx->ac, t_list,
601 vertex_index, voffset,
602 true);
603 }
604
605 /* Break up the vec4 into individual components */
606 for (chan = 0; chan < 4; chan++) {
607 LLVMValueRef llvm_chan = LLVMConstInt(ctx->i32, chan, 0);
608 out[chan] = LLVMBuildExtractElement(ctx->ac.builder,
609 input[0], llvm_chan, "");
610 }
611
612 switch (fix_fetch) {
613 case SI_FIX_FETCH_A2_SNORM:
614 case SI_FIX_FETCH_A2_SSCALED:
615 case SI_FIX_FETCH_A2_SINT: {
616 /* The hardware returns an unsigned value; convert it to a
617 * signed one.
618 */
619 LLVMValueRef tmp = out[3];
620 LLVMValueRef c30 = LLVMConstInt(ctx->i32, 30, 0);
621
622 /* First, recover the sign-extended signed integer value. */
623 if (fix_fetch == SI_FIX_FETCH_A2_SSCALED)
624 tmp = LLVMBuildFPToUI(ctx->ac.builder, tmp, ctx->i32, "");
625 else
626 tmp = ac_to_integer(&ctx->ac, tmp);
627
628 /* For the integer-like cases, do a natural sign extension.
629 *
630 * For the SNORM case, the values are 0.0, 0.333, 0.666, 1.0
631 * and happen to contain 0, 1, 2, 3 as the two LSBs of the
632 * exponent.
633 */
634 tmp = LLVMBuildShl(ctx->ac.builder, tmp,
635 fix_fetch == SI_FIX_FETCH_A2_SNORM ?
636 LLVMConstInt(ctx->i32, 7, 0) : c30, "");
637 tmp = LLVMBuildAShr(ctx->ac.builder, tmp, c30, "");
638
639 /* Convert back to the right type. */
640 if (fix_fetch == SI_FIX_FETCH_A2_SNORM) {
641 LLVMValueRef clamp;
642 LLVMValueRef neg_one = LLVMConstReal(ctx->f32, -1.0);
643 tmp = LLVMBuildSIToFP(ctx->ac.builder, tmp, ctx->f32, "");
644 clamp = LLVMBuildFCmp(ctx->ac.builder, LLVMRealULT, tmp, neg_one, "");
645 tmp = LLVMBuildSelect(ctx->ac.builder, clamp, neg_one, tmp, "");
646 } else if (fix_fetch == SI_FIX_FETCH_A2_SSCALED) {
647 tmp = LLVMBuildSIToFP(ctx->ac.builder, tmp, ctx->f32, "");
648 }
649
650 out[3] = tmp;
651 break;
652 }
653 case SI_FIX_FETCH_RGBA_32_UNORM:
654 case SI_FIX_FETCH_RGBX_32_UNORM:
655 for (chan = 0; chan < 4; chan++) {
656 out[chan] = ac_to_integer(&ctx->ac, out[chan]);
657 out[chan] = LLVMBuildUIToFP(ctx->ac.builder,
658 out[chan], ctx->f32, "");
659 out[chan] = LLVMBuildFMul(ctx->ac.builder, out[chan],
660 LLVMConstReal(ctx->f32, 1.0 / UINT_MAX), "");
661 }
662 /* RGBX UINT returns 1 in alpha, which would be rounded to 0 by normalizing. */
663 if (fix_fetch == SI_FIX_FETCH_RGBX_32_UNORM)
664 out[3] = LLVMConstReal(ctx->f32, 1);
665 break;
666 case SI_FIX_FETCH_RGBA_32_SNORM:
667 case SI_FIX_FETCH_RGBX_32_SNORM:
668 case SI_FIX_FETCH_RGBA_32_FIXED:
669 case SI_FIX_FETCH_RGBX_32_FIXED: {
670 double scale;
671 if (fix_fetch >= SI_FIX_FETCH_RGBA_32_FIXED)
672 scale = 1.0 / 0x10000;
673 else
674 scale = 1.0 / INT_MAX;
675
676 for (chan = 0; chan < 4; chan++) {
677 out[chan] = ac_to_integer(&ctx->ac, out[chan]);
678 out[chan] = LLVMBuildSIToFP(ctx->ac.builder,
679 out[chan], ctx->f32, "");
680 out[chan] = LLVMBuildFMul(ctx->ac.builder, out[chan],
681 LLVMConstReal(ctx->f32, scale), "");
682 }
683 /* RGBX SINT returns 1 in alpha, which would be rounded to 0 by normalizing. */
684 if (fix_fetch == SI_FIX_FETCH_RGBX_32_SNORM ||
685 fix_fetch == SI_FIX_FETCH_RGBX_32_FIXED)
686 out[3] = LLVMConstReal(ctx->f32, 1);
687 break;
688 }
689 case SI_FIX_FETCH_RGBA_32_USCALED:
690 for (chan = 0; chan < 4; chan++) {
691 out[chan] = ac_to_integer(&ctx->ac, out[chan]);
692 out[chan] = LLVMBuildUIToFP(ctx->ac.builder,
693 out[chan], ctx->f32, "");
694 }
695 break;
696 case SI_FIX_FETCH_RGBA_32_SSCALED:
697 for (chan = 0; chan < 4; chan++) {
698 out[chan] = ac_to_integer(&ctx->ac, out[chan]);
699 out[chan] = LLVMBuildSIToFP(ctx->ac.builder,
700 out[chan], ctx->f32, "");
701 }
702 break;
703 case SI_FIX_FETCH_RG_64_FLOAT:
704 for (chan = 0; chan < 2; chan++)
705 out[chan] = extract_double_to_float(ctx, input[0], chan);
706
707 out[2] = LLVMConstReal(ctx->f32, 0);
708 out[3] = LLVMConstReal(ctx->f32, 1);
709 break;
710 case SI_FIX_FETCH_RGB_64_FLOAT:
711 for (chan = 0; chan < 3; chan++)
712 out[chan] = extract_double_to_float(ctx, input[chan], 0);
713
714 out[3] = LLVMConstReal(ctx->f32, 1);
715 break;
716 case SI_FIX_FETCH_RGBA_64_FLOAT:
717 for (chan = 0; chan < 4; chan++) {
718 out[chan] = extract_double_to_float(ctx, input[chan / 2],
719 chan % 2);
720 }
721 break;
722 case SI_FIX_FETCH_RGB_8:
723 case SI_FIX_FETCH_RGB_8_INT:
724 case SI_FIX_FETCH_RGB_16:
725 case SI_FIX_FETCH_RGB_16_INT:
726 for (chan = 0; chan < 3; chan++) {
727 out[chan] = LLVMBuildExtractElement(ctx->ac.builder,
728 input[chan],
729 ctx->i32_0, "");
730 }
731 if (fix_fetch == SI_FIX_FETCH_RGB_8 ||
732 fix_fetch == SI_FIX_FETCH_RGB_16) {
733 out[3] = LLVMConstReal(ctx->f32, 1);
734 } else {
735 out[3] = ac_to_float(&ctx->ac, ctx->i32_1);
736 }
737 break;
738 }
739 }
740
741 static void declare_input_vs(
742 struct si_shader_context *ctx,
743 unsigned input_index,
744 const struct tgsi_full_declaration *decl,
745 LLVMValueRef out[4])
746 {
747 si_llvm_load_input_vs(ctx, input_index, out);
748 }
749
750 static LLVMValueRef get_primitive_id(struct si_shader_context *ctx,
751 unsigned swizzle)
752 {
753 if (swizzle > 0)
754 return ctx->i32_0;
755
756 switch (ctx->type) {
757 case PIPE_SHADER_VERTEX:
758 return LLVMGetParam(ctx->main_fn,
759 ctx->param_vs_prim_id);
760 case PIPE_SHADER_TESS_CTRL:
761 return LLVMGetParam(ctx->main_fn,
762 ctx->param_tcs_patch_id);
763 case PIPE_SHADER_TESS_EVAL:
764 return LLVMGetParam(ctx->main_fn,
765 ctx->param_tes_patch_id);
766 case PIPE_SHADER_GEOMETRY:
767 return LLVMGetParam(ctx->main_fn,
768 ctx->param_gs_prim_id);
769 default:
770 assert(0);
771 return ctx->i32_0;
772 }
773 }
774
775 /**
776 * Return the value of tgsi_ind_register for indexing.
777 * This is the indirect index with the constant offset added to it.
778 */
779 LLVMValueRef si_get_indirect_index(struct si_shader_context *ctx,
780 const struct tgsi_ind_register *ind,
781 unsigned addr_mul,
782 int rel_index)
783 {
784 LLVMValueRef result;
785
786 if (ind->File == TGSI_FILE_ADDRESS) {
787 result = ctx->addrs[ind->Index][ind->Swizzle];
788 result = LLVMBuildLoad(ctx->ac.builder, result, "");
789 } else {
790 struct tgsi_full_src_register src = {};
791
792 src.Register.File = ind->File;
793 src.Register.Index = ind->Index;
794
795 /* Set the second index to 0 for constants. */
796 if (ind->File == TGSI_FILE_CONSTANT)
797 src.Register.Dimension = 1;
798
799 result = ctx->bld_base.emit_fetch_funcs[ind->File](&ctx->bld_base, &src,
800 TGSI_TYPE_SIGNED,
801 ind->Swizzle);
802 result = ac_to_integer(&ctx->ac, result);
803 }
804
805 if (addr_mul != 1)
806 result = LLVMBuildMul(ctx->ac.builder, result,
807 LLVMConstInt(ctx->i32, addr_mul, 0), "");
808 result = LLVMBuildAdd(ctx->ac.builder, result,
809 LLVMConstInt(ctx->i32, rel_index, 0), "");
810 return result;
811 }
812
813 /**
814 * Like si_get_indirect_index, but restricts the return value to a (possibly
815 * undefined) value inside [0..num).
816 */
817 LLVMValueRef si_get_bounded_indirect_index(struct si_shader_context *ctx,
818 const struct tgsi_ind_register *ind,
819 int rel_index, unsigned num)
820 {
821 LLVMValueRef result = si_get_indirect_index(ctx, ind, 1, rel_index);
822
823 return si_llvm_bound_index(ctx, result, num);
824 }
825
826
827 /**
828 * Calculate a dword address given an input or output register and a stride.
829 */
830 static LLVMValueRef get_dw_address(struct si_shader_context *ctx,
831 const struct tgsi_full_dst_register *dst,
832 const struct tgsi_full_src_register *src,
833 LLVMValueRef vertex_dw_stride,
834 LLVMValueRef base_addr)
835 {
836 struct tgsi_shader_info *info = &ctx->shader->selector->info;
837 ubyte *name, *index, *array_first;
838 int first, param;
839 struct tgsi_full_dst_register reg;
840
841 /* Set the register description. The address computation is the same
842 * for sources and destinations. */
843 if (src) {
844 reg.Register.File = src->Register.File;
845 reg.Register.Index = src->Register.Index;
846 reg.Register.Indirect = src->Register.Indirect;
847 reg.Register.Dimension = src->Register.Dimension;
848 reg.Indirect = src->Indirect;
849 reg.Dimension = src->Dimension;
850 reg.DimIndirect = src->DimIndirect;
851 } else
852 reg = *dst;
853
854 /* If the register is 2-dimensional (e.g. an array of vertices
855 * in a primitive), calculate the base address of the vertex. */
856 if (reg.Register.Dimension) {
857 LLVMValueRef index;
858
859 if (reg.Dimension.Indirect)
860 index = si_get_indirect_index(ctx, &reg.DimIndirect,
861 1, reg.Dimension.Index);
862 else
863 index = LLVMConstInt(ctx->i32, reg.Dimension.Index, 0);
864
865 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
866 LLVMBuildMul(ctx->ac.builder, index,
867 vertex_dw_stride, ""), "");
868 }
869
870 /* Get information about the register. */
871 if (reg.Register.File == TGSI_FILE_INPUT) {
872 name = info->input_semantic_name;
873 index = info->input_semantic_index;
874 array_first = info->input_array_first;
875 } else if (reg.Register.File == TGSI_FILE_OUTPUT) {
876 name = info->output_semantic_name;
877 index = info->output_semantic_index;
878 array_first = info->output_array_first;
879 } else {
880 assert(0);
881 return NULL;
882 }
883
884 if (reg.Register.Indirect) {
885 /* Add the relative address of the element. */
886 LLVMValueRef ind_index;
887
888 if (reg.Indirect.ArrayID)
889 first = array_first[reg.Indirect.ArrayID];
890 else
891 first = reg.Register.Index;
892
893 ind_index = si_get_indirect_index(ctx, &reg.Indirect,
894 1, reg.Register.Index - first);
895
896 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
897 LLVMBuildMul(ctx->ac.builder, ind_index,
898 LLVMConstInt(ctx->i32, 4, 0), ""), "");
899
900 param = reg.Register.Dimension ?
901 si_shader_io_get_unique_index(name[first], index[first]) :
902 si_shader_io_get_unique_index_patch(name[first], index[first]);
903 } else {
904 param = reg.Register.Dimension ?
905 si_shader_io_get_unique_index(name[reg.Register.Index],
906 index[reg.Register.Index]) :
907 si_shader_io_get_unique_index_patch(name[reg.Register.Index],
908 index[reg.Register.Index]);
909 }
910
911 /* Add the base address of the element. */
912 return LLVMBuildAdd(ctx->ac.builder, base_addr,
913 LLVMConstInt(ctx->i32, param * 4, 0), "");
914 }
915
916 /* The offchip buffer layout for TCS->TES is
917 *
918 * - attribute 0 of patch 0 vertex 0
919 * - attribute 0 of patch 0 vertex 1
920 * - attribute 0 of patch 0 vertex 2
921 * ...
922 * - attribute 0 of patch 1 vertex 0
923 * - attribute 0 of patch 1 vertex 1
924 * ...
925 * - attribute 1 of patch 0 vertex 0
926 * - attribute 1 of patch 0 vertex 1
927 * ...
928 * - per patch attribute 0 of patch 0
929 * - per patch attribute 0 of patch 1
930 * ...
931 *
932 * Note that every attribute has 4 components.
933 */
934 static LLVMValueRef get_tcs_tes_buffer_address(struct si_shader_context *ctx,
935 LLVMValueRef rel_patch_id,
936 LLVMValueRef vertex_index,
937 LLVMValueRef param_index)
938 {
939 LLVMValueRef base_addr, vertices_per_patch, num_patches, total_vertices;
940 LLVMValueRef param_stride, constant16;
941
942 vertices_per_patch = get_num_tcs_out_vertices(ctx);
943 num_patches = unpack_param(ctx, ctx->param_tcs_offchip_layout, 0, 6);
944 total_vertices = LLVMBuildMul(ctx->ac.builder, vertices_per_patch,
945 num_patches, "");
946
947 constant16 = LLVMConstInt(ctx->i32, 16, 0);
948 if (vertex_index) {
949 base_addr = LLVMBuildMul(ctx->ac.builder, rel_patch_id,
950 vertices_per_patch, "");
951
952 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
953 vertex_index, "");
954
955 param_stride = total_vertices;
956 } else {
957 base_addr = rel_patch_id;
958 param_stride = num_patches;
959 }
960
961 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
962 LLVMBuildMul(ctx->ac.builder, param_index,
963 param_stride, ""), "");
964
965 base_addr = LLVMBuildMul(ctx->ac.builder, base_addr, constant16, "");
966
967 if (!vertex_index) {
968 LLVMValueRef patch_data_offset =
969 unpack_param(ctx, ctx->param_tcs_offchip_layout, 12, 20);
970
971 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
972 patch_data_offset, "");
973 }
974 return base_addr;
975 }
976
977 static LLVMValueRef get_tcs_tes_buffer_address_from_reg(
978 struct si_shader_context *ctx,
979 const struct tgsi_full_dst_register *dst,
980 const struct tgsi_full_src_register *src)
981 {
982 struct tgsi_shader_info *info = &ctx->shader->selector->info;
983 ubyte *name, *index, *array_first;
984 struct tgsi_full_src_register reg;
985 LLVMValueRef vertex_index = NULL;
986 LLVMValueRef param_index = NULL;
987 unsigned param_index_base, param_base;
988
989 reg = src ? *src : tgsi_full_src_register_from_dst(dst);
990
991 if (reg.Register.Dimension) {
992
993 if (reg.Dimension.Indirect)
994 vertex_index = si_get_indirect_index(ctx, &reg.DimIndirect,
995 1, reg.Dimension.Index);
996 else
997 vertex_index = LLVMConstInt(ctx->i32, reg.Dimension.Index, 0);
998 }
999
1000 /* Get information about the register. */
1001 if (reg.Register.File == TGSI_FILE_INPUT) {
1002 name = info->input_semantic_name;
1003 index = info->input_semantic_index;
1004 array_first = info->input_array_first;
1005 } else if (reg.Register.File == TGSI_FILE_OUTPUT) {
1006 name = info->output_semantic_name;
1007 index = info->output_semantic_index;
1008 array_first = info->output_array_first;
1009 } else {
1010 assert(0);
1011 return NULL;
1012 }
1013
1014 if (reg.Register.Indirect) {
1015 if (reg.Indirect.ArrayID)
1016 param_base = array_first[reg.Indirect.ArrayID];
1017 else
1018 param_base = reg.Register.Index;
1019
1020 param_index = si_get_indirect_index(ctx, &reg.Indirect,
1021 1, reg.Register.Index - param_base);
1022
1023 } else {
1024 param_base = reg.Register.Index;
1025 param_index = ctx->i32_0;
1026 }
1027
1028 param_index_base = reg.Register.Dimension ?
1029 si_shader_io_get_unique_index(name[param_base], index[param_base]) :
1030 si_shader_io_get_unique_index_patch(name[param_base], index[param_base]);
1031
1032 param_index = LLVMBuildAdd(ctx->ac.builder, param_index,
1033 LLVMConstInt(ctx->i32, param_index_base, 0),
1034 "");
1035
1036 return get_tcs_tes_buffer_address(ctx, get_rel_patch_id(ctx),
1037 vertex_index, param_index);
1038 }
1039
1040 static LLVMValueRef buffer_load(struct lp_build_tgsi_context *bld_base,
1041 enum tgsi_opcode_type type, unsigned swizzle,
1042 LLVMValueRef buffer, LLVMValueRef offset,
1043 LLVMValueRef base, bool can_speculate)
1044 {
1045 struct si_shader_context *ctx = si_shader_context(bld_base);
1046 LLVMValueRef value, value2;
1047 LLVMTypeRef llvm_type = tgsi2llvmtype(bld_base, type);
1048 LLVMTypeRef vec_type = LLVMVectorType(llvm_type, 4);
1049
1050 if (swizzle == ~0) {
1051 value = ac_build_buffer_load(&ctx->ac, buffer, 4, NULL, base, offset,
1052 0, 1, 0, can_speculate, false);
1053
1054 return LLVMBuildBitCast(ctx->ac.builder, value, vec_type, "");
1055 }
1056
1057 if (!tgsi_type_is_64bit(type)) {
1058 value = ac_build_buffer_load(&ctx->ac, buffer, 4, NULL, base, offset,
1059 0, 1, 0, can_speculate, false);
1060
1061 value = LLVMBuildBitCast(ctx->ac.builder, value, vec_type, "");
1062 return LLVMBuildExtractElement(ctx->ac.builder, value,
1063 LLVMConstInt(ctx->i32, swizzle, 0), "");
1064 }
1065
1066 value = ac_build_buffer_load(&ctx->ac, buffer, 1, NULL, base, offset,
1067 swizzle * 4, 1, 0, can_speculate, false);
1068
1069 value2 = ac_build_buffer_load(&ctx->ac, buffer, 1, NULL, base, offset,
1070 swizzle * 4 + 4, 1, 0, can_speculate, false);
1071
1072 return si_llvm_emit_fetch_64bit(bld_base, type, value, value2);
1073 }
1074
1075 /**
1076 * Load from LDS.
1077 *
1078 * \param type output value type
1079 * \param swizzle offset (typically 0..3); it can be ~0, which loads a vec4
1080 * \param dw_addr address in dwords
1081 */
1082 static LLVMValueRef lds_load(struct lp_build_tgsi_context *bld_base,
1083 enum tgsi_opcode_type type, unsigned swizzle,
1084 LLVMValueRef dw_addr)
1085 {
1086 struct si_shader_context *ctx = si_shader_context(bld_base);
1087 LLVMValueRef value;
1088
1089 if (swizzle == ~0) {
1090 LLVMValueRef values[TGSI_NUM_CHANNELS];
1091
1092 for (unsigned chan = 0; chan < TGSI_NUM_CHANNELS; chan++)
1093 values[chan] = lds_load(bld_base, type, chan, dw_addr);
1094
1095 return lp_build_gather_values(&ctx->gallivm, values,
1096 TGSI_NUM_CHANNELS);
1097 }
1098
1099 dw_addr = lp_build_add(&bld_base->uint_bld, dw_addr,
1100 LLVMConstInt(ctx->i32, swizzle, 0));
1101
1102 value = ac_build_load(&ctx->ac, ctx->lds, dw_addr);
1103 if (tgsi_type_is_64bit(type)) {
1104 LLVMValueRef value2;
1105 dw_addr = lp_build_add(&bld_base->uint_bld, dw_addr,
1106 ctx->i32_1);
1107 value2 = ac_build_load(&ctx->ac, ctx->lds, dw_addr);
1108 return si_llvm_emit_fetch_64bit(bld_base, type, value, value2);
1109 }
1110
1111 return bitcast(bld_base, type, value);
1112 }
1113
1114 /**
1115 * Store to LDS.
1116 *
1117 * \param swizzle offset (typically 0..3)
1118 * \param dw_addr address in dwords
1119 * \param value value to store
1120 */
1121 static void lds_store(struct lp_build_tgsi_context *bld_base,
1122 unsigned dw_offset_imm, LLVMValueRef dw_addr,
1123 LLVMValueRef value)
1124 {
1125 struct si_shader_context *ctx = si_shader_context(bld_base);
1126
1127 dw_addr = lp_build_add(&bld_base->uint_bld, dw_addr,
1128 LLVMConstInt(ctx->i32, dw_offset_imm, 0));
1129
1130 value = ac_to_integer(&ctx->ac, value);
1131 ac_build_indexed_store(&ctx->ac, ctx->lds,
1132 dw_addr, value);
1133 }
1134
1135 static LLVMValueRef desc_from_addr_base64k(struct si_shader_context *ctx,
1136 unsigned param)
1137 {
1138 LLVMBuilderRef builder = ctx->ac.builder;
1139
1140 LLVMValueRef addr = LLVMGetParam(ctx->main_fn, param);
1141 addr = LLVMBuildZExt(builder, addr, ctx->i64, "");
1142 addr = LLVMBuildShl(builder, addr, LLVMConstInt(ctx->i64, 16, 0), "");
1143
1144 uint64_t desc2 = 0xffffffff;
1145 uint64_t desc3 = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1146 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1147 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1148 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1149 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1150 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
1151 LLVMValueRef hi = LLVMConstInt(ctx->i64, desc2 | (desc3 << 32), 0);
1152
1153 LLVMValueRef desc = LLVMGetUndef(LLVMVectorType(ctx->i64, 2));
1154 desc = LLVMBuildInsertElement(builder, desc, addr, ctx->i32_0, "");
1155 desc = LLVMBuildInsertElement(builder, desc, hi, ctx->i32_1, "");
1156 return LLVMBuildBitCast(builder, desc, ctx->v4i32, "");
1157 }
1158
1159 static LLVMValueRef fetch_input_tcs(
1160 struct lp_build_tgsi_context *bld_base,
1161 const struct tgsi_full_src_register *reg,
1162 enum tgsi_opcode_type type, unsigned swizzle)
1163 {
1164 struct si_shader_context *ctx = si_shader_context(bld_base);
1165 LLVMValueRef dw_addr, stride;
1166
1167 stride = get_tcs_in_vertex_dw_stride(ctx);
1168 dw_addr = get_tcs_in_current_patch_offset(ctx);
1169 dw_addr = get_dw_address(ctx, NULL, reg, stride, dw_addr);
1170
1171 return lds_load(bld_base, type, swizzle, dw_addr);
1172 }
1173
1174 static LLVMValueRef fetch_output_tcs(
1175 struct lp_build_tgsi_context *bld_base,
1176 const struct tgsi_full_src_register *reg,
1177 enum tgsi_opcode_type type, unsigned swizzle)
1178 {
1179 struct si_shader_context *ctx = si_shader_context(bld_base);
1180 LLVMValueRef dw_addr, stride;
1181
1182 if (reg->Register.Dimension) {
1183 stride = get_tcs_out_vertex_dw_stride(ctx);
1184 dw_addr = get_tcs_out_current_patch_offset(ctx);
1185 dw_addr = get_dw_address(ctx, NULL, reg, stride, dw_addr);
1186 } else {
1187 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1188 dw_addr = get_dw_address(ctx, NULL, reg, NULL, dw_addr);
1189 }
1190
1191 return lds_load(bld_base, type, swizzle, dw_addr);
1192 }
1193
1194 static LLVMValueRef fetch_input_tes(
1195 struct lp_build_tgsi_context *bld_base,
1196 const struct tgsi_full_src_register *reg,
1197 enum tgsi_opcode_type type, unsigned swizzle)
1198 {
1199 struct si_shader_context *ctx = si_shader_context(bld_base);
1200 LLVMValueRef buffer, base, addr;
1201
1202 buffer = desc_from_addr_base64k(ctx, ctx->param_tcs_offchip_addr_base64k);
1203
1204 base = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
1205 addr = get_tcs_tes_buffer_address_from_reg(ctx, NULL, reg);
1206
1207 return buffer_load(bld_base, type, swizzle, buffer, base, addr, true);
1208 }
1209
1210 static void store_output_tcs(struct lp_build_tgsi_context *bld_base,
1211 const struct tgsi_full_instruction *inst,
1212 const struct tgsi_opcode_info *info,
1213 unsigned index,
1214 LLVMValueRef dst[4])
1215 {
1216 struct si_shader_context *ctx = si_shader_context(bld_base);
1217 const struct tgsi_full_dst_register *reg = &inst->Dst[index];
1218 const struct tgsi_shader_info *sh_info = &ctx->shader->selector->info;
1219 unsigned chan_index;
1220 LLVMValueRef dw_addr, stride;
1221 LLVMValueRef buffer, base, buf_addr;
1222 LLVMValueRef values[4];
1223 bool skip_lds_store;
1224 bool is_tess_factor = false, is_tess_inner = false;
1225
1226 /* Only handle per-patch and per-vertex outputs here.
1227 * Vectors will be lowered to scalars and this function will be called again.
1228 */
1229 if (reg->Register.File != TGSI_FILE_OUTPUT ||
1230 (dst[0] && LLVMGetTypeKind(LLVMTypeOf(dst[0])) == LLVMVectorTypeKind)) {
1231 si_llvm_emit_store(bld_base, inst, info, index, dst);
1232 return;
1233 }
1234
1235 if (reg->Register.Dimension) {
1236 stride = get_tcs_out_vertex_dw_stride(ctx);
1237 dw_addr = get_tcs_out_current_patch_offset(ctx);
1238 dw_addr = get_dw_address(ctx, reg, NULL, stride, dw_addr);
1239 skip_lds_store = !sh_info->reads_pervertex_outputs;
1240 } else {
1241 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1242 dw_addr = get_dw_address(ctx, reg, NULL, NULL, dw_addr);
1243 skip_lds_store = !sh_info->reads_perpatch_outputs;
1244
1245 if (!reg->Register.Indirect) {
1246 int name = sh_info->output_semantic_name[reg->Register.Index];
1247
1248 /* Always write tess factors into LDS for the TCS epilog. */
1249 if (name == TGSI_SEMANTIC_TESSINNER ||
1250 name == TGSI_SEMANTIC_TESSOUTER) {
1251 /* The epilog doesn't read LDS if invocation 0 defines tess factors. */
1252 skip_lds_store = !sh_info->reads_tessfactor_outputs &&
1253 ctx->shader->selector->tcs_info.tessfactors_are_def_in_all_invocs;
1254 is_tess_factor = true;
1255 is_tess_inner = name == TGSI_SEMANTIC_TESSINNER;
1256 }
1257 }
1258 }
1259
1260 buffer = desc_from_addr_base64k(ctx, ctx->param_tcs_offchip_addr_base64k);
1261
1262 base = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
1263 buf_addr = get_tcs_tes_buffer_address_from_reg(ctx, reg, NULL);
1264
1265 uint32_t writemask = reg->Register.WriteMask;
1266 while (writemask) {
1267 chan_index = u_bit_scan(&writemask);
1268 LLVMValueRef value = dst[chan_index];
1269
1270 if (inst->Instruction.Saturate)
1271 value = ac_build_clamp(&ctx->ac, value);
1272
1273 /* Skip LDS stores if there is no LDS read of this output. */
1274 if (!skip_lds_store)
1275 lds_store(bld_base, chan_index, dw_addr, value);
1276
1277 value = ac_to_integer(&ctx->ac, value);
1278 values[chan_index] = value;
1279
1280 if (reg->Register.WriteMask != 0xF && !is_tess_factor) {
1281 ac_build_buffer_store_dword(&ctx->ac, buffer, value, 1,
1282 buf_addr, base,
1283 4 * chan_index, 1, 0, true, false);
1284 }
1285
1286 /* Write tess factors into VGPRs for the epilog. */
1287 if (is_tess_factor &&
1288 ctx->shader->selector->tcs_info.tessfactors_are_def_in_all_invocs) {
1289 if (!is_tess_inner) {
1290 LLVMBuildStore(ctx->ac.builder, value, /* outer */
1291 ctx->invoc0_tess_factors[chan_index]);
1292 } else if (chan_index < 2) {
1293 LLVMBuildStore(ctx->ac.builder, value, /* inner */
1294 ctx->invoc0_tess_factors[4 + chan_index]);
1295 }
1296 }
1297 }
1298
1299 if (reg->Register.WriteMask == 0xF && !is_tess_factor) {
1300 LLVMValueRef value = lp_build_gather_values(&ctx->gallivm,
1301 values, 4);
1302 ac_build_buffer_store_dword(&ctx->ac, buffer, value, 4, buf_addr,
1303 base, 0, 1, 0, true, false);
1304 }
1305 }
1306
1307 static LLVMValueRef fetch_input_gs(
1308 struct lp_build_tgsi_context *bld_base,
1309 const struct tgsi_full_src_register *reg,
1310 enum tgsi_opcode_type type,
1311 unsigned swizzle)
1312 {
1313 struct si_shader_context *ctx = si_shader_context(bld_base);
1314 struct si_shader *shader = ctx->shader;
1315 struct lp_build_context *uint = &ctx->bld_base.uint_bld;
1316 LLVMValueRef vtx_offset, soffset;
1317 struct tgsi_shader_info *info = &shader->selector->info;
1318 unsigned semantic_name = info->input_semantic_name[reg->Register.Index];
1319 unsigned semantic_index = info->input_semantic_index[reg->Register.Index];
1320 unsigned param;
1321 LLVMValueRef value;
1322
1323 if (swizzle != ~0 && semantic_name == TGSI_SEMANTIC_PRIMID)
1324 return get_primitive_id(ctx, swizzle);
1325
1326 if (!reg->Register.Dimension)
1327 return NULL;
1328
1329 param = si_shader_io_get_unique_index(semantic_name, semantic_index);
1330
1331 /* GFX9 has the ESGS ring in LDS. */
1332 if (ctx->screen->b.chip_class >= GFX9) {
1333 unsigned index = reg->Dimension.Index;
1334
1335 switch (index / 2) {
1336 case 0:
1337 vtx_offset = unpack_param(ctx, ctx->param_gs_vtx01_offset,
1338 index % 2 ? 16 : 0, 16);
1339 break;
1340 case 1:
1341 vtx_offset = unpack_param(ctx, ctx->param_gs_vtx23_offset,
1342 index % 2 ? 16 : 0, 16);
1343 break;
1344 case 2:
1345 vtx_offset = unpack_param(ctx, ctx->param_gs_vtx45_offset,
1346 index % 2 ? 16 : 0, 16);
1347 break;
1348 default:
1349 assert(0);
1350 return NULL;
1351 }
1352
1353 vtx_offset = LLVMBuildAdd(ctx->ac.builder, vtx_offset,
1354 LLVMConstInt(ctx->i32, param * 4, 0), "");
1355 return lds_load(bld_base, type, swizzle, vtx_offset);
1356 }
1357
1358 /* GFX6: input load from the ESGS ring in memory. */
1359 if (swizzle == ~0) {
1360 LLVMValueRef values[TGSI_NUM_CHANNELS];
1361 unsigned chan;
1362 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1363 values[chan] = fetch_input_gs(bld_base, reg, type, chan);
1364 }
1365 return lp_build_gather_values(&ctx->gallivm, values,
1366 TGSI_NUM_CHANNELS);
1367 }
1368
1369 /* Get the vertex offset parameter on GFX6. */
1370 unsigned vtx_offset_param = reg->Dimension.Index;
1371 if (vtx_offset_param < 2) {
1372 vtx_offset_param += ctx->param_gs_vtx0_offset;
1373 } else {
1374 assert(vtx_offset_param < 6);
1375 vtx_offset_param += ctx->param_gs_vtx2_offset - 2;
1376 }
1377 vtx_offset = lp_build_mul_imm(uint,
1378 LLVMGetParam(ctx->main_fn,
1379 vtx_offset_param),
1380 4);
1381
1382 soffset = LLVMConstInt(ctx->i32, (param * 4 + swizzle) * 256, 0);
1383
1384 value = ac_build_buffer_load(&ctx->ac, ctx->esgs_ring, 1, ctx->i32_0,
1385 vtx_offset, soffset, 0, 1, 0, true, false);
1386 if (tgsi_type_is_64bit(type)) {
1387 LLVMValueRef value2;
1388 soffset = LLVMConstInt(ctx->i32, (param * 4 + swizzle + 1) * 256, 0);
1389
1390 value2 = ac_build_buffer_load(&ctx->ac, ctx->esgs_ring, 1,
1391 ctx->i32_0, vtx_offset, soffset,
1392 0, 1, 0, true, false);
1393 return si_llvm_emit_fetch_64bit(bld_base, type,
1394 value, value2);
1395 }
1396 return bitcast(bld_base, type, value);
1397 }
1398
1399 static int lookup_interp_param_index(unsigned interpolate, unsigned location)
1400 {
1401 switch (interpolate) {
1402 case TGSI_INTERPOLATE_CONSTANT:
1403 return 0;
1404
1405 case TGSI_INTERPOLATE_LINEAR:
1406 if (location == TGSI_INTERPOLATE_LOC_SAMPLE)
1407 return SI_PARAM_LINEAR_SAMPLE;
1408 else if (location == TGSI_INTERPOLATE_LOC_CENTROID)
1409 return SI_PARAM_LINEAR_CENTROID;
1410 else
1411 return SI_PARAM_LINEAR_CENTER;
1412 break;
1413 case TGSI_INTERPOLATE_COLOR:
1414 case TGSI_INTERPOLATE_PERSPECTIVE:
1415 if (location == TGSI_INTERPOLATE_LOC_SAMPLE)
1416 return SI_PARAM_PERSP_SAMPLE;
1417 else if (location == TGSI_INTERPOLATE_LOC_CENTROID)
1418 return SI_PARAM_PERSP_CENTROID;
1419 else
1420 return SI_PARAM_PERSP_CENTER;
1421 break;
1422 default:
1423 fprintf(stderr, "Warning: Unhandled interpolation mode.\n");
1424 return -1;
1425 }
1426 }
1427
1428 static LLVMValueRef si_build_fs_interp(struct si_shader_context *ctx,
1429 unsigned attr_index, unsigned chan,
1430 LLVMValueRef prim_mask,
1431 LLVMValueRef i, LLVMValueRef j)
1432 {
1433 if (i || j) {
1434 return ac_build_fs_interp(&ctx->ac,
1435 LLVMConstInt(ctx->i32, chan, 0),
1436 LLVMConstInt(ctx->i32, attr_index, 0),
1437 prim_mask, i, j);
1438 }
1439 return ac_build_fs_interp_mov(&ctx->ac,
1440 LLVMConstInt(ctx->i32, 2, 0), /* P0 */
1441 LLVMConstInt(ctx->i32, chan, 0),
1442 LLVMConstInt(ctx->i32, attr_index, 0),
1443 prim_mask);
1444 }
1445
1446 /**
1447 * Interpolate a fragment shader input.
1448 *
1449 * @param ctx context
1450 * @param input_index index of the input in hardware
1451 * @param semantic_name TGSI_SEMANTIC_*
1452 * @param semantic_index semantic index
1453 * @param num_interp_inputs number of all interpolated inputs (= BCOLOR offset)
1454 * @param colors_read_mask color components read (4 bits for each color, 8 bits in total)
1455 * @param interp_param interpolation weights (i,j)
1456 * @param prim_mask SI_PARAM_PRIM_MASK
1457 * @param face SI_PARAM_FRONT_FACE
1458 * @param result the return value (4 components)
1459 */
1460 static void interp_fs_input(struct si_shader_context *ctx,
1461 unsigned input_index,
1462 unsigned semantic_name,
1463 unsigned semantic_index,
1464 unsigned num_interp_inputs,
1465 unsigned colors_read_mask,
1466 LLVMValueRef interp_param,
1467 LLVMValueRef prim_mask,
1468 LLVMValueRef face,
1469 LLVMValueRef result[4])
1470 {
1471 LLVMValueRef i = NULL, j = NULL;
1472 unsigned chan;
1473
1474 /* fs.constant returns the param from the middle vertex, so it's not
1475 * really useful for flat shading. It's meant to be used for custom
1476 * interpolation (but the intrinsic can't fetch from the other two
1477 * vertices).
1478 *
1479 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
1480 * to do the right thing. The only reason we use fs.constant is that
1481 * fs.interp cannot be used on integers, because they can be equal
1482 * to NaN.
1483 *
1484 * When interp is false we will use fs.constant or for newer llvm,
1485 * amdgcn.interp.mov.
1486 */
1487 bool interp = interp_param != NULL;
1488
1489 if (interp) {
1490 interp_param = LLVMBuildBitCast(ctx->ac.builder, interp_param,
1491 LLVMVectorType(ctx->f32, 2), "");
1492
1493 i = LLVMBuildExtractElement(ctx->ac.builder, interp_param,
1494 ctx->i32_0, "");
1495 j = LLVMBuildExtractElement(ctx->ac.builder, interp_param,
1496 ctx->i32_1, "");
1497 }
1498
1499 if (semantic_name == TGSI_SEMANTIC_COLOR &&
1500 ctx->shader->key.part.ps.prolog.color_two_side) {
1501 LLVMValueRef is_face_positive;
1502
1503 /* If BCOLOR0 is used, BCOLOR1 is at offset "num_inputs + 1",
1504 * otherwise it's at offset "num_inputs".
1505 */
1506 unsigned back_attr_offset = num_interp_inputs;
1507 if (semantic_index == 1 && colors_read_mask & 0xf)
1508 back_attr_offset += 1;
1509
1510 is_face_positive = LLVMBuildICmp(ctx->ac.builder, LLVMIntNE,
1511 face, ctx->i32_0, "");
1512
1513 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1514 LLVMValueRef front, back;
1515
1516 front = si_build_fs_interp(ctx,
1517 input_index, chan,
1518 prim_mask, i, j);
1519 back = si_build_fs_interp(ctx,
1520 back_attr_offset, chan,
1521 prim_mask, i, j);
1522
1523 result[chan] = LLVMBuildSelect(ctx->ac.builder,
1524 is_face_positive,
1525 front,
1526 back,
1527 "");
1528 }
1529 } else if (semantic_name == TGSI_SEMANTIC_FOG) {
1530 result[0] = si_build_fs_interp(ctx, input_index,
1531 0, prim_mask, i, j);
1532 result[1] =
1533 result[2] = LLVMConstReal(ctx->f32, 0.0f);
1534 result[3] = LLVMConstReal(ctx->f32, 1.0f);
1535 } else {
1536 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1537 result[chan] = si_build_fs_interp(ctx,
1538 input_index, chan,
1539 prim_mask, i, j);
1540 }
1541 }
1542 }
1543
1544 void si_llvm_load_input_fs(
1545 struct si_shader_context *ctx,
1546 unsigned input_index,
1547 LLVMValueRef out[4])
1548 {
1549 struct lp_build_context *base = &ctx->bld_base.base;
1550 struct si_shader *shader = ctx->shader;
1551 struct tgsi_shader_info *info = &shader->selector->info;
1552 LLVMValueRef main_fn = ctx->main_fn;
1553 LLVMValueRef interp_param = NULL;
1554 int interp_param_idx;
1555 enum tgsi_semantic semantic_name = info->input_semantic_name[input_index];
1556 unsigned semantic_index = info->input_semantic_index[input_index];
1557 enum tgsi_interpolate_mode interp_mode = info->input_interpolate[input_index];
1558 enum tgsi_interpolate_loc interp_loc = info->input_interpolate_loc[input_index];
1559
1560 /* Get colors from input VGPRs (set by the prolog). */
1561 if (semantic_name == TGSI_SEMANTIC_COLOR) {
1562 unsigned colors_read = shader->selector->info.colors_read;
1563 unsigned mask = colors_read >> (semantic_index * 4);
1564 unsigned offset = SI_PARAM_POS_FIXED_PT + 1 +
1565 (semantic_index ? util_bitcount(colors_read & 0xf) : 0);
1566
1567 out[0] = mask & 0x1 ? LLVMGetParam(main_fn, offset++) : base->undef;
1568 out[1] = mask & 0x2 ? LLVMGetParam(main_fn, offset++) : base->undef;
1569 out[2] = mask & 0x4 ? LLVMGetParam(main_fn, offset++) : base->undef;
1570 out[3] = mask & 0x8 ? LLVMGetParam(main_fn, offset++) : base->undef;
1571 return;
1572 }
1573
1574 interp_param_idx = lookup_interp_param_index(interp_mode, interp_loc);
1575 if (interp_param_idx == -1)
1576 return;
1577 else if (interp_param_idx) {
1578 interp_param = LLVMGetParam(ctx->main_fn, interp_param_idx);
1579 }
1580
1581 interp_fs_input(ctx, input_index, semantic_name,
1582 semantic_index, 0, /* this param is unused */
1583 shader->selector->info.colors_read, interp_param,
1584 LLVMGetParam(main_fn, SI_PARAM_PRIM_MASK),
1585 LLVMGetParam(main_fn, SI_PARAM_FRONT_FACE),
1586 &out[0]);
1587 }
1588
1589 static void declare_input_fs(
1590 struct si_shader_context *ctx,
1591 unsigned input_index,
1592 const struct tgsi_full_declaration *decl,
1593 LLVMValueRef out[4])
1594 {
1595 si_llvm_load_input_fs(ctx, input_index, out);
1596 }
1597
1598 static LLVMValueRef get_sample_id(struct si_shader_context *ctx)
1599 {
1600 return unpack_param(ctx, SI_PARAM_ANCILLARY, 8, 4);
1601 }
1602
1603
1604 /**
1605 * Load a dword from a constant buffer.
1606 */
1607 static LLVMValueRef buffer_load_const(struct si_shader_context *ctx,
1608 LLVMValueRef resource,
1609 LLVMValueRef offset)
1610 {
1611 return ac_build_buffer_load(&ctx->ac, resource, 1, NULL, offset, NULL,
1612 0, 0, 0, true, true);
1613 }
1614
1615 static LLVMValueRef load_sample_position(struct si_shader_context *ctx, LLVMValueRef sample_id)
1616 {
1617 struct lp_build_context *uint_bld = &ctx->bld_base.uint_bld;
1618 LLVMValueRef desc = LLVMGetParam(ctx->main_fn, ctx->param_rw_buffers);
1619 LLVMValueRef buf_index = LLVMConstInt(ctx->i32, SI_PS_CONST_SAMPLE_POSITIONS, 0);
1620 LLVMValueRef resource = ac_build_load_to_sgpr(&ctx->ac, desc, buf_index);
1621
1622 /* offset = sample_id * 8 (8 = 2 floats containing samplepos.xy) */
1623 LLVMValueRef offset0 = lp_build_mul_imm(uint_bld, sample_id, 8);
1624 LLVMValueRef offset1 = LLVMBuildAdd(ctx->ac.builder, offset0, LLVMConstInt(ctx->i32, 4, 0), "");
1625
1626 LLVMValueRef pos[4] = {
1627 buffer_load_const(ctx, resource, offset0),
1628 buffer_load_const(ctx, resource, offset1),
1629 LLVMConstReal(ctx->f32, 0),
1630 LLVMConstReal(ctx->f32, 0)
1631 };
1632
1633 return lp_build_gather_values(&ctx->gallivm, pos, 4);
1634 }
1635
1636 void si_load_system_value(struct si_shader_context *ctx,
1637 unsigned index,
1638 const struct tgsi_full_declaration *decl)
1639 {
1640 struct lp_build_context *bld = &ctx->bld_base.base;
1641 LLVMValueRef value = 0;
1642
1643 assert(index < RADEON_LLVM_MAX_SYSTEM_VALUES);
1644
1645 switch (decl->Semantic.Name) {
1646 case TGSI_SEMANTIC_INSTANCEID:
1647 value = ctx->abi.instance_id;
1648 break;
1649
1650 case TGSI_SEMANTIC_VERTEXID:
1651 value = LLVMBuildAdd(ctx->ac.builder,
1652 ctx->abi.vertex_id,
1653 ctx->abi.base_vertex, "");
1654 break;
1655
1656 case TGSI_SEMANTIC_VERTEXID_NOBASE:
1657 /* Unused. Clarify the meaning in indexed vs. non-indexed
1658 * draws if this is ever used again. */
1659 assert(false);
1660 break;
1661
1662 case TGSI_SEMANTIC_BASEVERTEX:
1663 {
1664 /* For non-indexed draws, the base vertex set by the driver
1665 * (for direct draws) or the CP (for indirect draws) is the
1666 * first vertex ID, but GLSL expects 0 to be returned.
1667 */
1668 LLVMValueRef vs_state = LLVMGetParam(ctx->main_fn, ctx->param_vs_state_bits);
1669 LLVMValueRef indexed;
1670
1671 indexed = LLVMBuildLShr(ctx->ac.builder, vs_state, ctx->i32_1, "");
1672 indexed = LLVMBuildTrunc(ctx->ac.builder, indexed, ctx->i1, "");
1673
1674 value = LLVMBuildSelect(ctx->ac.builder, indexed,
1675 ctx->abi.base_vertex, ctx->i32_0, "");
1676 break;
1677 }
1678
1679 case TGSI_SEMANTIC_BASEINSTANCE:
1680 value = ctx->abi.start_instance;
1681 break;
1682
1683 case TGSI_SEMANTIC_DRAWID:
1684 value = ctx->abi.draw_id;
1685 break;
1686
1687 case TGSI_SEMANTIC_INVOCATIONID:
1688 if (ctx->type == PIPE_SHADER_TESS_CTRL)
1689 value = unpack_param(ctx, ctx->param_tcs_rel_ids, 8, 5);
1690 else if (ctx->type == PIPE_SHADER_GEOMETRY)
1691 value = LLVMGetParam(ctx->main_fn,
1692 ctx->param_gs_instance_id);
1693 else
1694 assert(!"INVOCATIONID not implemented");
1695 break;
1696
1697 case TGSI_SEMANTIC_POSITION:
1698 {
1699 LLVMValueRef pos[4] = {
1700 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_X_FLOAT),
1701 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_Y_FLOAT),
1702 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_Z_FLOAT),
1703 lp_build_emit_llvm_unary(&ctx->bld_base, TGSI_OPCODE_RCP,
1704 LLVMGetParam(ctx->main_fn,
1705 SI_PARAM_POS_W_FLOAT)),
1706 };
1707 value = lp_build_gather_values(&ctx->gallivm, pos, 4);
1708 break;
1709 }
1710
1711 case TGSI_SEMANTIC_FACE:
1712 value = ctx->abi.front_face;
1713 break;
1714
1715 case TGSI_SEMANTIC_SAMPLEID:
1716 value = get_sample_id(ctx);
1717 break;
1718
1719 case TGSI_SEMANTIC_SAMPLEPOS: {
1720 LLVMValueRef pos[4] = {
1721 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_X_FLOAT),
1722 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_Y_FLOAT),
1723 LLVMConstReal(ctx->f32, 0),
1724 LLVMConstReal(ctx->f32, 0)
1725 };
1726 pos[0] = lp_build_emit_llvm_unary(&ctx->bld_base,
1727 TGSI_OPCODE_FRC, pos[0]);
1728 pos[1] = lp_build_emit_llvm_unary(&ctx->bld_base,
1729 TGSI_OPCODE_FRC, pos[1]);
1730 value = lp_build_gather_values(&ctx->gallivm, pos, 4);
1731 break;
1732 }
1733
1734 case TGSI_SEMANTIC_SAMPLEMASK:
1735 /* This can only occur with the OpenGL Core profile, which
1736 * doesn't support smoothing.
1737 */
1738 value = LLVMGetParam(ctx->main_fn, SI_PARAM_SAMPLE_COVERAGE);
1739 break;
1740
1741 case TGSI_SEMANTIC_TESSCOORD:
1742 {
1743 LLVMValueRef coord[4] = {
1744 LLVMGetParam(ctx->main_fn, ctx->param_tes_u),
1745 LLVMGetParam(ctx->main_fn, ctx->param_tes_v),
1746 ctx->ac.f32_0,
1747 ctx->ac.f32_0
1748 };
1749
1750 /* For triangles, the vector should be (u, v, 1-u-v). */
1751 if (ctx->shader->selector->info.properties[TGSI_PROPERTY_TES_PRIM_MODE] ==
1752 PIPE_PRIM_TRIANGLES)
1753 coord[2] = lp_build_sub(bld, ctx->ac.f32_1,
1754 lp_build_add(bld, coord[0], coord[1]));
1755
1756 value = lp_build_gather_values(&ctx->gallivm, coord, 4);
1757 break;
1758 }
1759
1760 case TGSI_SEMANTIC_VERTICESIN:
1761 if (ctx->type == PIPE_SHADER_TESS_CTRL)
1762 value = unpack_param(ctx, ctx->param_tcs_out_lds_layout, 26, 6);
1763 else if (ctx->type == PIPE_SHADER_TESS_EVAL)
1764 value = get_num_tcs_out_vertices(ctx);
1765 else
1766 assert(!"invalid shader stage for TGSI_SEMANTIC_VERTICESIN");
1767 break;
1768
1769 case TGSI_SEMANTIC_TESSINNER:
1770 case TGSI_SEMANTIC_TESSOUTER:
1771 {
1772 LLVMValueRef buffer, base, addr;
1773 int param = si_shader_io_get_unique_index_patch(decl->Semantic.Name, 0);
1774
1775 buffer = desc_from_addr_base64k(ctx, ctx->param_tcs_offchip_addr_base64k);
1776
1777 base = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
1778 addr = get_tcs_tes_buffer_address(ctx, get_rel_patch_id(ctx), NULL,
1779 LLVMConstInt(ctx->i32, param, 0));
1780
1781 value = buffer_load(&ctx->bld_base, TGSI_TYPE_FLOAT,
1782 ~0, buffer, base, addr, true);
1783
1784 break;
1785 }
1786
1787 case TGSI_SEMANTIC_DEFAULT_TESSOUTER_SI:
1788 case TGSI_SEMANTIC_DEFAULT_TESSINNER_SI:
1789 {
1790 LLVMValueRef buf, slot, val[4];
1791 int i, offset;
1792
1793 slot = LLVMConstInt(ctx->i32, SI_HS_CONST_DEFAULT_TESS_LEVELS, 0);
1794 buf = LLVMGetParam(ctx->main_fn, ctx->param_rw_buffers);
1795 buf = ac_build_load_to_sgpr(&ctx->ac, buf, slot);
1796 offset = decl->Semantic.Name == TGSI_SEMANTIC_DEFAULT_TESSINNER_SI ? 4 : 0;
1797
1798 for (i = 0; i < 4; i++)
1799 val[i] = buffer_load_const(ctx, buf,
1800 LLVMConstInt(ctx->i32, (offset + i) * 4, 0));
1801 value = lp_build_gather_values(&ctx->gallivm, val, 4);
1802 break;
1803 }
1804
1805 case TGSI_SEMANTIC_PRIMID:
1806 value = get_primitive_id(ctx, 0);
1807 break;
1808
1809 case TGSI_SEMANTIC_GRID_SIZE:
1810 value = LLVMGetParam(ctx->main_fn, ctx->param_grid_size);
1811 break;
1812
1813 case TGSI_SEMANTIC_BLOCK_SIZE:
1814 {
1815 LLVMValueRef values[3];
1816 unsigned i;
1817 unsigned *properties = ctx->shader->selector->info.properties;
1818
1819 if (properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] != 0) {
1820 unsigned sizes[3] = {
1821 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH],
1822 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT],
1823 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH]
1824 };
1825
1826 for (i = 0; i < 3; ++i)
1827 values[i] = LLVMConstInt(ctx->i32, sizes[i], 0);
1828
1829 value = lp_build_gather_values(&ctx->gallivm, values, 3);
1830 } else {
1831 value = LLVMGetParam(ctx->main_fn, ctx->param_block_size);
1832 }
1833 break;
1834 }
1835
1836 case TGSI_SEMANTIC_BLOCK_ID:
1837 {
1838 LLVMValueRef values[3];
1839
1840 for (int i = 0; i < 3; i++) {
1841 values[i] = ctx->i32_0;
1842 if (ctx->param_block_id[i] >= 0) {
1843 values[i] = LLVMGetParam(ctx->main_fn,
1844 ctx->param_block_id[i]);
1845 }
1846 }
1847 value = lp_build_gather_values(&ctx->gallivm, values, 3);
1848 break;
1849 }
1850
1851 case TGSI_SEMANTIC_THREAD_ID:
1852 value = LLVMGetParam(ctx->main_fn, ctx->param_thread_id);
1853 break;
1854
1855 case TGSI_SEMANTIC_HELPER_INVOCATION:
1856 value = lp_build_intrinsic(ctx->ac.builder,
1857 "llvm.amdgcn.ps.live",
1858 ctx->i1, NULL, 0,
1859 LP_FUNC_ATTR_READNONE);
1860 value = LLVMBuildNot(ctx->ac.builder, value, "");
1861 value = LLVMBuildSExt(ctx->ac.builder, value, ctx->i32, "");
1862 break;
1863
1864 case TGSI_SEMANTIC_SUBGROUP_SIZE:
1865 value = LLVMConstInt(ctx->i32, 64, 0);
1866 break;
1867
1868 case TGSI_SEMANTIC_SUBGROUP_INVOCATION:
1869 value = ac_get_thread_id(&ctx->ac);
1870 break;
1871
1872 case TGSI_SEMANTIC_SUBGROUP_EQ_MASK:
1873 {
1874 LLVMValueRef id = ac_get_thread_id(&ctx->ac);
1875 id = LLVMBuildZExt(ctx->ac.builder, id, ctx->i64, "");
1876 value = LLVMBuildShl(ctx->ac.builder, LLVMConstInt(ctx->i64, 1, 0), id, "");
1877 value = LLVMBuildBitCast(ctx->ac.builder, value, ctx->v2i32, "");
1878 break;
1879 }
1880
1881 case TGSI_SEMANTIC_SUBGROUP_GE_MASK:
1882 case TGSI_SEMANTIC_SUBGROUP_GT_MASK:
1883 case TGSI_SEMANTIC_SUBGROUP_LE_MASK:
1884 case TGSI_SEMANTIC_SUBGROUP_LT_MASK:
1885 {
1886 LLVMValueRef id = ac_get_thread_id(&ctx->ac);
1887 if (decl->Semantic.Name == TGSI_SEMANTIC_SUBGROUP_GT_MASK ||
1888 decl->Semantic.Name == TGSI_SEMANTIC_SUBGROUP_LE_MASK) {
1889 /* All bits set except LSB */
1890 value = LLVMConstInt(ctx->i64, -2, 0);
1891 } else {
1892 /* All bits set */
1893 value = LLVMConstInt(ctx->i64, -1, 0);
1894 }
1895 id = LLVMBuildZExt(ctx->ac.builder, id, ctx->i64, "");
1896 value = LLVMBuildShl(ctx->ac.builder, value, id, "");
1897 if (decl->Semantic.Name == TGSI_SEMANTIC_SUBGROUP_LE_MASK ||
1898 decl->Semantic.Name == TGSI_SEMANTIC_SUBGROUP_LT_MASK)
1899 value = LLVMBuildNot(ctx->ac.builder, value, "");
1900 value = LLVMBuildBitCast(ctx->ac.builder, value, ctx->v2i32, "");
1901 break;
1902 }
1903
1904 default:
1905 assert(!"unknown system value");
1906 return;
1907 }
1908
1909 ctx->system_values[index] = value;
1910 }
1911
1912 void si_declare_compute_memory(struct si_shader_context *ctx,
1913 const struct tgsi_full_declaration *decl)
1914 {
1915 struct si_shader_selector *sel = ctx->shader->selector;
1916
1917 LLVMTypeRef i8p = LLVMPointerType(ctx->i8, LOCAL_ADDR_SPACE);
1918 LLVMValueRef var;
1919
1920 assert(decl->Declaration.MemType == TGSI_MEMORY_TYPE_SHARED);
1921 assert(decl->Range.First == decl->Range.Last);
1922 assert(!ctx->shared_memory);
1923
1924 var = LLVMAddGlobalInAddressSpace(ctx->ac.module,
1925 LLVMArrayType(ctx->i8, sel->local_size),
1926 "compute_lds",
1927 LOCAL_ADDR_SPACE);
1928 LLVMSetAlignment(var, 4);
1929
1930 ctx->shared_memory = LLVMBuildBitCast(ctx->ac.builder, var, i8p, "");
1931 }
1932
1933 static LLVMValueRef load_const_buffer_desc(struct si_shader_context *ctx, int i)
1934 {
1935 LLVMValueRef list_ptr = LLVMGetParam(ctx->main_fn,
1936 ctx->param_const_and_shader_buffers);
1937
1938 return ac_build_load_to_sgpr(&ctx->ac, list_ptr,
1939 LLVMConstInt(ctx->i32, si_get_constbuf_slot(i), 0));
1940 }
1941
1942 static LLVMValueRef load_ubo(struct ac_shader_abi *abi, LLVMValueRef index)
1943 {
1944 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1945 LLVMValueRef ptr = LLVMGetParam(ctx->main_fn, ctx->param_const_and_shader_buffers);
1946
1947 index = si_llvm_bound_index(ctx, index, ctx->num_const_buffers);
1948 index = LLVMBuildAdd(ctx->ac.builder, index,
1949 LLVMConstInt(ctx->i32, SI_NUM_SHADER_BUFFERS, 0), "");
1950
1951 return ac_build_load_to_sgpr(&ctx->ac, ptr, index);
1952 }
1953
1954 static LLVMValueRef
1955 load_ssbo(struct ac_shader_abi *abi, LLVMValueRef index, bool write)
1956 {
1957 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1958 LLVMValueRef rsrc_ptr = LLVMGetParam(ctx->main_fn,
1959 ctx->param_const_and_shader_buffers);
1960
1961 index = si_llvm_bound_index(ctx, index, ctx->num_shader_buffers);
1962 index = LLVMBuildSub(ctx->ac.builder,
1963 LLVMConstInt(ctx->i32, SI_NUM_SHADER_BUFFERS - 1, 0),
1964 index, "");
1965
1966 return ac_build_load_to_sgpr(&ctx->ac, rsrc_ptr, index);
1967 }
1968
1969 static LLVMValueRef fetch_constant(
1970 struct lp_build_tgsi_context *bld_base,
1971 const struct tgsi_full_src_register *reg,
1972 enum tgsi_opcode_type type,
1973 unsigned swizzle)
1974 {
1975 struct si_shader_context *ctx = si_shader_context(bld_base);
1976 struct si_shader_selector *sel = ctx->shader->selector;
1977 const struct tgsi_ind_register *ireg = &reg->Indirect;
1978 unsigned buf, idx;
1979
1980 LLVMValueRef addr, bufp;
1981
1982 if (swizzle == LP_CHAN_ALL) {
1983 unsigned chan;
1984 LLVMValueRef values[4];
1985 for (chan = 0; chan < TGSI_NUM_CHANNELS; ++chan)
1986 values[chan] = fetch_constant(bld_base, reg, type, chan);
1987
1988 return lp_build_gather_values(&ctx->gallivm, values, 4);
1989 }
1990
1991 /* Split 64-bit loads. */
1992 if (tgsi_type_is_64bit(type)) {
1993 LLVMValueRef lo, hi;
1994
1995 lo = fetch_constant(bld_base, reg, TGSI_TYPE_UNSIGNED, swizzle);
1996 hi = fetch_constant(bld_base, reg, TGSI_TYPE_UNSIGNED, swizzle + 1);
1997 return si_llvm_emit_fetch_64bit(bld_base, type, lo, hi);
1998 }
1999
2000 idx = reg->Register.Index * 4 + swizzle;
2001 if (reg->Register.Indirect) {
2002 addr = si_get_indirect_index(ctx, ireg, 16, idx * 4);
2003 } else {
2004 addr = LLVMConstInt(ctx->i32, idx * 4, 0);
2005 }
2006
2007 /* Fast path when user data SGPRs point to constant buffer 0 directly. */
2008 if (sel->info.const_buffers_declared == 1 &&
2009 sel->info.shader_buffers_declared == 0) {
2010 LLVMValueRef ptr =
2011 LLVMGetParam(ctx->main_fn, ctx->param_const_and_shader_buffers);
2012
2013 /* This enables use of s_load_dword and flat_load_dword for const buffer 0
2014 * loads, and up to x4 load opcode merging. However, it leads to horrible
2015 * code reducing SIMD wave occupancy from 8 to 2 in many cases.
2016 *
2017 * Using s_buffer_load_dword (x1) seems to be the best option right now.
2018 */
2019 #if 0 /* keep this codepath disabled */
2020 if (!reg->Register.Indirect) {
2021 addr = LLVMBuildLShr(ctx->ac.builder, addr, LLVMConstInt(ctx->i32, 2, 0), "");
2022 LLVMValueRef result = ac_build_load_invariant(&ctx->ac, ptr, addr);
2023 return bitcast(bld_base, type, result);
2024 }
2025 #endif
2026
2027 /* Do the bounds checking with a descriptor, because
2028 * doing computation and manual bounds checking of 64-bit
2029 * addresses generates horrible VALU code with very high
2030 * VGPR usage and very low SIMD occupancy.
2031 */
2032 ptr = LLVMBuildPtrToInt(ctx->ac.builder, ptr, ctx->i64, "");
2033 ptr = LLVMBuildBitCast(ctx->ac.builder, ptr, ctx->v2i32, "");
2034
2035 LLVMValueRef desc_elems[] = {
2036 LLVMBuildExtractElement(ctx->ac.builder, ptr, ctx->i32_0, ""),
2037 LLVMBuildExtractElement(ctx->ac.builder, ptr, ctx->i32_1, ""),
2038 LLVMConstInt(ctx->i32, (sel->info.const_file_max[0] + 1) * 16, 0),
2039 LLVMConstInt(ctx->i32,
2040 S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2041 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2042 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2043 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2044 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2045 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32), 0)
2046 };
2047 LLVMValueRef desc = ac_build_gather_values(&ctx->ac, desc_elems, 4);
2048 LLVMValueRef result = buffer_load_const(ctx, desc, addr);
2049 return bitcast(bld_base, type, result);
2050 }
2051
2052 assert(reg->Register.Dimension);
2053 buf = reg->Dimension.Index;
2054
2055 if (reg->Dimension.Indirect) {
2056 LLVMValueRef ptr = LLVMGetParam(ctx->main_fn, ctx->param_const_and_shader_buffers);
2057 LLVMValueRef index;
2058 index = si_get_bounded_indirect_index(ctx, &reg->DimIndirect,
2059 reg->Dimension.Index,
2060 ctx->num_const_buffers);
2061 index = LLVMBuildAdd(ctx->ac.builder, index,
2062 LLVMConstInt(ctx->i32, SI_NUM_SHADER_BUFFERS, 0), "");
2063 bufp = ac_build_load_to_sgpr(&ctx->ac, ptr, index);
2064 } else
2065 bufp = load_const_buffer_desc(ctx, buf);
2066
2067 return bitcast(bld_base, type, buffer_load_const(ctx, bufp, addr));
2068 }
2069
2070 /* Upper 16 bits must be zero. */
2071 static LLVMValueRef si_llvm_pack_two_int16(struct si_shader_context *ctx,
2072 LLVMValueRef val[2])
2073 {
2074 return LLVMBuildOr(ctx->ac.builder, val[0],
2075 LLVMBuildShl(ctx->ac.builder, val[1],
2076 LLVMConstInt(ctx->i32, 16, 0),
2077 ""), "");
2078 }
2079
2080 /* Upper 16 bits are ignored and will be dropped. */
2081 static LLVMValueRef si_llvm_pack_two_int32_as_int16(struct si_shader_context *ctx,
2082 LLVMValueRef val[2])
2083 {
2084 LLVMValueRef v[2] = {
2085 LLVMBuildAnd(ctx->ac.builder, val[0],
2086 LLVMConstInt(ctx->i32, 0xffff, 0), ""),
2087 val[1],
2088 };
2089 return si_llvm_pack_two_int16(ctx, v);
2090 }
2091
2092 /* Initialize arguments for the shader export intrinsic */
2093 static void si_llvm_init_export_args(struct lp_build_tgsi_context *bld_base,
2094 LLVMValueRef *values,
2095 unsigned target,
2096 struct ac_export_args *args)
2097 {
2098 struct si_shader_context *ctx = si_shader_context(bld_base);
2099 struct lp_build_context *base = &bld_base->base;
2100 LLVMBuilderRef builder = ctx->ac.builder;
2101 LLVMValueRef val[4];
2102 unsigned spi_shader_col_format = V_028714_SPI_SHADER_32_ABGR;
2103 unsigned chan;
2104 bool is_int8, is_int10;
2105
2106 /* Default is 0xf. Adjusted below depending on the format. */
2107 args->enabled_channels = 0xf; /* writemask */
2108
2109 /* Specify whether the EXEC mask represents the valid mask */
2110 args->valid_mask = 0;
2111
2112 /* Specify whether this is the last export */
2113 args->done = 0;
2114
2115 /* Specify the target we are exporting */
2116 args->target = target;
2117
2118 if (ctx->type == PIPE_SHADER_FRAGMENT) {
2119 const struct si_shader_key *key = &ctx->shader->key;
2120 unsigned col_formats = key->part.ps.epilog.spi_shader_col_format;
2121 int cbuf = target - V_008DFC_SQ_EXP_MRT;
2122
2123 assert(cbuf >= 0 && cbuf < 8);
2124 spi_shader_col_format = (col_formats >> (cbuf * 4)) & 0xf;
2125 is_int8 = (key->part.ps.epilog.color_is_int8 >> cbuf) & 0x1;
2126 is_int10 = (key->part.ps.epilog.color_is_int10 >> cbuf) & 0x1;
2127 }
2128
2129 args->compr = false;
2130 args->out[0] = base->undef;
2131 args->out[1] = base->undef;
2132 args->out[2] = base->undef;
2133 args->out[3] = base->undef;
2134
2135 switch (spi_shader_col_format) {
2136 case V_028714_SPI_SHADER_ZERO:
2137 args->enabled_channels = 0; /* writemask */
2138 args->target = V_008DFC_SQ_EXP_NULL;
2139 break;
2140
2141 case V_028714_SPI_SHADER_32_R:
2142 args->enabled_channels = 1; /* writemask */
2143 args->out[0] = values[0];
2144 break;
2145
2146 case V_028714_SPI_SHADER_32_GR:
2147 args->enabled_channels = 0x3; /* writemask */
2148 args->out[0] = values[0];
2149 args->out[1] = values[1];
2150 break;
2151
2152 case V_028714_SPI_SHADER_32_AR:
2153 args->enabled_channels = 0x9; /* writemask */
2154 args->out[0] = values[0];
2155 args->out[3] = values[3];
2156 break;
2157
2158 case V_028714_SPI_SHADER_FP16_ABGR:
2159 args->compr = 1; /* COMPR flag */
2160
2161 for (chan = 0; chan < 2; chan++) {
2162 LLVMValueRef pack_args[2] = {
2163 values[2 * chan],
2164 values[2 * chan + 1]
2165 };
2166 LLVMValueRef packed;
2167
2168 packed = ac_build_cvt_pkrtz_f16(&ctx->ac, pack_args);
2169 args->out[chan] = ac_to_float(&ctx->ac, packed);
2170 }
2171 break;
2172
2173 case V_028714_SPI_SHADER_UNORM16_ABGR:
2174 for (chan = 0; chan < 4; chan++) {
2175 val[chan] = ac_build_clamp(&ctx->ac, values[chan]);
2176 val[chan] = LLVMBuildFMul(builder, val[chan],
2177 LLVMConstReal(ctx->f32, 65535), "");
2178 val[chan] = LLVMBuildFAdd(builder, val[chan],
2179 LLVMConstReal(ctx->f32, 0.5), "");
2180 val[chan] = LLVMBuildFPToUI(builder, val[chan],
2181 ctx->i32, "");
2182 }
2183
2184 args->compr = 1; /* COMPR flag */
2185 args->out[0] = ac_to_float(&ctx->ac, si_llvm_pack_two_int16(ctx, val));
2186 args->out[1] = ac_to_float(&ctx->ac, si_llvm_pack_two_int16(ctx, val+2));
2187 break;
2188
2189 case V_028714_SPI_SHADER_SNORM16_ABGR:
2190 for (chan = 0; chan < 4; chan++) {
2191 /* Clamp between [-1, 1]. */
2192 val[chan] = lp_build_emit_llvm_binary(bld_base, TGSI_OPCODE_MIN,
2193 values[chan],
2194 LLVMConstReal(ctx->f32, 1));
2195 val[chan] = lp_build_emit_llvm_binary(bld_base, TGSI_OPCODE_MAX,
2196 val[chan],
2197 LLVMConstReal(ctx->f32, -1));
2198 /* Convert to a signed integer in [-32767, 32767]. */
2199 val[chan] = LLVMBuildFMul(builder, val[chan],
2200 LLVMConstReal(ctx->f32, 32767), "");
2201 /* If positive, add 0.5, else add -0.5. */
2202 val[chan] = LLVMBuildFAdd(builder, val[chan],
2203 LLVMBuildSelect(builder,
2204 LLVMBuildFCmp(builder, LLVMRealOGE,
2205 val[chan], ctx->ac.f32_0, ""),
2206 LLVMConstReal(ctx->f32, 0.5),
2207 LLVMConstReal(ctx->f32, -0.5), ""), "");
2208 val[chan] = LLVMBuildFPToSI(builder, val[chan], ctx->i32, "");
2209 }
2210
2211 args->compr = 1; /* COMPR flag */
2212 args->out[0] = ac_to_float(&ctx->ac, si_llvm_pack_two_int32_as_int16(ctx, val));
2213 args->out[1] = ac_to_float(&ctx->ac, si_llvm_pack_two_int32_as_int16(ctx, val+2));
2214 break;
2215
2216 case V_028714_SPI_SHADER_UINT16_ABGR: {
2217 LLVMValueRef max_rgb = LLVMConstInt(ctx->i32,
2218 is_int8 ? 255 : is_int10 ? 1023 : 65535, 0);
2219 LLVMValueRef max_alpha =
2220 !is_int10 ? max_rgb : LLVMConstInt(ctx->i32, 3, 0);
2221
2222 /* Clamp. */
2223 for (chan = 0; chan < 4; chan++) {
2224 val[chan] = ac_to_integer(&ctx->ac, values[chan]);
2225 val[chan] = lp_build_emit_llvm_binary(bld_base, TGSI_OPCODE_UMIN,
2226 val[chan],
2227 chan == 3 ? max_alpha : max_rgb);
2228 }
2229
2230 args->compr = 1; /* COMPR flag */
2231 args->out[0] = ac_to_float(&ctx->ac, si_llvm_pack_two_int16(ctx, val));
2232 args->out[1] = ac_to_float(&ctx->ac, si_llvm_pack_two_int16(ctx, val+2));
2233 break;
2234 }
2235
2236 case V_028714_SPI_SHADER_SINT16_ABGR: {
2237 LLVMValueRef max_rgb = LLVMConstInt(ctx->i32,
2238 is_int8 ? 127 : is_int10 ? 511 : 32767, 0);
2239 LLVMValueRef min_rgb = LLVMConstInt(ctx->i32,
2240 is_int8 ? -128 : is_int10 ? -512 : -32768, 0);
2241 LLVMValueRef max_alpha =
2242 !is_int10 ? max_rgb : ctx->i32_1;
2243 LLVMValueRef min_alpha =
2244 !is_int10 ? min_rgb : LLVMConstInt(ctx->i32, -2, 0);
2245
2246 /* Clamp. */
2247 for (chan = 0; chan < 4; chan++) {
2248 val[chan] = ac_to_integer(&ctx->ac, values[chan]);
2249 val[chan] = lp_build_emit_llvm_binary(bld_base,
2250 TGSI_OPCODE_IMIN,
2251 val[chan], chan == 3 ? max_alpha : max_rgb);
2252 val[chan] = lp_build_emit_llvm_binary(bld_base,
2253 TGSI_OPCODE_IMAX,
2254 val[chan], chan == 3 ? min_alpha : min_rgb);
2255 }
2256
2257 args->compr = 1; /* COMPR flag */
2258 args->out[0] = ac_to_float(&ctx->ac, si_llvm_pack_two_int32_as_int16(ctx, val));
2259 args->out[1] = ac_to_float(&ctx->ac, si_llvm_pack_two_int32_as_int16(ctx, val+2));
2260 break;
2261 }
2262
2263 case V_028714_SPI_SHADER_32_ABGR:
2264 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
2265 break;
2266 }
2267 }
2268
2269 static void si_alpha_test(struct lp_build_tgsi_context *bld_base,
2270 LLVMValueRef alpha)
2271 {
2272 struct si_shader_context *ctx = si_shader_context(bld_base);
2273
2274 if (ctx->shader->key.part.ps.epilog.alpha_func != PIPE_FUNC_NEVER) {
2275 static LLVMRealPredicate cond_map[PIPE_FUNC_ALWAYS + 1] = {
2276 [PIPE_FUNC_LESS] = LLVMRealOLT,
2277 [PIPE_FUNC_EQUAL] = LLVMRealOEQ,
2278 [PIPE_FUNC_LEQUAL] = LLVMRealOLE,
2279 [PIPE_FUNC_GREATER] = LLVMRealOGT,
2280 [PIPE_FUNC_NOTEQUAL] = LLVMRealONE,
2281 [PIPE_FUNC_GEQUAL] = LLVMRealOGE,
2282 };
2283 LLVMRealPredicate cond = cond_map[ctx->shader->key.part.ps.epilog.alpha_func];
2284 assert(cond);
2285
2286 LLVMValueRef alpha_ref = LLVMGetParam(ctx->main_fn,
2287 SI_PARAM_ALPHA_REF);
2288 LLVMValueRef alpha_pass =
2289 LLVMBuildFCmp(ctx->ac.builder, cond, alpha, alpha_ref, "");
2290 ac_build_kill_if_false(&ctx->ac, alpha_pass);
2291 } else {
2292 ac_build_kill_if_false(&ctx->ac, LLVMConstInt(ctx->i1, 0, 0));
2293 }
2294 }
2295
2296 static LLVMValueRef si_scale_alpha_by_sample_mask(struct lp_build_tgsi_context *bld_base,
2297 LLVMValueRef alpha,
2298 unsigned samplemask_param)
2299 {
2300 struct si_shader_context *ctx = si_shader_context(bld_base);
2301 LLVMValueRef coverage;
2302
2303 /* alpha = alpha * popcount(coverage) / SI_NUM_SMOOTH_AA_SAMPLES */
2304 coverage = LLVMGetParam(ctx->main_fn,
2305 samplemask_param);
2306 coverage = ac_to_integer(&ctx->ac, coverage);
2307
2308 coverage = lp_build_intrinsic(ctx->ac.builder, "llvm.ctpop.i32",
2309 ctx->i32,
2310 &coverage, 1, LP_FUNC_ATTR_READNONE);
2311
2312 coverage = LLVMBuildUIToFP(ctx->ac.builder, coverage,
2313 ctx->f32, "");
2314
2315 coverage = LLVMBuildFMul(ctx->ac.builder, coverage,
2316 LLVMConstReal(ctx->f32,
2317 1.0 / SI_NUM_SMOOTH_AA_SAMPLES), "");
2318
2319 return LLVMBuildFMul(ctx->ac.builder, alpha, coverage, "");
2320 }
2321
2322 static void si_llvm_emit_clipvertex(struct lp_build_tgsi_context *bld_base,
2323 struct ac_export_args *pos, LLVMValueRef *out_elts)
2324 {
2325 struct si_shader_context *ctx = si_shader_context(bld_base);
2326 struct lp_build_context *base = &bld_base->base;
2327 unsigned reg_index;
2328 unsigned chan;
2329 unsigned const_chan;
2330 LLVMValueRef base_elt;
2331 LLVMValueRef ptr = LLVMGetParam(ctx->main_fn, ctx->param_rw_buffers);
2332 LLVMValueRef constbuf_index = LLVMConstInt(ctx->i32,
2333 SI_VS_CONST_CLIP_PLANES, 0);
2334 LLVMValueRef const_resource = ac_build_load_to_sgpr(&ctx->ac, ptr, constbuf_index);
2335
2336 for (reg_index = 0; reg_index < 2; reg_index ++) {
2337 struct ac_export_args *args = &pos[2 + reg_index];
2338
2339 args->out[0] =
2340 args->out[1] =
2341 args->out[2] =
2342 args->out[3] = LLVMConstReal(ctx->f32, 0.0f);
2343
2344 /* Compute dot products of position and user clip plane vectors */
2345 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2346 for (const_chan = 0; const_chan < TGSI_NUM_CHANNELS; const_chan++) {
2347 LLVMValueRef addr =
2348 LLVMConstInt(ctx->i32, ((reg_index * 4 + chan) * 4 +
2349 const_chan) * 4, 0);
2350 base_elt = buffer_load_const(ctx, const_resource,
2351 addr);
2352 args->out[chan] =
2353 lp_build_add(base, args->out[chan],
2354 lp_build_mul(base, base_elt,
2355 out_elts[const_chan]));
2356 }
2357 }
2358
2359 args->enabled_channels = 0xf;
2360 args->valid_mask = 0;
2361 args->done = 0;
2362 args->target = V_008DFC_SQ_EXP_POS + 2 + reg_index;
2363 args->compr = 0;
2364 }
2365 }
2366
2367 static void si_dump_streamout(struct pipe_stream_output_info *so)
2368 {
2369 unsigned i;
2370
2371 if (so->num_outputs)
2372 fprintf(stderr, "STREAMOUT\n");
2373
2374 for (i = 0; i < so->num_outputs; i++) {
2375 unsigned mask = ((1 << so->output[i].num_components) - 1) <<
2376 so->output[i].start_component;
2377 fprintf(stderr, " %i: BUF%i[%i..%i] <- OUT[%i].%s%s%s%s\n",
2378 i, so->output[i].output_buffer,
2379 so->output[i].dst_offset, so->output[i].dst_offset + so->output[i].num_components - 1,
2380 so->output[i].register_index,
2381 mask & 1 ? "x" : "",
2382 mask & 2 ? "y" : "",
2383 mask & 4 ? "z" : "",
2384 mask & 8 ? "w" : "");
2385 }
2386 }
2387
2388 static void emit_streamout_output(struct si_shader_context *ctx,
2389 LLVMValueRef const *so_buffers,
2390 LLVMValueRef const *so_write_offsets,
2391 struct pipe_stream_output *stream_out,
2392 struct si_shader_output_values *shader_out)
2393 {
2394 unsigned buf_idx = stream_out->output_buffer;
2395 unsigned start = stream_out->start_component;
2396 unsigned num_comps = stream_out->num_components;
2397 LLVMValueRef out[4];
2398
2399 assert(num_comps && num_comps <= 4);
2400 if (!num_comps || num_comps > 4)
2401 return;
2402
2403 /* Load the output as int. */
2404 for (int j = 0; j < num_comps; j++) {
2405 assert(stream_out->stream == shader_out->vertex_stream[start + j]);
2406
2407 out[j] = ac_to_integer(&ctx->ac, shader_out->values[start + j]);
2408 }
2409
2410 /* Pack the output. */
2411 LLVMValueRef vdata = NULL;
2412
2413 switch (num_comps) {
2414 case 1: /* as i32 */
2415 vdata = out[0];
2416 break;
2417 case 2: /* as v2i32 */
2418 case 3: /* as v4i32 (aligned to 4) */
2419 case 4: /* as v4i32 */
2420 vdata = LLVMGetUndef(LLVMVectorType(ctx->i32, util_next_power_of_two(num_comps)));
2421 for (int j = 0; j < num_comps; j++) {
2422 vdata = LLVMBuildInsertElement(ctx->ac.builder, vdata, out[j],
2423 LLVMConstInt(ctx->i32, j, 0), "");
2424 }
2425 break;
2426 }
2427
2428 ac_build_buffer_store_dword(&ctx->ac, so_buffers[buf_idx],
2429 vdata, num_comps,
2430 so_write_offsets[buf_idx],
2431 ctx->i32_0,
2432 stream_out->dst_offset * 4, 1, 1, true, false);
2433 }
2434
2435 /**
2436 * Write streamout data to buffers for vertex stream @p stream (different
2437 * vertex streams can occur for GS copy shaders).
2438 */
2439 static void si_llvm_emit_streamout(struct si_shader_context *ctx,
2440 struct si_shader_output_values *outputs,
2441 unsigned noutput, unsigned stream)
2442 {
2443 struct si_shader_selector *sel = ctx->shader->selector;
2444 struct pipe_stream_output_info *so = &sel->so;
2445 LLVMBuilderRef builder = ctx->ac.builder;
2446 int i;
2447 struct lp_build_if_state if_ctx;
2448
2449 /* Get bits [22:16], i.e. (so_param >> 16) & 127; */
2450 LLVMValueRef so_vtx_count =
2451 unpack_param(ctx, ctx->param_streamout_config, 16, 7);
2452
2453 LLVMValueRef tid = ac_get_thread_id(&ctx->ac);
2454
2455 /* can_emit = tid < so_vtx_count; */
2456 LLVMValueRef can_emit =
2457 LLVMBuildICmp(builder, LLVMIntULT, tid, so_vtx_count, "");
2458
2459 /* Emit the streamout code conditionally. This actually avoids
2460 * out-of-bounds buffer access. The hw tells us via the SGPR
2461 * (so_vtx_count) which threads are allowed to emit streamout data. */
2462 lp_build_if(&if_ctx, &ctx->gallivm, can_emit);
2463 {
2464 /* The buffer offset is computed as follows:
2465 * ByteOffset = streamout_offset[buffer_id]*4 +
2466 * (streamout_write_index + thread_id)*stride[buffer_id] +
2467 * attrib_offset
2468 */
2469
2470 LLVMValueRef so_write_index =
2471 LLVMGetParam(ctx->main_fn,
2472 ctx->param_streamout_write_index);
2473
2474 /* Compute (streamout_write_index + thread_id). */
2475 so_write_index = LLVMBuildAdd(builder, so_write_index, tid, "");
2476
2477 /* Load the descriptor and compute the write offset for each
2478 * enabled buffer. */
2479 LLVMValueRef so_write_offset[4] = {};
2480 LLVMValueRef so_buffers[4];
2481 LLVMValueRef buf_ptr = LLVMGetParam(ctx->main_fn,
2482 ctx->param_rw_buffers);
2483
2484 for (i = 0; i < 4; i++) {
2485 if (!so->stride[i])
2486 continue;
2487
2488 LLVMValueRef offset = LLVMConstInt(ctx->i32,
2489 SI_VS_STREAMOUT_BUF0 + i, 0);
2490
2491 so_buffers[i] = ac_build_load_to_sgpr(&ctx->ac, buf_ptr, offset);
2492
2493 LLVMValueRef so_offset = LLVMGetParam(ctx->main_fn,
2494 ctx->param_streamout_offset[i]);
2495 so_offset = LLVMBuildMul(builder, so_offset, LLVMConstInt(ctx->i32, 4, 0), "");
2496
2497 so_write_offset[i] = LLVMBuildMul(builder, so_write_index,
2498 LLVMConstInt(ctx->i32, so->stride[i]*4, 0), "");
2499 so_write_offset[i] = LLVMBuildAdd(builder, so_write_offset[i], so_offset, "");
2500 }
2501
2502 /* Write streamout data. */
2503 for (i = 0; i < so->num_outputs; i++) {
2504 unsigned reg = so->output[i].register_index;
2505
2506 if (reg >= noutput)
2507 continue;
2508
2509 if (stream != so->output[i].stream)
2510 continue;
2511
2512 emit_streamout_output(ctx, so_buffers, so_write_offset,
2513 &so->output[i], &outputs[reg]);
2514 }
2515 }
2516 lp_build_endif(&if_ctx);
2517 }
2518
2519 static void si_export_param(struct si_shader_context *ctx, unsigned index,
2520 LLVMValueRef *values)
2521 {
2522 struct ac_export_args args;
2523
2524 si_llvm_init_export_args(&ctx->bld_base, values,
2525 V_008DFC_SQ_EXP_PARAM + index, &args);
2526 ac_build_export(&ctx->ac, &args);
2527 }
2528
2529 static void si_build_param_exports(struct si_shader_context *ctx,
2530 struct si_shader_output_values *outputs,
2531 unsigned noutput)
2532 {
2533 struct si_shader *shader = ctx->shader;
2534 unsigned param_count = 0;
2535
2536 for (unsigned i = 0; i < noutput; i++) {
2537 unsigned semantic_name = outputs[i].semantic_name;
2538 unsigned semantic_index = outputs[i].semantic_index;
2539
2540 if (outputs[i].vertex_stream[0] != 0 &&
2541 outputs[i].vertex_stream[1] != 0 &&
2542 outputs[i].vertex_stream[2] != 0 &&
2543 outputs[i].vertex_stream[3] != 0)
2544 continue;
2545
2546 switch (semantic_name) {
2547 case TGSI_SEMANTIC_LAYER:
2548 case TGSI_SEMANTIC_VIEWPORT_INDEX:
2549 case TGSI_SEMANTIC_CLIPDIST:
2550 case TGSI_SEMANTIC_COLOR:
2551 case TGSI_SEMANTIC_BCOLOR:
2552 case TGSI_SEMANTIC_PRIMID:
2553 case TGSI_SEMANTIC_FOG:
2554 case TGSI_SEMANTIC_TEXCOORD:
2555 case TGSI_SEMANTIC_GENERIC:
2556 break;
2557 default:
2558 continue;
2559 }
2560
2561 if ((semantic_name != TGSI_SEMANTIC_GENERIC ||
2562 semantic_index < SI_MAX_IO_GENERIC) &&
2563 shader->key.opt.kill_outputs &
2564 (1ull << si_shader_io_get_unique_index(semantic_name, semantic_index)))
2565 continue;
2566
2567 si_export_param(ctx, param_count, outputs[i].values);
2568
2569 assert(i < ARRAY_SIZE(shader->info.vs_output_param_offset));
2570 shader->info.vs_output_param_offset[i] = param_count++;
2571 }
2572
2573 shader->info.nr_param_exports = param_count;
2574 }
2575
2576 /* Generate export instructions for hardware VS shader stage */
2577 static void si_llvm_export_vs(struct lp_build_tgsi_context *bld_base,
2578 struct si_shader_output_values *outputs,
2579 unsigned noutput)
2580 {
2581 struct si_shader_context *ctx = si_shader_context(bld_base);
2582 struct si_shader *shader = ctx->shader;
2583 struct ac_export_args pos_args[4] = {};
2584 LLVMValueRef psize_value = NULL, edgeflag_value = NULL, layer_value = NULL, viewport_index_value = NULL;
2585 unsigned pos_idx;
2586 int i;
2587
2588 /* Build position exports. */
2589 for (i = 0; i < noutput; i++) {
2590 switch (outputs[i].semantic_name) {
2591 case TGSI_SEMANTIC_POSITION:
2592 si_llvm_init_export_args(bld_base, outputs[i].values,
2593 V_008DFC_SQ_EXP_POS, &pos_args[0]);
2594 break;
2595 case TGSI_SEMANTIC_PSIZE:
2596 psize_value = outputs[i].values[0];
2597 break;
2598 case TGSI_SEMANTIC_LAYER:
2599 layer_value = outputs[i].values[0];
2600 break;
2601 case TGSI_SEMANTIC_VIEWPORT_INDEX:
2602 viewport_index_value = outputs[i].values[0];
2603 break;
2604 case TGSI_SEMANTIC_EDGEFLAG:
2605 edgeflag_value = outputs[i].values[0];
2606 break;
2607 case TGSI_SEMANTIC_CLIPDIST:
2608 if (!shader->key.opt.clip_disable) {
2609 unsigned index = 2 + outputs[i].semantic_index;
2610 si_llvm_init_export_args(bld_base, outputs[i].values,
2611 V_008DFC_SQ_EXP_POS + index,
2612 &pos_args[index]);
2613 }
2614 break;
2615 case TGSI_SEMANTIC_CLIPVERTEX:
2616 if (!shader->key.opt.clip_disable) {
2617 si_llvm_emit_clipvertex(bld_base, pos_args,
2618 outputs[i].values);
2619 }
2620 break;
2621 }
2622 }
2623
2624 /* We need to add the position output manually if it's missing. */
2625 if (!pos_args[0].out[0]) {
2626 pos_args[0].enabled_channels = 0xf; /* writemask */
2627 pos_args[0].valid_mask = 0; /* EXEC mask */
2628 pos_args[0].done = 0; /* last export? */
2629 pos_args[0].target = V_008DFC_SQ_EXP_POS;
2630 pos_args[0].compr = 0; /* COMPR flag */
2631 pos_args[0].out[0] = ctx->ac.f32_0; /* X */
2632 pos_args[0].out[1] = ctx->ac.f32_0; /* Y */
2633 pos_args[0].out[2] = ctx->ac.f32_0; /* Z */
2634 pos_args[0].out[3] = ctx->ac.f32_1; /* W */
2635 }
2636
2637 /* Write the misc vector (point size, edgeflag, layer, viewport). */
2638 if (shader->selector->info.writes_psize ||
2639 shader->selector->info.writes_edgeflag ||
2640 shader->selector->info.writes_viewport_index ||
2641 shader->selector->info.writes_layer) {
2642 pos_args[1].enabled_channels = shader->selector->info.writes_psize |
2643 (shader->selector->info.writes_edgeflag << 1) |
2644 (shader->selector->info.writes_layer << 2);
2645
2646 pos_args[1].valid_mask = 0; /* EXEC mask */
2647 pos_args[1].done = 0; /* last export? */
2648 pos_args[1].target = V_008DFC_SQ_EXP_POS + 1;
2649 pos_args[1].compr = 0; /* COMPR flag */
2650 pos_args[1].out[0] = ctx->ac.f32_0; /* X */
2651 pos_args[1].out[1] = ctx->ac.f32_0; /* Y */
2652 pos_args[1].out[2] = ctx->ac.f32_0; /* Z */
2653 pos_args[1].out[3] = ctx->ac.f32_0; /* W */
2654
2655 if (shader->selector->info.writes_psize)
2656 pos_args[1].out[0] = psize_value;
2657
2658 if (shader->selector->info.writes_edgeflag) {
2659 /* The output is a float, but the hw expects an integer
2660 * with the first bit containing the edge flag. */
2661 edgeflag_value = LLVMBuildFPToUI(ctx->ac.builder,
2662 edgeflag_value,
2663 ctx->i32, "");
2664 edgeflag_value = ac_build_umin(&ctx->ac,
2665 edgeflag_value,
2666 ctx->i32_1);
2667
2668 /* The LLVM intrinsic expects a float. */
2669 pos_args[1].out[1] = ac_to_float(&ctx->ac, edgeflag_value);
2670 }
2671
2672 if (ctx->screen->b.chip_class >= GFX9) {
2673 /* GFX9 has the layer in out.z[10:0] and the viewport
2674 * index in out.z[19:16].
2675 */
2676 if (shader->selector->info.writes_layer)
2677 pos_args[1].out[2] = layer_value;
2678
2679 if (shader->selector->info.writes_viewport_index) {
2680 LLVMValueRef v = viewport_index_value;
2681
2682 v = ac_to_integer(&ctx->ac, v);
2683 v = LLVMBuildShl(ctx->ac.builder, v,
2684 LLVMConstInt(ctx->i32, 16, 0), "");
2685 v = LLVMBuildOr(ctx->ac.builder, v,
2686 ac_to_integer(&ctx->ac, pos_args[1].out[2]), "");
2687 pos_args[1].out[2] = ac_to_float(&ctx->ac, v);
2688 pos_args[1].enabled_channels |= 1 << 2;
2689 }
2690 } else {
2691 if (shader->selector->info.writes_layer)
2692 pos_args[1].out[2] = layer_value;
2693
2694 if (shader->selector->info.writes_viewport_index) {
2695 pos_args[1].out[3] = viewport_index_value;
2696 pos_args[1].enabled_channels |= 1 << 3;
2697 }
2698 }
2699 }
2700
2701 for (i = 0; i < 4; i++)
2702 if (pos_args[i].out[0])
2703 shader->info.nr_pos_exports++;
2704
2705 pos_idx = 0;
2706 for (i = 0; i < 4; i++) {
2707 if (!pos_args[i].out[0])
2708 continue;
2709
2710 /* Specify the target we are exporting */
2711 pos_args[i].target = V_008DFC_SQ_EXP_POS + pos_idx++;
2712
2713 if (pos_idx == shader->info.nr_pos_exports)
2714 /* Specify that this is the last export */
2715 pos_args[i].done = 1;
2716
2717 ac_build_export(&ctx->ac, &pos_args[i]);
2718 }
2719
2720 /* Build parameter exports. */
2721 si_build_param_exports(ctx, outputs, noutput);
2722 }
2723
2724 /**
2725 * Forward all outputs from the vertex shader to the TES. This is only used
2726 * for the fixed function TCS.
2727 */
2728 static void si_copy_tcs_inputs(struct lp_build_tgsi_context *bld_base)
2729 {
2730 struct si_shader_context *ctx = si_shader_context(bld_base);
2731 LLVMValueRef invocation_id, buffer, buffer_offset;
2732 LLVMValueRef lds_vertex_stride, lds_vertex_offset, lds_base;
2733 uint64_t inputs;
2734
2735 invocation_id = unpack_param(ctx, ctx->param_tcs_rel_ids, 8, 5);
2736 buffer = desc_from_addr_base64k(ctx, ctx->param_tcs_offchip_addr_base64k);
2737 buffer_offset = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
2738
2739 lds_vertex_stride = get_tcs_in_vertex_dw_stride(ctx);
2740 lds_vertex_offset = LLVMBuildMul(ctx->ac.builder, invocation_id,
2741 lds_vertex_stride, "");
2742 lds_base = get_tcs_in_current_patch_offset(ctx);
2743 lds_base = LLVMBuildAdd(ctx->ac.builder, lds_base, lds_vertex_offset, "");
2744
2745 inputs = ctx->shader->key.mono.u.ff_tcs_inputs_to_copy;
2746 while (inputs) {
2747 unsigned i = u_bit_scan64(&inputs);
2748
2749 LLVMValueRef lds_ptr = LLVMBuildAdd(ctx->ac.builder, lds_base,
2750 LLVMConstInt(ctx->i32, 4 * i, 0),
2751 "");
2752
2753 LLVMValueRef buffer_addr = get_tcs_tes_buffer_address(ctx,
2754 get_rel_patch_id(ctx),
2755 invocation_id,
2756 LLVMConstInt(ctx->i32, i, 0));
2757
2758 LLVMValueRef value = lds_load(bld_base, TGSI_TYPE_SIGNED, ~0,
2759 lds_ptr);
2760
2761 ac_build_buffer_store_dword(&ctx->ac, buffer, value, 4, buffer_addr,
2762 buffer_offset, 0, 1, 0, true, false);
2763 }
2764 }
2765
2766 static void si_write_tess_factors(struct lp_build_tgsi_context *bld_base,
2767 LLVMValueRef rel_patch_id,
2768 LLVMValueRef invocation_id,
2769 LLVMValueRef tcs_out_current_patch_data_offset,
2770 LLVMValueRef invoc0_tf_outer[4],
2771 LLVMValueRef invoc0_tf_inner[2])
2772 {
2773 struct si_shader_context *ctx = si_shader_context(bld_base);
2774 struct si_shader *shader = ctx->shader;
2775 unsigned tess_inner_index, tess_outer_index;
2776 LLVMValueRef lds_base, lds_inner, lds_outer, byteoffset, buffer;
2777 LLVMValueRef out[6], vec0, vec1, tf_base, inner[4], outer[4];
2778 unsigned stride, outer_comps, inner_comps, i, offset;
2779 struct lp_build_if_state if_ctx, inner_if_ctx;
2780
2781 /* Add a barrier before loading tess factors from LDS. */
2782 if (!shader->key.part.tcs.epilog.invoc0_tess_factors_are_def)
2783 si_llvm_emit_barrier(NULL, bld_base, NULL);
2784
2785 /* Do this only for invocation 0, because the tess levels are per-patch,
2786 * not per-vertex.
2787 *
2788 * This can't jump, because invocation 0 executes this. It should
2789 * at least mask out the loads and stores for other invocations.
2790 */
2791 lp_build_if(&if_ctx, &ctx->gallivm,
2792 LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
2793 invocation_id, ctx->i32_0, ""));
2794
2795 /* Determine the layout of one tess factor element in the buffer. */
2796 switch (shader->key.part.tcs.epilog.prim_mode) {
2797 case PIPE_PRIM_LINES:
2798 stride = 2; /* 2 dwords, 1 vec2 store */
2799 outer_comps = 2;
2800 inner_comps = 0;
2801 break;
2802 case PIPE_PRIM_TRIANGLES:
2803 stride = 4; /* 4 dwords, 1 vec4 store */
2804 outer_comps = 3;
2805 inner_comps = 1;
2806 break;
2807 case PIPE_PRIM_QUADS:
2808 stride = 6; /* 6 dwords, 2 stores (vec4 + vec2) */
2809 outer_comps = 4;
2810 inner_comps = 2;
2811 break;
2812 default:
2813 assert(0);
2814 return;
2815 }
2816
2817 for (i = 0; i < 4; i++) {
2818 inner[i] = LLVMGetUndef(ctx->i32);
2819 outer[i] = LLVMGetUndef(ctx->i32);
2820 }
2821
2822 if (shader->key.part.tcs.epilog.invoc0_tess_factors_are_def) {
2823 /* Tess factors are in VGPRs. */
2824 for (i = 0; i < outer_comps; i++)
2825 outer[i] = out[i] = invoc0_tf_outer[i];
2826 for (i = 0; i < inner_comps; i++)
2827 inner[i] = out[outer_comps+i] = invoc0_tf_inner[i];
2828 } else {
2829 /* Load tess_inner and tess_outer from LDS.
2830 * Any invocation can write them, so we can't get them from a temporary.
2831 */
2832 tess_inner_index = si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSINNER, 0);
2833 tess_outer_index = si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSOUTER, 0);
2834
2835 lds_base = tcs_out_current_patch_data_offset;
2836 lds_inner = LLVMBuildAdd(ctx->ac.builder, lds_base,
2837 LLVMConstInt(ctx->i32,
2838 tess_inner_index * 4, 0), "");
2839 lds_outer = LLVMBuildAdd(ctx->ac.builder, lds_base,
2840 LLVMConstInt(ctx->i32,
2841 tess_outer_index * 4, 0), "");
2842
2843 for (i = 0; i < outer_comps; i++) {
2844 outer[i] = out[i] =
2845 lds_load(bld_base, TGSI_TYPE_SIGNED, i, lds_outer);
2846 }
2847 for (i = 0; i < inner_comps; i++) {
2848 inner[i] = out[outer_comps+i] =
2849 lds_load(bld_base, TGSI_TYPE_SIGNED, i, lds_inner);
2850 }
2851 }
2852
2853 if (shader->key.part.tcs.epilog.prim_mode == PIPE_PRIM_LINES) {
2854 /* For isolines, the hardware expects tess factors in the
2855 * reverse order from what GLSL / TGSI specify.
2856 */
2857 LLVMValueRef tmp = out[0];
2858 out[0] = out[1];
2859 out[1] = tmp;
2860 }
2861
2862 /* Convert the outputs to vectors for stores. */
2863 vec0 = lp_build_gather_values(&ctx->gallivm, out, MIN2(stride, 4));
2864 vec1 = NULL;
2865
2866 if (stride > 4)
2867 vec1 = lp_build_gather_values(&ctx->gallivm, out+4, stride - 4);
2868
2869 /* Get the buffer. */
2870 buffer = desc_from_addr_base64k(ctx, ctx->param_tcs_factor_addr_base64k);
2871
2872 /* Get the offset. */
2873 tf_base = LLVMGetParam(ctx->main_fn,
2874 ctx->param_tcs_factor_offset);
2875 byteoffset = LLVMBuildMul(ctx->ac.builder, rel_patch_id,
2876 LLVMConstInt(ctx->i32, 4 * stride, 0), "");
2877
2878 lp_build_if(&inner_if_ctx, &ctx->gallivm,
2879 LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
2880 rel_patch_id, ctx->i32_0, ""));
2881
2882 /* Store the dynamic HS control word. */
2883 offset = 0;
2884 if (ctx->screen->b.chip_class <= VI) {
2885 ac_build_buffer_store_dword(&ctx->ac, buffer,
2886 LLVMConstInt(ctx->i32, 0x80000000, 0),
2887 1, ctx->i32_0, tf_base,
2888 offset, 1, 0, true, false);
2889 offset += 4;
2890 }
2891
2892 lp_build_endif(&inner_if_ctx);
2893
2894 /* Store the tessellation factors. */
2895 ac_build_buffer_store_dword(&ctx->ac, buffer, vec0,
2896 MIN2(stride, 4), byteoffset, tf_base,
2897 offset, 1, 0, true, false);
2898 offset += 16;
2899 if (vec1)
2900 ac_build_buffer_store_dword(&ctx->ac, buffer, vec1,
2901 stride - 4, byteoffset, tf_base,
2902 offset, 1, 0, true, false);
2903
2904 /* Store the tess factors into the offchip buffer if TES reads them. */
2905 if (shader->key.part.tcs.epilog.tes_reads_tess_factors) {
2906 LLVMValueRef buf, base, inner_vec, outer_vec, tf_outer_offset;
2907 LLVMValueRef tf_inner_offset;
2908 unsigned param_outer, param_inner;
2909
2910 buf = desc_from_addr_base64k(ctx, ctx->param_tcs_offchip_addr_base64k);
2911 base = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
2912
2913 param_outer = si_shader_io_get_unique_index_patch(
2914 TGSI_SEMANTIC_TESSOUTER, 0);
2915 tf_outer_offset = get_tcs_tes_buffer_address(ctx, rel_patch_id, NULL,
2916 LLVMConstInt(ctx->i32, param_outer, 0));
2917
2918 outer_vec = lp_build_gather_values(&ctx->gallivm, outer,
2919 util_next_power_of_two(outer_comps));
2920
2921 ac_build_buffer_store_dword(&ctx->ac, buf, outer_vec,
2922 outer_comps, tf_outer_offset,
2923 base, 0, 1, 0, true, false);
2924 if (inner_comps) {
2925 param_inner = si_shader_io_get_unique_index_patch(
2926 TGSI_SEMANTIC_TESSINNER, 0);
2927 tf_inner_offset = get_tcs_tes_buffer_address(ctx, rel_patch_id, NULL,
2928 LLVMConstInt(ctx->i32, param_inner, 0));
2929
2930 inner_vec = inner_comps == 1 ? inner[0] :
2931 lp_build_gather_values(&ctx->gallivm, inner, inner_comps);
2932 ac_build_buffer_store_dword(&ctx->ac, buf, inner_vec,
2933 inner_comps, tf_inner_offset,
2934 base, 0, 1, 0, true, false);
2935 }
2936 }
2937
2938 lp_build_endif(&if_ctx);
2939 }
2940
2941 static LLVMValueRef
2942 si_insert_input_ret(struct si_shader_context *ctx, LLVMValueRef ret,
2943 unsigned param, unsigned return_index)
2944 {
2945 return LLVMBuildInsertValue(ctx->ac.builder, ret,
2946 LLVMGetParam(ctx->main_fn, param),
2947 return_index, "");
2948 }
2949
2950 static LLVMValueRef
2951 si_insert_input_ret_float(struct si_shader_context *ctx, LLVMValueRef ret,
2952 unsigned param, unsigned return_index)
2953 {
2954 LLVMBuilderRef builder = ctx->ac.builder;
2955 LLVMValueRef p = LLVMGetParam(ctx->main_fn, param);
2956
2957 return LLVMBuildInsertValue(builder, ret,
2958 ac_to_float(&ctx->ac, p),
2959 return_index, "");
2960 }
2961
2962 static LLVMValueRef
2963 si_insert_input_ptr_as_2xi32(struct si_shader_context *ctx, LLVMValueRef ret,
2964 unsigned param, unsigned return_index)
2965 {
2966 LLVMBuilderRef builder = ctx->ac.builder;
2967 LLVMValueRef ptr, lo, hi;
2968
2969 ptr = LLVMGetParam(ctx->main_fn, param);
2970 ptr = LLVMBuildPtrToInt(builder, ptr, ctx->i64, "");
2971 ptr = LLVMBuildBitCast(builder, ptr, ctx->v2i32, "");
2972 lo = LLVMBuildExtractElement(builder, ptr, ctx->i32_0, "");
2973 hi = LLVMBuildExtractElement(builder, ptr, ctx->i32_1, "");
2974 ret = LLVMBuildInsertValue(builder, ret, lo, return_index, "");
2975 return LLVMBuildInsertValue(builder, ret, hi, return_index + 1, "");
2976 }
2977
2978 /* This only writes the tessellation factor levels. */
2979 static void si_llvm_emit_tcs_epilogue(struct lp_build_tgsi_context *bld_base)
2980 {
2981 struct si_shader_context *ctx = si_shader_context(bld_base);
2982 LLVMBuilderRef builder = ctx->ac.builder;
2983 LLVMValueRef rel_patch_id, invocation_id, tf_lds_offset;
2984
2985 si_copy_tcs_inputs(bld_base);
2986
2987 rel_patch_id = get_rel_patch_id(ctx);
2988 invocation_id = unpack_param(ctx, ctx->param_tcs_rel_ids, 8, 5);
2989 tf_lds_offset = get_tcs_out_current_patch_data_offset(ctx);
2990
2991 if (ctx->screen->b.chip_class >= GFX9) {
2992 LLVMBasicBlockRef blocks[2] = {
2993 LLVMGetInsertBlock(builder),
2994 ctx->merged_wrap_if_state.entry_block
2995 };
2996 LLVMValueRef values[2];
2997
2998 lp_build_endif(&ctx->merged_wrap_if_state);
2999
3000 values[0] = rel_patch_id;
3001 values[1] = LLVMGetUndef(ctx->i32);
3002 rel_patch_id = ac_build_phi(&ctx->ac, ctx->i32, 2, values, blocks);
3003
3004 values[0] = tf_lds_offset;
3005 values[1] = LLVMGetUndef(ctx->i32);
3006 tf_lds_offset = ac_build_phi(&ctx->ac, ctx->i32, 2, values, blocks);
3007
3008 values[0] = invocation_id;
3009 values[1] = ctx->i32_1; /* cause the epilog to skip threads */
3010 invocation_id = ac_build_phi(&ctx->ac, ctx->i32, 2, values, blocks);
3011 }
3012
3013 /* Return epilog parameters from this function. */
3014 LLVMValueRef ret = ctx->return_value;
3015 unsigned vgpr;
3016
3017 if (ctx->screen->b.chip_class >= GFX9) {
3018 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_layout,
3019 8 + GFX9_SGPR_TCS_OFFCHIP_LAYOUT);
3020 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_addr_base64k,
3021 8 + GFX9_SGPR_TCS_OFFCHIP_ADDR_BASE64K);
3022 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_factor_addr_base64k,
3023 8 + GFX9_SGPR_TCS_FACTOR_ADDR_BASE64K);
3024 /* Tess offchip and tess factor offsets are at the beginning. */
3025 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_offset, 2);
3026 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_factor_offset, 4);
3027 vgpr = 8 + GFX9_SGPR_TCS_FACTOR_ADDR_BASE64K + 1;
3028 } else {
3029 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_layout,
3030 GFX6_SGPR_TCS_OFFCHIP_LAYOUT);
3031 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_addr_base64k,
3032 GFX6_SGPR_TCS_OFFCHIP_ADDR_BASE64K);
3033 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_factor_addr_base64k,
3034 GFX6_SGPR_TCS_FACTOR_ADDR_BASE64K);
3035 /* Tess offchip and tess factor offsets are after user SGPRs. */
3036 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_offset,
3037 GFX6_TCS_NUM_USER_SGPR);
3038 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_factor_offset,
3039 GFX6_TCS_NUM_USER_SGPR + 1);
3040 vgpr = GFX6_TCS_NUM_USER_SGPR + 2;
3041 }
3042
3043 /* VGPRs */
3044 rel_patch_id = ac_to_float(&ctx->ac, rel_patch_id);
3045 invocation_id = ac_to_float(&ctx->ac, invocation_id);
3046 tf_lds_offset = ac_to_float(&ctx->ac, tf_lds_offset);
3047
3048 /* Leave a hole corresponding to the two input VGPRs. This ensures that
3049 * the invocation_id output does not alias the param_tcs_rel_ids input,
3050 * which saves a V_MOV on gfx9.
3051 */
3052 vgpr += 2;
3053
3054 ret = LLVMBuildInsertValue(builder, ret, rel_patch_id, vgpr++, "");
3055 ret = LLVMBuildInsertValue(builder, ret, invocation_id, vgpr++, "");
3056
3057 if (ctx->shader->selector->tcs_info.tessfactors_are_def_in_all_invocs) {
3058 vgpr++; /* skip the tess factor LDS offset */
3059 for (unsigned i = 0; i < 6; i++) {
3060 LLVMValueRef value =
3061 LLVMBuildLoad(builder, ctx->invoc0_tess_factors[i], "");
3062 value = ac_to_float(&ctx->ac, value);
3063 ret = LLVMBuildInsertValue(builder, ret, value, vgpr++, "");
3064 }
3065 } else {
3066 ret = LLVMBuildInsertValue(builder, ret, tf_lds_offset, vgpr++, "");
3067 }
3068 ctx->return_value = ret;
3069 }
3070
3071 /* Pass TCS inputs from LS to TCS on GFX9. */
3072 static void si_set_ls_return_value_for_tcs(struct si_shader_context *ctx)
3073 {
3074 LLVMValueRef ret = ctx->return_value;
3075
3076 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_offset, 2);
3077 ret = si_insert_input_ret(ctx, ret, ctx->param_merged_wave_info, 3);
3078 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_factor_offset, 4);
3079 ret = si_insert_input_ret(ctx, ret, ctx->param_merged_scratch_offset, 5);
3080
3081 ret = si_insert_input_ptr_as_2xi32(ctx, ret, ctx->param_rw_buffers,
3082 8 + SI_SGPR_RW_BUFFERS);
3083 ret = si_insert_input_ptr_as_2xi32(ctx, ret,
3084 ctx->param_bindless_samplers_and_images,
3085 8 + SI_SGPR_BINDLESS_SAMPLERS_AND_IMAGES);
3086
3087 ret = si_insert_input_ret(ctx, ret, ctx->param_vs_state_bits,
3088 8 + SI_SGPR_VS_STATE_BITS);
3089 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_layout,
3090 8 + GFX9_SGPR_TCS_OFFCHIP_LAYOUT);
3091 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_out_lds_offsets,
3092 8 + GFX9_SGPR_TCS_OUT_OFFSETS);
3093 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_out_lds_layout,
3094 8 + GFX9_SGPR_TCS_OUT_LAYOUT);
3095 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_addr_base64k,
3096 8 + GFX9_SGPR_TCS_OFFCHIP_ADDR_BASE64K);
3097 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_factor_addr_base64k,
3098 8 + GFX9_SGPR_TCS_FACTOR_ADDR_BASE64K);
3099
3100 unsigned desc_param = ctx->param_tcs_factor_addr_base64k + 2;
3101 ret = si_insert_input_ptr_as_2xi32(ctx, ret, desc_param,
3102 8 + GFX9_SGPR_TCS_CONST_AND_SHADER_BUFFERS);
3103 ret = si_insert_input_ptr_as_2xi32(ctx, ret, desc_param + 1,
3104 8 + GFX9_SGPR_TCS_SAMPLERS_AND_IMAGES);
3105
3106 unsigned vgpr = 8 + GFX9_TCS_NUM_USER_SGPR;
3107 ret = si_insert_input_ret_float(ctx, ret,
3108 ctx->param_tcs_patch_id, vgpr++);
3109 ret = si_insert_input_ret_float(ctx, ret,
3110 ctx->param_tcs_rel_ids, vgpr++);
3111 ctx->return_value = ret;
3112 }
3113
3114 /* Pass GS inputs from ES to GS on GFX9. */
3115 static void si_set_es_return_value_for_gs(struct si_shader_context *ctx)
3116 {
3117 LLVMValueRef ret = ctx->return_value;
3118
3119 ret = si_insert_input_ret(ctx, ret, ctx->param_gs2vs_offset, 2);
3120 ret = si_insert_input_ret(ctx, ret, ctx->param_merged_wave_info, 3);
3121 ret = si_insert_input_ret(ctx, ret, ctx->param_merged_scratch_offset, 5);
3122
3123 ret = si_insert_input_ptr_as_2xi32(ctx, ret, ctx->param_rw_buffers,
3124 8 + SI_SGPR_RW_BUFFERS);
3125 ret = si_insert_input_ptr_as_2xi32(ctx, ret,
3126 ctx->param_bindless_samplers_and_images,
3127 8 + SI_SGPR_BINDLESS_SAMPLERS_AND_IMAGES);
3128
3129 unsigned desc_param = ctx->param_vs_state_bits + 1;
3130 ret = si_insert_input_ptr_as_2xi32(ctx, ret, desc_param,
3131 8 + GFX9_SGPR_GS_CONST_AND_SHADER_BUFFERS);
3132 ret = si_insert_input_ptr_as_2xi32(ctx, ret, desc_param + 1,
3133 8 + GFX9_SGPR_GS_SAMPLERS_AND_IMAGES);
3134
3135 unsigned vgpr = 8 + GFX9_GS_NUM_USER_SGPR;
3136 for (unsigned i = 0; i < 5; i++) {
3137 unsigned param = ctx->param_gs_vtx01_offset + i;
3138 ret = si_insert_input_ret_float(ctx, ret, param, vgpr++);
3139 }
3140 ctx->return_value = ret;
3141 }
3142
3143 static void si_llvm_emit_ls_epilogue(struct lp_build_tgsi_context *bld_base)
3144 {
3145 struct si_shader_context *ctx = si_shader_context(bld_base);
3146 struct si_shader *shader = ctx->shader;
3147 struct tgsi_shader_info *info = &shader->selector->info;
3148 unsigned i, chan;
3149 LLVMValueRef vertex_id = LLVMGetParam(ctx->main_fn,
3150 ctx->param_rel_auto_id);
3151 LLVMValueRef vertex_dw_stride = get_tcs_in_vertex_dw_stride(ctx);
3152 LLVMValueRef base_dw_addr = LLVMBuildMul(ctx->ac.builder, vertex_id,
3153 vertex_dw_stride, "");
3154
3155 /* Write outputs to LDS. The next shader (TCS aka HS) will read
3156 * its inputs from it. */
3157 for (i = 0; i < info->num_outputs; i++) {
3158 LLVMValueRef *out_ptr = ctx->outputs[i];
3159 unsigned name = info->output_semantic_name[i];
3160 unsigned index = info->output_semantic_index[i];
3161
3162 /* The ARB_shader_viewport_layer_array spec contains the
3163 * following issue:
3164 *
3165 * 2) What happens if gl_ViewportIndex or gl_Layer is
3166 * written in the vertex shader and a geometry shader is
3167 * present?
3168 *
3169 * RESOLVED: The value written by the last vertex processing
3170 * stage is used. If the last vertex processing stage
3171 * (vertex, tessellation evaluation or geometry) does not
3172 * statically assign to gl_ViewportIndex or gl_Layer, index
3173 * or layer zero is assumed.
3174 *
3175 * So writes to those outputs in VS-as-LS are simply ignored.
3176 */
3177 if (name == TGSI_SEMANTIC_LAYER ||
3178 name == TGSI_SEMANTIC_VIEWPORT_INDEX)
3179 continue;
3180
3181 int param = si_shader_io_get_unique_index(name, index);
3182 LLVMValueRef dw_addr = LLVMBuildAdd(ctx->ac.builder, base_dw_addr,
3183 LLVMConstInt(ctx->i32, param * 4, 0), "");
3184
3185 for (chan = 0; chan < 4; chan++) {
3186 lds_store(bld_base, chan, dw_addr,
3187 LLVMBuildLoad(ctx->ac.builder, out_ptr[chan], ""));
3188 }
3189 }
3190
3191 if (ctx->screen->b.chip_class >= GFX9)
3192 si_set_ls_return_value_for_tcs(ctx);
3193 }
3194
3195 static void si_llvm_emit_es_epilogue(struct lp_build_tgsi_context *bld_base)
3196 {
3197 struct si_shader_context *ctx = si_shader_context(bld_base);
3198 struct si_shader *es = ctx->shader;
3199 struct tgsi_shader_info *info = &es->selector->info;
3200 LLVMValueRef soffset = LLVMGetParam(ctx->main_fn,
3201 ctx->param_es2gs_offset);
3202 LLVMValueRef lds_base = NULL;
3203 unsigned chan;
3204 int i;
3205
3206 if (ctx->screen->b.chip_class >= GFX9 && info->num_outputs) {
3207 unsigned itemsize_dw = es->selector->esgs_itemsize / 4;
3208 LLVMValueRef vertex_idx = ac_get_thread_id(&ctx->ac);
3209 LLVMValueRef wave_idx = unpack_param(ctx, ctx->param_merged_wave_info, 24, 4);
3210 vertex_idx = LLVMBuildOr(ctx->ac.builder, vertex_idx,
3211 LLVMBuildMul(ctx->ac.builder, wave_idx,
3212 LLVMConstInt(ctx->i32, 64, false), ""), "");
3213 lds_base = LLVMBuildMul(ctx->ac.builder, vertex_idx,
3214 LLVMConstInt(ctx->i32, itemsize_dw, 0), "");
3215 }
3216
3217 for (i = 0; i < info->num_outputs; i++) {
3218 LLVMValueRef *out_ptr = ctx->outputs[i];
3219 int param;
3220
3221 if (info->output_semantic_name[i] == TGSI_SEMANTIC_VIEWPORT_INDEX ||
3222 info->output_semantic_name[i] == TGSI_SEMANTIC_LAYER)
3223 continue;
3224
3225 param = si_shader_io_get_unique_index(info->output_semantic_name[i],
3226 info->output_semantic_index[i]);
3227
3228 for (chan = 0; chan < 4; chan++) {
3229 LLVMValueRef out_val = LLVMBuildLoad(ctx->ac.builder, out_ptr[chan], "");
3230 out_val = ac_to_integer(&ctx->ac, out_val);
3231
3232 /* GFX9 has the ESGS ring in LDS. */
3233 if (ctx->screen->b.chip_class >= GFX9) {
3234 lds_store(bld_base, param * 4 + chan, lds_base, out_val);
3235 continue;
3236 }
3237
3238 ac_build_buffer_store_dword(&ctx->ac,
3239 ctx->esgs_ring,
3240 out_val, 1, NULL, soffset,
3241 (4 * param + chan) * 4,
3242 1, 1, true, true);
3243 }
3244 }
3245
3246 if (ctx->screen->b.chip_class >= GFX9)
3247 si_set_es_return_value_for_gs(ctx);
3248 }
3249
3250 static LLVMValueRef si_get_gs_wave_id(struct si_shader_context *ctx)
3251 {
3252 if (ctx->screen->b.chip_class >= GFX9)
3253 return unpack_param(ctx, ctx->param_merged_wave_info, 16, 8);
3254 else
3255 return LLVMGetParam(ctx->main_fn, ctx->param_gs_wave_id);
3256 }
3257
3258 static void si_llvm_emit_gs_epilogue(struct lp_build_tgsi_context *bld_base)
3259 {
3260 struct si_shader_context *ctx = si_shader_context(bld_base);
3261
3262 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_NOP | AC_SENDMSG_GS_DONE,
3263 si_get_gs_wave_id(ctx));
3264
3265 if (ctx->screen->b.chip_class >= GFX9)
3266 lp_build_endif(&ctx->merged_wrap_if_state);
3267 }
3268
3269 static void si_llvm_emit_vs_epilogue(struct ac_shader_abi *abi,
3270 unsigned max_outputs,
3271 LLVMValueRef *addrs)
3272 {
3273 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
3274 struct tgsi_shader_info *info = &ctx->shader->selector->info;
3275 struct si_shader_output_values *outputs = NULL;
3276 int i,j;
3277
3278 assert(!ctx->shader->is_gs_copy_shader);
3279 assert(info->num_outputs <= max_outputs);
3280
3281 outputs = MALLOC((info->num_outputs + 1) * sizeof(outputs[0]));
3282
3283 /* Vertex color clamping.
3284 *
3285 * This uses a state constant loaded in a user data SGPR and
3286 * an IF statement is added that clamps all colors if the constant
3287 * is true.
3288 */
3289 if (ctx->type == PIPE_SHADER_VERTEX) {
3290 struct lp_build_if_state if_ctx;
3291 LLVMValueRef cond = NULL;
3292 LLVMValueRef addr, val;
3293
3294 for (i = 0; i < info->num_outputs; i++) {
3295 if (info->output_semantic_name[i] != TGSI_SEMANTIC_COLOR &&
3296 info->output_semantic_name[i] != TGSI_SEMANTIC_BCOLOR)
3297 continue;
3298
3299 /* We've found a color. */
3300 if (!cond) {
3301 /* The state is in the first bit of the user SGPR. */
3302 cond = LLVMGetParam(ctx->main_fn,
3303 ctx->param_vs_state_bits);
3304 cond = LLVMBuildTrunc(ctx->ac.builder, cond,
3305 ctx->i1, "");
3306 lp_build_if(&if_ctx, &ctx->gallivm, cond);
3307 }
3308
3309 for (j = 0; j < 4; j++) {
3310 addr = addrs[4 * i + j];
3311 val = LLVMBuildLoad(ctx->ac.builder, addr, "");
3312 val = ac_build_clamp(&ctx->ac, val);
3313 LLVMBuildStore(ctx->ac.builder, val, addr);
3314 }
3315 }
3316
3317 if (cond)
3318 lp_build_endif(&if_ctx);
3319 }
3320
3321 for (i = 0; i < info->num_outputs; i++) {
3322 outputs[i].semantic_name = info->output_semantic_name[i];
3323 outputs[i].semantic_index = info->output_semantic_index[i];
3324
3325 for (j = 0; j < 4; j++) {
3326 outputs[i].values[j] =
3327 LLVMBuildLoad(ctx->ac.builder,
3328 addrs[4 * i + j],
3329 "");
3330 outputs[i].vertex_stream[j] =
3331 (info->output_streams[i] >> (2 * j)) & 3;
3332 }
3333 }
3334
3335 if (ctx->shader->selector->so.num_outputs)
3336 si_llvm_emit_streamout(ctx, outputs, i, 0);
3337
3338 /* Export PrimitiveID. */
3339 if (ctx->shader->key.mono.u.vs_export_prim_id) {
3340 outputs[i].semantic_name = TGSI_SEMANTIC_PRIMID;
3341 outputs[i].semantic_index = 0;
3342 outputs[i].values[0] = ac_to_float(&ctx->ac, get_primitive_id(ctx, 0));
3343 for (j = 1; j < 4; j++)
3344 outputs[i].values[j] = LLVMConstReal(ctx->f32, 0);
3345
3346 memset(outputs[i].vertex_stream, 0,
3347 sizeof(outputs[i].vertex_stream));
3348 i++;
3349 }
3350
3351 si_llvm_export_vs(&ctx->bld_base, outputs, i);
3352 FREE(outputs);
3353 }
3354
3355 static void si_tgsi_emit_epilogue(struct lp_build_tgsi_context *bld_base)
3356 {
3357 struct si_shader_context *ctx = si_shader_context(bld_base);
3358
3359 ctx->abi.emit_outputs(&ctx->abi, RADEON_LLVM_MAX_OUTPUTS,
3360 &ctx->outputs[0][0]);
3361 }
3362
3363 struct si_ps_exports {
3364 unsigned num;
3365 struct ac_export_args args[10];
3366 };
3367
3368 unsigned si_get_spi_shader_z_format(bool writes_z, bool writes_stencil,
3369 bool writes_samplemask)
3370 {
3371 if (writes_z) {
3372 /* Z needs 32 bits. */
3373 if (writes_samplemask)
3374 return V_028710_SPI_SHADER_32_ABGR;
3375 else if (writes_stencil)
3376 return V_028710_SPI_SHADER_32_GR;
3377 else
3378 return V_028710_SPI_SHADER_32_R;
3379 } else if (writes_stencil || writes_samplemask) {
3380 /* Both stencil and sample mask need only 16 bits. */
3381 return V_028710_SPI_SHADER_UINT16_ABGR;
3382 } else {
3383 return V_028710_SPI_SHADER_ZERO;
3384 }
3385 }
3386
3387 static void si_export_mrt_z(struct lp_build_tgsi_context *bld_base,
3388 LLVMValueRef depth, LLVMValueRef stencil,
3389 LLVMValueRef samplemask, struct si_ps_exports *exp)
3390 {
3391 struct si_shader_context *ctx = si_shader_context(bld_base);
3392 struct lp_build_context *base = &bld_base->base;
3393 struct ac_export_args args;
3394 unsigned mask = 0;
3395 unsigned format = si_get_spi_shader_z_format(depth != NULL,
3396 stencil != NULL,
3397 samplemask != NULL);
3398
3399 assert(depth || stencil || samplemask);
3400
3401 args.valid_mask = 1; /* whether the EXEC mask is valid */
3402 args.done = 1; /* DONE bit */
3403
3404 /* Specify the target we are exporting */
3405 args.target = V_008DFC_SQ_EXP_MRTZ;
3406
3407 args.compr = 0; /* COMP flag */
3408 args.out[0] = base->undef; /* R, depth */
3409 args.out[1] = base->undef; /* G, stencil test value[0:7], stencil op value[8:15] */
3410 args.out[2] = base->undef; /* B, sample mask */
3411 args.out[3] = base->undef; /* A, alpha to mask */
3412
3413 if (format == V_028710_SPI_SHADER_UINT16_ABGR) {
3414 assert(!depth);
3415 args.compr = 1; /* COMPR flag */
3416
3417 if (stencil) {
3418 /* Stencil should be in X[23:16]. */
3419 stencil = ac_to_integer(&ctx->ac, stencil);
3420 stencil = LLVMBuildShl(ctx->ac.builder, stencil,
3421 LLVMConstInt(ctx->i32, 16, 0), "");
3422 args.out[0] = ac_to_float(&ctx->ac, stencil);
3423 mask |= 0x3;
3424 }
3425 if (samplemask) {
3426 /* SampleMask should be in Y[15:0]. */
3427 args.out[1] = samplemask;
3428 mask |= 0xc;
3429 }
3430 } else {
3431 if (depth) {
3432 args.out[0] = depth;
3433 mask |= 0x1;
3434 }
3435 if (stencil) {
3436 args.out[1] = stencil;
3437 mask |= 0x2;
3438 }
3439 if (samplemask) {
3440 args.out[2] = samplemask;
3441 mask |= 0x4;
3442 }
3443 }
3444
3445 /* SI (except OLAND and HAINAN) has a bug that it only looks
3446 * at the X writemask component. */
3447 if (ctx->screen->b.chip_class == SI &&
3448 ctx->screen->b.family != CHIP_OLAND &&
3449 ctx->screen->b.family != CHIP_HAINAN)
3450 mask |= 0x1;
3451
3452 /* Specify which components to enable */
3453 args.enabled_channels = mask;
3454
3455 memcpy(&exp->args[exp->num++], &args, sizeof(args));
3456 }
3457
3458 static void si_export_mrt_color(struct lp_build_tgsi_context *bld_base,
3459 LLVMValueRef *color, unsigned index,
3460 unsigned samplemask_param,
3461 bool is_last, struct si_ps_exports *exp)
3462 {
3463 struct si_shader_context *ctx = si_shader_context(bld_base);
3464 int i;
3465
3466 /* Clamp color */
3467 if (ctx->shader->key.part.ps.epilog.clamp_color)
3468 for (i = 0; i < 4; i++)
3469 color[i] = ac_build_clamp(&ctx->ac, color[i]);
3470
3471 /* Alpha to one */
3472 if (ctx->shader->key.part.ps.epilog.alpha_to_one)
3473 color[3] = ctx->ac.f32_1;
3474
3475 /* Alpha test */
3476 if (index == 0 &&
3477 ctx->shader->key.part.ps.epilog.alpha_func != PIPE_FUNC_ALWAYS)
3478 si_alpha_test(bld_base, color[3]);
3479
3480 /* Line & polygon smoothing */
3481 if (ctx->shader->key.part.ps.epilog.poly_line_smoothing)
3482 color[3] = si_scale_alpha_by_sample_mask(bld_base, color[3],
3483 samplemask_param);
3484
3485 /* If last_cbuf > 0, FS_COLOR0_WRITES_ALL_CBUFS is true. */
3486 if (ctx->shader->key.part.ps.epilog.last_cbuf > 0) {
3487 struct ac_export_args args[8];
3488 int c, last = -1;
3489
3490 /* Get the export arguments, also find out what the last one is. */
3491 for (c = 0; c <= ctx->shader->key.part.ps.epilog.last_cbuf; c++) {
3492 si_llvm_init_export_args(bld_base, color,
3493 V_008DFC_SQ_EXP_MRT + c, &args[c]);
3494 if (args[c].enabled_channels)
3495 last = c;
3496 }
3497
3498 /* Emit all exports. */
3499 for (c = 0; c <= ctx->shader->key.part.ps.epilog.last_cbuf; c++) {
3500 if (is_last && last == c) {
3501 args[c].valid_mask = 1; /* whether the EXEC mask is valid */
3502 args[c].done = 1; /* DONE bit */
3503 } else if (!args[c].enabled_channels)
3504 continue; /* unnecessary NULL export */
3505
3506 memcpy(&exp->args[exp->num++], &args[c], sizeof(args[c]));
3507 }
3508 } else {
3509 struct ac_export_args args;
3510
3511 /* Export */
3512 si_llvm_init_export_args(bld_base, color, V_008DFC_SQ_EXP_MRT + index,
3513 &args);
3514 if (is_last) {
3515 args.valid_mask = 1; /* whether the EXEC mask is valid */
3516 args.done = 1; /* DONE bit */
3517 } else if (!args.enabled_channels)
3518 return; /* unnecessary NULL export */
3519
3520 memcpy(&exp->args[exp->num++], &args, sizeof(args));
3521 }
3522 }
3523
3524 static void si_emit_ps_exports(struct si_shader_context *ctx,
3525 struct si_ps_exports *exp)
3526 {
3527 for (unsigned i = 0; i < exp->num; i++)
3528 ac_build_export(&ctx->ac, &exp->args[i]);
3529 }
3530
3531 static void si_export_null(struct lp_build_tgsi_context *bld_base)
3532 {
3533 struct si_shader_context *ctx = si_shader_context(bld_base);
3534 struct lp_build_context *base = &bld_base->base;
3535 struct ac_export_args args;
3536
3537 args.enabled_channels = 0x0; /* enabled channels */
3538 args.valid_mask = 1; /* whether the EXEC mask is valid */
3539 args.done = 1; /* DONE bit */
3540 args.target = V_008DFC_SQ_EXP_NULL;
3541 args.compr = 0; /* COMPR flag (0 = 32-bit export) */
3542 args.out[0] = base->undef; /* R */
3543 args.out[1] = base->undef; /* G */
3544 args.out[2] = base->undef; /* B */
3545 args.out[3] = base->undef; /* A */
3546
3547 ac_build_export(&ctx->ac, &args);
3548 }
3549
3550 /**
3551 * Return PS outputs in this order:
3552 *
3553 * v[0:3] = color0.xyzw
3554 * v[4:7] = color1.xyzw
3555 * ...
3556 * vN+0 = Depth
3557 * vN+1 = Stencil
3558 * vN+2 = SampleMask
3559 * vN+3 = SampleMaskIn (used for OpenGL smoothing)
3560 *
3561 * The alpha-ref SGPR is returned via its original location.
3562 */
3563 static void si_llvm_return_fs_outputs(struct ac_shader_abi *abi,
3564 unsigned max_outputs,
3565 LLVMValueRef *addrs)
3566 {
3567 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
3568 struct si_shader *shader = ctx->shader;
3569 struct tgsi_shader_info *info = &shader->selector->info;
3570 LLVMBuilderRef builder = ctx->ac.builder;
3571 unsigned i, j, first_vgpr, vgpr;
3572
3573 LLVMValueRef color[8][4] = {};
3574 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
3575 LLVMValueRef ret;
3576
3577 if (ctx->postponed_kill)
3578 ac_build_kill_if_false(&ctx->ac, LLVMBuildLoad(builder, ctx->postponed_kill, ""));
3579
3580 /* Read the output values. */
3581 for (i = 0; i < info->num_outputs; i++) {
3582 unsigned semantic_name = info->output_semantic_name[i];
3583 unsigned semantic_index = info->output_semantic_index[i];
3584
3585 switch (semantic_name) {
3586 case TGSI_SEMANTIC_COLOR:
3587 assert(semantic_index < 8);
3588 for (j = 0; j < 4; j++) {
3589 LLVMValueRef ptr = addrs[4 * i + j];
3590 LLVMValueRef result = LLVMBuildLoad(builder, ptr, "");
3591 color[semantic_index][j] = result;
3592 }
3593 break;
3594 case TGSI_SEMANTIC_POSITION:
3595 depth = LLVMBuildLoad(builder,
3596 addrs[4 * i + 2], "");
3597 break;
3598 case TGSI_SEMANTIC_STENCIL:
3599 stencil = LLVMBuildLoad(builder,
3600 addrs[4 * i + 1], "");
3601 break;
3602 case TGSI_SEMANTIC_SAMPLEMASK:
3603 samplemask = LLVMBuildLoad(builder,
3604 addrs[4 * i + 0], "");
3605 break;
3606 default:
3607 fprintf(stderr, "Warning: SI unhandled fs output type:%d\n",
3608 semantic_name);
3609 }
3610 }
3611
3612 /* Fill the return structure. */
3613 ret = ctx->return_value;
3614
3615 /* Set SGPRs. */
3616 ret = LLVMBuildInsertValue(builder, ret,
3617 ac_to_integer(&ctx->ac,
3618 LLVMGetParam(ctx->main_fn,
3619 SI_PARAM_ALPHA_REF)),
3620 SI_SGPR_ALPHA_REF, "");
3621
3622 /* Set VGPRs */
3623 first_vgpr = vgpr = SI_SGPR_ALPHA_REF + 1;
3624 for (i = 0; i < ARRAY_SIZE(color); i++) {
3625 if (!color[i][0])
3626 continue;
3627
3628 for (j = 0; j < 4; j++)
3629 ret = LLVMBuildInsertValue(builder, ret, color[i][j], vgpr++, "");
3630 }
3631 if (depth)
3632 ret = LLVMBuildInsertValue(builder, ret, depth, vgpr++, "");
3633 if (stencil)
3634 ret = LLVMBuildInsertValue(builder, ret, stencil, vgpr++, "");
3635 if (samplemask)
3636 ret = LLVMBuildInsertValue(builder, ret, samplemask, vgpr++, "");
3637
3638 /* Add the input sample mask for smoothing at the end. */
3639 if (vgpr < first_vgpr + PS_EPILOG_SAMPLEMASK_MIN_LOC)
3640 vgpr = first_vgpr + PS_EPILOG_SAMPLEMASK_MIN_LOC;
3641 ret = LLVMBuildInsertValue(builder, ret,
3642 LLVMGetParam(ctx->main_fn,
3643 SI_PARAM_SAMPLE_COVERAGE), vgpr++, "");
3644
3645 ctx->return_value = ret;
3646 }
3647
3648 void si_emit_waitcnt(struct si_shader_context *ctx, unsigned simm16)
3649 {
3650 LLVMValueRef args[1] = {
3651 LLVMConstInt(ctx->i32, simm16, 0)
3652 };
3653 lp_build_intrinsic(ctx->ac.builder, "llvm.amdgcn.s.waitcnt",
3654 ctx->voidt, args, 1, 0);
3655 }
3656
3657 static void membar_emit(
3658 const struct lp_build_tgsi_action *action,
3659 struct lp_build_tgsi_context *bld_base,
3660 struct lp_build_emit_data *emit_data)
3661 {
3662 struct si_shader_context *ctx = si_shader_context(bld_base);
3663 LLVMValueRef src0 = lp_build_emit_fetch(bld_base, emit_data->inst, 0, 0);
3664 unsigned flags = LLVMConstIntGetZExtValue(src0);
3665 unsigned waitcnt = NOOP_WAITCNT;
3666
3667 if (flags & TGSI_MEMBAR_THREAD_GROUP)
3668 waitcnt &= VM_CNT & LGKM_CNT;
3669
3670 if (flags & (TGSI_MEMBAR_ATOMIC_BUFFER |
3671 TGSI_MEMBAR_SHADER_BUFFER |
3672 TGSI_MEMBAR_SHADER_IMAGE))
3673 waitcnt &= VM_CNT;
3674
3675 if (flags & TGSI_MEMBAR_SHARED)
3676 waitcnt &= LGKM_CNT;
3677
3678 if (waitcnt != NOOP_WAITCNT)
3679 si_emit_waitcnt(ctx, waitcnt);
3680 }
3681
3682 static void clock_emit(
3683 const struct lp_build_tgsi_action *action,
3684 struct lp_build_tgsi_context *bld_base,
3685 struct lp_build_emit_data *emit_data)
3686 {
3687 struct si_shader_context *ctx = si_shader_context(bld_base);
3688 LLVMValueRef tmp;
3689
3690 tmp = lp_build_intrinsic(ctx->ac.builder, "llvm.readcyclecounter",
3691 ctx->i64, NULL, 0, 0);
3692 tmp = LLVMBuildBitCast(ctx->ac.builder, tmp, ctx->v2i32, "");
3693
3694 emit_data->output[0] =
3695 LLVMBuildExtractElement(ctx->ac.builder, tmp, ctx->i32_0, "");
3696 emit_data->output[1] =
3697 LLVMBuildExtractElement(ctx->ac.builder, tmp, ctx->i32_1, "");
3698 }
3699
3700 LLVMTypeRef si_const_array(LLVMTypeRef elem_type, int num_elements)
3701 {
3702 return LLVMPointerType(LLVMArrayType(elem_type, num_elements),
3703 CONST_ADDR_SPACE);
3704 }
3705
3706 static void si_llvm_emit_ddxy(
3707 const struct lp_build_tgsi_action *action,
3708 struct lp_build_tgsi_context *bld_base,
3709 struct lp_build_emit_data *emit_data)
3710 {
3711 struct si_shader_context *ctx = si_shader_context(bld_base);
3712 unsigned opcode = emit_data->info->opcode;
3713 LLVMValueRef val;
3714 int idx;
3715 unsigned mask;
3716
3717 if (opcode == TGSI_OPCODE_DDX_FINE)
3718 mask = AC_TID_MASK_LEFT;
3719 else if (opcode == TGSI_OPCODE_DDY_FINE)
3720 mask = AC_TID_MASK_TOP;
3721 else
3722 mask = AC_TID_MASK_TOP_LEFT;
3723
3724 /* for DDX we want to next X pixel, DDY next Y pixel. */
3725 idx = (opcode == TGSI_OPCODE_DDX || opcode == TGSI_OPCODE_DDX_FINE) ? 1 : 2;
3726
3727 val = ac_to_integer(&ctx->ac, emit_data->args[0]);
3728 val = ac_build_ddxy(&ctx->ac, mask, idx, val);
3729 emit_data->output[emit_data->chan] = val;
3730 }
3731
3732 /*
3733 * this takes an I,J coordinate pair,
3734 * and works out the X and Y derivatives.
3735 * it returns DDX(I), DDX(J), DDY(I), DDY(J).
3736 */
3737 static LLVMValueRef si_llvm_emit_ddxy_interp(
3738 struct lp_build_tgsi_context *bld_base,
3739 LLVMValueRef interp_ij)
3740 {
3741 struct si_shader_context *ctx = si_shader_context(bld_base);
3742 LLVMValueRef result[4], a;
3743 unsigned i;
3744
3745 for (i = 0; i < 2; i++) {
3746 a = LLVMBuildExtractElement(ctx->ac.builder, interp_ij,
3747 LLVMConstInt(ctx->i32, i, 0), "");
3748 result[i] = lp_build_emit_llvm_unary(bld_base, TGSI_OPCODE_DDX, a);
3749 result[2+i] = lp_build_emit_llvm_unary(bld_base, TGSI_OPCODE_DDY, a);
3750 }
3751
3752 return lp_build_gather_values(&ctx->gallivm, result, 4);
3753 }
3754
3755 static void interp_fetch_args(
3756 struct lp_build_tgsi_context *bld_base,
3757 struct lp_build_emit_data *emit_data)
3758 {
3759 struct si_shader_context *ctx = si_shader_context(bld_base);
3760 const struct tgsi_full_instruction *inst = emit_data->inst;
3761
3762 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET) {
3763 /* offset is in second src, first two channels */
3764 emit_data->args[0] = lp_build_emit_fetch(bld_base,
3765 emit_data->inst, 1,
3766 TGSI_CHAN_X);
3767 emit_data->args[1] = lp_build_emit_fetch(bld_base,
3768 emit_data->inst, 1,
3769 TGSI_CHAN_Y);
3770 emit_data->arg_count = 2;
3771 } else if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
3772 LLVMValueRef sample_position;
3773 LLVMValueRef sample_id;
3774 LLVMValueRef halfval = LLVMConstReal(ctx->f32, 0.5f);
3775
3776 /* fetch sample ID, then fetch its sample position,
3777 * and place into first two channels.
3778 */
3779 sample_id = lp_build_emit_fetch(bld_base,
3780 emit_data->inst, 1, TGSI_CHAN_X);
3781 sample_id = ac_to_integer(&ctx->ac, sample_id);
3782
3783 /* Section 8.13.2 (Interpolation Functions) of the OpenGL Shading
3784 * Language 4.50 spec says about interpolateAtSample:
3785 *
3786 * "Returns the value of the input interpolant variable at
3787 * the location of sample number sample. If multisample
3788 * buffers are not available, the input variable will be
3789 * evaluated at the center of the pixel. If sample sample
3790 * does not exist, the position used to interpolate the
3791 * input variable is undefined."
3792 *
3793 * This means that sample_id values outside of the valid are
3794 * in fact valid input, and the usual mechanism for loading the
3795 * sample position doesn't work.
3796 */
3797 if (ctx->shader->key.mono.u.ps.interpolate_at_sample_force_center) {
3798 LLVMValueRef center[4] = {
3799 LLVMConstReal(ctx->f32, 0.5),
3800 LLVMConstReal(ctx->f32, 0.5),
3801 ctx->ac.f32_0,
3802 ctx->ac.f32_0,
3803 };
3804
3805 sample_position = lp_build_gather_values(&ctx->gallivm, center, 4);
3806 } else {
3807 sample_position = load_sample_position(ctx, sample_id);
3808 }
3809
3810 emit_data->args[0] = LLVMBuildExtractElement(ctx->ac.builder,
3811 sample_position,
3812 ctx->i32_0, "");
3813
3814 emit_data->args[0] = LLVMBuildFSub(ctx->ac.builder, emit_data->args[0], halfval, "");
3815 emit_data->args[1] = LLVMBuildExtractElement(ctx->ac.builder,
3816 sample_position,
3817 ctx->i32_1, "");
3818 emit_data->args[1] = LLVMBuildFSub(ctx->ac.builder, emit_data->args[1], halfval, "");
3819 emit_data->arg_count = 2;
3820 }
3821 }
3822
3823 static void build_interp_intrinsic(const struct lp_build_tgsi_action *action,
3824 struct lp_build_tgsi_context *bld_base,
3825 struct lp_build_emit_data *emit_data)
3826 {
3827 struct si_shader_context *ctx = si_shader_context(bld_base);
3828 struct si_shader *shader = ctx->shader;
3829 const struct tgsi_shader_info *info = &shader->selector->info;
3830 LLVMValueRef interp_param;
3831 const struct tgsi_full_instruction *inst = emit_data->inst;
3832 const struct tgsi_full_src_register *input = &inst->Src[0];
3833 int input_base, input_array_size;
3834 int chan;
3835 int i;
3836 LLVMValueRef prim_mask = LLVMGetParam(ctx->main_fn, SI_PARAM_PRIM_MASK);
3837 LLVMValueRef array_idx;
3838 int interp_param_idx;
3839 unsigned interp;
3840 unsigned location;
3841
3842 assert(input->Register.File == TGSI_FILE_INPUT);
3843
3844 if (input->Register.Indirect) {
3845 unsigned array_id = input->Indirect.ArrayID;
3846
3847 if (array_id) {
3848 input_base = info->input_array_first[array_id];
3849 input_array_size = info->input_array_last[array_id] - input_base + 1;
3850 } else {
3851 input_base = inst->Src[0].Register.Index;
3852 input_array_size = info->num_inputs - input_base;
3853 }
3854
3855 array_idx = si_get_indirect_index(ctx, &input->Indirect,
3856 1, input->Register.Index - input_base);
3857 } else {
3858 input_base = inst->Src[0].Register.Index;
3859 input_array_size = 1;
3860 array_idx = ctx->i32_0;
3861 }
3862
3863 interp = shader->selector->info.input_interpolate[input_base];
3864
3865 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
3866 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE)
3867 location = TGSI_INTERPOLATE_LOC_CENTER;
3868 else
3869 location = TGSI_INTERPOLATE_LOC_CENTROID;
3870
3871 interp_param_idx = lookup_interp_param_index(interp, location);
3872 if (interp_param_idx == -1)
3873 return;
3874 else if (interp_param_idx)
3875 interp_param = LLVMGetParam(ctx->main_fn, interp_param_idx);
3876 else
3877 interp_param = NULL;
3878
3879 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
3880 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
3881 LLVMValueRef ij_out[2];
3882 LLVMValueRef ddxy_out = si_llvm_emit_ddxy_interp(bld_base, interp_param);
3883
3884 /*
3885 * take the I then J parameters, and the DDX/Y for it, and
3886 * calculate the IJ inputs for the interpolator.
3887 * temp1 = ddx * offset/sample.x + I;
3888 * interp_param.I = ddy * offset/sample.y + temp1;
3889 * temp1 = ddx * offset/sample.x + J;
3890 * interp_param.J = ddy * offset/sample.y + temp1;
3891 */
3892 for (i = 0; i < 2; i++) {
3893 LLVMValueRef ix_ll = LLVMConstInt(ctx->i32, i, 0);
3894 LLVMValueRef iy_ll = LLVMConstInt(ctx->i32, i + 2, 0);
3895 LLVMValueRef ddx_el = LLVMBuildExtractElement(ctx->ac.builder,
3896 ddxy_out, ix_ll, "");
3897 LLVMValueRef ddy_el = LLVMBuildExtractElement(ctx->ac.builder,
3898 ddxy_out, iy_ll, "");
3899 LLVMValueRef interp_el = LLVMBuildExtractElement(ctx->ac.builder,
3900 interp_param, ix_ll, "");
3901 LLVMValueRef temp1, temp2;
3902
3903 interp_el = ac_to_float(&ctx->ac, interp_el);
3904
3905 temp1 = LLVMBuildFMul(ctx->ac.builder, ddx_el, emit_data->args[0], "");
3906
3907 temp1 = LLVMBuildFAdd(ctx->ac.builder, temp1, interp_el, "");
3908
3909 temp2 = LLVMBuildFMul(ctx->ac.builder, ddy_el, emit_data->args[1], "");
3910
3911 ij_out[i] = LLVMBuildFAdd(ctx->ac.builder, temp2, temp1, "");
3912 }
3913 interp_param = lp_build_gather_values(&ctx->gallivm, ij_out, 2);
3914 }
3915
3916 if (interp_param)
3917 interp_param = ac_to_float(&ctx->ac, interp_param);
3918
3919 for (chan = 0; chan < 4; chan++) {
3920 LLVMValueRef gather = LLVMGetUndef(LLVMVectorType(ctx->f32, input_array_size));
3921 unsigned schan = tgsi_util_get_full_src_register_swizzle(&inst->Src[0], chan);
3922
3923 for (unsigned idx = 0; idx < input_array_size; ++idx) {
3924 LLVMValueRef v, i = NULL, j = NULL;
3925
3926 if (interp_param) {
3927 i = LLVMBuildExtractElement(
3928 ctx->ac.builder, interp_param, ctx->i32_0, "");
3929 j = LLVMBuildExtractElement(
3930 ctx->ac.builder, interp_param, ctx->i32_1, "");
3931 }
3932 v = si_build_fs_interp(ctx, input_base + idx, schan,
3933 prim_mask, i, j);
3934
3935 gather = LLVMBuildInsertElement(ctx->ac.builder,
3936 gather, v, LLVMConstInt(ctx->i32, idx, false), "");
3937 }
3938
3939 emit_data->output[chan] = LLVMBuildExtractElement(
3940 ctx->ac.builder, gather, array_idx, "");
3941 }
3942 }
3943
3944 static void vote_all_emit(
3945 const struct lp_build_tgsi_action *action,
3946 struct lp_build_tgsi_context *bld_base,
3947 struct lp_build_emit_data *emit_data)
3948 {
3949 struct si_shader_context *ctx = si_shader_context(bld_base);
3950
3951 LLVMValueRef tmp = ac_build_vote_all(&ctx->ac, emit_data->args[0]);
3952 emit_data->output[emit_data->chan] =
3953 LLVMBuildSExt(ctx->ac.builder, tmp, ctx->i32, "");
3954 }
3955
3956 static void vote_any_emit(
3957 const struct lp_build_tgsi_action *action,
3958 struct lp_build_tgsi_context *bld_base,
3959 struct lp_build_emit_data *emit_data)
3960 {
3961 struct si_shader_context *ctx = si_shader_context(bld_base);
3962
3963 LLVMValueRef tmp = ac_build_vote_any(&ctx->ac, emit_data->args[0]);
3964 emit_data->output[emit_data->chan] =
3965 LLVMBuildSExt(ctx->ac.builder, tmp, ctx->i32, "");
3966 }
3967
3968 static void vote_eq_emit(
3969 const struct lp_build_tgsi_action *action,
3970 struct lp_build_tgsi_context *bld_base,
3971 struct lp_build_emit_data *emit_data)
3972 {
3973 struct si_shader_context *ctx = si_shader_context(bld_base);
3974
3975 LLVMValueRef tmp = ac_build_vote_eq(&ctx->ac, emit_data->args[0]);
3976 emit_data->output[emit_data->chan] =
3977 LLVMBuildSExt(ctx->ac.builder, tmp, ctx->i32, "");
3978 }
3979
3980 static void ballot_emit(
3981 const struct lp_build_tgsi_action *action,
3982 struct lp_build_tgsi_context *bld_base,
3983 struct lp_build_emit_data *emit_data)
3984 {
3985 struct si_shader_context *ctx = si_shader_context(bld_base);
3986 LLVMBuilderRef builder = ctx->ac.builder;
3987 LLVMValueRef tmp;
3988
3989 tmp = lp_build_emit_fetch(bld_base, emit_data->inst, 0, TGSI_CHAN_X);
3990 tmp = ac_build_ballot(&ctx->ac, tmp);
3991 tmp = LLVMBuildBitCast(builder, tmp, ctx->v2i32, "");
3992
3993 emit_data->output[0] = LLVMBuildExtractElement(builder, tmp, ctx->i32_0, "");
3994 emit_data->output[1] = LLVMBuildExtractElement(builder, tmp, ctx->i32_1, "");
3995 }
3996
3997 static void read_invoc_fetch_args(
3998 struct lp_build_tgsi_context *bld_base,
3999 struct lp_build_emit_data *emit_data)
4000 {
4001 emit_data->args[0] = lp_build_emit_fetch(bld_base, emit_data->inst,
4002 0, emit_data->src_chan);
4003
4004 /* Always read the source invocation (= lane) from the X channel. */
4005 emit_data->args[1] = lp_build_emit_fetch(bld_base, emit_data->inst,
4006 1, TGSI_CHAN_X);
4007 emit_data->arg_count = 2;
4008 }
4009
4010 static void read_lane_emit(
4011 const struct lp_build_tgsi_action *action,
4012 struct lp_build_tgsi_context *bld_base,
4013 struct lp_build_emit_data *emit_data)
4014 {
4015 struct si_shader_context *ctx = si_shader_context(bld_base);
4016
4017 /* We currently have no other way to prevent LLVM from lifting the icmp
4018 * calls to a dominating basic block.
4019 */
4020 ac_build_optimization_barrier(&ctx->ac, &emit_data->args[0]);
4021
4022 for (unsigned i = 0; i < emit_data->arg_count; ++i)
4023 emit_data->args[i] = ac_to_integer(&ctx->ac, emit_data->args[i]);
4024
4025 emit_data->output[emit_data->chan] =
4026 ac_build_intrinsic(&ctx->ac, action->intr_name,
4027 ctx->i32, emit_data->args, emit_data->arg_count,
4028 AC_FUNC_ATTR_READNONE |
4029 AC_FUNC_ATTR_CONVERGENT);
4030 }
4031
4032 static unsigned si_llvm_get_stream(struct lp_build_tgsi_context *bld_base,
4033 struct lp_build_emit_data *emit_data)
4034 {
4035 struct si_shader_context *ctx = si_shader_context(bld_base);
4036 struct tgsi_src_register src0 = emit_data->inst->Src[0].Register;
4037 LLVMValueRef imm;
4038 unsigned stream;
4039
4040 assert(src0.File == TGSI_FILE_IMMEDIATE);
4041
4042 imm = ctx->imms[src0.Index * TGSI_NUM_CHANNELS + src0.SwizzleX];
4043 stream = LLVMConstIntGetZExtValue(imm) & 0x3;
4044 return stream;
4045 }
4046
4047 /* Emit one vertex from the geometry shader */
4048 static void si_llvm_emit_vertex(
4049 const struct lp_build_tgsi_action *action,
4050 struct lp_build_tgsi_context *bld_base,
4051 struct lp_build_emit_data *emit_data)
4052 {
4053 struct si_shader_context *ctx = si_shader_context(bld_base);
4054 struct lp_build_context *uint = &bld_base->uint_bld;
4055 struct si_shader *shader = ctx->shader;
4056 struct tgsi_shader_info *info = &shader->selector->info;
4057 struct lp_build_if_state if_state;
4058 LLVMValueRef soffset = LLVMGetParam(ctx->main_fn,
4059 ctx->param_gs2vs_offset);
4060 LLVMValueRef gs_next_vertex;
4061 LLVMValueRef can_emit;
4062 unsigned chan, offset;
4063 int i;
4064 unsigned stream;
4065
4066 stream = si_llvm_get_stream(bld_base, emit_data);
4067
4068 /* Write vertex attribute values to GSVS ring */
4069 gs_next_vertex = LLVMBuildLoad(ctx->ac.builder,
4070 ctx->gs_next_vertex[stream],
4071 "");
4072
4073 /* If this thread has already emitted the declared maximum number of
4074 * vertices, skip the write: excessive vertex emissions are not
4075 * supposed to have any effect.
4076 *
4077 * If the shader has no writes to memory, kill it instead. This skips
4078 * further memory loads and may allow LLVM to skip to the end
4079 * altogether.
4080 */
4081 can_emit = LLVMBuildICmp(ctx->ac.builder, LLVMIntULT, gs_next_vertex,
4082 LLVMConstInt(ctx->i32,
4083 shader->selector->gs_max_out_vertices, 0), "");
4084
4085 bool use_kill = !info->writes_memory;
4086 if (use_kill) {
4087 ac_build_kill_if_false(&ctx->ac, can_emit);
4088 } else {
4089 lp_build_if(&if_state, &ctx->gallivm, can_emit);
4090 }
4091
4092 offset = 0;
4093 for (i = 0; i < info->num_outputs; i++) {
4094 LLVMValueRef *out_ptr = ctx->outputs[i];
4095
4096 for (chan = 0; chan < 4; chan++) {
4097 if (!(info->output_usagemask[i] & (1 << chan)) ||
4098 ((info->output_streams[i] >> (2 * chan)) & 3) != stream)
4099 continue;
4100
4101 LLVMValueRef out_val = LLVMBuildLoad(ctx->ac.builder, out_ptr[chan], "");
4102 LLVMValueRef voffset =
4103 LLVMConstInt(ctx->i32, offset *
4104 shader->selector->gs_max_out_vertices, 0);
4105 offset++;
4106
4107 voffset = lp_build_add(uint, voffset, gs_next_vertex);
4108 voffset = lp_build_mul_imm(uint, voffset, 4);
4109
4110 out_val = ac_to_integer(&ctx->ac, out_val);
4111
4112 ac_build_buffer_store_dword(&ctx->ac,
4113 ctx->gsvs_ring[stream],
4114 out_val, 1,
4115 voffset, soffset, 0,
4116 1, 1, true, true);
4117 }
4118 }
4119
4120 gs_next_vertex = lp_build_add(uint, gs_next_vertex,
4121 ctx->i32_1);
4122
4123 LLVMBuildStore(ctx->ac.builder, gs_next_vertex, ctx->gs_next_vertex[stream]);
4124
4125 /* Signal vertex emission */
4126 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_EMIT | AC_SENDMSG_GS | (stream << 8),
4127 si_get_gs_wave_id(ctx));
4128 if (!use_kill)
4129 lp_build_endif(&if_state);
4130 }
4131
4132 /* Cut one primitive from the geometry shader */
4133 static void si_llvm_emit_primitive(
4134 const struct lp_build_tgsi_action *action,
4135 struct lp_build_tgsi_context *bld_base,
4136 struct lp_build_emit_data *emit_data)
4137 {
4138 struct si_shader_context *ctx = si_shader_context(bld_base);
4139 unsigned stream;
4140
4141 /* Signal primitive cut */
4142 stream = si_llvm_get_stream(bld_base, emit_data);
4143 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_CUT | AC_SENDMSG_GS | (stream << 8),
4144 si_get_gs_wave_id(ctx));
4145 }
4146
4147 static void si_llvm_emit_barrier(const struct lp_build_tgsi_action *action,
4148 struct lp_build_tgsi_context *bld_base,
4149 struct lp_build_emit_data *emit_data)
4150 {
4151 struct si_shader_context *ctx = si_shader_context(bld_base);
4152
4153 /* SI only (thanks to a hw bug workaround):
4154 * The real barrier instruction isn’t needed, because an entire patch
4155 * always fits into a single wave.
4156 */
4157 if (ctx->screen->b.chip_class == SI &&
4158 ctx->type == PIPE_SHADER_TESS_CTRL) {
4159 si_emit_waitcnt(ctx, LGKM_CNT & VM_CNT);
4160 return;
4161 }
4162
4163 lp_build_intrinsic(ctx->ac.builder,
4164 "llvm.amdgcn.s.barrier",
4165 ctx->voidt, NULL, 0, LP_FUNC_ATTR_CONVERGENT);
4166 }
4167
4168 static const struct lp_build_tgsi_action interp_action = {
4169 .fetch_args = interp_fetch_args,
4170 .emit = build_interp_intrinsic,
4171 };
4172
4173 static void si_create_function(struct si_shader_context *ctx,
4174 const char *name,
4175 LLVMTypeRef *returns, unsigned num_returns,
4176 struct si_function_info *fninfo,
4177 unsigned max_workgroup_size)
4178 {
4179 int i;
4180
4181 si_llvm_create_func(ctx, name, returns, num_returns,
4182 fninfo->types, fninfo->num_params);
4183 ctx->return_value = LLVMGetUndef(ctx->return_type);
4184
4185 for (i = 0; i < fninfo->num_sgpr_params; ++i) {
4186 LLVMValueRef P = LLVMGetParam(ctx->main_fn, i);
4187
4188 /* The combination of:
4189 * - ByVal
4190 * - dereferenceable
4191 * - invariant.load
4192 * allows the optimization passes to move loads and reduces
4193 * SGPR spilling significantly.
4194 */
4195 if (LLVMGetTypeKind(LLVMTypeOf(P)) == LLVMPointerTypeKind) {
4196 lp_add_function_attr(ctx->main_fn, i + 1, LP_FUNC_ATTR_BYVAL);
4197 lp_add_function_attr(ctx->main_fn, i + 1, LP_FUNC_ATTR_NOALIAS);
4198 ac_add_attr_dereferenceable(P, UINT64_MAX);
4199 } else
4200 lp_add_function_attr(ctx->main_fn, i + 1, LP_FUNC_ATTR_INREG);
4201 }
4202
4203 for (i = 0; i < fninfo->num_params; ++i) {
4204 if (fninfo->assign[i])
4205 *fninfo->assign[i] = LLVMGetParam(ctx->main_fn, i);
4206 }
4207
4208 if (max_workgroup_size) {
4209 si_llvm_add_attribute(ctx->main_fn, "amdgpu-max-work-group-size",
4210 max_workgroup_size);
4211 }
4212 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
4213 "no-signed-zeros-fp-math",
4214 "true");
4215
4216 if (ctx->screen->b.debug_flags & DBG(UNSAFE_MATH)) {
4217 /* These were copied from some LLVM test. */
4218 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
4219 "less-precise-fpmad",
4220 "true");
4221 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
4222 "no-infs-fp-math",
4223 "true");
4224 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
4225 "no-nans-fp-math",
4226 "true");
4227 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
4228 "unsafe-fp-math",
4229 "true");
4230 }
4231 }
4232
4233 static void declare_streamout_params(struct si_shader_context *ctx,
4234 struct pipe_stream_output_info *so,
4235 struct si_function_info *fninfo)
4236 {
4237 int i;
4238
4239 /* Streamout SGPRs. */
4240 if (so->num_outputs) {
4241 if (ctx->type != PIPE_SHADER_TESS_EVAL)
4242 ctx->param_streamout_config = add_arg(fninfo, ARG_SGPR, ctx->ac.i32);
4243 else
4244 ctx->param_streamout_config = fninfo->num_params - 1;
4245
4246 ctx->param_streamout_write_index = add_arg(fninfo, ARG_SGPR, ctx->ac.i32);
4247 }
4248 /* A streamout buffer offset is loaded if the stride is non-zero. */
4249 for (i = 0; i < 4; i++) {
4250 if (!so->stride[i])
4251 continue;
4252
4253 ctx->param_streamout_offset[i] = add_arg(fninfo, ARG_SGPR, ctx->ac.i32);
4254 }
4255 }
4256
4257 static void declare_lds_as_pointer(struct si_shader_context *ctx)
4258 {
4259 unsigned lds_size = ctx->screen->b.chip_class >= CIK ? 65536 : 32768;
4260 ctx->lds = LLVMBuildIntToPtr(ctx->ac.builder, ctx->i32_0,
4261 LLVMPointerType(LLVMArrayType(ctx->i32, lds_size / 4), LOCAL_ADDR_SPACE),
4262 "lds");
4263 }
4264
4265 static unsigned si_get_max_workgroup_size(const struct si_shader *shader)
4266 {
4267 switch (shader->selector->type) {
4268 case PIPE_SHADER_TESS_CTRL:
4269 /* Return this so that LLVM doesn't remove s_barrier
4270 * instructions on chips where we use s_barrier. */
4271 return shader->selector->screen->b.chip_class >= CIK ? 128 : 64;
4272
4273 case PIPE_SHADER_GEOMETRY:
4274 return shader->selector->screen->b.chip_class >= GFX9 ? 128 : 64;
4275
4276 case PIPE_SHADER_COMPUTE:
4277 break; /* see below */
4278
4279 default:
4280 return 0;
4281 }
4282
4283 const unsigned *properties = shader->selector->info.properties;
4284 unsigned max_work_group_size =
4285 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] *
4286 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT] *
4287 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH];
4288
4289 if (!max_work_group_size) {
4290 /* This is a variable group size compute shader,
4291 * compile it for the maximum possible group size.
4292 */
4293 max_work_group_size = SI_MAX_VARIABLE_THREADS_PER_BLOCK;
4294 }
4295 return max_work_group_size;
4296 }
4297
4298 static void declare_per_stage_desc_pointers(struct si_shader_context *ctx,
4299 struct si_function_info *fninfo,
4300 bool assign_params)
4301 {
4302 LLVMTypeRef const_shader_buf_type;
4303
4304 if (ctx->shader->selector->info.const_buffers_declared == 1 &&
4305 ctx->shader->selector->info.shader_buffers_declared == 0)
4306 const_shader_buf_type = ctx->f32;
4307 else
4308 const_shader_buf_type = ctx->v4i32;
4309
4310 unsigned const_and_shader_buffers =
4311 add_arg(fninfo, ARG_SGPR,
4312 si_const_array(const_shader_buf_type, 0));
4313
4314 unsigned samplers_and_images =
4315 add_arg(fninfo, ARG_SGPR,
4316 si_const_array(ctx->v8i32,
4317 SI_NUM_IMAGES + SI_NUM_SAMPLERS * 2));
4318
4319 if (assign_params) {
4320 ctx->param_const_and_shader_buffers = const_and_shader_buffers;
4321 ctx->param_samplers_and_images = samplers_and_images;
4322 }
4323 }
4324
4325 static void declare_global_desc_pointers(struct si_shader_context *ctx,
4326 struct si_function_info *fninfo)
4327 {
4328 ctx->param_rw_buffers = add_arg(fninfo, ARG_SGPR,
4329 si_const_array(ctx->v4i32, SI_NUM_RW_BUFFERS));
4330 ctx->param_bindless_samplers_and_images = add_arg(fninfo, ARG_SGPR,
4331 si_const_array(ctx->v8i32, 0));
4332 }
4333
4334 static void declare_vs_specific_input_sgprs(struct si_shader_context *ctx,
4335 struct si_function_info *fninfo)
4336 {
4337 ctx->param_vertex_buffers = add_arg(fninfo, ARG_SGPR,
4338 si_const_array(ctx->v4i32, SI_NUM_VERTEX_BUFFERS));
4339 add_arg_assign(fninfo, ARG_SGPR, ctx->i32, &ctx->abi.base_vertex);
4340 add_arg_assign(fninfo, ARG_SGPR, ctx->i32, &ctx->abi.start_instance);
4341 add_arg_assign(fninfo, ARG_SGPR, ctx->i32, &ctx->abi.draw_id);
4342 ctx->param_vs_state_bits = add_arg(fninfo, ARG_SGPR, ctx->i32);
4343 }
4344
4345 static void declare_vs_input_vgprs(struct si_shader_context *ctx,
4346 struct si_function_info *fninfo,
4347 unsigned *num_prolog_vgprs)
4348 {
4349 struct si_shader *shader = ctx->shader;
4350
4351 add_arg_assign(fninfo, ARG_VGPR, ctx->i32, &ctx->abi.vertex_id);
4352 if (shader->key.as_ls) {
4353 ctx->param_rel_auto_id = add_arg(fninfo, ARG_VGPR, ctx->i32);
4354 add_arg_assign(fninfo, ARG_VGPR, ctx->i32, &ctx->abi.instance_id);
4355 } else {
4356 add_arg_assign(fninfo, ARG_VGPR, ctx->i32, &ctx->abi.instance_id);
4357 ctx->param_vs_prim_id = add_arg(fninfo, ARG_VGPR, ctx->i32);
4358 }
4359 add_arg(fninfo, ARG_VGPR, ctx->i32); /* unused */
4360
4361 if (!shader->is_gs_copy_shader) {
4362 /* Vertex load indices. */
4363 ctx->param_vertex_index0 = fninfo->num_params;
4364 for (unsigned i = 0; i < shader->selector->info.num_inputs; i++)
4365 add_arg(fninfo, ARG_VGPR, ctx->i32);
4366 *num_prolog_vgprs += shader->selector->info.num_inputs;
4367 }
4368 }
4369
4370 static void declare_tes_input_vgprs(struct si_shader_context *ctx,
4371 struct si_function_info *fninfo)
4372 {
4373 ctx->param_tes_u = add_arg(fninfo, ARG_VGPR, ctx->f32);
4374 ctx->param_tes_v = add_arg(fninfo, ARG_VGPR, ctx->f32);
4375 ctx->param_tes_rel_patch_id = add_arg(fninfo, ARG_VGPR, ctx->i32);
4376 ctx->param_tes_patch_id = add_arg(fninfo, ARG_VGPR, ctx->i32);
4377 }
4378
4379 enum {
4380 /* Convenient merged shader definitions. */
4381 SI_SHADER_MERGED_VERTEX_TESSCTRL = PIPE_SHADER_TYPES,
4382 SI_SHADER_MERGED_VERTEX_OR_TESSEVAL_GEOMETRY,
4383 };
4384
4385 static void create_function(struct si_shader_context *ctx)
4386 {
4387 struct si_shader *shader = ctx->shader;
4388 struct si_function_info fninfo;
4389 LLVMTypeRef returns[16+32*4];
4390 unsigned i, num_return_sgprs;
4391 unsigned num_returns = 0;
4392 unsigned num_prolog_vgprs = 0;
4393 unsigned type = ctx->type;
4394 unsigned vs_blit_property =
4395 shader->selector->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS];
4396
4397 si_init_function_info(&fninfo);
4398
4399 /* Set MERGED shaders. */
4400 if (ctx->screen->b.chip_class >= GFX9) {
4401 if (shader->key.as_ls || type == PIPE_SHADER_TESS_CTRL)
4402 type = SI_SHADER_MERGED_VERTEX_TESSCTRL; /* LS or HS */
4403 else if (shader->key.as_es || type == PIPE_SHADER_GEOMETRY)
4404 type = SI_SHADER_MERGED_VERTEX_OR_TESSEVAL_GEOMETRY;
4405 }
4406
4407 LLVMTypeRef v3i32 = LLVMVectorType(ctx->i32, 3);
4408
4409 switch (type) {
4410 case PIPE_SHADER_VERTEX:
4411 declare_global_desc_pointers(ctx, &fninfo);
4412
4413 if (vs_blit_property) {
4414 ctx->param_vs_blit_inputs = fninfo.num_params;
4415 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* i16 x1, y1 */
4416 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* i16 x2, y2 */
4417 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* depth */
4418
4419 if (vs_blit_property == SI_VS_BLIT_SGPRS_POS_COLOR) {
4420 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* color0 */
4421 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* color1 */
4422 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* color2 */
4423 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* color3 */
4424 } else if (vs_blit_property == SI_VS_BLIT_SGPRS_POS_TEXCOORD) {
4425 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* texcoord.x1 */
4426 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* texcoord.y1 */
4427 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* texcoord.x2 */
4428 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* texcoord.y2 */
4429 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* texcoord.z */
4430 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* texcoord.w */
4431 }
4432
4433 /* VGPRs */
4434 declare_vs_input_vgprs(ctx, &fninfo, &num_prolog_vgprs);
4435 break;
4436 }
4437
4438 declare_per_stage_desc_pointers(ctx, &fninfo, true);
4439 declare_vs_specific_input_sgprs(ctx, &fninfo);
4440
4441 if (shader->key.as_es) {
4442 assert(!shader->selector->nir);
4443 ctx->param_es2gs_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4444 } else if (shader->key.as_ls) {
4445 assert(!shader->selector->nir);
4446 /* no extra parameters */
4447 } else {
4448 if (shader->is_gs_copy_shader) {
4449 fninfo.num_params = ctx->param_rw_buffers + 1;
4450 fninfo.num_sgpr_params = fninfo.num_params;
4451 }
4452
4453 /* The locations of the other parameters are assigned dynamically. */
4454 declare_streamout_params(ctx, &shader->selector->so,
4455 &fninfo);
4456 }
4457
4458 /* VGPRs */
4459 declare_vs_input_vgprs(ctx, &fninfo, &num_prolog_vgprs);
4460 break;
4461
4462 case PIPE_SHADER_TESS_CTRL: /* SI-CI-VI */
4463 declare_global_desc_pointers(ctx, &fninfo);
4464 declare_per_stage_desc_pointers(ctx, &fninfo, true);
4465 ctx->param_tcs_offchip_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4466 ctx->param_tcs_out_lds_offsets = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4467 ctx->param_tcs_out_lds_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4468 ctx->param_vs_state_bits = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4469 ctx->param_tcs_offchip_addr_base64k = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4470 ctx->param_tcs_factor_addr_base64k = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4471 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4472 ctx->param_tcs_factor_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4473
4474 /* VGPRs */
4475 ctx->param_tcs_patch_id = add_arg(&fninfo, ARG_VGPR, ctx->i32);
4476 ctx->param_tcs_rel_ids = add_arg(&fninfo, ARG_VGPR, ctx->i32);
4477
4478 /* param_tcs_offchip_offset and param_tcs_factor_offset are
4479 * placed after the user SGPRs.
4480 */
4481 for (i = 0; i < GFX6_TCS_NUM_USER_SGPR + 2; i++)
4482 returns[num_returns++] = ctx->i32; /* SGPRs */
4483 for (i = 0; i < 11; i++)
4484 returns[num_returns++] = ctx->f32; /* VGPRs */
4485 break;
4486
4487 case SI_SHADER_MERGED_VERTEX_TESSCTRL:
4488 /* Merged stages have 8 system SGPRs at the beginning. */
4489 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* SPI_SHADER_USER_DATA_ADDR_LO_HS */
4490 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* SPI_SHADER_USER_DATA_ADDR_HI_HS */
4491 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4492 ctx->param_merged_wave_info = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4493 ctx->param_tcs_factor_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4494 ctx->param_merged_scratch_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4495 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused */
4496 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused */
4497
4498 declare_global_desc_pointers(ctx, &fninfo);
4499 declare_per_stage_desc_pointers(ctx, &fninfo,
4500 ctx->type == PIPE_SHADER_VERTEX);
4501 declare_vs_specific_input_sgprs(ctx, &fninfo);
4502
4503 ctx->param_tcs_offchip_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4504 ctx->param_tcs_out_lds_offsets = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4505 ctx->param_tcs_out_lds_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4506 ctx->param_tcs_offchip_addr_base64k = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4507 ctx->param_tcs_factor_addr_base64k = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4508 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused */
4509
4510 declare_per_stage_desc_pointers(ctx, &fninfo,
4511 ctx->type == PIPE_SHADER_TESS_CTRL);
4512
4513 /* VGPRs (first TCS, then VS) */
4514 ctx->param_tcs_patch_id = add_arg(&fninfo, ARG_VGPR, ctx->i32);
4515 ctx->param_tcs_rel_ids = add_arg(&fninfo, ARG_VGPR, ctx->i32);
4516
4517 if (ctx->type == PIPE_SHADER_VERTEX) {
4518 declare_vs_input_vgprs(ctx, &fninfo,
4519 &num_prolog_vgprs);
4520
4521 /* LS return values are inputs to the TCS main shader part. */
4522 for (i = 0; i < 8 + GFX9_TCS_NUM_USER_SGPR; i++)
4523 returns[num_returns++] = ctx->i32; /* SGPRs */
4524 for (i = 0; i < 2; i++)
4525 returns[num_returns++] = ctx->f32; /* VGPRs */
4526 } else {
4527 /* TCS return values are inputs to the TCS epilog.
4528 *
4529 * param_tcs_offchip_offset, param_tcs_factor_offset,
4530 * param_tcs_offchip_layout, and param_rw_buffers
4531 * should be passed to the epilog.
4532 */
4533 for (i = 0; i <= 8 + GFX9_SGPR_TCS_FACTOR_ADDR_BASE64K; i++)
4534 returns[num_returns++] = ctx->i32; /* SGPRs */
4535 for (i = 0; i < 11; i++)
4536 returns[num_returns++] = ctx->f32; /* VGPRs */
4537 }
4538 break;
4539
4540 case SI_SHADER_MERGED_VERTEX_OR_TESSEVAL_GEOMETRY:
4541 /* Merged stages have 8 system SGPRs at the beginning. */
4542 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused (SPI_SHADER_USER_DATA_ADDR_LO_GS) */
4543 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused (SPI_SHADER_USER_DATA_ADDR_HI_GS) */
4544 ctx->param_gs2vs_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4545 ctx->param_merged_wave_info = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4546 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4547 ctx->param_merged_scratch_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4548 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused (SPI_SHADER_PGM_LO/HI_GS << 8) */
4549 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused (SPI_SHADER_PGM_LO/HI_GS >> 24) */
4550
4551 declare_global_desc_pointers(ctx, &fninfo);
4552 declare_per_stage_desc_pointers(ctx, &fninfo,
4553 (ctx->type == PIPE_SHADER_VERTEX ||
4554 ctx->type == PIPE_SHADER_TESS_EVAL));
4555 if (ctx->type == PIPE_SHADER_VERTEX) {
4556 declare_vs_specific_input_sgprs(ctx, &fninfo);
4557 } else {
4558 /* TESS_EVAL (and also GEOMETRY):
4559 * Declare as many input SGPRs as the VS has. */
4560 ctx->param_tcs_offchip_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4561 ctx->param_tcs_offchip_addr_base64k = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4562 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused */
4563 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused */
4564 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused */
4565 ctx->param_vs_state_bits = add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused */
4566 }
4567
4568 declare_per_stage_desc_pointers(ctx, &fninfo,
4569 ctx->type == PIPE_SHADER_GEOMETRY);
4570
4571 /* VGPRs (first GS, then VS/TES) */
4572 ctx->param_gs_vtx01_offset = add_arg(&fninfo, ARG_VGPR, ctx->i32);
4573 ctx->param_gs_vtx23_offset = add_arg(&fninfo, ARG_VGPR, ctx->i32);
4574 ctx->param_gs_prim_id = add_arg(&fninfo, ARG_VGPR, ctx->i32);
4575 ctx->param_gs_instance_id = add_arg(&fninfo, ARG_VGPR, ctx->i32);
4576 ctx->param_gs_vtx45_offset = add_arg(&fninfo, ARG_VGPR, ctx->i32);
4577
4578 if (ctx->type == PIPE_SHADER_VERTEX) {
4579 declare_vs_input_vgprs(ctx, &fninfo,
4580 &num_prolog_vgprs);
4581 } else if (ctx->type == PIPE_SHADER_TESS_EVAL) {
4582 declare_tes_input_vgprs(ctx, &fninfo);
4583 }
4584
4585 if (ctx->type == PIPE_SHADER_VERTEX ||
4586 ctx->type == PIPE_SHADER_TESS_EVAL) {
4587 /* ES return values are inputs to GS. */
4588 for (i = 0; i < 8 + GFX9_GS_NUM_USER_SGPR; i++)
4589 returns[num_returns++] = ctx->i32; /* SGPRs */
4590 for (i = 0; i < 5; i++)
4591 returns[num_returns++] = ctx->f32; /* VGPRs */
4592 }
4593 break;
4594
4595 case PIPE_SHADER_TESS_EVAL:
4596 declare_global_desc_pointers(ctx, &fninfo);
4597 declare_per_stage_desc_pointers(ctx, &fninfo, true);
4598 ctx->param_tcs_offchip_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4599 ctx->param_tcs_offchip_addr_base64k = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4600
4601 if (shader->key.as_es) {
4602 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4603 add_arg(&fninfo, ARG_SGPR, ctx->i32);
4604 ctx->param_es2gs_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4605 } else {
4606 add_arg(&fninfo, ARG_SGPR, ctx->i32);
4607 declare_streamout_params(ctx, &shader->selector->so,
4608 &fninfo);
4609 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4610 }
4611
4612 /* VGPRs */
4613 declare_tes_input_vgprs(ctx, &fninfo);
4614 break;
4615
4616 case PIPE_SHADER_GEOMETRY:
4617 declare_global_desc_pointers(ctx, &fninfo);
4618 declare_per_stage_desc_pointers(ctx, &fninfo, true);
4619 ctx->param_gs2vs_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4620 ctx->param_gs_wave_id = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4621
4622 /* VGPRs */
4623 ctx->param_gs_vtx0_offset = add_arg(&fninfo, ARG_VGPR, ctx->i32);
4624 ctx->param_gs_vtx1_offset = add_arg(&fninfo, ARG_VGPR, ctx->i32);
4625 ctx->param_gs_prim_id = add_arg(&fninfo, ARG_VGPR, ctx->i32);
4626 ctx->param_gs_vtx2_offset = add_arg(&fninfo, ARG_VGPR, ctx->i32);
4627 ctx->param_gs_vtx3_offset = add_arg(&fninfo, ARG_VGPR, ctx->i32);
4628 ctx->param_gs_vtx4_offset = add_arg(&fninfo, ARG_VGPR, ctx->i32);
4629 ctx->param_gs_vtx5_offset = add_arg(&fninfo, ARG_VGPR, ctx->i32);
4630 ctx->param_gs_instance_id = add_arg(&fninfo, ARG_VGPR, ctx->i32);
4631 break;
4632
4633 case PIPE_SHADER_FRAGMENT:
4634 declare_global_desc_pointers(ctx, &fninfo);
4635 declare_per_stage_desc_pointers(ctx, &fninfo, true);
4636 add_arg_checked(&fninfo, ARG_SGPR, ctx->f32, SI_PARAM_ALPHA_REF);
4637 add_arg_checked(&fninfo, ARG_SGPR, ctx->i32, SI_PARAM_PRIM_MASK);
4638
4639 add_arg_checked(&fninfo, ARG_VGPR, ctx->v2i32, SI_PARAM_PERSP_SAMPLE);
4640 add_arg_checked(&fninfo, ARG_VGPR, ctx->v2i32, SI_PARAM_PERSP_CENTER);
4641 add_arg_checked(&fninfo, ARG_VGPR, ctx->v2i32, SI_PARAM_PERSP_CENTROID);
4642 add_arg_checked(&fninfo, ARG_VGPR, v3i32, SI_PARAM_PERSP_PULL_MODEL);
4643 add_arg_checked(&fninfo, ARG_VGPR, ctx->v2i32, SI_PARAM_LINEAR_SAMPLE);
4644 add_arg_checked(&fninfo, ARG_VGPR, ctx->v2i32, SI_PARAM_LINEAR_CENTER);
4645 add_arg_checked(&fninfo, ARG_VGPR, ctx->v2i32, SI_PARAM_LINEAR_CENTROID);
4646 add_arg_checked(&fninfo, ARG_VGPR, ctx->f32, SI_PARAM_LINE_STIPPLE_TEX);
4647 add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->f32,
4648 &ctx->abi.frag_pos[0], SI_PARAM_POS_X_FLOAT);
4649 add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->f32,
4650 &ctx->abi.frag_pos[1], SI_PARAM_POS_Y_FLOAT);
4651 add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->f32,
4652 &ctx->abi.frag_pos[2], SI_PARAM_POS_Z_FLOAT);
4653 add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->f32,
4654 &ctx->abi.frag_pos[3], SI_PARAM_POS_W_FLOAT);
4655 add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->i32,
4656 &ctx->abi.front_face, SI_PARAM_FRONT_FACE);
4657 shader->info.face_vgpr_index = 20;
4658 add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->i32,
4659 &ctx->abi.ancillary, SI_PARAM_ANCILLARY);
4660 shader->info.ancillary_vgpr_index = 21;
4661 add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->f32,
4662 &ctx->abi.sample_coverage, SI_PARAM_SAMPLE_COVERAGE);
4663 add_arg_checked(&fninfo, ARG_VGPR, ctx->i32, SI_PARAM_POS_FIXED_PT);
4664
4665 /* Color inputs from the prolog. */
4666 if (shader->selector->info.colors_read) {
4667 unsigned num_color_elements =
4668 util_bitcount(shader->selector->info.colors_read);
4669
4670 assert(fninfo.num_params + num_color_elements <= ARRAY_SIZE(fninfo.types));
4671 for (i = 0; i < num_color_elements; i++)
4672 add_arg(&fninfo, ARG_VGPR, ctx->f32);
4673
4674 num_prolog_vgprs += num_color_elements;
4675 }
4676
4677 /* Outputs for the epilog. */
4678 num_return_sgprs = SI_SGPR_ALPHA_REF + 1;
4679 num_returns =
4680 num_return_sgprs +
4681 util_bitcount(shader->selector->info.colors_written) * 4 +
4682 shader->selector->info.writes_z +
4683 shader->selector->info.writes_stencil +
4684 shader->selector->info.writes_samplemask +
4685 1 /* SampleMaskIn */;
4686
4687 num_returns = MAX2(num_returns,
4688 num_return_sgprs +
4689 PS_EPILOG_SAMPLEMASK_MIN_LOC + 1);
4690
4691 for (i = 0; i < num_return_sgprs; i++)
4692 returns[i] = ctx->i32;
4693 for (; i < num_returns; i++)
4694 returns[i] = ctx->f32;
4695 break;
4696
4697 case PIPE_SHADER_COMPUTE:
4698 declare_global_desc_pointers(ctx, &fninfo);
4699 declare_per_stage_desc_pointers(ctx, &fninfo, true);
4700 if (shader->selector->info.uses_grid_size)
4701 ctx->param_grid_size = add_arg(&fninfo, ARG_SGPR, v3i32);
4702 if (shader->selector->info.uses_block_size)
4703 ctx->param_block_size = add_arg(&fninfo, ARG_SGPR, v3i32);
4704
4705 for (i = 0; i < 3; i++) {
4706 ctx->param_block_id[i] = -1;
4707 if (shader->selector->info.uses_block_id[i])
4708 ctx->param_block_id[i] = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4709 }
4710
4711 ctx->param_thread_id = add_arg(&fninfo, ARG_VGPR, v3i32);
4712 break;
4713 default:
4714 assert(0 && "unimplemented shader");
4715 return;
4716 }
4717
4718 si_create_function(ctx, "main", returns, num_returns, &fninfo,
4719 si_get_max_workgroup_size(shader));
4720
4721 /* Reserve register locations for VGPR inputs the PS prolog may need. */
4722 if (ctx->type == PIPE_SHADER_FRAGMENT &&
4723 ctx->separate_prolog) {
4724 si_llvm_add_attribute(ctx->main_fn,
4725 "InitialPSInputAddr",
4726 S_0286D0_PERSP_SAMPLE_ENA(1) |
4727 S_0286D0_PERSP_CENTER_ENA(1) |
4728 S_0286D0_PERSP_CENTROID_ENA(1) |
4729 S_0286D0_LINEAR_SAMPLE_ENA(1) |
4730 S_0286D0_LINEAR_CENTER_ENA(1) |
4731 S_0286D0_LINEAR_CENTROID_ENA(1) |
4732 S_0286D0_FRONT_FACE_ENA(1) |
4733 S_0286D0_ANCILLARY_ENA(1) |
4734 S_0286D0_POS_FIXED_PT_ENA(1));
4735 }
4736
4737 shader->info.num_input_sgprs = 0;
4738 shader->info.num_input_vgprs = 0;
4739
4740 for (i = 0; i < fninfo.num_sgpr_params; ++i)
4741 shader->info.num_input_sgprs += ac_get_type_size(fninfo.types[i]) / 4;
4742
4743 for (; i < fninfo.num_params; ++i)
4744 shader->info.num_input_vgprs += ac_get_type_size(fninfo.types[i]) / 4;
4745
4746 assert(shader->info.num_input_vgprs >= num_prolog_vgprs);
4747 shader->info.num_input_vgprs -= num_prolog_vgprs;
4748
4749 if (shader->key.as_ls ||
4750 ctx->type == PIPE_SHADER_TESS_CTRL ||
4751 /* GFX9 has the ESGS ring buffer in LDS. */
4752 (ctx->screen->b.chip_class >= GFX9 &&
4753 (shader->key.as_es ||
4754 ctx->type == PIPE_SHADER_GEOMETRY)))
4755 declare_lds_as_pointer(ctx);
4756 }
4757
4758 /**
4759 * Load ESGS and GSVS ring buffer resource descriptors and save the variables
4760 * for later use.
4761 */
4762 static void preload_ring_buffers(struct si_shader_context *ctx)
4763 {
4764 LLVMBuilderRef builder = ctx->ac.builder;
4765
4766 LLVMValueRef buf_ptr = LLVMGetParam(ctx->main_fn,
4767 ctx->param_rw_buffers);
4768
4769 if (ctx->screen->b.chip_class <= VI &&
4770 (ctx->shader->key.as_es || ctx->type == PIPE_SHADER_GEOMETRY)) {
4771 unsigned ring =
4772 ctx->type == PIPE_SHADER_GEOMETRY ? SI_GS_RING_ESGS
4773 : SI_ES_RING_ESGS;
4774 LLVMValueRef offset = LLVMConstInt(ctx->i32, ring, 0);
4775
4776 ctx->esgs_ring =
4777 ac_build_load_to_sgpr(&ctx->ac, buf_ptr, offset);
4778 }
4779
4780 if (ctx->shader->is_gs_copy_shader) {
4781 LLVMValueRef offset = LLVMConstInt(ctx->i32, SI_RING_GSVS, 0);
4782
4783 ctx->gsvs_ring[0] =
4784 ac_build_load_to_sgpr(&ctx->ac, buf_ptr, offset);
4785 } else if (ctx->type == PIPE_SHADER_GEOMETRY) {
4786 const struct si_shader_selector *sel = ctx->shader->selector;
4787 LLVMValueRef offset = LLVMConstInt(ctx->i32, SI_RING_GSVS, 0);
4788 LLVMValueRef base_ring;
4789
4790 base_ring = ac_build_load_to_sgpr(&ctx->ac, buf_ptr, offset);
4791
4792 /* The conceptual layout of the GSVS ring is
4793 * v0c0 .. vLv0 v0c1 .. vLc1 ..
4794 * but the real memory layout is swizzled across
4795 * threads:
4796 * t0v0c0 .. t15v0c0 t0v1c0 .. t15v1c0 ... t15vLcL
4797 * t16v0c0 ..
4798 * Override the buffer descriptor accordingly.
4799 */
4800 LLVMTypeRef v2i64 = LLVMVectorType(ctx->i64, 2);
4801 uint64_t stream_offset = 0;
4802
4803 for (unsigned stream = 0; stream < 4; ++stream) {
4804 unsigned num_components;
4805 unsigned stride;
4806 unsigned num_records;
4807 LLVMValueRef ring, tmp;
4808
4809 num_components = sel->info.num_stream_output_components[stream];
4810 if (!num_components)
4811 continue;
4812
4813 stride = 4 * num_components * sel->gs_max_out_vertices;
4814
4815 /* Limit on the stride field for <= CIK. */
4816 assert(stride < (1 << 14));
4817
4818 num_records = 64;
4819
4820 ring = LLVMBuildBitCast(builder, base_ring, v2i64, "");
4821 tmp = LLVMBuildExtractElement(builder, ring, ctx->i32_0, "");
4822 tmp = LLVMBuildAdd(builder, tmp,
4823 LLVMConstInt(ctx->i64,
4824 stream_offset, 0), "");
4825 stream_offset += stride * 64;
4826
4827 ring = LLVMBuildInsertElement(builder, ring, tmp, ctx->i32_0, "");
4828 ring = LLVMBuildBitCast(builder, ring, ctx->v4i32, "");
4829 tmp = LLVMBuildExtractElement(builder, ring, ctx->i32_1, "");
4830 tmp = LLVMBuildOr(builder, tmp,
4831 LLVMConstInt(ctx->i32,
4832 S_008F04_STRIDE(stride) |
4833 S_008F04_SWIZZLE_ENABLE(1), 0), "");
4834 ring = LLVMBuildInsertElement(builder, ring, tmp, ctx->i32_1, "");
4835 ring = LLVMBuildInsertElement(builder, ring,
4836 LLVMConstInt(ctx->i32, num_records, 0),
4837 LLVMConstInt(ctx->i32, 2, 0), "");
4838 ring = LLVMBuildInsertElement(builder, ring,
4839 LLVMConstInt(ctx->i32,
4840 S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
4841 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
4842 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
4843 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
4844 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
4845 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
4846 S_008F0C_ELEMENT_SIZE(1) | /* element_size = 4 (bytes) */
4847 S_008F0C_INDEX_STRIDE(1) | /* index_stride = 16 (elements) */
4848 S_008F0C_ADD_TID_ENABLE(1),
4849 0),
4850 LLVMConstInt(ctx->i32, 3, 0), "");
4851
4852 ctx->gsvs_ring[stream] = ring;
4853 }
4854 }
4855 }
4856
4857 static void si_llvm_emit_polygon_stipple(struct si_shader_context *ctx,
4858 LLVMValueRef param_rw_buffers,
4859 unsigned param_pos_fixed_pt)
4860 {
4861 LLVMBuilderRef builder = ctx->ac.builder;
4862 LLVMValueRef slot, desc, offset, row, bit, address[2];
4863
4864 /* Use the fixed-point gl_FragCoord input.
4865 * Since the stipple pattern is 32x32 and it repeats, just get 5 bits
4866 * per coordinate to get the repeating effect.
4867 */
4868 address[0] = unpack_param(ctx, param_pos_fixed_pt, 0, 5);
4869 address[1] = unpack_param(ctx, param_pos_fixed_pt, 16, 5);
4870
4871 /* Load the buffer descriptor. */
4872 slot = LLVMConstInt(ctx->i32, SI_PS_CONST_POLY_STIPPLE, 0);
4873 desc = ac_build_load_to_sgpr(&ctx->ac, param_rw_buffers, slot);
4874
4875 /* The stipple pattern is 32x32, each row has 32 bits. */
4876 offset = LLVMBuildMul(builder, address[1],
4877 LLVMConstInt(ctx->i32, 4, 0), "");
4878 row = buffer_load_const(ctx, desc, offset);
4879 row = ac_to_integer(&ctx->ac, row);
4880 bit = LLVMBuildLShr(builder, row, address[0], "");
4881 bit = LLVMBuildTrunc(builder, bit, ctx->i1, "");
4882 ac_build_kill_if_false(&ctx->ac, bit);
4883 }
4884
4885 void si_shader_binary_read_config(struct ac_shader_binary *binary,
4886 struct si_shader_config *conf,
4887 unsigned symbol_offset)
4888 {
4889 unsigned i;
4890 const unsigned char *config =
4891 ac_shader_binary_config_start(binary, symbol_offset);
4892 bool really_needs_scratch = false;
4893
4894 /* LLVM adds SGPR spills to the scratch size.
4895 * Find out if we really need the scratch buffer.
4896 */
4897 for (i = 0; i < binary->reloc_count; i++) {
4898 const struct ac_shader_reloc *reloc = &binary->relocs[i];
4899
4900 if (!strcmp(scratch_rsrc_dword0_symbol, reloc->name) ||
4901 !strcmp(scratch_rsrc_dword1_symbol, reloc->name)) {
4902 really_needs_scratch = true;
4903 break;
4904 }
4905 }
4906
4907 /* XXX: We may be able to emit some of these values directly rather than
4908 * extracting fields to be emitted later.
4909 */
4910
4911 for (i = 0; i < binary->config_size_per_symbol; i+= 8) {
4912 unsigned reg = util_le32_to_cpu(*(uint32_t*)(config + i));
4913 unsigned value = util_le32_to_cpu(*(uint32_t*)(config + i + 4));
4914 switch (reg) {
4915 case R_00B028_SPI_SHADER_PGM_RSRC1_PS:
4916 case R_00B128_SPI_SHADER_PGM_RSRC1_VS:
4917 case R_00B228_SPI_SHADER_PGM_RSRC1_GS:
4918 case R_00B428_SPI_SHADER_PGM_RSRC1_HS:
4919 case R_00B848_COMPUTE_PGM_RSRC1:
4920 conf->num_sgprs = MAX2(conf->num_sgprs, (G_00B028_SGPRS(value) + 1) * 8);
4921 conf->num_vgprs = MAX2(conf->num_vgprs, (G_00B028_VGPRS(value) + 1) * 4);
4922 conf->float_mode = G_00B028_FLOAT_MODE(value);
4923 conf->rsrc1 = value;
4924 break;
4925 case R_00B02C_SPI_SHADER_PGM_RSRC2_PS:
4926 conf->lds_size = MAX2(conf->lds_size, G_00B02C_EXTRA_LDS_SIZE(value));
4927 break;
4928 case R_00B84C_COMPUTE_PGM_RSRC2:
4929 conf->lds_size = MAX2(conf->lds_size, G_00B84C_LDS_SIZE(value));
4930 conf->rsrc2 = value;
4931 break;
4932 case R_0286CC_SPI_PS_INPUT_ENA:
4933 conf->spi_ps_input_ena = value;
4934 break;
4935 case R_0286D0_SPI_PS_INPUT_ADDR:
4936 conf->spi_ps_input_addr = value;
4937 break;
4938 case R_0286E8_SPI_TMPRING_SIZE:
4939 case R_00B860_COMPUTE_TMPRING_SIZE:
4940 /* WAVESIZE is in units of 256 dwords. */
4941 if (really_needs_scratch)
4942 conf->scratch_bytes_per_wave =
4943 G_00B860_WAVESIZE(value) * 256 * 4;
4944 break;
4945 case 0x4: /* SPILLED_SGPRS */
4946 conf->spilled_sgprs = value;
4947 break;
4948 case 0x8: /* SPILLED_VGPRS */
4949 conf->spilled_vgprs = value;
4950 break;
4951 default:
4952 {
4953 static bool printed;
4954
4955 if (!printed) {
4956 fprintf(stderr, "Warning: LLVM emitted unknown "
4957 "config register: 0x%x\n", reg);
4958 printed = true;
4959 }
4960 }
4961 break;
4962 }
4963 }
4964
4965 if (!conf->spi_ps_input_addr)
4966 conf->spi_ps_input_addr = conf->spi_ps_input_ena;
4967 }
4968
4969 void si_shader_apply_scratch_relocs(struct si_shader *shader,
4970 uint64_t scratch_va)
4971 {
4972 unsigned i;
4973 uint32_t scratch_rsrc_dword0 = scratch_va;
4974 uint32_t scratch_rsrc_dword1 =
4975 S_008F04_BASE_ADDRESS_HI(scratch_va >> 32);
4976
4977 /* Enable scratch coalescing. */
4978 scratch_rsrc_dword1 |= S_008F04_SWIZZLE_ENABLE(1);
4979
4980 for (i = 0 ; i < shader->binary.reloc_count; i++) {
4981 const struct ac_shader_reloc *reloc =
4982 &shader->binary.relocs[i];
4983 if (!strcmp(scratch_rsrc_dword0_symbol, reloc->name)) {
4984 util_memcpy_cpu_to_le32(shader->binary.code + reloc->offset,
4985 &scratch_rsrc_dword0, 4);
4986 } else if (!strcmp(scratch_rsrc_dword1_symbol, reloc->name)) {
4987 util_memcpy_cpu_to_le32(shader->binary.code + reloc->offset,
4988 &scratch_rsrc_dword1, 4);
4989 }
4990 }
4991 }
4992
4993 static unsigned si_get_shader_binary_size(const struct si_shader *shader)
4994 {
4995 unsigned size = shader->binary.code_size;
4996
4997 if (shader->prolog)
4998 size += shader->prolog->binary.code_size;
4999 if (shader->previous_stage)
5000 size += shader->previous_stage->binary.code_size;
5001 if (shader->prolog2)
5002 size += shader->prolog2->binary.code_size;
5003 if (shader->epilog)
5004 size += shader->epilog->binary.code_size;
5005 return size;
5006 }
5007
5008 int si_shader_binary_upload(struct si_screen *sscreen, struct si_shader *shader)
5009 {
5010 const struct ac_shader_binary *prolog =
5011 shader->prolog ? &shader->prolog->binary : NULL;
5012 const struct ac_shader_binary *previous_stage =
5013 shader->previous_stage ? &shader->previous_stage->binary : NULL;
5014 const struct ac_shader_binary *prolog2 =
5015 shader->prolog2 ? &shader->prolog2->binary : NULL;
5016 const struct ac_shader_binary *epilog =
5017 shader->epilog ? &shader->epilog->binary : NULL;
5018 const struct ac_shader_binary *mainb = &shader->binary;
5019 unsigned bo_size = si_get_shader_binary_size(shader) +
5020 (!epilog ? mainb->rodata_size : 0);
5021 unsigned char *ptr;
5022
5023 assert(!prolog || !prolog->rodata_size);
5024 assert(!previous_stage || !previous_stage->rodata_size);
5025 assert(!prolog2 || !prolog2->rodata_size);
5026 assert((!prolog && !previous_stage && !prolog2 && !epilog) ||
5027 !mainb->rodata_size);
5028 assert(!epilog || !epilog->rodata_size);
5029
5030 r600_resource_reference(&shader->bo, NULL);
5031 shader->bo = (struct r600_resource*)
5032 pipe_buffer_create(&sscreen->b.b, 0,
5033 PIPE_USAGE_IMMUTABLE,
5034 align(bo_size, SI_CPDMA_ALIGNMENT));
5035 if (!shader->bo)
5036 return -ENOMEM;
5037
5038 /* Upload. */
5039 ptr = sscreen->b.ws->buffer_map(shader->bo->buf, NULL,
5040 PIPE_TRANSFER_READ_WRITE |
5041 PIPE_TRANSFER_UNSYNCHRONIZED);
5042
5043 /* Don't use util_memcpy_cpu_to_le32. LLVM binaries are
5044 * endian-independent. */
5045 if (prolog) {
5046 memcpy(ptr, prolog->code, prolog->code_size);
5047 ptr += prolog->code_size;
5048 }
5049 if (previous_stage) {
5050 memcpy(ptr, previous_stage->code, previous_stage->code_size);
5051 ptr += previous_stage->code_size;
5052 }
5053 if (prolog2) {
5054 memcpy(ptr, prolog2->code, prolog2->code_size);
5055 ptr += prolog2->code_size;
5056 }
5057
5058 memcpy(ptr, mainb->code, mainb->code_size);
5059 ptr += mainb->code_size;
5060
5061 if (epilog)
5062 memcpy(ptr, epilog->code, epilog->code_size);
5063 else if (mainb->rodata_size > 0)
5064 memcpy(ptr, mainb->rodata, mainb->rodata_size);
5065
5066 sscreen->b.ws->buffer_unmap(shader->bo->buf);
5067 return 0;
5068 }
5069
5070 static void si_shader_dump_disassembly(const struct ac_shader_binary *binary,
5071 struct pipe_debug_callback *debug,
5072 const char *name, FILE *file)
5073 {
5074 char *line, *p;
5075 unsigned i, count;
5076
5077 if (binary->disasm_string) {
5078 fprintf(file, "Shader %s disassembly:\n", name);
5079 fprintf(file, "%s", binary->disasm_string);
5080
5081 if (debug && debug->debug_message) {
5082 /* Very long debug messages are cut off, so send the
5083 * disassembly one line at a time. This causes more
5084 * overhead, but on the plus side it simplifies
5085 * parsing of resulting logs.
5086 */
5087 pipe_debug_message(debug, SHADER_INFO,
5088 "Shader Disassembly Begin");
5089
5090 line = binary->disasm_string;
5091 while (*line) {
5092 p = util_strchrnul(line, '\n');
5093 count = p - line;
5094
5095 if (count) {
5096 pipe_debug_message(debug, SHADER_INFO,
5097 "%.*s", count, line);
5098 }
5099
5100 if (!*p)
5101 break;
5102 line = p + 1;
5103 }
5104
5105 pipe_debug_message(debug, SHADER_INFO,
5106 "Shader Disassembly End");
5107 }
5108 } else {
5109 fprintf(file, "Shader %s binary:\n", name);
5110 for (i = 0; i < binary->code_size; i += 4) {
5111 fprintf(file, "@0x%x: %02x%02x%02x%02x\n", i,
5112 binary->code[i + 3], binary->code[i + 2],
5113 binary->code[i + 1], binary->code[i]);
5114 }
5115 }
5116 }
5117
5118 static void si_shader_dump_stats(struct si_screen *sscreen,
5119 const struct si_shader *shader,
5120 struct pipe_debug_callback *debug,
5121 unsigned processor,
5122 FILE *file,
5123 bool check_debug_option)
5124 {
5125 const struct si_shader_config *conf = &shader->config;
5126 unsigned num_inputs = shader->selector ? shader->selector->info.num_inputs : 0;
5127 unsigned code_size = si_get_shader_binary_size(shader);
5128 unsigned lds_increment = sscreen->b.chip_class >= CIK ? 512 : 256;
5129 unsigned lds_per_wave = 0;
5130 unsigned max_simd_waves;
5131
5132 switch (sscreen->b.family) {
5133 /* These always have 8 waves: */
5134 case CHIP_POLARIS10:
5135 case CHIP_POLARIS11:
5136 case CHIP_POLARIS12:
5137 max_simd_waves = 8;
5138 break;
5139 default:
5140 max_simd_waves = 10;
5141 }
5142
5143 /* Compute LDS usage for PS. */
5144 switch (processor) {
5145 case PIPE_SHADER_FRAGMENT:
5146 /* The minimum usage per wave is (num_inputs * 48). The maximum
5147 * usage is (num_inputs * 48 * 16).
5148 * We can get anything in between and it varies between waves.
5149 *
5150 * The 48 bytes per input for a single primitive is equal to
5151 * 4 bytes/component * 4 components/input * 3 points.
5152 *
5153 * Other stages don't know the size at compile time or don't
5154 * allocate LDS per wave, but instead they do it per thread group.
5155 */
5156 lds_per_wave = conf->lds_size * lds_increment +
5157 align(num_inputs * 48, lds_increment);
5158 break;
5159 case PIPE_SHADER_COMPUTE:
5160 if (shader->selector) {
5161 unsigned max_workgroup_size =
5162 si_get_max_workgroup_size(shader);
5163 lds_per_wave = (conf->lds_size * lds_increment) /
5164 DIV_ROUND_UP(max_workgroup_size, 64);
5165 }
5166 break;
5167 }
5168
5169 /* Compute the per-SIMD wave counts. */
5170 if (conf->num_sgprs) {
5171 if (sscreen->b.chip_class >= VI)
5172 max_simd_waves = MIN2(max_simd_waves, 800 / conf->num_sgprs);
5173 else
5174 max_simd_waves = MIN2(max_simd_waves, 512 / conf->num_sgprs);
5175 }
5176
5177 if (conf->num_vgprs)
5178 max_simd_waves = MIN2(max_simd_waves, 256 / conf->num_vgprs);
5179
5180 /* LDS is 64KB per CU (4 SIMDs), which is 16KB per SIMD (usage above
5181 * 16KB makes some SIMDs unoccupied). */
5182 if (lds_per_wave)
5183 max_simd_waves = MIN2(max_simd_waves, 16384 / lds_per_wave);
5184
5185 if (!check_debug_option ||
5186 si_can_dump_shader(&sscreen->b, processor)) {
5187 if (processor == PIPE_SHADER_FRAGMENT) {
5188 fprintf(file, "*** SHADER CONFIG ***\n"
5189 "SPI_PS_INPUT_ADDR = 0x%04x\n"
5190 "SPI_PS_INPUT_ENA = 0x%04x\n",
5191 conf->spi_ps_input_addr, conf->spi_ps_input_ena);
5192 }
5193
5194 fprintf(file, "*** SHADER STATS ***\n"
5195 "SGPRS: %d\n"
5196 "VGPRS: %d\n"
5197 "Spilled SGPRs: %d\n"
5198 "Spilled VGPRs: %d\n"
5199 "Private memory VGPRs: %d\n"
5200 "Code Size: %d bytes\n"
5201 "LDS: %d blocks\n"
5202 "Scratch: %d bytes per wave\n"
5203 "Max Waves: %d\n"
5204 "********************\n\n\n",
5205 conf->num_sgprs, conf->num_vgprs,
5206 conf->spilled_sgprs, conf->spilled_vgprs,
5207 conf->private_mem_vgprs, code_size,
5208 conf->lds_size, conf->scratch_bytes_per_wave,
5209 max_simd_waves);
5210 }
5211
5212 pipe_debug_message(debug, SHADER_INFO,
5213 "Shader Stats: SGPRS: %d VGPRS: %d Code Size: %d "
5214 "LDS: %d Scratch: %d Max Waves: %d Spilled SGPRs: %d "
5215 "Spilled VGPRs: %d PrivMem VGPRs: %d",
5216 conf->num_sgprs, conf->num_vgprs, code_size,
5217 conf->lds_size, conf->scratch_bytes_per_wave,
5218 max_simd_waves, conf->spilled_sgprs,
5219 conf->spilled_vgprs, conf->private_mem_vgprs);
5220 }
5221
5222 const char *si_get_shader_name(const struct si_shader *shader, unsigned processor)
5223 {
5224 switch (processor) {
5225 case PIPE_SHADER_VERTEX:
5226 if (shader->key.as_es)
5227 return "Vertex Shader as ES";
5228 else if (shader->key.as_ls)
5229 return "Vertex Shader as LS";
5230 else
5231 return "Vertex Shader as VS";
5232 case PIPE_SHADER_TESS_CTRL:
5233 return "Tessellation Control Shader";
5234 case PIPE_SHADER_TESS_EVAL:
5235 if (shader->key.as_es)
5236 return "Tessellation Evaluation Shader as ES";
5237 else
5238 return "Tessellation Evaluation Shader as VS";
5239 case PIPE_SHADER_GEOMETRY:
5240 if (shader->is_gs_copy_shader)
5241 return "GS Copy Shader as VS";
5242 else
5243 return "Geometry Shader";
5244 case PIPE_SHADER_FRAGMENT:
5245 return "Pixel Shader";
5246 case PIPE_SHADER_COMPUTE:
5247 return "Compute Shader";
5248 default:
5249 return "Unknown Shader";
5250 }
5251 }
5252
5253 void si_shader_dump(struct si_screen *sscreen, const struct si_shader *shader,
5254 struct pipe_debug_callback *debug, unsigned processor,
5255 FILE *file, bool check_debug_option)
5256 {
5257 if (!check_debug_option ||
5258 si_can_dump_shader(&sscreen->b, processor))
5259 si_dump_shader_key(processor, shader, file);
5260
5261 if (!check_debug_option && shader->binary.llvm_ir_string) {
5262 if (shader->previous_stage &&
5263 shader->previous_stage->binary.llvm_ir_string) {
5264 fprintf(file, "\n%s - previous stage - LLVM IR:\n\n",
5265 si_get_shader_name(shader, processor));
5266 fprintf(file, "%s\n", shader->previous_stage->binary.llvm_ir_string);
5267 }
5268
5269 fprintf(file, "\n%s - main shader part - LLVM IR:\n\n",
5270 si_get_shader_name(shader, processor));
5271 fprintf(file, "%s\n", shader->binary.llvm_ir_string);
5272 }
5273
5274 if (!check_debug_option ||
5275 (si_can_dump_shader(&sscreen->b, processor) &&
5276 !(sscreen->b.debug_flags & DBG(NO_ASM)))) {
5277 fprintf(file, "\n%s:\n", si_get_shader_name(shader, processor));
5278
5279 if (shader->prolog)
5280 si_shader_dump_disassembly(&shader->prolog->binary,
5281 debug, "prolog", file);
5282 if (shader->previous_stage)
5283 si_shader_dump_disassembly(&shader->previous_stage->binary,
5284 debug, "previous stage", file);
5285 if (shader->prolog2)
5286 si_shader_dump_disassembly(&shader->prolog2->binary,
5287 debug, "prolog2", file);
5288
5289 si_shader_dump_disassembly(&shader->binary, debug, "main", file);
5290
5291 if (shader->epilog)
5292 si_shader_dump_disassembly(&shader->epilog->binary,
5293 debug, "epilog", file);
5294 fprintf(file, "\n");
5295 }
5296
5297 si_shader_dump_stats(sscreen, shader, debug, processor, file,
5298 check_debug_option);
5299 }
5300
5301 static int si_compile_llvm(struct si_screen *sscreen,
5302 struct ac_shader_binary *binary,
5303 struct si_shader_config *conf,
5304 LLVMTargetMachineRef tm,
5305 LLVMModuleRef mod,
5306 struct pipe_debug_callback *debug,
5307 unsigned processor,
5308 const char *name)
5309 {
5310 int r = 0;
5311 unsigned count = p_atomic_inc_return(&sscreen->b.num_compilations);
5312
5313 if (si_can_dump_shader(&sscreen->b, processor)) {
5314 fprintf(stderr, "radeonsi: Compiling shader %d\n", count);
5315
5316 if (!(sscreen->b.debug_flags & (DBG(NO_IR) | DBG(PREOPT_IR)))) {
5317 fprintf(stderr, "%s LLVM IR:\n\n", name);
5318 ac_dump_module(mod);
5319 fprintf(stderr, "\n");
5320 }
5321 }
5322
5323 if (sscreen->record_llvm_ir) {
5324 char *ir = LLVMPrintModuleToString(mod);
5325 binary->llvm_ir_string = strdup(ir);
5326 LLVMDisposeMessage(ir);
5327 }
5328
5329 if (!si_replace_shader(count, binary)) {
5330 r = si_llvm_compile(mod, binary, tm, debug);
5331 if (r)
5332 return r;
5333 }
5334
5335 si_shader_binary_read_config(binary, conf, 0);
5336
5337 /* Enable 64-bit and 16-bit denormals, because there is no performance
5338 * cost.
5339 *
5340 * If denormals are enabled, all floating-point output modifiers are
5341 * ignored.
5342 *
5343 * Don't enable denormals for 32-bit floats, because:
5344 * - Floating-point output modifiers would be ignored by the hw.
5345 * - Some opcodes don't support denormals, such as v_mad_f32. We would
5346 * have to stop using those.
5347 * - SI & CI would be very slow.
5348 */
5349 conf->float_mode |= V_00B028_FP_64_DENORMS;
5350
5351 FREE(binary->config);
5352 FREE(binary->global_symbol_offsets);
5353 binary->config = NULL;
5354 binary->global_symbol_offsets = NULL;
5355
5356 /* Some shaders can't have rodata because their binaries can be
5357 * concatenated.
5358 */
5359 if (binary->rodata_size &&
5360 (processor == PIPE_SHADER_VERTEX ||
5361 processor == PIPE_SHADER_TESS_CTRL ||
5362 processor == PIPE_SHADER_TESS_EVAL ||
5363 processor == PIPE_SHADER_FRAGMENT)) {
5364 fprintf(stderr, "radeonsi: The shader can't have rodata.");
5365 return -EINVAL;
5366 }
5367
5368 return r;
5369 }
5370
5371 static void si_llvm_build_ret(struct si_shader_context *ctx, LLVMValueRef ret)
5372 {
5373 if (LLVMGetTypeKind(LLVMTypeOf(ret)) == LLVMVoidTypeKind)
5374 LLVMBuildRetVoid(ctx->ac.builder);
5375 else
5376 LLVMBuildRet(ctx->ac.builder, ret);
5377 }
5378
5379 /* Generate code for the hardware VS shader stage to go with a geometry shader */
5380 struct si_shader *
5381 si_generate_gs_copy_shader(struct si_screen *sscreen,
5382 LLVMTargetMachineRef tm,
5383 struct si_shader_selector *gs_selector,
5384 struct pipe_debug_callback *debug)
5385 {
5386 struct si_shader_context ctx;
5387 struct si_shader *shader;
5388 LLVMBuilderRef builder;
5389 struct lp_build_tgsi_context *bld_base = &ctx.bld_base;
5390 struct lp_build_context *uint = &bld_base->uint_bld;
5391 struct si_shader_output_values *outputs;
5392 struct tgsi_shader_info *gsinfo = &gs_selector->info;
5393 int i, r;
5394
5395 outputs = MALLOC(gsinfo->num_outputs * sizeof(outputs[0]));
5396
5397 if (!outputs)
5398 return NULL;
5399
5400 shader = CALLOC_STRUCT(si_shader);
5401 if (!shader) {
5402 FREE(outputs);
5403 return NULL;
5404 }
5405
5406
5407 shader->selector = gs_selector;
5408 shader->is_gs_copy_shader = true;
5409
5410 si_init_shader_ctx(&ctx, sscreen, tm);
5411 ctx.shader = shader;
5412 ctx.type = PIPE_SHADER_VERTEX;
5413
5414 builder = ctx.ac.builder;
5415
5416 create_function(&ctx);
5417 preload_ring_buffers(&ctx);
5418
5419 LLVMValueRef voffset =
5420 lp_build_mul_imm(uint, ctx.abi.vertex_id, 4);
5421
5422 /* Fetch the vertex stream ID.*/
5423 LLVMValueRef stream_id;
5424
5425 if (gs_selector->so.num_outputs)
5426 stream_id = unpack_param(&ctx, ctx.param_streamout_config, 24, 2);
5427 else
5428 stream_id = ctx.i32_0;
5429
5430 /* Fill in output information. */
5431 for (i = 0; i < gsinfo->num_outputs; ++i) {
5432 outputs[i].semantic_name = gsinfo->output_semantic_name[i];
5433 outputs[i].semantic_index = gsinfo->output_semantic_index[i];
5434
5435 for (int chan = 0; chan < 4; chan++) {
5436 outputs[i].vertex_stream[chan] =
5437 (gsinfo->output_streams[i] >> (2 * chan)) & 3;
5438 }
5439 }
5440
5441 LLVMBasicBlockRef end_bb;
5442 LLVMValueRef switch_inst;
5443
5444 end_bb = LLVMAppendBasicBlockInContext(ctx.ac.context, ctx.main_fn, "end");
5445 switch_inst = LLVMBuildSwitch(builder, stream_id, end_bb, 4);
5446
5447 for (int stream = 0; stream < 4; stream++) {
5448 LLVMBasicBlockRef bb;
5449 unsigned offset;
5450
5451 if (!gsinfo->num_stream_output_components[stream])
5452 continue;
5453
5454 if (stream > 0 && !gs_selector->so.num_outputs)
5455 continue;
5456
5457 bb = LLVMInsertBasicBlockInContext(ctx.ac.context, end_bb, "out");
5458 LLVMAddCase(switch_inst, LLVMConstInt(ctx.i32, stream, 0), bb);
5459 LLVMPositionBuilderAtEnd(builder, bb);
5460
5461 /* Fetch vertex data from GSVS ring */
5462 offset = 0;
5463 for (i = 0; i < gsinfo->num_outputs; ++i) {
5464 for (unsigned chan = 0; chan < 4; chan++) {
5465 if (!(gsinfo->output_usagemask[i] & (1 << chan)) ||
5466 outputs[i].vertex_stream[chan] != stream) {
5467 outputs[i].values[chan] = ctx.bld_base.base.undef;
5468 continue;
5469 }
5470
5471 LLVMValueRef soffset = LLVMConstInt(ctx.i32,
5472 offset * gs_selector->gs_max_out_vertices * 16 * 4, 0);
5473 offset++;
5474
5475 outputs[i].values[chan] =
5476 ac_build_buffer_load(&ctx.ac,
5477 ctx.gsvs_ring[0], 1,
5478 ctx.i32_0, voffset,
5479 soffset, 0, 1, 1,
5480 true, false);
5481 }
5482 }
5483
5484 /* Streamout and exports. */
5485 if (gs_selector->so.num_outputs) {
5486 si_llvm_emit_streamout(&ctx, outputs,
5487 gsinfo->num_outputs,
5488 stream);
5489 }
5490
5491 if (stream == 0)
5492 si_llvm_export_vs(bld_base, outputs, gsinfo->num_outputs);
5493
5494 LLVMBuildBr(builder, end_bb);
5495 }
5496
5497 LLVMPositionBuilderAtEnd(builder, end_bb);
5498
5499 LLVMBuildRetVoid(ctx.ac.builder);
5500
5501 ctx.type = PIPE_SHADER_GEOMETRY; /* override for shader dumping */
5502 si_llvm_optimize_module(&ctx);
5503
5504 r = si_compile_llvm(sscreen, &ctx.shader->binary,
5505 &ctx.shader->config, ctx.tm,
5506 ctx.gallivm.module,
5507 debug, PIPE_SHADER_GEOMETRY,
5508 "GS Copy Shader");
5509 if (!r) {
5510 if (si_can_dump_shader(&sscreen->b, PIPE_SHADER_GEOMETRY))
5511 fprintf(stderr, "GS Copy Shader:\n");
5512 si_shader_dump(sscreen, ctx.shader, debug,
5513 PIPE_SHADER_GEOMETRY, stderr, true);
5514 r = si_shader_binary_upload(sscreen, ctx.shader);
5515 }
5516
5517 si_llvm_dispose(&ctx);
5518
5519 FREE(outputs);
5520
5521 if (r != 0) {
5522 FREE(shader);
5523 shader = NULL;
5524 }
5525 return shader;
5526 }
5527
5528 static void si_dump_shader_key_vs(const struct si_shader_key *key,
5529 const struct si_vs_prolog_bits *prolog,
5530 const char *prefix, FILE *f)
5531 {
5532 fprintf(f, " %s.instance_divisor_is_one = %u\n",
5533 prefix, prolog->instance_divisor_is_one);
5534 fprintf(f, " %s.instance_divisor_is_fetched = %u\n",
5535 prefix, prolog->instance_divisor_is_fetched);
5536 fprintf(f, " %s.ls_vgpr_fix = %u\n",
5537 prefix, prolog->ls_vgpr_fix);
5538
5539 fprintf(f, " mono.vs.fix_fetch = {");
5540 for (int i = 0; i < SI_MAX_ATTRIBS; i++)
5541 fprintf(f, !i ? "%u" : ", %u", key->mono.vs_fix_fetch[i]);
5542 fprintf(f, "}\n");
5543 }
5544
5545 static void si_dump_shader_key(unsigned processor, const struct si_shader *shader,
5546 FILE *f)
5547 {
5548 const struct si_shader_key *key = &shader->key;
5549
5550 fprintf(f, "SHADER KEY\n");
5551
5552 switch (processor) {
5553 case PIPE_SHADER_VERTEX:
5554 si_dump_shader_key_vs(key, &key->part.vs.prolog,
5555 "part.vs.prolog", f);
5556 fprintf(f, " as_es = %u\n", key->as_es);
5557 fprintf(f, " as_ls = %u\n", key->as_ls);
5558 fprintf(f, " mono.u.vs_export_prim_id = %u\n",
5559 key->mono.u.vs_export_prim_id);
5560 break;
5561
5562 case PIPE_SHADER_TESS_CTRL:
5563 if (shader->selector->screen->b.chip_class >= GFX9) {
5564 si_dump_shader_key_vs(key, &key->part.tcs.ls_prolog,
5565 "part.tcs.ls_prolog", f);
5566 }
5567 fprintf(f, " part.tcs.epilog.prim_mode = %u\n", key->part.tcs.epilog.prim_mode);
5568 fprintf(f, " mono.u.ff_tcs_inputs_to_copy = 0x%"PRIx64"\n", key->mono.u.ff_tcs_inputs_to_copy);
5569 break;
5570
5571 case PIPE_SHADER_TESS_EVAL:
5572 fprintf(f, " as_es = %u\n", key->as_es);
5573 fprintf(f, " mono.u.vs_export_prim_id = %u\n",
5574 key->mono.u.vs_export_prim_id);
5575 break;
5576
5577 case PIPE_SHADER_GEOMETRY:
5578 if (shader->is_gs_copy_shader)
5579 break;
5580
5581 if (shader->selector->screen->b.chip_class >= GFX9 &&
5582 key->part.gs.es->type == PIPE_SHADER_VERTEX) {
5583 si_dump_shader_key_vs(key, &key->part.gs.vs_prolog,
5584 "part.gs.vs_prolog", f);
5585 }
5586 fprintf(f, " part.gs.prolog.tri_strip_adj_fix = %u\n", key->part.gs.prolog.tri_strip_adj_fix);
5587 break;
5588
5589 case PIPE_SHADER_COMPUTE:
5590 break;
5591
5592 case PIPE_SHADER_FRAGMENT:
5593 fprintf(f, " part.ps.prolog.color_two_side = %u\n", key->part.ps.prolog.color_two_side);
5594 fprintf(f, " part.ps.prolog.flatshade_colors = %u\n", key->part.ps.prolog.flatshade_colors);
5595 fprintf(f, " part.ps.prolog.poly_stipple = %u\n", key->part.ps.prolog.poly_stipple);
5596 fprintf(f, " part.ps.prolog.force_persp_sample_interp = %u\n", key->part.ps.prolog.force_persp_sample_interp);
5597 fprintf(f, " part.ps.prolog.force_linear_sample_interp = %u\n", key->part.ps.prolog.force_linear_sample_interp);
5598 fprintf(f, " part.ps.prolog.force_persp_center_interp = %u\n", key->part.ps.prolog.force_persp_center_interp);
5599 fprintf(f, " part.ps.prolog.force_linear_center_interp = %u\n", key->part.ps.prolog.force_linear_center_interp);
5600 fprintf(f, " part.ps.prolog.bc_optimize_for_persp = %u\n", key->part.ps.prolog.bc_optimize_for_persp);
5601 fprintf(f, " part.ps.prolog.bc_optimize_for_linear = %u\n", key->part.ps.prolog.bc_optimize_for_linear);
5602 fprintf(f, " part.ps.epilog.spi_shader_col_format = 0x%x\n", key->part.ps.epilog.spi_shader_col_format);
5603 fprintf(f, " part.ps.epilog.color_is_int8 = 0x%X\n", key->part.ps.epilog.color_is_int8);
5604 fprintf(f, " part.ps.epilog.color_is_int10 = 0x%X\n", key->part.ps.epilog.color_is_int10);
5605 fprintf(f, " part.ps.epilog.last_cbuf = %u\n", key->part.ps.epilog.last_cbuf);
5606 fprintf(f, " part.ps.epilog.alpha_func = %u\n", key->part.ps.epilog.alpha_func);
5607 fprintf(f, " part.ps.epilog.alpha_to_one = %u\n", key->part.ps.epilog.alpha_to_one);
5608 fprintf(f, " part.ps.epilog.poly_line_smoothing = %u\n", key->part.ps.epilog.poly_line_smoothing);
5609 fprintf(f, " part.ps.epilog.clamp_color = %u\n", key->part.ps.epilog.clamp_color);
5610 break;
5611
5612 default:
5613 assert(0);
5614 }
5615
5616 if ((processor == PIPE_SHADER_GEOMETRY ||
5617 processor == PIPE_SHADER_TESS_EVAL ||
5618 processor == PIPE_SHADER_VERTEX) &&
5619 !key->as_es && !key->as_ls) {
5620 fprintf(f, " opt.kill_outputs = 0x%"PRIx64"\n", key->opt.kill_outputs);
5621 fprintf(f, " opt.clip_disable = %u\n", key->opt.clip_disable);
5622 }
5623 }
5624
5625 static void si_init_shader_ctx(struct si_shader_context *ctx,
5626 struct si_screen *sscreen,
5627 LLVMTargetMachineRef tm)
5628 {
5629 struct lp_build_tgsi_context *bld_base;
5630
5631 si_llvm_context_init(ctx, sscreen, tm);
5632
5633 bld_base = &ctx->bld_base;
5634 bld_base->emit_fetch_funcs[TGSI_FILE_CONSTANT] = fetch_constant;
5635
5636 bld_base->op_actions[TGSI_OPCODE_INTERP_CENTROID] = interp_action;
5637 bld_base->op_actions[TGSI_OPCODE_INTERP_SAMPLE] = interp_action;
5638 bld_base->op_actions[TGSI_OPCODE_INTERP_OFFSET] = interp_action;
5639
5640 bld_base->op_actions[TGSI_OPCODE_MEMBAR].emit = membar_emit;
5641
5642 bld_base->op_actions[TGSI_OPCODE_CLOCK].emit = clock_emit;
5643
5644 bld_base->op_actions[TGSI_OPCODE_DDX].emit = si_llvm_emit_ddxy;
5645 bld_base->op_actions[TGSI_OPCODE_DDY].emit = si_llvm_emit_ddxy;
5646 bld_base->op_actions[TGSI_OPCODE_DDX_FINE].emit = si_llvm_emit_ddxy;
5647 bld_base->op_actions[TGSI_OPCODE_DDY_FINE].emit = si_llvm_emit_ddxy;
5648
5649 bld_base->op_actions[TGSI_OPCODE_VOTE_ALL].emit = vote_all_emit;
5650 bld_base->op_actions[TGSI_OPCODE_VOTE_ANY].emit = vote_any_emit;
5651 bld_base->op_actions[TGSI_OPCODE_VOTE_EQ].emit = vote_eq_emit;
5652 bld_base->op_actions[TGSI_OPCODE_BALLOT].emit = ballot_emit;
5653 bld_base->op_actions[TGSI_OPCODE_READ_FIRST].intr_name = "llvm.amdgcn.readfirstlane";
5654 bld_base->op_actions[TGSI_OPCODE_READ_FIRST].emit = read_lane_emit;
5655 bld_base->op_actions[TGSI_OPCODE_READ_INVOC].intr_name = "llvm.amdgcn.readlane";
5656 bld_base->op_actions[TGSI_OPCODE_READ_INVOC].fetch_args = read_invoc_fetch_args;
5657 bld_base->op_actions[TGSI_OPCODE_READ_INVOC].emit = read_lane_emit;
5658
5659 bld_base->op_actions[TGSI_OPCODE_EMIT].emit = si_llvm_emit_vertex;
5660 bld_base->op_actions[TGSI_OPCODE_ENDPRIM].emit = si_llvm_emit_primitive;
5661 bld_base->op_actions[TGSI_OPCODE_BARRIER].emit = si_llvm_emit_barrier;
5662 }
5663
5664 static void si_optimize_vs_outputs(struct si_shader_context *ctx)
5665 {
5666 struct si_shader *shader = ctx->shader;
5667 struct tgsi_shader_info *info = &shader->selector->info;
5668
5669 if ((ctx->type != PIPE_SHADER_VERTEX &&
5670 ctx->type != PIPE_SHADER_TESS_EVAL) ||
5671 shader->key.as_ls ||
5672 shader->key.as_es)
5673 return;
5674
5675 ac_optimize_vs_outputs(&ctx->ac,
5676 ctx->main_fn,
5677 shader->info.vs_output_param_offset,
5678 info->num_outputs,
5679 &shader->info.nr_param_exports);
5680 }
5681
5682 static void si_count_scratch_private_memory(struct si_shader_context *ctx)
5683 {
5684 ctx->shader->config.private_mem_vgprs = 0;
5685
5686 /* Process all LLVM instructions. */
5687 LLVMBasicBlockRef bb = LLVMGetFirstBasicBlock(ctx->main_fn);
5688 while (bb) {
5689 LLVMValueRef next = LLVMGetFirstInstruction(bb);
5690
5691 while (next) {
5692 LLVMValueRef inst = next;
5693 next = LLVMGetNextInstruction(next);
5694
5695 if (LLVMGetInstructionOpcode(inst) != LLVMAlloca)
5696 continue;
5697
5698 LLVMTypeRef type = LLVMGetElementType(LLVMTypeOf(inst));
5699 /* No idea why LLVM aligns allocas to 4 elements. */
5700 unsigned alignment = LLVMGetAlignment(inst);
5701 unsigned dw_size = align(ac_get_type_size(type) / 4, alignment);
5702 ctx->shader->config.private_mem_vgprs += dw_size;
5703 }
5704 bb = LLVMGetNextBasicBlock(bb);
5705 }
5706 }
5707
5708 static void si_init_exec_full_mask(struct si_shader_context *ctx)
5709 {
5710 LLVMValueRef full_mask = LLVMConstInt(ctx->i64, ~0ull, 0);
5711 lp_build_intrinsic(ctx->ac.builder,
5712 "llvm.amdgcn.init.exec", ctx->voidt,
5713 &full_mask, 1, LP_FUNC_ATTR_CONVERGENT);
5714 }
5715
5716 static void si_init_exec_from_input(struct si_shader_context *ctx,
5717 unsigned param, unsigned bitoffset)
5718 {
5719 LLVMValueRef args[] = {
5720 LLVMGetParam(ctx->main_fn, param),
5721 LLVMConstInt(ctx->i32, bitoffset, 0),
5722 };
5723 lp_build_intrinsic(ctx->ac.builder,
5724 "llvm.amdgcn.init.exec.from.input",
5725 ctx->voidt, args, 2, LP_FUNC_ATTR_CONVERGENT);
5726 }
5727
5728 static bool si_vs_needs_prolog(const struct si_shader_selector *sel,
5729 const struct si_vs_prolog_bits *key)
5730 {
5731 /* VGPR initialization fixup for Vega10 and Raven is always done in the
5732 * VS prolog. */
5733 return sel->vs_needs_prolog || key->ls_vgpr_fix;
5734 }
5735
5736 static bool si_compile_tgsi_main(struct si_shader_context *ctx,
5737 bool is_monolithic)
5738 {
5739 struct si_shader *shader = ctx->shader;
5740 struct si_shader_selector *sel = shader->selector;
5741 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
5742
5743 // TODO clean all this up!
5744 switch (ctx->type) {
5745 case PIPE_SHADER_VERTEX:
5746 ctx->load_input = declare_input_vs;
5747 if (shader->key.as_ls)
5748 bld_base->emit_epilogue = si_llvm_emit_ls_epilogue;
5749 else if (shader->key.as_es)
5750 bld_base->emit_epilogue = si_llvm_emit_es_epilogue;
5751 else {
5752 ctx->abi.emit_outputs = si_llvm_emit_vs_epilogue;
5753 bld_base->emit_epilogue = si_tgsi_emit_epilogue;
5754 }
5755 break;
5756 case PIPE_SHADER_TESS_CTRL:
5757 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_tcs;
5758 bld_base->emit_fetch_funcs[TGSI_FILE_OUTPUT] = fetch_output_tcs;
5759 bld_base->emit_store = store_output_tcs;
5760 bld_base->emit_epilogue = si_llvm_emit_tcs_epilogue;
5761 break;
5762 case PIPE_SHADER_TESS_EVAL:
5763 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_tes;
5764 if (shader->key.as_es)
5765 bld_base->emit_epilogue = si_llvm_emit_es_epilogue;
5766 else {
5767 ctx->abi.emit_outputs = si_llvm_emit_vs_epilogue;
5768 bld_base->emit_epilogue = si_tgsi_emit_epilogue;
5769 }
5770 break;
5771 case PIPE_SHADER_GEOMETRY:
5772 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_gs;
5773 bld_base->emit_epilogue = si_llvm_emit_gs_epilogue;
5774 break;
5775 case PIPE_SHADER_FRAGMENT:
5776 ctx->load_input = declare_input_fs;
5777 ctx->abi.emit_outputs = si_llvm_return_fs_outputs;
5778 bld_base->emit_epilogue = si_tgsi_emit_epilogue;
5779 break;
5780 case PIPE_SHADER_COMPUTE:
5781 break;
5782 default:
5783 assert(!"Unsupported shader type");
5784 return false;
5785 }
5786
5787 ctx->abi.load_ubo = load_ubo;
5788 ctx->abi.load_ssbo = load_ssbo;
5789
5790 create_function(ctx);
5791 preload_ring_buffers(ctx);
5792
5793 /* For GFX9 merged shaders:
5794 * - Set EXEC for the first shader. If the prolog is present, set
5795 * EXEC there instead.
5796 * - Add a barrier before the second shader.
5797 * - In the second shader, reset EXEC to ~0 and wrap the main part in
5798 * an if-statement. This is required for correctness in geometry
5799 * shaders, to ensure that empty GS waves do not send GS_EMIT and
5800 * GS_CUT messages.
5801 *
5802 * For monolithic merged shaders, the first shader is wrapped in an
5803 * if-block together with its prolog in si_build_wrapper_function.
5804 */
5805 if (ctx->screen->b.chip_class >= GFX9) {
5806 if (!is_monolithic &&
5807 sel->info.num_instructions > 1 && /* not empty shader */
5808 (shader->key.as_es || shader->key.as_ls) &&
5809 (ctx->type == PIPE_SHADER_TESS_EVAL ||
5810 (ctx->type == PIPE_SHADER_VERTEX &&
5811 !si_vs_needs_prolog(sel, &shader->key.part.vs.prolog)))) {
5812 si_init_exec_from_input(ctx,
5813 ctx->param_merged_wave_info, 0);
5814 } else if (ctx->type == PIPE_SHADER_TESS_CTRL ||
5815 ctx->type == PIPE_SHADER_GEOMETRY) {
5816 if (!is_monolithic)
5817 si_init_exec_full_mask(ctx);
5818
5819 /* The barrier must execute for all shaders in a
5820 * threadgroup.
5821 */
5822 si_llvm_emit_barrier(NULL, bld_base, NULL);
5823
5824 LLVMValueRef num_threads = unpack_param(ctx, ctx->param_merged_wave_info, 8, 8);
5825 LLVMValueRef ena =
5826 LLVMBuildICmp(ctx->ac.builder, LLVMIntULT,
5827 ac_get_thread_id(&ctx->ac), num_threads, "");
5828 lp_build_if(&ctx->merged_wrap_if_state, &ctx->gallivm, ena);
5829 }
5830 }
5831
5832 if (ctx->type == PIPE_SHADER_TESS_CTRL &&
5833 sel->tcs_info.tessfactors_are_def_in_all_invocs) {
5834 for (unsigned i = 0; i < 6; i++) {
5835 ctx->invoc0_tess_factors[i] =
5836 lp_build_alloca_undef(&ctx->gallivm, ctx->i32, "");
5837 }
5838 }
5839
5840 if (ctx->type == PIPE_SHADER_GEOMETRY) {
5841 int i;
5842 for (i = 0; i < 4; i++) {
5843 ctx->gs_next_vertex[i] =
5844 lp_build_alloca(&ctx->gallivm,
5845 ctx->i32, "");
5846 }
5847 }
5848
5849 if (sel->force_correct_derivs_after_kill) {
5850 ctx->postponed_kill = lp_build_alloca_undef(&ctx->gallivm, ctx->i1, "");
5851 /* true = don't kill. */
5852 LLVMBuildStore(ctx->ac.builder, LLVMConstInt(ctx->i1, 1, 0),
5853 ctx->postponed_kill);
5854 }
5855
5856 if (sel->tokens) {
5857 if (!lp_build_tgsi_llvm(bld_base, sel->tokens)) {
5858 fprintf(stderr, "Failed to translate shader from TGSI to LLVM\n");
5859 return false;
5860 }
5861 } else {
5862 if (!si_nir_build_llvm(ctx, sel->nir)) {
5863 fprintf(stderr, "Failed to translate shader from NIR to LLVM\n");
5864 return false;
5865 }
5866 }
5867
5868 si_llvm_build_ret(ctx, ctx->return_value);
5869 return true;
5870 }
5871
5872 /**
5873 * Compute the VS prolog key, which contains all the information needed to
5874 * build the VS prolog function, and set shader->info bits where needed.
5875 *
5876 * \param info Shader info of the vertex shader.
5877 * \param num_input_sgprs Number of input SGPRs for the vertex shader.
5878 * \param prolog_key Key of the VS prolog
5879 * \param shader_out The vertex shader, or the next shader if merging LS+HS or ES+GS.
5880 * \param key Output shader part key.
5881 */
5882 static void si_get_vs_prolog_key(const struct tgsi_shader_info *info,
5883 unsigned num_input_sgprs,
5884 const struct si_vs_prolog_bits *prolog_key,
5885 struct si_shader *shader_out,
5886 union si_shader_part_key *key)
5887 {
5888 memset(key, 0, sizeof(*key));
5889 key->vs_prolog.states = *prolog_key;
5890 key->vs_prolog.num_input_sgprs = num_input_sgprs;
5891 key->vs_prolog.last_input = MAX2(1, info->num_inputs) - 1;
5892 key->vs_prolog.as_ls = shader_out->key.as_ls;
5893
5894 if (shader_out->selector->type == PIPE_SHADER_TESS_CTRL) {
5895 key->vs_prolog.as_ls = 1;
5896 key->vs_prolog.num_merged_next_stage_vgprs = 2;
5897 } else if (shader_out->selector->type == PIPE_SHADER_GEOMETRY) {
5898 key->vs_prolog.num_merged_next_stage_vgprs = 5;
5899 }
5900
5901 /* Enable loading the InstanceID VGPR. */
5902 uint16_t input_mask = u_bit_consecutive(0, info->num_inputs);
5903
5904 if ((key->vs_prolog.states.instance_divisor_is_one |
5905 key->vs_prolog.states.instance_divisor_is_fetched) & input_mask)
5906 shader_out->info.uses_instanceid = true;
5907 }
5908
5909 /**
5910 * Compute the PS prolog key, which contains all the information needed to
5911 * build the PS prolog function, and set related bits in shader->config.
5912 */
5913 static void si_get_ps_prolog_key(struct si_shader *shader,
5914 union si_shader_part_key *key,
5915 bool separate_prolog)
5916 {
5917 struct tgsi_shader_info *info = &shader->selector->info;
5918
5919 memset(key, 0, sizeof(*key));
5920 key->ps_prolog.states = shader->key.part.ps.prolog;
5921 key->ps_prolog.colors_read = info->colors_read;
5922 key->ps_prolog.num_input_sgprs = shader->info.num_input_sgprs;
5923 key->ps_prolog.num_input_vgprs = shader->info.num_input_vgprs;
5924 key->ps_prolog.wqm = info->uses_derivatives &&
5925 (key->ps_prolog.colors_read ||
5926 key->ps_prolog.states.force_persp_sample_interp ||
5927 key->ps_prolog.states.force_linear_sample_interp ||
5928 key->ps_prolog.states.force_persp_center_interp ||
5929 key->ps_prolog.states.force_linear_center_interp ||
5930 key->ps_prolog.states.bc_optimize_for_persp ||
5931 key->ps_prolog.states.bc_optimize_for_linear);
5932 key->ps_prolog.ancillary_vgpr_index = shader->info.ancillary_vgpr_index;
5933
5934 if (info->colors_read) {
5935 unsigned *color = shader->selector->color_attr_index;
5936
5937 if (shader->key.part.ps.prolog.color_two_side) {
5938 /* BCOLORs are stored after the last input. */
5939 key->ps_prolog.num_interp_inputs = info->num_inputs;
5940 key->ps_prolog.face_vgpr_index = shader->info.face_vgpr_index;
5941 shader->config.spi_ps_input_ena |= S_0286CC_FRONT_FACE_ENA(1);
5942 }
5943
5944 for (unsigned i = 0; i < 2; i++) {
5945 unsigned interp = info->input_interpolate[color[i]];
5946 unsigned location = info->input_interpolate_loc[color[i]];
5947
5948 if (!(info->colors_read & (0xf << i*4)))
5949 continue;
5950
5951 key->ps_prolog.color_attr_index[i] = color[i];
5952
5953 if (shader->key.part.ps.prolog.flatshade_colors &&
5954 interp == TGSI_INTERPOLATE_COLOR)
5955 interp = TGSI_INTERPOLATE_CONSTANT;
5956
5957 switch (interp) {
5958 case TGSI_INTERPOLATE_CONSTANT:
5959 key->ps_prolog.color_interp_vgpr_index[i] = -1;
5960 break;
5961 case TGSI_INTERPOLATE_PERSPECTIVE:
5962 case TGSI_INTERPOLATE_COLOR:
5963 /* Force the interpolation location for colors here. */
5964 if (shader->key.part.ps.prolog.force_persp_sample_interp)
5965 location = TGSI_INTERPOLATE_LOC_SAMPLE;
5966 if (shader->key.part.ps.prolog.force_persp_center_interp)
5967 location = TGSI_INTERPOLATE_LOC_CENTER;
5968
5969 switch (location) {
5970 case TGSI_INTERPOLATE_LOC_SAMPLE:
5971 key->ps_prolog.color_interp_vgpr_index[i] = 0;
5972 shader->config.spi_ps_input_ena |=
5973 S_0286CC_PERSP_SAMPLE_ENA(1);
5974 break;
5975 case TGSI_INTERPOLATE_LOC_CENTER:
5976 key->ps_prolog.color_interp_vgpr_index[i] = 2;
5977 shader->config.spi_ps_input_ena |=
5978 S_0286CC_PERSP_CENTER_ENA(1);
5979 break;
5980 case TGSI_INTERPOLATE_LOC_CENTROID:
5981 key->ps_prolog.color_interp_vgpr_index[i] = 4;
5982 shader->config.spi_ps_input_ena |=
5983 S_0286CC_PERSP_CENTROID_ENA(1);
5984 break;
5985 default:
5986 assert(0);
5987 }
5988 break;
5989 case TGSI_INTERPOLATE_LINEAR:
5990 /* Force the interpolation location for colors here. */
5991 if (shader->key.part.ps.prolog.force_linear_sample_interp)
5992 location = TGSI_INTERPOLATE_LOC_SAMPLE;
5993 if (shader->key.part.ps.prolog.force_linear_center_interp)
5994 location = TGSI_INTERPOLATE_LOC_CENTER;
5995
5996 /* The VGPR assignment for non-monolithic shaders
5997 * works because InitialPSInputAddr is set on the
5998 * main shader and PERSP_PULL_MODEL is never used.
5999 */
6000 switch (location) {
6001 case TGSI_INTERPOLATE_LOC_SAMPLE:
6002 key->ps_prolog.color_interp_vgpr_index[i] =
6003 separate_prolog ? 6 : 9;
6004 shader->config.spi_ps_input_ena |=
6005 S_0286CC_LINEAR_SAMPLE_ENA(1);
6006 break;
6007 case TGSI_INTERPOLATE_LOC_CENTER:
6008 key->ps_prolog.color_interp_vgpr_index[i] =
6009 separate_prolog ? 8 : 11;
6010 shader->config.spi_ps_input_ena |=
6011 S_0286CC_LINEAR_CENTER_ENA(1);
6012 break;
6013 case TGSI_INTERPOLATE_LOC_CENTROID:
6014 key->ps_prolog.color_interp_vgpr_index[i] =
6015 separate_prolog ? 10 : 13;
6016 shader->config.spi_ps_input_ena |=
6017 S_0286CC_LINEAR_CENTROID_ENA(1);
6018 break;
6019 default:
6020 assert(0);
6021 }
6022 break;
6023 default:
6024 assert(0);
6025 }
6026 }
6027 }
6028 }
6029
6030 /**
6031 * Check whether a PS prolog is required based on the key.
6032 */
6033 static bool si_need_ps_prolog(const union si_shader_part_key *key)
6034 {
6035 return key->ps_prolog.colors_read ||
6036 key->ps_prolog.states.force_persp_sample_interp ||
6037 key->ps_prolog.states.force_linear_sample_interp ||
6038 key->ps_prolog.states.force_persp_center_interp ||
6039 key->ps_prolog.states.force_linear_center_interp ||
6040 key->ps_prolog.states.bc_optimize_for_persp ||
6041 key->ps_prolog.states.bc_optimize_for_linear ||
6042 key->ps_prolog.states.poly_stipple ||
6043 key->ps_prolog.states.samplemask_log_ps_iter;
6044 }
6045
6046 /**
6047 * Compute the PS epilog key, which contains all the information needed to
6048 * build the PS epilog function.
6049 */
6050 static void si_get_ps_epilog_key(struct si_shader *shader,
6051 union si_shader_part_key *key)
6052 {
6053 struct tgsi_shader_info *info = &shader->selector->info;
6054 memset(key, 0, sizeof(*key));
6055 key->ps_epilog.colors_written = info->colors_written;
6056 key->ps_epilog.writes_z = info->writes_z;
6057 key->ps_epilog.writes_stencil = info->writes_stencil;
6058 key->ps_epilog.writes_samplemask = info->writes_samplemask;
6059 key->ps_epilog.states = shader->key.part.ps.epilog;
6060 }
6061
6062 /**
6063 * Build the GS prolog function. Rotate the input vertices for triangle strips
6064 * with adjacency.
6065 */
6066 static void si_build_gs_prolog_function(struct si_shader_context *ctx,
6067 union si_shader_part_key *key)
6068 {
6069 unsigned num_sgprs, num_vgprs;
6070 struct si_function_info fninfo;
6071 LLVMBuilderRef builder = ctx->ac.builder;
6072 LLVMTypeRef returns[48];
6073 LLVMValueRef func, ret;
6074
6075 si_init_function_info(&fninfo);
6076
6077 if (ctx->screen->b.chip_class >= GFX9) {
6078 num_sgprs = 8 + GFX9_GS_NUM_USER_SGPR;
6079 num_vgprs = 5; /* ES inputs are not needed by GS */
6080 } else {
6081 num_sgprs = GFX6_GS_NUM_USER_SGPR + 2;
6082 num_vgprs = 8;
6083 }
6084
6085 for (unsigned i = 0; i < num_sgprs; ++i) {
6086 add_arg(&fninfo, ARG_SGPR, ctx->i32);
6087 returns[i] = ctx->i32;
6088 }
6089
6090 for (unsigned i = 0; i < num_vgprs; ++i) {
6091 add_arg(&fninfo, ARG_VGPR, ctx->i32);
6092 returns[num_sgprs + i] = ctx->f32;
6093 }
6094
6095 /* Create the function. */
6096 si_create_function(ctx, "gs_prolog", returns, num_sgprs + num_vgprs,
6097 &fninfo, 0);
6098 func = ctx->main_fn;
6099
6100 /* Set the full EXEC mask for the prolog, because we are only fiddling
6101 * with registers here. The main shader part will set the correct EXEC
6102 * mask.
6103 */
6104 if (ctx->screen->b.chip_class >= GFX9 && !key->gs_prolog.is_monolithic)
6105 si_init_exec_full_mask(ctx);
6106
6107 /* Copy inputs to outputs. This should be no-op, as the registers match,
6108 * but it will prevent the compiler from overwriting them unintentionally.
6109 */
6110 ret = ctx->return_value;
6111 for (unsigned i = 0; i < num_sgprs; i++) {
6112 LLVMValueRef p = LLVMGetParam(func, i);
6113 ret = LLVMBuildInsertValue(builder, ret, p, i, "");
6114 }
6115 for (unsigned i = 0; i < num_vgprs; i++) {
6116 LLVMValueRef p = LLVMGetParam(func, num_sgprs + i);
6117 p = ac_to_float(&ctx->ac, p);
6118 ret = LLVMBuildInsertValue(builder, ret, p, num_sgprs + i, "");
6119 }
6120
6121 if (key->gs_prolog.states.tri_strip_adj_fix) {
6122 /* Remap the input vertices for every other primitive. */
6123 const unsigned gfx6_vtx_params[6] = {
6124 num_sgprs,
6125 num_sgprs + 1,
6126 num_sgprs + 3,
6127 num_sgprs + 4,
6128 num_sgprs + 5,
6129 num_sgprs + 6
6130 };
6131 const unsigned gfx9_vtx_params[3] = {
6132 num_sgprs,
6133 num_sgprs + 1,
6134 num_sgprs + 4,
6135 };
6136 LLVMValueRef vtx_in[6], vtx_out[6];
6137 LLVMValueRef prim_id, rotate;
6138
6139 if (ctx->screen->b.chip_class >= GFX9) {
6140 for (unsigned i = 0; i < 3; i++) {
6141 vtx_in[i*2] = unpack_param(ctx, gfx9_vtx_params[i], 0, 16);
6142 vtx_in[i*2+1] = unpack_param(ctx, gfx9_vtx_params[i], 16, 16);
6143 }
6144 } else {
6145 for (unsigned i = 0; i < 6; i++)
6146 vtx_in[i] = LLVMGetParam(func, gfx6_vtx_params[i]);
6147 }
6148
6149 prim_id = LLVMGetParam(func, num_sgprs + 2);
6150 rotate = LLVMBuildTrunc(builder, prim_id, ctx->i1, "");
6151
6152 for (unsigned i = 0; i < 6; ++i) {
6153 LLVMValueRef base, rotated;
6154 base = vtx_in[i];
6155 rotated = vtx_in[(i + 4) % 6];
6156 vtx_out[i] = LLVMBuildSelect(builder, rotate, rotated, base, "");
6157 }
6158
6159 if (ctx->screen->b.chip_class >= GFX9) {
6160 for (unsigned i = 0; i < 3; i++) {
6161 LLVMValueRef hi, out;
6162
6163 hi = LLVMBuildShl(builder, vtx_out[i*2+1],
6164 LLVMConstInt(ctx->i32, 16, 0), "");
6165 out = LLVMBuildOr(builder, vtx_out[i*2], hi, "");
6166 out = ac_to_float(&ctx->ac, out);
6167 ret = LLVMBuildInsertValue(builder, ret, out,
6168 gfx9_vtx_params[i], "");
6169 }
6170 } else {
6171 for (unsigned i = 0; i < 6; i++) {
6172 LLVMValueRef out;
6173
6174 out = ac_to_float(&ctx->ac, vtx_out[i]);
6175 ret = LLVMBuildInsertValue(builder, ret, out,
6176 gfx6_vtx_params[i], "");
6177 }
6178 }
6179 }
6180
6181 LLVMBuildRet(builder, ret);
6182 }
6183
6184 /**
6185 * Given a list of shader part functions, build a wrapper function that
6186 * runs them in sequence to form a monolithic shader.
6187 */
6188 static void si_build_wrapper_function(struct si_shader_context *ctx,
6189 LLVMValueRef *parts,
6190 unsigned num_parts,
6191 unsigned main_part,
6192 unsigned next_shader_first_part)
6193 {
6194 LLVMBuilderRef builder = ctx->ac.builder;
6195 /* PS epilog has one arg per color component; gfx9 merged shader
6196 * prologs need to forward 32 user SGPRs.
6197 */
6198 struct si_function_info fninfo;
6199 LLVMValueRef initial[64], out[64];
6200 LLVMTypeRef function_type;
6201 unsigned num_first_params;
6202 unsigned num_out, initial_num_out;
6203 MAYBE_UNUSED unsigned num_out_sgpr; /* used in debug checks */
6204 MAYBE_UNUSED unsigned initial_num_out_sgpr; /* used in debug checks */
6205 unsigned num_sgprs, num_vgprs;
6206 unsigned gprs;
6207 struct lp_build_if_state if_state;
6208
6209 si_init_function_info(&fninfo);
6210
6211 for (unsigned i = 0; i < num_parts; ++i) {
6212 lp_add_function_attr(parts[i], -1, LP_FUNC_ATTR_ALWAYSINLINE);
6213 LLVMSetLinkage(parts[i], LLVMPrivateLinkage);
6214 }
6215
6216 /* The parameters of the wrapper function correspond to those of the
6217 * first part in terms of SGPRs and VGPRs, but we use the types of the
6218 * main part to get the right types. This is relevant for the
6219 * dereferenceable attribute on descriptor table pointers.
6220 */
6221 num_sgprs = 0;
6222 num_vgprs = 0;
6223
6224 function_type = LLVMGetElementType(LLVMTypeOf(parts[0]));
6225 num_first_params = LLVMCountParamTypes(function_type);
6226
6227 for (unsigned i = 0; i < num_first_params; ++i) {
6228 LLVMValueRef param = LLVMGetParam(parts[0], i);
6229
6230 if (ac_is_sgpr_param(param)) {
6231 assert(num_vgprs == 0);
6232 num_sgprs += ac_get_type_size(LLVMTypeOf(param)) / 4;
6233 } else {
6234 num_vgprs += ac_get_type_size(LLVMTypeOf(param)) / 4;
6235 }
6236 }
6237
6238 gprs = 0;
6239 while (gprs < num_sgprs + num_vgprs) {
6240 LLVMValueRef param = LLVMGetParam(parts[main_part], fninfo.num_params);
6241 LLVMTypeRef type = LLVMTypeOf(param);
6242 unsigned size = ac_get_type_size(type) / 4;
6243
6244 add_arg(&fninfo, gprs < num_sgprs ? ARG_SGPR : ARG_VGPR, type);
6245
6246 assert(ac_is_sgpr_param(param) == (gprs < num_sgprs));
6247 assert(gprs + size <= num_sgprs + num_vgprs &&
6248 (gprs >= num_sgprs || gprs + size <= num_sgprs));
6249
6250 gprs += size;
6251 }
6252
6253 si_create_function(ctx, "wrapper", NULL, 0, &fninfo,
6254 si_get_max_workgroup_size(ctx->shader));
6255
6256 if (is_merged_shader(ctx->shader))
6257 si_init_exec_full_mask(ctx);
6258
6259 /* Record the arguments of the function as if they were an output of
6260 * a previous part.
6261 */
6262 num_out = 0;
6263 num_out_sgpr = 0;
6264
6265 for (unsigned i = 0; i < fninfo.num_params; ++i) {
6266 LLVMValueRef param = LLVMGetParam(ctx->main_fn, i);
6267 LLVMTypeRef param_type = LLVMTypeOf(param);
6268 LLVMTypeRef out_type = i < fninfo.num_sgpr_params ? ctx->i32 : ctx->f32;
6269 unsigned size = ac_get_type_size(param_type) / 4;
6270
6271 if (size == 1) {
6272 if (param_type != out_type)
6273 param = LLVMBuildBitCast(builder, param, out_type, "");
6274 out[num_out++] = param;
6275 } else {
6276 LLVMTypeRef vector_type = LLVMVectorType(out_type, size);
6277
6278 if (LLVMGetTypeKind(param_type) == LLVMPointerTypeKind) {
6279 param = LLVMBuildPtrToInt(builder, param, ctx->i64, "");
6280 param_type = ctx->i64;
6281 }
6282
6283 if (param_type != vector_type)
6284 param = LLVMBuildBitCast(builder, param, vector_type, "");
6285
6286 for (unsigned j = 0; j < size; ++j)
6287 out[num_out++] = LLVMBuildExtractElement(
6288 builder, param, LLVMConstInt(ctx->i32, j, 0), "");
6289 }
6290
6291 if (i < fninfo.num_sgpr_params)
6292 num_out_sgpr = num_out;
6293 }
6294
6295 memcpy(initial, out, sizeof(out));
6296 initial_num_out = num_out;
6297 initial_num_out_sgpr = num_out_sgpr;
6298
6299 /* Now chain the parts. */
6300 for (unsigned part = 0; part < num_parts; ++part) {
6301 LLVMValueRef in[48];
6302 LLVMValueRef ret;
6303 LLVMTypeRef ret_type;
6304 unsigned out_idx = 0;
6305 unsigned num_params = LLVMCountParams(parts[part]);
6306
6307 /* Merged shaders are executed conditionally depending
6308 * on the number of enabled threads passed in the input SGPRs. */
6309 if (is_merged_shader(ctx->shader) && part == 0) {
6310 LLVMValueRef ena, count = initial[3];
6311
6312 count = LLVMBuildAnd(builder, count,
6313 LLVMConstInt(ctx->i32, 0x7f, 0), "");
6314 ena = LLVMBuildICmp(builder, LLVMIntULT,
6315 ac_get_thread_id(&ctx->ac), count, "");
6316 lp_build_if(&if_state, &ctx->gallivm, ena);
6317 }
6318
6319 /* Derive arguments for the next part from outputs of the
6320 * previous one.
6321 */
6322 for (unsigned param_idx = 0; param_idx < num_params; ++param_idx) {
6323 LLVMValueRef param;
6324 LLVMTypeRef param_type;
6325 bool is_sgpr;
6326 unsigned param_size;
6327 LLVMValueRef arg = NULL;
6328
6329 param = LLVMGetParam(parts[part], param_idx);
6330 param_type = LLVMTypeOf(param);
6331 param_size = ac_get_type_size(param_type) / 4;
6332 is_sgpr = ac_is_sgpr_param(param);
6333
6334 if (is_sgpr) {
6335 #if HAVE_LLVM < 0x0400
6336 LLVMRemoveAttribute(param, LLVMByValAttribute);
6337 #else
6338 unsigned kind_id = LLVMGetEnumAttributeKindForName("byval", 5);
6339 LLVMRemoveEnumAttributeAtIndex(parts[part], param_idx + 1, kind_id);
6340 #endif
6341 lp_add_function_attr(parts[part], param_idx + 1, LP_FUNC_ATTR_INREG);
6342 }
6343
6344 assert(out_idx + param_size <= (is_sgpr ? num_out_sgpr : num_out));
6345 assert(is_sgpr || out_idx >= num_out_sgpr);
6346
6347 if (param_size == 1)
6348 arg = out[out_idx];
6349 else
6350 arg = lp_build_gather_values(&ctx->gallivm, &out[out_idx], param_size);
6351
6352 if (LLVMTypeOf(arg) != param_type) {
6353 if (LLVMGetTypeKind(param_type) == LLVMPointerTypeKind) {
6354 arg = LLVMBuildBitCast(builder, arg, ctx->i64, "");
6355 arg = LLVMBuildIntToPtr(builder, arg, param_type, "");
6356 } else {
6357 arg = LLVMBuildBitCast(builder, arg, param_type, "");
6358 }
6359 }
6360
6361 in[param_idx] = arg;
6362 out_idx += param_size;
6363 }
6364
6365 ret = LLVMBuildCall(builder, parts[part], in, num_params, "");
6366
6367 if (is_merged_shader(ctx->shader) &&
6368 part + 1 == next_shader_first_part) {
6369 lp_build_endif(&if_state);
6370
6371 /* The second half of the merged shader should use
6372 * the inputs from the toplevel (wrapper) function,
6373 * not the return value from the last call.
6374 *
6375 * That's because the last call was executed condi-
6376 * tionally, so we can't consume it in the main
6377 * block.
6378 */
6379 memcpy(out, initial, sizeof(initial));
6380 num_out = initial_num_out;
6381 num_out_sgpr = initial_num_out_sgpr;
6382 continue;
6383 }
6384
6385 /* Extract the returned GPRs. */
6386 ret_type = LLVMTypeOf(ret);
6387 num_out = 0;
6388 num_out_sgpr = 0;
6389
6390 if (LLVMGetTypeKind(ret_type) != LLVMVoidTypeKind) {
6391 assert(LLVMGetTypeKind(ret_type) == LLVMStructTypeKind);
6392
6393 unsigned ret_size = LLVMCountStructElementTypes(ret_type);
6394
6395 for (unsigned i = 0; i < ret_size; ++i) {
6396 LLVMValueRef val =
6397 LLVMBuildExtractValue(builder, ret, i, "");
6398
6399 assert(num_out < ARRAY_SIZE(out));
6400 out[num_out++] = val;
6401
6402 if (LLVMTypeOf(val) == ctx->i32) {
6403 assert(num_out_sgpr + 1 == num_out);
6404 num_out_sgpr = num_out;
6405 }
6406 }
6407 }
6408 }
6409
6410 LLVMBuildRetVoid(builder);
6411 }
6412
6413 int si_compile_tgsi_shader(struct si_screen *sscreen,
6414 LLVMTargetMachineRef tm,
6415 struct si_shader *shader,
6416 bool is_monolithic,
6417 struct pipe_debug_callback *debug)
6418 {
6419 struct si_shader_selector *sel = shader->selector;
6420 struct si_shader_context ctx;
6421 int r = -1;
6422
6423 /* Dump TGSI code before doing TGSI->LLVM conversion in case the
6424 * conversion fails. */
6425 if (si_can_dump_shader(&sscreen->b, sel->info.processor) &&
6426 !(sscreen->b.debug_flags & DBG(NO_TGSI))) {
6427 if (sel->tokens)
6428 tgsi_dump(sel->tokens, 0);
6429 else
6430 nir_print_shader(sel->nir, stderr);
6431 si_dump_streamout(&sel->so);
6432 }
6433
6434 si_init_shader_ctx(&ctx, sscreen, tm);
6435 si_llvm_context_set_tgsi(&ctx, shader);
6436 ctx.separate_prolog = !is_monolithic;
6437
6438 memset(shader->info.vs_output_param_offset, AC_EXP_PARAM_UNDEFINED,
6439 sizeof(shader->info.vs_output_param_offset));
6440
6441 shader->info.uses_instanceid = sel->info.uses_instanceid;
6442
6443 if (!si_compile_tgsi_main(&ctx, is_monolithic)) {
6444 si_llvm_dispose(&ctx);
6445 return -1;
6446 }
6447
6448 if (is_monolithic && ctx.type == PIPE_SHADER_VERTEX) {
6449 LLVMValueRef parts[2];
6450 bool need_prolog = sel->vs_needs_prolog;
6451
6452 parts[1] = ctx.main_fn;
6453
6454 if (need_prolog) {
6455 union si_shader_part_key prolog_key;
6456 si_get_vs_prolog_key(&sel->info,
6457 shader->info.num_input_sgprs,
6458 &shader->key.part.vs.prolog,
6459 shader, &prolog_key);
6460 si_build_vs_prolog_function(&ctx, &prolog_key);
6461 parts[0] = ctx.main_fn;
6462 }
6463
6464 si_build_wrapper_function(&ctx, parts + !need_prolog,
6465 1 + need_prolog, need_prolog, 0);
6466 } else if (is_monolithic && ctx.type == PIPE_SHADER_TESS_CTRL) {
6467 if (sscreen->b.chip_class >= GFX9) {
6468 struct si_shader_selector *ls = shader->key.part.tcs.ls;
6469 LLVMValueRef parts[4];
6470 bool vs_needs_prolog =
6471 si_vs_needs_prolog(ls, &shader->key.part.tcs.ls_prolog);
6472
6473 /* TCS main part */
6474 parts[2] = ctx.main_fn;
6475
6476 /* TCS epilog */
6477 union si_shader_part_key tcs_epilog_key;
6478 memset(&tcs_epilog_key, 0, sizeof(tcs_epilog_key));
6479 tcs_epilog_key.tcs_epilog.states = shader->key.part.tcs.epilog;
6480 si_build_tcs_epilog_function(&ctx, &tcs_epilog_key);
6481 parts[3] = ctx.main_fn;
6482
6483 /* VS prolog */
6484 if (vs_needs_prolog) {
6485 union si_shader_part_key vs_prolog_key;
6486 si_get_vs_prolog_key(&ls->info,
6487 shader->info.num_input_sgprs,
6488 &shader->key.part.tcs.ls_prolog,
6489 shader, &vs_prolog_key);
6490 vs_prolog_key.vs_prolog.is_monolithic = true;
6491 si_build_vs_prolog_function(&ctx, &vs_prolog_key);
6492 parts[0] = ctx.main_fn;
6493 }
6494
6495 /* VS as LS main part */
6496 struct si_shader shader_ls = {};
6497 shader_ls.selector = ls;
6498 shader_ls.key.as_ls = 1;
6499 shader_ls.key.mono = shader->key.mono;
6500 shader_ls.key.opt = shader->key.opt;
6501 si_llvm_context_set_tgsi(&ctx, &shader_ls);
6502
6503 if (!si_compile_tgsi_main(&ctx, true)) {
6504 si_llvm_dispose(&ctx);
6505 return -1;
6506 }
6507 shader->info.uses_instanceid |= ls->info.uses_instanceid;
6508 parts[1] = ctx.main_fn;
6509
6510 /* Reset the shader context. */
6511 ctx.shader = shader;
6512 ctx.type = PIPE_SHADER_TESS_CTRL;
6513
6514 si_build_wrapper_function(&ctx,
6515 parts + !vs_needs_prolog,
6516 4 - !vs_needs_prolog, 0,
6517 vs_needs_prolog ? 2 : 1);
6518 } else {
6519 LLVMValueRef parts[2];
6520 union si_shader_part_key epilog_key;
6521
6522 parts[0] = ctx.main_fn;
6523
6524 memset(&epilog_key, 0, sizeof(epilog_key));
6525 epilog_key.tcs_epilog.states = shader->key.part.tcs.epilog;
6526 si_build_tcs_epilog_function(&ctx, &epilog_key);
6527 parts[1] = ctx.main_fn;
6528
6529 si_build_wrapper_function(&ctx, parts, 2, 0, 0);
6530 }
6531 } else if (is_monolithic && ctx.type == PIPE_SHADER_GEOMETRY) {
6532 if (ctx.screen->b.chip_class >= GFX9) {
6533 struct si_shader_selector *es = shader->key.part.gs.es;
6534 LLVMValueRef es_prolog = NULL;
6535 LLVMValueRef es_main = NULL;
6536 LLVMValueRef gs_prolog = NULL;
6537 LLVMValueRef gs_main = ctx.main_fn;
6538
6539 /* GS prolog */
6540 union si_shader_part_key gs_prolog_key;
6541 memset(&gs_prolog_key, 0, sizeof(gs_prolog_key));
6542 gs_prolog_key.gs_prolog.states = shader->key.part.gs.prolog;
6543 gs_prolog_key.gs_prolog.is_monolithic = true;
6544 si_build_gs_prolog_function(&ctx, &gs_prolog_key);
6545 gs_prolog = ctx.main_fn;
6546
6547 /* ES prolog */
6548 if (es->vs_needs_prolog) {
6549 union si_shader_part_key vs_prolog_key;
6550 si_get_vs_prolog_key(&es->info,
6551 shader->info.num_input_sgprs,
6552 &shader->key.part.tcs.ls_prolog,
6553 shader, &vs_prolog_key);
6554 vs_prolog_key.vs_prolog.is_monolithic = true;
6555 si_build_vs_prolog_function(&ctx, &vs_prolog_key);
6556 es_prolog = ctx.main_fn;
6557 }
6558
6559 /* ES main part */
6560 struct si_shader shader_es = {};
6561 shader_es.selector = es;
6562 shader_es.key.as_es = 1;
6563 shader_es.key.mono = shader->key.mono;
6564 shader_es.key.opt = shader->key.opt;
6565 si_llvm_context_set_tgsi(&ctx, &shader_es);
6566
6567 if (!si_compile_tgsi_main(&ctx, true)) {
6568 si_llvm_dispose(&ctx);
6569 return -1;
6570 }
6571 shader->info.uses_instanceid |= es->info.uses_instanceid;
6572 es_main = ctx.main_fn;
6573
6574 /* Reset the shader context. */
6575 ctx.shader = shader;
6576 ctx.type = PIPE_SHADER_GEOMETRY;
6577
6578 /* Prepare the array of shader parts. */
6579 LLVMValueRef parts[4];
6580 unsigned num_parts = 0, main_part, next_first_part;
6581
6582 if (es_prolog)
6583 parts[num_parts++] = es_prolog;
6584
6585 parts[main_part = num_parts++] = es_main;
6586 parts[next_first_part = num_parts++] = gs_prolog;
6587 parts[num_parts++] = gs_main;
6588
6589 si_build_wrapper_function(&ctx, parts, num_parts,
6590 main_part, next_first_part);
6591 } else {
6592 LLVMValueRef parts[2];
6593 union si_shader_part_key prolog_key;
6594
6595 parts[1] = ctx.main_fn;
6596
6597 memset(&prolog_key, 0, sizeof(prolog_key));
6598 prolog_key.gs_prolog.states = shader->key.part.gs.prolog;
6599 si_build_gs_prolog_function(&ctx, &prolog_key);
6600 parts[0] = ctx.main_fn;
6601
6602 si_build_wrapper_function(&ctx, parts, 2, 1, 0);
6603 }
6604 } else if (is_monolithic && ctx.type == PIPE_SHADER_FRAGMENT) {
6605 LLVMValueRef parts[3];
6606 union si_shader_part_key prolog_key;
6607 union si_shader_part_key epilog_key;
6608 bool need_prolog;
6609
6610 si_get_ps_prolog_key(shader, &prolog_key, false);
6611 need_prolog = si_need_ps_prolog(&prolog_key);
6612
6613 parts[need_prolog ? 1 : 0] = ctx.main_fn;
6614
6615 if (need_prolog) {
6616 si_build_ps_prolog_function(&ctx, &prolog_key);
6617 parts[0] = ctx.main_fn;
6618 }
6619
6620 si_get_ps_epilog_key(shader, &epilog_key);
6621 si_build_ps_epilog_function(&ctx, &epilog_key);
6622 parts[need_prolog ? 2 : 1] = ctx.main_fn;
6623
6624 si_build_wrapper_function(&ctx, parts, need_prolog ? 3 : 2,
6625 need_prolog ? 1 : 0, 0);
6626 }
6627
6628 si_llvm_optimize_module(&ctx);
6629
6630 /* Post-optimization transformations and analysis. */
6631 si_optimize_vs_outputs(&ctx);
6632
6633 if ((debug && debug->debug_message) ||
6634 si_can_dump_shader(&sscreen->b, ctx.type))
6635 si_count_scratch_private_memory(&ctx);
6636
6637 /* Compile to bytecode. */
6638 r = si_compile_llvm(sscreen, &shader->binary, &shader->config, tm,
6639 ctx.gallivm.module, debug, ctx.type, "TGSI shader");
6640 si_llvm_dispose(&ctx);
6641 if (r) {
6642 fprintf(stderr, "LLVM failed to compile shader\n");
6643 return r;
6644 }
6645
6646 /* Validate SGPR and VGPR usage for compute to detect compiler bugs.
6647 * LLVM 3.9svn has this bug.
6648 */
6649 if (sel->type == PIPE_SHADER_COMPUTE) {
6650 unsigned wave_size = 64;
6651 unsigned max_vgprs = 256;
6652 unsigned max_sgprs = sscreen->b.chip_class >= VI ? 800 : 512;
6653 unsigned max_sgprs_per_wave = 128;
6654 unsigned max_block_threads = si_get_max_workgroup_size(shader);
6655 unsigned min_waves_per_cu = DIV_ROUND_UP(max_block_threads, wave_size);
6656 unsigned min_waves_per_simd = DIV_ROUND_UP(min_waves_per_cu, 4);
6657
6658 max_vgprs = max_vgprs / min_waves_per_simd;
6659 max_sgprs = MIN2(max_sgprs / min_waves_per_simd, max_sgprs_per_wave);
6660
6661 if (shader->config.num_sgprs > max_sgprs ||
6662 shader->config.num_vgprs > max_vgprs) {
6663 fprintf(stderr, "LLVM failed to compile a shader correctly: "
6664 "SGPR:VGPR usage is %u:%u, but the hw limit is %u:%u\n",
6665 shader->config.num_sgprs, shader->config.num_vgprs,
6666 max_sgprs, max_vgprs);
6667
6668 /* Just terminate the process, because dependent
6669 * shaders can hang due to bad input data, but use
6670 * the env var to allow shader-db to work.
6671 */
6672 if (!debug_get_bool_option("SI_PASS_BAD_SHADERS", false))
6673 abort();
6674 }
6675 }
6676
6677 /* Add the scratch offset to input SGPRs. */
6678 if (shader->config.scratch_bytes_per_wave && !is_merged_shader(shader))
6679 shader->info.num_input_sgprs += 1; /* scratch byte offset */
6680
6681 /* Calculate the number of fragment input VGPRs. */
6682 if (ctx.type == PIPE_SHADER_FRAGMENT) {
6683 shader->info.num_input_vgprs = 0;
6684 shader->info.face_vgpr_index = -1;
6685 shader->info.ancillary_vgpr_index = -1;
6686
6687 if (G_0286CC_PERSP_SAMPLE_ENA(shader->config.spi_ps_input_addr))
6688 shader->info.num_input_vgprs += 2;
6689 if (G_0286CC_PERSP_CENTER_ENA(shader->config.spi_ps_input_addr))
6690 shader->info.num_input_vgprs += 2;
6691 if (G_0286CC_PERSP_CENTROID_ENA(shader->config.spi_ps_input_addr))
6692 shader->info.num_input_vgprs += 2;
6693 if (G_0286CC_PERSP_PULL_MODEL_ENA(shader->config.spi_ps_input_addr))
6694 shader->info.num_input_vgprs += 3;
6695 if (G_0286CC_LINEAR_SAMPLE_ENA(shader->config.spi_ps_input_addr))
6696 shader->info.num_input_vgprs += 2;
6697 if (G_0286CC_LINEAR_CENTER_ENA(shader->config.spi_ps_input_addr))
6698 shader->info.num_input_vgprs += 2;
6699 if (G_0286CC_LINEAR_CENTROID_ENA(shader->config.spi_ps_input_addr))
6700 shader->info.num_input_vgprs += 2;
6701 if (G_0286CC_LINE_STIPPLE_TEX_ENA(shader->config.spi_ps_input_addr))
6702 shader->info.num_input_vgprs += 1;
6703 if (G_0286CC_POS_X_FLOAT_ENA(shader->config.spi_ps_input_addr))
6704 shader->info.num_input_vgprs += 1;
6705 if (G_0286CC_POS_Y_FLOAT_ENA(shader->config.spi_ps_input_addr))
6706 shader->info.num_input_vgprs += 1;
6707 if (G_0286CC_POS_Z_FLOAT_ENA(shader->config.spi_ps_input_addr))
6708 shader->info.num_input_vgprs += 1;
6709 if (G_0286CC_POS_W_FLOAT_ENA(shader->config.spi_ps_input_addr))
6710 shader->info.num_input_vgprs += 1;
6711 if (G_0286CC_FRONT_FACE_ENA(shader->config.spi_ps_input_addr)) {
6712 shader->info.face_vgpr_index = shader->info.num_input_vgprs;
6713 shader->info.num_input_vgprs += 1;
6714 }
6715 if (G_0286CC_ANCILLARY_ENA(shader->config.spi_ps_input_addr)) {
6716 shader->info.ancillary_vgpr_index = shader->info.num_input_vgprs;
6717 shader->info.num_input_vgprs += 1;
6718 }
6719 if (G_0286CC_SAMPLE_COVERAGE_ENA(shader->config.spi_ps_input_addr))
6720 shader->info.num_input_vgprs += 1;
6721 if (G_0286CC_POS_FIXED_PT_ENA(shader->config.spi_ps_input_addr))
6722 shader->info.num_input_vgprs += 1;
6723 }
6724
6725 return 0;
6726 }
6727
6728 /**
6729 * Create, compile and return a shader part (prolog or epilog).
6730 *
6731 * \param sscreen screen
6732 * \param list list of shader parts of the same category
6733 * \param type shader type
6734 * \param key shader part key
6735 * \param prolog whether the part being requested is a prolog
6736 * \param tm LLVM target machine
6737 * \param debug debug callback
6738 * \param build the callback responsible for building the main function
6739 * \return non-NULL on success
6740 */
6741 static struct si_shader_part *
6742 si_get_shader_part(struct si_screen *sscreen,
6743 struct si_shader_part **list,
6744 enum pipe_shader_type type,
6745 bool prolog,
6746 union si_shader_part_key *key,
6747 LLVMTargetMachineRef tm,
6748 struct pipe_debug_callback *debug,
6749 void (*build)(struct si_shader_context *,
6750 union si_shader_part_key *),
6751 const char *name)
6752 {
6753 struct si_shader_part *result;
6754
6755 mtx_lock(&sscreen->shader_parts_mutex);
6756
6757 /* Find existing. */
6758 for (result = *list; result; result = result->next) {
6759 if (memcmp(&result->key, key, sizeof(*key)) == 0) {
6760 mtx_unlock(&sscreen->shader_parts_mutex);
6761 return result;
6762 }
6763 }
6764
6765 /* Compile a new one. */
6766 result = CALLOC_STRUCT(si_shader_part);
6767 result->key = *key;
6768
6769 struct si_shader shader = {};
6770 struct si_shader_context ctx;
6771
6772 si_init_shader_ctx(&ctx, sscreen, tm);
6773 ctx.shader = &shader;
6774 ctx.type = type;
6775
6776 switch (type) {
6777 case PIPE_SHADER_VERTEX:
6778 break;
6779 case PIPE_SHADER_TESS_CTRL:
6780 assert(!prolog);
6781 shader.key.part.tcs.epilog = key->tcs_epilog.states;
6782 break;
6783 case PIPE_SHADER_GEOMETRY:
6784 assert(prolog);
6785 break;
6786 case PIPE_SHADER_FRAGMENT:
6787 if (prolog)
6788 shader.key.part.ps.prolog = key->ps_prolog.states;
6789 else
6790 shader.key.part.ps.epilog = key->ps_epilog.states;
6791 break;
6792 default:
6793 unreachable("bad shader part");
6794 }
6795
6796 build(&ctx, key);
6797
6798 /* Compile. */
6799 si_llvm_optimize_module(&ctx);
6800
6801 if (si_compile_llvm(sscreen, &result->binary, &result->config, tm,
6802 ctx.ac.module, debug, ctx.type, name)) {
6803 FREE(result);
6804 result = NULL;
6805 goto out;
6806 }
6807
6808 result->next = *list;
6809 *list = result;
6810
6811 out:
6812 si_llvm_dispose(&ctx);
6813 mtx_unlock(&sscreen->shader_parts_mutex);
6814 return result;
6815 }
6816
6817 static LLVMValueRef si_prolog_get_rw_buffers(struct si_shader_context *ctx)
6818 {
6819 LLVMValueRef ptr[2], list;
6820
6821 /* Get the pointer to rw buffers. */
6822 ptr[0] = LLVMGetParam(ctx->main_fn, SI_SGPR_RW_BUFFERS);
6823 ptr[1] = LLVMGetParam(ctx->main_fn, SI_SGPR_RW_BUFFERS_HI);
6824 list = lp_build_gather_values(&ctx->gallivm, ptr, 2);
6825 list = LLVMBuildBitCast(ctx->ac.builder, list, ctx->i64, "");
6826 list = LLVMBuildIntToPtr(ctx->ac.builder, list,
6827 si_const_array(ctx->v4i32, SI_NUM_RW_BUFFERS), "");
6828 return list;
6829 }
6830
6831 /**
6832 * Build the vertex shader prolog function.
6833 *
6834 * The inputs are the same as VS (a lot of SGPRs and 4 VGPR system values).
6835 * All inputs are returned unmodified. The vertex load indices are
6836 * stored after them, which will be used by the API VS for fetching inputs.
6837 *
6838 * For example, the expected outputs for instance_divisors[] = {0, 1, 2} are:
6839 * input_v0,
6840 * input_v1,
6841 * input_v2,
6842 * input_v3,
6843 * (VertexID + BaseVertex),
6844 * (InstanceID + StartInstance),
6845 * (InstanceID / 2 + StartInstance)
6846 */
6847 static void si_build_vs_prolog_function(struct si_shader_context *ctx,
6848 union si_shader_part_key *key)
6849 {
6850 struct si_function_info fninfo;
6851 LLVMTypeRef *returns;
6852 LLVMValueRef ret, func;
6853 int num_returns, i;
6854 unsigned first_vs_vgpr = key->vs_prolog.num_merged_next_stage_vgprs;
6855 unsigned num_input_vgprs = key->vs_prolog.num_merged_next_stage_vgprs + 4;
6856 LLVMValueRef input_vgprs[9];
6857 unsigned num_all_input_regs = key->vs_prolog.num_input_sgprs +
6858 num_input_vgprs;
6859 unsigned user_sgpr_base = key->vs_prolog.num_merged_next_stage_vgprs ? 8 : 0;
6860
6861 si_init_function_info(&fninfo);
6862
6863 /* 4 preloaded VGPRs + vertex load indices as prolog outputs */
6864 returns = alloca((num_all_input_regs + key->vs_prolog.last_input + 1) *
6865 sizeof(LLVMTypeRef));
6866 num_returns = 0;
6867
6868 /* Declare input and output SGPRs. */
6869 for (i = 0; i < key->vs_prolog.num_input_sgprs; i++) {
6870 add_arg(&fninfo, ARG_SGPR, ctx->i32);
6871 returns[num_returns++] = ctx->i32;
6872 }
6873
6874 /* Preloaded VGPRs (outputs must be floats) */
6875 for (i = 0; i < num_input_vgprs; i++) {
6876 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &input_vgprs[i]);
6877 returns[num_returns++] = ctx->f32;
6878 }
6879
6880 /* Vertex load indices. */
6881 for (i = 0; i <= key->vs_prolog.last_input; i++)
6882 returns[num_returns++] = ctx->f32;
6883
6884 /* Create the function. */
6885 si_create_function(ctx, "vs_prolog", returns, num_returns, &fninfo, 0);
6886 func = ctx->main_fn;
6887
6888 if (key->vs_prolog.num_merged_next_stage_vgprs) {
6889 if (!key->vs_prolog.is_monolithic)
6890 si_init_exec_from_input(ctx, 3, 0);
6891
6892 if (key->vs_prolog.as_ls &&
6893 (ctx->screen->b.family == CHIP_VEGA10 ||
6894 ctx->screen->b.family == CHIP_RAVEN)) {
6895 /* If there are no HS threads, SPI loads the LS VGPRs
6896 * starting at VGPR 0. Shift them back to where they
6897 * belong.
6898 */
6899 LLVMValueRef has_hs_threads =
6900 LLVMBuildICmp(ctx->ac.builder, LLVMIntNE,
6901 unpack_param(ctx, 3, 8, 8),
6902 ctx->i32_0, "");
6903
6904 for (i = 4; i > 0; --i) {
6905 input_vgprs[i + 1] =
6906 LLVMBuildSelect(ctx->ac.builder, has_hs_threads,
6907 input_vgprs[i + 1],
6908 input_vgprs[i - 1], "");
6909 }
6910 }
6911 }
6912
6913 ctx->abi.vertex_id = input_vgprs[first_vs_vgpr];
6914 ctx->abi.instance_id = input_vgprs[first_vs_vgpr + (key->vs_prolog.as_ls ? 2 : 1)];
6915
6916 /* Copy inputs to outputs. This should be no-op, as the registers match,
6917 * but it will prevent the compiler from overwriting them unintentionally.
6918 */
6919 ret = ctx->return_value;
6920 for (i = 0; i < key->vs_prolog.num_input_sgprs; i++) {
6921 LLVMValueRef p = LLVMGetParam(func, i);
6922 ret = LLVMBuildInsertValue(ctx->ac.builder, ret, p, i, "");
6923 }
6924 for (i = 0; i < num_input_vgprs; i++) {
6925 LLVMValueRef p = input_vgprs[i];
6926 p = ac_to_float(&ctx->ac, p);
6927 ret = LLVMBuildInsertValue(ctx->ac.builder, ret, p,
6928 key->vs_prolog.num_input_sgprs + i, "");
6929 }
6930
6931 /* Compute vertex load indices from instance divisors. */
6932 LLVMValueRef instance_divisor_constbuf = NULL;
6933
6934 if (key->vs_prolog.states.instance_divisor_is_fetched) {
6935 LLVMValueRef list = si_prolog_get_rw_buffers(ctx);
6936 LLVMValueRef buf_index =
6937 LLVMConstInt(ctx->i32, SI_VS_CONST_INSTANCE_DIVISORS, 0);
6938 instance_divisor_constbuf =
6939 ac_build_load_to_sgpr(&ctx->ac, list, buf_index);
6940 }
6941
6942 for (i = 0; i <= key->vs_prolog.last_input; i++) {
6943 bool divisor_is_one =
6944 key->vs_prolog.states.instance_divisor_is_one & (1u << i);
6945 bool divisor_is_fetched =
6946 key->vs_prolog.states.instance_divisor_is_fetched & (1u << i);
6947 LLVMValueRef index;
6948
6949 if (divisor_is_one || divisor_is_fetched) {
6950 LLVMValueRef divisor = ctx->i32_1;
6951
6952 if (divisor_is_fetched) {
6953 divisor = buffer_load_const(ctx, instance_divisor_constbuf,
6954 LLVMConstInt(ctx->i32, i * 4, 0));
6955 divisor = ac_to_integer(&ctx->ac, divisor);
6956 }
6957
6958 /* InstanceID / Divisor + StartInstance */
6959 index = get_instance_index_for_fetch(ctx,
6960 user_sgpr_base +
6961 SI_SGPR_START_INSTANCE,
6962 divisor);
6963 } else {
6964 /* VertexID + BaseVertex */
6965 index = LLVMBuildAdd(ctx->ac.builder,
6966 ctx->abi.vertex_id,
6967 LLVMGetParam(func, user_sgpr_base +
6968 SI_SGPR_BASE_VERTEX), "");
6969 }
6970
6971 index = ac_to_float(&ctx->ac, index);
6972 ret = LLVMBuildInsertValue(ctx->ac.builder, ret, index,
6973 fninfo.num_params + i, "");
6974 }
6975
6976 si_llvm_build_ret(ctx, ret);
6977 }
6978
6979 static bool si_get_vs_prolog(struct si_screen *sscreen,
6980 LLVMTargetMachineRef tm,
6981 struct si_shader *shader,
6982 struct pipe_debug_callback *debug,
6983 struct si_shader *main_part,
6984 const struct si_vs_prolog_bits *key)
6985 {
6986 struct si_shader_selector *vs = main_part->selector;
6987
6988 if (!si_vs_needs_prolog(vs, key))
6989 return true;
6990
6991 /* Get the prolog. */
6992 union si_shader_part_key prolog_key;
6993 si_get_vs_prolog_key(&vs->info, main_part->info.num_input_sgprs,
6994 key, shader, &prolog_key);
6995
6996 shader->prolog =
6997 si_get_shader_part(sscreen, &sscreen->vs_prologs,
6998 PIPE_SHADER_VERTEX, true, &prolog_key, tm,
6999 debug, si_build_vs_prolog_function,
7000 "Vertex Shader Prolog");
7001 return shader->prolog != NULL;
7002 }
7003
7004 /**
7005 * Select and compile (or reuse) vertex shader parts (prolog & epilog).
7006 */
7007 static bool si_shader_select_vs_parts(struct si_screen *sscreen,
7008 LLVMTargetMachineRef tm,
7009 struct si_shader *shader,
7010 struct pipe_debug_callback *debug)
7011 {
7012 return si_get_vs_prolog(sscreen, tm, shader, debug, shader,
7013 &shader->key.part.vs.prolog);
7014 }
7015
7016 /**
7017 * Compile the TCS epilog function. This writes tesselation factors to memory
7018 * based on the output primitive type of the tesselator (determined by TES).
7019 */
7020 static void si_build_tcs_epilog_function(struct si_shader_context *ctx,
7021 union si_shader_part_key *key)
7022 {
7023 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
7024 struct si_function_info fninfo;
7025 LLVMValueRef func;
7026
7027 si_init_function_info(&fninfo);
7028
7029 if (ctx->screen->b.chip_class >= GFX9) {
7030 add_arg(&fninfo, ARG_SGPR, ctx->i64);
7031 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7032 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* wave info */
7033 ctx->param_tcs_factor_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7034 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7035 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7036 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7037 add_arg(&fninfo, ARG_SGPR, ctx->i64);
7038 add_arg(&fninfo, ARG_SGPR, ctx->i64);
7039 add_arg(&fninfo, ARG_SGPR, ctx->i64);
7040 add_arg(&fninfo, ARG_SGPR, ctx->i64);
7041 add_arg(&fninfo, ARG_SGPR, ctx->i64);
7042 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7043 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7044 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7045 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7046 ctx->param_tcs_offchip_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7047 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7048 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7049 ctx->param_tcs_offchip_addr_base64k = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7050 ctx->param_tcs_factor_addr_base64k = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7051 } else {
7052 add_arg(&fninfo, ARG_SGPR, ctx->i64);
7053 add_arg(&fninfo, ARG_SGPR, ctx->i64);
7054 add_arg(&fninfo, ARG_SGPR, ctx->i64);
7055 add_arg(&fninfo, ARG_SGPR, ctx->i64);
7056 ctx->param_tcs_offchip_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7057 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7058 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7059 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7060 ctx->param_tcs_offchip_addr_base64k = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7061 ctx->param_tcs_factor_addr_base64k = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7062 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7063 ctx->param_tcs_factor_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7064 }
7065
7066 add_arg(&fninfo, ARG_VGPR, ctx->i32); /* VGPR gap */
7067 add_arg(&fninfo, ARG_VGPR, ctx->i32); /* VGPR gap */
7068 unsigned tess_factors_idx =
7069 add_arg(&fninfo, ARG_VGPR, ctx->i32); /* patch index within the wave (REL_PATCH_ID) */
7070 add_arg(&fninfo, ARG_VGPR, ctx->i32); /* invocation ID within the patch */
7071 add_arg(&fninfo, ARG_VGPR, ctx->i32); /* LDS offset where tess factors should be loaded from */
7072
7073 for (unsigned i = 0; i < 6; i++)
7074 add_arg(&fninfo, ARG_VGPR, ctx->i32); /* tess factors */
7075
7076 /* Create the function. */
7077 si_create_function(ctx, "tcs_epilog", NULL, 0, &fninfo,
7078 ctx->screen->b.chip_class >= CIK ? 128 : 64);
7079 declare_lds_as_pointer(ctx);
7080 func = ctx->main_fn;
7081
7082 LLVMValueRef invoc0_tess_factors[6];
7083 for (unsigned i = 0; i < 6; i++)
7084 invoc0_tess_factors[i] = LLVMGetParam(func, tess_factors_idx + 3 + i);
7085
7086 si_write_tess_factors(bld_base,
7087 LLVMGetParam(func, tess_factors_idx),
7088 LLVMGetParam(func, tess_factors_idx + 1),
7089 LLVMGetParam(func, tess_factors_idx + 2),
7090 invoc0_tess_factors, invoc0_tess_factors + 4);
7091
7092 LLVMBuildRetVoid(ctx->ac.builder);
7093 }
7094
7095 /**
7096 * Select and compile (or reuse) TCS parts (epilog).
7097 */
7098 static bool si_shader_select_tcs_parts(struct si_screen *sscreen,
7099 LLVMTargetMachineRef tm,
7100 struct si_shader *shader,
7101 struct pipe_debug_callback *debug)
7102 {
7103 if (sscreen->b.chip_class >= GFX9) {
7104 struct si_shader *ls_main_part =
7105 shader->key.part.tcs.ls->main_shader_part_ls;
7106
7107 if (!si_get_vs_prolog(sscreen, tm, shader, debug, ls_main_part,
7108 &shader->key.part.tcs.ls_prolog))
7109 return false;
7110
7111 shader->previous_stage = ls_main_part;
7112 }
7113
7114 /* Get the epilog. */
7115 union si_shader_part_key epilog_key;
7116 memset(&epilog_key, 0, sizeof(epilog_key));
7117 epilog_key.tcs_epilog.states = shader->key.part.tcs.epilog;
7118
7119 shader->epilog = si_get_shader_part(sscreen, &sscreen->tcs_epilogs,
7120 PIPE_SHADER_TESS_CTRL, false,
7121 &epilog_key, tm, debug,
7122 si_build_tcs_epilog_function,
7123 "Tessellation Control Shader Epilog");
7124 return shader->epilog != NULL;
7125 }
7126
7127 /**
7128 * Select and compile (or reuse) GS parts (prolog).
7129 */
7130 static bool si_shader_select_gs_parts(struct si_screen *sscreen,
7131 LLVMTargetMachineRef tm,
7132 struct si_shader *shader,
7133 struct pipe_debug_callback *debug)
7134 {
7135 if (sscreen->b.chip_class >= GFX9) {
7136 struct si_shader *es_main_part =
7137 shader->key.part.gs.es->main_shader_part_es;
7138
7139 if (shader->key.part.gs.es->type == PIPE_SHADER_VERTEX &&
7140 !si_get_vs_prolog(sscreen, tm, shader, debug, es_main_part,
7141 &shader->key.part.gs.vs_prolog))
7142 return false;
7143
7144 shader->previous_stage = es_main_part;
7145 }
7146
7147 if (!shader->key.part.gs.prolog.tri_strip_adj_fix)
7148 return true;
7149
7150 union si_shader_part_key prolog_key;
7151 memset(&prolog_key, 0, sizeof(prolog_key));
7152 prolog_key.gs_prolog.states = shader->key.part.gs.prolog;
7153
7154 shader->prolog2 = si_get_shader_part(sscreen, &sscreen->gs_prologs,
7155 PIPE_SHADER_GEOMETRY, true,
7156 &prolog_key, tm, debug,
7157 si_build_gs_prolog_function,
7158 "Geometry Shader Prolog");
7159 return shader->prolog2 != NULL;
7160 }
7161
7162 /**
7163 * Build the pixel shader prolog function. This handles:
7164 * - two-side color selection and interpolation
7165 * - overriding interpolation parameters for the API PS
7166 * - polygon stippling
7167 *
7168 * All preloaded SGPRs and VGPRs are passed through unmodified unless they are
7169 * overriden by other states. (e.g. per-sample interpolation)
7170 * Interpolated colors are stored after the preloaded VGPRs.
7171 */
7172 static void si_build_ps_prolog_function(struct si_shader_context *ctx,
7173 union si_shader_part_key *key)
7174 {
7175 struct si_function_info fninfo;
7176 LLVMValueRef ret, func;
7177 int num_returns, i, num_color_channels;
7178
7179 assert(si_need_ps_prolog(key));
7180
7181 si_init_function_info(&fninfo);
7182
7183 /* Declare inputs. */
7184 for (i = 0; i < key->ps_prolog.num_input_sgprs; i++)
7185 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7186
7187 for (i = 0; i < key->ps_prolog.num_input_vgprs; i++)
7188 add_arg(&fninfo, ARG_VGPR, ctx->f32);
7189
7190 /* Declare outputs (same as inputs + add colors if needed) */
7191 num_returns = fninfo.num_params;
7192 num_color_channels = util_bitcount(key->ps_prolog.colors_read);
7193 for (i = 0; i < num_color_channels; i++)
7194 fninfo.types[num_returns++] = ctx->f32;
7195
7196 /* Create the function. */
7197 si_create_function(ctx, "ps_prolog", fninfo.types, num_returns,
7198 &fninfo, 0);
7199 func = ctx->main_fn;
7200
7201 /* Copy inputs to outputs. This should be no-op, as the registers match,
7202 * but it will prevent the compiler from overwriting them unintentionally.
7203 */
7204 ret = ctx->return_value;
7205 for (i = 0; i < fninfo.num_params; i++) {
7206 LLVMValueRef p = LLVMGetParam(func, i);
7207 ret = LLVMBuildInsertValue(ctx->ac.builder, ret, p, i, "");
7208 }
7209
7210 /* Polygon stippling. */
7211 if (key->ps_prolog.states.poly_stipple) {
7212 /* POS_FIXED_PT is always last. */
7213 unsigned pos = key->ps_prolog.num_input_sgprs +
7214 key->ps_prolog.num_input_vgprs - 1;
7215 LLVMValueRef list = si_prolog_get_rw_buffers(ctx);
7216
7217 si_llvm_emit_polygon_stipple(ctx, list, pos);
7218 }
7219
7220 if (key->ps_prolog.states.bc_optimize_for_persp ||
7221 key->ps_prolog.states.bc_optimize_for_linear) {
7222 unsigned i, base = key->ps_prolog.num_input_sgprs;
7223 LLVMValueRef center[2], centroid[2], tmp, bc_optimize;
7224
7225 /* The shader should do: if (PRIM_MASK[31]) CENTROID = CENTER;
7226 * The hw doesn't compute CENTROID if the whole wave only
7227 * contains fully-covered quads.
7228 *
7229 * PRIM_MASK is after user SGPRs.
7230 */
7231 bc_optimize = LLVMGetParam(func, SI_PS_NUM_USER_SGPR);
7232 bc_optimize = LLVMBuildLShr(ctx->ac.builder, bc_optimize,
7233 LLVMConstInt(ctx->i32, 31, 0), "");
7234 bc_optimize = LLVMBuildTrunc(ctx->ac.builder, bc_optimize,
7235 ctx->i1, "");
7236
7237 if (key->ps_prolog.states.bc_optimize_for_persp) {
7238 /* Read PERSP_CENTER. */
7239 for (i = 0; i < 2; i++)
7240 center[i] = LLVMGetParam(func, base + 2 + i);
7241 /* Read PERSP_CENTROID. */
7242 for (i = 0; i < 2; i++)
7243 centroid[i] = LLVMGetParam(func, base + 4 + i);
7244 /* Select PERSP_CENTROID. */
7245 for (i = 0; i < 2; i++) {
7246 tmp = LLVMBuildSelect(ctx->ac.builder, bc_optimize,
7247 center[i], centroid[i], "");
7248 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7249 tmp, base + 4 + i, "");
7250 }
7251 }
7252 if (key->ps_prolog.states.bc_optimize_for_linear) {
7253 /* Read LINEAR_CENTER. */
7254 for (i = 0; i < 2; i++)
7255 center[i] = LLVMGetParam(func, base + 8 + i);
7256 /* Read LINEAR_CENTROID. */
7257 for (i = 0; i < 2; i++)
7258 centroid[i] = LLVMGetParam(func, base + 10 + i);
7259 /* Select LINEAR_CENTROID. */
7260 for (i = 0; i < 2; i++) {
7261 tmp = LLVMBuildSelect(ctx->ac.builder, bc_optimize,
7262 center[i], centroid[i], "");
7263 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7264 tmp, base + 10 + i, "");
7265 }
7266 }
7267 }
7268
7269 /* Force per-sample interpolation. */
7270 if (key->ps_prolog.states.force_persp_sample_interp) {
7271 unsigned i, base = key->ps_prolog.num_input_sgprs;
7272 LLVMValueRef persp_sample[2];
7273
7274 /* Read PERSP_SAMPLE. */
7275 for (i = 0; i < 2; i++)
7276 persp_sample[i] = LLVMGetParam(func, base + i);
7277 /* Overwrite PERSP_CENTER. */
7278 for (i = 0; i < 2; i++)
7279 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7280 persp_sample[i], base + 2 + i, "");
7281 /* Overwrite PERSP_CENTROID. */
7282 for (i = 0; i < 2; i++)
7283 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7284 persp_sample[i], base + 4 + i, "");
7285 }
7286 if (key->ps_prolog.states.force_linear_sample_interp) {
7287 unsigned i, base = key->ps_prolog.num_input_sgprs;
7288 LLVMValueRef linear_sample[2];
7289
7290 /* Read LINEAR_SAMPLE. */
7291 for (i = 0; i < 2; i++)
7292 linear_sample[i] = LLVMGetParam(func, base + 6 + i);
7293 /* Overwrite LINEAR_CENTER. */
7294 for (i = 0; i < 2; i++)
7295 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7296 linear_sample[i], base + 8 + i, "");
7297 /* Overwrite LINEAR_CENTROID. */
7298 for (i = 0; i < 2; i++)
7299 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7300 linear_sample[i], base + 10 + i, "");
7301 }
7302
7303 /* Force center interpolation. */
7304 if (key->ps_prolog.states.force_persp_center_interp) {
7305 unsigned i, base = key->ps_prolog.num_input_sgprs;
7306 LLVMValueRef persp_center[2];
7307
7308 /* Read PERSP_CENTER. */
7309 for (i = 0; i < 2; i++)
7310 persp_center[i] = LLVMGetParam(func, base + 2 + i);
7311 /* Overwrite PERSP_SAMPLE. */
7312 for (i = 0; i < 2; i++)
7313 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7314 persp_center[i], base + i, "");
7315 /* Overwrite PERSP_CENTROID. */
7316 for (i = 0; i < 2; i++)
7317 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7318 persp_center[i], base + 4 + i, "");
7319 }
7320 if (key->ps_prolog.states.force_linear_center_interp) {
7321 unsigned i, base = key->ps_prolog.num_input_sgprs;
7322 LLVMValueRef linear_center[2];
7323
7324 /* Read LINEAR_CENTER. */
7325 for (i = 0; i < 2; i++)
7326 linear_center[i] = LLVMGetParam(func, base + 8 + i);
7327 /* Overwrite LINEAR_SAMPLE. */
7328 for (i = 0; i < 2; i++)
7329 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7330 linear_center[i], base + 6 + i, "");
7331 /* Overwrite LINEAR_CENTROID. */
7332 for (i = 0; i < 2; i++)
7333 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7334 linear_center[i], base + 10 + i, "");
7335 }
7336
7337 /* Interpolate colors. */
7338 unsigned color_out_idx = 0;
7339 for (i = 0; i < 2; i++) {
7340 unsigned writemask = (key->ps_prolog.colors_read >> (i * 4)) & 0xf;
7341 unsigned face_vgpr = key->ps_prolog.num_input_sgprs +
7342 key->ps_prolog.face_vgpr_index;
7343 LLVMValueRef interp[2], color[4];
7344 LLVMValueRef interp_ij = NULL, prim_mask = NULL, face = NULL;
7345
7346 if (!writemask)
7347 continue;
7348
7349 /* If the interpolation qualifier is not CONSTANT (-1). */
7350 if (key->ps_prolog.color_interp_vgpr_index[i] != -1) {
7351 unsigned interp_vgpr = key->ps_prolog.num_input_sgprs +
7352 key->ps_prolog.color_interp_vgpr_index[i];
7353
7354 /* Get the (i,j) updated by bc_optimize handling. */
7355 interp[0] = LLVMBuildExtractValue(ctx->ac.builder, ret,
7356 interp_vgpr, "");
7357 interp[1] = LLVMBuildExtractValue(ctx->ac.builder, ret,
7358 interp_vgpr + 1, "");
7359 interp_ij = lp_build_gather_values(&ctx->gallivm, interp, 2);
7360 }
7361
7362 /* Use the absolute location of the input. */
7363 prim_mask = LLVMGetParam(func, SI_PS_NUM_USER_SGPR);
7364
7365 if (key->ps_prolog.states.color_two_side) {
7366 face = LLVMGetParam(func, face_vgpr);
7367 face = ac_to_integer(&ctx->ac, face);
7368 }
7369
7370 interp_fs_input(ctx,
7371 key->ps_prolog.color_attr_index[i],
7372 TGSI_SEMANTIC_COLOR, i,
7373 key->ps_prolog.num_interp_inputs,
7374 key->ps_prolog.colors_read, interp_ij,
7375 prim_mask, face, color);
7376
7377 while (writemask) {
7378 unsigned chan = u_bit_scan(&writemask);
7379 ret = LLVMBuildInsertValue(ctx->ac.builder, ret, color[chan],
7380 fninfo.num_params + color_out_idx++, "");
7381 }
7382 }
7383
7384 /* Section 15.2.2 (Shader Inputs) of the OpenGL 4.5 (Core Profile) spec
7385 * says:
7386 *
7387 * "When per-sample shading is active due to the use of a fragment
7388 * input qualified by sample or due to the use of the gl_SampleID
7389 * or gl_SamplePosition variables, only the bit for the current
7390 * sample is set in gl_SampleMaskIn. When state specifies multiple
7391 * fragment shader invocations for a given fragment, the sample
7392 * mask for any single fragment shader invocation may specify a
7393 * subset of the covered samples for the fragment. In this case,
7394 * the bit corresponding to each covered sample will be set in
7395 * exactly one fragment shader invocation."
7396 *
7397 * The samplemask loaded by hardware is always the coverage of the
7398 * entire pixel/fragment, so mask bits out based on the sample ID.
7399 */
7400 if (key->ps_prolog.states.samplemask_log_ps_iter) {
7401 /* The bit pattern matches that used by fixed function fragment
7402 * processing. */
7403 static const uint16_t ps_iter_masks[] = {
7404 0xffff, /* not used */
7405 0x5555,
7406 0x1111,
7407 0x0101,
7408 0x0001,
7409 };
7410 assert(key->ps_prolog.states.samplemask_log_ps_iter < ARRAY_SIZE(ps_iter_masks));
7411
7412 uint32_t ps_iter_mask = ps_iter_masks[key->ps_prolog.states.samplemask_log_ps_iter];
7413 unsigned ancillary_vgpr = key->ps_prolog.num_input_sgprs +
7414 key->ps_prolog.ancillary_vgpr_index;
7415 LLVMValueRef sampleid = unpack_param(ctx, ancillary_vgpr, 8, 4);
7416 LLVMValueRef samplemask = LLVMGetParam(func, ancillary_vgpr + 1);
7417
7418 samplemask = ac_to_integer(&ctx->ac, samplemask);
7419 samplemask = LLVMBuildAnd(
7420 ctx->ac.builder,
7421 samplemask,
7422 LLVMBuildShl(ctx->ac.builder,
7423 LLVMConstInt(ctx->i32, ps_iter_mask, false),
7424 sampleid, ""),
7425 "");
7426 samplemask = ac_to_float(&ctx->ac, samplemask);
7427
7428 ret = LLVMBuildInsertValue(ctx->ac.builder, ret, samplemask,
7429 ancillary_vgpr + 1, "");
7430 }
7431
7432 /* Tell LLVM to insert WQM instruction sequence when needed. */
7433 if (key->ps_prolog.wqm) {
7434 LLVMAddTargetDependentFunctionAttr(func,
7435 "amdgpu-ps-wqm-outputs", "");
7436 }
7437
7438 si_llvm_build_ret(ctx, ret);
7439 }
7440
7441 /**
7442 * Build the pixel shader epilog function. This handles everything that must be
7443 * emulated for pixel shader exports. (alpha-test, format conversions, etc)
7444 */
7445 static void si_build_ps_epilog_function(struct si_shader_context *ctx,
7446 union si_shader_part_key *key)
7447 {
7448 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
7449 struct si_function_info fninfo;
7450 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
7451 int i;
7452 struct si_ps_exports exp = {};
7453
7454 si_init_function_info(&fninfo);
7455
7456 /* Declare input SGPRs. */
7457 ctx->param_rw_buffers = add_arg(&fninfo, ARG_SGPR, ctx->i64);
7458 ctx->param_bindless_samplers_and_images = add_arg(&fninfo, ARG_SGPR, ctx->i64);
7459 ctx->param_const_and_shader_buffers = add_arg(&fninfo, ARG_SGPR, ctx->i64);
7460 ctx->param_samplers_and_images = add_arg(&fninfo, ARG_SGPR, ctx->i64);
7461 add_arg_checked(&fninfo, ARG_SGPR, ctx->f32, SI_PARAM_ALPHA_REF);
7462
7463 /* Declare input VGPRs. */
7464 unsigned required_num_params =
7465 fninfo.num_sgpr_params +
7466 util_bitcount(key->ps_epilog.colors_written) * 4 +
7467 key->ps_epilog.writes_z +
7468 key->ps_epilog.writes_stencil +
7469 key->ps_epilog.writes_samplemask;
7470
7471 required_num_params = MAX2(required_num_params,
7472 fninfo.num_sgpr_params + PS_EPILOG_SAMPLEMASK_MIN_LOC + 1);
7473
7474 while (fninfo.num_params < required_num_params)
7475 add_arg(&fninfo, ARG_VGPR, ctx->f32);
7476
7477 /* Create the function. */
7478 si_create_function(ctx, "ps_epilog", NULL, 0, &fninfo, 0);
7479 /* Disable elimination of unused inputs. */
7480 si_llvm_add_attribute(ctx->main_fn,
7481 "InitialPSInputAddr", 0xffffff);
7482
7483 /* Process colors. */
7484 unsigned vgpr = fninfo.num_sgpr_params;
7485 unsigned colors_written = key->ps_epilog.colors_written;
7486 int last_color_export = -1;
7487
7488 /* Find the last color export. */
7489 if (!key->ps_epilog.writes_z &&
7490 !key->ps_epilog.writes_stencil &&
7491 !key->ps_epilog.writes_samplemask) {
7492 unsigned spi_format = key->ps_epilog.states.spi_shader_col_format;
7493
7494 /* If last_cbuf > 0, FS_COLOR0_WRITES_ALL_CBUFS is true. */
7495 if (colors_written == 0x1 && key->ps_epilog.states.last_cbuf > 0) {
7496 /* Just set this if any of the colorbuffers are enabled. */
7497 if (spi_format &
7498 ((1ull << (4 * (key->ps_epilog.states.last_cbuf + 1))) - 1))
7499 last_color_export = 0;
7500 } else {
7501 for (i = 0; i < 8; i++)
7502 if (colors_written & (1 << i) &&
7503 (spi_format >> (i * 4)) & 0xf)
7504 last_color_export = i;
7505 }
7506 }
7507
7508 while (colors_written) {
7509 LLVMValueRef color[4];
7510 int mrt = u_bit_scan(&colors_written);
7511
7512 for (i = 0; i < 4; i++)
7513 color[i] = LLVMGetParam(ctx->main_fn, vgpr++);
7514
7515 si_export_mrt_color(bld_base, color, mrt,
7516 fninfo.num_params - 1,
7517 mrt == last_color_export, &exp);
7518 }
7519
7520 /* Process depth, stencil, samplemask. */
7521 if (key->ps_epilog.writes_z)
7522 depth = LLVMGetParam(ctx->main_fn, vgpr++);
7523 if (key->ps_epilog.writes_stencil)
7524 stencil = LLVMGetParam(ctx->main_fn, vgpr++);
7525 if (key->ps_epilog.writes_samplemask)
7526 samplemask = LLVMGetParam(ctx->main_fn, vgpr++);
7527
7528 if (depth || stencil || samplemask)
7529 si_export_mrt_z(bld_base, depth, stencil, samplemask, &exp);
7530 else if (last_color_export == -1)
7531 si_export_null(bld_base);
7532
7533 if (exp.num)
7534 si_emit_ps_exports(ctx, &exp);
7535
7536 /* Compile. */
7537 LLVMBuildRetVoid(ctx->ac.builder);
7538 }
7539
7540 /**
7541 * Select and compile (or reuse) pixel shader parts (prolog & epilog).
7542 */
7543 static bool si_shader_select_ps_parts(struct si_screen *sscreen,
7544 LLVMTargetMachineRef tm,
7545 struct si_shader *shader,
7546 struct pipe_debug_callback *debug)
7547 {
7548 union si_shader_part_key prolog_key;
7549 union si_shader_part_key epilog_key;
7550
7551 /* Get the prolog. */
7552 si_get_ps_prolog_key(shader, &prolog_key, true);
7553
7554 /* The prolog is a no-op if these aren't set. */
7555 if (si_need_ps_prolog(&prolog_key)) {
7556 shader->prolog =
7557 si_get_shader_part(sscreen, &sscreen->ps_prologs,
7558 PIPE_SHADER_FRAGMENT, true,
7559 &prolog_key, tm, debug,
7560 si_build_ps_prolog_function,
7561 "Fragment Shader Prolog");
7562 if (!shader->prolog)
7563 return false;
7564 }
7565
7566 /* Get the epilog. */
7567 si_get_ps_epilog_key(shader, &epilog_key);
7568
7569 shader->epilog =
7570 si_get_shader_part(sscreen, &sscreen->ps_epilogs,
7571 PIPE_SHADER_FRAGMENT, false,
7572 &epilog_key, tm, debug,
7573 si_build_ps_epilog_function,
7574 "Fragment Shader Epilog");
7575 if (!shader->epilog)
7576 return false;
7577
7578 /* Enable POS_FIXED_PT if polygon stippling is enabled. */
7579 if (shader->key.part.ps.prolog.poly_stipple) {
7580 shader->config.spi_ps_input_ena |= S_0286CC_POS_FIXED_PT_ENA(1);
7581 assert(G_0286CC_POS_FIXED_PT_ENA(shader->config.spi_ps_input_addr));
7582 }
7583
7584 /* Set up the enable bits for per-sample shading if needed. */
7585 if (shader->key.part.ps.prolog.force_persp_sample_interp &&
7586 (G_0286CC_PERSP_CENTER_ENA(shader->config.spi_ps_input_ena) ||
7587 G_0286CC_PERSP_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
7588 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_CENTER_ENA;
7589 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_CENTROID_ENA;
7590 shader->config.spi_ps_input_ena |= S_0286CC_PERSP_SAMPLE_ENA(1);
7591 }
7592 if (shader->key.part.ps.prolog.force_linear_sample_interp &&
7593 (G_0286CC_LINEAR_CENTER_ENA(shader->config.spi_ps_input_ena) ||
7594 G_0286CC_LINEAR_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
7595 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_CENTER_ENA;
7596 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_CENTROID_ENA;
7597 shader->config.spi_ps_input_ena |= S_0286CC_LINEAR_SAMPLE_ENA(1);
7598 }
7599 if (shader->key.part.ps.prolog.force_persp_center_interp &&
7600 (G_0286CC_PERSP_SAMPLE_ENA(shader->config.spi_ps_input_ena) ||
7601 G_0286CC_PERSP_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
7602 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_SAMPLE_ENA;
7603 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_CENTROID_ENA;
7604 shader->config.spi_ps_input_ena |= S_0286CC_PERSP_CENTER_ENA(1);
7605 }
7606 if (shader->key.part.ps.prolog.force_linear_center_interp &&
7607 (G_0286CC_LINEAR_SAMPLE_ENA(shader->config.spi_ps_input_ena) ||
7608 G_0286CC_LINEAR_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
7609 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_SAMPLE_ENA;
7610 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_CENTROID_ENA;
7611 shader->config.spi_ps_input_ena |= S_0286CC_LINEAR_CENTER_ENA(1);
7612 }
7613
7614 /* POW_W_FLOAT requires that one of the perspective weights is enabled. */
7615 if (G_0286CC_POS_W_FLOAT_ENA(shader->config.spi_ps_input_ena) &&
7616 !(shader->config.spi_ps_input_ena & 0xf)) {
7617 shader->config.spi_ps_input_ena |= S_0286CC_PERSP_CENTER_ENA(1);
7618 assert(G_0286CC_PERSP_CENTER_ENA(shader->config.spi_ps_input_addr));
7619 }
7620
7621 /* At least one pair of interpolation weights must be enabled. */
7622 if (!(shader->config.spi_ps_input_ena & 0x7f)) {
7623 shader->config.spi_ps_input_ena |= S_0286CC_LINEAR_CENTER_ENA(1);
7624 assert(G_0286CC_LINEAR_CENTER_ENA(shader->config.spi_ps_input_addr));
7625 }
7626
7627 /* Samplemask fixup requires the sample ID. */
7628 if (shader->key.part.ps.prolog.samplemask_log_ps_iter) {
7629 shader->config.spi_ps_input_ena |= S_0286CC_ANCILLARY_ENA(1);
7630 assert(G_0286CC_ANCILLARY_ENA(shader->config.spi_ps_input_addr));
7631 }
7632
7633 /* The sample mask input is always enabled, because the API shader always
7634 * passes it through to the epilog. Disable it here if it's unused.
7635 */
7636 if (!shader->key.part.ps.epilog.poly_line_smoothing &&
7637 !shader->selector->info.reads_samplemask)
7638 shader->config.spi_ps_input_ena &= C_0286CC_SAMPLE_COVERAGE_ENA;
7639
7640 return true;
7641 }
7642
7643 void si_multiwave_lds_size_workaround(struct si_screen *sscreen,
7644 unsigned *lds_size)
7645 {
7646 /* SPI barrier management bug:
7647 * Make sure we have at least 4k of LDS in use to avoid the bug.
7648 * It applies to workgroup sizes of more than one wavefront.
7649 */
7650 if (sscreen->b.family == CHIP_BONAIRE ||
7651 sscreen->b.family == CHIP_KABINI ||
7652 sscreen->b.family == CHIP_MULLINS)
7653 *lds_size = MAX2(*lds_size, 8);
7654 }
7655
7656 static void si_fix_resource_usage(struct si_screen *sscreen,
7657 struct si_shader *shader)
7658 {
7659 unsigned min_sgprs = shader->info.num_input_sgprs + 2; /* VCC */
7660
7661 shader->config.num_sgprs = MAX2(shader->config.num_sgprs, min_sgprs);
7662
7663 if (shader->selector->type == PIPE_SHADER_COMPUTE &&
7664 si_get_max_workgroup_size(shader) > 64) {
7665 si_multiwave_lds_size_workaround(sscreen,
7666 &shader->config.lds_size);
7667 }
7668 }
7669
7670 int si_shader_create(struct si_screen *sscreen, LLVMTargetMachineRef tm,
7671 struct si_shader *shader,
7672 struct pipe_debug_callback *debug)
7673 {
7674 struct si_shader_selector *sel = shader->selector;
7675 struct si_shader *mainp = *si_get_main_shader_part(sel, &shader->key);
7676 int r;
7677
7678 /* LS, ES, VS are compiled on demand if the main part hasn't been
7679 * compiled for that stage.
7680 *
7681 * Vertex shaders are compiled on demand when a vertex fetch
7682 * workaround must be applied.
7683 */
7684 if (shader->is_monolithic) {
7685 /* Monolithic shader (compiled as a whole, has many variants,
7686 * may take a long time to compile).
7687 */
7688 r = si_compile_tgsi_shader(sscreen, tm, shader, true, debug);
7689 if (r)
7690 return r;
7691 } else {
7692 /* The shader consists of several parts:
7693 *
7694 * - the middle part is the user shader, it has 1 variant only
7695 * and it was compiled during the creation of the shader
7696 * selector
7697 * - the prolog part is inserted at the beginning
7698 * - the epilog part is inserted at the end
7699 *
7700 * The prolog and epilog have many (but simple) variants.
7701 *
7702 * Starting with gfx9, geometry and tessellation control
7703 * shaders also contain the prolog and user shader parts of
7704 * the previous shader stage.
7705 */
7706
7707 if (!mainp)
7708 return -1;
7709
7710 /* Copy the compiled TGSI shader data over. */
7711 shader->is_binary_shared = true;
7712 shader->binary = mainp->binary;
7713 shader->config = mainp->config;
7714 shader->info.num_input_sgprs = mainp->info.num_input_sgprs;
7715 shader->info.num_input_vgprs = mainp->info.num_input_vgprs;
7716 shader->info.face_vgpr_index = mainp->info.face_vgpr_index;
7717 shader->info.ancillary_vgpr_index = mainp->info.ancillary_vgpr_index;
7718 memcpy(shader->info.vs_output_param_offset,
7719 mainp->info.vs_output_param_offset,
7720 sizeof(mainp->info.vs_output_param_offset));
7721 shader->info.uses_instanceid = mainp->info.uses_instanceid;
7722 shader->info.nr_pos_exports = mainp->info.nr_pos_exports;
7723 shader->info.nr_param_exports = mainp->info.nr_param_exports;
7724
7725 /* Select prologs and/or epilogs. */
7726 switch (sel->type) {
7727 case PIPE_SHADER_VERTEX:
7728 if (!si_shader_select_vs_parts(sscreen, tm, shader, debug))
7729 return -1;
7730 break;
7731 case PIPE_SHADER_TESS_CTRL:
7732 if (!si_shader_select_tcs_parts(sscreen, tm, shader, debug))
7733 return -1;
7734 break;
7735 case PIPE_SHADER_TESS_EVAL:
7736 break;
7737 case PIPE_SHADER_GEOMETRY:
7738 if (!si_shader_select_gs_parts(sscreen, tm, shader, debug))
7739 return -1;
7740 break;
7741 case PIPE_SHADER_FRAGMENT:
7742 if (!si_shader_select_ps_parts(sscreen, tm, shader, debug))
7743 return -1;
7744
7745 /* Make sure we have at least as many VGPRs as there
7746 * are allocated inputs.
7747 */
7748 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
7749 shader->info.num_input_vgprs);
7750 break;
7751 }
7752
7753 /* Update SGPR and VGPR counts. */
7754 if (shader->prolog) {
7755 shader->config.num_sgprs = MAX2(shader->config.num_sgprs,
7756 shader->prolog->config.num_sgprs);
7757 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
7758 shader->prolog->config.num_vgprs);
7759 }
7760 if (shader->previous_stage) {
7761 shader->config.num_sgprs = MAX2(shader->config.num_sgprs,
7762 shader->previous_stage->config.num_sgprs);
7763 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
7764 shader->previous_stage->config.num_vgprs);
7765 shader->config.spilled_sgprs =
7766 MAX2(shader->config.spilled_sgprs,
7767 shader->previous_stage->config.spilled_sgprs);
7768 shader->config.spilled_vgprs =
7769 MAX2(shader->config.spilled_vgprs,
7770 shader->previous_stage->config.spilled_vgprs);
7771 shader->config.private_mem_vgprs =
7772 MAX2(shader->config.private_mem_vgprs,
7773 shader->previous_stage->config.private_mem_vgprs);
7774 shader->config.scratch_bytes_per_wave =
7775 MAX2(shader->config.scratch_bytes_per_wave,
7776 shader->previous_stage->config.scratch_bytes_per_wave);
7777 shader->info.uses_instanceid |=
7778 shader->previous_stage->info.uses_instanceid;
7779 }
7780 if (shader->prolog2) {
7781 shader->config.num_sgprs = MAX2(shader->config.num_sgprs,
7782 shader->prolog2->config.num_sgprs);
7783 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
7784 shader->prolog2->config.num_vgprs);
7785 }
7786 if (shader->epilog) {
7787 shader->config.num_sgprs = MAX2(shader->config.num_sgprs,
7788 shader->epilog->config.num_sgprs);
7789 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
7790 shader->epilog->config.num_vgprs);
7791 }
7792 }
7793
7794 si_fix_resource_usage(sscreen, shader);
7795 si_shader_dump(sscreen, shader, debug, sel->info.processor,
7796 stderr, true);
7797
7798 /* Upload. */
7799 r = si_shader_binary_upload(sscreen, shader);
7800 if (r) {
7801 fprintf(stderr, "LLVM failed to upload shader\n");
7802 return r;
7803 }
7804
7805 return 0;
7806 }
7807
7808 void si_shader_destroy(struct si_shader *shader)
7809 {
7810 if (shader->scratch_bo)
7811 r600_resource_reference(&shader->scratch_bo, NULL);
7812
7813 r600_resource_reference(&shader->bo, NULL);
7814
7815 if (!shader->is_binary_shared)
7816 si_radeon_shader_binary_clean(&shader->binary);
7817
7818 free(shader->shader_log);
7819 }