projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
radeonsi: avoid sending GS_EMIT in shaders without outputs
[mesa.git] / src / gallium / drivers / radeonsi / si_shader.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 #include "util/u_memory.h"
26 #include "util/u_string.h"
27 #include "tgsi/tgsi_build.h"
28 #include "tgsi/tgsi_util.h"
29 #include "tgsi/tgsi_dump.h"
30
31 #include "ac_exp_param.h"
32 #include "ac_shader_util.h"
33 #include "ac_llvm_util.h"
34 #include "si_shader_internal.h"
35 #include "si_pipe.h"
36 #include "sid.h"
37
38 #include "compiler/nir/nir.h"
39
40 static const char *scratch_rsrc_dword0_symbol =
41 "SCRATCH_RSRC_DWORD0";
42
43 static const char *scratch_rsrc_dword1_symbol =
44 "SCRATCH_RSRC_DWORD1";
45
46 struct si_shader_output_values
47 {
48 LLVMValueRef values[4];
49 unsigned semantic_name;
50 unsigned semantic_index;
51 ubyte vertex_stream[4];
52 };
53
54 /**
55 * Used to collect types and other info about arguments of the LLVM function
56 * before the function is created.
57 */
58 struct si_function_info {
59 LLVMTypeRef types[100];
60 LLVMValueRef *assign[100];
61 unsigned num_sgpr_params;
62 unsigned num_params;
63 };
64
65 enum si_arg_regfile {
66 ARG_SGPR,
67 ARG_VGPR
68 };
69
70 static void si_init_shader_ctx(struct si_shader_context *ctx,
71 struct si_screen *sscreen,
72 struct ac_llvm_compiler *compiler);
73
74 static void si_llvm_emit_barrier(const struct lp_build_tgsi_action *action,
75 struct lp_build_tgsi_context *bld_base,
76 struct lp_build_emit_data *emit_data);
77
78 static void si_dump_shader_key(unsigned processor, const struct si_shader *shader,
79 FILE *f);
80
81 static void si_build_vs_prolog_function(struct si_shader_context *ctx,
82 union si_shader_part_key *key);
83 static void si_build_tcs_epilog_function(struct si_shader_context *ctx,
84 union si_shader_part_key *key);
85 static void si_build_ps_prolog_function(struct si_shader_context *ctx,
86 union si_shader_part_key *key);
87 static void si_build_ps_epilog_function(struct si_shader_context *ctx,
88 union si_shader_part_key *key);
89
90 /* Ideally pass the sample mask input to the PS epilog as v14, which
91 * is its usual location, so that the shader doesn't have to add v_mov.
92 */
93 #define PS_EPILOG_SAMPLEMASK_MIN_LOC 14
94
95 static bool llvm_type_is_64bit(struct si_shader_context *ctx,
96 LLVMTypeRef type)
97 {
98 if (type == ctx->ac.i64 || type == ctx->ac.f64)
99 return true;
100
101 return false;
102 }
103
104 static bool is_merged_shader(struct si_shader_context *ctx)
105 {
106 if (ctx->screen->info.chip_class <= VI)
107 return false;
108
109 return ctx->shader->key.as_ls ||
110 ctx->shader->key.as_es ||
111 ctx->type == PIPE_SHADER_TESS_CTRL ||
112 ctx->type == PIPE_SHADER_GEOMETRY;
113 }
114
115 static void si_init_function_info(struct si_function_info *fninfo)
116 {
117 fninfo->num_params = 0;
118 fninfo->num_sgpr_params = 0;
119 }
120
121 static unsigned add_arg_assign(struct si_function_info *fninfo,
122 enum si_arg_regfile regfile, LLVMTypeRef type,
123 LLVMValueRef *assign)
124 {
125 assert(regfile != ARG_SGPR || fninfo->num_sgpr_params == fninfo->num_params);
126
127 unsigned idx = fninfo->num_params++;
128 assert(idx < ARRAY_SIZE(fninfo->types));
129
130 if (regfile == ARG_SGPR)
131 fninfo->num_sgpr_params = fninfo->num_params;
132
133 fninfo->types[idx] = type;
134 fninfo->assign[idx] = assign;
135 return idx;
136 }
137
138 static unsigned add_arg(struct si_function_info *fninfo,
139 enum si_arg_regfile regfile, LLVMTypeRef type)
140 {
141 return add_arg_assign(fninfo, regfile, type, NULL);
142 }
143
144 static void add_arg_assign_checked(struct si_function_info *fninfo,
145 enum si_arg_regfile regfile, LLVMTypeRef type,
146 LLVMValueRef *assign, unsigned idx)
147 {
148 MAYBE_UNUSED unsigned actual = add_arg_assign(fninfo, regfile, type, assign);
149 assert(actual == idx);
150 }
151
152 static void add_arg_checked(struct si_function_info *fninfo,
153 enum si_arg_regfile regfile, LLVMTypeRef type,
154 unsigned idx)
155 {
156 add_arg_assign_checked(fninfo, regfile, type, NULL, idx);
157 }
158
159 /**
160 * Returns a unique index for a per-patch semantic name and index. The index
161 * must be less than 32, so that a 32-bit bitmask of used inputs or outputs
162 * can be calculated.
163 */
164 unsigned si_shader_io_get_unique_index_patch(unsigned semantic_name, unsigned index)
165 {
166 switch (semantic_name) {
167 case TGSI_SEMANTIC_TESSOUTER:
168 return 0;
169 case TGSI_SEMANTIC_TESSINNER:
170 return 1;
171 case TGSI_SEMANTIC_PATCH:
172 assert(index < 30);
173 return 2 + index;
174
175 default:
176 assert(!"invalid semantic name");
177 return 0;
178 }
179 }
180
181 /**
182 * Returns a unique index for a semantic name and index. The index must be
183 * less than 64, so that a 64-bit bitmask of used inputs or outputs can be
184 * calculated.
185 */
186 unsigned si_shader_io_get_unique_index(unsigned semantic_name, unsigned index,
187 unsigned is_varying)
188 {
189 switch (semantic_name) {
190 case TGSI_SEMANTIC_POSITION:
191 return 0;
192 case TGSI_SEMANTIC_GENERIC:
193 /* Since some shader stages use the the highest used IO index
194 * to determine the size to allocate for inputs/outputs
195 * (in LDS, tess and GS rings). GENERIC should be placed right
196 * after POSITION to make that size as small as possible.
197 */
198 if (index < SI_MAX_IO_GENERIC)
199 return 1 + index;
200
201 assert(!"invalid generic index");
202 return 0;
203 case TGSI_SEMANTIC_PSIZE:
204 return SI_MAX_IO_GENERIC + 1;
205 case TGSI_SEMANTIC_CLIPDIST:
206 assert(index <= 1);
207 return SI_MAX_IO_GENERIC + 2 + index;
208 case TGSI_SEMANTIC_FOG:
209 return SI_MAX_IO_GENERIC + 4;
210 case TGSI_SEMANTIC_LAYER:
211 return SI_MAX_IO_GENERIC + 5;
212 case TGSI_SEMANTIC_VIEWPORT_INDEX:
213 return SI_MAX_IO_GENERIC + 6;
214 case TGSI_SEMANTIC_PRIMID:
215 return SI_MAX_IO_GENERIC + 7;
216 case TGSI_SEMANTIC_COLOR:
217 assert(index < 2);
218 return SI_MAX_IO_GENERIC + 8 + index;
219 case TGSI_SEMANTIC_BCOLOR:
220 assert(index < 2);
221 /* If it's a varying, COLOR and BCOLOR alias. */
222 if (is_varying)
223 return SI_MAX_IO_GENERIC + 8 + index;
224 else
225 return SI_MAX_IO_GENERIC + 10 + index;
226 case TGSI_SEMANTIC_TEXCOORD:
227 assert(index < 8);
228 STATIC_ASSERT(SI_MAX_IO_GENERIC + 12 + 8 <= 63);
229 return SI_MAX_IO_GENERIC + 12 + index;
230 case TGSI_SEMANTIC_CLIPVERTEX:
231 return 63;
232 default:
233 fprintf(stderr, "invalid semantic name = %u\n", semantic_name);
234 assert(!"invalid semantic name");
235 return 0;
236 }
237 }
238
239 /**
240 * Get the value of a shader input parameter and extract a bitfield.
241 */
242 static LLVMValueRef unpack_llvm_param(struct si_shader_context *ctx,
243 LLVMValueRef value, unsigned rshift,
244 unsigned bitwidth)
245 {
246 if (LLVMGetTypeKind(LLVMTypeOf(value)) == LLVMFloatTypeKind)
247 value = ac_to_integer(&ctx->ac, value);
248
249 if (rshift)
250 value = LLVMBuildLShr(ctx->ac.builder, value,
251 LLVMConstInt(ctx->i32, rshift, 0), "");
252
253 if (rshift + bitwidth < 32) {
254 unsigned mask = (1 << bitwidth) - 1;
255 value = LLVMBuildAnd(ctx->ac.builder, value,
256 LLVMConstInt(ctx->i32, mask, 0), "");
257 }
258
259 return value;
260 }
261
262 LLVMValueRef si_unpack_param(struct si_shader_context *ctx,
263 unsigned param, unsigned rshift,
264 unsigned bitwidth)
265 {
266 LLVMValueRef value = LLVMGetParam(ctx->main_fn, param);
267
268 return unpack_llvm_param(ctx, value, rshift, bitwidth);
269 }
270
271 static LLVMValueRef get_rel_patch_id(struct si_shader_context *ctx)
272 {
273 switch (ctx->type) {
274 case PIPE_SHADER_TESS_CTRL:
275 return unpack_llvm_param(ctx, ctx->abi.tcs_rel_ids, 0, 8);
276
277 case PIPE_SHADER_TESS_EVAL:
278 return LLVMGetParam(ctx->main_fn,
279 ctx->param_tes_rel_patch_id);
280
281 default:
282 assert(0);
283 return NULL;
284 }
285 }
286
287 /* Tessellation shaders pass outputs to the next shader using LDS.
288 *
289 * LS outputs = TCS inputs
290 * TCS outputs = TES inputs
291 *
292 * The LDS layout is:
293 * - TCS inputs for patch 0
294 * - TCS inputs for patch 1
295 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
296 * - ...
297 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
298 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
299 * - TCS outputs for patch 1
300 * - Per-patch TCS outputs for patch 1
301 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
302 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
303 * - ...
304 *
305 * All three shaders VS(LS), TCS, TES share the same LDS space.
306 */
307
308 static LLVMValueRef
309 get_tcs_in_patch_stride(struct si_shader_context *ctx)
310 {
311 return si_unpack_param(ctx, ctx->param_vs_state_bits, 8, 13);
312 }
313
314 static unsigned get_tcs_out_vertex_dw_stride_constant(struct si_shader_context *ctx)
315 {
316 assert(ctx->type == PIPE_SHADER_TESS_CTRL);
317
318 if (ctx->shader->key.mono.u.ff_tcs_inputs_to_copy)
319 return util_last_bit64(ctx->shader->key.mono.u.ff_tcs_inputs_to_copy) * 4;
320
321 return util_last_bit64(ctx->shader->selector->outputs_written) * 4;
322 }
323
324 static LLVMValueRef get_tcs_out_vertex_dw_stride(struct si_shader_context *ctx)
325 {
326 unsigned stride = get_tcs_out_vertex_dw_stride_constant(ctx);
327
328 return LLVMConstInt(ctx->i32, stride, 0);
329 }
330
331 static LLVMValueRef get_tcs_out_patch_stride(struct si_shader_context *ctx)
332 {
333 if (ctx->shader->key.mono.u.ff_tcs_inputs_to_copy)
334 return si_unpack_param(ctx, ctx->param_tcs_out_lds_layout, 0, 13);
335
336 const struct tgsi_shader_info *info = &ctx->shader->selector->info;
337 unsigned tcs_out_vertices = info->properties[TGSI_PROPERTY_TCS_VERTICES_OUT];
338 unsigned vertex_dw_stride = get_tcs_out_vertex_dw_stride_constant(ctx);
339 unsigned num_patch_outputs = util_last_bit64(ctx->shader->selector->patch_outputs_written);
340 unsigned patch_dw_stride = tcs_out_vertices * vertex_dw_stride +
341 num_patch_outputs * 4;
342 return LLVMConstInt(ctx->i32, patch_dw_stride, 0);
343 }
344
345 static LLVMValueRef
346 get_tcs_out_patch0_offset(struct si_shader_context *ctx)
347 {
348 return LLVMBuildMul(ctx->ac.builder,
349 si_unpack_param(ctx,
350 ctx->param_tcs_out_lds_offsets,
351 0, 16),
352 LLVMConstInt(ctx->i32, 4, 0), "");
353 }
354
355 static LLVMValueRef
356 get_tcs_out_patch0_patch_data_offset(struct si_shader_context *ctx)
357 {
358 return LLVMBuildMul(ctx->ac.builder,
359 si_unpack_param(ctx,
360 ctx->param_tcs_out_lds_offsets,
361 16, 16),
362 LLVMConstInt(ctx->i32, 4, 0), "");
363 }
364
365 static LLVMValueRef
366 get_tcs_in_current_patch_offset(struct si_shader_context *ctx)
367 {
368 LLVMValueRef patch_stride = get_tcs_in_patch_stride(ctx);
369 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
370
371 return LLVMBuildMul(ctx->ac.builder, patch_stride, rel_patch_id, "");
372 }
373
374 static LLVMValueRef
375 get_tcs_out_current_patch_offset(struct si_shader_context *ctx)
376 {
377 LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(ctx);
378 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
379 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
380
381 return ac_build_imad(&ctx->ac, patch_stride, rel_patch_id, patch0_offset);
382 }
383
384 static LLVMValueRef
385 get_tcs_out_current_patch_data_offset(struct si_shader_context *ctx)
386 {
387 LLVMValueRef patch0_patch_data_offset =
388 get_tcs_out_patch0_patch_data_offset(ctx);
389 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
390 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
391
392 return ac_build_imad(&ctx->ac, patch_stride, rel_patch_id, patch0_patch_data_offset);
393 }
394
395 static LLVMValueRef get_num_tcs_out_vertices(struct si_shader_context *ctx)
396 {
397 unsigned tcs_out_vertices =
398 ctx->shader->selector ?
399 ctx->shader->selector->info.properties[TGSI_PROPERTY_TCS_VERTICES_OUT] : 0;
400
401 /* If !tcs_out_vertices, it's either the fixed-func TCS or the TCS epilog. */
402 if (ctx->type == PIPE_SHADER_TESS_CTRL && tcs_out_vertices)
403 return LLVMConstInt(ctx->i32, tcs_out_vertices, 0);
404
405 return si_unpack_param(ctx, ctx->param_tcs_offchip_layout, 6, 6);
406 }
407
408 static LLVMValueRef get_tcs_in_vertex_dw_stride(struct si_shader_context *ctx)
409 {
410 unsigned stride;
411
412 switch (ctx->type) {
413 case PIPE_SHADER_VERTEX:
414 stride = ctx->shader->selector->lshs_vertex_stride / 4;
415 return LLVMConstInt(ctx->i32, stride, 0);
416
417 case PIPE_SHADER_TESS_CTRL:
418 if (ctx->screen->info.chip_class >= GFX9 &&
419 ctx->shader->is_monolithic) {
420 stride = ctx->shader->key.part.tcs.ls->lshs_vertex_stride / 4;
421 return LLVMConstInt(ctx->i32, stride, 0);
422 }
423 return si_unpack_param(ctx, ctx->param_vs_state_bits, 24, 8);
424
425 default:
426 assert(0);
427 return NULL;
428 }
429 }
430
431 static LLVMValueRef get_instance_index_for_fetch(
432 struct si_shader_context *ctx,
433 unsigned param_start_instance, LLVMValueRef divisor)
434 {
435 LLVMValueRef result = ctx->abi.instance_id;
436
437 /* The division must be done before START_INSTANCE is added. */
438 if (divisor != ctx->i32_1)
439 result = LLVMBuildUDiv(ctx->ac.builder, result, divisor, "");
440
441 return LLVMBuildAdd(ctx->ac.builder, result,
442 LLVMGetParam(ctx->main_fn, param_start_instance), "");
443 }
444
445 /* Bitcast <4 x float> to <2 x double>, extract the component, and convert
446 * to float. */
447 static LLVMValueRef extract_double_to_float(struct si_shader_context *ctx,
448 LLVMValueRef vec4,
449 unsigned double_index)
450 {
451 LLVMBuilderRef builder = ctx->ac.builder;
452 LLVMTypeRef f64 = LLVMDoubleTypeInContext(ctx->ac.context);
453 LLVMValueRef dvec2 = LLVMBuildBitCast(builder, vec4,
454 LLVMVectorType(f64, 2), "");
455 LLVMValueRef index = LLVMConstInt(ctx->i32, double_index, 0);
456 LLVMValueRef value = LLVMBuildExtractElement(builder, dvec2, index, "");
457 return LLVMBuildFPTrunc(builder, value, ctx->f32, "");
458 }
459
460 static LLVMValueRef unpack_sint16(struct si_shader_context *ctx,
461 LLVMValueRef i32, unsigned index)
462 {
463 assert(index <= 1);
464
465 if (index == 1)
466 return LLVMBuildAShr(ctx->ac.builder, i32,
467 LLVMConstInt(ctx->i32, 16, 0), "");
468
469 return LLVMBuildSExt(ctx->ac.builder,
470 LLVMBuildTrunc(ctx->ac.builder, i32,
471 ctx->ac.i16, ""),
472 ctx->i32, "");
473 }
474
475 void si_llvm_load_input_vs(
476 struct si_shader_context *ctx,
477 unsigned input_index,
478 LLVMValueRef out[4])
479 {
480 const struct tgsi_shader_info *info = &ctx->shader->selector->info;
481 unsigned vs_blit_property = info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS];
482
483 if (vs_blit_property) {
484 LLVMValueRef vertex_id = ctx->abi.vertex_id;
485 LLVMValueRef sel_x1 = LLVMBuildICmp(ctx->ac.builder,
486 LLVMIntULE, vertex_id,
487 ctx->i32_1, "");
488 /* Use LLVMIntNE, because we have 3 vertices and only
489 * the middle one should use y2.
490 */
491 LLVMValueRef sel_y1 = LLVMBuildICmp(ctx->ac.builder,
492 LLVMIntNE, vertex_id,
493 ctx->i32_1, "");
494
495 if (input_index == 0) {
496 /* Position: */
497 LLVMValueRef x1y1 = LLVMGetParam(ctx->main_fn,
498 ctx->param_vs_blit_inputs);
499 LLVMValueRef x2y2 = LLVMGetParam(ctx->main_fn,
500 ctx->param_vs_blit_inputs + 1);
501
502 LLVMValueRef x1 = unpack_sint16(ctx, x1y1, 0);
503 LLVMValueRef y1 = unpack_sint16(ctx, x1y1, 1);
504 LLVMValueRef x2 = unpack_sint16(ctx, x2y2, 0);
505 LLVMValueRef y2 = unpack_sint16(ctx, x2y2, 1);
506
507 LLVMValueRef x = LLVMBuildSelect(ctx->ac.builder, sel_x1,
508 x1, x2, "");
509 LLVMValueRef y = LLVMBuildSelect(ctx->ac.builder, sel_y1,
510 y1, y2, "");
511
512 out[0] = LLVMBuildSIToFP(ctx->ac.builder, x, ctx->f32, "");
513 out[1] = LLVMBuildSIToFP(ctx->ac.builder, y, ctx->f32, "");
514 out[2] = LLVMGetParam(ctx->main_fn,
515 ctx->param_vs_blit_inputs + 2);
516 out[3] = ctx->ac.f32_1;
517 return;
518 }
519
520 /* Color or texture coordinates: */
521 assert(input_index == 1);
522
523 if (vs_blit_property == SI_VS_BLIT_SGPRS_POS_COLOR) {
524 for (int i = 0; i < 4; i++) {
525 out[i] = LLVMGetParam(ctx->main_fn,
526 ctx->param_vs_blit_inputs + 3 + i);
527 }
528 } else {
529 assert(vs_blit_property == SI_VS_BLIT_SGPRS_POS_TEXCOORD);
530 LLVMValueRef x1 = LLVMGetParam(ctx->main_fn,
531 ctx->param_vs_blit_inputs + 3);
532 LLVMValueRef y1 = LLVMGetParam(ctx->main_fn,
533 ctx->param_vs_blit_inputs + 4);
534 LLVMValueRef x2 = LLVMGetParam(ctx->main_fn,
535 ctx->param_vs_blit_inputs + 5);
536 LLVMValueRef y2 = LLVMGetParam(ctx->main_fn,
537 ctx->param_vs_blit_inputs + 6);
538
539 out[0] = LLVMBuildSelect(ctx->ac.builder, sel_x1,
540 x1, x2, "");
541 out[1] = LLVMBuildSelect(ctx->ac.builder, sel_y1,
542 y1, y2, "");
543 out[2] = LLVMGetParam(ctx->main_fn,
544 ctx->param_vs_blit_inputs + 7);
545 out[3] = LLVMGetParam(ctx->main_fn,
546 ctx->param_vs_blit_inputs + 8);
547 }
548 return;
549 }
550
551 unsigned chan;
552 unsigned fix_fetch;
553 unsigned num_fetches;
554 unsigned fetch_stride;
555 unsigned num_channels;
556
557 LLVMValueRef t_list_ptr;
558 LLVMValueRef t_offset;
559 LLVMValueRef t_list;
560 LLVMValueRef vertex_index;
561 LLVMValueRef input[3];
562
563 /* Load the T list */
564 t_list_ptr = LLVMGetParam(ctx->main_fn, ctx->param_vertex_buffers);
565
566 t_offset = LLVMConstInt(ctx->i32, input_index, 0);
567
568 t_list = ac_build_load_to_sgpr(&ctx->ac, t_list_ptr, t_offset);
569
570 vertex_index = LLVMGetParam(ctx->main_fn,
571 ctx->param_vertex_index0 +
572 input_index);
573
574 fix_fetch = ctx->shader->key.mono.vs_fix_fetch[input_index];
575
576 /* Do multiple loads for special formats. */
577 switch (fix_fetch) {
578 case SI_FIX_FETCH_RGB_64_FLOAT:
579 num_fetches = 3; /* 3 2-dword loads */
580 fetch_stride = 8;
581 num_channels = 2;
582 break;
583 case SI_FIX_FETCH_RGBA_64_FLOAT:
584 num_fetches = 2; /* 2 4-dword loads */
585 fetch_stride = 16;
586 num_channels = 4;
587 break;
588 case SI_FIX_FETCH_RGB_8:
589 case SI_FIX_FETCH_RGB_8_INT:
590 num_fetches = 3;
591 fetch_stride = 1;
592 num_channels = 1;
593 break;
594 case SI_FIX_FETCH_RGB_16:
595 case SI_FIX_FETCH_RGB_16_INT:
596 num_fetches = 3;
597 fetch_stride = 2;
598 num_channels = 1;
599 break;
600 default:
601 num_fetches = 1;
602 fetch_stride = 0;
603 num_channels = util_last_bit(info->input_usage_mask[input_index]);
604 }
605
606 for (unsigned i = 0; i < num_fetches; i++) {
607 LLVMValueRef voffset = LLVMConstInt(ctx->i32, fetch_stride * i, 0);
608
609 input[i] = ac_build_buffer_load_format(&ctx->ac, t_list,
610 vertex_index, voffset,
611 num_channels, false, true);
612 input[i] = ac_build_expand_to_vec4(&ctx->ac, input[i], num_channels);
613 }
614
615 /* Break up the vec4 into individual components */
616 for (chan = 0; chan < 4; chan++) {
617 LLVMValueRef llvm_chan = LLVMConstInt(ctx->i32, chan, 0);
618 out[chan] = LLVMBuildExtractElement(ctx->ac.builder,
619 input[0], llvm_chan, "");
620 }
621
622 switch (fix_fetch) {
623 case SI_FIX_FETCH_A2_SNORM:
624 case SI_FIX_FETCH_A2_SSCALED:
625 case SI_FIX_FETCH_A2_SINT: {
626 /* The hardware returns an unsigned value; convert it to a
627 * signed one.
628 */
629 LLVMValueRef tmp = out[3];
630 LLVMValueRef c30 = LLVMConstInt(ctx->i32, 30, 0);
631
632 /* First, recover the sign-extended signed integer value. */
633 if (fix_fetch == SI_FIX_FETCH_A2_SSCALED)
634 tmp = LLVMBuildFPToUI(ctx->ac.builder, tmp, ctx->i32, "");
635 else
636 tmp = ac_to_integer(&ctx->ac, tmp);
637
638 /* For the integer-like cases, do a natural sign extension.
639 *
640 * For the SNORM case, the values are 0.0, 0.333, 0.666, 1.0
641 * and happen to contain 0, 1, 2, 3 as the two LSBs of the
642 * exponent.
643 */
644 tmp = LLVMBuildShl(ctx->ac.builder, tmp,
645 fix_fetch == SI_FIX_FETCH_A2_SNORM ?
646 LLVMConstInt(ctx->i32, 7, 0) : c30, "");
647 tmp = LLVMBuildAShr(ctx->ac.builder, tmp, c30, "");
648
649 /* Convert back to the right type. */
650 if (fix_fetch == SI_FIX_FETCH_A2_SNORM) {
651 LLVMValueRef clamp;
652 LLVMValueRef neg_one = LLVMConstReal(ctx->f32, -1.0);
653 tmp = LLVMBuildSIToFP(ctx->ac.builder, tmp, ctx->f32, "");
654 clamp = LLVMBuildFCmp(ctx->ac.builder, LLVMRealULT, tmp, neg_one, "");
655 tmp = LLVMBuildSelect(ctx->ac.builder, clamp, neg_one, tmp, "");
656 } else if (fix_fetch == SI_FIX_FETCH_A2_SSCALED) {
657 tmp = LLVMBuildSIToFP(ctx->ac.builder, tmp, ctx->f32, "");
658 }
659
660 out[3] = tmp;
661 break;
662 }
663 case SI_FIX_FETCH_RGBA_32_UNORM:
664 case SI_FIX_FETCH_RGBX_32_UNORM:
665 for (chan = 0; chan < 4; chan++) {
666 out[chan] = ac_to_integer(&ctx->ac, out[chan]);
667 out[chan] = LLVMBuildUIToFP(ctx->ac.builder,
668 out[chan], ctx->f32, "");
669 out[chan] = LLVMBuildFMul(ctx->ac.builder, out[chan],
670 LLVMConstReal(ctx->f32, 1.0 / UINT_MAX), "");
671 }
672 /* RGBX UINT returns 1 in alpha, which would be rounded to 0 by normalizing. */
673 if (fix_fetch == SI_FIX_FETCH_RGBX_32_UNORM)
674 out[3] = LLVMConstReal(ctx->f32, 1);
675 break;
676 case SI_FIX_FETCH_RGBA_32_SNORM:
677 case SI_FIX_FETCH_RGBX_32_SNORM:
678 case SI_FIX_FETCH_RGBA_32_FIXED:
679 case SI_FIX_FETCH_RGBX_32_FIXED: {
680 double scale;
681 if (fix_fetch >= SI_FIX_FETCH_RGBA_32_FIXED)
682 scale = 1.0 / 0x10000;
683 else
684 scale = 1.0 / INT_MAX;
685
686 for (chan = 0; chan < 4; chan++) {
687 out[chan] = ac_to_integer(&ctx->ac, out[chan]);
688 out[chan] = LLVMBuildSIToFP(ctx->ac.builder,
689 out[chan], ctx->f32, "");
690 out[chan] = LLVMBuildFMul(ctx->ac.builder, out[chan],
691 LLVMConstReal(ctx->f32, scale), "");
692 }
693 /* RGBX SINT returns 1 in alpha, which would be rounded to 0 by normalizing. */
694 if (fix_fetch == SI_FIX_FETCH_RGBX_32_SNORM ||
695 fix_fetch == SI_FIX_FETCH_RGBX_32_FIXED)
696 out[3] = LLVMConstReal(ctx->f32, 1);
697 break;
698 }
699 case SI_FIX_FETCH_RGBA_32_USCALED:
700 for (chan = 0; chan < 4; chan++) {
701 out[chan] = ac_to_integer(&ctx->ac, out[chan]);
702 out[chan] = LLVMBuildUIToFP(ctx->ac.builder,
703 out[chan], ctx->f32, "");
704 }
705 break;
706 case SI_FIX_FETCH_RGBA_32_SSCALED:
707 for (chan = 0; chan < 4; chan++) {
708 out[chan] = ac_to_integer(&ctx->ac, out[chan]);
709 out[chan] = LLVMBuildSIToFP(ctx->ac.builder,
710 out[chan], ctx->f32, "");
711 }
712 break;
713 case SI_FIX_FETCH_RG_64_FLOAT:
714 for (chan = 0; chan < 2; chan++)
715 out[chan] = extract_double_to_float(ctx, input[0], chan);
716
717 out[2] = LLVMConstReal(ctx->f32, 0);
718 out[3] = LLVMConstReal(ctx->f32, 1);
719 break;
720 case SI_FIX_FETCH_RGB_64_FLOAT:
721 for (chan = 0; chan < 3; chan++)
722 out[chan] = extract_double_to_float(ctx, input[chan], 0);
723
724 out[3] = LLVMConstReal(ctx->f32, 1);
725 break;
726 case SI_FIX_FETCH_RGBA_64_FLOAT:
727 for (chan = 0; chan < 4; chan++) {
728 out[chan] = extract_double_to_float(ctx, input[chan / 2],
729 chan % 2);
730 }
731 break;
732 case SI_FIX_FETCH_RGB_8:
733 case SI_FIX_FETCH_RGB_8_INT:
734 case SI_FIX_FETCH_RGB_16:
735 case SI_FIX_FETCH_RGB_16_INT:
736 for (chan = 0; chan < 3; chan++) {
737 out[chan] = LLVMBuildExtractElement(ctx->ac.builder,
738 input[chan],
739 ctx->i32_0, "");
740 }
741 if (fix_fetch == SI_FIX_FETCH_RGB_8 ||
742 fix_fetch == SI_FIX_FETCH_RGB_16) {
743 out[3] = LLVMConstReal(ctx->f32, 1);
744 } else {
745 out[3] = ac_to_float(&ctx->ac, ctx->i32_1);
746 }
747 break;
748 }
749 }
750
751 static void declare_input_vs(
752 struct si_shader_context *ctx,
753 unsigned input_index,
754 const struct tgsi_full_declaration *decl,
755 LLVMValueRef out[4])
756 {
757 si_llvm_load_input_vs(ctx, input_index, out);
758 }
759
760 static LLVMValueRef get_primitive_id(struct si_shader_context *ctx,
761 unsigned swizzle)
762 {
763 if (swizzle > 0)
764 return ctx->i32_0;
765
766 switch (ctx->type) {
767 case PIPE_SHADER_VERTEX:
768 return LLVMGetParam(ctx->main_fn,
769 ctx->param_vs_prim_id);
770 case PIPE_SHADER_TESS_CTRL:
771 return ctx->abi.tcs_patch_id;
772 case PIPE_SHADER_TESS_EVAL:
773 return ctx->abi.tes_patch_id;
774 case PIPE_SHADER_GEOMETRY:
775 return ctx->abi.gs_prim_id;
776 default:
777 assert(0);
778 return ctx->i32_0;
779 }
780 }
781
782 /**
783 * Return the value of tgsi_ind_register for indexing.
784 * This is the indirect index with the constant offset added to it.
785 */
786 LLVMValueRef si_get_indirect_index(struct si_shader_context *ctx,
787 const struct tgsi_ind_register *ind,
788 unsigned addr_mul,
789 int rel_index)
790 {
791 LLVMValueRef result;
792
793 if (ind->File == TGSI_FILE_ADDRESS) {
794 result = ctx->addrs[ind->Index][ind->Swizzle];
795 result = LLVMBuildLoad(ctx->ac.builder, result, "");
796 } else {
797 struct tgsi_full_src_register src = {};
798
799 src.Register.File = ind->File;
800 src.Register.Index = ind->Index;
801
802 /* Set the second index to 0 for constants. */
803 if (ind->File == TGSI_FILE_CONSTANT)
804 src.Register.Dimension = 1;
805
806 result = ctx->bld_base.emit_fetch_funcs[ind->File](&ctx->bld_base, &src,
807 TGSI_TYPE_SIGNED,
808 ind->Swizzle);
809 result = ac_to_integer(&ctx->ac, result);
810 }
811
812 return ac_build_imad(&ctx->ac, result, LLVMConstInt(ctx->i32, addr_mul, 0),
813 LLVMConstInt(ctx->i32, rel_index, 0));
814 }
815
816 /**
817 * Like si_get_indirect_index, but restricts the return value to a (possibly
818 * undefined) value inside [0..num).
819 */
820 LLVMValueRef si_get_bounded_indirect_index(struct si_shader_context *ctx,
821 const struct tgsi_ind_register *ind,
822 int rel_index, unsigned num)
823 {
824 LLVMValueRef result = si_get_indirect_index(ctx, ind, 1, rel_index);
825
826 return si_llvm_bound_index(ctx, result, num);
827 }
828
829 static LLVMValueRef get_dw_address_from_generic_indices(struct si_shader_context *ctx,
830 LLVMValueRef vertex_dw_stride,
831 LLVMValueRef base_addr,
832 LLVMValueRef vertex_index,
833 LLVMValueRef param_index,
834 unsigned input_index,
835 ubyte *name,
836 ubyte *index,
837 bool is_patch)
838 {
839 if (vertex_dw_stride) {
840 base_addr = ac_build_imad(&ctx->ac, vertex_index,
841 vertex_dw_stride, base_addr);
842 }
843
844 if (param_index) {
845 base_addr = ac_build_imad(&ctx->ac, param_index,
846 LLVMConstInt(ctx->i32, 4, 0), base_addr);
847 }
848
849 int param = is_patch ?
850 si_shader_io_get_unique_index_patch(name[input_index],
851 index[input_index]) :
852 si_shader_io_get_unique_index(name[input_index],
853 index[input_index], false);
854
855 /* Add the base address of the element. */
856 return LLVMBuildAdd(ctx->ac.builder, base_addr,
857 LLVMConstInt(ctx->i32, param * 4, 0), "");
858 }
859
860 /**
861 * Calculate a dword address given an input or output register and a stride.
862 */
863 static LLVMValueRef get_dw_address(struct si_shader_context *ctx,
864 const struct tgsi_full_dst_register *dst,
865 const struct tgsi_full_src_register *src,
866 LLVMValueRef vertex_dw_stride,
867 LLVMValueRef base_addr)
868 {
869 struct tgsi_shader_info *info = &ctx->shader->selector->info;
870 ubyte *name, *index, *array_first;
871 int input_index;
872 struct tgsi_full_dst_register reg;
873 LLVMValueRef vertex_index = NULL;
874 LLVMValueRef ind_index = NULL;
875
876 /* Set the register description. The address computation is the same
877 * for sources and destinations. */
878 if (src) {
879 reg.Register.File = src->Register.File;
880 reg.Register.Index = src->Register.Index;
881 reg.Register.Indirect = src->Register.Indirect;
882 reg.Register.Dimension = src->Register.Dimension;
883 reg.Indirect = src->Indirect;
884 reg.Dimension = src->Dimension;
885 reg.DimIndirect = src->DimIndirect;
886 } else
887 reg = *dst;
888
889 /* If the register is 2-dimensional (e.g. an array of vertices
890 * in a primitive), calculate the base address of the vertex. */
891 if (reg.Register.Dimension) {
892 if (reg.Dimension.Indirect)
893 vertex_index = si_get_indirect_index(ctx, &reg.DimIndirect,
894 1, reg.Dimension.Index);
895 else
896 vertex_index = LLVMConstInt(ctx->i32, reg.Dimension.Index, 0);
897 }
898
899 /* Get information about the register. */
900 if (reg.Register.File == TGSI_FILE_INPUT) {
901 name = info->input_semantic_name;
902 index = info->input_semantic_index;
903 array_first = info->input_array_first;
904 } else if (reg.Register.File == TGSI_FILE_OUTPUT) {
905 name = info->output_semantic_name;
906 index = info->output_semantic_index;
907 array_first = info->output_array_first;
908 } else {
909 assert(0);
910 return NULL;
911 }
912
913 if (reg.Register.Indirect) {
914 /* Add the relative address of the element. */
915 if (reg.Indirect.ArrayID)
916 input_index = array_first[reg.Indirect.ArrayID];
917 else
918 input_index = reg.Register.Index;
919
920 ind_index = si_get_indirect_index(ctx, &reg.Indirect,
921 1, reg.Register.Index - input_index);
922 } else {
923 input_index = reg.Register.Index;
924 }
925
926 return get_dw_address_from_generic_indices(ctx, vertex_dw_stride,
927 base_addr, vertex_index,
928 ind_index, input_index,
929 name, index,
930 !reg.Register.Dimension);
931 }
932
933 /* The offchip buffer layout for TCS->TES is
934 *
935 * - attribute 0 of patch 0 vertex 0
936 * - attribute 0 of patch 0 vertex 1
937 * - attribute 0 of patch 0 vertex 2
938 * ...
939 * - attribute 0 of patch 1 vertex 0
940 * - attribute 0 of patch 1 vertex 1
941 * ...
942 * - attribute 1 of patch 0 vertex 0
943 * - attribute 1 of patch 0 vertex 1
944 * ...
945 * - per patch attribute 0 of patch 0
946 * - per patch attribute 0 of patch 1
947 * ...
948 *
949 * Note that every attribute has 4 components.
950 */
951 static LLVMValueRef get_tcs_tes_buffer_address(struct si_shader_context *ctx,
952 LLVMValueRef rel_patch_id,
953 LLVMValueRef vertex_index,
954 LLVMValueRef param_index)
955 {
956 LLVMValueRef base_addr, vertices_per_patch, num_patches, total_vertices;
957 LLVMValueRef param_stride, constant16;
958
959 vertices_per_patch = get_num_tcs_out_vertices(ctx);
960 num_patches = si_unpack_param(ctx, ctx->param_tcs_offchip_layout, 0, 6);
961 total_vertices = LLVMBuildMul(ctx->ac.builder, vertices_per_patch,
962 num_patches, "");
963
964 constant16 = LLVMConstInt(ctx->i32, 16, 0);
965 if (vertex_index) {
966 base_addr = ac_build_imad(&ctx->ac, rel_patch_id,
967 vertices_per_patch, vertex_index);
968 param_stride = total_vertices;
969 } else {
970 base_addr = rel_patch_id;
971 param_stride = num_patches;
972 }
973
974 base_addr = ac_build_imad(&ctx->ac, param_index, param_stride, base_addr);
975 base_addr = LLVMBuildMul(ctx->ac.builder, base_addr, constant16, "");
976
977 if (!vertex_index) {
978 LLVMValueRef patch_data_offset =
979 si_unpack_param(ctx, ctx->param_tcs_offchip_layout, 12, 20);
980
981 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
982 patch_data_offset, "");
983 }
984 return base_addr;
985 }
986
987 /* This is a generic helper that can be shared by the NIR and TGSI backends */
988 static LLVMValueRef get_tcs_tes_buffer_address_from_generic_indices(
989 struct si_shader_context *ctx,
990 LLVMValueRef vertex_index,
991 LLVMValueRef param_index,
992 unsigned param_base,
993 ubyte *name,
994 ubyte *index,
995 bool is_patch)
996 {
997 unsigned param_index_base;
998
999 param_index_base = is_patch ?
1000 si_shader_io_get_unique_index_patch(name[param_base], index[param_base]) :
1001 si_shader_io_get_unique_index(name[param_base], index[param_base], false);
1002
1003 if (param_index) {
1004 param_index = LLVMBuildAdd(ctx->ac.builder, param_index,
1005 LLVMConstInt(ctx->i32, param_index_base, 0),
1006 "");
1007 } else {
1008 param_index = LLVMConstInt(ctx->i32, param_index_base, 0);
1009 }
1010
1011 return get_tcs_tes_buffer_address(ctx, get_rel_patch_id(ctx),
1012 vertex_index, param_index);
1013 }
1014
1015 static LLVMValueRef get_tcs_tes_buffer_address_from_reg(
1016 struct si_shader_context *ctx,
1017 const struct tgsi_full_dst_register *dst,
1018 const struct tgsi_full_src_register *src)
1019 {
1020 struct tgsi_shader_info *info = &ctx->shader->selector->info;
1021 ubyte *name, *index, *array_first;
1022 struct tgsi_full_src_register reg;
1023 LLVMValueRef vertex_index = NULL;
1024 LLVMValueRef param_index = NULL;
1025 unsigned param_base;
1026
1027 reg = src ? *src : tgsi_full_src_register_from_dst(dst);
1028
1029 if (reg.Register.Dimension) {
1030
1031 if (reg.Dimension.Indirect)
1032 vertex_index = si_get_indirect_index(ctx, &reg.DimIndirect,
1033 1, reg.Dimension.Index);
1034 else
1035 vertex_index = LLVMConstInt(ctx->i32, reg.Dimension.Index, 0);
1036 }
1037
1038 /* Get information about the register. */
1039 if (reg.Register.File == TGSI_FILE_INPUT) {
1040 name = info->input_semantic_name;
1041 index = info->input_semantic_index;
1042 array_first = info->input_array_first;
1043 } else if (reg.Register.File == TGSI_FILE_OUTPUT) {
1044 name = info->output_semantic_name;
1045 index = info->output_semantic_index;
1046 array_first = info->output_array_first;
1047 } else {
1048 assert(0);
1049 return NULL;
1050 }
1051
1052 if (reg.Register.Indirect) {
1053 if (reg.Indirect.ArrayID)
1054 param_base = array_first[reg.Indirect.ArrayID];
1055 else
1056 param_base = reg.Register.Index;
1057
1058 param_index = si_get_indirect_index(ctx, &reg.Indirect,
1059 1, reg.Register.Index - param_base);
1060
1061 } else {
1062 param_base = reg.Register.Index;
1063 }
1064
1065 return get_tcs_tes_buffer_address_from_generic_indices(ctx, vertex_index,
1066 param_index, param_base,
1067 name, index, !reg.Register.Dimension);
1068 }
1069
1070 static LLVMValueRef buffer_load(struct lp_build_tgsi_context *bld_base,
1071 LLVMTypeRef type, unsigned swizzle,
1072 LLVMValueRef buffer, LLVMValueRef offset,
1073 LLVMValueRef base, bool can_speculate)
1074 {
1075 struct si_shader_context *ctx = si_shader_context(bld_base);
1076 LLVMValueRef value, value2;
1077 LLVMTypeRef vec_type = LLVMVectorType(type, 4);
1078
1079 if (swizzle == ~0) {
1080 value = ac_build_buffer_load(&ctx->ac, buffer, 4, NULL, base, offset,
1081 0, 1, 0, can_speculate, false);
1082
1083 return LLVMBuildBitCast(ctx->ac.builder, value, vec_type, "");
1084 }
1085
1086 if (!llvm_type_is_64bit(ctx, type)) {
1087 value = ac_build_buffer_load(&ctx->ac, buffer, 4, NULL, base, offset,
1088 0, 1, 0, can_speculate, false);
1089
1090 value = LLVMBuildBitCast(ctx->ac.builder, value, vec_type, "");
1091 return LLVMBuildExtractElement(ctx->ac.builder, value,
1092 LLVMConstInt(ctx->i32, swizzle, 0), "");
1093 }
1094
1095 value = ac_build_buffer_load(&ctx->ac, buffer, 1, NULL, base, offset,
1096 swizzle * 4, 1, 0, can_speculate, false);
1097
1098 value2 = ac_build_buffer_load(&ctx->ac, buffer, 1, NULL, base, offset,
1099 swizzle * 4 + 4, 1, 0, can_speculate, false);
1100
1101 return si_llvm_emit_fetch_64bit(bld_base, type, value, value2);
1102 }
1103
1104 /**
1105 * Load from LDS.
1106 *
1107 * \param type output value type
1108 * \param swizzle offset (typically 0..3); it can be ~0, which loads a vec4
1109 * \param dw_addr address in dwords
1110 */
1111 static LLVMValueRef lds_load(struct lp_build_tgsi_context *bld_base,
1112 LLVMTypeRef type, unsigned swizzle,
1113 LLVMValueRef dw_addr)
1114 {
1115 struct si_shader_context *ctx = si_shader_context(bld_base);
1116 LLVMValueRef value;
1117
1118 if (swizzle == ~0) {
1119 LLVMValueRef values[TGSI_NUM_CHANNELS];
1120
1121 for (unsigned chan = 0; chan < TGSI_NUM_CHANNELS; chan++)
1122 values[chan] = lds_load(bld_base, type, chan, dw_addr);
1123
1124 return ac_build_gather_values(&ctx->ac, values,
1125 TGSI_NUM_CHANNELS);
1126 }
1127
1128 /* Split 64-bit loads. */
1129 if (llvm_type_is_64bit(ctx, type)) {
1130 LLVMValueRef lo, hi;
1131
1132 lo = lds_load(bld_base, ctx->i32, swizzle, dw_addr);
1133 hi = lds_load(bld_base, ctx->i32, swizzle + 1, dw_addr);
1134 return si_llvm_emit_fetch_64bit(bld_base, type, lo, hi);
1135 }
1136
1137 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
1138 LLVMConstInt(ctx->i32, swizzle, 0), "");
1139
1140 value = ac_lds_load(&ctx->ac, dw_addr);
1141
1142 return LLVMBuildBitCast(ctx->ac.builder, value, type, "");
1143 }
1144
1145 /**
1146 * Store to LDS.
1147 *
1148 * \param swizzle offset (typically 0..3)
1149 * \param dw_addr address in dwords
1150 * \param value value to store
1151 */
1152 static void lds_store(struct si_shader_context *ctx,
1153 unsigned dw_offset_imm, LLVMValueRef dw_addr,
1154 LLVMValueRef value)
1155 {
1156 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
1157 LLVMConstInt(ctx->i32, dw_offset_imm, 0), "");
1158
1159 ac_lds_store(&ctx->ac, dw_addr, value);
1160 }
1161
1162 enum si_tess_ring {
1163 TCS_FACTOR_RING,
1164 TESS_OFFCHIP_RING_TCS,
1165 TESS_OFFCHIP_RING_TES,
1166 };
1167
1168 static LLVMValueRef get_tess_ring_descriptor(struct si_shader_context *ctx,
1169 enum si_tess_ring ring)
1170 {
1171 LLVMBuilderRef builder = ctx->ac.builder;
1172 unsigned param = ring == TESS_OFFCHIP_RING_TES ? ctx->param_tes_offchip_addr :
1173 ctx->param_tcs_out_lds_layout;
1174 LLVMValueRef addr = LLVMGetParam(ctx->main_fn, param);
1175
1176 /* TCS only receives high 13 bits of the address. */
1177 if (ring == TESS_OFFCHIP_RING_TCS || ring == TCS_FACTOR_RING) {
1178 addr = LLVMBuildAnd(builder, addr,
1179 LLVMConstInt(ctx->i32, 0xfff80000, 0), "");
1180 }
1181
1182 if (ring == TCS_FACTOR_RING) {
1183 unsigned tf_offset = ctx->screen->tess_offchip_ring_size;
1184 addr = LLVMBuildAdd(builder, addr,
1185 LLVMConstInt(ctx->i32, tf_offset, 0), "");
1186 }
1187
1188 LLVMValueRef desc[4];
1189 desc[0] = addr;
1190 desc[1] = LLVMConstInt(ctx->i32,
1191 S_008F04_BASE_ADDRESS_HI(ctx->screen->info.address32_hi), 0);
1192 desc[2] = LLVMConstInt(ctx->i32, 0xffffffff, 0);
1193 desc[3] = LLVMConstInt(ctx->i32,
1194 S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1195 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1196 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1197 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1198 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1199 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32), 0);
1200
1201 return ac_build_gather_values(&ctx->ac, desc, 4);
1202 }
1203
1204 static LLVMValueRef fetch_input_tcs(
1205 struct lp_build_tgsi_context *bld_base,
1206 const struct tgsi_full_src_register *reg,
1207 enum tgsi_opcode_type type, unsigned swizzle_in)
1208 {
1209 struct si_shader_context *ctx = si_shader_context(bld_base);
1210 LLVMValueRef dw_addr, stride;
1211 unsigned swizzle = swizzle_in & 0xffff;
1212 stride = get_tcs_in_vertex_dw_stride(ctx);
1213 dw_addr = get_tcs_in_current_patch_offset(ctx);
1214 dw_addr = get_dw_address(ctx, NULL, reg, stride, dw_addr);
1215
1216 return lds_load(bld_base, tgsi2llvmtype(bld_base, type), swizzle, dw_addr);
1217 }
1218
1219 static LLVMValueRef si_nir_load_tcs_varyings(struct ac_shader_abi *abi,
1220 LLVMTypeRef type,
1221 LLVMValueRef vertex_index,
1222 LLVMValueRef param_index,
1223 unsigned const_index,
1224 unsigned location,
1225 unsigned driver_location,
1226 unsigned component,
1227 unsigned num_components,
1228 bool is_patch,
1229 bool is_compact,
1230 bool load_input)
1231 {
1232 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1233 struct tgsi_shader_info *info = &ctx->shader->selector->info;
1234 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
1235 LLVMValueRef dw_addr, stride;
1236
1237 driver_location = driver_location / 4;
1238
1239 if (load_input) {
1240 stride = get_tcs_in_vertex_dw_stride(ctx);
1241 dw_addr = get_tcs_in_current_patch_offset(ctx);
1242 } else {
1243 if (is_patch) {
1244 stride = NULL;
1245 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1246 } else {
1247 stride = get_tcs_out_vertex_dw_stride(ctx);
1248 dw_addr = get_tcs_out_current_patch_offset(ctx);
1249 }
1250 }
1251
1252 if (param_index) {
1253 /* Add the constant index to the indirect index */
1254 param_index = LLVMBuildAdd(ctx->ac.builder, param_index,
1255 LLVMConstInt(ctx->i32, const_index, 0), "");
1256 } else {
1257 param_index = LLVMConstInt(ctx->i32, const_index, 0);
1258 }
1259
1260 ubyte *names;
1261 ubyte *indices;
1262 if (load_input) {
1263 names = info->input_semantic_name;
1264 indices = info->input_semantic_index;
1265 } else {
1266 names = info->output_semantic_name;
1267 indices = info->output_semantic_index;
1268 }
1269
1270 dw_addr = get_dw_address_from_generic_indices(ctx, stride, dw_addr,
1271 vertex_index, param_index,
1272 driver_location,
1273 names, indices,
1274 is_patch);
1275
1276 LLVMValueRef value[4];
1277 for (unsigned i = 0; i < num_components; i++) {
1278 unsigned offset = i;
1279 if (llvm_type_is_64bit(ctx, type))
1280 offset *= 2;
1281
1282 offset += component;
1283 value[i + component] = lds_load(bld_base, type, offset, dw_addr);
1284 }
1285
1286 return ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
1287 }
1288
1289 static LLVMValueRef fetch_output_tcs(
1290 struct lp_build_tgsi_context *bld_base,
1291 const struct tgsi_full_src_register *reg,
1292 enum tgsi_opcode_type type, unsigned swizzle_in)
1293 {
1294 struct si_shader_context *ctx = si_shader_context(bld_base);
1295 LLVMValueRef dw_addr, stride;
1296 unsigned swizzle = (swizzle_in & 0xffff);
1297
1298 if (reg->Register.Dimension) {
1299 stride = get_tcs_out_vertex_dw_stride(ctx);
1300 dw_addr = get_tcs_out_current_patch_offset(ctx);
1301 dw_addr = get_dw_address(ctx, NULL, reg, stride, dw_addr);
1302 } else {
1303 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1304 dw_addr = get_dw_address(ctx, NULL, reg, NULL, dw_addr);
1305 }
1306
1307 return lds_load(bld_base, tgsi2llvmtype(bld_base, type), swizzle, dw_addr);
1308 }
1309
1310 static LLVMValueRef fetch_input_tes(
1311 struct lp_build_tgsi_context *bld_base,
1312 const struct tgsi_full_src_register *reg,
1313 enum tgsi_opcode_type type, unsigned swizzle_in)
1314 {
1315 struct si_shader_context *ctx = si_shader_context(bld_base);
1316 LLVMValueRef base, addr;
1317 unsigned swizzle = (swizzle_in & 0xffff);
1318
1319 base = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
1320 addr = get_tcs_tes_buffer_address_from_reg(ctx, NULL, reg);
1321
1322 return buffer_load(bld_base, tgsi2llvmtype(bld_base, type), swizzle,
1323 ctx->tess_offchip_ring, base, addr, true);
1324 }
1325
1326 LLVMValueRef si_nir_load_input_tes(struct ac_shader_abi *abi,
1327 LLVMTypeRef type,
1328 LLVMValueRef vertex_index,
1329 LLVMValueRef param_index,
1330 unsigned const_index,
1331 unsigned location,
1332 unsigned driver_location,
1333 unsigned component,
1334 unsigned num_components,
1335 bool is_patch,
1336 bool is_compact,
1337 bool load_input)
1338 {
1339 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1340 struct tgsi_shader_info *info = &ctx->shader->selector->info;
1341 LLVMValueRef base, addr;
1342
1343 driver_location = driver_location / 4;
1344
1345 base = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
1346
1347 if (param_index) {
1348 /* Add the constant index to the indirect index */
1349 param_index = LLVMBuildAdd(ctx->ac.builder, param_index,
1350 LLVMConstInt(ctx->i32, const_index, 0), "");
1351 } else {
1352 param_index = LLVMConstInt(ctx->i32, const_index, 0);
1353 }
1354
1355 addr = get_tcs_tes_buffer_address_from_generic_indices(ctx, vertex_index,
1356 param_index, driver_location,
1357 info->input_semantic_name,
1358 info->input_semantic_index,
1359 is_patch);
1360
1361 /* TODO: This will generate rather ordinary llvm code, although it
1362 * should be easy for the optimiser to fix up. In future we might want
1363 * to refactor buffer_load(), but for now this maximises code sharing
1364 * between the NIR and TGSI backends.
1365 */
1366 LLVMValueRef value[4];
1367 for (unsigned i = 0; i < num_components; i++) {
1368 unsigned offset = i;
1369 if (llvm_type_is_64bit(ctx, type))
1370 offset *= 2;
1371
1372 offset += component;
1373 value[i + component] = buffer_load(&ctx->bld_base, type, offset,
1374 ctx->tess_offchip_ring, base, addr, true);
1375 }
1376
1377 return ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
1378 }
1379
1380 static void store_output_tcs(struct lp_build_tgsi_context *bld_base,
1381 const struct tgsi_full_instruction *inst,
1382 const struct tgsi_opcode_info *info,
1383 unsigned index,
1384 LLVMValueRef dst[4])
1385 {
1386 struct si_shader_context *ctx = si_shader_context(bld_base);
1387 const struct tgsi_full_dst_register *reg = &inst->Dst[index];
1388 const struct tgsi_shader_info *sh_info = &ctx->shader->selector->info;
1389 unsigned chan_index;
1390 LLVMValueRef dw_addr, stride;
1391 LLVMValueRef buffer, base, buf_addr;
1392 LLVMValueRef values[4];
1393 bool skip_lds_store;
1394 bool is_tess_factor = false, is_tess_inner = false;
1395
1396 /* Only handle per-patch and per-vertex outputs here.
1397 * Vectors will be lowered to scalars and this function will be called again.
1398 */
1399 if (reg->Register.File != TGSI_FILE_OUTPUT ||
1400 (dst[0] && LLVMGetTypeKind(LLVMTypeOf(dst[0])) == LLVMVectorTypeKind)) {
1401 si_llvm_emit_store(bld_base, inst, info, index, dst);
1402 return;
1403 }
1404
1405 if (reg->Register.Dimension) {
1406 stride = get_tcs_out_vertex_dw_stride(ctx);
1407 dw_addr = get_tcs_out_current_patch_offset(ctx);
1408 dw_addr = get_dw_address(ctx, reg, NULL, stride, dw_addr);
1409 skip_lds_store = !sh_info->reads_pervertex_outputs;
1410 } else {
1411 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1412 dw_addr = get_dw_address(ctx, reg, NULL, NULL, dw_addr);
1413 skip_lds_store = !sh_info->reads_perpatch_outputs;
1414
1415 if (!reg->Register.Indirect) {
1416 int name = sh_info->output_semantic_name[reg->Register.Index];
1417
1418 /* Always write tess factors into LDS for the TCS epilog. */
1419 if (name == TGSI_SEMANTIC_TESSINNER ||
1420 name == TGSI_SEMANTIC_TESSOUTER) {
1421 /* The epilog doesn't read LDS if invocation 0 defines tess factors. */
1422 skip_lds_store = !sh_info->reads_tessfactor_outputs &&
1423 ctx->shader->selector->tcs_info.tessfactors_are_def_in_all_invocs;
1424 is_tess_factor = true;
1425 is_tess_inner = name == TGSI_SEMANTIC_TESSINNER;
1426 }
1427 }
1428 }
1429
1430 buffer = get_tess_ring_descriptor(ctx, TESS_OFFCHIP_RING_TCS);
1431
1432 base = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
1433 buf_addr = get_tcs_tes_buffer_address_from_reg(ctx, reg, NULL);
1434
1435 uint32_t writemask = reg->Register.WriteMask;
1436 while (writemask) {
1437 chan_index = u_bit_scan(&writemask);
1438 LLVMValueRef value = dst[chan_index];
1439
1440 if (inst->Instruction.Saturate)
1441 value = ac_build_clamp(&ctx->ac, value);
1442
1443 /* Skip LDS stores if there is no LDS read of this output. */
1444 if (!skip_lds_store)
1445 lds_store(ctx, chan_index, dw_addr, value);
1446
1447 value = ac_to_integer(&ctx->ac, value);
1448 values[chan_index] = value;
1449
1450 if (reg->Register.WriteMask != 0xF && !is_tess_factor) {
1451 ac_build_buffer_store_dword(&ctx->ac, buffer, value, 1,
1452 buf_addr, base,
1453 4 * chan_index, 1, 0, true, false);
1454 }
1455
1456 /* Write tess factors into VGPRs for the epilog. */
1457 if (is_tess_factor &&
1458 ctx->shader->selector->tcs_info.tessfactors_are_def_in_all_invocs) {
1459 if (!is_tess_inner) {
1460 LLVMBuildStore(ctx->ac.builder, value, /* outer */
1461 ctx->invoc0_tess_factors[chan_index]);
1462 } else if (chan_index < 2) {
1463 LLVMBuildStore(ctx->ac.builder, value, /* inner */
1464 ctx->invoc0_tess_factors[4 + chan_index]);
1465 }
1466 }
1467 }
1468
1469 if (reg->Register.WriteMask == 0xF && !is_tess_factor) {
1470 LLVMValueRef value = ac_build_gather_values(&ctx->ac,
1471 values, 4);
1472 ac_build_buffer_store_dword(&ctx->ac, buffer, value, 4, buf_addr,
1473 base, 0, 1, 0, true, false);
1474 }
1475 }
1476
1477 static void si_nir_store_output_tcs(struct ac_shader_abi *abi,
1478 const struct nir_variable *var,
1479 LLVMValueRef vertex_index,
1480 LLVMValueRef param_index,
1481 unsigned const_index,
1482 LLVMValueRef src,
1483 unsigned writemask)
1484 {
1485 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1486 struct tgsi_shader_info *info = &ctx->shader->selector->info;
1487 const unsigned component = var->data.location_frac;
1488 const bool is_patch = var->data.patch;
1489 unsigned driver_location = var->data.driver_location;
1490 LLVMValueRef dw_addr, stride;
1491 LLVMValueRef buffer, base, addr;
1492 LLVMValueRef values[4];
1493 bool skip_lds_store;
1494 bool is_tess_factor = false, is_tess_inner = false;
1495
1496 driver_location = driver_location / 4;
1497
1498 if (param_index) {
1499 /* Add the constant index to the indirect index */
1500 param_index = LLVMBuildAdd(ctx->ac.builder, param_index,
1501 LLVMConstInt(ctx->i32, const_index, 0), "");
1502 } else {
1503 if (const_index != 0)
1504 param_index = LLVMConstInt(ctx->i32, const_index, 0);
1505 }
1506
1507 if (!is_patch) {
1508 stride = get_tcs_out_vertex_dw_stride(ctx);
1509 dw_addr = get_tcs_out_current_patch_offset(ctx);
1510 dw_addr = get_dw_address_from_generic_indices(ctx, stride, dw_addr,
1511 vertex_index, param_index,
1512 driver_location,
1513 info->output_semantic_name,
1514 info->output_semantic_index,
1515 is_patch);
1516
1517 skip_lds_store = !info->reads_pervertex_outputs;
1518 } else {
1519 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1520 dw_addr = get_dw_address_from_generic_indices(ctx, NULL, dw_addr,
1521 vertex_index, param_index,
1522 driver_location,
1523 info->output_semantic_name,
1524 info->output_semantic_index,
1525 is_patch);
1526
1527 skip_lds_store = !info->reads_perpatch_outputs;
1528
1529 if (!param_index) {
1530 int name = info->output_semantic_name[driver_location];
1531
1532 /* Always write tess factors into LDS for the TCS epilog. */
1533 if (name == TGSI_SEMANTIC_TESSINNER ||
1534 name == TGSI_SEMANTIC_TESSOUTER) {
1535 /* The epilog doesn't read LDS if invocation 0 defines tess factors. */
1536 skip_lds_store = !info->reads_tessfactor_outputs &&
1537 ctx->shader->selector->tcs_info.tessfactors_are_def_in_all_invocs;
1538 is_tess_factor = true;
1539 is_tess_inner = name == TGSI_SEMANTIC_TESSINNER;
1540 }
1541 }
1542 }
1543
1544 buffer = get_tess_ring_descriptor(ctx, TESS_OFFCHIP_RING_TCS);
1545
1546 base = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
1547
1548 addr = get_tcs_tes_buffer_address_from_generic_indices(ctx, vertex_index,
1549 param_index, driver_location,
1550 info->output_semantic_name,
1551 info->output_semantic_index,
1552 is_patch);
1553
1554 for (unsigned chan = 0; chan < 4; chan++) {
1555 if (!(writemask & (1 << chan)))
1556 continue;
1557 LLVMValueRef value = ac_llvm_extract_elem(&ctx->ac, src, chan - component);
1558
1559 /* Skip LDS stores if there is no LDS read of this output. */
1560 if (!skip_lds_store)
1561 lds_store(ctx, chan, dw_addr, value);
1562
1563 value = ac_to_integer(&ctx->ac, value);
1564 values[chan] = value;
1565
1566 if (writemask != 0xF && !is_tess_factor) {
1567 ac_build_buffer_store_dword(&ctx->ac, buffer, value, 1,
1568 addr, base,
1569 4 * chan, 1, 0, true, false);
1570 }
1571
1572 /* Write tess factors into VGPRs for the epilog. */
1573 if (is_tess_factor &&
1574 ctx->shader->selector->tcs_info.tessfactors_are_def_in_all_invocs) {
1575 if (!is_tess_inner) {
1576 LLVMBuildStore(ctx->ac.builder, value, /* outer */
1577 ctx->invoc0_tess_factors[chan]);
1578 } else if (chan < 2) {
1579 LLVMBuildStore(ctx->ac.builder, value, /* inner */
1580 ctx->invoc0_tess_factors[4 + chan]);
1581 }
1582 }
1583 }
1584
1585 if (writemask == 0xF && !is_tess_factor) {
1586 LLVMValueRef value = ac_build_gather_values(&ctx->ac,
1587 values, 4);
1588 ac_build_buffer_store_dword(&ctx->ac, buffer, value, 4, addr,
1589 base, 0, 1, 0, true, false);
1590 }
1591 }
1592
1593 LLVMValueRef si_llvm_load_input_gs(struct ac_shader_abi *abi,
1594 unsigned input_index,
1595 unsigned vtx_offset_param,
1596 LLVMTypeRef type,
1597 unsigned swizzle)
1598 {
1599 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1600 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
1601 struct si_shader *shader = ctx->shader;
1602 LLVMValueRef vtx_offset, soffset;
1603 struct tgsi_shader_info *info = &shader->selector->info;
1604 unsigned semantic_name = info->input_semantic_name[input_index];
1605 unsigned semantic_index = info->input_semantic_index[input_index];
1606 unsigned param;
1607 LLVMValueRef value;
1608
1609 param = si_shader_io_get_unique_index(semantic_name, semantic_index, false);
1610
1611 /* GFX9 has the ESGS ring in LDS. */
1612 if (ctx->screen->info.chip_class >= GFX9) {
1613 unsigned index = vtx_offset_param;
1614
1615 switch (index / 2) {
1616 case 0:
1617 vtx_offset = si_unpack_param(ctx, ctx->param_gs_vtx01_offset,
1618 index % 2 ? 16 : 0, 16);
1619 break;
1620 case 1:
1621 vtx_offset = si_unpack_param(ctx, ctx->param_gs_vtx23_offset,
1622 index % 2 ? 16 : 0, 16);
1623 break;
1624 case 2:
1625 vtx_offset = si_unpack_param(ctx, ctx->param_gs_vtx45_offset,
1626 index % 2 ? 16 : 0, 16);
1627 break;
1628 default:
1629 assert(0);
1630 return NULL;
1631 }
1632
1633 vtx_offset = LLVMBuildAdd(ctx->ac.builder, vtx_offset,
1634 LLVMConstInt(ctx->i32, param * 4, 0), "");
1635 return lds_load(bld_base, type, swizzle, vtx_offset);
1636 }
1637
1638 /* GFX6: input load from the ESGS ring in memory. */
1639 if (swizzle == ~0) {
1640 LLVMValueRef values[TGSI_NUM_CHANNELS];
1641 unsigned chan;
1642 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1643 values[chan] = si_llvm_load_input_gs(abi, input_index, vtx_offset_param,
1644 type, chan);
1645 }
1646 return ac_build_gather_values(&ctx->ac, values,
1647 TGSI_NUM_CHANNELS);
1648 }
1649
1650 /* Get the vertex offset parameter on GFX6. */
1651 LLVMValueRef gs_vtx_offset = ctx->gs_vtx_offset[vtx_offset_param];
1652
1653 vtx_offset = LLVMBuildMul(ctx->ac.builder, gs_vtx_offset,
1654 LLVMConstInt(ctx->i32, 4, 0), "");
1655
1656 soffset = LLVMConstInt(ctx->i32, (param * 4 + swizzle) * 256, 0);
1657
1658 value = ac_build_buffer_load(&ctx->ac, ctx->esgs_ring, 1, ctx->i32_0,
1659 vtx_offset, soffset, 0, 1, 0, true, false);
1660 if (llvm_type_is_64bit(ctx, type)) {
1661 LLVMValueRef value2;
1662 soffset = LLVMConstInt(ctx->i32, (param * 4 + swizzle + 1) * 256, 0);
1663
1664 value2 = ac_build_buffer_load(&ctx->ac, ctx->esgs_ring, 1,
1665 ctx->i32_0, vtx_offset, soffset,
1666 0, 1, 0, true, false);
1667 return si_llvm_emit_fetch_64bit(bld_base, type, value, value2);
1668 }
1669 return LLVMBuildBitCast(ctx->ac.builder, value, type, "");
1670 }
1671
1672 static LLVMValueRef si_nir_load_input_gs(struct ac_shader_abi *abi,
1673 unsigned location,
1674 unsigned driver_location,
1675 unsigned component,
1676 unsigned num_components,
1677 unsigned vertex_index,
1678 unsigned const_index,
1679 LLVMTypeRef type)
1680 {
1681 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1682
1683 LLVMValueRef value[4];
1684 for (unsigned i = 0; i < num_components; i++) {
1685 unsigned offset = i;
1686 if (llvm_type_is_64bit(ctx, type))
1687 offset *= 2;
1688
1689 offset += component;
1690 value[i + component] = si_llvm_load_input_gs(&ctx->abi, driver_location / 4,
1691 vertex_index, type, offset);
1692 }
1693
1694 return ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
1695 }
1696
1697 static LLVMValueRef fetch_input_gs(
1698 struct lp_build_tgsi_context *bld_base,
1699 const struct tgsi_full_src_register *reg,
1700 enum tgsi_opcode_type type,
1701 unsigned swizzle_in)
1702 {
1703 struct si_shader_context *ctx = si_shader_context(bld_base);
1704 struct tgsi_shader_info *info = &ctx->shader->selector->info;
1705 unsigned swizzle = swizzle_in & 0xffff;
1706
1707 unsigned semantic_name = info->input_semantic_name[reg->Register.Index];
1708 if (swizzle != ~0 && semantic_name == TGSI_SEMANTIC_PRIMID)
1709 return get_primitive_id(ctx, swizzle);
1710
1711 if (!reg->Register.Dimension)
1712 return NULL;
1713
1714 return si_llvm_load_input_gs(&ctx->abi, reg->Register.Index,
1715 reg->Dimension.Index,
1716 tgsi2llvmtype(bld_base, type),
1717 swizzle);
1718 }
1719
1720 static int lookup_interp_param_index(unsigned interpolate, unsigned location)
1721 {
1722 switch (interpolate) {
1723 case TGSI_INTERPOLATE_CONSTANT:
1724 return 0;
1725
1726 case TGSI_INTERPOLATE_LINEAR:
1727 if (location == TGSI_INTERPOLATE_LOC_SAMPLE)
1728 return SI_PARAM_LINEAR_SAMPLE;
1729 else if (location == TGSI_INTERPOLATE_LOC_CENTROID)
1730 return SI_PARAM_LINEAR_CENTROID;
1731 else
1732 return SI_PARAM_LINEAR_CENTER;
1733 break;
1734 case TGSI_INTERPOLATE_COLOR:
1735 case TGSI_INTERPOLATE_PERSPECTIVE:
1736 if (location == TGSI_INTERPOLATE_LOC_SAMPLE)
1737 return SI_PARAM_PERSP_SAMPLE;
1738 else if (location == TGSI_INTERPOLATE_LOC_CENTROID)
1739 return SI_PARAM_PERSP_CENTROID;
1740 else
1741 return SI_PARAM_PERSP_CENTER;
1742 break;
1743 default:
1744 fprintf(stderr, "Warning: Unhandled interpolation mode.\n");
1745 return -1;
1746 }
1747 }
1748
1749 static LLVMValueRef si_build_fs_interp(struct si_shader_context *ctx,
1750 unsigned attr_index, unsigned chan,
1751 LLVMValueRef prim_mask,
1752 LLVMValueRef i, LLVMValueRef j)
1753 {
1754 if (i || j) {
1755 return ac_build_fs_interp(&ctx->ac,
1756 LLVMConstInt(ctx->i32, chan, 0),
1757 LLVMConstInt(ctx->i32, attr_index, 0),
1758 prim_mask, i, j);
1759 }
1760 return ac_build_fs_interp_mov(&ctx->ac,
1761 LLVMConstInt(ctx->i32, 2, 0), /* P0 */
1762 LLVMConstInt(ctx->i32, chan, 0),
1763 LLVMConstInt(ctx->i32, attr_index, 0),
1764 prim_mask);
1765 }
1766
1767 /**
1768 * Interpolate a fragment shader input.
1769 *
1770 * @param ctx context
1771 * @param input_index index of the input in hardware
1772 * @param semantic_name TGSI_SEMANTIC_*
1773 * @param semantic_index semantic index
1774 * @param num_interp_inputs number of all interpolated inputs (= BCOLOR offset)
1775 * @param colors_read_mask color components read (4 bits for each color, 8 bits in total)
1776 * @param interp_param interpolation weights (i,j)
1777 * @param prim_mask SI_PARAM_PRIM_MASK
1778 * @param face SI_PARAM_FRONT_FACE
1779 * @param result the return value (4 components)
1780 */
1781 static void interp_fs_input(struct si_shader_context *ctx,
1782 unsigned input_index,
1783 unsigned semantic_name,
1784 unsigned semantic_index,
1785 unsigned num_interp_inputs,
1786 unsigned colors_read_mask,
1787 LLVMValueRef interp_param,
1788 LLVMValueRef prim_mask,
1789 LLVMValueRef face,
1790 LLVMValueRef result[4])
1791 {
1792 LLVMValueRef i = NULL, j = NULL;
1793 unsigned chan;
1794
1795 /* fs.constant returns the param from the middle vertex, so it's not
1796 * really useful for flat shading. It's meant to be used for custom
1797 * interpolation (but the intrinsic can't fetch from the other two
1798 * vertices).
1799 *
1800 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
1801 * to do the right thing. The only reason we use fs.constant is that
1802 * fs.interp cannot be used on integers, because they can be equal
1803 * to NaN.
1804 *
1805 * When interp is false we will use fs.constant or for newer llvm,
1806 * amdgcn.interp.mov.
1807 */
1808 bool interp = interp_param != NULL;
1809
1810 if (interp) {
1811 interp_param = LLVMBuildBitCast(ctx->ac.builder, interp_param,
1812 LLVMVectorType(ctx->f32, 2), "");
1813
1814 i = LLVMBuildExtractElement(ctx->ac.builder, interp_param,
1815 ctx->i32_0, "");
1816 j = LLVMBuildExtractElement(ctx->ac.builder, interp_param,
1817 ctx->i32_1, "");
1818 }
1819
1820 if (semantic_name == TGSI_SEMANTIC_COLOR &&
1821 ctx->shader->key.part.ps.prolog.color_two_side) {
1822 LLVMValueRef is_face_positive;
1823
1824 /* If BCOLOR0 is used, BCOLOR1 is at offset "num_inputs + 1",
1825 * otherwise it's at offset "num_inputs".
1826 */
1827 unsigned back_attr_offset = num_interp_inputs;
1828 if (semantic_index == 1 && colors_read_mask & 0xf)
1829 back_attr_offset += 1;
1830
1831 is_face_positive = LLVMBuildICmp(ctx->ac.builder, LLVMIntNE,
1832 face, ctx->i32_0, "");
1833
1834 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1835 LLVMValueRef front, back;
1836
1837 front = si_build_fs_interp(ctx,
1838 input_index, chan,
1839 prim_mask, i, j);
1840 back = si_build_fs_interp(ctx,
1841 back_attr_offset, chan,
1842 prim_mask, i, j);
1843
1844 result[chan] = LLVMBuildSelect(ctx->ac.builder,
1845 is_face_positive,
1846 front,
1847 back,
1848 "");
1849 }
1850 } else if (semantic_name == TGSI_SEMANTIC_FOG) {
1851 result[0] = si_build_fs_interp(ctx, input_index,
1852 0, prim_mask, i, j);
1853 result[1] =
1854 result[2] = LLVMConstReal(ctx->f32, 0.0f);
1855 result[3] = LLVMConstReal(ctx->f32, 1.0f);
1856 } else {
1857 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1858 result[chan] = si_build_fs_interp(ctx,
1859 input_index, chan,
1860 prim_mask, i, j);
1861 }
1862 }
1863 }
1864
1865 void si_llvm_load_input_fs(
1866 struct si_shader_context *ctx,
1867 unsigned input_index,
1868 LLVMValueRef out[4])
1869 {
1870 struct si_shader *shader = ctx->shader;
1871 struct tgsi_shader_info *info = &shader->selector->info;
1872 LLVMValueRef main_fn = ctx->main_fn;
1873 LLVMValueRef interp_param = NULL;
1874 int interp_param_idx;
1875 enum tgsi_semantic semantic_name = info->input_semantic_name[input_index];
1876 unsigned semantic_index = info->input_semantic_index[input_index];
1877 enum tgsi_interpolate_mode interp_mode = info->input_interpolate[input_index];
1878 enum tgsi_interpolate_loc interp_loc = info->input_interpolate_loc[input_index];
1879
1880 /* Get colors from input VGPRs (set by the prolog). */
1881 if (semantic_name == TGSI_SEMANTIC_COLOR) {
1882 unsigned colors_read = shader->selector->info.colors_read;
1883 unsigned mask = colors_read >> (semantic_index * 4);
1884 unsigned offset = SI_PARAM_POS_FIXED_PT + 1 +
1885 (semantic_index ? util_bitcount(colors_read & 0xf) : 0);
1886 LLVMValueRef undef = LLVMGetUndef(ctx->f32);
1887
1888 out[0] = mask & 0x1 ? LLVMGetParam(main_fn, offset++) : undef;
1889 out[1] = mask & 0x2 ? LLVMGetParam(main_fn, offset++) : undef;
1890 out[2] = mask & 0x4 ? LLVMGetParam(main_fn, offset++) : undef;
1891 out[3] = mask & 0x8 ? LLVMGetParam(main_fn, offset++) : undef;
1892 return;
1893 }
1894
1895 interp_param_idx = lookup_interp_param_index(interp_mode, interp_loc);
1896 if (interp_param_idx == -1)
1897 return;
1898 else if (interp_param_idx) {
1899 interp_param = LLVMGetParam(ctx->main_fn, interp_param_idx);
1900 }
1901
1902 interp_fs_input(ctx, input_index, semantic_name,
1903 semantic_index, 0, /* this param is unused */
1904 shader->selector->info.colors_read, interp_param,
1905 ctx->abi.prim_mask,
1906 LLVMGetParam(main_fn, SI_PARAM_FRONT_FACE),
1907 &out[0]);
1908 }
1909
1910 static void declare_input_fs(
1911 struct si_shader_context *ctx,
1912 unsigned input_index,
1913 const struct tgsi_full_declaration *decl,
1914 LLVMValueRef out[4])
1915 {
1916 si_llvm_load_input_fs(ctx, input_index, out);
1917 }
1918
1919 LLVMValueRef si_get_sample_id(struct si_shader_context *ctx)
1920 {
1921 return si_unpack_param(ctx, SI_PARAM_ANCILLARY, 8, 4);
1922 }
1923
1924 static LLVMValueRef get_base_vertex(struct ac_shader_abi *abi)
1925 {
1926 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1927
1928 /* For non-indexed draws, the base vertex set by the driver
1929 * (for direct draws) or the CP (for indirect draws) is the
1930 * first vertex ID, but GLSL expects 0 to be returned.
1931 */
1932 LLVMValueRef vs_state = LLVMGetParam(ctx->main_fn,
1933 ctx->param_vs_state_bits);
1934 LLVMValueRef indexed;
1935
1936 indexed = LLVMBuildLShr(ctx->ac.builder, vs_state, ctx->i32_1, "");
1937 indexed = LLVMBuildTrunc(ctx->ac.builder, indexed, ctx->i1, "");
1938
1939 return LLVMBuildSelect(ctx->ac.builder, indexed, ctx->abi.base_vertex,
1940 ctx->i32_0, "");
1941 }
1942
1943 static LLVMValueRef get_block_size(struct ac_shader_abi *abi)
1944 {
1945 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1946
1947 LLVMValueRef values[3];
1948 LLVMValueRef result;
1949 unsigned i;
1950 unsigned *properties = ctx->shader->selector->info.properties;
1951
1952 if (properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] != 0) {
1953 unsigned sizes[3] = {
1954 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH],
1955 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT],
1956 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH]
1957 };
1958
1959 for (i = 0; i < 3; ++i)
1960 values[i] = LLVMConstInt(ctx->i32, sizes[i], 0);
1961
1962 result = ac_build_gather_values(&ctx->ac, values, 3);
1963 } else {
1964 result = LLVMGetParam(ctx->main_fn, ctx->param_block_size);
1965 }
1966
1967 return result;
1968 }
1969
1970 /**
1971 * Load a dword from a constant buffer.
1972 */
1973 static LLVMValueRef buffer_load_const(struct si_shader_context *ctx,
1974 LLVMValueRef resource,
1975 LLVMValueRef offset)
1976 {
1977 return ac_build_buffer_load(&ctx->ac, resource, 1, NULL, offset, NULL,
1978 0, 0, 0, true, true);
1979 }
1980
1981 static LLVMValueRef load_sample_position(struct ac_shader_abi *abi, LLVMValueRef sample_id)
1982 {
1983 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1984 LLVMValueRef desc = LLVMGetParam(ctx->main_fn, ctx->param_rw_buffers);
1985 LLVMValueRef buf_index = LLVMConstInt(ctx->i32, SI_PS_CONST_SAMPLE_POSITIONS, 0);
1986 LLVMValueRef resource = ac_build_load_to_sgpr(&ctx->ac, desc, buf_index);
1987
1988 /* offset = sample_id * 8 (8 = 2 floats containing samplepos.xy) */
1989 LLVMValueRef offset0 = LLVMBuildMul(ctx->ac.builder, sample_id, LLVMConstInt(ctx->i32, 8, 0), "");
1990 LLVMValueRef offset1 = LLVMBuildAdd(ctx->ac.builder, offset0, LLVMConstInt(ctx->i32, 4, 0), "");
1991
1992 LLVMValueRef pos[4] = {
1993 buffer_load_const(ctx, resource, offset0),
1994 buffer_load_const(ctx, resource, offset1),
1995 LLVMConstReal(ctx->f32, 0),
1996 LLVMConstReal(ctx->f32, 0)
1997 };
1998
1999 return ac_build_gather_values(&ctx->ac, pos, 4);
2000 }
2001
2002 static LLVMValueRef load_sample_mask_in(struct ac_shader_abi *abi)
2003 {
2004 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
2005 return ac_to_integer(&ctx->ac, abi->sample_coverage);
2006 }
2007
2008 static LLVMValueRef si_load_tess_coord(struct ac_shader_abi *abi)
2009 {
2010 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
2011 LLVMValueRef coord[4] = {
2012 LLVMGetParam(ctx->main_fn, ctx->param_tes_u),
2013 LLVMGetParam(ctx->main_fn, ctx->param_tes_v),
2014 ctx->ac.f32_0,
2015 ctx->ac.f32_0
2016 };
2017
2018 /* For triangles, the vector should be (u, v, 1-u-v). */
2019 if (ctx->shader->selector->info.properties[TGSI_PROPERTY_TES_PRIM_MODE] ==
2020 PIPE_PRIM_TRIANGLES) {
2021 coord[2] = LLVMBuildFSub(ctx->ac.builder, ctx->ac.f32_1,
2022 LLVMBuildFAdd(ctx->ac.builder,
2023 coord[0], coord[1], ""), "");
2024 }
2025 return ac_build_gather_values(&ctx->ac, coord, 4);
2026 }
2027
2028 static LLVMValueRef load_tess_level(struct si_shader_context *ctx,
2029 unsigned semantic_name)
2030 {
2031 LLVMValueRef base, addr;
2032
2033 int param = si_shader_io_get_unique_index_patch(semantic_name, 0);
2034
2035 base = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
2036 addr = get_tcs_tes_buffer_address(ctx, get_rel_patch_id(ctx), NULL,
2037 LLVMConstInt(ctx->i32, param, 0));
2038
2039 return buffer_load(&ctx->bld_base, ctx->f32,
2040 ~0, ctx->tess_offchip_ring, base, addr, true);
2041
2042 }
2043
2044 static LLVMValueRef si_load_tess_level(struct ac_shader_abi *abi,
2045 unsigned varying_id)
2046 {
2047 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
2048 unsigned semantic_name;
2049
2050 switch (varying_id) {
2051 case VARYING_SLOT_TESS_LEVEL_INNER:
2052 semantic_name = TGSI_SEMANTIC_TESSINNER;
2053 break;
2054 case VARYING_SLOT_TESS_LEVEL_OUTER:
2055 semantic_name = TGSI_SEMANTIC_TESSOUTER;
2056 break;
2057 default:
2058 unreachable("unknown tess level");
2059 }
2060
2061 return load_tess_level(ctx, semantic_name);
2062
2063 }
2064
2065 static LLVMValueRef si_load_patch_vertices_in(struct ac_shader_abi *abi)
2066 {
2067 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
2068 if (ctx->type == PIPE_SHADER_TESS_CTRL)
2069 return si_unpack_param(ctx, ctx->param_tcs_out_lds_layout, 13, 6);
2070 else if (ctx->type == PIPE_SHADER_TESS_EVAL)
2071 return get_num_tcs_out_vertices(ctx);
2072 else
2073 unreachable("invalid shader stage for TGSI_SEMANTIC_VERTICESIN");
2074 }
2075
2076 void si_load_system_value(struct si_shader_context *ctx,
2077 unsigned index,
2078 const struct tgsi_full_declaration *decl)
2079 {
2080 LLVMValueRef value = 0;
2081
2082 assert(index < RADEON_LLVM_MAX_SYSTEM_VALUES);
2083
2084 switch (decl->Semantic.Name) {
2085 case TGSI_SEMANTIC_INSTANCEID:
2086 value = ctx->abi.instance_id;
2087 break;
2088
2089 case TGSI_SEMANTIC_VERTEXID:
2090 value = LLVMBuildAdd(ctx->ac.builder,
2091 ctx->abi.vertex_id,
2092 ctx->abi.base_vertex, "");
2093 break;
2094
2095 case TGSI_SEMANTIC_VERTEXID_NOBASE:
2096 /* Unused. Clarify the meaning in indexed vs. non-indexed
2097 * draws if this is ever used again. */
2098 assert(false);
2099 break;
2100
2101 case TGSI_SEMANTIC_BASEVERTEX:
2102 value = get_base_vertex(&ctx->abi);
2103 break;
2104
2105 case TGSI_SEMANTIC_BASEINSTANCE:
2106 value = ctx->abi.start_instance;
2107 break;
2108
2109 case TGSI_SEMANTIC_DRAWID:
2110 value = ctx->abi.draw_id;
2111 break;
2112
2113 case TGSI_SEMANTIC_INVOCATIONID:
2114 if (ctx->type == PIPE_SHADER_TESS_CTRL)
2115 value = unpack_llvm_param(ctx, ctx->abi.tcs_rel_ids, 8, 5);
2116 else if (ctx->type == PIPE_SHADER_GEOMETRY)
2117 value = ctx->abi.gs_invocation_id;
2118 else
2119 assert(!"INVOCATIONID not implemented");
2120 break;
2121
2122 case TGSI_SEMANTIC_POSITION:
2123 {
2124 LLVMValueRef pos[4] = {
2125 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_X_FLOAT),
2126 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_Y_FLOAT),
2127 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_Z_FLOAT),
2128 ac_build_fdiv(&ctx->ac, ctx->ac.f32_1,
2129 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_W_FLOAT)),
2130 };
2131 value = ac_build_gather_values(&ctx->ac, pos, 4);
2132 break;
2133 }
2134
2135 case TGSI_SEMANTIC_FACE:
2136 value = ctx->abi.front_face;
2137 break;
2138
2139 case TGSI_SEMANTIC_SAMPLEID:
2140 value = si_get_sample_id(ctx);
2141 break;
2142
2143 case TGSI_SEMANTIC_SAMPLEPOS: {
2144 LLVMValueRef pos[4] = {
2145 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_X_FLOAT),
2146 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_Y_FLOAT),
2147 LLVMConstReal(ctx->f32, 0),
2148 LLVMConstReal(ctx->f32, 0)
2149 };
2150 pos[0] = ac_build_fract(&ctx->ac, pos[0], 32);
2151 pos[1] = ac_build_fract(&ctx->ac, pos[1], 32);
2152 value = ac_build_gather_values(&ctx->ac, pos, 4);
2153 break;
2154 }
2155
2156 case TGSI_SEMANTIC_SAMPLEMASK:
2157 /* This can only occur with the OpenGL Core profile, which
2158 * doesn't support smoothing.
2159 */
2160 value = LLVMGetParam(ctx->main_fn, SI_PARAM_SAMPLE_COVERAGE);
2161 break;
2162
2163 case TGSI_SEMANTIC_TESSCOORD:
2164 value = si_load_tess_coord(&ctx->abi);
2165 break;
2166
2167 case TGSI_SEMANTIC_VERTICESIN:
2168 value = si_load_patch_vertices_in(&ctx->abi);
2169 break;
2170
2171 case TGSI_SEMANTIC_TESSINNER:
2172 case TGSI_SEMANTIC_TESSOUTER:
2173 value = load_tess_level(ctx, decl->Semantic.Name);
2174 break;
2175
2176 case TGSI_SEMANTIC_DEFAULT_TESSOUTER_SI:
2177 case TGSI_SEMANTIC_DEFAULT_TESSINNER_SI:
2178 {
2179 LLVMValueRef buf, slot, val[4];
2180 int i, offset;
2181
2182 slot = LLVMConstInt(ctx->i32, SI_HS_CONST_DEFAULT_TESS_LEVELS, 0);
2183 buf = LLVMGetParam(ctx->main_fn, ctx->param_rw_buffers);
2184 buf = ac_build_load_to_sgpr(&ctx->ac, buf, slot);
2185 offset = decl->Semantic.Name == TGSI_SEMANTIC_DEFAULT_TESSINNER_SI ? 4 : 0;
2186
2187 for (i = 0; i < 4; i++)
2188 val[i] = buffer_load_const(ctx, buf,
2189 LLVMConstInt(ctx->i32, (offset + i) * 4, 0));
2190 value = ac_build_gather_values(&ctx->ac, val, 4);
2191 break;
2192 }
2193
2194 case TGSI_SEMANTIC_PRIMID:
2195 value = get_primitive_id(ctx, 0);
2196 break;
2197
2198 case TGSI_SEMANTIC_GRID_SIZE:
2199 value = ctx->abi.num_work_groups;
2200 break;
2201
2202 case TGSI_SEMANTIC_BLOCK_SIZE:
2203 value = get_block_size(&ctx->abi);
2204 break;
2205
2206 case TGSI_SEMANTIC_BLOCK_ID:
2207 {
2208 LLVMValueRef values[3];
2209
2210 for (int i = 0; i < 3; i++) {
2211 values[i] = ctx->i32_0;
2212 if (ctx->abi.workgroup_ids[i]) {
2213 values[i] = ctx->abi.workgroup_ids[i];
2214 }
2215 }
2216 value = ac_build_gather_values(&ctx->ac, values, 3);
2217 break;
2218 }
2219
2220 case TGSI_SEMANTIC_THREAD_ID:
2221 value = ctx->abi.local_invocation_ids;
2222 break;
2223
2224 case TGSI_SEMANTIC_HELPER_INVOCATION:
2225 value = ac_build_intrinsic(&ctx->ac,
2226 "llvm.amdgcn.ps.live",
2227 ctx->i1, NULL, 0,
2228 AC_FUNC_ATTR_READNONE);
2229 value = LLVMBuildNot(ctx->ac.builder, value, "");
2230 value = LLVMBuildSExt(ctx->ac.builder, value, ctx->i32, "");
2231 break;
2232
2233 case TGSI_SEMANTIC_SUBGROUP_SIZE:
2234 value = LLVMConstInt(ctx->i32, 64, 0);
2235 break;
2236
2237 case TGSI_SEMANTIC_SUBGROUP_INVOCATION:
2238 value = ac_get_thread_id(&ctx->ac);
2239 break;
2240
2241 case TGSI_SEMANTIC_SUBGROUP_EQ_MASK:
2242 {
2243 LLVMValueRef id = ac_get_thread_id(&ctx->ac);
2244 id = LLVMBuildZExt(ctx->ac.builder, id, ctx->i64, "");
2245 value = LLVMBuildShl(ctx->ac.builder, LLVMConstInt(ctx->i64, 1, 0), id, "");
2246 value = LLVMBuildBitCast(ctx->ac.builder, value, ctx->v2i32, "");
2247 break;
2248 }
2249
2250 case TGSI_SEMANTIC_SUBGROUP_GE_MASK:
2251 case TGSI_SEMANTIC_SUBGROUP_GT_MASK:
2252 case TGSI_SEMANTIC_SUBGROUP_LE_MASK:
2253 case TGSI_SEMANTIC_SUBGROUP_LT_MASK:
2254 {
2255 LLVMValueRef id = ac_get_thread_id(&ctx->ac);
2256 if (decl->Semantic.Name == TGSI_SEMANTIC_SUBGROUP_GT_MASK ||
2257 decl->Semantic.Name == TGSI_SEMANTIC_SUBGROUP_LE_MASK) {
2258 /* All bits set except LSB */
2259 value = LLVMConstInt(ctx->i64, -2, 0);
2260 } else {
2261 /* All bits set */
2262 value = LLVMConstInt(ctx->i64, -1, 0);
2263 }
2264 id = LLVMBuildZExt(ctx->ac.builder, id, ctx->i64, "");
2265 value = LLVMBuildShl(ctx->ac.builder, value, id, "");
2266 if (decl->Semantic.Name == TGSI_SEMANTIC_SUBGROUP_LE_MASK ||
2267 decl->Semantic.Name == TGSI_SEMANTIC_SUBGROUP_LT_MASK)
2268 value = LLVMBuildNot(ctx->ac.builder, value, "");
2269 value = LLVMBuildBitCast(ctx->ac.builder, value, ctx->v2i32, "");
2270 break;
2271 }
2272
2273 case TGSI_SEMANTIC_CS_USER_DATA:
2274 value = LLVMGetParam(ctx->main_fn, ctx->param_cs_user_data);
2275 break;
2276
2277 default:
2278 assert(!"unknown system value");
2279 return;
2280 }
2281
2282 ctx->system_values[index] = value;
2283 }
2284
2285 void si_declare_compute_memory(struct si_shader_context *ctx)
2286 {
2287 struct si_shader_selector *sel = ctx->shader->selector;
2288 unsigned lds_size = sel->info.properties[TGSI_PROPERTY_CS_LOCAL_SIZE];
2289
2290 LLVMTypeRef i8p = LLVMPointerType(ctx->i8, AC_LOCAL_ADDR_SPACE);
2291 LLVMValueRef var;
2292
2293 assert(!ctx->ac.lds);
2294
2295 var = LLVMAddGlobalInAddressSpace(ctx->ac.module,
2296 LLVMArrayType(ctx->i8, lds_size),
2297 "compute_lds",
2298 AC_LOCAL_ADDR_SPACE);
2299 LLVMSetAlignment(var, 4);
2300
2301 ctx->ac.lds = LLVMBuildBitCast(ctx->ac.builder, var, i8p, "");
2302 }
2303
2304 void si_tgsi_declare_compute_memory(struct si_shader_context *ctx,
2305 const struct tgsi_full_declaration *decl)
2306 {
2307 assert(decl->Declaration.MemType == TGSI_MEMORY_TYPE_SHARED);
2308 assert(decl->Range.First == decl->Range.Last);
2309
2310 si_declare_compute_memory(ctx);
2311 }
2312
2313 static LLVMValueRef load_const_buffer_desc_fast_path(struct si_shader_context *ctx)
2314 {
2315 LLVMValueRef ptr =
2316 LLVMGetParam(ctx->main_fn, ctx->param_const_and_shader_buffers);
2317 struct si_shader_selector *sel = ctx->shader->selector;
2318
2319 /* Do the bounds checking with a descriptor, because
2320 * doing computation and manual bounds checking of 64-bit
2321 * addresses generates horrible VALU code with very high
2322 * VGPR usage and very low SIMD occupancy.
2323 */
2324 ptr = LLVMBuildPtrToInt(ctx->ac.builder, ptr, ctx->ac.intptr, "");
2325
2326 LLVMValueRef desc0, desc1;
2327 if (HAVE_32BIT_POINTERS) {
2328 desc0 = ptr;
2329 desc1 = LLVMConstInt(ctx->i32,
2330 S_008F04_BASE_ADDRESS_HI(ctx->screen->info.address32_hi), 0);
2331 } else {
2332 ptr = LLVMBuildBitCast(ctx->ac.builder, ptr, ctx->v2i32, "");
2333 desc0 = LLVMBuildExtractElement(ctx->ac.builder, ptr, ctx->i32_0, "");
2334 desc1 = LLVMBuildExtractElement(ctx->ac.builder, ptr, ctx->i32_1, "");
2335 /* Mask out all bits except BASE_ADDRESS_HI. */
2336 desc1 = LLVMBuildAnd(ctx->ac.builder, desc1,
2337 LLVMConstInt(ctx->i32, ~C_008F04_BASE_ADDRESS_HI, 0), "");
2338 }
2339
2340 LLVMValueRef desc_elems[] = {
2341 desc0,
2342 desc1,
2343 LLVMConstInt(ctx->i32, (sel->info.const_file_max[0] + 1) * 16, 0),
2344 LLVMConstInt(ctx->i32,
2345 S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2346 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2347 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2348 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2349 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2350 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32), 0)
2351 };
2352
2353 return ac_build_gather_values(&ctx->ac, desc_elems, 4);
2354 }
2355
2356 static LLVMValueRef load_const_buffer_desc(struct si_shader_context *ctx, int i)
2357 {
2358 LLVMValueRef list_ptr = LLVMGetParam(ctx->main_fn,
2359 ctx->param_const_and_shader_buffers);
2360
2361 return ac_build_load_to_sgpr(&ctx->ac, list_ptr,
2362 LLVMConstInt(ctx->i32, si_get_constbuf_slot(i), 0));
2363 }
2364
2365 static LLVMValueRef load_ubo(struct ac_shader_abi *abi, LLVMValueRef index)
2366 {
2367 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
2368 struct si_shader_selector *sel = ctx->shader->selector;
2369
2370 LLVMValueRef ptr = LLVMGetParam(ctx->main_fn, ctx->param_const_and_shader_buffers);
2371
2372 if (sel->info.const_buffers_declared == 1 &&
2373 sel->info.shader_buffers_declared == 0) {
2374 return load_const_buffer_desc_fast_path(ctx);
2375 }
2376
2377 index = si_llvm_bound_index(ctx, index, ctx->num_const_buffers);
2378 index = LLVMBuildAdd(ctx->ac.builder, index,
2379 LLVMConstInt(ctx->i32, SI_NUM_SHADER_BUFFERS, 0), "");
2380
2381 return ac_build_load_to_sgpr(&ctx->ac, ptr, index);
2382 }
2383
2384 static LLVMValueRef
2385 load_ssbo(struct ac_shader_abi *abi, LLVMValueRef index, bool write)
2386 {
2387 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
2388 LLVMValueRef rsrc_ptr = LLVMGetParam(ctx->main_fn,
2389 ctx->param_const_and_shader_buffers);
2390
2391 index = si_llvm_bound_index(ctx, index, ctx->num_shader_buffers);
2392 index = LLVMBuildSub(ctx->ac.builder,
2393 LLVMConstInt(ctx->i32, SI_NUM_SHADER_BUFFERS - 1, 0),
2394 index, "");
2395
2396 return ac_build_load_to_sgpr(&ctx->ac, rsrc_ptr, index);
2397 }
2398
2399 static LLVMValueRef fetch_constant(
2400 struct lp_build_tgsi_context *bld_base,
2401 const struct tgsi_full_src_register *reg,
2402 enum tgsi_opcode_type type,
2403 unsigned swizzle_in)
2404 {
2405 struct si_shader_context *ctx = si_shader_context(bld_base);
2406 struct si_shader_selector *sel = ctx->shader->selector;
2407 const struct tgsi_ind_register *ireg = &reg->Indirect;
2408 unsigned buf, idx;
2409 unsigned swizzle = swizzle_in & 0xffff;
2410
2411 LLVMValueRef addr, bufp;
2412
2413 if (swizzle_in == LP_CHAN_ALL) {
2414 unsigned chan;
2415 LLVMValueRef values[4];
2416 for (chan = 0; chan < TGSI_NUM_CHANNELS; ++chan)
2417 values[chan] = fetch_constant(bld_base, reg, type, chan);
2418
2419 return ac_build_gather_values(&ctx->ac, values, 4);
2420 }
2421
2422 /* Split 64-bit loads. */
2423 if (tgsi_type_is_64bit(type)) {
2424 LLVMValueRef lo, hi;
2425
2426 lo = fetch_constant(bld_base, reg, TGSI_TYPE_UNSIGNED, swizzle);
2427 hi = fetch_constant(bld_base, reg, TGSI_TYPE_UNSIGNED, (swizzle_in >> 16));
2428 return si_llvm_emit_fetch_64bit(bld_base, tgsi2llvmtype(bld_base, type),
2429 lo, hi);
2430 }
2431
2432 idx = reg->Register.Index * 4 + swizzle;
2433 if (reg->Register.Indirect) {
2434 addr = si_get_indirect_index(ctx, ireg, 16, idx * 4);
2435 } else {
2436 addr = LLVMConstInt(ctx->i32, idx * 4, 0);
2437 }
2438
2439 /* Fast path when user data SGPRs point to constant buffer 0 directly. */
2440 if (sel->info.const_buffers_declared == 1 &&
2441 sel->info.shader_buffers_declared == 0) {
2442 LLVMValueRef desc = load_const_buffer_desc_fast_path(ctx);
2443 LLVMValueRef result = buffer_load_const(ctx, desc, addr);
2444 return bitcast(bld_base, type, result);
2445 }
2446
2447 assert(reg->Register.Dimension);
2448 buf = reg->Dimension.Index;
2449
2450 if (reg->Dimension.Indirect) {
2451 LLVMValueRef ptr = LLVMGetParam(ctx->main_fn, ctx->param_const_and_shader_buffers);
2452 LLVMValueRef index;
2453 index = si_get_bounded_indirect_index(ctx, &reg->DimIndirect,
2454 reg->Dimension.Index,
2455 ctx->num_const_buffers);
2456 index = LLVMBuildAdd(ctx->ac.builder, index,
2457 LLVMConstInt(ctx->i32, SI_NUM_SHADER_BUFFERS, 0), "");
2458 bufp = ac_build_load_to_sgpr(&ctx->ac, ptr, index);
2459 } else
2460 bufp = load_const_buffer_desc(ctx, buf);
2461
2462 return bitcast(bld_base, type, buffer_load_const(ctx, bufp, addr));
2463 }
2464
2465 /* Initialize arguments for the shader export intrinsic */
2466 static void si_llvm_init_export_args(struct si_shader_context *ctx,
2467 LLVMValueRef *values,
2468 unsigned target,
2469 struct ac_export_args *args)
2470 {
2471 LLVMValueRef f32undef = LLVMGetUndef(ctx->ac.f32);
2472 unsigned spi_shader_col_format = V_028714_SPI_SHADER_32_ABGR;
2473 unsigned chan;
2474 bool is_int8, is_int10;
2475
2476 /* Default is 0xf. Adjusted below depending on the format. */
2477 args->enabled_channels = 0xf; /* writemask */
2478
2479 /* Specify whether the EXEC mask represents the valid mask */
2480 args->valid_mask = 0;
2481
2482 /* Specify whether this is the last export */
2483 args->done = 0;
2484
2485 /* Specify the target we are exporting */
2486 args->target = target;
2487
2488 if (ctx->type == PIPE_SHADER_FRAGMENT) {
2489 const struct si_shader_key *key = &ctx->shader->key;
2490 unsigned col_formats = key->part.ps.epilog.spi_shader_col_format;
2491 int cbuf = target - V_008DFC_SQ_EXP_MRT;
2492
2493 assert(cbuf >= 0 && cbuf < 8);
2494 spi_shader_col_format = (col_formats >> (cbuf * 4)) & 0xf;
2495 is_int8 = (key->part.ps.epilog.color_is_int8 >> cbuf) & 0x1;
2496 is_int10 = (key->part.ps.epilog.color_is_int10 >> cbuf) & 0x1;
2497 }
2498
2499 args->compr = false;
2500 args->out[0] = f32undef;
2501 args->out[1] = f32undef;
2502 args->out[2] = f32undef;
2503 args->out[3] = f32undef;
2504
2505 LLVMValueRef (*packf)(struct ac_llvm_context *ctx, LLVMValueRef args[2]) = NULL;
2506 LLVMValueRef (*packi)(struct ac_llvm_context *ctx, LLVMValueRef args[2],
2507 unsigned bits, bool hi) = NULL;
2508
2509 switch (spi_shader_col_format) {
2510 case V_028714_SPI_SHADER_ZERO:
2511 args->enabled_channels = 0; /* writemask */
2512 args->target = V_008DFC_SQ_EXP_NULL;
2513 break;
2514
2515 case V_028714_SPI_SHADER_32_R:
2516 args->enabled_channels = 1; /* writemask */
2517 args->out[0] = values[0];
2518 break;
2519
2520 case V_028714_SPI_SHADER_32_GR:
2521 args->enabled_channels = 0x3; /* writemask */
2522 args->out[0] = values[0];
2523 args->out[1] = values[1];
2524 break;
2525
2526 case V_028714_SPI_SHADER_32_AR:
2527 args->enabled_channels = 0x9; /* writemask */
2528 args->out[0] = values[0];
2529 args->out[3] = values[3];
2530 break;
2531
2532 case V_028714_SPI_SHADER_FP16_ABGR:
2533 packf = ac_build_cvt_pkrtz_f16;
2534 break;
2535
2536 case V_028714_SPI_SHADER_UNORM16_ABGR:
2537 packf = ac_build_cvt_pknorm_u16;
2538 break;
2539
2540 case V_028714_SPI_SHADER_SNORM16_ABGR:
2541 packf = ac_build_cvt_pknorm_i16;
2542 break;
2543
2544 case V_028714_SPI_SHADER_UINT16_ABGR:
2545 packi = ac_build_cvt_pk_u16;
2546 break;
2547
2548 case V_028714_SPI_SHADER_SINT16_ABGR:
2549 packi = ac_build_cvt_pk_i16;
2550 break;
2551
2552 case V_028714_SPI_SHADER_32_ABGR:
2553 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
2554 break;
2555 }
2556
2557 /* Pack f16 or norm_i16/u16. */
2558 if (packf) {
2559 for (chan = 0; chan < 2; chan++) {
2560 LLVMValueRef pack_args[2] = {
2561 values[2 * chan],
2562 values[2 * chan + 1]
2563 };
2564 LLVMValueRef packed;
2565
2566 packed = packf(&ctx->ac, pack_args);
2567 args->out[chan] = ac_to_float(&ctx->ac, packed);
2568 }
2569 args->compr = 1; /* COMPR flag */
2570 }
2571 /* Pack i16/u16. */
2572 if (packi) {
2573 for (chan = 0; chan < 2; chan++) {
2574 LLVMValueRef pack_args[2] = {
2575 ac_to_integer(&ctx->ac, values[2 * chan]),
2576 ac_to_integer(&ctx->ac, values[2 * chan + 1])
2577 };
2578 LLVMValueRef packed;
2579
2580 packed = packi(&ctx->ac, pack_args,
2581 is_int8 ? 8 : is_int10 ? 10 : 16,
2582 chan == 1);
2583 args->out[chan] = ac_to_float(&ctx->ac, packed);
2584 }
2585 args->compr = 1; /* COMPR flag */
2586 }
2587 }
2588
2589 static void si_alpha_test(struct lp_build_tgsi_context *bld_base,
2590 LLVMValueRef alpha)
2591 {
2592 struct si_shader_context *ctx = si_shader_context(bld_base);
2593
2594 if (ctx->shader->key.part.ps.epilog.alpha_func != PIPE_FUNC_NEVER) {
2595 static LLVMRealPredicate cond_map[PIPE_FUNC_ALWAYS + 1] = {
2596 [PIPE_FUNC_LESS] = LLVMRealOLT,
2597 [PIPE_FUNC_EQUAL] = LLVMRealOEQ,
2598 [PIPE_FUNC_LEQUAL] = LLVMRealOLE,
2599 [PIPE_FUNC_GREATER] = LLVMRealOGT,
2600 [PIPE_FUNC_NOTEQUAL] = LLVMRealONE,
2601 [PIPE_FUNC_GEQUAL] = LLVMRealOGE,
2602 };
2603 LLVMRealPredicate cond = cond_map[ctx->shader->key.part.ps.epilog.alpha_func];
2604 assert(cond);
2605
2606 LLVMValueRef alpha_ref = LLVMGetParam(ctx->main_fn,
2607 SI_PARAM_ALPHA_REF);
2608 LLVMValueRef alpha_pass =
2609 LLVMBuildFCmp(ctx->ac.builder, cond, alpha, alpha_ref, "");
2610 ac_build_kill_if_false(&ctx->ac, alpha_pass);
2611 } else {
2612 ac_build_kill_if_false(&ctx->ac, ctx->i1false);
2613 }
2614 }
2615
2616 static LLVMValueRef si_scale_alpha_by_sample_mask(struct lp_build_tgsi_context *bld_base,
2617 LLVMValueRef alpha,
2618 unsigned samplemask_param)
2619 {
2620 struct si_shader_context *ctx = si_shader_context(bld_base);
2621 LLVMValueRef coverage;
2622
2623 /* alpha = alpha * popcount(coverage) / SI_NUM_SMOOTH_AA_SAMPLES */
2624 coverage = LLVMGetParam(ctx->main_fn,
2625 samplemask_param);
2626 coverage = ac_to_integer(&ctx->ac, coverage);
2627
2628 coverage = ac_build_intrinsic(&ctx->ac, "llvm.ctpop.i32",
2629 ctx->i32,
2630 &coverage, 1, AC_FUNC_ATTR_READNONE);
2631
2632 coverage = LLVMBuildUIToFP(ctx->ac.builder, coverage,
2633 ctx->f32, "");
2634
2635 coverage = LLVMBuildFMul(ctx->ac.builder, coverage,
2636 LLVMConstReal(ctx->f32,
2637 1.0 / SI_NUM_SMOOTH_AA_SAMPLES), "");
2638
2639 return LLVMBuildFMul(ctx->ac.builder, alpha, coverage, "");
2640 }
2641
2642 static void si_llvm_emit_clipvertex(struct si_shader_context *ctx,
2643 struct ac_export_args *pos, LLVMValueRef *out_elts)
2644 {
2645 unsigned reg_index;
2646 unsigned chan;
2647 unsigned const_chan;
2648 LLVMValueRef base_elt;
2649 LLVMValueRef ptr = LLVMGetParam(ctx->main_fn, ctx->param_rw_buffers);
2650 LLVMValueRef constbuf_index = LLVMConstInt(ctx->i32,
2651 SI_VS_CONST_CLIP_PLANES, 0);
2652 LLVMValueRef const_resource = ac_build_load_to_sgpr(&ctx->ac, ptr, constbuf_index);
2653
2654 for (reg_index = 0; reg_index < 2; reg_index ++) {
2655 struct ac_export_args *args = &pos[2 + reg_index];
2656
2657 args->out[0] =
2658 args->out[1] =
2659 args->out[2] =
2660 args->out[3] = LLVMConstReal(ctx->f32, 0.0f);
2661
2662 /* Compute dot products of position and user clip plane vectors */
2663 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2664 for (const_chan = 0; const_chan < TGSI_NUM_CHANNELS; const_chan++) {
2665 LLVMValueRef addr =
2666 LLVMConstInt(ctx->i32, ((reg_index * 4 + chan) * 4 +
2667 const_chan) * 4, 0);
2668 base_elt = buffer_load_const(ctx, const_resource,
2669 addr);
2670 args->out[chan] = ac_build_fmad(&ctx->ac, base_elt,
2671 out_elts[const_chan], args->out[chan]);
2672 }
2673 }
2674
2675 args->enabled_channels = 0xf;
2676 args->valid_mask = 0;
2677 args->done = 0;
2678 args->target = V_008DFC_SQ_EXP_POS + 2 + reg_index;
2679 args->compr = 0;
2680 }
2681 }
2682
2683 static void si_dump_streamout(struct pipe_stream_output_info *so)
2684 {
2685 unsigned i;
2686
2687 if (so->num_outputs)
2688 fprintf(stderr, "STREAMOUT\n");
2689
2690 for (i = 0; i < so->num_outputs; i++) {
2691 unsigned mask = ((1 << so->output[i].num_components) - 1) <<
2692 so->output[i].start_component;
2693 fprintf(stderr, " %i: BUF%i[%i..%i] <- OUT[%i].%s%s%s%s\n",
2694 i, so->output[i].output_buffer,
2695 so->output[i].dst_offset, so->output[i].dst_offset + so->output[i].num_components - 1,
2696 so->output[i].register_index,
2697 mask & 1 ? "x" : "",
2698 mask & 2 ? "y" : "",
2699 mask & 4 ? "z" : "",
2700 mask & 8 ? "w" : "");
2701 }
2702 }
2703
2704 static void emit_streamout_output(struct si_shader_context *ctx,
2705 LLVMValueRef const *so_buffers,
2706 LLVMValueRef const *so_write_offsets,
2707 struct pipe_stream_output *stream_out,
2708 struct si_shader_output_values *shader_out)
2709 {
2710 unsigned buf_idx = stream_out->output_buffer;
2711 unsigned start = stream_out->start_component;
2712 unsigned num_comps = stream_out->num_components;
2713 LLVMValueRef out[4];
2714
2715 assert(num_comps && num_comps <= 4);
2716 if (!num_comps || num_comps > 4)
2717 return;
2718
2719 /* Load the output as int. */
2720 for (int j = 0; j < num_comps; j++) {
2721 assert(stream_out->stream == shader_out->vertex_stream[start + j]);
2722
2723 out[j] = ac_to_integer(&ctx->ac, shader_out->values[start + j]);
2724 }
2725
2726 /* Pack the output. */
2727 LLVMValueRef vdata = NULL;
2728
2729 switch (num_comps) {
2730 case 1: /* as i32 */
2731 vdata = out[0];
2732 break;
2733 case 2: /* as v2i32 */
2734 case 3: /* as v4i32 (aligned to 4) */
2735 out[3] = LLVMGetUndef(ctx->i32);
2736 /* fall through */
2737 case 4: /* as v4i32 */
2738 vdata = ac_build_gather_values(&ctx->ac, out, util_next_power_of_two(num_comps));
2739 break;
2740 }
2741
2742 ac_build_buffer_store_dword(&ctx->ac, so_buffers[buf_idx],
2743 vdata, num_comps,
2744 so_write_offsets[buf_idx],
2745 ctx->i32_0,
2746 stream_out->dst_offset * 4, 1, 1, true, false);
2747 }
2748
2749 /**
2750 * Write streamout data to buffers for vertex stream @p stream (different
2751 * vertex streams can occur for GS copy shaders).
2752 */
2753 static void si_llvm_emit_streamout(struct si_shader_context *ctx,
2754 struct si_shader_output_values *outputs,
2755 unsigned noutput, unsigned stream)
2756 {
2757 struct si_shader_selector *sel = ctx->shader->selector;
2758 struct pipe_stream_output_info *so = &sel->so;
2759 LLVMBuilderRef builder = ctx->ac.builder;
2760 int i;
2761 struct lp_build_if_state if_ctx;
2762
2763 /* Get bits [22:16], i.e. (so_param >> 16) & 127; */
2764 LLVMValueRef so_vtx_count =
2765 si_unpack_param(ctx, ctx->param_streamout_config, 16, 7);
2766
2767 LLVMValueRef tid = ac_get_thread_id(&ctx->ac);
2768
2769 /* can_emit = tid < so_vtx_count; */
2770 LLVMValueRef can_emit =
2771 LLVMBuildICmp(builder, LLVMIntULT, tid, so_vtx_count, "");
2772
2773 /* Emit the streamout code conditionally. This actually avoids
2774 * out-of-bounds buffer access. The hw tells us via the SGPR
2775 * (so_vtx_count) which threads are allowed to emit streamout data. */
2776 lp_build_if(&if_ctx, &ctx->gallivm, can_emit);
2777 {
2778 /* The buffer offset is computed as follows:
2779 * ByteOffset = streamout_offset[buffer_id]*4 +
2780 * (streamout_write_index + thread_id)*stride[buffer_id] +
2781 * attrib_offset
2782 */
2783
2784 LLVMValueRef so_write_index =
2785 LLVMGetParam(ctx->main_fn,
2786 ctx->param_streamout_write_index);
2787
2788 /* Compute (streamout_write_index + thread_id). */
2789 so_write_index = LLVMBuildAdd(builder, so_write_index, tid, "");
2790
2791 /* Load the descriptor and compute the write offset for each
2792 * enabled buffer. */
2793 LLVMValueRef so_write_offset[4] = {};
2794 LLVMValueRef so_buffers[4];
2795 LLVMValueRef buf_ptr = LLVMGetParam(ctx->main_fn,
2796 ctx->param_rw_buffers);
2797
2798 for (i = 0; i < 4; i++) {
2799 if (!so->stride[i])
2800 continue;
2801
2802 LLVMValueRef offset = LLVMConstInt(ctx->i32,
2803 SI_VS_STREAMOUT_BUF0 + i, 0);
2804
2805 so_buffers[i] = ac_build_load_to_sgpr(&ctx->ac, buf_ptr, offset);
2806
2807 LLVMValueRef so_offset = LLVMGetParam(ctx->main_fn,
2808 ctx->param_streamout_offset[i]);
2809 so_offset = LLVMBuildMul(builder, so_offset, LLVMConstInt(ctx->i32, 4, 0), "");
2810
2811 so_write_offset[i] = ac_build_imad(&ctx->ac, so_write_index,
2812 LLVMConstInt(ctx->i32, so->stride[i]*4, 0),
2813 so_offset);
2814 }
2815
2816 /* Write streamout data. */
2817 for (i = 0; i < so->num_outputs; i++) {
2818 unsigned reg = so->output[i].register_index;
2819
2820 if (reg >= noutput)
2821 continue;
2822
2823 if (stream != so->output[i].stream)
2824 continue;
2825
2826 emit_streamout_output(ctx, so_buffers, so_write_offset,
2827 &so->output[i], &outputs[reg]);
2828 }
2829 }
2830 lp_build_endif(&if_ctx);
2831 }
2832
2833 static void si_export_param(struct si_shader_context *ctx, unsigned index,
2834 LLVMValueRef *values)
2835 {
2836 struct ac_export_args args;
2837
2838 si_llvm_init_export_args(ctx, values,
2839 V_008DFC_SQ_EXP_PARAM + index, &args);
2840 ac_build_export(&ctx->ac, &args);
2841 }
2842
2843 static void si_build_param_exports(struct si_shader_context *ctx,
2844 struct si_shader_output_values *outputs,
2845 unsigned noutput)
2846 {
2847 struct si_shader *shader = ctx->shader;
2848 unsigned param_count = 0;
2849
2850 for (unsigned i = 0; i < noutput; i++) {
2851 unsigned semantic_name = outputs[i].semantic_name;
2852 unsigned semantic_index = outputs[i].semantic_index;
2853
2854 if (outputs[i].vertex_stream[0] != 0 &&
2855 outputs[i].vertex_stream[1] != 0 &&
2856 outputs[i].vertex_stream[2] != 0 &&
2857 outputs[i].vertex_stream[3] != 0)
2858 continue;
2859
2860 switch (semantic_name) {
2861 case TGSI_SEMANTIC_LAYER:
2862 case TGSI_SEMANTIC_VIEWPORT_INDEX:
2863 case TGSI_SEMANTIC_CLIPDIST:
2864 case TGSI_SEMANTIC_COLOR:
2865 case TGSI_SEMANTIC_BCOLOR:
2866 case TGSI_SEMANTIC_PRIMID:
2867 case TGSI_SEMANTIC_FOG:
2868 case TGSI_SEMANTIC_TEXCOORD:
2869 case TGSI_SEMANTIC_GENERIC:
2870 break;
2871 default:
2872 continue;
2873 }
2874
2875 if ((semantic_name != TGSI_SEMANTIC_GENERIC ||
2876 semantic_index < SI_MAX_IO_GENERIC) &&
2877 shader->key.opt.kill_outputs &
2878 (1ull << si_shader_io_get_unique_index(semantic_name,
2879 semantic_index, true)))
2880 continue;
2881
2882 si_export_param(ctx, param_count, outputs[i].values);
2883
2884 assert(i < ARRAY_SIZE(shader->info.vs_output_param_offset));
2885 shader->info.vs_output_param_offset[i] = param_count++;
2886 }
2887
2888 shader->info.nr_param_exports = param_count;
2889 }
2890
2891 /* Generate export instructions for hardware VS shader stage */
2892 static void si_llvm_export_vs(struct si_shader_context *ctx,
2893 struct si_shader_output_values *outputs,
2894 unsigned noutput)
2895 {
2896 struct si_shader *shader = ctx->shader;
2897 struct ac_export_args pos_args[4] = {};
2898 LLVMValueRef psize_value = NULL, edgeflag_value = NULL, layer_value = NULL, viewport_index_value = NULL;
2899 unsigned pos_idx;
2900 int i;
2901
2902 /* Build position exports. */
2903 for (i = 0; i < noutput; i++) {
2904 switch (outputs[i].semantic_name) {
2905 case TGSI_SEMANTIC_POSITION:
2906 si_llvm_init_export_args(ctx, outputs[i].values,
2907 V_008DFC_SQ_EXP_POS, &pos_args[0]);
2908 break;
2909 case TGSI_SEMANTIC_PSIZE:
2910 psize_value = outputs[i].values[0];
2911 break;
2912 case TGSI_SEMANTIC_LAYER:
2913 layer_value = outputs[i].values[0];
2914 break;
2915 case TGSI_SEMANTIC_VIEWPORT_INDEX:
2916 viewport_index_value = outputs[i].values[0];
2917 break;
2918 case TGSI_SEMANTIC_EDGEFLAG:
2919 edgeflag_value = outputs[i].values[0];
2920 break;
2921 case TGSI_SEMANTIC_CLIPDIST:
2922 if (!shader->key.opt.clip_disable) {
2923 unsigned index = 2 + outputs[i].semantic_index;
2924 si_llvm_init_export_args(ctx, outputs[i].values,
2925 V_008DFC_SQ_EXP_POS + index,
2926 &pos_args[index]);
2927 }
2928 break;
2929 case TGSI_SEMANTIC_CLIPVERTEX:
2930 if (!shader->key.opt.clip_disable) {
2931 si_llvm_emit_clipvertex(ctx, pos_args,
2932 outputs[i].values);
2933 }
2934 break;
2935 }
2936 }
2937
2938 /* We need to add the position output manually if it's missing. */
2939 if (!pos_args[0].out[0]) {
2940 pos_args[0].enabled_channels = 0xf; /* writemask */
2941 pos_args[0].valid_mask = 0; /* EXEC mask */
2942 pos_args[0].done = 0; /* last export? */
2943 pos_args[0].target = V_008DFC_SQ_EXP_POS;
2944 pos_args[0].compr = 0; /* COMPR flag */
2945 pos_args[0].out[0] = ctx->ac.f32_0; /* X */
2946 pos_args[0].out[1] = ctx->ac.f32_0; /* Y */
2947 pos_args[0].out[2] = ctx->ac.f32_0; /* Z */
2948 pos_args[0].out[3] = ctx->ac.f32_1; /* W */
2949 }
2950
2951 /* Write the misc vector (point size, edgeflag, layer, viewport). */
2952 if (shader->selector->info.writes_psize ||
2953 shader->selector->info.writes_edgeflag ||
2954 shader->selector->info.writes_viewport_index ||
2955 shader->selector->info.writes_layer) {
2956 pos_args[1].enabled_channels = shader->selector->info.writes_psize |
2957 (shader->selector->info.writes_edgeflag << 1) |
2958 (shader->selector->info.writes_layer << 2);
2959
2960 pos_args[1].valid_mask = 0; /* EXEC mask */
2961 pos_args[1].done = 0; /* last export? */
2962 pos_args[1].target = V_008DFC_SQ_EXP_POS + 1;
2963 pos_args[1].compr = 0; /* COMPR flag */
2964 pos_args[1].out[0] = ctx->ac.f32_0; /* X */
2965 pos_args[1].out[1] = ctx->ac.f32_0; /* Y */
2966 pos_args[1].out[2] = ctx->ac.f32_0; /* Z */
2967 pos_args[1].out[3] = ctx->ac.f32_0; /* W */
2968
2969 if (shader->selector->info.writes_psize)
2970 pos_args[1].out[0] = psize_value;
2971
2972 if (shader->selector->info.writes_edgeflag) {
2973 /* The output is a float, but the hw expects an integer
2974 * with the first bit containing the edge flag. */
2975 edgeflag_value = LLVMBuildFPToUI(ctx->ac.builder,
2976 edgeflag_value,
2977 ctx->i32, "");
2978 edgeflag_value = ac_build_umin(&ctx->ac,
2979 edgeflag_value,
2980 ctx->i32_1);
2981
2982 /* The LLVM intrinsic expects a float. */
2983 pos_args[1].out[1] = ac_to_float(&ctx->ac, edgeflag_value);
2984 }
2985
2986 if (ctx->screen->info.chip_class >= GFX9) {
2987 /* GFX9 has the layer in out.z[10:0] and the viewport
2988 * index in out.z[19:16].
2989 */
2990 if (shader->selector->info.writes_layer)
2991 pos_args[1].out[2] = layer_value;
2992
2993 if (shader->selector->info.writes_viewport_index) {
2994 LLVMValueRef v = viewport_index_value;
2995
2996 v = ac_to_integer(&ctx->ac, v);
2997 v = LLVMBuildShl(ctx->ac.builder, v,
2998 LLVMConstInt(ctx->i32, 16, 0), "");
2999 v = LLVMBuildOr(ctx->ac.builder, v,
3000 ac_to_integer(&ctx->ac, pos_args[1].out[2]), "");
3001 pos_args[1].out[2] = ac_to_float(&ctx->ac, v);
3002 pos_args[1].enabled_channels |= 1 << 2;
3003 }
3004 } else {
3005 if (shader->selector->info.writes_layer)
3006 pos_args[1].out[2] = layer_value;
3007
3008 if (shader->selector->info.writes_viewport_index) {
3009 pos_args[1].out[3] = viewport_index_value;
3010 pos_args[1].enabled_channels |= 1 << 3;
3011 }
3012 }
3013 }
3014
3015 for (i = 0; i < 4; i++)
3016 if (pos_args[i].out[0])
3017 shader->info.nr_pos_exports++;
3018
3019 pos_idx = 0;
3020 for (i = 0; i < 4; i++) {
3021 if (!pos_args[i].out[0])
3022 continue;
3023
3024 /* Specify the target we are exporting */
3025 pos_args[i].target = V_008DFC_SQ_EXP_POS + pos_idx++;
3026
3027 if (pos_idx == shader->info.nr_pos_exports)
3028 /* Specify that this is the last export */
3029 pos_args[i].done = 1;
3030
3031 ac_build_export(&ctx->ac, &pos_args[i]);
3032 }
3033
3034 /* Build parameter exports. */
3035 si_build_param_exports(ctx, outputs, noutput);
3036 }
3037
3038 /**
3039 * Forward all outputs from the vertex shader to the TES. This is only used
3040 * for the fixed function TCS.
3041 */
3042 static void si_copy_tcs_inputs(struct lp_build_tgsi_context *bld_base)
3043 {
3044 struct si_shader_context *ctx = si_shader_context(bld_base);
3045 LLVMValueRef invocation_id, buffer, buffer_offset;
3046 LLVMValueRef lds_vertex_stride, lds_base;
3047 uint64_t inputs;
3048
3049 invocation_id = unpack_llvm_param(ctx, ctx->abi.tcs_rel_ids, 8, 5);
3050 buffer = get_tess_ring_descriptor(ctx, TESS_OFFCHIP_RING_TCS);
3051 buffer_offset = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
3052
3053 lds_vertex_stride = get_tcs_in_vertex_dw_stride(ctx);
3054 lds_base = get_tcs_in_current_patch_offset(ctx);
3055 lds_base = ac_build_imad(&ctx->ac, invocation_id, lds_vertex_stride,
3056 lds_base);
3057
3058 inputs = ctx->shader->key.mono.u.ff_tcs_inputs_to_copy;
3059 while (inputs) {
3060 unsigned i = u_bit_scan64(&inputs);
3061
3062 LLVMValueRef lds_ptr = LLVMBuildAdd(ctx->ac.builder, lds_base,
3063 LLVMConstInt(ctx->i32, 4 * i, 0),
3064 "");
3065
3066 LLVMValueRef buffer_addr = get_tcs_tes_buffer_address(ctx,
3067 get_rel_patch_id(ctx),
3068 invocation_id,
3069 LLVMConstInt(ctx->i32, i, 0));
3070
3071 LLVMValueRef value = lds_load(bld_base, ctx->ac.i32, ~0,
3072 lds_ptr);
3073
3074 ac_build_buffer_store_dword(&ctx->ac, buffer, value, 4, buffer_addr,
3075 buffer_offset, 0, 1, 0, true, false);
3076 }
3077 }
3078
3079 static void si_write_tess_factors(struct lp_build_tgsi_context *bld_base,
3080 LLVMValueRef rel_patch_id,
3081 LLVMValueRef invocation_id,
3082 LLVMValueRef tcs_out_current_patch_data_offset,
3083 LLVMValueRef invoc0_tf_outer[4],
3084 LLVMValueRef invoc0_tf_inner[2])
3085 {
3086 struct si_shader_context *ctx = si_shader_context(bld_base);
3087 struct si_shader *shader = ctx->shader;
3088 unsigned tess_inner_index, tess_outer_index;
3089 LLVMValueRef lds_base, lds_inner, lds_outer, byteoffset, buffer;
3090 LLVMValueRef out[6], vec0, vec1, tf_base, inner[4], outer[4];
3091 unsigned stride, outer_comps, inner_comps, i, offset;
3092 struct lp_build_if_state if_ctx, inner_if_ctx;
3093
3094 /* Add a barrier before loading tess factors from LDS. */
3095 if (!shader->key.part.tcs.epilog.invoc0_tess_factors_are_def)
3096 si_llvm_emit_barrier(NULL, bld_base, NULL);
3097
3098 /* Do this only for invocation 0, because the tess levels are per-patch,
3099 * not per-vertex.
3100 *
3101 * This can't jump, because invocation 0 executes this. It should
3102 * at least mask out the loads and stores for other invocations.
3103 */
3104 lp_build_if(&if_ctx, &ctx->gallivm,
3105 LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
3106 invocation_id, ctx->i32_0, ""));
3107
3108 /* Determine the layout of one tess factor element in the buffer. */
3109 switch (shader->key.part.tcs.epilog.prim_mode) {
3110 case PIPE_PRIM_LINES:
3111 stride = 2; /* 2 dwords, 1 vec2 store */
3112 outer_comps = 2;
3113 inner_comps = 0;
3114 break;
3115 case PIPE_PRIM_TRIANGLES:
3116 stride = 4; /* 4 dwords, 1 vec4 store */
3117 outer_comps = 3;
3118 inner_comps = 1;
3119 break;
3120 case PIPE_PRIM_QUADS:
3121 stride = 6; /* 6 dwords, 2 stores (vec4 + vec2) */
3122 outer_comps = 4;
3123 inner_comps = 2;
3124 break;
3125 default:
3126 assert(0);
3127 return;
3128 }
3129
3130 for (i = 0; i < 4; i++) {
3131 inner[i] = LLVMGetUndef(ctx->i32);
3132 outer[i] = LLVMGetUndef(ctx->i32);
3133 }
3134
3135 if (shader->key.part.tcs.epilog.invoc0_tess_factors_are_def) {
3136 /* Tess factors are in VGPRs. */
3137 for (i = 0; i < outer_comps; i++)
3138 outer[i] = out[i] = invoc0_tf_outer[i];
3139 for (i = 0; i < inner_comps; i++)
3140 inner[i] = out[outer_comps+i] = invoc0_tf_inner[i];
3141 } else {
3142 /* Load tess_inner and tess_outer from LDS.
3143 * Any invocation can write them, so we can't get them from a temporary.
3144 */
3145 tess_inner_index = si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSINNER, 0);
3146 tess_outer_index = si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSOUTER, 0);
3147
3148 lds_base = tcs_out_current_patch_data_offset;
3149 lds_inner = LLVMBuildAdd(ctx->ac.builder, lds_base,
3150 LLVMConstInt(ctx->i32,
3151 tess_inner_index * 4, 0), "");
3152 lds_outer = LLVMBuildAdd(ctx->ac.builder, lds_base,
3153 LLVMConstInt(ctx->i32,
3154 tess_outer_index * 4, 0), "");
3155
3156 for (i = 0; i < outer_comps; i++) {
3157 outer[i] = out[i] =
3158 lds_load(bld_base, ctx->ac.i32, i, lds_outer);
3159 }
3160 for (i = 0; i < inner_comps; i++) {
3161 inner[i] = out[outer_comps+i] =
3162 lds_load(bld_base, ctx->ac.i32, i, lds_inner);
3163 }
3164 }
3165
3166 if (shader->key.part.tcs.epilog.prim_mode == PIPE_PRIM_LINES) {
3167 /* For isolines, the hardware expects tess factors in the
3168 * reverse order from what GLSL / TGSI specify.
3169 */
3170 LLVMValueRef tmp = out[0];
3171 out[0] = out[1];
3172 out[1] = tmp;
3173 }
3174
3175 /* Convert the outputs to vectors for stores. */
3176 vec0 = ac_build_gather_values(&ctx->ac, out, MIN2(stride, 4));
3177 vec1 = NULL;
3178
3179 if (stride > 4)
3180 vec1 = ac_build_gather_values(&ctx->ac, out+4, stride - 4);
3181
3182 /* Get the buffer. */
3183 buffer = get_tess_ring_descriptor(ctx, TCS_FACTOR_RING);
3184
3185 /* Get the offset. */
3186 tf_base = LLVMGetParam(ctx->main_fn,
3187 ctx->param_tcs_factor_offset);
3188 byteoffset = LLVMBuildMul(ctx->ac.builder, rel_patch_id,
3189 LLVMConstInt(ctx->i32, 4 * stride, 0), "");
3190
3191 lp_build_if(&inner_if_ctx, &ctx->gallivm,
3192 LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
3193 rel_patch_id, ctx->i32_0, ""));
3194
3195 /* Store the dynamic HS control word. */
3196 offset = 0;
3197 if (ctx->screen->info.chip_class <= VI) {
3198 ac_build_buffer_store_dword(&ctx->ac, buffer,
3199 LLVMConstInt(ctx->i32, 0x80000000, 0),
3200 1, ctx->i32_0, tf_base,
3201 offset, 1, 0, true, false);
3202 offset += 4;
3203 }
3204
3205 lp_build_endif(&inner_if_ctx);
3206
3207 /* Store the tessellation factors. */
3208 ac_build_buffer_store_dword(&ctx->ac, buffer, vec0,
3209 MIN2(stride, 4), byteoffset, tf_base,
3210 offset, 1, 0, true, false);
3211 offset += 16;
3212 if (vec1)
3213 ac_build_buffer_store_dword(&ctx->ac, buffer, vec1,
3214 stride - 4, byteoffset, tf_base,
3215 offset, 1, 0, true, false);
3216
3217 /* Store the tess factors into the offchip buffer if TES reads them. */
3218 if (shader->key.part.tcs.epilog.tes_reads_tess_factors) {
3219 LLVMValueRef buf, base, inner_vec, outer_vec, tf_outer_offset;
3220 LLVMValueRef tf_inner_offset;
3221 unsigned param_outer, param_inner;
3222
3223 buf = get_tess_ring_descriptor(ctx, TESS_OFFCHIP_RING_TCS);
3224 base = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
3225
3226 param_outer = si_shader_io_get_unique_index_patch(
3227 TGSI_SEMANTIC_TESSOUTER, 0);
3228 tf_outer_offset = get_tcs_tes_buffer_address(ctx, rel_patch_id, NULL,
3229 LLVMConstInt(ctx->i32, param_outer, 0));
3230
3231 outer_vec = ac_build_gather_values(&ctx->ac, outer,
3232 util_next_power_of_two(outer_comps));
3233
3234 ac_build_buffer_store_dword(&ctx->ac, buf, outer_vec,
3235 outer_comps, tf_outer_offset,
3236 base, 0, 1, 0, true, false);
3237 if (inner_comps) {
3238 param_inner = si_shader_io_get_unique_index_patch(
3239 TGSI_SEMANTIC_TESSINNER, 0);
3240 tf_inner_offset = get_tcs_tes_buffer_address(ctx, rel_patch_id, NULL,
3241 LLVMConstInt(ctx->i32, param_inner, 0));
3242
3243 inner_vec = inner_comps == 1 ? inner[0] :
3244 ac_build_gather_values(&ctx->ac, inner, inner_comps);
3245 ac_build_buffer_store_dword(&ctx->ac, buf, inner_vec,
3246 inner_comps, tf_inner_offset,
3247 base, 0, 1, 0, true, false);
3248 }
3249 }
3250
3251 lp_build_endif(&if_ctx);
3252 }
3253
3254 static LLVMValueRef
3255 si_insert_input_ret(struct si_shader_context *ctx, LLVMValueRef ret,
3256 unsigned param, unsigned return_index)
3257 {
3258 return LLVMBuildInsertValue(ctx->ac.builder, ret,
3259 LLVMGetParam(ctx->main_fn, param),
3260 return_index, "");
3261 }
3262
3263 static LLVMValueRef
3264 si_insert_input_ret_float(struct si_shader_context *ctx, LLVMValueRef ret,
3265 unsigned param, unsigned return_index)
3266 {
3267 LLVMBuilderRef builder = ctx->ac.builder;
3268 LLVMValueRef p = LLVMGetParam(ctx->main_fn, param);
3269
3270 return LLVMBuildInsertValue(builder, ret,
3271 ac_to_float(&ctx->ac, p),
3272 return_index, "");
3273 }
3274
3275 static LLVMValueRef
3276 si_insert_input_ptr(struct si_shader_context *ctx, LLVMValueRef ret,
3277 unsigned param, unsigned return_index)
3278 {
3279 LLVMBuilderRef builder = ctx->ac.builder;
3280 LLVMValueRef ptr, lo, hi;
3281
3282 if (HAVE_32BIT_POINTERS) {
3283 ptr = LLVMGetParam(ctx->main_fn, param);
3284 ptr = LLVMBuildPtrToInt(builder, ptr, ctx->i32, "");
3285 return LLVMBuildInsertValue(builder, ret, ptr, return_index, "");
3286 }
3287
3288 ptr = LLVMGetParam(ctx->main_fn, param);
3289 ptr = LLVMBuildPtrToInt(builder, ptr, ctx->i64, "");
3290 ptr = LLVMBuildBitCast(builder, ptr, ctx->v2i32, "");
3291 lo = LLVMBuildExtractElement(builder, ptr, ctx->i32_0, "");
3292 hi = LLVMBuildExtractElement(builder, ptr, ctx->i32_1, "");
3293 ret = LLVMBuildInsertValue(builder, ret, lo, return_index, "");
3294 return LLVMBuildInsertValue(builder, ret, hi, return_index + 1, "");
3295 }
3296
3297 /* This only writes the tessellation factor levels. */
3298 static void si_llvm_emit_tcs_epilogue(struct ac_shader_abi *abi,
3299 unsigned max_outputs,
3300 LLVMValueRef *addrs)
3301 {
3302 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
3303 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
3304 LLVMBuilderRef builder = ctx->ac.builder;
3305 LLVMValueRef rel_patch_id, invocation_id, tf_lds_offset;
3306
3307 si_copy_tcs_inputs(bld_base);
3308
3309 rel_patch_id = get_rel_patch_id(ctx);
3310 invocation_id = unpack_llvm_param(ctx, ctx->abi.tcs_rel_ids, 8, 5);
3311 tf_lds_offset = get_tcs_out_current_patch_data_offset(ctx);
3312
3313 if (ctx->screen->info.chip_class >= GFX9) {
3314 LLVMBasicBlockRef blocks[2] = {
3315 LLVMGetInsertBlock(builder),
3316 ctx->merged_wrap_if_state.entry_block
3317 };
3318 LLVMValueRef values[2];
3319
3320 lp_build_endif(&ctx->merged_wrap_if_state);
3321
3322 values[0] = rel_patch_id;
3323 values[1] = LLVMGetUndef(ctx->i32);
3324 rel_patch_id = ac_build_phi(&ctx->ac, ctx->i32, 2, values, blocks);
3325
3326 values[0] = tf_lds_offset;
3327 values[1] = LLVMGetUndef(ctx->i32);
3328 tf_lds_offset = ac_build_phi(&ctx->ac, ctx->i32, 2, values, blocks);
3329
3330 values[0] = invocation_id;
3331 values[1] = ctx->i32_1; /* cause the epilog to skip threads */
3332 invocation_id = ac_build_phi(&ctx->ac, ctx->i32, 2, values, blocks);
3333 }
3334
3335 /* Return epilog parameters from this function. */
3336 LLVMValueRef ret = ctx->return_value;
3337 unsigned vgpr;
3338
3339 if (ctx->screen->info.chip_class >= GFX9) {
3340 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_layout,
3341 8 + GFX9_SGPR_TCS_OFFCHIP_LAYOUT);
3342 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_out_lds_layout,
3343 8 + GFX9_SGPR_TCS_OUT_LAYOUT);
3344 /* Tess offchip and tess factor offsets are at the beginning. */
3345 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_offset, 2);
3346 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_factor_offset, 4);
3347 vgpr = 8 + GFX9_SGPR_TCS_OUT_LAYOUT + 1;
3348 } else {
3349 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_layout,
3350 GFX6_SGPR_TCS_OFFCHIP_LAYOUT);
3351 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_out_lds_layout,
3352 GFX6_SGPR_TCS_OUT_LAYOUT);
3353 /* Tess offchip and tess factor offsets are after user SGPRs. */
3354 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_offset,
3355 GFX6_TCS_NUM_USER_SGPR);
3356 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_factor_offset,
3357 GFX6_TCS_NUM_USER_SGPR + 1);
3358 vgpr = GFX6_TCS_NUM_USER_SGPR + 2;
3359 }
3360
3361 /* VGPRs */
3362 rel_patch_id = ac_to_float(&ctx->ac, rel_patch_id);
3363 invocation_id = ac_to_float(&ctx->ac, invocation_id);
3364 tf_lds_offset = ac_to_float(&ctx->ac, tf_lds_offset);
3365
3366 /* Leave a hole corresponding to the two input VGPRs. This ensures that
3367 * the invocation_id output does not alias the tcs_rel_ids input,
3368 * which saves a V_MOV on gfx9.
3369 */
3370 vgpr += 2;
3371
3372 ret = LLVMBuildInsertValue(builder, ret, rel_patch_id, vgpr++, "");
3373 ret = LLVMBuildInsertValue(builder, ret, invocation_id, vgpr++, "");
3374
3375 if (ctx->shader->selector->tcs_info.tessfactors_are_def_in_all_invocs) {
3376 vgpr++; /* skip the tess factor LDS offset */
3377 for (unsigned i = 0; i < 6; i++) {
3378 LLVMValueRef value =
3379 LLVMBuildLoad(builder, ctx->invoc0_tess_factors[i], "");
3380 value = ac_to_float(&ctx->ac, value);
3381 ret = LLVMBuildInsertValue(builder, ret, value, vgpr++, "");
3382 }
3383 } else {
3384 ret = LLVMBuildInsertValue(builder, ret, tf_lds_offset, vgpr++, "");
3385 }
3386 ctx->return_value = ret;
3387 }
3388
3389 /* Pass TCS inputs from LS to TCS on GFX9. */
3390 static void si_set_ls_return_value_for_tcs(struct si_shader_context *ctx)
3391 {
3392 LLVMValueRef ret = ctx->return_value;
3393
3394 ret = si_insert_input_ptr(ctx, ret, 0, 0);
3395 if (HAVE_32BIT_POINTERS)
3396 ret = si_insert_input_ptr(ctx, ret, 1, 1);
3397 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_offset, 2);
3398 ret = si_insert_input_ret(ctx, ret, ctx->param_merged_wave_info, 3);
3399 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_factor_offset, 4);
3400 ret = si_insert_input_ret(ctx, ret, ctx->param_merged_scratch_offset, 5);
3401
3402 ret = si_insert_input_ptr(ctx, ret, ctx->param_rw_buffers,
3403 8 + SI_SGPR_RW_BUFFERS);
3404 ret = si_insert_input_ptr(ctx, ret,
3405 ctx->param_bindless_samplers_and_images,
3406 8 + SI_SGPR_BINDLESS_SAMPLERS_AND_IMAGES);
3407
3408 ret = si_insert_input_ret(ctx, ret, ctx->param_vs_state_bits,
3409 8 + SI_SGPR_VS_STATE_BITS);
3410
3411 #if !HAVE_32BIT_POINTERS
3412 ret = si_insert_input_ptr(ctx, ret, ctx->param_vs_state_bits + 4,
3413 8 + GFX9_SGPR_2ND_SAMPLERS_AND_IMAGES);
3414 #endif
3415
3416 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_layout,
3417 8 + GFX9_SGPR_TCS_OFFCHIP_LAYOUT);
3418 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_out_lds_offsets,
3419 8 + GFX9_SGPR_TCS_OUT_OFFSETS);
3420 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_out_lds_layout,
3421 8 + GFX9_SGPR_TCS_OUT_LAYOUT);
3422
3423 unsigned vgpr = 8 + GFX9_TCS_NUM_USER_SGPR;
3424 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
3425 ac_to_float(&ctx->ac, ctx->abi.tcs_patch_id),
3426 vgpr++, "");
3427 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
3428 ac_to_float(&ctx->ac, ctx->abi.tcs_rel_ids),
3429 vgpr++, "");
3430 ctx->return_value = ret;
3431 }
3432
3433 /* Pass GS inputs from ES to GS on GFX9. */
3434 static void si_set_es_return_value_for_gs(struct si_shader_context *ctx)
3435 {
3436 LLVMValueRef ret = ctx->return_value;
3437
3438 ret = si_insert_input_ptr(ctx, ret, 0, 0);
3439 if (HAVE_32BIT_POINTERS)
3440 ret = si_insert_input_ptr(ctx, ret, 1, 1);
3441 ret = si_insert_input_ret(ctx, ret, ctx->param_gs2vs_offset, 2);
3442 ret = si_insert_input_ret(ctx, ret, ctx->param_merged_wave_info, 3);
3443 ret = si_insert_input_ret(ctx, ret, ctx->param_merged_scratch_offset, 5);
3444
3445 ret = si_insert_input_ptr(ctx, ret, ctx->param_rw_buffers,
3446 8 + SI_SGPR_RW_BUFFERS);
3447 ret = si_insert_input_ptr(ctx, ret,
3448 ctx->param_bindless_samplers_and_images,
3449 8 + SI_SGPR_BINDLESS_SAMPLERS_AND_IMAGES);
3450
3451 #if !HAVE_32BIT_POINTERS
3452 ret = si_insert_input_ptr(ctx, ret, ctx->param_vs_state_bits + 4,
3453 8 + GFX9_SGPR_2ND_SAMPLERS_AND_IMAGES);
3454 #endif
3455
3456 unsigned vgpr;
3457 if (ctx->type == PIPE_SHADER_VERTEX)
3458 vgpr = 8 + GFX9_VSGS_NUM_USER_SGPR;
3459 else
3460 vgpr = 8 + GFX9_TESGS_NUM_USER_SGPR;
3461
3462 for (unsigned i = 0; i < 5; i++) {
3463 unsigned param = ctx->param_gs_vtx01_offset + i;
3464 ret = si_insert_input_ret_float(ctx, ret, param, vgpr++);
3465 }
3466 ctx->return_value = ret;
3467 }
3468
3469 static void si_llvm_emit_ls_epilogue(struct ac_shader_abi *abi,
3470 unsigned max_outputs,
3471 LLVMValueRef *addrs)
3472 {
3473 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
3474 struct si_shader *shader = ctx->shader;
3475 struct tgsi_shader_info *info = &shader->selector->info;
3476 unsigned i, chan;
3477 LLVMValueRef vertex_id = LLVMGetParam(ctx->main_fn,
3478 ctx->param_rel_auto_id);
3479 LLVMValueRef vertex_dw_stride = get_tcs_in_vertex_dw_stride(ctx);
3480 LLVMValueRef base_dw_addr = LLVMBuildMul(ctx->ac.builder, vertex_id,
3481 vertex_dw_stride, "");
3482
3483 /* Write outputs to LDS. The next shader (TCS aka HS) will read
3484 * its inputs from it. */
3485 for (i = 0; i < info->num_outputs; i++) {
3486 unsigned name = info->output_semantic_name[i];
3487 unsigned index = info->output_semantic_index[i];
3488
3489 /* The ARB_shader_viewport_layer_array spec contains the
3490 * following issue:
3491 *
3492 * 2) What happens if gl_ViewportIndex or gl_Layer is
3493 * written in the vertex shader and a geometry shader is
3494 * present?
3495 *
3496 * RESOLVED: The value written by the last vertex processing
3497 * stage is used. If the last vertex processing stage
3498 * (vertex, tessellation evaluation or geometry) does not
3499 * statically assign to gl_ViewportIndex or gl_Layer, index
3500 * or layer zero is assumed.
3501 *
3502 * So writes to those outputs in VS-as-LS are simply ignored.
3503 */
3504 if (name == TGSI_SEMANTIC_LAYER ||
3505 name == TGSI_SEMANTIC_VIEWPORT_INDEX)
3506 continue;
3507
3508 int param = si_shader_io_get_unique_index(name, index, false);
3509 LLVMValueRef dw_addr = LLVMBuildAdd(ctx->ac.builder, base_dw_addr,
3510 LLVMConstInt(ctx->i32, param * 4, 0), "");
3511
3512 for (chan = 0; chan < 4; chan++) {
3513 if (!(info->output_usagemask[i] & (1 << chan)))
3514 continue;
3515
3516 lds_store(ctx, chan, dw_addr,
3517 LLVMBuildLoad(ctx->ac.builder, addrs[4 * i + chan], ""));
3518 }
3519 }
3520
3521 if (ctx->screen->info.chip_class >= GFX9)
3522 si_set_ls_return_value_for_tcs(ctx);
3523 }
3524
3525 static void si_llvm_emit_es_epilogue(struct ac_shader_abi *abi,
3526 unsigned max_outputs,
3527 LLVMValueRef *addrs)
3528 {
3529 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
3530 struct si_shader *es = ctx->shader;
3531 struct tgsi_shader_info *info = &es->selector->info;
3532 LLVMValueRef soffset = LLVMGetParam(ctx->main_fn,
3533 ctx->param_es2gs_offset);
3534 LLVMValueRef lds_base = NULL;
3535 unsigned chan;
3536 int i;
3537
3538 if (ctx->screen->info.chip_class >= GFX9 && info->num_outputs) {
3539 unsigned itemsize_dw = es->selector->esgs_itemsize / 4;
3540 LLVMValueRef vertex_idx = ac_get_thread_id(&ctx->ac);
3541 LLVMValueRef wave_idx = si_unpack_param(ctx, ctx->param_merged_wave_info, 24, 4);
3542 vertex_idx = LLVMBuildOr(ctx->ac.builder, vertex_idx,
3543 LLVMBuildMul(ctx->ac.builder, wave_idx,
3544 LLVMConstInt(ctx->i32, 64, false), ""), "");
3545 lds_base = LLVMBuildMul(ctx->ac.builder, vertex_idx,
3546 LLVMConstInt(ctx->i32, itemsize_dw, 0), "");
3547 }
3548
3549 for (i = 0; i < info->num_outputs; i++) {
3550 int param;
3551
3552 if (info->output_semantic_name[i] == TGSI_SEMANTIC_VIEWPORT_INDEX ||
3553 info->output_semantic_name[i] == TGSI_SEMANTIC_LAYER)
3554 continue;
3555
3556 param = si_shader_io_get_unique_index(info->output_semantic_name[i],
3557 info->output_semantic_index[i], false);
3558
3559 for (chan = 0; chan < 4; chan++) {
3560 if (!(info->output_usagemask[i] & (1 << chan)))
3561 continue;
3562
3563 LLVMValueRef out_val = LLVMBuildLoad(ctx->ac.builder, addrs[4 * i + chan], "");
3564 out_val = ac_to_integer(&ctx->ac, out_val);
3565
3566 /* GFX9 has the ESGS ring in LDS. */
3567 if (ctx->screen->info.chip_class >= GFX9) {
3568 lds_store(ctx, param * 4 + chan, lds_base, out_val);
3569 continue;
3570 }
3571
3572 ac_build_buffer_store_dword(&ctx->ac,
3573 ctx->esgs_ring,
3574 out_val, 1, NULL, soffset,
3575 (4 * param + chan) * 4,
3576 1, 1, true, true);
3577 }
3578 }
3579
3580 if (ctx->screen->info.chip_class >= GFX9)
3581 si_set_es_return_value_for_gs(ctx);
3582 }
3583
3584 static LLVMValueRef si_get_gs_wave_id(struct si_shader_context *ctx)
3585 {
3586 if (ctx->screen->info.chip_class >= GFX9)
3587 return si_unpack_param(ctx, ctx->param_merged_wave_info, 16, 8);
3588 else
3589 return LLVMGetParam(ctx->main_fn, ctx->param_gs_wave_id);
3590 }
3591
3592 static void emit_gs_epilogue(struct si_shader_context *ctx)
3593 {
3594 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_NOP | AC_SENDMSG_GS_DONE,
3595 si_get_gs_wave_id(ctx));
3596
3597 if (ctx->screen->info.chip_class >= GFX9)
3598 lp_build_endif(&ctx->merged_wrap_if_state);
3599 }
3600
3601 static void si_llvm_emit_gs_epilogue(struct ac_shader_abi *abi,
3602 unsigned max_outputs,
3603 LLVMValueRef *addrs)
3604 {
3605 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
3606 struct tgsi_shader_info UNUSED *info = &ctx->shader->selector->info;
3607
3608 assert(info->num_outputs <= max_outputs);
3609
3610 emit_gs_epilogue(ctx);
3611 }
3612
3613 static void si_tgsi_emit_gs_epilogue(struct lp_build_tgsi_context *bld_base)
3614 {
3615 struct si_shader_context *ctx = si_shader_context(bld_base);
3616 emit_gs_epilogue(ctx);
3617 }
3618
3619 static void si_llvm_emit_vs_epilogue(struct ac_shader_abi *abi,
3620 unsigned max_outputs,
3621 LLVMValueRef *addrs)
3622 {
3623 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
3624 struct tgsi_shader_info *info = &ctx->shader->selector->info;
3625 struct si_shader_output_values *outputs = NULL;
3626 int i,j;
3627
3628 assert(!ctx->shader->is_gs_copy_shader);
3629 assert(info->num_outputs <= max_outputs);
3630
3631 outputs = MALLOC((info->num_outputs + 1) * sizeof(outputs[0]));
3632
3633 /* Vertex color clamping.
3634 *
3635 * This uses a state constant loaded in a user data SGPR and
3636 * an IF statement is added that clamps all colors if the constant
3637 * is true.
3638 */
3639 struct lp_build_if_state if_ctx;
3640 LLVMValueRef cond = NULL;
3641 LLVMValueRef addr, val;
3642
3643 for (i = 0; i < info->num_outputs; i++) {
3644 if (info->output_semantic_name[i] != TGSI_SEMANTIC_COLOR &&
3645 info->output_semantic_name[i] != TGSI_SEMANTIC_BCOLOR)
3646 continue;
3647
3648 /* We've found a color. */
3649 if (!cond) {
3650 /* The state is in the first bit of the user SGPR. */
3651 cond = LLVMGetParam(ctx->main_fn,
3652 ctx->param_vs_state_bits);
3653 cond = LLVMBuildTrunc(ctx->ac.builder, cond,
3654 ctx->i1, "");
3655 lp_build_if(&if_ctx, &ctx->gallivm, cond);
3656 }
3657
3658 for (j = 0; j < 4; j++) {
3659 addr = addrs[4 * i + j];
3660 val = LLVMBuildLoad(ctx->ac.builder, addr, "");
3661 val = ac_build_clamp(&ctx->ac, val);
3662 LLVMBuildStore(ctx->ac.builder, val, addr);
3663 }
3664 }
3665
3666 if (cond)
3667 lp_build_endif(&if_ctx);
3668
3669 for (i = 0; i < info->num_outputs; i++) {
3670 outputs[i].semantic_name = info->output_semantic_name[i];
3671 outputs[i].semantic_index = info->output_semantic_index[i];
3672
3673 for (j = 0; j < 4; j++) {
3674 outputs[i].values[j] =
3675 LLVMBuildLoad(ctx->ac.builder,
3676 addrs[4 * i + j],
3677 "");
3678 outputs[i].vertex_stream[j] =
3679 (info->output_streams[i] >> (2 * j)) & 3;
3680 }
3681 }
3682
3683 if (ctx->shader->selector->so.num_outputs)
3684 si_llvm_emit_streamout(ctx, outputs, i, 0);
3685
3686 /* Export PrimitiveID. */
3687 if (ctx->shader->key.mono.u.vs_export_prim_id) {
3688 outputs[i].semantic_name = TGSI_SEMANTIC_PRIMID;
3689 outputs[i].semantic_index = 0;
3690 outputs[i].values[0] = ac_to_float(&ctx->ac, get_primitive_id(ctx, 0));
3691 for (j = 1; j < 4; j++)
3692 outputs[i].values[j] = LLVMConstReal(ctx->f32, 0);
3693
3694 memset(outputs[i].vertex_stream, 0,
3695 sizeof(outputs[i].vertex_stream));
3696 i++;
3697 }
3698
3699 si_llvm_export_vs(ctx, outputs, i);
3700 FREE(outputs);
3701 }
3702
3703 static void si_tgsi_emit_epilogue(struct lp_build_tgsi_context *bld_base)
3704 {
3705 struct si_shader_context *ctx = si_shader_context(bld_base);
3706
3707 ctx->abi.emit_outputs(&ctx->abi, RADEON_LLVM_MAX_OUTPUTS,
3708 &ctx->outputs[0][0]);
3709 }
3710
3711 struct si_ps_exports {
3712 unsigned num;
3713 struct ac_export_args args[10];
3714 };
3715
3716 static void si_export_mrt_z(struct lp_build_tgsi_context *bld_base,
3717 LLVMValueRef depth, LLVMValueRef stencil,
3718 LLVMValueRef samplemask, struct si_ps_exports *exp)
3719 {
3720 struct si_shader_context *ctx = si_shader_context(bld_base);
3721 struct ac_export_args args;
3722
3723 ac_export_mrt_z(&ctx->ac, depth, stencil, samplemask, &args);
3724
3725 memcpy(&exp->args[exp->num++], &args, sizeof(args));
3726 }
3727
3728 static void si_export_mrt_color(struct lp_build_tgsi_context *bld_base,
3729 LLVMValueRef *color, unsigned index,
3730 unsigned samplemask_param,
3731 bool is_last, struct si_ps_exports *exp)
3732 {
3733 struct si_shader_context *ctx = si_shader_context(bld_base);
3734 int i;
3735
3736 /* Clamp color */
3737 if (ctx->shader->key.part.ps.epilog.clamp_color)
3738 for (i = 0; i < 4; i++)
3739 color[i] = ac_build_clamp(&ctx->ac, color[i]);
3740
3741 /* Alpha to one */
3742 if (ctx->shader->key.part.ps.epilog.alpha_to_one)
3743 color[3] = ctx->ac.f32_1;
3744
3745 /* Alpha test */
3746 if (index == 0 &&
3747 ctx->shader->key.part.ps.epilog.alpha_func != PIPE_FUNC_ALWAYS)
3748 si_alpha_test(bld_base, color[3]);
3749
3750 /* Line & polygon smoothing */
3751 if (ctx->shader->key.part.ps.epilog.poly_line_smoothing)
3752 color[3] = si_scale_alpha_by_sample_mask(bld_base, color[3],
3753 samplemask_param);
3754
3755 /* If last_cbuf > 0, FS_COLOR0_WRITES_ALL_CBUFS is true. */
3756 if (ctx->shader->key.part.ps.epilog.last_cbuf > 0) {
3757 struct ac_export_args args[8];
3758 int c, last = -1;
3759
3760 /* Get the export arguments, also find out what the last one is. */
3761 for (c = 0; c <= ctx->shader->key.part.ps.epilog.last_cbuf; c++) {
3762 si_llvm_init_export_args(ctx, color,
3763 V_008DFC_SQ_EXP_MRT + c, &args[c]);
3764 if (args[c].enabled_channels)
3765 last = c;
3766 }
3767
3768 /* Emit all exports. */
3769 for (c = 0; c <= ctx->shader->key.part.ps.epilog.last_cbuf; c++) {
3770 if (is_last && last == c) {
3771 args[c].valid_mask = 1; /* whether the EXEC mask is valid */
3772 args[c].done = 1; /* DONE bit */
3773 } else if (!args[c].enabled_channels)
3774 continue; /* unnecessary NULL export */
3775
3776 memcpy(&exp->args[exp->num++], &args[c], sizeof(args[c]));
3777 }
3778 } else {
3779 struct ac_export_args args;
3780
3781 /* Export */
3782 si_llvm_init_export_args(ctx, color, V_008DFC_SQ_EXP_MRT + index,
3783 &args);
3784 if (is_last) {
3785 args.valid_mask = 1; /* whether the EXEC mask is valid */
3786 args.done = 1; /* DONE bit */
3787 } else if (!args.enabled_channels)
3788 return; /* unnecessary NULL export */
3789
3790 memcpy(&exp->args[exp->num++], &args, sizeof(args));
3791 }
3792 }
3793
3794 static void si_emit_ps_exports(struct si_shader_context *ctx,
3795 struct si_ps_exports *exp)
3796 {
3797 for (unsigned i = 0; i < exp->num; i++)
3798 ac_build_export(&ctx->ac, &exp->args[i]);
3799 }
3800
3801 /**
3802 * Return PS outputs in this order:
3803 *
3804 * v[0:3] = color0.xyzw
3805 * v[4:7] = color1.xyzw
3806 * ...
3807 * vN+0 = Depth
3808 * vN+1 = Stencil
3809 * vN+2 = SampleMask
3810 * vN+3 = SampleMaskIn (used for OpenGL smoothing)
3811 *
3812 * The alpha-ref SGPR is returned via its original location.
3813 */
3814 static void si_llvm_return_fs_outputs(struct ac_shader_abi *abi,
3815 unsigned max_outputs,
3816 LLVMValueRef *addrs)
3817 {
3818 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
3819 struct si_shader *shader = ctx->shader;
3820 struct tgsi_shader_info *info = &shader->selector->info;
3821 LLVMBuilderRef builder = ctx->ac.builder;
3822 unsigned i, j, first_vgpr, vgpr;
3823
3824 LLVMValueRef color[8][4] = {};
3825 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
3826 LLVMValueRef ret;
3827
3828 if (ctx->postponed_kill)
3829 ac_build_kill_if_false(&ctx->ac, LLVMBuildLoad(builder, ctx->postponed_kill, ""));
3830
3831 /* Read the output values. */
3832 for (i = 0; i < info->num_outputs; i++) {
3833 unsigned semantic_name = info->output_semantic_name[i];
3834 unsigned semantic_index = info->output_semantic_index[i];
3835
3836 switch (semantic_name) {
3837 case TGSI_SEMANTIC_COLOR:
3838 assert(semantic_index < 8);
3839 for (j = 0; j < 4; j++) {
3840 LLVMValueRef ptr = addrs[4 * i + j];
3841 LLVMValueRef result = LLVMBuildLoad(builder, ptr, "");
3842 color[semantic_index][j] = result;
3843 }
3844 break;
3845 case TGSI_SEMANTIC_POSITION:
3846 depth = LLVMBuildLoad(builder,
3847 addrs[4 * i + 2], "");
3848 break;
3849 case TGSI_SEMANTIC_STENCIL:
3850 stencil = LLVMBuildLoad(builder,
3851 addrs[4 * i + 1], "");
3852 break;
3853 case TGSI_SEMANTIC_SAMPLEMASK:
3854 samplemask = LLVMBuildLoad(builder,
3855 addrs[4 * i + 0], "");
3856 break;
3857 default:
3858 fprintf(stderr, "Warning: SI unhandled fs output type:%d\n",
3859 semantic_name);
3860 }
3861 }
3862
3863 /* Fill the return structure. */
3864 ret = ctx->return_value;
3865
3866 /* Set SGPRs. */
3867 ret = LLVMBuildInsertValue(builder, ret,
3868 ac_to_integer(&ctx->ac,
3869 LLVMGetParam(ctx->main_fn,
3870 SI_PARAM_ALPHA_REF)),
3871 SI_SGPR_ALPHA_REF, "");
3872
3873 /* Set VGPRs */
3874 first_vgpr = vgpr = SI_SGPR_ALPHA_REF + 1;
3875 for (i = 0; i < ARRAY_SIZE(color); i++) {
3876 if (!color[i][0])
3877 continue;
3878
3879 for (j = 0; j < 4; j++)
3880 ret = LLVMBuildInsertValue(builder, ret, color[i][j], vgpr++, "");
3881 }
3882 if (depth)
3883 ret = LLVMBuildInsertValue(builder, ret, depth, vgpr++, "");
3884 if (stencil)
3885 ret = LLVMBuildInsertValue(builder, ret, stencil, vgpr++, "");
3886 if (samplemask)
3887 ret = LLVMBuildInsertValue(builder, ret, samplemask, vgpr++, "");
3888
3889 /* Add the input sample mask for smoothing at the end. */
3890 if (vgpr < first_vgpr + PS_EPILOG_SAMPLEMASK_MIN_LOC)
3891 vgpr = first_vgpr + PS_EPILOG_SAMPLEMASK_MIN_LOC;
3892 ret = LLVMBuildInsertValue(builder, ret,
3893 LLVMGetParam(ctx->main_fn,
3894 SI_PARAM_SAMPLE_COVERAGE), vgpr++, "");
3895
3896 ctx->return_value = ret;
3897 }
3898
3899 static void membar_emit(
3900 const struct lp_build_tgsi_action *action,
3901 struct lp_build_tgsi_context *bld_base,
3902 struct lp_build_emit_data *emit_data)
3903 {
3904 struct si_shader_context *ctx = si_shader_context(bld_base);
3905 LLVMValueRef src0 = lp_build_emit_fetch(bld_base, emit_data->inst, 0, 0);
3906 unsigned flags = LLVMConstIntGetZExtValue(src0);
3907 unsigned waitcnt = NOOP_WAITCNT;
3908
3909 if (flags & TGSI_MEMBAR_THREAD_GROUP)
3910 waitcnt &= VM_CNT & LGKM_CNT;
3911
3912 if (flags & (TGSI_MEMBAR_ATOMIC_BUFFER |
3913 TGSI_MEMBAR_SHADER_BUFFER |
3914 TGSI_MEMBAR_SHADER_IMAGE))
3915 waitcnt &= VM_CNT;
3916
3917 if (flags & TGSI_MEMBAR_SHARED)
3918 waitcnt &= LGKM_CNT;
3919
3920 if (waitcnt != NOOP_WAITCNT)
3921 ac_build_waitcnt(&ctx->ac, waitcnt);
3922 }
3923
3924 static void clock_emit(
3925 const struct lp_build_tgsi_action *action,
3926 struct lp_build_tgsi_context *bld_base,
3927 struct lp_build_emit_data *emit_data)
3928 {
3929 struct si_shader_context *ctx = si_shader_context(bld_base);
3930 LLVMValueRef tmp = ac_build_shader_clock(&ctx->ac);
3931
3932 emit_data->output[0] =
3933 LLVMBuildExtractElement(ctx->ac.builder, tmp, ctx->i32_0, "");
3934 emit_data->output[1] =
3935 LLVMBuildExtractElement(ctx->ac.builder, tmp, ctx->i32_1, "");
3936 }
3937
3938 static void si_llvm_emit_ddxy(
3939 const struct lp_build_tgsi_action *action,
3940 struct lp_build_tgsi_context *bld_base,
3941 struct lp_build_emit_data *emit_data)
3942 {
3943 struct si_shader_context *ctx = si_shader_context(bld_base);
3944 unsigned opcode = emit_data->info->opcode;
3945 LLVMValueRef val;
3946 int idx;
3947 unsigned mask;
3948
3949 if (opcode == TGSI_OPCODE_DDX_FINE)
3950 mask = AC_TID_MASK_LEFT;
3951 else if (opcode == TGSI_OPCODE_DDY_FINE)
3952 mask = AC_TID_MASK_TOP;
3953 else
3954 mask = AC_TID_MASK_TOP_LEFT;
3955
3956 /* for DDX we want to next X pixel, DDY next Y pixel. */
3957 idx = (opcode == TGSI_OPCODE_DDX || opcode == TGSI_OPCODE_DDX_FINE) ? 1 : 2;
3958
3959 val = ac_to_integer(&ctx->ac, emit_data->args[0]);
3960 val = ac_build_ddxy(&ctx->ac, mask, idx, val);
3961 emit_data->output[emit_data->chan] = val;
3962 }
3963
3964 /*
3965 * this takes an I,J coordinate pair,
3966 * and works out the X and Y derivatives.
3967 * it returns DDX(I), DDX(J), DDY(I), DDY(J).
3968 */
3969 static LLVMValueRef si_llvm_emit_ddxy_interp(
3970 struct lp_build_tgsi_context *bld_base,
3971 LLVMValueRef interp_ij)
3972 {
3973 struct si_shader_context *ctx = si_shader_context(bld_base);
3974 LLVMValueRef result[4], a;
3975 unsigned i;
3976
3977 for (i = 0; i < 2; i++) {
3978 a = LLVMBuildExtractElement(ctx->ac.builder, interp_ij,
3979 LLVMConstInt(ctx->i32, i, 0), "");
3980 result[i] = ac_build_ddxy(&ctx->ac, AC_TID_MASK_TOP_LEFT, 1,
3981 ac_to_integer(&ctx->ac, a)); /* DDX */
3982 result[2+i] = ac_build_ddxy(&ctx->ac, AC_TID_MASK_TOP_LEFT, 2,
3983 ac_to_integer(&ctx->ac, a)); /* DDY */
3984 }
3985
3986 return ac_build_gather_values(&ctx->ac, result, 4);
3987 }
3988
3989 static void build_interp_intrinsic(const struct lp_build_tgsi_action *action,
3990 struct lp_build_tgsi_context *bld_base,
3991 struct lp_build_emit_data *emit_data)
3992 {
3993 struct si_shader_context *ctx = si_shader_context(bld_base);
3994 struct si_shader *shader = ctx->shader;
3995 const struct tgsi_shader_info *info = &shader->selector->info;
3996 LLVMValueRef interp_param;
3997 const struct tgsi_full_instruction *inst = emit_data->inst;
3998 const struct tgsi_full_src_register *input = &inst->Src[0];
3999 int input_base, input_array_size;
4000 int chan;
4001 int i;
4002 LLVMValueRef prim_mask = ctx->abi.prim_mask;
4003 LLVMValueRef array_idx, offset_x = NULL, offset_y = NULL;
4004 int interp_param_idx;
4005 unsigned interp;
4006 unsigned location;
4007
4008 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET) {
4009 /* offset is in second src, first two channels */
4010 offset_x = lp_build_emit_fetch(bld_base, emit_data->inst, 1,
4011 TGSI_CHAN_X);
4012 offset_y = lp_build_emit_fetch(bld_base, emit_data->inst, 1,
4013 TGSI_CHAN_Y);
4014 } else if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
4015 LLVMValueRef sample_position;
4016 LLVMValueRef sample_id;
4017 LLVMValueRef halfval = LLVMConstReal(ctx->f32, 0.5f);
4018
4019 /* fetch sample ID, then fetch its sample position,
4020 * and place into first two channels.
4021 */
4022 sample_id = lp_build_emit_fetch(bld_base,
4023 emit_data->inst, 1, TGSI_CHAN_X);
4024 sample_id = ac_to_integer(&ctx->ac, sample_id);
4025
4026 /* Section 8.13.2 (Interpolation Functions) of the OpenGL Shading
4027 * Language 4.50 spec says about interpolateAtSample:
4028 *
4029 * "Returns the value of the input interpolant variable at
4030 * the location of sample number sample. If multisample
4031 * buffers are not available, the input variable will be
4032 * evaluated at the center of the pixel. If sample sample
4033 * does not exist, the position used to interpolate the
4034 * input variable is undefined."
4035 *
4036 * This means that sample_id values outside of the valid are
4037 * in fact valid input, and the usual mechanism for loading the
4038 * sample position doesn't work.
4039 */
4040 if (ctx->shader->key.mono.u.ps.interpolate_at_sample_force_center) {
4041 LLVMValueRef center[4] = {
4042 LLVMConstReal(ctx->f32, 0.5),
4043 LLVMConstReal(ctx->f32, 0.5),
4044 ctx->ac.f32_0,
4045 ctx->ac.f32_0,
4046 };
4047
4048 sample_position = ac_build_gather_values(&ctx->ac, center, 4);
4049 } else {
4050 sample_position = load_sample_position(&ctx->abi, sample_id);
4051 }
4052
4053 offset_x = LLVMBuildExtractElement(ctx->ac.builder, sample_position,
4054 ctx->i32_0, "");
4055
4056 offset_x = LLVMBuildFSub(ctx->ac.builder, offset_x, halfval, "");
4057 offset_y = LLVMBuildExtractElement(ctx->ac.builder, sample_position,
4058 ctx->i32_1, "");
4059 offset_y = LLVMBuildFSub(ctx->ac.builder, offset_y, halfval, "");
4060 }
4061
4062 assert(input->Register.File == TGSI_FILE_INPUT);
4063
4064 if (input->Register.Indirect) {
4065 unsigned array_id = input->Indirect.ArrayID;
4066
4067 if (array_id) {
4068 input_base = info->input_array_first[array_id];
4069 input_array_size = info->input_array_last[array_id] - input_base + 1;
4070 } else {
4071 input_base = inst->Src[0].Register.Index;
4072 input_array_size = info->num_inputs - input_base;
4073 }
4074
4075 array_idx = si_get_indirect_index(ctx, &input->Indirect,
4076 1, input->Register.Index - input_base);
4077 } else {
4078 input_base = inst->Src[0].Register.Index;
4079 input_array_size = 1;
4080 array_idx = ctx->i32_0;
4081 }
4082
4083 interp = shader->selector->info.input_interpolate[input_base];
4084
4085 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
4086 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE)
4087 location = TGSI_INTERPOLATE_LOC_CENTER;
4088 else
4089 location = TGSI_INTERPOLATE_LOC_CENTROID;
4090
4091 interp_param_idx = lookup_interp_param_index(interp, location);
4092 if (interp_param_idx == -1)
4093 return;
4094 else if (interp_param_idx)
4095 interp_param = LLVMGetParam(ctx->main_fn, interp_param_idx);
4096 else
4097 interp_param = NULL;
4098
4099 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
4100 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
4101 LLVMValueRef ij_out[2];
4102 LLVMValueRef ddxy_out = si_llvm_emit_ddxy_interp(bld_base, interp_param);
4103
4104 /*
4105 * take the I then J parameters, and the DDX/Y for it, and
4106 * calculate the IJ inputs for the interpolator.
4107 * temp1 = ddx * offset/sample.x + I;
4108 * interp_param.I = ddy * offset/sample.y + temp1;
4109 * temp1 = ddx * offset/sample.x + J;
4110 * interp_param.J = ddy * offset/sample.y + temp1;
4111 */
4112 for (i = 0; i < 2; i++) {
4113 LLVMValueRef ix_ll = LLVMConstInt(ctx->i32, i, 0);
4114 LLVMValueRef iy_ll = LLVMConstInt(ctx->i32, i + 2, 0);
4115 LLVMValueRef ddx_el = LLVMBuildExtractElement(ctx->ac.builder,
4116 ddxy_out, ix_ll, "");
4117 LLVMValueRef ddy_el = LLVMBuildExtractElement(ctx->ac.builder,
4118 ddxy_out, iy_ll, "");
4119 LLVMValueRef interp_el = LLVMBuildExtractElement(ctx->ac.builder,
4120 interp_param, ix_ll, "");
4121 LLVMValueRef temp;
4122
4123 interp_el = ac_to_float(&ctx->ac, interp_el);
4124
4125 temp = ac_build_fmad(&ctx->ac, ddx_el, offset_x, interp_el);
4126 ij_out[i] = ac_build_fmad(&ctx->ac, ddy_el, offset_y, temp);
4127 }
4128 interp_param = ac_build_gather_values(&ctx->ac, ij_out, 2);
4129 }
4130
4131 if (interp_param)
4132 interp_param = ac_to_float(&ctx->ac, interp_param);
4133
4134 for (chan = 0; chan < 4; chan++) {
4135 LLVMValueRef gather = LLVMGetUndef(LLVMVectorType(ctx->f32, input_array_size));
4136 unsigned schan = tgsi_util_get_full_src_register_swizzle(&inst->Src[0], chan);
4137
4138 for (unsigned idx = 0; idx < input_array_size; ++idx) {
4139 LLVMValueRef v, i = NULL, j = NULL;
4140
4141 if (interp_param) {
4142 i = LLVMBuildExtractElement(
4143 ctx->ac.builder, interp_param, ctx->i32_0, "");
4144 j = LLVMBuildExtractElement(
4145 ctx->ac.builder, interp_param, ctx->i32_1, "");
4146 }
4147 v = si_build_fs_interp(ctx, input_base + idx, schan,
4148 prim_mask, i, j);
4149
4150 gather = LLVMBuildInsertElement(ctx->ac.builder,
4151 gather, v, LLVMConstInt(ctx->i32, idx, false), "");
4152 }
4153
4154 emit_data->output[chan] = LLVMBuildExtractElement(
4155 ctx->ac.builder, gather, array_idx, "");
4156 }
4157 }
4158
4159 static void vote_all_emit(
4160 const struct lp_build_tgsi_action *action,
4161 struct lp_build_tgsi_context *bld_base,
4162 struct lp_build_emit_data *emit_data)
4163 {
4164 struct si_shader_context *ctx = si_shader_context(bld_base);
4165
4166 LLVMValueRef tmp = ac_build_vote_all(&ctx->ac, emit_data->args[0]);
4167 emit_data->output[emit_data->chan] =
4168 LLVMBuildSExt(ctx->ac.builder, tmp, ctx->i32, "");
4169 }
4170
4171 static void vote_any_emit(
4172 const struct lp_build_tgsi_action *action,
4173 struct lp_build_tgsi_context *bld_base,
4174 struct lp_build_emit_data *emit_data)
4175 {
4176 struct si_shader_context *ctx = si_shader_context(bld_base);
4177
4178 LLVMValueRef tmp = ac_build_vote_any(&ctx->ac, emit_data->args[0]);
4179 emit_data->output[emit_data->chan] =
4180 LLVMBuildSExt(ctx->ac.builder, tmp, ctx->i32, "");
4181 }
4182
4183 static void vote_eq_emit(
4184 const struct lp_build_tgsi_action *action,
4185 struct lp_build_tgsi_context *bld_base,
4186 struct lp_build_emit_data *emit_data)
4187 {
4188 struct si_shader_context *ctx = si_shader_context(bld_base);
4189
4190 LLVMValueRef tmp = ac_build_vote_eq(&ctx->ac, emit_data->args[0]);
4191 emit_data->output[emit_data->chan] =
4192 LLVMBuildSExt(ctx->ac.builder, tmp, ctx->i32, "");
4193 }
4194
4195 static void ballot_emit(
4196 const struct lp_build_tgsi_action *action,
4197 struct lp_build_tgsi_context *bld_base,
4198 struct lp_build_emit_data *emit_data)
4199 {
4200 struct si_shader_context *ctx = si_shader_context(bld_base);
4201 LLVMBuilderRef builder = ctx->ac.builder;
4202 LLVMValueRef tmp;
4203
4204 tmp = lp_build_emit_fetch(bld_base, emit_data->inst, 0, TGSI_CHAN_X);
4205 tmp = ac_build_ballot(&ctx->ac, tmp);
4206 tmp = LLVMBuildBitCast(builder, tmp, ctx->v2i32, "");
4207
4208 emit_data->output[0] = LLVMBuildExtractElement(builder, tmp, ctx->i32_0, "");
4209 emit_data->output[1] = LLVMBuildExtractElement(builder, tmp, ctx->i32_1, "");
4210 }
4211
4212 static void read_lane_emit(
4213 const struct lp_build_tgsi_action *action,
4214 struct lp_build_tgsi_context *bld_base,
4215 struct lp_build_emit_data *emit_data)
4216 {
4217 struct si_shader_context *ctx = si_shader_context(bld_base);
4218
4219 if (emit_data->inst->Instruction.Opcode == TGSI_OPCODE_READ_INVOC) {
4220 emit_data->args[0] = lp_build_emit_fetch(bld_base, emit_data->inst,
4221 0, emit_data->src_chan);
4222
4223 /* Always read the source invocation (= lane) from the X channel. */
4224 emit_data->args[1] = lp_build_emit_fetch(bld_base, emit_data->inst,
4225 1, TGSI_CHAN_X);
4226 emit_data->arg_count = 2;
4227 }
4228
4229 /* We currently have no other way to prevent LLVM from lifting the icmp
4230 * calls to a dominating basic block.
4231 */
4232 ac_build_optimization_barrier(&ctx->ac, &emit_data->args[0]);
4233
4234 for (unsigned i = 0; i < emit_data->arg_count; ++i)
4235 emit_data->args[i] = ac_to_integer(&ctx->ac, emit_data->args[i]);
4236
4237 emit_data->output[emit_data->chan] =
4238 ac_build_intrinsic(&ctx->ac, action->intr_name,
4239 ctx->i32, emit_data->args, emit_data->arg_count,
4240 AC_FUNC_ATTR_READNONE |
4241 AC_FUNC_ATTR_CONVERGENT);
4242 }
4243
4244 static unsigned si_llvm_get_stream(struct lp_build_tgsi_context *bld_base,
4245 struct lp_build_emit_data *emit_data)
4246 {
4247 struct si_shader_context *ctx = si_shader_context(bld_base);
4248 struct tgsi_src_register src0 = emit_data->inst->Src[0].Register;
4249 LLVMValueRef imm;
4250 unsigned stream;
4251
4252 assert(src0.File == TGSI_FILE_IMMEDIATE);
4253
4254 imm = ctx->imms[src0.Index * TGSI_NUM_CHANNELS + src0.SwizzleX];
4255 stream = LLVMConstIntGetZExtValue(imm) & 0x3;
4256 return stream;
4257 }
4258
4259 /* Emit one vertex from the geometry shader */
4260 static void si_llvm_emit_vertex(struct ac_shader_abi *abi,
4261 unsigned stream,
4262 LLVMValueRef *addrs)
4263 {
4264 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
4265 struct tgsi_shader_info *info = &ctx->shader->selector->info;
4266 struct si_shader *shader = ctx->shader;
4267 struct lp_build_if_state if_state;
4268 LLVMValueRef soffset = LLVMGetParam(ctx->main_fn,
4269 ctx->param_gs2vs_offset);
4270 LLVMValueRef gs_next_vertex;
4271 LLVMValueRef can_emit;
4272 unsigned chan, offset;
4273 int i;
4274
4275 /* Write vertex attribute values to GSVS ring */
4276 gs_next_vertex = LLVMBuildLoad(ctx->ac.builder,
4277 ctx->gs_next_vertex[stream],
4278 "");
4279
4280 /* If this thread has already emitted the declared maximum number of
4281 * vertices, skip the write: excessive vertex emissions are not
4282 * supposed to have any effect.
4283 *
4284 * If the shader has no writes to memory, kill it instead. This skips
4285 * further memory loads and may allow LLVM to skip to the end
4286 * altogether.
4287 */
4288 can_emit = LLVMBuildICmp(ctx->ac.builder, LLVMIntULT, gs_next_vertex,
4289 LLVMConstInt(ctx->i32,
4290 shader->selector->gs_max_out_vertices, 0), "");
4291
4292 bool use_kill = !info->writes_memory;
4293 if (use_kill) {
4294 ac_build_kill_if_false(&ctx->ac, can_emit);
4295 } else {
4296 lp_build_if(&if_state, &ctx->gallivm, can_emit);
4297 }
4298
4299 offset = 0;
4300 for (i = 0; i < info->num_outputs; i++) {
4301 for (chan = 0; chan < 4; chan++) {
4302 if (!(info->output_usagemask[i] & (1 << chan)) ||
4303 ((info->output_streams[i] >> (2 * chan)) & 3) != stream)
4304 continue;
4305
4306 LLVMValueRef out_val = LLVMBuildLoad(ctx->ac.builder, addrs[4 * i + chan], "");
4307 LLVMValueRef voffset =
4308 LLVMConstInt(ctx->i32, offset *
4309 shader->selector->gs_max_out_vertices, 0);
4310 offset++;
4311
4312 voffset = LLVMBuildAdd(ctx->ac.builder, voffset, gs_next_vertex, "");
4313 voffset = LLVMBuildMul(ctx->ac.builder, voffset,
4314 LLVMConstInt(ctx->i32, 4, 0), "");
4315
4316 out_val = ac_to_integer(&ctx->ac, out_val);
4317
4318 ac_build_buffer_store_dword(&ctx->ac,
4319 ctx->gsvs_ring[stream],
4320 out_val, 1,
4321 voffset, soffset, 0,
4322 1, 1, true, true);
4323 }
4324 }
4325
4326 gs_next_vertex = LLVMBuildAdd(ctx->ac.builder, gs_next_vertex, ctx->i32_1, "");
4327 LLVMBuildStore(ctx->ac.builder, gs_next_vertex, ctx->gs_next_vertex[stream]);
4328
4329 /* Signal vertex emission if vertex data was written. */
4330 if (offset) {
4331 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_EMIT | AC_SENDMSG_GS | (stream << 8),
4332 si_get_gs_wave_id(ctx));
4333 }
4334
4335 if (!use_kill)
4336 lp_build_endif(&if_state);
4337 }
4338
4339 /* Emit one vertex from the geometry shader */
4340 static void si_tgsi_emit_vertex(
4341 const struct lp_build_tgsi_action *action,
4342 struct lp_build_tgsi_context *bld_base,
4343 struct lp_build_emit_data *emit_data)
4344 {
4345 struct si_shader_context *ctx = si_shader_context(bld_base);
4346 unsigned stream = si_llvm_get_stream(bld_base, emit_data);
4347
4348 si_llvm_emit_vertex(&ctx->abi, stream, ctx->outputs[0]);
4349 }
4350
4351 /* Cut one primitive from the geometry shader */
4352 static void si_llvm_emit_primitive(struct ac_shader_abi *abi,
4353 unsigned stream)
4354 {
4355 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
4356
4357 /* Signal primitive cut */
4358 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_CUT | AC_SENDMSG_GS | (stream << 8),
4359 si_get_gs_wave_id(ctx));
4360 }
4361
4362 /* Cut one primitive from the geometry shader */
4363 static void si_tgsi_emit_primitive(
4364 const struct lp_build_tgsi_action *action,
4365 struct lp_build_tgsi_context *bld_base,
4366 struct lp_build_emit_data *emit_data)
4367 {
4368 struct si_shader_context *ctx = si_shader_context(bld_base);
4369
4370 si_llvm_emit_primitive(&ctx->abi, si_llvm_get_stream(bld_base, emit_data));
4371 }
4372
4373 static void si_llvm_emit_barrier(const struct lp_build_tgsi_action *action,
4374 struct lp_build_tgsi_context *bld_base,
4375 struct lp_build_emit_data *emit_data)
4376 {
4377 struct si_shader_context *ctx = si_shader_context(bld_base);
4378
4379 /* SI only (thanks to a hw bug workaround):
4380 * The real barrier instruction isn’t needed, because an entire patch
4381 * always fits into a single wave.
4382 */
4383 if (ctx->screen->info.chip_class == SI &&
4384 ctx->type == PIPE_SHADER_TESS_CTRL) {
4385 ac_build_waitcnt(&ctx->ac, LGKM_CNT & VM_CNT);
4386 return;
4387 }
4388
4389 ac_build_s_barrier(&ctx->ac);
4390 }
4391
4392 static void si_create_function(struct si_shader_context *ctx,
4393 const char *name,
4394 LLVMTypeRef *returns, unsigned num_returns,
4395 struct si_function_info *fninfo,
4396 unsigned max_workgroup_size)
4397 {
4398 int i;
4399
4400 si_llvm_create_func(ctx, name, returns, num_returns,
4401 fninfo->types, fninfo->num_params);
4402 ctx->return_value = LLVMGetUndef(ctx->return_type);
4403
4404 for (i = 0; i < fninfo->num_sgpr_params; ++i) {
4405 LLVMValueRef P = LLVMGetParam(ctx->main_fn, i);
4406
4407 /* The combination of:
4408 * - noalias
4409 * - dereferenceable
4410 * - invariant.load
4411 * allows the optimization passes to move loads and reduces
4412 * SGPR spilling significantly.
4413 */
4414 ac_add_function_attr(ctx->ac.context, ctx->main_fn, i + 1,
4415 AC_FUNC_ATTR_INREG);
4416
4417 if (LLVMGetTypeKind(LLVMTypeOf(P)) == LLVMPointerTypeKind) {
4418 ac_add_function_attr(ctx->ac.context, ctx->main_fn, i + 1,
4419 AC_FUNC_ATTR_NOALIAS);
4420 ac_add_attr_dereferenceable(P, UINT64_MAX);
4421 }
4422 }
4423
4424 for (i = 0; i < fninfo->num_params; ++i) {
4425 if (fninfo->assign[i])
4426 *fninfo->assign[i] = LLVMGetParam(ctx->main_fn, i);
4427 }
4428
4429 if (ctx->screen->info.address32_hi) {
4430 ac_llvm_add_target_dep_function_attr(ctx->main_fn,
4431 "amdgpu-32bit-address-high-bits",
4432 ctx->screen->info.address32_hi);
4433 }
4434
4435 if (max_workgroup_size) {
4436 ac_llvm_add_target_dep_function_attr(ctx->main_fn,
4437 "amdgpu-max-work-group-size",
4438 max_workgroup_size);
4439 }
4440 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
4441 "no-signed-zeros-fp-math",
4442 "true");
4443
4444 if (ctx->screen->debug_flags & DBG(UNSAFE_MATH)) {
4445 /* These were copied from some LLVM test. */
4446 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
4447 "less-precise-fpmad",
4448 "true");
4449 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
4450 "no-infs-fp-math",
4451 "true");
4452 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
4453 "no-nans-fp-math",
4454 "true");
4455 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
4456 "unsafe-fp-math",
4457 "true");
4458 }
4459 }
4460
4461 static void declare_streamout_params(struct si_shader_context *ctx,
4462 struct pipe_stream_output_info *so,
4463 struct si_function_info *fninfo)
4464 {
4465 int i;
4466
4467 /* Streamout SGPRs. */
4468 if (so->num_outputs) {
4469 if (ctx->type != PIPE_SHADER_TESS_EVAL)
4470 ctx->param_streamout_config = add_arg(fninfo, ARG_SGPR, ctx->ac.i32);
4471 else
4472 ctx->param_streamout_config = fninfo->num_params - 1;
4473
4474 ctx->param_streamout_write_index = add_arg(fninfo, ARG_SGPR, ctx->ac.i32);
4475 }
4476 /* A streamout buffer offset is loaded if the stride is non-zero. */
4477 for (i = 0; i < 4; i++) {
4478 if (!so->stride[i])
4479 continue;
4480
4481 ctx->param_streamout_offset[i] = add_arg(fninfo, ARG_SGPR, ctx->ac.i32);
4482 }
4483 }
4484
4485 static unsigned si_get_max_workgroup_size(const struct si_shader *shader)
4486 {
4487 switch (shader->selector->type) {
4488 case PIPE_SHADER_TESS_CTRL:
4489 /* Return this so that LLVM doesn't remove s_barrier
4490 * instructions on chips where we use s_barrier. */
4491 return shader->selector->screen->info.chip_class >= CIK ? 128 : 64;
4492
4493 case PIPE_SHADER_GEOMETRY:
4494 return shader->selector->screen->info.chip_class >= GFX9 ? 128 : 64;
4495
4496 case PIPE_SHADER_COMPUTE:
4497 break; /* see below */
4498
4499 default:
4500 return 0;
4501 }
4502
4503 const unsigned *properties = shader->selector->info.properties;
4504 unsigned max_work_group_size =
4505 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] *
4506 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT] *
4507 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH];
4508
4509 if (!max_work_group_size) {
4510 /* This is a variable group size compute shader,
4511 * compile it for the maximum possible group size.
4512 */
4513 max_work_group_size = SI_MAX_VARIABLE_THREADS_PER_BLOCK;
4514 }
4515 return max_work_group_size;
4516 }
4517
4518 static void declare_const_and_shader_buffers(struct si_shader_context *ctx,
4519 struct si_function_info *fninfo,
4520 bool assign_params)
4521 {
4522 LLVMTypeRef const_shader_buf_type;
4523
4524 if (ctx->shader->selector->info.const_buffers_declared == 1 &&
4525 ctx->shader->selector->info.shader_buffers_declared == 0)
4526 const_shader_buf_type = ctx->f32;
4527 else
4528 const_shader_buf_type = ctx->v4i32;
4529
4530 unsigned const_and_shader_buffers =
4531 add_arg(fninfo, ARG_SGPR,
4532 ac_array_in_const32_addr_space(const_shader_buf_type));
4533
4534 if (assign_params)
4535 ctx->param_const_and_shader_buffers = const_and_shader_buffers;
4536 }
4537
4538 static void declare_samplers_and_images(struct si_shader_context *ctx,
4539 struct si_function_info *fninfo,
4540 bool assign_params)
4541 {
4542 unsigned samplers_and_images =
4543 add_arg(fninfo, ARG_SGPR,
4544 ac_array_in_const32_addr_space(ctx->v8i32));
4545
4546 if (assign_params)
4547 ctx->param_samplers_and_images = samplers_and_images;
4548 }
4549
4550 static void declare_per_stage_desc_pointers(struct si_shader_context *ctx,
4551 struct si_function_info *fninfo,
4552 bool assign_params)
4553 {
4554 declare_const_and_shader_buffers(ctx, fninfo, assign_params);
4555 declare_samplers_and_images(ctx, fninfo, assign_params);
4556 }
4557
4558 static void declare_global_desc_pointers(struct si_shader_context *ctx,
4559 struct si_function_info *fninfo)
4560 {
4561 ctx->param_rw_buffers = add_arg(fninfo, ARG_SGPR,
4562 ac_array_in_const32_addr_space(ctx->v4i32));
4563 ctx->param_bindless_samplers_and_images = add_arg(fninfo, ARG_SGPR,
4564 ac_array_in_const32_addr_space(ctx->v8i32));
4565 }
4566
4567 static void declare_vs_specific_input_sgprs(struct si_shader_context *ctx,
4568 struct si_function_info *fninfo)
4569 {
4570 ctx->param_vs_state_bits = add_arg(fninfo, ARG_SGPR, ctx->i32);
4571 add_arg_assign(fninfo, ARG_SGPR, ctx->i32, &ctx->abi.base_vertex);
4572 add_arg_assign(fninfo, ARG_SGPR, ctx->i32, &ctx->abi.start_instance);
4573 add_arg_assign(fninfo, ARG_SGPR, ctx->i32, &ctx->abi.draw_id);
4574 }
4575
4576 static void declare_vs_input_vgprs(struct si_shader_context *ctx,
4577 struct si_function_info *fninfo,
4578 unsigned *num_prolog_vgprs)
4579 {
4580 struct si_shader *shader = ctx->shader;
4581
4582 add_arg_assign(fninfo, ARG_VGPR, ctx->i32, &ctx->abi.vertex_id);
4583 if (shader->key.as_ls) {
4584 ctx->param_rel_auto_id = add_arg(fninfo, ARG_VGPR, ctx->i32);
4585 add_arg_assign(fninfo, ARG_VGPR, ctx->i32, &ctx->abi.instance_id);
4586 } else {
4587 add_arg_assign(fninfo, ARG_VGPR, ctx->i32, &ctx->abi.instance_id);
4588 ctx->param_vs_prim_id = add_arg(fninfo, ARG_VGPR, ctx->i32);
4589 }
4590 add_arg(fninfo, ARG_VGPR, ctx->i32); /* unused */
4591
4592 if (!shader->is_gs_copy_shader) {
4593 /* Vertex load indices. */
4594 ctx->param_vertex_index0 = fninfo->num_params;
4595 for (unsigned i = 0; i < shader->selector->info.num_inputs; i++)
4596 add_arg(fninfo, ARG_VGPR, ctx->i32);
4597 *num_prolog_vgprs += shader->selector->info.num_inputs;
4598 }
4599 }
4600
4601 static void declare_tes_input_vgprs(struct si_shader_context *ctx,
4602 struct si_function_info *fninfo)
4603 {
4604 ctx->param_tes_u = add_arg(fninfo, ARG_VGPR, ctx->f32);
4605 ctx->param_tes_v = add_arg(fninfo, ARG_VGPR, ctx->f32);
4606 ctx->param_tes_rel_patch_id = add_arg(fninfo, ARG_VGPR, ctx->i32);
4607 add_arg_assign(fninfo, ARG_VGPR, ctx->i32, &ctx->abi.tes_patch_id);
4608 }
4609
4610 enum {
4611 /* Convenient merged shader definitions. */
4612 SI_SHADER_MERGED_VERTEX_TESSCTRL = PIPE_SHADER_TYPES,
4613 SI_SHADER_MERGED_VERTEX_OR_TESSEVAL_GEOMETRY,
4614 };
4615
4616 static void create_function(struct si_shader_context *ctx)
4617 {
4618 struct si_shader *shader = ctx->shader;
4619 struct si_function_info fninfo;
4620 LLVMTypeRef returns[16+32*4];
4621 unsigned i, num_return_sgprs;
4622 unsigned num_returns = 0;
4623 unsigned num_prolog_vgprs = 0;
4624 unsigned type = ctx->type;
4625 unsigned vs_blit_property =
4626 shader->selector->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS];
4627
4628 si_init_function_info(&fninfo);
4629
4630 /* Set MERGED shaders. */
4631 if (ctx->screen->info.chip_class >= GFX9) {
4632 if (shader->key.as_ls || type == PIPE_SHADER_TESS_CTRL)
4633 type = SI_SHADER_MERGED_VERTEX_TESSCTRL; /* LS or HS */
4634 else if (shader->key.as_es || type == PIPE_SHADER_GEOMETRY)
4635 type = SI_SHADER_MERGED_VERTEX_OR_TESSEVAL_GEOMETRY;
4636 }
4637
4638 LLVMTypeRef v3i32 = LLVMVectorType(ctx->i32, 3);
4639
4640 switch (type) {
4641 case PIPE_SHADER_VERTEX:
4642 declare_global_desc_pointers(ctx, &fninfo);
4643
4644 if (vs_blit_property) {
4645 ctx->param_vs_blit_inputs = fninfo.num_params;
4646 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* i16 x1, y1 */
4647 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* i16 x2, y2 */
4648 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* depth */
4649
4650 if (vs_blit_property == SI_VS_BLIT_SGPRS_POS_COLOR) {
4651 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* color0 */
4652 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* color1 */
4653 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* color2 */
4654 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* color3 */
4655 } else if (vs_blit_property == SI_VS_BLIT_SGPRS_POS_TEXCOORD) {
4656 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* texcoord.x1 */
4657 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* texcoord.y1 */
4658 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* texcoord.x2 */
4659 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* texcoord.y2 */
4660 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* texcoord.z */
4661 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* texcoord.w */
4662 }
4663
4664 /* VGPRs */
4665 declare_vs_input_vgprs(ctx, &fninfo, &num_prolog_vgprs);
4666 break;
4667 }
4668
4669 declare_per_stage_desc_pointers(ctx, &fninfo, true);
4670 declare_vs_specific_input_sgprs(ctx, &fninfo);
4671 ctx->param_vertex_buffers = add_arg(&fninfo, ARG_SGPR,
4672 ac_array_in_const32_addr_space(ctx->v4i32));
4673
4674 if (shader->key.as_es) {
4675 ctx->param_es2gs_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4676 } else if (shader->key.as_ls) {
4677 /* no extra parameters */
4678 } else {
4679 if (shader->is_gs_copy_shader) {
4680 fninfo.num_params = ctx->param_vs_state_bits + 1;
4681 fninfo.num_sgpr_params = fninfo.num_params;
4682 }
4683
4684 /* The locations of the other parameters are assigned dynamically. */
4685 declare_streamout_params(ctx, &shader->selector->so,
4686 &fninfo);
4687 }
4688
4689 /* VGPRs */
4690 declare_vs_input_vgprs(ctx, &fninfo, &num_prolog_vgprs);
4691 break;
4692
4693 case PIPE_SHADER_TESS_CTRL: /* SI-CI-VI */
4694 declare_global_desc_pointers(ctx, &fninfo);
4695 declare_per_stage_desc_pointers(ctx, &fninfo, true);
4696 ctx->param_tcs_offchip_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4697 ctx->param_tcs_out_lds_offsets = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4698 ctx->param_tcs_out_lds_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4699 ctx->param_vs_state_bits = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4700 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4701 ctx->param_tcs_factor_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4702
4703 /* VGPRs */
4704 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->abi.tcs_patch_id);
4705 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->abi.tcs_rel_ids);
4706
4707 /* param_tcs_offchip_offset and param_tcs_factor_offset are
4708 * placed after the user SGPRs.
4709 */
4710 for (i = 0; i < GFX6_TCS_NUM_USER_SGPR + 2; i++)
4711 returns[num_returns++] = ctx->i32; /* SGPRs */
4712 for (i = 0; i < 11; i++)
4713 returns[num_returns++] = ctx->f32; /* VGPRs */
4714 break;
4715
4716 case SI_SHADER_MERGED_VERTEX_TESSCTRL:
4717 /* Merged stages have 8 system SGPRs at the beginning. */
4718 /* SPI_SHADER_USER_DATA_ADDR_LO/HI_HS */
4719 if (HAVE_32BIT_POINTERS) {
4720 declare_per_stage_desc_pointers(ctx, &fninfo,
4721 ctx->type == PIPE_SHADER_TESS_CTRL);
4722 } else {
4723 declare_const_and_shader_buffers(ctx, &fninfo,
4724 ctx->type == PIPE_SHADER_TESS_CTRL);
4725 }
4726 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4727 ctx->param_merged_wave_info = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4728 ctx->param_tcs_factor_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4729 ctx->param_merged_scratch_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4730 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused */
4731 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused */
4732
4733 declare_global_desc_pointers(ctx, &fninfo);
4734 declare_per_stage_desc_pointers(ctx, &fninfo,
4735 ctx->type == PIPE_SHADER_VERTEX);
4736 declare_vs_specific_input_sgprs(ctx, &fninfo);
4737
4738 if (!HAVE_32BIT_POINTERS) {
4739 declare_samplers_and_images(ctx, &fninfo,
4740 ctx->type == PIPE_SHADER_TESS_CTRL);
4741 }
4742 ctx->param_tcs_offchip_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4743 ctx->param_tcs_out_lds_offsets = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4744 ctx->param_tcs_out_lds_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4745 if (!HAVE_32BIT_POINTERS) /* Align to 2 dwords. */
4746 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused */
4747 ctx->param_vertex_buffers = add_arg(&fninfo, ARG_SGPR,
4748 ac_array_in_const32_addr_space(ctx->v4i32));
4749
4750 /* VGPRs (first TCS, then VS) */
4751 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->abi.tcs_patch_id);
4752 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->abi.tcs_rel_ids);
4753
4754 if (ctx->type == PIPE_SHADER_VERTEX) {
4755 declare_vs_input_vgprs(ctx, &fninfo,
4756 &num_prolog_vgprs);
4757
4758 /* LS return values are inputs to the TCS main shader part. */
4759 for (i = 0; i < 8 + GFX9_TCS_NUM_USER_SGPR; i++)
4760 returns[num_returns++] = ctx->i32; /* SGPRs */
4761 for (i = 0; i < 2; i++)
4762 returns[num_returns++] = ctx->f32; /* VGPRs */
4763 } else {
4764 /* TCS return values are inputs to the TCS epilog.
4765 *
4766 * param_tcs_offchip_offset, param_tcs_factor_offset,
4767 * param_tcs_offchip_layout, and param_rw_buffers
4768 * should be passed to the epilog.
4769 */
4770 for (i = 0; i <= 8 + GFX9_SGPR_TCS_OUT_LAYOUT; i++)
4771 returns[num_returns++] = ctx->i32; /* SGPRs */
4772 for (i = 0; i < 11; i++)
4773 returns[num_returns++] = ctx->f32; /* VGPRs */
4774 }
4775 break;
4776
4777 case SI_SHADER_MERGED_VERTEX_OR_TESSEVAL_GEOMETRY:
4778 /* Merged stages have 8 system SGPRs at the beginning. */
4779 /* SPI_SHADER_USER_DATA_ADDR_LO/HI_GS */
4780 if (HAVE_32BIT_POINTERS) {
4781 declare_per_stage_desc_pointers(ctx, &fninfo,
4782 ctx->type == PIPE_SHADER_GEOMETRY);
4783 } else {
4784 declare_const_and_shader_buffers(ctx, &fninfo,
4785 ctx->type == PIPE_SHADER_GEOMETRY);
4786 }
4787 ctx->param_gs2vs_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4788 ctx->param_merged_wave_info = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4789 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4790 ctx->param_merged_scratch_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4791 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused (SPI_SHADER_PGM_LO/HI_GS << 8) */
4792 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused (SPI_SHADER_PGM_LO/HI_GS >> 24) */
4793
4794 declare_global_desc_pointers(ctx, &fninfo);
4795 declare_per_stage_desc_pointers(ctx, &fninfo,
4796 (ctx->type == PIPE_SHADER_VERTEX ||
4797 ctx->type == PIPE_SHADER_TESS_EVAL));
4798 if (ctx->type == PIPE_SHADER_VERTEX) {
4799 declare_vs_specific_input_sgprs(ctx, &fninfo);
4800 } else {
4801 ctx->param_vs_state_bits = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4802 ctx->param_tcs_offchip_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4803 ctx->param_tes_offchip_addr = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4804 /* Declare as many input SGPRs as the VS has. */
4805 if (!HAVE_32BIT_POINTERS)
4806 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused */
4807 }
4808
4809 if (!HAVE_32BIT_POINTERS) {
4810 declare_samplers_and_images(ctx, &fninfo,
4811 ctx->type == PIPE_SHADER_GEOMETRY);
4812 }
4813 if (ctx->type == PIPE_SHADER_VERTEX) {
4814 ctx->param_vertex_buffers = add_arg(&fninfo, ARG_SGPR,
4815 ac_array_in_const32_addr_space(ctx->v4i32));
4816 }
4817
4818 /* VGPRs (first GS, then VS/TES) */
4819 ctx->param_gs_vtx01_offset = add_arg(&fninfo, ARG_VGPR, ctx->i32);
4820 ctx->param_gs_vtx23_offset = add_arg(&fninfo, ARG_VGPR, ctx->i32);
4821 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->abi.gs_prim_id);
4822 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->abi.gs_invocation_id);
4823 ctx->param_gs_vtx45_offset = add_arg(&fninfo, ARG_VGPR, ctx->i32);
4824
4825 if (ctx->type == PIPE_SHADER_VERTEX) {
4826 declare_vs_input_vgprs(ctx, &fninfo,
4827 &num_prolog_vgprs);
4828 } else if (ctx->type == PIPE_SHADER_TESS_EVAL) {
4829 declare_tes_input_vgprs(ctx, &fninfo);
4830 }
4831
4832 if (ctx->type == PIPE_SHADER_VERTEX ||
4833 ctx->type == PIPE_SHADER_TESS_EVAL) {
4834 unsigned num_user_sgprs;
4835
4836 if (ctx->type == PIPE_SHADER_VERTEX)
4837 num_user_sgprs = GFX9_VSGS_NUM_USER_SGPR;
4838 else
4839 num_user_sgprs = GFX9_TESGS_NUM_USER_SGPR;
4840
4841 /* ES return values are inputs to GS. */
4842 for (i = 0; i < 8 + num_user_sgprs; i++)
4843 returns[num_returns++] = ctx->i32; /* SGPRs */
4844 for (i = 0; i < 5; i++)
4845 returns[num_returns++] = ctx->f32; /* VGPRs */
4846 }
4847 break;
4848
4849 case PIPE_SHADER_TESS_EVAL:
4850 declare_global_desc_pointers(ctx, &fninfo);
4851 declare_per_stage_desc_pointers(ctx, &fninfo, true);
4852 ctx->param_vs_state_bits = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4853 ctx->param_tcs_offchip_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4854 ctx->param_tes_offchip_addr = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4855
4856 if (shader->key.as_es) {
4857 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4858 add_arg(&fninfo, ARG_SGPR, ctx->i32);
4859 ctx->param_es2gs_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4860 } else {
4861 add_arg(&fninfo, ARG_SGPR, ctx->i32);
4862 declare_streamout_params(ctx, &shader->selector->so,
4863 &fninfo);
4864 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4865 }
4866
4867 /* VGPRs */
4868 declare_tes_input_vgprs(ctx, &fninfo);
4869 break;
4870
4871 case PIPE_SHADER_GEOMETRY:
4872 declare_global_desc_pointers(ctx, &fninfo);
4873 declare_per_stage_desc_pointers(ctx, &fninfo, true);
4874 ctx->param_gs2vs_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4875 ctx->param_gs_wave_id = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4876
4877 /* VGPRs */
4878 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->gs_vtx_offset[0]);
4879 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->gs_vtx_offset[1]);
4880 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->abi.gs_prim_id);
4881 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->gs_vtx_offset[2]);
4882 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->gs_vtx_offset[3]);
4883 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->gs_vtx_offset[4]);
4884 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->gs_vtx_offset[5]);
4885 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->abi.gs_invocation_id);
4886 break;
4887
4888 case PIPE_SHADER_FRAGMENT:
4889 declare_global_desc_pointers(ctx, &fninfo);
4890 declare_per_stage_desc_pointers(ctx, &fninfo, true);
4891 add_arg_checked(&fninfo, ARG_SGPR, ctx->f32, SI_PARAM_ALPHA_REF);
4892 add_arg_assign_checked(&fninfo, ARG_SGPR, ctx->i32,
4893 &ctx->abi.prim_mask, SI_PARAM_PRIM_MASK);
4894
4895 add_arg_checked(&fninfo, ARG_VGPR, ctx->v2i32, SI_PARAM_PERSP_SAMPLE);
4896 add_arg_checked(&fninfo, ARG_VGPR, ctx->v2i32, SI_PARAM_PERSP_CENTER);
4897 add_arg_checked(&fninfo, ARG_VGPR, ctx->v2i32, SI_PARAM_PERSP_CENTROID);
4898 add_arg_checked(&fninfo, ARG_VGPR, v3i32, SI_PARAM_PERSP_PULL_MODEL);
4899 add_arg_checked(&fninfo, ARG_VGPR, ctx->v2i32, SI_PARAM_LINEAR_SAMPLE);
4900 add_arg_checked(&fninfo, ARG_VGPR, ctx->v2i32, SI_PARAM_LINEAR_CENTER);
4901 add_arg_checked(&fninfo, ARG_VGPR, ctx->v2i32, SI_PARAM_LINEAR_CENTROID);
4902 add_arg_checked(&fninfo, ARG_VGPR, ctx->f32, SI_PARAM_LINE_STIPPLE_TEX);
4903 add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->f32,
4904 &ctx->abi.frag_pos[0], SI_PARAM_POS_X_FLOAT);
4905 add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->f32,
4906 &ctx->abi.frag_pos[1], SI_PARAM_POS_Y_FLOAT);
4907 add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->f32,
4908 &ctx->abi.frag_pos[2], SI_PARAM_POS_Z_FLOAT);
4909 add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->f32,
4910 &ctx->abi.frag_pos[3], SI_PARAM_POS_W_FLOAT);
4911 add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->i32,
4912 &ctx->abi.front_face, SI_PARAM_FRONT_FACE);
4913 shader->info.face_vgpr_index = 20;
4914 add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->i32,
4915 &ctx->abi.ancillary, SI_PARAM_ANCILLARY);
4916 shader->info.ancillary_vgpr_index = 21;
4917 add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->f32,
4918 &ctx->abi.sample_coverage, SI_PARAM_SAMPLE_COVERAGE);
4919 add_arg_checked(&fninfo, ARG_VGPR, ctx->i32, SI_PARAM_POS_FIXED_PT);
4920
4921 /* Color inputs from the prolog. */
4922 if (shader->selector->info.colors_read) {
4923 unsigned num_color_elements =
4924 util_bitcount(shader->selector->info.colors_read);
4925
4926 assert(fninfo.num_params + num_color_elements <= ARRAY_SIZE(fninfo.types));
4927 for (i = 0; i < num_color_elements; i++)
4928 add_arg(&fninfo, ARG_VGPR, ctx->f32);
4929
4930 num_prolog_vgprs += num_color_elements;
4931 }
4932
4933 /* Outputs for the epilog. */
4934 num_return_sgprs = SI_SGPR_ALPHA_REF + 1;
4935 num_returns =
4936 num_return_sgprs +
4937 util_bitcount(shader->selector->info.colors_written) * 4 +
4938 shader->selector->info.writes_z +
4939 shader->selector->info.writes_stencil +
4940 shader->selector->info.writes_samplemask +
4941 1 /* SampleMaskIn */;
4942
4943 num_returns = MAX2(num_returns,
4944 num_return_sgprs +
4945 PS_EPILOG_SAMPLEMASK_MIN_LOC + 1);
4946
4947 for (i = 0; i < num_return_sgprs; i++)
4948 returns[i] = ctx->i32;
4949 for (; i < num_returns; i++)
4950 returns[i] = ctx->f32;
4951 break;
4952
4953 case PIPE_SHADER_COMPUTE:
4954 declare_global_desc_pointers(ctx, &fninfo);
4955 declare_per_stage_desc_pointers(ctx, &fninfo, true);
4956 if (shader->selector->info.uses_grid_size)
4957 add_arg_assign(&fninfo, ARG_SGPR, v3i32, &ctx->abi.num_work_groups);
4958 if (shader->selector->info.uses_block_size &&
4959 shader->selector->info.properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] == 0)
4960 ctx->param_block_size = add_arg(&fninfo, ARG_SGPR, v3i32);
4961
4962 unsigned cs_user_data_dwords =
4963 shader->selector->info.properties[TGSI_PROPERTY_CS_USER_DATA_DWORDS];
4964 if (cs_user_data_dwords) {
4965 ctx->param_cs_user_data = add_arg(&fninfo, ARG_SGPR,
4966 LLVMVectorType(ctx->i32, cs_user_data_dwords));
4967 }
4968
4969 for (i = 0; i < 3; i++) {
4970 ctx->abi.workgroup_ids[i] = NULL;
4971 if (shader->selector->info.uses_block_id[i])
4972 add_arg_assign(&fninfo, ARG_SGPR, ctx->i32, &ctx->abi.workgroup_ids[i]);
4973 }
4974
4975 add_arg_assign(&fninfo, ARG_VGPR, v3i32, &ctx->abi.local_invocation_ids);
4976 break;
4977 default:
4978 assert(0 && "unimplemented shader");
4979 return;
4980 }
4981
4982 si_create_function(ctx, "main", returns, num_returns, &fninfo,
4983 si_get_max_workgroup_size(shader));
4984
4985 /* Reserve register locations for VGPR inputs the PS prolog may need. */
4986 if (ctx->type == PIPE_SHADER_FRAGMENT && !ctx->shader->is_monolithic) {
4987 ac_llvm_add_target_dep_function_attr(ctx->main_fn,
4988 "InitialPSInputAddr",
4989 S_0286D0_PERSP_SAMPLE_ENA(1) |
4990 S_0286D0_PERSP_CENTER_ENA(1) |
4991 S_0286D0_PERSP_CENTROID_ENA(1) |
4992 S_0286D0_LINEAR_SAMPLE_ENA(1) |
4993 S_0286D0_LINEAR_CENTER_ENA(1) |
4994 S_0286D0_LINEAR_CENTROID_ENA(1) |
4995 S_0286D0_FRONT_FACE_ENA(1) |
4996 S_0286D0_ANCILLARY_ENA(1) |
4997 S_0286D0_POS_FIXED_PT_ENA(1));
4998 }
4999
5000 shader->info.num_input_sgprs = 0;
5001 shader->info.num_input_vgprs = 0;
5002
5003 for (i = 0; i < fninfo.num_sgpr_params; ++i)
5004 shader->info.num_input_sgprs += ac_get_type_size(fninfo.types[i]) / 4;
5005
5006 for (; i < fninfo.num_params; ++i)
5007 shader->info.num_input_vgprs += ac_get_type_size(fninfo.types[i]) / 4;
5008
5009 assert(shader->info.num_input_vgprs >= num_prolog_vgprs);
5010 shader->info.num_input_vgprs -= num_prolog_vgprs;
5011
5012 if (shader->key.as_ls ||
5013 ctx->type == PIPE_SHADER_TESS_CTRL ||
5014 /* GFX9 has the ESGS ring buffer in LDS. */
5015 type == SI_SHADER_MERGED_VERTEX_OR_TESSEVAL_GEOMETRY)
5016 ac_declare_lds_as_pointer(&ctx->ac);
5017 }
5018
5019 /**
5020 * Load ESGS and GSVS ring buffer resource descriptors and save the variables
5021 * for later use.
5022 */
5023 static void preload_ring_buffers(struct si_shader_context *ctx)
5024 {
5025 LLVMBuilderRef builder = ctx->ac.builder;
5026
5027 LLVMValueRef buf_ptr = LLVMGetParam(ctx->main_fn,
5028 ctx->param_rw_buffers);
5029
5030 if (ctx->screen->info.chip_class <= VI &&
5031 (ctx->shader->key.as_es || ctx->type == PIPE_SHADER_GEOMETRY)) {
5032 unsigned ring =
5033 ctx->type == PIPE_SHADER_GEOMETRY ? SI_GS_RING_ESGS
5034 : SI_ES_RING_ESGS;
5035 LLVMValueRef offset = LLVMConstInt(ctx->i32, ring, 0);
5036
5037 ctx->esgs_ring =
5038 ac_build_load_to_sgpr(&ctx->ac, buf_ptr, offset);
5039 }
5040
5041 if (ctx->shader->is_gs_copy_shader) {
5042 LLVMValueRef offset = LLVMConstInt(ctx->i32, SI_RING_GSVS, 0);
5043
5044 ctx->gsvs_ring[0] =
5045 ac_build_load_to_sgpr(&ctx->ac, buf_ptr, offset);
5046 } else if (ctx->type == PIPE_SHADER_GEOMETRY) {
5047 const struct si_shader_selector *sel = ctx->shader->selector;
5048 LLVMValueRef offset = LLVMConstInt(ctx->i32, SI_RING_GSVS, 0);
5049 LLVMValueRef base_ring;
5050
5051 base_ring = ac_build_load_to_sgpr(&ctx->ac, buf_ptr, offset);
5052
5053 /* The conceptual layout of the GSVS ring is
5054 * v0c0 .. vLv0 v0c1 .. vLc1 ..
5055 * but the real memory layout is swizzled across
5056 * threads:
5057 * t0v0c0 .. t15v0c0 t0v1c0 .. t15v1c0 ... t15vLcL
5058 * t16v0c0 ..
5059 * Override the buffer descriptor accordingly.
5060 */
5061 LLVMTypeRef v2i64 = LLVMVectorType(ctx->i64, 2);
5062 uint64_t stream_offset = 0;
5063
5064 for (unsigned stream = 0; stream < 4; ++stream) {
5065 unsigned num_components;
5066 unsigned stride;
5067 unsigned num_records;
5068 LLVMValueRef ring, tmp;
5069
5070 num_components = sel->info.num_stream_output_components[stream];
5071 if (!num_components)
5072 continue;
5073
5074 stride = 4 * num_components * sel->gs_max_out_vertices;
5075
5076 /* Limit on the stride field for <= CIK. */
5077 assert(stride < (1 << 14));
5078
5079 num_records = 64;
5080
5081 ring = LLVMBuildBitCast(builder, base_ring, v2i64, "");
5082 tmp = LLVMBuildExtractElement(builder, ring, ctx->i32_0, "");
5083 tmp = LLVMBuildAdd(builder, tmp,
5084 LLVMConstInt(ctx->i64,
5085 stream_offset, 0), "");
5086 stream_offset += stride * 64;
5087
5088 ring = LLVMBuildInsertElement(builder, ring, tmp, ctx->i32_0, "");
5089 ring = LLVMBuildBitCast(builder, ring, ctx->v4i32, "");
5090 tmp = LLVMBuildExtractElement(builder, ring, ctx->i32_1, "");
5091 tmp = LLVMBuildOr(builder, tmp,
5092 LLVMConstInt(ctx->i32,
5093 S_008F04_STRIDE(stride) |
5094 S_008F04_SWIZZLE_ENABLE(1), 0), "");
5095 ring = LLVMBuildInsertElement(builder, ring, tmp, ctx->i32_1, "");
5096 ring = LLVMBuildInsertElement(builder, ring,
5097 LLVMConstInt(ctx->i32, num_records, 0),
5098 LLVMConstInt(ctx->i32, 2, 0), "");
5099 ring = LLVMBuildInsertElement(builder, ring,
5100 LLVMConstInt(ctx->i32,
5101 S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
5102 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
5103 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
5104 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
5105 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
5106 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
5107 S_008F0C_ELEMENT_SIZE(1) | /* element_size = 4 (bytes) */
5108 S_008F0C_INDEX_STRIDE(1) | /* index_stride = 16 (elements) */
5109 S_008F0C_ADD_TID_ENABLE(1),
5110 0),
5111 LLVMConstInt(ctx->i32, 3, 0), "");
5112
5113 ctx->gsvs_ring[stream] = ring;
5114 }
5115 } else if (ctx->type == PIPE_SHADER_TESS_EVAL) {
5116 ctx->tess_offchip_ring = get_tess_ring_descriptor(ctx, TESS_OFFCHIP_RING_TES);
5117 }
5118 }
5119
5120 static void si_llvm_emit_polygon_stipple(struct si_shader_context *ctx,
5121 LLVMValueRef param_rw_buffers,
5122 unsigned param_pos_fixed_pt)
5123 {
5124 LLVMBuilderRef builder = ctx->ac.builder;
5125 LLVMValueRef slot, desc, offset, row, bit, address[2];
5126
5127 /* Use the fixed-point gl_FragCoord input.
5128 * Since the stipple pattern is 32x32 and it repeats, just get 5 bits
5129 * per coordinate to get the repeating effect.
5130 */
5131 address[0] = si_unpack_param(ctx, param_pos_fixed_pt, 0, 5);
5132 address[1] = si_unpack_param(ctx, param_pos_fixed_pt, 16, 5);
5133
5134 /* Load the buffer descriptor. */
5135 slot = LLVMConstInt(ctx->i32, SI_PS_CONST_POLY_STIPPLE, 0);
5136 desc = ac_build_load_to_sgpr(&ctx->ac, param_rw_buffers, slot);
5137
5138 /* The stipple pattern is 32x32, each row has 32 bits. */
5139 offset = LLVMBuildMul(builder, address[1],
5140 LLVMConstInt(ctx->i32, 4, 0), "");
5141 row = buffer_load_const(ctx, desc, offset);
5142 row = ac_to_integer(&ctx->ac, row);
5143 bit = LLVMBuildLShr(builder, row, address[0], "");
5144 bit = LLVMBuildTrunc(builder, bit, ctx->i1, "");
5145 ac_build_kill_if_false(&ctx->ac, bit);
5146 }
5147
5148 void si_shader_binary_read_config(struct ac_shader_binary *binary,
5149 struct si_shader_config *conf,
5150 unsigned symbol_offset)
5151 {
5152 unsigned i;
5153 const unsigned char *config =
5154 ac_shader_binary_config_start(binary, symbol_offset);
5155 bool really_needs_scratch = false;
5156
5157 /* LLVM adds SGPR spills to the scratch size.
5158 * Find out if we really need the scratch buffer.
5159 */
5160 for (i = 0; i < binary->reloc_count; i++) {
5161 const struct ac_shader_reloc *reloc = &binary->relocs[i];
5162
5163 if (!strcmp(scratch_rsrc_dword0_symbol, reloc->name) ||
5164 !strcmp(scratch_rsrc_dword1_symbol, reloc->name)) {
5165 really_needs_scratch = true;
5166 break;
5167 }
5168 }
5169
5170 /* XXX: We may be able to emit some of these values directly rather than
5171 * extracting fields to be emitted later.
5172 */
5173
5174 for (i = 0; i < binary->config_size_per_symbol; i+= 8) {
5175 unsigned reg = util_le32_to_cpu(*(uint32_t*)(config + i));
5176 unsigned value = util_le32_to_cpu(*(uint32_t*)(config + i + 4));
5177 switch (reg) {
5178 case R_00B028_SPI_SHADER_PGM_RSRC1_PS:
5179 case R_00B128_SPI_SHADER_PGM_RSRC1_VS:
5180 case R_00B228_SPI_SHADER_PGM_RSRC1_GS:
5181 case R_00B428_SPI_SHADER_PGM_RSRC1_HS:
5182 case R_00B848_COMPUTE_PGM_RSRC1:
5183 conf->num_sgprs = MAX2(conf->num_sgprs, (G_00B028_SGPRS(value) + 1) * 8);
5184 conf->num_vgprs = MAX2(conf->num_vgprs, (G_00B028_VGPRS(value) + 1) * 4);
5185 conf->float_mode = G_00B028_FLOAT_MODE(value);
5186 conf->rsrc1 = value;
5187 break;
5188 case R_00B02C_SPI_SHADER_PGM_RSRC2_PS:
5189 conf->lds_size = MAX2(conf->lds_size, G_00B02C_EXTRA_LDS_SIZE(value));
5190 break;
5191 case R_00B84C_COMPUTE_PGM_RSRC2:
5192 conf->lds_size = MAX2(conf->lds_size, G_00B84C_LDS_SIZE(value));
5193 conf->rsrc2 = value;
5194 break;
5195 case R_0286CC_SPI_PS_INPUT_ENA:
5196 conf->spi_ps_input_ena = value;
5197 break;
5198 case R_0286D0_SPI_PS_INPUT_ADDR:
5199 conf->spi_ps_input_addr = value;
5200 break;
5201 case R_0286E8_SPI_TMPRING_SIZE:
5202 case R_00B860_COMPUTE_TMPRING_SIZE:
5203 /* WAVESIZE is in units of 256 dwords. */
5204 if (really_needs_scratch)
5205 conf->scratch_bytes_per_wave =
5206 G_00B860_WAVESIZE(value) * 256 * 4;
5207 break;
5208 case 0x4: /* SPILLED_SGPRS */
5209 conf->spilled_sgprs = value;
5210 break;
5211 case 0x8: /* SPILLED_VGPRS */
5212 conf->spilled_vgprs = value;
5213 break;
5214 default:
5215 {
5216 static bool printed;
5217
5218 if (!printed) {
5219 fprintf(stderr, "Warning: LLVM emitted unknown "
5220 "config register: 0x%x\n", reg);
5221 printed = true;
5222 }
5223 }
5224 break;
5225 }
5226 }
5227
5228 if (!conf->spi_ps_input_addr)
5229 conf->spi_ps_input_addr = conf->spi_ps_input_ena;
5230 }
5231
5232 void si_shader_apply_scratch_relocs(struct si_shader *shader,
5233 uint64_t scratch_va)
5234 {
5235 unsigned i;
5236 uint32_t scratch_rsrc_dword0 = scratch_va;
5237 uint32_t scratch_rsrc_dword1 =
5238 S_008F04_BASE_ADDRESS_HI(scratch_va >> 32);
5239
5240 /* Enable scratch coalescing. */
5241 scratch_rsrc_dword1 |= S_008F04_SWIZZLE_ENABLE(1);
5242
5243 for (i = 0 ; i < shader->binary.reloc_count; i++) {
5244 const struct ac_shader_reloc *reloc =
5245 &shader->binary.relocs[i];
5246 if (!strcmp(scratch_rsrc_dword0_symbol, reloc->name)) {
5247 util_memcpy_cpu_to_le32(shader->binary.code + reloc->offset,
5248 &scratch_rsrc_dword0, 4);
5249 } else if (!strcmp(scratch_rsrc_dword1_symbol, reloc->name)) {
5250 util_memcpy_cpu_to_le32(shader->binary.code + reloc->offset,
5251 &scratch_rsrc_dword1, 4);
5252 }
5253 }
5254 }
5255
5256 /* For the UMR disassembler. */
5257 #define DEBUGGER_END_OF_CODE_MARKER 0xbf9f0000 /* invalid instruction */
5258 #define DEBUGGER_NUM_MARKERS 5
5259
5260 static unsigned si_get_shader_binary_size(const struct si_shader *shader)
5261 {
5262 unsigned size = shader->binary.code_size;
5263
5264 if (shader->prolog)
5265 size += shader->prolog->binary.code_size;
5266 if (shader->previous_stage)
5267 size += shader->previous_stage->binary.code_size;
5268 if (shader->prolog2)
5269 size += shader->prolog2->binary.code_size;
5270 if (shader->epilog)
5271 size += shader->epilog->binary.code_size;
5272 return size + DEBUGGER_NUM_MARKERS * 4;
5273 }
5274
5275 int si_shader_binary_upload(struct si_screen *sscreen, struct si_shader *shader)
5276 {
5277 const struct ac_shader_binary *prolog =
5278 shader->prolog ? &shader->prolog->binary : NULL;
5279 const struct ac_shader_binary *previous_stage =
5280 shader->previous_stage ? &shader->previous_stage->binary : NULL;
5281 const struct ac_shader_binary *prolog2 =
5282 shader->prolog2 ? &shader->prolog2->binary : NULL;
5283 const struct ac_shader_binary *epilog =
5284 shader->epilog ? &shader->epilog->binary : NULL;
5285 const struct ac_shader_binary *mainb = &shader->binary;
5286 unsigned bo_size = si_get_shader_binary_size(shader) +
5287 (!epilog ? mainb->rodata_size : 0);
5288 unsigned char *ptr;
5289
5290 assert(!prolog || !prolog->rodata_size);
5291 assert(!previous_stage || !previous_stage->rodata_size);
5292 assert(!prolog2 || !prolog2->rodata_size);
5293 assert((!prolog && !previous_stage && !prolog2 && !epilog) ||
5294 !mainb->rodata_size);
5295 assert(!epilog || !epilog->rodata_size);
5296
5297 r600_resource_reference(&shader->bo, NULL);
5298 shader->bo = si_aligned_buffer_create(&sscreen->b,
5299 sscreen->cpdma_prefetch_writes_memory ?
5300 0 : SI_RESOURCE_FLAG_READ_ONLY,
5301 PIPE_USAGE_IMMUTABLE,
5302 align(bo_size, SI_CPDMA_ALIGNMENT),
5303 256);
5304 if (!shader->bo)
5305 return -ENOMEM;
5306
5307 /* Upload. */
5308 ptr = sscreen->ws->buffer_map(shader->bo->buf, NULL,
5309 PIPE_TRANSFER_READ_WRITE |
5310 PIPE_TRANSFER_UNSYNCHRONIZED);
5311
5312 /* Don't use util_memcpy_cpu_to_le32. LLVM binaries are
5313 * endian-independent. */
5314 if (prolog) {
5315 memcpy(ptr, prolog->code, prolog->code_size);
5316 ptr += prolog->code_size;
5317 }
5318 if (previous_stage) {
5319 memcpy(ptr, previous_stage->code, previous_stage->code_size);
5320 ptr += previous_stage->code_size;
5321 }
5322 if (prolog2) {
5323 memcpy(ptr, prolog2->code, prolog2->code_size);
5324 ptr += prolog2->code_size;
5325 }
5326
5327 memcpy(ptr, mainb->code, mainb->code_size);
5328 ptr += mainb->code_size;
5329
5330 if (epilog) {
5331 memcpy(ptr, epilog->code, epilog->code_size);
5332 ptr += epilog->code_size;
5333 } else if (mainb->rodata_size > 0) {
5334 memcpy(ptr, mainb->rodata, mainb->rodata_size);
5335 ptr += mainb->rodata_size;
5336 }
5337
5338 /* Add end-of-code markers for the UMR disassembler. */
5339 uint32_t *ptr32 = (uint32_t*)ptr;
5340 for (unsigned i = 0; i < DEBUGGER_NUM_MARKERS; i++)
5341 ptr32[i] = DEBUGGER_END_OF_CODE_MARKER;
5342
5343 sscreen->ws->buffer_unmap(shader->bo->buf);
5344 return 0;
5345 }
5346
5347 static void si_shader_dump_disassembly(const struct ac_shader_binary *binary,
5348 struct pipe_debug_callback *debug,
5349 const char *name, FILE *file)
5350 {
5351 char *line, *p;
5352 unsigned i, count;
5353
5354 if (binary->disasm_string) {
5355 fprintf(file, "Shader %s disassembly:\n", name);
5356 fprintf(file, "%s", binary->disasm_string);
5357
5358 if (debug && debug->debug_message) {
5359 /* Very long debug messages are cut off, so send the
5360 * disassembly one line at a time. This causes more
5361 * overhead, but on the plus side it simplifies
5362 * parsing of resulting logs.
5363 */
5364 pipe_debug_message(debug, SHADER_INFO,
5365 "Shader Disassembly Begin");
5366
5367 line = binary->disasm_string;
5368 while (*line) {
5369 p = util_strchrnul(line, '\n');
5370 count = p - line;
5371
5372 if (count) {
5373 pipe_debug_message(debug, SHADER_INFO,
5374 "%.*s", count, line);
5375 }
5376
5377 if (!*p)
5378 break;
5379 line = p + 1;
5380 }
5381
5382 pipe_debug_message(debug, SHADER_INFO,
5383 "Shader Disassembly End");
5384 }
5385 } else {
5386 fprintf(file, "Shader %s binary:\n", name);
5387 for (i = 0; i < binary->code_size; i += 4) {
5388 fprintf(file, "@0x%x: %02x%02x%02x%02x\n", i,
5389 binary->code[i + 3], binary->code[i + 2],
5390 binary->code[i + 1], binary->code[i]);
5391 }
5392 }
5393 }
5394
5395 static void si_calculate_max_simd_waves(struct si_shader *shader)
5396 {
5397 struct si_screen *sscreen = shader->selector->screen;
5398 struct si_shader_config *conf = &shader->config;
5399 unsigned num_inputs = shader->selector->info.num_inputs;
5400 unsigned lds_increment = sscreen->info.chip_class >= CIK ? 512 : 256;
5401 unsigned lds_per_wave = 0;
5402 unsigned max_simd_waves;
5403
5404 max_simd_waves = ac_get_max_simd_waves(sscreen->info.family);
5405
5406 /* Compute LDS usage for PS. */
5407 switch (shader->selector->type) {
5408 case PIPE_SHADER_FRAGMENT:
5409 /* The minimum usage per wave is (num_inputs * 48). The maximum
5410 * usage is (num_inputs * 48 * 16).
5411 * We can get anything in between and it varies between waves.
5412 *
5413 * The 48 bytes per input for a single primitive is equal to
5414 * 4 bytes/component * 4 components/input * 3 points.
5415 *
5416 * Other stages don't know the size at compile time or don't
5417 * allocate LDS per wave, but instead they do it per thread group.
5418 */
5419 lds_per_wave = conf->lds_size * lds_increment +
5420 align(num_inputs * 48, lds_increment);
5421 break;
5422 case PIPE_SHADER_COMPUTE:
5423 if (shader->selector) {
5424 unsigned max_workgroup_size =
5425 si_get_max_workgroup_size(shader);
5426 lds_per_wave = (conf->lds_size * lds_increment) /
5427 DIV_ROUND_UP(max_workgroup_size, 64);
5428 }
5429 break;
5430 }
5431
5432 /* Compute the per-SIMD wave counts. */
5433 if (conf->num_sgprs) {
5434 if (sscreen->info.chip_class >= VI)
5435 max_simd_waves = MIN2(max_simd_waves, 800 / conf->num_sgprs);
5436 else
5437 max_simd_waves = MIN2(max_simd_waves, 512 / conf->num_sgprs);
5438 }
5439
5440 if (conf->num_vgprs)
5441 max_simd_waves = MIN2(max_simd_waves, 256 / conf->num_vgprs);
5442
5443 /* LDS is 64KB per CU (4 SIMDs), which is 16KB per SIMD (usage above
5444 * 16KB makes some SIMDs unoccupied). */
5445 if (lds_per_wave)
5446 max_simd_waves = MIN2(max_simd_waves, 16384 / lds_per_wave);
5447
5448 conf->max_simd_waves = max_simd_waves;
5449 }
5450
5451 void si_shader_dump_stats_for_shader_db(const struct si_shader *shader,
5452 struct pipe_debug_callback *debug)
5453 {
5454 const struct si_shader_config *conf = &shader->config;
5455
5456 pipe_debug_message(debug, SHADER_INFO,
5457 "Shader Stats: SGPRS: %d VGPRS: %d Code Size: %d "
5458 "LDS: %d Scratch: %d Max Waves: %d Spilled SGPRs: %d "
5459 "Spilled VGPRs: %d PrivMem VGPRs: %d",
5460 conf->num_sgprs, conf->num_vgprs,
5461 si_get_shader_binary_size(shader),
5462 conf->lds_size, conf->scratch_bytes_per_wave,
5463 conf->max_simd_waves, conf->spilled_sgprs,
5464 conf->spilled_vgprs, conf->private_mem_vgprs);
5465 }
5466
5467 static void si_shader_dump_stats(struct si_screen *sscreen,
5468 const struct si_shader *shader,
5469 unsigned processor,
5470 FILE *file,
5471 bool check_debug_option)
5472 {
5473 const struct si_shader_config *conf = &shader->config;
5474
5475 if (!check_debug_option ||
5476 si_can_dump_shader(sscreen, processor)) {
5477 if (processor == PIPE_SHADER_FRAGMENT) {
5478 fprintf(file, "*** SHADER CONFIG ***\n"
5479 "SPI_PS_INPUT_ADDR = 0x%04x\n"
5480 "SPI_PS_INPUT_ENA = 0x%04x\n",
5481 conf->spi_ps_input_addr, conf->spi_ps_input_ena);
5482 }
5483
5484 fprintf(file, "*** SHADER STATS ***\n"
5485 "SGPRS: %d\n"
5486 "VGPRS: %d\n"
5487 "Spilled SGPRs: %d\n"
5488 "Spilled VGPRs: %d\n"
5489 "Private memory VGPRs: %d\n"
5490 "Code Size: %d bytes\n"
5491 "LDS: %d blocks\n"
5492 "Scratch: %d bytes per wave\n"
5493 "Max Waves: %d\n"
5494 "********************\n\n\n",
5495 conf->num_sgprs, conf->num_vgprs,
5496 conf->spilled_sgprs, conf->spilled_vgprs,
5497 conf->private_mem_vgprs,
5498 si_get_shader_binary_size(shader),
5499 conf->lds_size, conf->scratch_bytes_per_wave,
5500 conf->max_simd_waves);
5501 }
5502 }
5503
5504 const char *si_get_shader_name(const struct si_shader *shader, unsigned processor)
5505 {
5506 switch (processor) {
5507 case PIPE_SHADER_VERTEX:
5508 if (shader->key.as_es)
5509 return "Vertex Shader as ES";
5510 else if (shader->key.as_ls)
5511 return "Vertex Shader as LS";
5512 else
5513 return "Vertex Shader as VS";
5514 case PIPE_SHADER_TESS_CTRL:
5515 return "Tessellation Control Shader";
5516 case PIPE_SHADER_TESS_EVAL:
5517 if (shader->key.as_es)
5518 return "Tessellation Evaluation Shader as ES";
5519 else
5520 return "Tessellation Evaluation Shader as VS";
5521 case PIPE_SHADER_GEOMETRY:
5522 if (shader->is_gs_copy_shader)
5523 return "GS Copy Shader as VS";
5524 else
5525 return "Geometry Shader";
5526 case PIPE_SHADER_FRAGMENT:
5527 return "Pixel Shader";
5528 case PIPE_SHADER_COMPUTE:
5529 return "Compute Shader";
5530 default:
5531 return "Unknown Shader";
5532 }
5533 }
5534
5535 void si_shader_dump(struct si_screen *sscreen, const struct si_shader *shader,
5536 struct pipe_debug_callback *debug, unsigned processor,
5537 FILE *file, bool check_debug_option)
5538 {
5539 if (!check_debug_option ||
5540 si_can_dump_shader(sscreen, processor))
5541 si_dump_shader_key(processor, shader, file);
5542
5543 if (!check_debug_option && shader->binary.llvm_ir_string) {
5544 if (shader->previous_stage &&
5545 shader->previous_stage->binary.llvm_ir_string) {
5546 fprintf(file, "\n%s - previous stage - LLVM IR:\n\n",
5547 si_get_shader_name(shader, processor));
5548 fprintf(file, "%s\n", shader->previous_stage->binary.llvm_ir_string);
5549 }
5550
5551 fprintf(file, "\n%s - main shader part - LLVM IR:\n\n",
5552 si_get_shader_name(shader, processor));
5553 fprintf(file, "%s\n", shader->binary.llvm_ir_string);
5554 }
5555
5556 if (!check_debug_option ||
5557 (si_can_dump_shader(sscreen, processor) &&
5558 !(sscreen->debug_flags & DBG(NO_ASM)))) {
5559 fprintf(file, "\n%s:\n", si_get_shader_name(shader, processor));
5560
5561 if (shader->prolog)
5562 si_shader_dump_disassembly(&shader->prolog->binary,
5563 debug, "prolog", file);
5564 if (shader->previous_stage)
5565 si_shader_dump_disassembly(&shader->previous_stage->binary,
5566 debug, "previous stage", file);
5567 if (shader->prolog2)
5568 si_shader_dump_disassembly(&shader->prolog2->binary,
5569 debug, "prolog2", file);
5570
5571 si_shader_dump_disassembly(&shader->binary, debug, "main", file);
5572
5573 if (shader->epilog)
5574 si_shader_dump_disassembly(&shader->epilog->binary,
5575 debug, "epilog", file);
5576 fprintf(file, "\n");
5577 }
5578
5579 si_shader_dump_stats(sscreen, shader, processor, file,
5580 check_debug_option);
5581 }
5582
5583 static int si_compile_llvm(struct si_screen *sscreen,
5584 struct ac_shader_binary *binary,
5585 struct si_shader_config *conf,
5586 struct ac_llvm_compiler *compiler,
5587 LLVMModuleRef mod,
5588 struct pipe_debug_callback *debug,
5589 unsigned processor,
5590 const char *name,
5591 bool less_optimized)
5592 {
5593 int r = 0;
5594 unsigned count = p_atomic_inc_return(&sscreen->num_compilations);
5595
5596 if (si_can_dump_shader(sscreen, processor)) {
5597 fprintf(stderr, "radeonsi: Compiling shader %d\n", count);
5598
5599 if (!(sscreen->debug_flags & (DBG(NO_IR) | DBG(PREOPT_IR)))) {
5600 fprintf(stderr, "%s LLVM IR:\n\n", name);
5601 ac_dump_module(mod);
5602 fprintf(stderr, "\n");
5603 }
5604 }
5605
5606 if (sscreen->record_llvm_ir) {
5607 char *ir = LLVMPrintModuleToString(mod);
5608 binary->llvm_ir_string = strdup(ir);
5609 LLVMDisposeMessage(ir);
5610 }
5611
5612 if (!si_replace_shader(count, binary)) {
5613 r = si_llvm_compile(mod, binary, compiler, debug,
5614 less_optimized);
5615 if (r)
5616 return r;
5617 }
5618
5619 si_shader_binary_read_config(binary, conf, 0);
5620
5621 /* Enable 64-bit and 16-bit denormals, because there is no performance
5622 * cost.
5623 *
5624 * If denormals are enabled, all floating-point output modifiers are
5625 * ignored.
5626 *
5627 * Don't enable denormals for 32-bit floats, because:
5628 * - Floating-point output modifiers would be ignored by the hw.
5629 * - Some opcodes don't support denormals, such as v_mad_f32. We would
5630 * have to stop using those.
5631 * - SI & CI would be very slow.
5632 */
5633 conf->float_mode |= V_00B028_FP_64_DENORMS;
5634
5635 FREE(binary->config);
5636 FREE(binary->global_symbol_offsets);
5637 binary->config = NULL;
5638 binary->global_symbol_offsets = NULL;
5639
5640 /* Some shaders can't have rodata because their binaries can be
5641 * concatenated.
5642 */
5643 if (binary->rodata_size &&
5644 (processor == PIPE_SHADER_VERTEX ||
5645 processor == PIPE_SHADER_TESS_CTRL ||
5646 processor == PIPE_SHADER_TESS_EVAL ||
5647 processor == PIPE_SHADER_FRAGMENT)) {
5648 fprintf(stderr, "radeonsi: The shader can't have rodata.");
5649 return -EINVAL;
5650 }
5651
5652 return r;
5653 }
5654
5655 static void si_llvm_build_ret(struct si_shader_context *ctx, LLVMValueRef ret)
5656 {
5657 if (LLVMGetTypeKind(LLVMTypeOf(ret)) == LLVMVoidTypeKind)
5658 LLVMBuildRetVoid(ctx->ac.builder);
5659 else
5660 LLVMBuildRet(ctx->ac.builder, ret);
5661 }
5662
5663 /* Generate code for the hardware VS shader stage to go with a geometry shader */
5664 struct si_shader *
5665 si_generate_gs_copy_shader(struct si_screen *sscreen,
5666 struct ac_llvm_compiler *compiler,
5667 struct si_shader_selector *gs_selector,
5668 struct pipe_debug_callback *debug)
5669 {
5670 struct si_shader_context ctx;
5671 struct si_shader *shader;
5672 LLVMBuilderRef builder;
5673 struct si_shader_output_values outputs[SI_MAX_VS_OUTPUTS];
5674 struct tgsi_shader_info *gsinfo = &gs_selector->info;
5675 int i, r;
5676
5677
5678 shader = CALLOC_STRUCT(si_shader);
5679 if (!shader)
5680 return NULL;
5681
5682 /* We can leave the fence as permanently signaled because the GS copy
5683 * shader only becomes visible globally after it has been compiled. */
5684 util_queue_fence_init(&shader->ready);
5685
5686 shader->selector = gs_selector;
5687 shader->is_gs_copy_shader = true;
5688
5689 si_init_shader_ctx(&ctx, sscreen, compiler);
5690 ctx.shader = shader;
5691 ctx.type = PIPE_SHADER_VERTEX;
5692
5693 builder = ctx.ac.builder;
5694
5695 create_function(&ctx);
5696 preload_ring_buffers(&ctx);
5697
5698 LLVMValueRef voffset =
5699 LLVMBuildMul(ctx.ac.builder, ctx.abi.vertex_id,
5700 LLVMConstInt(ctx.i32, 4, 0), "");
5701
5702 /* Fetch the vertex stream ID.*/
5703 LLVMValueRef stream_id;
5704
5705 if (gs_selector->so.num_outputs)
5706 stream_id = si_unpack_param(&ctx, ctx.param_streamout_config, 24, 2);
5707 else
5708 stream_id = ctx.i32_0;
5709
5710 /* Fill in output information. */
5711 for (i = 0; i < gsinfo->num_outputs; ++i) {
5712 outputs[i].semantic_name = gsinfo->output_semantic_name[i];
5713 outputs[i].semantic_index = gsinfo->output_semantic_index[i];
5714
5715 for (int chan = 0; chan < 4; chan++) {
5716 outputs[i].vertex_stream[chan] =
5717 (gsinfo->output_streams[i] >> (2 * chan)) & 3;
5718 }
5719 }
5720
5721 LLVMBasicBlockRef end_bb;
5722 LLVMValueRef switch_inst;
5723
5724 end_bb = LLVMAppendBasicBlockInContext(ctx.ac.context, ctx.main_fn, "end");
5725 switch_inst = LLVMBuildSwitch(builder, stream_id, end_bb, 4);
5726
5727 for (int stream = 0; stream < 4; stream++) {
5728 LLVMBasicBlockRef bb;
5729 unsigned offset;
5730
5731 if (!gsinfo->num_stream_output_components[stream])
5732 continue;
5733
5734 if (stream > 0 && !gs_selector->so.num_outputs)
5735 continue;
5736
5737 bb = LLVMInsertBasicBlockInContext(ctx.ac.context, end_bb, "out");
5738 LLVMAddCase(switch_inst, LLVMConstInt(ctx.i32, stream, 0), bb);
5739 LLVMPositionBuilderAtEnd(builder, bb);
5740
5741 /* Fetch vertex data from GSVS ring */
5742 offset = 0;
5743 for (i = 0; i < gsinfo->num_outputs; ++i) {
5744 for (unsigned chan = 0; chan < 4; chan++) {
5745 if (!(gsinfo->output_usagemask[i] & (1 << chan)) ||
5746 outputs[i].vertex_stream[chan] != stream) {
5747 outputs[i].values[chan] = LLVMGetUndef(ctx.f32);
5748 continue;
5749 }
5750
5751 LLVMValueRef soffset = LLVMConstInt(ctx.i32,
5752 offset * gs_selector->gs_max_out_vertices * 16 * 4, 0);
5753 offset++;
5754
5755 outputs[i].values[chan] =
5756 ac_build_buffer_load(&ctx.ac,
5757 ctx.gsvs_ring[0], 1,
5758 ctx.i32_0, voffset,
5759 soffset, 0, 1, 1,
5760 true, false);
5761 }
5762 }
5763
5764 /* Streamout and exports. */
5765 if (gs_selector->so.num_outputs) {
5766 si_llvm_emit_streamout(&ctx, outputs,
5767 gsinfo->num_outputs,
5768 stream);
5769 }
5770
5771 if (stream == 0) {
5772 /* Vertex color clamping.
5773 *
5774 * This uses a state constant loaded in a user data SGPR and
5775 * an IF statement is added that clamps all colors if the constant
5776 * is true.
5777 */
5778 struct lp_build_if_state if_ctx;
5779 LLVMValueRef v[2], cond = NULL;
5780 LLVMBasicBlockRef blocks[2];
5781
5782 for (unsigned i = 0; i < gsinfo->num_outputs; i++) {
5783 if (gsinfo->output_semantic_name[i] != TGSI_SEMANTIC_COLOR &&
5784 gsinfo->output_semantic_name[i] != TGSI_SEMANTIC_BCOLOR)
5785 continue;
5786
5787 /* We've found a color. */
5788 if (!cond) {
5789 /* The state is in the first bit of the user SGPR. */
5790 cond = LLVMGetParam(ctx.main_fn,
5791 ctx.param_vs_state_bits);
5792 cond = LLVMBuildTrunc(ctx.ac.builder, cond,
5793 ctx.i1, "");
5794 lp_build_if(&if_ctx, &ctx.gallivm, cond);
5795 /* Remember blocks for Phi. */
5796 blocks[0] = if_ctx.true_block;
5797 blocks[1] = if_ctx.entry_block;
5798 }
5799
5800 for (unsigned j = 0; j < 4; j++) {
5801 /* Insert clamp into the true block. */
5802 v[0] = ac_build_clamp(&ctx.ac, outputs[i].values[j]);
5803 v[1] = outputs[i].values[j];
5804
5805 /* Insert Phi into the endif block. */
5806 LLVMPositionBuilderAtEnd(ctx.ac.builder, if_ctx.merge_block);
5807 outputs[i].values[j] = ac_build_phi(&ctx.ac, ctx.f32, 2, v, blocks);
5808 LLVMPositionBuilderAtEnd(ctx.ac.builder, if_ctx.true_block);
5809 }
5810 }
5811 if (cond)
5812 lp_build_endif(&if_ctx);
5813
5814 si_llvm_export_vs(&ctx, outputs, gsinfo->num_outputs);
5815 }
5816
5817 LLVMBuildBr(builder, end_bb);
5818 }
5819
5820 LLVMPositionBuilderAtEnd(builder, end_bb);
5821
5822 LLVMBuildRetVoid(ctx.ac.builder);
5823
5824 ctx.type = PIPE_SHADER_GEOMETRY; /* override for shader dumping */
5825 si_llvm_optimize_module(&ctx);
5826
5827 r = si_compile_llvm(sscreen, &ctx.shader->binary,
5828 &ctx.shader->config, ctx.compiler,
5829 ctx.ac.module,
5830 debug, PIPE_SHADER_GEOMETRY,
5831 "GS Copy Shader", false);
5832 if (!r) {
5833 if (si_can_dump_shader(sscreen, PIPE_SHADER_GEOMETRY))
5834 fprintf(stderr, "GS Copy Shader:\n");
5835 si_shader_dump(sscreen, ctx.shader, debug,
5836 PIPE_SHADER_GEOMETRY, stderr, true);
5837 r = si_shader_binary_upload(sscreen, ctx.shader);
5838 }
5839
5840 si_llvm_dispose(&ctx);
5841
5842 if (r != 0) {
5843 FREE(shader);
5844 shader = NULL;
5845 }
5846 return shader;
5847 }
5848
5849 static void si_dump_shader_key_vs(const struct si_shader_key *key,
5850 const struct si_vs_prolog_bits *prolog,
5851 const char *prefix, FILE *f)
5852 {
5853 fprintf(f, " %s.instance_divisor_is_one = %u\n",
5854 prefix, prolog->instance_divisor_is_one);
5855 fprintf(f, " %s.instance_divisor_is_fetched = %u\n",
5856 prefix, prolog->instance_divisor_is_fetched);
5857 fprintf(f, " %s.ls_vgpr_fix = %u\n",
5858 prefix, prolog->ls_vgpr_fix);
5859
5860 fprintf(f, " mono.vs.fix_fetch = {");
5861 for (int i = 0; i < SI_MAX_ATTRIBS; i++)
5862 fprintf(f, !i ? "%u" : ", %u", key->mono.vs_fix_fetch[i]);
5863 fprintf(f, "}\n");
5864 }
5865
5866 static void si_dump_shader_key(unsigned processor, const struct si_shader *shader,
5867 FILE *f)
5868 {
5869 const struct si_shader_key *key = &shader->key;
5870
5871 fprintf(f, "SHADER KEY\n");
5872
5873 switch (processor) {
5874 case PIPE_SHADER_VERTEX:
5875 si_dump_shader_key_vs(key, &key->part.vs.prolog,
5876 "part.vs.prolog", f);
5877 fprintf(f, " as_es = %u\n", key->as_es);
5878 fprintf(f, " as_ls = %u\n", key->as_ls);
5879 fprintf(f, " mono.u.vs_export_prim_id = %u\n",
5880 key->mono.u.vs_export_prim_id);
5881 break;
5882
5883 case PIPE_SHADER_TESS_CTRL:
5884 if (shader->selector->screen->info.chip_class >= GFX9) {
5885 si_dump_shader_key_vs(key, &key->part.tcs.ls_prolog,
5886 "part.tcs.ls_prolog", f);
5887 }
5888 fprintf(f, " part.tcs.epilog.prim_mode = %u\n", key->part.tcs.epilog.prim_mode);
5889 fprintf(f, " mono.u.ff_tcs_inputs_to_copy = 0x%"PRIx64"\n", key->mono.u.ff_tcs_inputs_to_copy);
5890 break;
5891
5892 case PIPE_SHADER_TESS_EVAL:
5893 fprintf(f, " as_es = %u\n", key->as_es);
5894 fprintf(f, " mono.u.vs_export_prim_id = %u\n",
5895 key->mono.u.vs_export_prim_id);
5896 break;
5897
5898 case PIPE_SHADER_GEOMETRY:
5899 if (shader->is_gs_copy_shader)
5900 break;
5901
5902 if (shader->selector->screen->info.chip_class >= GFX9 &&
5903 key->part.gs.es->type == PIPE_SHADER_VERTEX) {
5904 si_dump_shader_key_vs(key, &key->part.gs.vs_prolog,
5905 "part.gs.vs_prolog", f);
5906 }
5907 fprintf(f, " part.gs.prolog.tri_strip_adj_fix = %u\n", key->part.gs.prolog.tri_strip_adj_fix);
5908 break;
5909
5910 case PIPE_SHADER_COMPUTE:
5911 break;
5912
5913 case PIPE_SHADER_FRAGMENT:
5914 fprintf(f, " part.ps.prolog.color_two_side = %u\n", key->part.ps.prolog.color_two_side);
5915 fprintf(f, " part.ps.prolog.flatshade_colors = %u\n", key->part.ps.prolog.flatshade_colors);
5916 fprintf(f, " part.ps.prolog.poly_stipple = %u\n", key->part.ps.prolog.poly_stipple);
5917 fprintf(f, " part.ps.prolog.force_persp_sample_interp = %u\n", key->part.ps.prolog.force_persp_sample_interp);
5918 fprintf(f, " part.ps.prolog.force_linear_sample_interp = %u\n", key->part.ps.prolog.force_linear_sample_interp);
5919 fprintf(f, " part.ps.prolog.force_persp_center_interp = %u\n", key->part.ps.prolog.force_persp_center_interp);
5920 fprintf(f, " part.ps.prolog.force_linear_center_interp = %u\n", key->part.ps.prolog.force_linear_center_interp);
5921 fprintf(f, " part.ps.prolog.bc_optimize_for_persp = %u\n", key->part.ps.prolog.bc_optimize_for_persp);
5922 fprintf(f, " part.ps.prolog.bc_optimize_for_linear = %u\n", key->part.ps.prolog.bc_optimize_for_linear);
5923 fprintf(f, " part.ps.epilog.spi_shader_col_format = 0x%x\n", key->part.ps.epilog.spi_shader_col_format);
5924 fprintf(f, " part.ps.epilog.color_is_int8 = 0x%X\n", key->part.ps.epilog.color_is_int8);
5925 fprintf(f, " part.ps.epilog.color_is_int10 = 0x%X\n", key->part.ps.epilog.color_is_int10);
5926 fprintf(f, " part.ps.epilog.last_cbuf = %u\n", key->part.ps.epilog.last_cbuf);
5927 fprintf(f, " part.ps.epilog.alpha_func = %u\n", key->part.ps.epilog.alpha_func);
5928 fprintf(f, " part.ps.epilog.alpha_to_one = %u\n", key->part.ps.epilog.alpha_to_one);
5929 fprintf(f, " part.ps.epilog.poly_line_smoothing = %u\n", key->part.ps.epilog.poly_line_smoothing);
5930 fprintf(f, " part.ps.epilog.clamp_color = %u\n", key->part.ps.epilog.clamp_color);
5931 break;
5932
5933 default:
5934 assert(0);
5935 }
5936
5937 if ((processor == PIPE_SHADER_GEOMETRY ||
5938 processor == PIPE_SHADER_TESS_EVAL ||
5939 processor == PIPE_SHADER_VERTEX) &&
5940 !key->as_es && !key->as_ls) {
5941 fprintf(f, " opt.kill_outputs = 0x%"PRIx64"\n", key->opt.kill_outputs);
5942 fprintf(f, " opt.clip_disable = %u\n", key->opt.clip_disable);
5943 }
5944 }
5945
5946 static void si_init_shader_ctx(struct si_shader_context *ctx,
5947 struct si_screen *sscreen,
5948 struct ac_llvm_compiler *compiler)
5949 {
5950 struct lp_build_tgsi_context *bld_base;
5951
5952 si_llvm_context_init(ctx, sscreen, compiler);
5953
5954 bld_base = &ctx->bld_base;
5955 bld_base->emit_fetch_funcs[TGSI_FILE_CONSTANT] = fetch_constant;
5956
5957 bld_base->op_actions[TGSI_OPCODE_INTERP_CENTROID].emit = build_interp_intrinsic;
5958 bld_base->op_actions[TGSI_OPCODE_INTERP_SAMPLE].emit = build_interp_intrinsic;
5959 bld_base->op_actions[TGSI_OPCODE_INTERP_OFFSET].emit = build_interp_intrinsic;
5960
5961 bld_base->op_actions[TGSI_OPCODE_MEMBAR].emit = membar_emit;
5962
5963 bld_base->op_actions[TGSI_OPCODE_CLOCK].emit = clock_emit;
5964
5965 bld_base->op_actions[TGSI_OPCODE_DDX].emit = si_llvm_emit_ddxy;
5966 bld_base->op_actions[TGSI_OPCODE_DDY].emit = si_llvm_emit_ddxy;
5967 bld_base->op_actions[TGSI_OPCODE_DDX_FINE].emit = si_llvm_emit_ddxy;
5968 bld_base->op_actions[TGSI_OPCODE_DDY_FINE].emit = si_llvm_emit_ddxy;
5969
5970 bld_base->op_actions[TGSI_OPCODE_VOTE_ALL].emit = vote_all_emit;
5971 bld_base->op_actions[TGSI_OPCODE_VOTE_ANY].emit = vote_any_emit;
5972 bld_base->op_actions[TGSI_OPCODE_VOTE_EQ].emit = vote_eq_emit;
5973 bld_base->op_actions[TGSI_OPCODE_BALLOT].emit = ballot_emit;
5974 bld_base->op_actions[TGSI_OPCODE_READ_FIRST].intr_name = "llvm.amdgcn.readfirstlane";
5975 bld_base->op_actions[TGSI_OPCODE_READ_FIRST].emit = read_lane_emit;
5976 bld_base->op_actions[TGSI_OPCODE_READ_INVOC].intr_name = "llvm.amdgcn.readlane";
5977 bld_base->op_actions[TGSI_OPCODE_READ_INVOC].emit = read_lane_emit;
5978
5979 bld_base->op_actions[TGSI_OPCODE_EMIT].emit = si_tgsi_emit_vertex;
5980 bld_base->op_actions[TGSI_OPCODE_ENDPRIM].emit = si_tgsi_emit_primitive;
5981 bld_base->op_actions[TGSI_OPCODE_BARRIER].emit = si_llvm_emit_barrier;
5982 }
5983
5984 static void si_optimize_vs_outputs(struct si_shader_context *ctx)
5985 {
5986 struct si_shader *shader = ctx->shader;
5987 struct tgsi_shader_info *info = &shader->selector->info;
5988
5989 if ((ctx->type != PIPE_SHADER_VERTEX &&
5990 ctx->type != PIPE_SHADER_TESS_EVAL) ||
5991 shader->key.as_ls ||
5992 shader->key.as_es)
5993 return;
5994
5995 ac_optimize_vs_outputs(&ctx->ac,
5996 ctx->main_fn,
5997 shader->info.vs_output_param_offset,
5998 info->num_outputs,
5999 &shader->info.nr_param_exports);
6000 }
6001
6002 static void si_init_exec_from_input(struct si_shader_context *ctx,
6003 unsigned param, unsigned bitoffset)
6004 {
6005 LLVMValueRef args[] = {
6006 LLVMGetParam(ctx->main_fn, param),
6007 LLVMConstInt(ctx->i32, bitoffset, 0),
6008 };
6009 ac_build_intrinsic(&ctx->ac,
6010 "llvm.amdgcn.init.exec.from.input",
6011 ctx->voidt, args, 2, AC_FUNC_ATTR_CONVERGENT);
6012 }
6013
6014 static bool si_vs_needs_prolog(const struct si_shader_selector *sel,
6015 const struct si_vs_prolog_bits *key)
6016 {
6017 /* VGPR initialization fixup for Vega10 and Raven is always done in the
6018 * VS prolog. */
6019 return sel->vs_needs_prolog || key->ls_vgpr_fix;
6020 }
6021
6022 static bool si_compile_tgsi_main(struct si_shader_context *ctx)
6023 {
6024 struct si_shader *shader = ctx->shader;
6025 struct si_shader_selector *sel = shader->selector;
6026 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
6027
6028 // TODO clean all this up!
6029 switch (ctx->type) {
6030 case PIPE_SHADER_VERTEX:
6031 ctx->load_input = declare_input_vs;
6032 if (shader->key.as_ls)
6033 ctx->abi.emit_outputs = si_llvm_emit_ls_epilogue;
6034 else if (shader->key.as_es)
6035 ctx->abi.emit_outputs = si_llvm_emit_es_epilogue;
6036 else
6037 ctx->abi.emit_outputs = si_llvm_emit_vs_epilogue;
6038 bld_base->emit_epilogue = si_tgsi_emit_epilogue;
6039 ctx->abi.load_base_vertex = get_base_vertex;
6040 break;
6041 case PIPE_SHADER_TESS_CTRL:
6042 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_tcs;
6043 ctx->abi.load_tess_varyings = si_nir_load_tcs_varyings;
6044 bld_base->emit_fetch_funcs[TGSI_FILE_OUTPUT] = fetch_output_tcs;
6045 bld_base->emit_store = store_output_tcs;
6046 ctx->abi.store_tcs_outputs = si_nir_store_output_tcs;
6047 ctx->abi.emit_outputs = si_llvm_emit_tcs_epilogue;
6048 ctx->abi.load_patch_vertices_in = si_load_patch_vertices_in;
6049 bld_base->emit_epilogue = si_tgsi_emit_epilogue;
6050 break;
6051 case PIPE_SHADER_TESS_EVAL:
6052 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_tes;
6053 ctx->abi.load_tess_varyings = si_nir_load_input_tes;
6054 ctx->abi.load_tess_coord = si_load_tess_coord;
6055 ctx->abi.load_tess_level = si_load_tess_level;
6056 ctx->abi.load_patch_vertices_in = si_load_patch_vertices_in;
6057 if (shader->key.as_es)
6058 ctx->abi.emit_outputs = si_llvm_emit_es_epilogue;
6059 else
6060 ctx->abi.emit_outputs = si_llvm_emit_vs_epilogue;
6061 bld_base->emit_epilogue = si_tgsi_emit_epilogue;
6062 break;
6063 case PIPE_SHADER_GEOMETRY:
6064 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_gs;
6065 ctx->abi.load_inputs = si_nir_load_input_gs;
6066 ctx->abi.emit_vertex = si_llvm_emit_vertex;
6067 ctx->abi.emit_primitive = si_llvm_emit_primitive;
6068 ctx->abi.emit_outputs = si_llvm_emit_gs_epilogue;
6069 bld_base->emit_epilogue = si_tgsi_emit_gs_epilogue;
6070 break;
6071 case PIPE_SHADER_FRAGMENT:
6072 ctx->load_input = declare_input_fs;
6073 ctx->abi.emit_outputs = si_llvm_return_fs_outputs;
6074 bld_base->emit_epilogue = si_tgsi_emit_epilogue;
6075 ctx->abi.lookup_interp_param = si_nir_lookup_interp_param;
6076 ctx->abi.load_sample_position = load_sample_position;
6077 ctx->abi.load_sample_mask_in = load_sample_mask_in;
6078 ctx->abi.emit_kill = si_llvm_emit_kill;
6079 break;
6080 case PIPE_SHADER_COMPUTE:
6081 ctx->abi.load_local_group_size = get_block_size;
6082 break;
6083 default:
6084 assert(!"Unsupported shader type");
6085 return false;
6086 }
6087
6088 ctx->abi.load_ubo = load_ubo;
6089 ctx->abi.load_ssbo = load_ssbo;
6090
6091 create_function(ctx);
6092 preload_ring_buffers(ctx);
6093
6094 /* For GFX9 merged shaders:
6095 * - Set EXEC for the first shader. If the prolog is present, set
6096 * EXEC there instead.
6097 * - Add a barrier before the second shader.
6098 * - In the second shader, reset EXEC to ~0 and wrap the main part in
6099 * an if-statement. This is required for correctness in geometry
6100 * shaders, to ensure that empty GS waves do not send GS_EMIT and
6101 * GS_CUT messages.
6102 *
6103 * For monolithic merged shaders, the first shader is wrapped in an
6104 * if-block together with its prolog in si_build_wrapper_function.
6105 */
6106 if (ctx->screen->info.chip_class >= GFX9) {
6107 if (!shader->is_monolithic &&
6108 sel->info.num_instructions > 1 && /* not empty shader */
6109 (shader->key.as_es || shader->key.as_ls) &&
6110 (ctx->type == PIPE_SHADER_TESS_EVAL ||
6111 (ctx->type == PIPE_SHADER_VERTEX &&
6112 !si_vs_needs_prolog(sel, &shader->key.part.vs.prolog)))) {
6113 si_init_exec_from_input(ctx,
6114 ctx->param_merged_wave_info, 0);
6115 } else if (ctx->type == PIPE_SHADER_TESS_CTRL ||
6116 ctx->type == PIPE_SHADER_GEOMETRY) {
6117 if (!shader->is_monolithic)
6118 ac_init_exec_full_mask(&ctx->ac);
6119
6120 LLVMValueRef num_threads = si_unpack_param(ctx, ctx->param_merged_wave_info, 8, 8);
6121 LLVMValueRef ena =
6122 LLVMBuildICmp(ctx->ac.builder, LLVMIntULT,
6123 ac_get_thread_id(&ctx->ac), num_threads, "");
6124 lp_build_if(&ctx->merged_wrap_if_state, &ctx->gallivm, ena);
6125
6126 /* The barrier must execute for all shaders in a
6127 * threadgroup.
6128 *
6129 * Execute the barrier inside the conditional block,
6130 * so that empty waves can jump directly to s_endpgm,
6131 * which will also signal the barrier.
6132 *
6133 * If the shader is TCS and the TCS epilog is present
6134 * and contains a barrier, it will wait there and then
6135 * reach s_endpgm.
6136 */
6137 si_llvm_emit_barrier(NULL, bld_base, NULL);
6138 }
6139 }
6140
6141 if (ctx->type == PIPE_SHADER_TESS_CTRL &&
6142 sel->tcs_info.tessfactors_are_def_in_all_invocs) {
6143 for (unsigned i = 0; i < 6; i++) {
6144 ctx->invoc0_tess_factors[i] =
6145 ac_build_alloca_undef(&ctx->ac, ctx->i32, "");
6146 }
6147 }
6148
6149 if (ctx->type == PIPE_SHADER_GEOMETRY) {
6150 int i;
6151 for (i = 0; i < 4; i++) {
6152 ctx->gs_next_vertex[i] =
6153 ac_build_alloca(&ctx->ac, ctx->i32, "");
6154 }
6155 }
6156
6157 if (sel->force_correct_derivs_after_kill) {
6158 ctx->postponed_kill = ac_build_alloca_undef(&ctx->ac, ctx->i1, "");
6159 /* true = don't kill. */
6160 LLVMBuildStore(ctx->ac.builder, ctx->i1true,
6161 ctx->postponed_kill);
6162 }
6163
6164 if (sel->tokens) {
6165 if (!lp_build_tgsi_llvm(bld_base, sel->tokens)) {
6166 fprintf(stderr, "Failed to translate shader from TGSI to LLVM\n");
6167 return false;
6168 }
6169 } else {
6170 if (!si_nir_build_llvm(ctx, sel->nir)) {
6171 fprintf(stderr, "Failed to translate shader from NIR to LLVM\n");
6172 return false;
6173 }
6174 }
6175
6176 si_llvm_build_ret(ctx, ctx->return_value);
6177 return true;
6178 }
6179
6180 /**
6181 * Compute the VS prolog key, which contains all the information needed to
6182 * build the VS prolog function, and set shader->info bits where needed.
6183 *
6184 * \param info Shader info of the vertex shader.
6185 * \param num_input_sgprs Number of input SGPRs for the vertex shader.
6186 * \param prolog_key Key of the VS prolog
6187 * \param shader_out The vertex shader, or the next shader if merging LS+HS or ES+GS.
6188 * \param key Output shader part key.
6189 */
6190 static void si_get_vs_prolog_key(const struct tgsi_shader_info *info,
6191 unsigned num_input_sgprs,
6192 const struct si_vs_prolog_bits *prolog_key,
6193 struct si_shader *shader_out,
6194 union si_shader_part_key *key)
6195 {
6196 memset(key, 0, sizeof(*key));
6197 key->vs_prolog.states = *prolog_key;
6198 key->vs_prolog.num_input_sgprs = num_input_sgprs;
6199 key->vs_prolog.last_input = MAX2(1, info->num_inputs) - 1;
6200 key->vs_prolog.as_ls = shader_out->key.as_ls;
6201 key->vs_prolog.as_es = shader_out->key.as_es;
6202
6203 if (shader_out->selector->type == PIPE_SHADER_TESS_CTRL) {
6204 key->vs_prolog.as_ls = 1;
6205 key->vs_prolog.num_merged_next_stage_vgprs = 2;
6206 } else if (shader_out->selector->type == PIPE_SHADER_GEOMETRY) {
6207 key->vs_prolog.as_es = 1;
6208 key->vs_prolog.num_merged_next_stage_vgprs = 5;
6209 }
6210
6211 /* Enable loading the InstanceID VGPR. */
6212 uint16_t input_mask = u_bit_consecutive(0, info->num_inputs);
6213
6214 if ((key->vs_prolog.states.instance_divisor_is_one |
6215 key->vs_prolog.states.instance_divisor_is_fetched) & input_mask)
6216 shader_out->info.uses_instanceid = true;
6217 }
6218
6219 /**
6220 * Compute the PS prolog key, which contains all the information needed to
6221 * build the PS prolog function, and set related bits in shader->config.
6222 */
6223 static void si_get_ps_prolog_key(struct si_shader *shader,
6224 union si_shader_part_key *key,
6225 bool separate_prolog)
6226 {
6227 struct tgsi_shader_info *info = &shader->selector->info;
6228
6229 memset(key, 0, sizeof(*key));
6230 key->ps_prolog.states = shader->key.part.ps.prolog;
6231 key->ps_prolog.colors_read = info->colors_read;
6232 key->ps_prolog.num_input_sgprs = shader->info.num_input_sgprs;
6233 key->ps_prolog.num_input_vgprs = shader->info.num_input_vgprs;
6234 key->ps_prolog.wqm = info->uses_derivatives &&
6235 (key->ps_prolog.colors_read ||
6236 key->ps_prolog.states.force_persp_sample_interp ||
6237 key->ps_prolog.states.force_linear_sample_interp ||
6238 key->ps_prolog.states.force_persp_center_interp ||
6239 key->ps_prolog.states.force_linear_center_interp ||
6240 key->ps_prolog.states.bc_optimize_for_persp ||
6241 key->ps_prolog.states.bc_optimize_for_linear);
6242 key->ps_prolog.ancillary_vgpr_index = shader->info.ancillary_vgpr_index;
6243
6244 if (info->colors_read) {
6245 unsigned *color = shader->selector->color_attr_index;
6246
6247 if (shader->key.part.ps.prolog.color_two_side) {
6248 /* BCOLORs are stored after the last input. */
6249 key->ps_prolog.num_interp_inputs = info->num_inputs;
6250 key->ps_prolog.face_vgpr_index = shader->info.face_vgpr_index;
6251 shader->config.spi_ps_input_ena |= S_0286CC_FRONT_FACE_ENA(1);
6252 }
6253
6254 for (unsigned i = 0; i < 2; i++) {
6255 unsigned interp = info->input_interpolate[color[i]];
6256 unsigned location = info->input_interpolate_loc[color[i]];
6257
6258 if (!(info->colors_read & (0xf << i*4)))
6259 continue;
6260
6261 key->ps_prolog.color_attr_index[i] = color[i];
6262
6263 if (shader->key.part.ps.prolog.flatshade_colors &&
6264 interp == TGSI_INTERPOLATE_COLOR)
6265 interp = TGSI_INTERPOLATE_CONSTANT;
6266
6267 switch (interp) {
6268 case TGSI_INTERPOLATE_CONSTANT:
6269 key->ps_prolog.color_interp_vgpr_index[i] = -1;
6270 break;
6271 case TGSI_INTERPOLATE_PERSPECTIVE:
6272 case TGSI_INTERPOLATE_COLOR:
6273 /* Force the interpolation location for colors here. */
6274 if (shader->key.part.ps.prolog.force_persp_sample_interp)
6275 location = TGSI_INTERPOLATE_LOC_SAMPLE;
6276 if (shader->key.part.ps.prolog.force_persp_center_interp)
6277 location = TGSI_INTERPOLATE_LOC_CENTER;
6278
6279 switch (location) {
6280 case TGSI_INTERPOLATE_LOC_SAMPLE:
6281 key->ps_prolog.color_interp_vgpr_index[i] = 0;
6282 shader->config.spi_ps_input_ena |=
6283 S_0286CC_PERSP_SAMPLE_ENA(1);
6284 break;
6285 case TGSI_INTERPOLATE_LOC_CENTER:
6286 key->ps_prolog.color_interp_vgpr_index[i] = 2;
6287 shader->config.spi_ps_input_ena |=
6288 S_0286CC_PERSP_CENTER_ENA(1);
6289 break;
6290 case TGSI_INTERPOLATE_LOC_CENTROID:
6291 key->ps_prolog.color_interp_vgpr_index[i] = 4;
6292 shader->config.spi_ps_input_ena |=
6293 S_0286CC_PERSP_CENTROID_ENA(1);
6294 break;
6295 default:
6296 assert(0);
6297 }
6298 break;
6299 case TGSI_INTERPOLATE_LINEAR:
6300 /* Force the interpolation location for colors here. */
6301 if (shader->key.part.ps.prolog.force_linear_sample_interp)
6302 location = TGSI_INTERPOLATE_LOC_SAMPLE;
6303 if (shader->key.part.ps.prolog.force_linear_center_interp)
6304 location = TGSI_INTERPOLATE_LOC_CENTER;
6305
6306 /* The VGPR assignment for non-monolithic shaders
6307 * works because InitialPSInputAddr is set on the
6308 * main shader and PERSP_PULL_MODEL is never used.
6309 */
6310 switch (location) {
6311 case TGSI_INTERPOLATE_LOC_SAMPLE:
6312 key->ps_prolog.color_interp_vgpr_index[i] =
6313 separate_prolog ? 6 : 9;
6314 shader->config.spi_ps_input_ena |=
6315 S_0286CC_LINEAR_SAMPLE_ENA(1);
6316 break;
6317 case TGSI_INTERPOLATE_LOC_CENTER:
6318 key->ps_prolog.color_interp_vgpr_index[i] =
6319 separate_prolog ? 8 : 11;
6320 shader->config.spi_ps_input_ena |=
6321 S_0286CC_LINEAR_CENTER_ENA(1);
6322 break;
6323 case TGSI_INTERPOLATE_LOC_CENTROID:
6324 key->ps_prolog.color_interp_vgpr_index[i] =
6325 separate_prolog ? 10 : 13;
6326 shader->config.spi_ps_input_ena |=
6327 S_0286CC_LINEAR_CENTROID_ENA(1);
6328 break;
6329 default:
6330 assert(0);
6331 }
6332 break;
6333 default:
6334 assert(0);
6335 }
6336 }
6337 }
6338 }
6339
6340 /**
6341 * Check whether a PS prolog is required based on the key.
6342 */
6343 static bool si_need_ps_prolog(const union si_shader_part_key *key)
6344 {
6345 return key->ps_prolog.colors_read ||
6346 key->ps_prolog.states.force_persp_sample_interp ||
6347 key->ps_prolog.states.force_linear_sample_interp ||
6348 key->ps_prolog.states.force_persp_center_interp ||
6349 key->ps_prolog.states.force_linear_center_interp ||
6350 key->ps_prolog.states.bc_optimize_for_persp ||
6351 key->ps_prolog.states.bc_optimize_for_linear ||
6352 key->ps_prolog.states.poly_stipple ||
6353 key->ps_prolog.states.samplemask_log_ps_iter;
6354 }
6355
6356 /**
6357 * Compute the PS epilog key, which contains all the information needed to
6358 * build the PS epilog function.
6359 */
6360 static void si_get_ps_epilog_key(struct si_shader *shader,
6361 union si_shader_part_key *key)
6362 {
6363 struct tgsi_shader_info *info = &shader->selector->info;
6364 memset(key, 0, sizeof(*key));
6365 key->ps_epilog.colors_written = info->colors_written;
6366 key->ps_epilog.writes_z = info->writes_z;
6367 key->ps_epilog.writes_stencil = info->writes_stencil;
6368 key->ps_epilog.writes_samplemask = info->writes_samplemask;
6369 key->ps_epilog.states = shader->key.part.ps.epilog;
6370 }
6371
6372 /**
6373 * Build the GS prolog function. Rotate the input vertices for triangle strips
6374 * with adjacency.
6375 */
6376 static void si_build_gs_prolog_function(struct si_shader_context *ctx,
6377 union si_shader_part_key *key)
6378 {
6379 unsigned num_sgprs, num_vgprs;
6380 struct si_function_info fninfo;
6381 LLVMBuilderRef builder = ctx->ac.builder;
6382 LLVMTypeRef returns[48];
6383 LLVMValueRef func, ret;
6384
6385 si_init_function_info(&fninfo);
6386
6387 if (ctx->screen->info.chip_class >= GFX9) {
6388 if (key->gs_prolog.states.gfx9_prev_is_vs)
6389 num_sgprs = 8 + GFX9_VSGS_NUM_USER_SGPR;
6390 else
6391 num_sgprs = 8 + GFX9_TESGS_NUM_USER_SGPR;
6392 num_vgprs = 5; /* ES inputs are not needed by GS */
6393 } else {
6394 num_sgprs = GFX6_GS_NUM_USER_SGPR + 2;
6395 num_vgprs = 8;
6396 }
6397
6398 for (unsigned i = 0; i < num_sgprs; ++i) {
6399 add_arg(&fninfo, ARG_SGPR, ctx->i32);
6400 returns[i] = ctx->i32;
6401 }
6402
6403 for (unsigned i = 0; i < num_vgprs; ++i) {
6404 add_arg(&fninfo, ARG_VGPR, ctx->i32);
6405 returns[num_sgprs + i] = ctx->f32;
6406 }
6407
6408 /* Create the function. */
6409 si_create_function(ctx, "gs_prolog", returns, num_sgprs + num_vgprs,
6410 &fninfo, 0);
6411 func = ctx->main_fn;
6412
6413 /* Set the full EXEC mask for the prolog, because we are only fiddling
6414 * with registers here. The main shader part will set the correct EXEC
6415 * mask.
6416 */
6417 if (ctx->screen->info.chip_class >= GFX9 && !key->gs_prolog.is_monolithic)
6418 ac_init_exec_full_mask(&ctx->ac);
6419
6420 /* Copy inputs to outputs. This should be no-op, as the registers match,
6421 * but it will prevent the compiler from overwriting them unintentionally.
6422 */
6423 ret = ctx->return_value;
6424 for (unsigned i = 0; i < num_sgprs; i++) {
6425 LLVMValueRef p = LLVMGetParam(func, i);
6426 ret = LLVMBuildInsertValue(builder, ret, p, i, "");
6427 }
6428 for (unsigned i = 0; i < num_vgprs; i++) {
6429 LLVMValueRef p = LLVMGetParam(func, num_sgprs + i);
6430 p = ac_to_float(&ctx->ac, p);
6431 ret = LLVMBuildInsertValue(builder, ret, p, num_sgprs + i, "");
6432 }
6433
6434 if (key->gs_prolog.states.tri_strip_adj_fix) {
6435 /* Remap the input vertices for every other primitive. */
6436 const unsigned gfx6_vtx_params[6] = {
6437 num_sgprs,
6438 num_sgprs + 1,
6439 num_sgprs + 3,
6440 num_sgprs + 4,
6441 num_sgprs + 5,
6442 num_sgprs + 6
6443 };
6444 const unsigned gfx9_vtx_params[3] = {
6445 num_sgprs,
6446 num_sgprs + 1,
6447 num_sgprs + 4,
6448 };
6449 LLVMValueRef vtx_in[6], vtx_out[6];
6450 LLVMValueRef prim_id, rotate;
6451
6452 if (ctx->screen->info.chip_class >= GFX9) {
6453 for (unsigned i = 0; i < 3; i++) {
6454 vtx_in[i*2] = si_unpack_param(ctx, gfx9_vtx_params[i], 0, 16);
6455 vtx_in[i*2+1] = si_unpack_param(ctx, gfx9_vtx_params[i], 16, 16);
6456 }
6457 } else {
6458 for (unsigned i = 0; i < 6; i++)
6459 vtx_in[i] = LLVMGetParam(func, gfx6_vtx_params[i]);
6460 }
6461
6462 prim_id = LLVMGetParam(func, num_sgprs + 2);
6463 rotate = LLVMBuildTrunc(builder, prim_id, ctx->i1, "");
6464
6465 for (unsigned i = 0; i < 6; ++i) {
6466 LLVMValueRef base, rotated;
6467 base = vtx_in[i];
6468 rotated = vtx_in[(i + 4) % 6];
6469 vtx_out[i] = LLVMBuildSelect(builder, rotate, rotated, base, "");
6470 }
6471
6472 if (ctx->screen->info.chip_class >= GFX9) {
6473 for (unsigned i = 0; i < 3; i++) {
6474 LLVMValueRef hi, out;
6475
6476 hi = LLVMBuildShl(builder, vtx_out[i*2+1],
6477 LLVMConstInt(ctx->i32, 16, 0), "");
6478 out = LLVMBuildOr(builder, vtx_out[i*2], hi, "");
6479 out = ac_to_float(&ctx->ac, out);
6480 ret = LLVMBuildInsertValue(builder, ret, out,
6481 gfx9_vtx_params[i], "");
6482 }
6483 } else {
6484 for (unsigned i = 0; i < 6; i++) {
6485 LLVMValueRef out;
6486
6487 out = ac_to_float(&ctx->ac, vtx_out[i]);
6488 ret = LLVMBuildInsertValue(builder, ret, out,
6489 gfx6_vtx_params[i], "");
6490 }
6491 }
6492 }
6493
6494 LLVMBuildRet(builder, ret);
6495 }
6496
6497 /**
6498 * Given a list of shader part functions, build a wrapper function that
6499 * runs them in sequence to form a monolithic shader.
6500 */
6501 static void si_build_wrapper_function(struct si_shader_context *ctx,
6502 LLVMValueRef *parts,
6503 unsigned num_parts,
6504 unsigned main_part,
6505 unsigned next_shader_first_part)
6506 {
6507 LLVMBuilderRef builder = ctx->ac.builder;
6508 /* PS epilog has one arg per color component; gfx9 merged shader
6509 * prologs need to forward 32 user SGPRs.
6510 */
6511 struct si_function_info fninfo;
6512 LLVMValueRef initial[64], out[64];
6513 LLVMTypeRef function_type;
6514 unsigned num_first_params;
6515 unsigned num_out, initial_num_out;
6516 MAYBE_UNUSED unsigned num_out_sgpr; /* used in debug checks */
6517 MAYBE_UNUSED unsigned initial_num_out_sgpr; /* used in debug checks */
6518 unsigned num_sgprs, num_vgprs;
6519 unsigned gprs;
6520 struct lp_build_if_state if_state;
6521
6522 si_init_function_info(&fninfo);
6523
6524 for (unsigned i = 0; i < num_parts; ++i) {
6525 ac_add_function_attr(ctx->ac.context, parts[i], -1,
6526 AC_FUNC_ATTR_ALWAYSINLINE);
6527 LLVMSetLinkage(parts[i], LLVMPrivateLinkage);
6528 }
6529
6530 /* The parameters of the wrapper function correspond to those of the
6531 * first part in terms of SGPRs and VGPRs, but we use the types of the
6532 * main part to get the right types. This is relevant for the
6533 * dereferenceable attribute on descriptor table pointers.
6534 */
6535 num_sgprs = 0;
6536 num_vgprs = 0;
6537
6538 function_type = LLVMGetElementType(LLVMTypeOf(parts[0]));
6539 num_first_params = LLVMCountParamTypes(function_type);
6540
6541 for (unsigned i = 0; i < num_first_params; ++i) {
6542 LLVMValueRef param = LLVMGetParam(parts[0], i);
6543
6544 if (ac_is_sgpr_param(param)) {
6545 assert(num_vgprs == 0);
6546 num_sgprs += ac_get_type_size(LLVMTypeOf(param)) / 4;
6547 } else {
6548 num_vgprs += ac_get_type_size(LLVMTypeOf(param)) / 4;
6549 }
6550 }
6551
6552 gprs = 0;
6553 while (gprs < num_sgprs + num_vgprs) {
6554 LLVMValueRef param = LLVMGetParam(parts[main_part], fninfo.num_params);
6555 LLVMTypeRef type = LLVMTypeOf(param);
6556 unsigned size = ac_get_type_size(type) / 4;
6557
6558 add_arg(&fninfo, gprs < num_sgprs ? ARG_SGPR : ARG_VGPR, type);
6559
6560 assert(ac_is_sgpr_param(param) == (gprs < num_sgprs));
6561 assert(gprs + size <= num_sgprs + num_vgprs &&
6562 (gprs >= num_sgprs || gprs + size <= num_sgprs));
6563
6564 gprs += size;
6565 }
6566
6567 si_create_function(ctx, "wrapper", NULL, 0, &fninfo,
6568 si_get_max_workgroup_size(ctx->shader));
6569
6570 if (is_merged_shader(ctx))
6571 ac_init_exec_full_mask(&ctx->ac);
6572
6573 /* Record the arguments of the function as if they were an output of
6574 * a previous part.
6575 */
6576 num_out = 0;
6577 num_out_sgpr = 0;
6578
6579 for (unsigned i = 0; i < fninfo.num_params; ++i) {
6580 LLVMValueRef param = LLVMGetParam(ctx->main_fn, i);
6581 LLVMTypeRef param_type = LLVMTypeOf(param);
6582 LLVMTypeRef out_type = i < fninfo.num_sgpr_params ? ctx->i32 : ctx->f32;
6583 unsigned size = ac_get_type_size(param_type) / 4;
6584
6585 if (size == 1) {
6586 if (LLVMGetTypeKind(param_type) == LLVMPointerTypeKind) {
6587 param = LLVMBuildPtrToInt(builder, param, ctx->i32, "");
6588 param_type = ctx->i32;
6589 }
6590
6591 if (param_type != out_type)
6592 param = LLVMBuildBitCast(builder, param, out_type, "");
6593 out[num_out++] = param;
6594 } else {
6595 LLVMTypeRef vector_type = LLVMVectorType(out_type, size);
6596
6597 if (LLVMGetTypeKind(param_type) == LLVMPointerTypeKind) {
6598 param = LLVMBuildPtrToInt(builder, param, ctx->i64, "");
6599 param_type = ctx->i64;
6600 }
6601
6602 if (param_type != vector_type)
6603 param = LLVMBuildBitCast(builder, param, vector_type, "");
6604
6605 for (unsigned j = 0; j < size; ++j)
6606 out[num_out++] = LLVMBuildExtractElement(
6607 builder, param, LLVMConstInt(ctx->i32, j, 0), "");
6608 }
6609
6610 if (i < fninfo.num_sgpr_params)
6611 num_out_sgpr = num_out;
6612 }
6613
6614 memcpy(initial, out, sizeof(out));
6615 initial_num_out = num_out;
6616 initial_num_out_sgpr = num_out_sgpr;
6617
6618 /* Now chain the parts. */
6619 for (unsigned part = 0; part < num_parts; ++part) {
6620 LLVMValueRef in[48];
6621 LLVMValueRef ret;
6622 LLVMTypeRef ret_type;
6623 unsigned out_idx = 0;
6624 unsigned num_params = LLVMCountParams(parts[part]);
6625
6626 /* Merged shaders are executed conditionally depending
6627 * on the number of enabled threads passed in the input SGPRs. */
6628 if (is_merged_shader(ctx) && part == 0) {
6629 LLVMValueRef ena, count = initial[3];
6630
6631 count = LLVMBuildAnd(builder, count,
6632 LLVMConstInt(ctx->i32, 0x7f, 0), "");
6633 ena = LLVMBuildICmp(builder, LLVMIntULT,
6634 ac_get_thread_id(&ctx->ac), count, "");
6635 lp_build_if(&if_state, &ctx->gallivm, ena);
6636 }
6637
6638 /* Derive arguments for the next part from outputs of the
6639 * previous one.
6640 */
6641 for (unsigned param_idx = 0; param_idx < num_params; ++param_idx) {
6642 LLVMValueRef param;
6643 LLVMTypeRef param_type;
6644 bool is_sgpr;
6645 unsigned param_size;
6646 LLVMValueRef arg = NULL;
6647
6648 param = LLVMGetParam(parts[part], param_idx);
6649 param_type = LLVMTypeOf(param);
6650 param_size = ac_get_type_size(param_type) / 4;
6651 is_sgpr = ac_is_sgpr_param(param);
6652
6653 if (is_sgpr) {
6654 ac_add_function_attr(ctx->ac.context, parts[part],
6655 param_idx + 1, AC_FUNC_ATTR_INREG);
6656 } else if (out_idx < num_out_sgpr) {
6657 /* Skip returned SGPRs the current part doesn't
6658 * declare on the input. */
6659 out_idx = num_out_sgpr;
6660 }
6661
6662 assert(out_idx + param_size <= (is_sgpr ? num_out_sgpr : num_out));
6663
6664 if (param_size == 1)
6665 arg = out[out_idx];
6666 else
6667 arg = ac_build_gather_values(&ctx->ac, &out[out_idx], param_size);
6668
6669 if (LLVMTypeOf(arg) != param_type) {
6670 if (LLVMGetTypeKind(param_type) == LLVMPointerTypeKind) {
6671 if (LLVMGetPointerAddressSpace(param_type) ==
6672 AC_CONST_32BIT_ADDR_SPACE) {
6673 arg = LLVMBuildBitCast(builder, arg, ctx->i32, "");
6674 arg = LLVMBuildIntToPtr(builder, arg, param_type, "");
6675 } else {
6676 arg = LLVMBuildBitCast(builder, arg, ctx->i64, "");
6677 arg = LLVMBuildIntToPtr(builder, arg, param_type, "");
6678 }
6679 } else {
6680 arg = LLVMBuildBitCast(builder, arg, param_type, "");
6681 }
6682 }
6683
6684 in[param_idx] = arg;
6685 out_idx += param_size;
6686 }
6687
6688 ret = LLVMBuildCall(builder, parts[part], in, num_params, "");
6689
6690 if (is_merged_shader(ctx) &&
6691 part + 1 == next_shader_first_part) {
6692 lp_build_endif(&if_state);
6693
6694 /* The second half of the merged shader should use
6695 * the inputs from the toplevel (wrapper) function,
6696 * not the return value from the last call.
6697 *
6698 * That's because the last call was executed condi-
6699 * tionally, so we can't consume it in the main
6700 * block.
6701 */
6702 memcpy(out, initial, sizeof(initial));
6703 num_out = initial_num_out;
6704 num_out_sgpr = initial_num_out_sgpr;
6705 continue;
6706 }
6707
6708 /* Extract the returned GPRs. */
6709 ret_type = LLVMTypeOf(ret);
6710 num_out = 0;
6711 num_out_sgpr = 0;
6712
6713 if (LLVMGetTypeKind(ret_type) != LLVMVoidTypeKind) {
6714 assert(LLVMGetTypeKind(ret_type) == LLVMStructTypeKind);
6715
6716 unsigned ret_size = LLVMCountStructElementTypes(ret_type);
6717
6718 for (unsigned i = 0; i < ret_size; ++i) {
6719 LLVMValueRef val =
6720 LLVMBuildExtractValue(builder, ret, i, "");
6721
6722 assert(num_out < ARRAY_SIZE(out));
6723 out[num_out++] = val;
6724
6725 if (LLVMTypeOf(val) == ctx->i32) {
6726 assert(num_out_sgpr + 1 == num_out);
6727 num_out_sgpr = num_out;
6728 }
6729 }
6730 }
6731 }
6732
6733 LLVMBuildRetVoid(builder);
6734 }
6735
6736 static bool si_should_optimize_less(struct ac_llvm_compiler *compiler,
6737 struct si_shader_selector *sel)
6738 {
6739 if (!compiler->low_opt_passes)
6740 return false;
6741
6742 /* Assume a slow CPU. */
6743 assert(!sel->screen->info.has_dedicated_vram &&
6744 sel->screen->info.chip_class <= VI);
6745
6746 /* For a crazy dEQP test containing 2597 memory opcodes, mostly
6747 * buffer stores. */
6748 return sel->type == PIPE_SHADER_COMPUTE &&
6749 sel->info.num_memory_instructions > 1000;
6750 }
6751
6752 int si_compile_tgsi_shader(struct si_screen *sscreen,
6753 struct ac_llvm_compiler *compiler,
6754 struct si_shader *shader,
6755 struct pipe_debug_callback *debug)
6756 {
6757 struct si_shader_selector *sel = shader->selector;
6758 struct si_shader_context ctx;
6759 int r = -1;
6760
6761 /* Dump TGSI code before doing TGSI->LLVM conversion in case the
6762 * conversion fails. */
6763 if (si_can_dump_shader(sscreen, sel->info.processor) &&
6764 !(sscreen->debug_flags & DBG(NO_TGSI))) {
6765 if (sel->tokens)
6766 tgsi_dump(sel->tokens, 0);
6767 else
6768 nir_print_shader(sel->nir, stderr);
6769 si_dump_streamout(&sel->so);
6770 }
6771
6772 si_init_shader_ctx(&ctx, sscreen, compiler);
6773 si_llvm_context_set_tgsi(&ctx, shader);
6774
6775 memset(shader->info.vs_output_param_offset, AC_EXP_PARAM_UNDEFINED,
6776 sizeof(shader->info.vs_output_param_offset));
6777
6778 shader->info.uses_instanceid = sel->info.uses_instanceid;
6779
6780 if (!si_compile_tgsi_main(&ctx)) {
6781 si_llvm_dispose(&ctx);
6782 return -1;
6783 }
6784
6785 if (shader->is_monolithic && ctx.type == PIPE_SHADER_VERTEX) {
6786 LLVMValueRef parts[2];
6787 bool need_prolog = sel->vs_needs_prolog;
6788
6789 parts[1] = ctx.main_fn;
6790
6791 if (need_prolog) {
6792 union si_shader_part_key prolog_key;
6793 si_get_vs_prolog_key(&sel->info,
6794 shader->info.num_input_sgprs,
6795 &shader->key.part.vs.prolog,
6796 shader, &prolog_key);
6797 si_build_vs_prolog_function(&ctx, &prolog_key);
6798 parts[0] = ctx.main_fn;
6799 }
6800
6801 si_build_wrapper_function(&ctx, parts + !need_prolog,
6802 1 + need_prolog, need_prolog, 0);
6803 } else if (shader->is_monolithic && ctx.type == PIPE_SHADER_TESS_CTRL) {
6804 if (sscreen->info.chip_class >= GFX9) {
6805 struct si_shader_selector *ls = shader->key.part.tcs.ls;
6806 LLVMValueRef parts[4];
6807 bool vs_needs_prolog =
6808 si_vs_needs_prolog(ls, &shader->key.part.tcs.ls_prolog);
6809
6810 /* TCS main part */
6811 parts[2] = ctx.main_fn;
6812
6813 /* TCS epilog */
6814 union si_shader_part_key tcs_epilog_key;
6815 memset(&tcs_epilog_key, 0, sizeof(tcs_epilog_key));
6816 tcs_epilog_key.tcs_epilog.states = shader->key.part.tcs.epilog;
6817 si_build_tcs_epilog_function(&ctx, &tcs_epilog_key);
6818 parts[3] = ctx.main_fn;
6819
6820 /* VS as LS main part */
6821 struct si_shader shader_ls = {};
6822 shader_ls.selector = ls;
6823 shader_ls.key.as_ls = 1;
6824 shader_ls.key.mono = shader->key.mono;
6825 shader_ls.key.opt = shader->key.opt;
6826 shader_ls.is_monolithic = true;
6827 si_llvm_context_set_tgsi(&ctx, &shader_ls);
6828
6829 if (!si_compile_tgsi_main(&ctx)) {
6830 si_llvm_dispose(&ctx);
6831 return -1;
6832 }
6833 shader->info.uses_instanceid |= ls->info.uses_instanceid;
6834 parts[1] = ctx.main_fn;
6835
6836 /* LS prolog */
6837 if (vs_needs_prolog) {
6838 union si_shader_part_key vs_prolog_key;
6839 si_get_vs_prolog_key(&ls->info,
6840 shader_ls.info.num_input_sgprs,
6841 &shader->key.part.tcs.ls_prolog,
6842 shader, &vs_prolog_key);
6843 vs_prolog_key.vs_prolog.is_monolithic = true;
6844 si_build_vs_prolog_function(&ctx, &vs_prolog_key);
6845 parts[0] = ctx.main_fn;
6846 }
6847
6848 /* Reset the shader context. */
6849 ctx.shader = shader;
6850 ctx.type = PIPE_SHADER_TESS_CTRL;
6851
6852 si_build_wrapper_function(&ctx,
6853 parts + !vs_needs_prolog,
6854 4 - !vs_needs_prolog, vs_needs_prolog,
6855 vs_needs_prolog ? 2 : 1);
6856 } else {
6857 LLVMValueRef parts[2];
6858 union si_shader_part_key epilog_key;
6859
6860 parts[0] = ctx.main_fn;
6861
6862 memset(&epilog_key, 0, sizeof(epilog_key));
6863 epilog_key.tcs_epilog.states = shader->key.part.tcs.epilog;
6864 si_build_tcs_epilog_function(&ctx, &epilog_key);
6865 parts[1] = ctx.main_fn;
6866
6867 si_build_wrapper_function(&ctx, parts, 2, 0, 0);
6868 }
6869 } else if (shader->is_monolithic && ctx.type == PIPE_SHADER_GEOMETRY) {
6870 if (ctx.screen->info.chip_class >= GFX9) {
6871 struct si_shader_selector *es = shader->key.part.gs.es;
6872 LLVMValueRef es_prolog = NULL;
6873 LLVMValueRef es_main = NULL;
6874 LLVMValueRef gs_prolog = NULL;
6875 LLVMValueRef gs_main = ctx.main_fn;
6876
6877 /* GS prolog */
6878 union si_shader_part_key gs_prolog_key;
6879 memset(&gs_prolog_key, 0, sizeof(gs_prolog_key));
6880 gs_prolog_key.gs_prolog.states = shader->key.part.gs.prolog;
6881 gs_prolog_key.gs_prolog.is_monolithic = true;
6882 si_build_gs_prolog_function(&ctx, &gs_prolog_key);
6883 gs_prolog = ctx.main_fn;
6884
6885 /* ES main part */
6886 struct si_shader shader_es = {};
6887 shader_es.selector = es;
6888 shader_es.key.as_es = 1;
6889 shader_es.key.mono = shader->key.mono;
6890 shader_es.key.opt = shader->key.opt;
6891 shader_es.is_monolithic = true;
6892 si_llvm_context_set_tgsi(&ctx, &shader_es);
6893
6894 if (!si_compile_tgsi_main(&ctx)) {
6895 si_llvm_dispose(&ctx);
6896 return -1;
6897 }
6898 shader->info.uses_instanceid |= es->info.uses_instanceid;
6899 es_main = ctx.main_fn;
6900
6901 /* ES prolog */
6902 if (es->vs_needs_prolog) {
6903 union si_shader_part_key vs_prolog_key;
6904 si_get_vs_prolog_key(&es->info,
6905 shader_es.info.num_input_sgprs,
6906 &shader->key.part.gs.vs_prolog,
6907 shader, &vs_prolog_key);
6908 vs_prolog_key.vs_prolog.is_monolithic = true;
6909 si_build_vs_prolog_function(&ctx, &vs_prolog_key);
6910 es_prolog = ctx.main_fn;
6911 }
6912
6913 /* Reset the shader context. */
6914 ctx.shader = shader;
6915 ctx.type = PIPE_SHADER_GEOMETRY;
6916
6917 /* Prepare the array of shader parts. */
6918 LLVMValueRef parts[4];
6919 unsigned num_parts = 0, main_part, next_first_part;
6920
6921 if (es_prolog)
6922 parts[num_parts++] = es_prolog;
6923
6924 parts[main_part = num_parts++] = es_main;
6925 parts[next_first_part = num_parts++] = gs_prolog;
6926 parts[num_parts++] = gs_main;
6927
6928 si_build_wrapper_function(&ctx, parts, num_parts,
6929 main_part, next_first_part);
6930 } else {
6931 LLVMValueRef parts[2];
6932 union si_shader_part_key prolog_key;
6933
6934 parts[1] = ctx.main_fn;
6935
6936 memset(&prolog_key, 0, sizeof(prolog_key));
6937 prolog_key.gs_prolog.states = shader->key.part.gs.prolog;
6938 si_build_gs_prolog_function(&ctx, &prolog_key);
6939 parts[0] = ctx.main_fn;
6940
6941 si_build_wrapper_function(&ctx, parts, 2, 1, 0);
6942 }
6943 } else if (shader->is_monolithic && ctx.type == PIPE_SHADER_FRAGMENT) {
6944 LLVMValueRef parts[3];
6945 union si_shader_part_key prolog_key;
6946 union si_shader_part_key epilog_key;
6947 bool need_prolog;
6948
6949 si_get_ps_prolog_key(shader, &prolog_key, false);
6950 need_prolog = si_need_ps_prolog(&prolog_key);
6951
6952 parts[need_prolog ? 1 : 0] = ctx.main_fn;
6953
6954 if (need_prolog) {
6955 si_build_ps_prolog_function(&ctx, &prolog_key);
6956 parts[0] = ctx.main_fn;
6957 }
6958
6959 si_get_ps_epilog_key(shader, &epilog_key);
6960 si_build_ps_epilog_function(&ctx, &epilog_key);
6961 parts[need_prolog ? 2 : 1] = ctx.main_fn;
6962
6963 si_build_wrapper_function(&ctx, parts, need_prolog ? 3 : 2,
6964 need_prolog ? 1 : 0, 0);
6965 }
6966
6967 si_llvm_optimize_module(&ctx);
6968
6969 /* Post-optimization transformations and analysis. */
6970 si_optimize_vs_outputs(&ctx);
6971
6972 if ((debug && debug->debug_message) ||
6973 si_can_dump_shader(sscreen, ctx.type)) {
6974 ctx.shader->config.private_mem_vgprs =
6975 ac_count_scratch_private_memory(ctx.main_fn);
6976 }
6977
6978 /* Make sure the input is a pointer and not integer followed by inttoptr. */
6979 assert(LLVMGetTypeKind(LLVMTypeOf(LLVMGetParam(ctx.main_fn, 0))) ==
6980 LLVMPointerTypeKind);
6981
6982 /* Compile to bytecode. */
6983 r = si_compile_llvm(sscreen, &shader->binary, &shader->config, compiler,
6984 ctx.ac.module, debug, ctx.type,
6985 si_get_shader_name(shader, ctx.type),
6986 si_should_optimize_less(compiler, shader->selector));
6987 si_llvm_dispose(&ctx);
6988 if (r) {
6989 fprintf(stderr, "LLVM failed to compile shader\n");
6990 return r;
6991 }
6992
6993 /* Validate SGPR and VGPR usage for compute to detect compiler bugs.
6994 * LLVM 3.9svn has this bug.
6995 */
6996 if (sel->type == PIPE_SHADER_COMPUTE) {
6997 unsigned wave_size = 64;
6998 unsigned max_vgprs = 256;
6999 unsigned max_sgprs = sscreen->info.chip_class >= VI ? 800 : 512;
7000 unsigned max_sgprs_per_wave = 128;
7001 unsigned max_block_threads = si_get_max_workgroup_size(shader);
7002 unsigned min_waves_per_cu = DIV_ROUND_UP(max_block_threads, wave_size);
7003 unsigned min_waves_per_simd = DIV_ROUND_UP(min_waves_per_cu, 4);
7004
7005 max_vgprs = max_vgprs / min_waves_per_simd;
7006 max_sgprs = MIN2(max_sgprs / min_waves_per_simd, max_sgprs_per_wave);
7007
7008 if (shader->config.num_sgprs > max_sgprs ||
7009 shader->config.num_vgprs > max_vgprs) {
7010 fprintf(stderr, "LLVM failed to compile a shader correctly: "
7011 "SGPR:VGPR usage is %u:%u, but the hw limit is %u:%u\n",
7012 shader->config.num_sgprs, shader->config.num_vgprs,
7013 max_sgprs, max_vgprs);
7014
7015 /* Just terminate the process, because dependent
7016 * shaders can hang due to bad input data, but use
7017 * the env var to allow shader-db to work.
7018 */
7019 if (!debug_get_bool_option("SI_PASS_BAD_SHADERS", false))
7020 abort();
7021 }
7022 }
7023
7024 /* Add the scratch offset to input SGPRs. */
7025 if (shader->config.scratch_bytes_per_wave && !is_merged_shader(&ctx))
7026 shader->info.num_input_sgprs += 1; /* scratch byte offset */
7027
7028 /* Calculate the number of fragment input VGPRs. */
7029 if (ctx.type == PIPE_SHADER_FRAGMENT) {
7030 shader->info.num_input_vgprs = 0;
7031 shader->info.face_vgpr_index = -1;
7032 shader->info.ancillary_vgpr_index = -1;
7033
7034 if (G_0286CC_PERSP_SAMPLE_ENA(shader->config.spi_ps_input_addr))
7035 shader->info.num_input_vgprs += 2;
7036 if (G_0286CC_PERSP_CENTER_ENA(shader->config.spi_ps_input_addr))
7037 shader->info.num_input_vgprs += 2;
7038 if (G_0286CC_PERSP_CENTROID_ENA(shader->config.spi_ps_input_addr))
7039 shader->info.num_input_vgprs += 2;
7040 if (G_0286CC_PERSP_PULL_MODEL_ENA(shader->config.spi_ps_input_addr))
7041 shader->info.num_input_vgprs += 3;
7042 if (G_0286CC_LINEAR_SAMPLE_ENA(shader->config.spi_ps_input_addr))
7043 shader->info.num_input_vgprs += 2;
7044 if (G_0286CC_LINEAR_CENTER_ENA(shader->config.spi_ps_input_addr))
7045 shader->info.num_input_vgprs += 2;
7046 if (G_0286CC_LINEAR_CENTROID_ENA(shader->config.spi_ps_input_addr))
7047 shader->info.num_input_vgprs += 2;
7048 if (G_0286CC_LINE_STIPPLE_TEX_ENA(shader->config.spi_ps_input_addr))
7049 shader->info.num_input_vgprs += 1;
7050 if (G_0286CC_POS_X_FLOAT_ENA(shader->config.spi_ps_input_addr))
7051 shader->info.num_input_vgprs += 1;
7052 if (G_0286CC_POS_Y_FLOAT_ENA(shader->config.spi_ps_input_addr))
7053 shader->info.num_input_vgprs += 1;
7054 if (G_0286CC_POS_Z_FLOAT_ENA(shader->config.spi_ps_input_addr))
7055 shader->info.num_input_vgprs += 1;
7056 if (G_0286CC_POS_W_FLOAT_ENA(shader->config.spi_ps_input_addr))
7057 shader->info.num_input_vgprs += 1;
7058 if (G_0286CC_FRONT_FACE_ENA(shader->config.spi_ps_input_addr)) {
7059 shader->info.face_vgpr_index = shader->info.num_input_vgprs;
7060 shader->info.num_input_vgprs += 1;
7061 }
7062 if (G_0286CC_ANCILLARY_ENA(shader->config.spi_ps_input_addr)) {
7063 shader->info.ancillary_vgpr_index = shader->info.num_input_vgprs;
7064 shader->info.num_input_vgprs += 1;
7065 }
7066 if (G_0286CC_SAMPLE_COVERAGE_ENA(shader->config.spi_ps_input_addr))
7067 shader->info.num_input_vgprs += 1;
7068 if (G_0286CC_POS_FIXED_PT_ENA(shader->config.spi_ps_input_addr))
7069 shader->info.num_input_vgprs += 1;
7070 }
7071
7072 si_calculate_max_simd_waves(shader);
7073 si_shader_dump_stats_for_shader_db(shader, debug);
7074 return 0;
7075 }
7076
7077 /**
7078 * Create, compile and return a shader part (prolog or epilog).
7079 *
7080 * \param sscreen screen
7081 * \param list list of shader parts of the same category
7082 * \param type shader type
7083 * \param key shader part key
7084 * \param prolog whether the part being requested is a prolog
7085 * \param tm LLVM target machine
7086 * \param debug debug callback
7087 * \param build the callback responsible for building the main function
7088 * \return non-NULL on success
7089 */
7090 static struct si_shader_part *
7091 si_get_shader_part(struct si_screen *sscreen,
7092 struct si_shader_part **list,
7093 enum pipe_shader_type type,
7094 bool prolog,
7095 union si_shader_part_key *key,
7096 struct ac_llvm_compiler *compiler,
7097 struct pipe_debug_callback *debug,
7098 void (*build)(struct si_shader_context *,
7099 union si_shader_part_key *),
7100 const char *name)
7101 {
7102 struct si_shader_part *result;
7103
7104 mtx_lock(&sscreen->shader_parts_mutex);
7105
7106 /* Find existing. */
7107 for (result = *list; result; result = result->next) {
7108 if (memcmp(&result->key, key, sizeof(*key)) == 0) {
7109 mtx_unlock(&sscreen->shader_parts_mutex);
7110 return result;
7111 }
7112 }
7113
7114 /* Compile a new one. */
7115 result = CALLOC_STRUCT(si_shader_part);
7116 result->key = *key;
7117
7118 struct si_shader shader = {};
7119 struct si_shader_context ctx;
7120
7121 si_init_shader_ctx(&ctx, sscreen, compiler);
7122 ctx.shader = &shader;
7123 ctx.type = type;
7124
7125 switch (type) {
7126 case PIPE_SHADER_VERTEX:
7127 shader.key.as_ls = key->vs_prolog.as_ls;
7128 shader.key.as_es = key->vs_prolog.as_es;
7129 break;
7130 case PIPE_SHADER_TESS_CTRL:
7131 assert(!prolog);
7132 shader.key.part.tcs.epilog = key->tcs_epilog.states;
7133 break;
7134 case PIPE_SHADER_GEOMETRY:
7135 assert(prolog);
7136 break;
7137 case PIPE_SHADER_FRAGMENT:
7138 if (prolog)
7139 shader.key.part.ps.prolog = key->ps_prolog.states;
7140 else
7141 shader.key.part.ps.epilog = key->ps_epilog.states;
7142 break;
7143 default:
7144 unreachable("bad shader part");
7145 }
7146
7147 build(&ctx, key);
7148
7149 /* Compile. */
7150 si_llvm_optimize_module(&ctx);
7151
7152 if (si_compile_llvm(sscreen, &result->binary, &result->config, compiler,
7153 ctx.ac.module, debug, ctx.type, name, false)) {
7154 FREE(result);
7155 result = NULL;
7156 goto out;
7157 }
7158
7159 result->next = *list;
7160 *list = result;
7161
7162 out:
7163 si_llvm_dispose(&ctx);
7164 mtx_unlock(&sscreen->shader_parts_mutex);
7165 return result;
7166 }
7167
7168 static LLVMValueRef si_prolog_get_rw_buffers(struct si_shader_context *ctx)
7169 {
7170 LLVMValueRef ptr[2], list;
7171 bool merged_shader = is_merged_shader(ctx);
7172
7173 if (HAVE_32BIT_POINTERS) {
7174 ptr[0] = LLVMGetParam(ctx->main_fn, (merged_shader ? 8 : 0) + SI_SGPR_RW_BUFFERS);
7175 list = LLVMBuildIntToPtr(ctx->ac.builder, ptr[0],
7176 ac_array_in_const32_addr_space(ctx->v4i32), "");
7177 return list;
7178 }
7179
7180 /* Get the pointer to rw buffers. */
7181 ptr[0] = LLVMGetParam(ctx->main_fn, (merged_shader ? 8 : 0) + SI_SGPR_RW_BUFFERS);
7182 ptr[1] = LLVMGetParam(ctx->main_fn, (merged_shader ? 8 : 0) + SI_SGPR_RW_BUFFERS + 1);
7183 list = ac_build_gather_values(&ctx->ac, ptr, 2);
7184 list = LLVMBuildBitCast(ctx->ac.builder, list, ctx->i64, "");
7185 list = LLVMBuildIntToPtr(ctx->ac.builder, list,
7186 ac_array_in_const_addr_space(ctx->v4i32), "");
7187 return list;
7188 }
7189
7190 /**
7191 * Build the vertex shader prolog function.
7192 *
7193 * The inputs are the same as VS (a lot of SGPRs and 4 VGPR system values).
7194 * All inputs are returned unmodified. The vertex load indices are
7195 * stored after them, which will be used by the API VS for fetching inputs.
7196 *
7197 * For example, the expected outputs for instance_divisors[] = {0, 1, 2} are:
7198 * input_v0,
7199 * input_v1,
7200 * input_v2,
7201 * input_v3,
7202 * (VertexID + BaseVertex),
7203 * (InstanceID + StartInstance),
7204 * (InstanceID / 2 + StartInstance)
7205 */
7206 static void si_build_vs_prolog_function(struct si_shader_context *ctx,
7207 union si_shader_part_key *key)
7208 {
7209 struct si_function_info fninfo;
7210 LLVMTypeRef *returns;
7211 LLVMValueRef ret, func;
7212 int num_returns, i;
7213 unsigned first_vs_vgpr = key->vs_prolog.num_merged_next_stage_vgprs;
7214 unsigned num_input_vgprs = key->vs_prolog.num_merged_next_stage_vgprs + 4;
7215 LLVMValueRef input_vgprs[9];
7216 unsigned num_all_input_regs = key->vs_prolog.num_input_sgprs +
7217 num_input_vgprs;
7218 unsigned user_sgpr_base = key->vs_prolog.num_merged_next_stage_vgprs ? 8 : 0;
7219
7220 si_init_function_info(&fninfo);
7221
7222 /* 4 preloaded VGPRs + vertex load indices as prolog outputs */
7223 returns = alloca((num_all_input_regs + key->vs_prolog.last_input + 1) *
7224 sizeof(LLVMTypeRef));
7225 num_returns = 0;
7226
7227 /* Declare input and output SGPRs. */
7228 for (i = 0; i < key->vs_prolog.num_input_sgprs; i++) {
7229 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7230 returns[num_returns++] = ctx->i32;
7231 }
7232
7233 /* Preloaded VGPRs (outputs must be floats) */
7234 for (i = 0; i < num_input_vgprs; i++) {
7235 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &input_vgprs[i]);
7236 returns[num_returns++] = ctx->f32;
7237 }
7238
7239 /* Vertex load indices. */
7240 for (i = 0; i <= key->vs_prolog.last_input; i++)
7241 returns[num_returns++] = ctx->f32;
7242
7243 /* Create the function. */
7244 si_create_function(ctx, "vs_prolog", returns, num_returns, &fninfo, 0);
7245 func = ctx->main_fn;
7246
7247 if (key->vs_prolog.num_merged_next_stage_vgprs) {
7248 if (!key->vs_prolog.is_monolithic)
7249 si_init_exec_from_input(ctx, 3, 0);
7250
7251 if (key->vs_prolog.as_ls &&
7252 ctx->screen->has_ls_vgpr_init_bug) {
7253 /* If there are no HS threads, SPI loads the LS VGPRs
7254 * starting at VGPR 0. Shift them back to where they
7255 * belong.
7256 */
7257 LLVMValueRef has_hs_threads =
7258 LLVMBuildICmp(ctx->ac.builder, LLVMIntNE,
7259 si_unpack_param(ctx, 3, 8, 8),
7260 ctx->i32_0, "");
7261
7262 for (i = 4; i > 0; --i) {
7263 input_vgprs[i + 1] =
7264 LLVMBuildSelect(ctx->ac.builder, has_hs_threads,
7265 input_vgprs[i + 1],
7266 input_vgprs[i - 1], "");
7267 }
7268 }
7269 }
7270
7271 ctx->abi.vertex_id = input_vgprs[first_vs_vgpr];
7272 ctx->abi.instance_id = input_vgprs[first_vs_vgpr + (key->vs_prolog.as_ls ? 2 : 1)];
7273
7274 /* Copy inputs to outputs. This should be no-op, as the registers match,
7275 * but it will prevent the compiler from overwriting them unintentionally.
7276 */
7277 ret = ctx->return_value;
7278 for (i = 0; i < key->vs_prolog.num_input_sgprs; i++) {
7279 LLVMValueRef p = LLVMGetParam(func, i);
7280 ret = LLVMBuildInsertValue(ctx->ac.builder, ret, p, i, "");
7281 }
7282 for (i = 0; i < num_input_vgprs; i++) {
7283 LLVMValueRef p = input_vgprs[i];
7284 p = ac_to_float(&ctx->ac, p);
7285 ret = LLVMBuildInsertValue(ctx->ac.builder, ret, p,
7286 key->vs_prolog.num_input_sgprs + i, "");
7287 }
7288
7289 /* Compute vertex load indices from instance divisors. */
7290 LLVMValueRef instance_divisor_constbuf = NULL;
7291
7292 if (key->vs_prolog.states.instance_divisor_is_fetched) {
7293 LLVMValueRef list = si_prolog_get_rw_buffers(ctx);
7294 LLVMValueRef buf_index =
7295 LLVMConstInt(ctx->i32, SI_VS_CONST_INSTANCE_DIVISORS, 0);
7296 instance_divisor_constbuf =
7297 ac_build_load_to_sgpr(&ctx->ac, list, buf_index);
7298 }
7299
7300 for (i = 0; i <= key->vs_prolog.last_input; i++) {
7301 bool divisor_is_one =
7302 key->vs_prolog.states.instance_divisor_is_one & (1u << i);
7303 bool divisor_is_fetched =
7304 key->vs_prolog.states.instance_divisor_is_fetched & (1u << i);
7305 LLVMValueRef index;
7306
7307 if (divisor_is_one || divisor_is_fetched) {
7308 LLVMValueRef divisor = ctx->i32_1;
7309
7310 if (divisor_is_fetched) {
7311 divisor = buffer_load_const(ctx, instance_divisor_constbuf,
7312 LLVMConstInt(ctx->i32, i * 4, 0));
7313 divisor = ac_to_integer(&ctx->ac, divisor);
7314 }
7315
7316 /* InstanceID / Divisor + StartInstance */
7317 index = get_instance_index_for_fetch(ctx,
7318 user_sgpr_base +
7319 SI_SGPR_START_INSTANCE,
7320 divisor);
7321 } else {
7322 /* VertexID + BaseVertex */
7323 index = LLVMBuildAdd(ctx->ac.builder,
7324 ctx->abi.vertex_id,
7325 LLVMGetParam(func, user_sgpr_base +
7326 SI_SGPR_BASE_VERTEX), "");
7327 }
7328
7329 index = ac_to_float(&ctx->ac, index);
7330 ret = LLVMBuildInsertValue(ctx->ac.builder, ret, index,
7331 fninfo.num_params + i, "");
7332 }
7333
7334 si_llvm_build_ret(ctx, ret);
7335 }
7336
7337 static bool si_get_vs_prolog(struct si_screen *sscreen,
7338 struct ac_llvm_compiler *compiler,
7339 struct si_shader *shader,
7340 struct pipe_debug_callback *debug,
7341 struct si_shader *main_part,
7342 const struct si_vs_prolog_bits *key)
7343 {
7344 struct si_shader_selector *vs = main_part->selector;
7345
7346 if (!si_vs_needs_prolog(vs, key))
7347 return true;
7348
7349 /* Get the prolog. */
7350 union si_shader_part_key prolog_key;
7351 si_get_vs_prolog_key(&vs->info, main_part->info.num_input_sgprs,
7352 key, shader, &prolog_key);
7353
7354 shader->prolog =
7355 si_get_shader_part(sscreen, &sscreen->vs_prologs,
7356 PIPE_SHADER_VERTEX, true, &prolog_key, compiler,
7357 debug, si_build_vs_prolog_function,
7358 "Vertex Shader Prolog");
7359 return shader->prolog != NULL;
7360 }
7361
7362 /**
7363 * Select and compile (or reuse) vertex shader parts (prolog & epilog).
7364 */
7365 static bool si_shader_select_vs_parts(struct si_screen *sscreen,
7366 struct ac_llvm_compiler *compiler,
7367 struct si_shader *shader,
7368 struct pipe_debug_callback *debug)
7369 {
7370 return si_get_vs_prolog(sscreen, compiler, shader, debug, shader,
7371 &shader->key.part.vs.prolog);
7372 }
7373
7374 /**
7375 * Compile the TCS epilog function. This writes tesselation factors to memory
7376 * based on the output primitive type of the tesselator (determined by TES).
7377 */
7378 static void si_build_tcs_epilog_function(struct si_shader_context *ctx,
7379 union si_shader_part_key *key)
7380 {
7381 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
7382 struct si_function_info fninfo;
7383 LLVMValueRef func;
7384
7385 si_init_function_info(&fninfo);
7386
7387 if (ctx->screen->info.chip_class >= GFX9) {
7388 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7389 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7390 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7391 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* wave info */
7392 ctx->param_tcs_factor_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7393 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7394 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7395 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7396 add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7397 add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7398 add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7399 add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7400 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7401 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7402 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7403 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7404 if (!HAVE_32BIT_POINTERS)
7405 add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7406 ctx->param_tcs_offchip_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7407 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7408 ctx->param_tcs_out_lds_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7409 } else {
7410 add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7411 add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7412 add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7413 add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7414 ctx->param_tcs_offchip_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7415 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7416 ctx->param_tcs_out_lds_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7417 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7418 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7419 ctx->param_tcs_factor_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7420 }
7421
7422 add_arg(&fninfo, ARG_VGPR, ctx->i32); /* VGPR gap */
7423 add_arg(&fninfo, ARG_VGPR, ctx->i32); /* VGPR gap */
7424 unsigned tess_factors_idx =
7425 add_arg(&fninfo, ARG_VGPR, ctx->i32); /* patch index within the wave (REL_PATCH_ID) */
7426 add_arg(&fninfo, ARG_VGPR, ctx->i32); /* invocation ID within the patch */
7427 add_arg(&fninfo, ARG_VGPR, ctx->i32); /* LDS offset where tess factors should be loaded from */
7428
7429 for (unsigned i = 0; i < 6; i++)
7430 add_arg(&fninfo, ARG_VGPR, ctx->i32); /* tess factors */
7431
7432 /* Create the function. */
7433 si_create_function(ctx, "tcs_epilog", NULL, 0, &fninfo,
7434 ctx->screen->info.chip_class >= CIK ? 128 : 64);
7435 ac_declare_lds_as_pointer(&ctx->ac);
7436 func = ctx->main_fn;
7437
7438 LLVMValueRef invoc0_tess_factors[6];
7439 for (unsigned i = 0; i < 6; i++)
7440 invoc0_tess_factors[i] = LLVMGetParam(func, tess_factors_idx + 3 + i);
7441
7442 si_write_tess_factors(bld_base,
7443 LLVMGetParam(func, tess_factors_idx),
7444 LLVMGetParam(func, tess_factors_idx + 1),
7445 LLVMGetParam(func, tess_factors_idx + 2),
7446 invoc0_tess_factors, invoc0_tess_factors + 4);
7447
7448 LLVMBuildRetVoid(ctx->ac.builder);
7449 }
7450
7451 /**
7452 * Select and compile (or reuse) TCS parts (epilog).
7453 */
7454 static bool si_shader_select_tcs_parts(struct si_screen *sscreen,
7455 struct ac_llvm_compiler *compiler,
7456 struct si_shader *shader,
7457 struct pipe_debug_callback *debug)
7458 {
7459 if (sscreen->info.chip_class >= GFX9) {
7460 struct si_shader *ls_main_part =
7461 shader->key.part.tcs.ls->main_shader_part_ls;
7462
7463 if (!si_get_vs_prolog(sscreen, compiler, shader, debug, ls_main_part,
7464 &shader->key.part.tcs.ls_prolog))
7465 return false;
7466
7467 shader->previous_stage = ls_main_part;
7468 }
7469
7470 /* Get the epilog. */
7471 union si_shader_part_key epilog_key;
7472 memset(&epilog_key, 0, sizeof(epilog_key));
7473 epilog_key.tcs_epilog.states = shader->key.part.tcs.epilog;
7474
7475 shader->epilog = si_get_shader_part(sscreen, &sscreen->tcs_epilogs,
7476 PIPE_SHADER_TESS_CTRL, false,
7477 &epilog_key, compiler, debug,
7478 si_build_tcs_epilog_function,
7479 "Tessellation Control Shader Epilog");
7480 return shader->epilog != NULL;
7481 }
7482
7483 /**
7484 * Select and compile (or reuse) GS parts (prolog).
7485 */
7486 static bool si_shader_select_gs_parts(struct si_screen *sscreen,
7487 struct ac_llvm_compiler *compiler,
7488 struct si_shader *shader,
7489 struct pipe_debug_callback *debug)
7490 {
7491 if (sscreen->info.chip_class >= GFX9) {
7492 struct si_shader *es_main_part =
7493 shader->key.part.gs.es->main_shader_part_es;
7494
7495 if (shader->key.part.gs.es->type == PIPE_SHADER_VERTEX &&
7496 !si_get_vs_prolog(sscreen, compiler, shader, debug, es_main_part,
7497 &shader->key.part.gs.vs_prolog))
7498 return false;
7499
7500 shader->previous_stage = es_main_part;
7501 }
7502
7503 if (!shader->key.part.gs.prolog.tri_strip_adj_fix)
7504 return true;
7505
7506 union si_shader_part_key prolog_key;
7507 memset(&prolog_key, 0, sizeof(prolog_key));
7508 prolog_key.gs_prolog.states = shader->key.part.gs.prolog;
7509
7510 shader->prolog2 = si_get_shader_part(sscreen, &sscreen->gs_prologs,
7511 PIPE_SHADER_GEOMETRY, true,
7512 &prolog_key, compiler, debug,
7513 si_build_gs_prolog_function,
7514 "Geometry Shader Prolog");
7515 return shader->prolog2 != NULL;
7516 }
7517
7518 /**
7519 * Build the pixel shader prolog function. This handles:
7520 * - two-side color selection and interpolation
7521 * - overriding interpolation parameters for the API PS
7522 * - polygon stippling
7523 *
7524 * All preloaded SGPRs and VGPRs are passed through unmodified unless they are
7525 * overriden by other states. (e.g. per-sample interpolation)
7526 * Interpolated colors are stored after the preloaded VGPRs.
7527 */
7528 static void si_build_ps_prolog_function(struct si_shader_context *ctx,
7529 union si_shader_part_key *key)
7530 {
7531 struct si_function_info fninfo;
7532 LLVMValueRef ret, func;
7533 int num_returns, i, num_color_channels;
7534
7535 assert(si_need_ps_prolog(key));
7536
7537 si_init_function_info(&fninfo);
7538
7539 /* Declare inputs. */
7540 for (i = 0; i < key->ps_prolog.num_input_sgprs; i++)
7541 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7542
7543 for (i = 0; i < key->ps_prolog.num_input_vgprs; i++)
7544 add_arg(&fninfo, ARG_VGPR, ctx->f32);
7545
7546 /* Declare outputs (same as inputs + add colors if needed) */
7547 num_returns = fninfo.num_params;
7548 num_color_channels = util_bitcount(key->ps_prolog.colors_read);
7549 for (i = 0; i < num_color_channels; i++)
7550 fninfo.types[num_returns++] = ctx->f32;
7551
7552 /* Create the function. */
7553 si_create_function(ctx, "ps_prolog", fninfo.types, num_returns,
7554 &fninfo, 0);
7555 func = ctx->main_fn;
7556
7557 /* Copy inputs to outputs. This should be no-op, as the registers match,
7558 * but it will prevent the compiler from overwriting them unintentionally.
7559 */
7560 ret = ctx->return_value;
7561 for (i = 0; i < fninfo.num_params; i++) {
7562 LLVMValueRef p = LLVMGetParam(func, i);
7563 ret = LLVMBuildInsertValue(ctx->ac.builder, ret, p, i, "");
7564 }
7565
7566 /* Polygon stippling. */
7567 if (key->ps_prolog.states.poly_stipple) {
7568 /* POS_FIXED_PT is always last. */
7569 unsigned pos = key->ps_prolog.num_input_sgprs +
7570 key->ps_prolog.num_input_vgprs - 1;
7571 LLVMValueRef list = si_prolog_get_rw_buffers(ctx);
7572
7573 si_llvm_emit_polygon_stipple(ctx, list, pos);
7574 }
7575
7576 if (key->ps_prolog.states.bc_optimize_for_persp ||
7577 key->ps_prolog.states.bc_optimize_for_linear) {
7578 unsigned i, base = key->ps_prolog.num_input_sgprs;
7579 LLVMValueRef center[2], centroid[2], tmp, bc_optimize;
7580
7581 /* The shader should do: if (PRIM_MASK[31]) CENTROID = CENTER;
7582 * The hw doesn't compute CENTROID if the whole wave only
7583 * contains fully-covered quads.
7584 *
7585 * PRIM_MASK is after user SGPRs.
7586 */
7587 bc_optimize = LLVMGetParam(func, SI_PS_NUM_USER_SGPR);
7588 bc_optimize = LLVMBuildLShr(ctx->ac.builder, bc_optimize,
7589 LLVMConstInt(ctx->i32, 31, 0), "");
7590 bc_optimize = LLVMBuildTrunc(ctx->ac.builder, bc_optimize,
7591 ctx->i1, "");
7592
7593 if (key->ps_prolog.states.bc_optimize_for_persp) {
7594 /* Read PERSP_CENTER. */
7595 for (i = 0; i < 2; i++)
7596 center[i] = LLVMGetParam(func, base + 2 + i);
7597 /* Read PERSP_CENTROID. */
7598 for (i = 0; i < 2; i++)
7599 centroid[i] = LLVMGetParam(func, base + 4 + i);
7600 /* Select PERSP_CENTROID. */
7601 for (i = 0; i < 2; i++) {
7602 tmp = LLVMBuildSelect(ctx->ac.builder, bc_optimize,
7603 center[i], centroid[i], "");
7604 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7605 tmp, base + 4 + i, "");
7606 }
7607 }
7608 if (key->ps_prolog.states.bc_optimize_for_linear) {
7609 /* Read LINEAR_CENTER. */
7610 for (i = 0; i < 2; i++)
7611 center[i] = LLVMGetParam(func, base + 8 + i);
7612 /* Read LINEAR_CENTROID. */
7613 for (i = 0; i < 2; i++)
7614 centroid[i] = LLVMGetParam(func, base + 10 + i);
7615 /* Select LINEAR_CENTROID. */
7616 for (i = 0; i < 2; i++) {
7617 tmp = LLVMBuildSelect(ctx->ac.builder, bc_optimize,
7618 center[i], centroid[i], "");
7619 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7620 tmp, base + 10 + i, "");
7621 }
7622 }
7623 }
7624
7625 /* Force per-sample interpolation. */
7626 if (key->ps_prolog.states.force_persp_sample_interp) {
7627 unsigned i, base = key->ps_prolog.num_input_sgprs;
7628 LLVMValueRef persp_sample[2];
7629
7630 /* Read PERSP_SAMPLE. */
7631 for (i = 0; i < 2; i++)
7632 persp_sample[i] = LLVMGetParam(func, base + i);
7633 /* Overwrite PERSP_CENTER. */
7634 for (i = 0; i < 2; i++)
7635 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7636 persp_sample[i], base + 2 + i, "");
7637 /* Overwrite PERSP_CENTROID. */
7638 for (i = 0; i < 2; i++)
7639 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7640 persp_sample[i], base + 4 + i, "");
7641 }
7642 if (key->ps_prolog.states.force_linear_sample_interp) {
7643 unsigned i, base = key->ps_prolog.num_input_sgprs;
7644 LLVMValueRef linear_sample[2];
7645
7646 /* Read LINEAR_SAMPLE. */
7647 for (i = 0; i < 2; i++)
7648 linear_sample[i] = LLVMGetParam(func, base + 6 + i);
7649 /* Overwrite LINEAR_CENTER. */
7650 for (i = 0; i < 2; i++)
7651 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7652 linear_sample[i], base + 8 + i, "");
7653 /* Overwrite LINEAR_CENTROID. */
7654 for (i = 0; i < 2; i++)
7655 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7656 linear_sample[i], base + 10 + i, "");
7657 }
7658
7659 /* Force center interpolation. */
7660 if (key->ps_prolog.states.force_persp_center_interp) {
7661 unsigned i, base = key->ps_prolog.num_input_sgprs;
7662 LLVMValueRef persp_center[2];
7663
7664 /* Read PERSP_CENTER. */
7665 for (i = 0; i < 2; i++)
7666 persp_center[i] = LLVMGetParam(func, base + 2 + i);
7667 /* Overwrite PERSP_SAMPLE. */
7668 for (i = 0; i < 2; i++)
7669 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7670 persp_center[i], base + i, "");
7671 /* Overwrite PERSP_CENTROID. */
7672 for (i = 0; i < 2; i++)
7673 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7674 persp_center[i], base + 4 + i, "");
7675 }
7676 if (key->ps_prolog.states.force_linear_center_interp) {
7677 unsigned i, base = key->ps_prolog.num_input_sgprs;
7678 LLVMValueRef linear_center[2];
7679
7680 /* Read LINEAR_CENTER. */
7681 for (i = 0; i < 2; i++)
7682 linear_center[i] = LLVMGetParam(func, base + 8 + i);
7683 /* Overwrite LINEAR_SAMPLE. */
7684 for (i = 0; i < 2; i++)
7685 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7686 linear_center[i], base + 6 + i, "");
7687 /* Overwrite LINEAR_CENTROID. */
7688 for (i = 0; i < 2; i++)
7689 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7690 linear_center[i], base + 10 + i, "");
7691 }
7692
7693 /* Interpolate colors. */
7694 unsigned color_out_idx = 0;
7695 for (i = 0; i < 2; i++) {
7696 unsigned writemask = (key->ps_prolog.colors_read >> (i * 4)) & 0xf;
7697 unsigned face_vgpr = key->ps_prolog.num_input_sgprs +
7698 key->ps_prolog.face_vgpr_index;
7699 LLVMValueRef interp[2], color[4];
7700 LLVMValueRef interp_ij = NULL, prim_mask = NULL, face = NULL;
7701
7702 if (!writemask)
7703 continue;
7704
7705 /* If the interpolation qualifier is not CONSTANT (-1). */
7706 if (key->ps_prolog.color_interp_vgpr_index[i] != -1) {
7707 unsigned interp_vgpr = key->ps_prolog.num_input_sgprs +
7708 key->ps_prolog.color_interp_vgpr_index[i];
7709
7710 /* Get the (i,j) updated by bc_optimize handling. */
7711 interp[0] = LLVMBuildExtractValue(ctx->ac.builder, ret,
7712 interp_vgpr, "");
7713 interp[1] = LLVMBuildExtractValue(ctx->ac.builder, ret,
7714 interp_vgpr + 1, "");
7715 interp_ij = ac_build_gather_values(&ctx->ac, interp, 2);
7716 }
7717
7718 /* Use the absolute location of the input. */
7719 prim_mask = LLVMGetParam(func, SI_PS_NUM_USER_SGPR);
7720
7721 if (key->ps_prolog.states.color_two_side) {
7722 face = LLVMGetParam(func, face_vgpr);
7723 face = ac_to_integer(&ctx->ac, face);
7724 }
7725
7726 interp_fs_input(ctx,
7727 key->ps_prolog.color_attr_index[i],
7728 TGSI_SEMANTIC_COLOR, i,
7729 key->ps_prolog.num_interp_inputs,
7730 key->ps_prolog.colors_read, interp_ij,
7731 prim_mask, face, color);
7732
7733 while (writemask) {
7734 unsigned chan = u_bit_scan(&writemask);
7735 ret = LLVMBuildInsertValue(ctx->ac.builder, ret, color[chan],
7736 fninfo.num_params + color_out_idx++, "");
7737 }
7738 }
7739
7740 /* Section 15.2.2 (Shader Inputs) of the OpenGL 4.5 (Core Profile) spec
7741 * says:
7742 *
7743 * "When per-sample shading is active due to the use of a fragment
7744 * input qualified by sample or due to the use of the gl_SampleID
7745 * or gl_SamplePosition variables, only the bit for the current
7746 * sample is set in gl_SampleMaskIn. When state specifies multiple
7747 * fragment shader invocations for a given fragment, the sample
7748 * mask for any single fragment shader invocation may specify a
7749 * subset of the covered samples for the fragment. In this case,
7750 * the bit corresponding to each covered sample will be set in
7751 * exactly one fragment shader invocation."
7752 *
7753 * The samplemask loaded by hardware is always the coverage of the
7754 * entire pixel/fragment, so mask bits out based on the sample ID.
7755 */
7756 if (key->ps_prolog.states.samplemask_log_ps_iter) {
7757 /* The bit pattern matches that used by fixed function fragment
7758 * processing. */
7759 static const uint16_t ps_iter_masks[] = {
7760 0xffff, /* not used */
7761 0x5555,
7762 0x1111,
7763 0x0101,
7764 0x0001,
7765 };
7766 assert(key->ps_prolog.states.samplemask_log_ps_iter < ARRAY_SIZE(ps_iter_masks));
7767
7768 uint32_t ps_iter_mask = ps_iter_masks[key->ps_prolog.states.samplemask_log_ps_iter];
7769 unsigned ancillary_vgpr = key->ps_prolog.num_input_sgprs +
7770 key->ps_prolog.ancillary_vgpr_index;
7771 LLVMValueRef sampleid = si_unpack_param(ctx, ancillary_vgpr, 8, 4);
7772 LLVMValueRef samplemask = LLVMGetParam(func, ancillary_vgpr + 1);
7773
7774 samplemask = ac_to_integer(&ctx->ac, samplemask);
7775 samplemask = LLVMBuildAnd(
7776 ctx->ac.builder,
7777 samplemask,
7778 LLVMBuildShl(ctx->ac.builder,
7779 LLVMConstInt(ctx->i32, ps_iter_mask, false),
7780 sampleid, ""),
7781 "");
7782 samplemask = ac_to_float(&ctx->ac, samplemask);
7783
7784 ret = LLVMBuildInsertValue(ctx->ac.builder, ret, samplemask,
7785 ancillary_vgpr + 1, "");
7786 }
7787
7788 /* Tell LLVM to insert WQM instruction sequence when needed. */
7789 if (key->ps_prolog.wqm) {
7790 LLVMAddTargetDependentFunctionAttr(func,
7791 "amdgpu-ps-wqm-outputs", "");
7792 }
7793
7794 si_llvm_build_ret(ctx, ret);
7795 }
7796
7797 /**
7798 * Build the pixel shader epilog function. This handles everything that must be
7799 * emulated for pixel shader exports. (alpha-test, format conversions, etc)
7800 */
7801 static void si_build_ps_epilog_function(struct si_shader_context *ctx,
7802 union si_shader_part_key *key)
7803 {
7804 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
7805 struct si_function_info fninfo;
7806 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
7807 int i;
7808 struct si_ps_exports exp = {};
7809
7810 si_init_function_info(&fninfo);
7811
7812 /* Declare input SGPRs. */
7813 ctx->param_rw_buffers = add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7814 ctx->param_bindless_samplers_and_images = add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7815 ctx->param_const_and_shader_buffers = add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7816 ctx->param_samplers_and_images = add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7817 add_arg_checked(&fninfo, ARG_SGPR, ctx->f32, SI_PARAM_ALPHA_REF);
7818
7819 /* Declare input VGPRs. */
7820 unsigned required_num_params =
7821 fninfo.num_sgpr_params +
7822 util_bitcount(key->ps_epilog.colors_written) * 4 +
7823 key->ps_epilog.writes_z +
7824 key->ps_epilog.writes_stencil +
7825 key->ps_epilog.writes_samplemask;
7826
7827 required_num_params = MAX2(required_num_params,
7828 fninfo.num_sgpr_params + PS_EPILOG_SAMPLEMASK_MIN_LOC + 1);
7829
7830 while (fninfo.num_params < required_num_params)
7831 add_arg(&fninfo, ARG_VGPR, ctx->f32);
7832
7833 /* Create the function. */
7834 si_create_function(ctx, "ps_epilog", NULL, 0, &fninfo, 0);
7835 /* Disable elimination of unused inputs. */
7836 ac_llvm_add_target_dep_function_attr(ctx->main_fn,
7837 "InitialPSInputAddr", 0xffffff);
7838
7839 /* Process colors. */
7840 unsigned vgpr = fninfo.num_sgpr_params;
7841 unsigned colors_written = key->ps_epilog.colors_written;
7842 int last_color_export = -1;
7843
7844 /* Find the last color export. */
7845 if (!key->ps_epilog.writes_z &&
7846 !key->ps_epilog.writes_stencil &&
7847 !key->ps_epilog.writes_samplemask) {
7848 unsigned spi_format = key->ps_epilog.states.spi_shader_col_format;
7849
7850 /* If last_cbuf > 0, FS_COLOR0_WRITES_ALL_CBUFS is true. */
7851 if (colors_written == 0x1 && key->ps_epilog.states.last_cbuf > 0) {
7852 /* Just set this if any of the colorbuffers are enabled. */
7853 if (spi_format &
7854 ((1ull << (4 * (key->ps_epilog.states.last_cbuf + 1))) - 1))
7855 last_color_export = 0;
7856 } else {
7857 for (i = 0; i < 8; i++)
7858 if (colors_written & (1 << i) &&
7859 (spi_format >> (i * 4)) & 0xf)
7860 last_color_export = i;
7861 }
7862 }
7863
7864 while (colors_written) {
7865 LLVMValueRef color[4];
7866 int mrt = u_bit_scan(&colors_written);
7867
7868 for (i = 0; i < 4; i++)
7869 color[i] = LLVMGetParam(ctx->main_fn, vgpr++);
7870
7871 si_export_mrt_color(bld_base, color, mrt,
7872 fninfo.num_params - 1,
7873 mrt == last_color_export, &exp);
7874 }
7875
7876 /* Process depth, stencil, samplemask. */
7877 if (key->ps_epilog.writes_z)
7878 depth = LLVMGetParam(ctx->main_fn, vgpr++);
7879 if (key->ps_epilog.writes_stencil)
7880 stencil = LLVMGetParam(ctx->main_fn, vgpr++);
7881 if (key->ps_epilog.writes_samplemask)
7882 samplemask = LLVMGetParam(ctx->main_fn, vgpr++);
7883
7884 if (depth || stencil || samplemask)
7885 si_export_mrt_z(bld_base, depth, stencil, samplemask, &exp);
7886 else if (last_color_export == -1)
7887 ac_build_export_null(&ctx->ac);
7888
7889 if (exp.num)
7890 si_emit_ps_exports(ctx, &exp);
7891
7892 /* Compile. */
7893 LLVMBuildRetVoid(ctx->ac.builder);
7894 }
7895
7896 /**
7897 * Select and compile (or reuse) pixel shader parts (prolog & epilog).
7898 */
7899 static bool si_shader_select_ps_parts(struct si_screen *sscreen,
7900 struct ac_llvm_compiler *compiler,
7901 struct si_shader *shader,
7902 struct pipe_debug_callback *debug)
7903 {
7904 union si_shader_part_key prolog_key;
7905 union si_shader_part_key epilog_key;
7906
7907 /* Get the prolog. */
7908 si_get_ps_prolog_key(shader, &prolog_key, true);
7909
7910 /* The prolog is a no-op if these aren't set. */
7911 if (si_need_ps_prolog(&prolog_key)) {
7912 shader->prolog =
7913 si_get_shader_part(sscreen, &sscreen->ps_prologs,
7914 PIPE_SHADER_FRAGMENT, true,
7915 &prolog_key, compiler, debug,
7916 si_build_ps_prolog_function,
7917 "Fragment Shader Prolog");
7918 if (!shader->prolog)
7919 return false;
7920 }
7921
7922 /* Get the epilog. */
7923 si_get_ps_epilog_key(shader, &epilog_key);
7924
7925 shader->epilog =
7926 si_get_shader_part(sscreen, &sscreen->ps_epilogs,
7927 PIPE_SHADER_FRAGMENT, false,
7928 &epilog_key, compiler, debug,
7929 si_build_ps_epilog_function,
7930 "Fragment Shader Epilog");
7931 if (!shader->epilog)
7932 return false;
7933
7934 /* Enable POS_FIXED_PT if polygon stippling is enabled. */
7935 if (shader->key.part.ps.prolog.poly_stipple) {
7936 shader->config.spi_ps_input_ena |= S_0286CC_POS_FIXED_PT_ENA(1);
7937 assert(G_0286CC_POS_FIXED_PT_ENA(shader->config.spi_ps_input_addr));
7938 }
7939
7940 /* Set up the enable bits for per-sample shading if needed. */
7941 if (shader->key.part.ps.prolog.force_persp_sample_interp &&
7942 (G_0286CC_PERSP_CENTER_ENA(shader->config.spi_ps_input_ena) ||
7943 G_0286CC_PERSP_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
7944 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_CENTER_ENA;
7945 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_CENTROID_ENA;
7946 shader->config.spi_ps_input_ena |= S_0286CC_PERSP_SAMPLE_ENA(1);
7947 }
7948 if (shader->key.part.ps.prolog.force_linear_sample_interp &&
7949 (G_0286CC_LINEAR_CENTER_ENA(shader->config.spi_ps_input_ena) ||
7950 G_0286CC_LINEAR_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
7951 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_CENTER_ENA;
7952 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_CENTROID_ENA;
7953 shader->config.spi_ps_input_ena |= S_0286CC_LINEAR_SAMPLE_ENA(1);
7954 }
7955 if (shader->key.part.ps.prolog.force_persp_center_interp &&
7956 (G_0286CC_PERSP_SAMPLE_ENA(shader->config.spi_ps_input_ena) ||
7957 G_0286CC_PERSP_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
7958 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_SAMPLE_ENA;
7959 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_CENTROID_ENA;
7960 shader->config.spi_ps_input_ena |= S_0286CC_PERSP_CENTER_ENA(1);
7961 }
7962 if (shader->key.part.ps.prolog.force_linear_center_interp &&
7963 (G_0286CC_LINEAR_SAMPLE_ENA(shader->config.spi_ps_input_ena) ||
7964 G_0286CC_LINEAR_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
7965 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_SAMPLE_ENA;
7966 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_CENTROID_ENA;
7967 shader->config.spi_ps_input_ena |= S_0286CC_LINEAR_CENTER_ENA(1);
7968 }
7969
7970 /* POW_W_FLOAT requires that one of the perspective weights is enabled. */
7971 if (G_0286CC_POS_W_FLOAT_ENA(shader->config.spi_ps_input_ena) &&
7972 !(shader->config.spi_ps_input_ena & 0xf)) {
7973 shader->config.spi_ps_input_ena |= S_0286CC_PERSP_CENTER_ENA(1);
7974 assert(G_0286CC_PERSP_CENTER_ENA(shader->config.spi_ps_input_addr));
7975 }
7976
7977 /* At least one pair of interpolation weights must be enabled. */
7978 if (!(shader->config.spi_ps_input_ena & 0x7f)) {
7979 shader->config.spi_ps_input_ena |= S_0286CC_LINEAR_CENTER_ENA(1);
7980 assert(G_0286CC_LINEAR_CENTER_ENA(shader->config.spi_ps_input_addr));
7981 }
7982
7983 /* Samplemask fixup requires the sample ID. */
7984 if (shader->key.part.ps.prolog.samplemask_log_ps_iter) {
7985 shader->config.spi_ps_input_ena |= S_0286CC_ANCILLARY_ENA(1);
7986 assert(G_0286CC_ANCILLARY_ENA(shader->config.spi_ps_input_addr));
7987 }
7988
7989 /* The sample mask input is always enabled, because the API shader always
7990 * passes it through to the epilog. Disable it here if it's unused.
7991 */
7992 if (!shader->key.part.ps.epilog.poly_line_smoothing &&
7993 !shader->selector->info.reads_samplemask)
7994 shader->config.spi_ps_input_ena &= C_0286CC_SAMPLE_COVERAGE_ENA;
7995
7996 return true;
7997 }
7998
7999 void si_multiwave_lds_size_workaround(struct si_screen *sscreen,
8000 unsigned *lds_size)
8001 {
8002 /* If tessellation is all offchip and on-chip GS isn't used, this
8003 * workaround is not needed.
8004 */
8005 return;
8006
8007 /* SPI barrier management bug:
8008 * Make sure we have at least 4k of LDS in use to avoid the bug.
8009 * It applies to workgroup sizes of more than one wavefront.
8010 */
8011 if (sscreen->info.family == CHIP_BONAIRE ||
8012 sscreen->info.family == CHIP_KABINI ||
8013 sscreen->info.family == CHIP_MULLINS)
8014 *lds_size = MAX2(*lds_size, 8);
8015 }
8016
8017 static void si_fix_resource_usage(struct si_screen *sscreen,
8018 struct si_shader *shader)
8019 {
8020 unsigned min_sgprs = shader->info.num_input_sgprs + 2; /* VCC */
8021
8022 shader->config.num_sgprs = MAX2(shader->config.num_sgprs, min_sgprs);
8023
8024 if (shader->selector->type == PIPE_SHADER_COMPUTE &&
8025 si_get_max_workgroup_size(shader) > 64) {
8026 si_multiwave_lds_size_workaround(sscreen,
8027 &shader->config.lds_size);
8028 }
8029 }
8030
8031 int si_shader_create(struct si_screen *sscreen, struct ac_llvm_compiler *compiler,
8032 struct si_shader *shader,
8033 struct pipe_debug_callback *debug)
8034 {
8035 struct si_shader_selector *sel = shader->selector;
8036 struct si_shader *mainp = *si_get_main_shader_part(sel, &shader->key);
8037 int r;
8038
8039 /* LS, ES, VS are compiled on demand if the main part hasn't been
8040 * compiled for that stage.
8041 *
8042 * Vertex shaders are compiled on demand when a vertex fetch
8043 * workaround must be applied.
8044 */
8045 if (shader->is_monolithic) {
8046 /* Monolithic shader (compiled as a whole, has many variants,
8047 * may take a long time to compile).
8048 */
8049 r = si_compile_tgsi_shader(sscreen, compiler, shader, debug);
8050 if (r)
8051 return r;
8052 } else {
8053 /* The shader consists of several parts:
8054 *
8055 * - the middle part is the user shader, it has 1 variant only
8056 * and it was compiled during the creation of the shader
8057 * selector
8058 * - the prolog part is inserted at the beginning
8059 * - the epilog part is inserted at the end
8060 *
8061 * The prolog and epilog have many (but simple) variants.
8062 *
8063 * Starting with gfx9, geometry and tessellation control
8064 * shaders also contain the prolog and user shader parts of
8065 * the previous shader stage.
8066 */
8067
8068 if (!mainp)
8069 return -1;
8070
8071 /* Copy the compiled TGSI shader data over. */
8072 shader->is_binary_shared = true;
8073 shader->binary = mainp->binary;
8074 shader->config = mainp->config;
8075 shader->info.num_input_sgprs = mainp->info.num_input_sgprs;
8076 shader->info.num_input_vgprs = mainp->info.num_input_vgprs;
8077 shader->info.face_vgpr_index = mainp->info.face_vgpr_index;
8078 shader->info.ancillary_vgpr_index = mainp->info.ancillary_vgpr_index;
8079 memcpy(shader->info.vs_output_param_offset,
8080 mainp->info.vs_output_param_offset,
8081 sizeof(mainp->info.vs_output_param_offset));
8082 shader->info.uses_instanceid = mainp->info.uses_instanceid;
8083 shader->info.nr_pos_exports = mainp->info.nr_pos_exports;
8084 shader->info.nr_param_exports = mainp->info.nr_param_exports;
8085
8086 /* Select prologs and/or epilogs. */
8087 switch (sel->type) {
8088 case PIPE_SHADER_VERTEX:
8089 if (!si_shader_select_vs_parts(sscreen, compiler, shader, debug))
8090 return -1;
8091 break;
8092 case PIPE_SHADER_TESS_CTRL:
8093 if (!si_shader_select_tcs_parts(sscreen, compiler, shader, debug))
8094 return -1;
8095 break;
8096 case PIPE_SHADER_TESS_EVAL:
8097 break;
8098 case PIPE_SHADER_GEOMETRY:
8099 if (!si_shader_select_gs_parts(sscreen, compiler, shader, debug))
8100 return -1;
8101 break;
8102 case PIPE_SHADER_FRAGMENT:
8103 if (!si_shader_select_ps_parts(sscreen, compiler, shader, debug))
8104 return -1;
8105
8106 /* Make sure we have at least as many VGPRs as there
8107 * are allocated inputs.
8108 */
8109 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
8110 shader->info.num_input_vgprs);
8111 break;
8112 }
8113
8114 /* Update SGPR and VGPR counts. */
8115 if (shader->prolog) {
8116 shader->config.num_sgprs = MAX2(shader->config.num_sgprs,
8117 shader->prolog->config.num_sgprs);
8118 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
8119 shader->prolog->config.num_vgprs);
8120 }
8121 if (shader->previous_stage) {
8122 shader->config.num_sgprs = MAX2(shader->config.num_sgprs,
8123 shader->previous_stage->config.num_sgprs);
8124 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
8125 shader->previous_stage->config.num_vgprs);
8126 shader->config.spilled_sgprs =
8127 MAX2(shader->config.spilled_sgprs,
8128 shader->previous_stage->config.spilled_sgprs);
8129 shader->config.spilled_vgprs =
8130 MAX2(shader->config.spilled_vgprs,
8131 shader->previous_stage->config.spilled_vgprs);
8132 shader->config.private_mem_vgprs =
8133 MAX2(shader->config.private_mem_vgprs,
8134 shader->previous_stage->config.private_mem_vgprs);
8135 shader->config.scratch_bytes_per_wave =
8136 MAX2(shader->config.scratch_bytes_per_wave,
8137 shader->previous_stage->config.scratch_bytes_per_wave);
8138 shader->info.uses_instanceid |=
8139 shader->previous_stage->info.uses_instanceid;
8140 }
8141 if (shader->prolog2) {
8142 shader->config.num_sgprs = MAX2(shader->config.num_sgprs,
8143 shader->prolog2->config.num_sgprs);
8144 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
8145 shader->prolog2->config.num_vgprs);
8146 }
8147 if (shader->epilog) {
8148 shader->config.num_sgprs = MAX2(shader->config.num_sgprs,
8149 shader->epilog->config.num_sgprs);
8150 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
8151 shader->epilog->config.num_vgprs);
8152 }
8153 si_calculate_max_simd_waves(shader);
8154 }
8155
8156 si_fix_resource_usage(sscreen, shader);
8157 si_shader_dump(sscreen, shader, debug, sel->info.processor,
8158 stderr, true);
8159
8160 /* Upload. */
8161 r = si_shader_binary_upload(sscreen, shader);
8162 if (r) {
8163 fprintf(stderr, "LLVM failed to upload shader\n");
8164 return r;
8165 }
8166
8167 return 0;
8168 }
8169
8170 void si_shader_destroy(struct si_shader *shader)
8171 {
8172 if (shader->scratch_bo)
8173 r600_resource_reference(&shader->scratch_bo, NULL);
8174
8175 r600_resource_reference(&shader->bo, NULL);
8176
8177 if (!shader->is_binary_shared)
8178 ac_shader_binary_clean(&shader->binary);
8179
8180 free(shader->shader_log);
8181 }