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radeonsi: implement VERTEXID_NOBASE and BASEVERTEX system values
[mesa.git] / src / gallium / drivers / radeonsi / si_shader.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Tom Stellard <thomas.stellard@amd.com>
25 * Michel Dänzer <michel.daenzer@amd.com>
26 * Christian König <christian.koenig@amd.com>
27 */
28
29 #include "gallivm/lp_bld_const.h"
30 #include "gallivm/lp_bld_gather.h"
31 #include "gallivm/lp_bld_intr.h"
32 #include "gallivm/lp_bld_logic.h"
33 #include "gallivm/lp_bld_arit.h"
34 #include "gallivm/lp_bld_flow.h"
35 #include "radeon/radeon_llvm.h"
36 #include "radeon/radeon_elf_util.h"
37 #include "radeon/radeon_llvm_emit.h"
38 #include "util/u_memory.h"
39 #include "tgsi/tgsi_parse.h"
40 #include "tgsi/tgsi_util.h"
41 #include "tgsi/tgsi_dump.h"
42
43 #include "si_pipe.h"
44 #include "si_shader.h"
45 #include "sid.h"
46
47 #include <errno.h>
48
49 struct si_shader_output_values
50 {
51 LLVMValueRef values[4];
52 unsigned name;
53 unsigned sid;
54 };
55
56 struct si_shader_context
57 {
58 struct radeon_llvm_context radeon_bld;
59 struct tgsi_parse_context parse;
60 struct tgsi_token * tokens;
61 struct si_shader *shader;
62 struct si_screen *screen;
63 unsigned type; /* TGSI_PROCESSOR_* specifies the type of shader. */
64 int param_streamout_config;
65 int param_streamout_write_index;
66 int param_streamout_offset[4];
67 int param_vertex_id;
68 int param_instance_id;
69 LLVMValueRef const_md;
70 LLVMValueRef const_resource[SI_NUM_CONST_BUFFERS];
71 LLVMValueRef ddxy_lds;
72 LLVMValueRef *constants[SI_NUM_CONST_BUFFERS];
73 LLVMValueRef resources[SI_NUM_SAMPLER_VIEWS];
74 LLVMValueRef samplers[SI_NUM_SAMPLER_STATES];
75 LLVMValueRef so_buffers[4];
76 LLVMValueRef esgs_ring;
77 LLVMValueRef gsvs_ring;
78 LLVMValueRef gs_next_vertex;
79 };
80
81 static struct si_shader_context * si_shader_context(
82 struct lp_build_tgsi_context * bld_base)
83 {
84 return (struct si_shader_context *)bld_base;
85 }
86
87
88 #define PERSPECTIVE_BASE 0
89 #define LINEAR_BASE 9
90
91 #define SAMPLE_OFFSET 0
92 #define CENTER_OFFSET 2
93 #define CENTROID_OFSET 4
94
95 #define USE_SGPR_MAX_SUFFIX_LEN 5
96 #define CONST_ADDR_SPACE 2
97 #define LOCAL_ADDR_SPACE 3
98 #define USER_SGPR_ADDR_SPACE 8
99
100
101 #define SENDMSG_GS 2
102 #define SENDMSG_GS_DONE 3
103
104 #define SENDMSG_GS_OP_NOP (0 << 4)
105 #define SENDMSG_GS_OP_CUT (1 << 4)
106 #define SENDMSG_GS_OP_EMIT (2 << 4)
107 #define SENDMSG_GS_OP_EMIT_CUT (3 << 4)
108
109 /**
110 * Returns a unique index for a semantic name and index. The index must be
111 * less than 64, so that a 64-bit bitmask of used inputs or outputs can be
112 * calculated.
113 */
114 unsigned si_shader_io_get_unique_index(unsigned semantic_name, unsigned index)
115 {
116 switch (semantic_name) {
117 case TGSI_SEMANTIC_POSITION:
118 return 0;
119 case TGSI_SEMANTIC_PSIZE:
120 return 1;
121 case TGSI_SEMANTIC_CLIPDIST:
122 assert(index <= 1);
123 return 2 + index;
124 case TGSI_SEMANTIC_CLIPVERTEX:
125 return 4;
126 case TGSI_SEMANTIC_COLOR:
127 assert(index <= 1);
128 return 5 + index;
129 case TGSI_SEMANTIC_BCOLOR:
130 assert(index <= 1);
131 return 7 + index;
132 case TGSI_SEMANTIC_FOG:
133 return 9;
134 case TGSI_SEMANTIC_EDGEFLAG:
135 return 10;
136 case TGSI_SEMANTIC_GENERIC:
137 assert(index <= 63-11);
138 return 11 + index;
139 default:
140 assert(0);
141 return 63;
142 }
143 }
144
145 /**
146 * Given a semantic name and index of a parameter and a mask of used parameters
147 * (inputs or outputs), return the index of the parameter in the list of all
148 * used parameters.
149 *
150 * For example, assume this list of parameters:
151 * POSITION, PSIZE, GENERIC0, GENERIC2
152 * which has the mask:
153 * 11000000000101
154 * Then:
155 * querying POSITION returns 0,
156 * querying PSIZE returns 1,
157 * querying GENERIC0 returns 2,
158 * querying GENERIC2 returns 3.
159 *
160 * Which can be used as an offset to a parameter buffer in units of vec4s.
161 */
162 static int get_param_index(unsigned semantic_name, unsigned index,
163 uint64_t mask)
164 {
165 unsigned unique_index = si_shader_io_get_unique_index(semantic_name, index);
166 int i, param_index = 0;
167
168 /* If not present... */
169 if (!((1llu << unique_index) & mask))
170 return -1;
171
172 for (i = 0; mask; i++) {
173 uint64_t bit = 1llu << i;
174
175 if (bit & mask) {
176 if (i == unique_index)
177 return param_index;
178
179 mask &= ~bit;
180 param_index++;
181 }
182 }
183
184 assert(!"unreachable");
185 return -1;
186 }
187
188 /**
189 * Build an LLVM bytecode indexed load using LLVMBuildGEP + LLVMBuildLoad.
190 * It's equivalent to doing a load from &base_ptr[index].
191 *
192 * \param base_ptr Where the array starts.
193 * \param index The element index into the array.
194 */
195 static LLVMValueRef build_indexed_load(struct si_shader_context *si_shader_ctx,
196 LLVMValueRef base_ptr, LLVMValueRef index)
197 {
198 struct lp_build_tgsi_context *bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
199 struct gallivm_state *gallivm = bld_base->base.gallivm;
200 LLVMValueRef indices[2], pointer;
201
202 indices[0] = bld_base->uint_bld.zero;
203 indices[1] = index;
204
205 pointer = LLVMBuildGEP(gallivm->builder, base_ptr, indices, 2, "");
206 return LLVMBuildLoad(gallivm->builder, pointer, "");
207 }
208
209 /**
210 * Do a load from &base_ptr[index], but also add a flag that it's loading
211 * a constant.
212 */
213 static LLVMValueRef build_indexed_load_const(
214 struct si_shader_context * si_shader_ctx,
215 LLVMValueRef base_ptr, LLVMValueRef index)
216 {
217 LLVMValueRef result = build_indexed_load(si_shader_ctx, base_ptr, index);
218 LLVMSetMetadata(result, 1, si_shader_ctx->const_md);
219 return result;
220 }
221
222 static LLVMValueRef get_instance_index_for_fetch(
223 struct radeon_llvm_context * radeon_bld,
224 unsigned divisor)
225 {
226 struct si_shader_context *si_shader_ctx =
227 si_shader_context(&radeon_bld->soa.bld_base);
228 struct gallivm_state * gallivm = radeon_bld->soa.bld_base.base.gallivm;
229
230 LLVMValueRef result = LLVMGetParam(radeon_bld->main_fn,
231 si_shader_ctx->param_instance_id);
232 result = LLVMBuildAdd(gallivm->builder, result, LLVMGetParam(
233 radeon_bld->main_fn, SI_PARAM_START_INSTANCE), "");
234
235 if (divisor > 1)
236 result = LLVMBuildUDiv(gallivm->builder, result,
237 lp_build_const_int32(gallivm, divisor), "");
238
239 return result;
240 }
241
242 static void declare_input_vs(
243 struct radeon_llvm_context *radeon_bld,
244 unsigned input_index,
245 const struct tgsi_full_declaration *decl)
246 {
247 struct lp_build_context *base = &radeon_bld->soa.bld_base.base;
248 struct gallivm_state *gallivm = base->gallivm;
249 struct si_shader_context *si_shader_ctx =
250 si_shader_context(&radeon_bld->soa.bld_base);
251 unsigned divisor = si_shader_ctx->shader->key.vs.instance_divisors[input_index];
252
253 unsigned chan;
254
255 LLVMValueRef t_list_ptr;
256 LLVMValueRef t_offset;
257 LLVMValueRef t_list;
258 LLVMValueRef attribute_offset;
259 LLVMValueRef buffer_index;
260 LLVMValueRef args[3];
261 LLVMTypeRef vec4_type;
262 LLVMValueRef input;
263
264 /* Load the T list */
265 t_list_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_VERTEX_BUFFER);
266
267 t_offset = lp_build_const_int32(gallivm, input_index);
268
269 t_list = build_indexed_load_const(si_shader_ctx, t_list_ptr, t_offset);
270
271 /* Build the attribute offset */
272 attribute_offset = lp_build_const_int32(gallivm, 0);
273
274 if (divisor) {
275 /* Build index from instance ID, start instance and divisor */
276 si_shader_ctx->shader->uses_instanceid = true;
277 buffer_index = get_instance_index_for_fetch(&si_shader_ctx->radeon_bld, divisor);
278 } else {
279 /* Load the buffer index for vertices. */
280 LLVMValueRef vertex_id = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
281 si_shader_ctx->param_vertex_id);
282 LLVMValueRef base_vertex = LLVMGetParam(radeon_bld->main_fn,
283 SI_PARAM_BASE_VERTEX);
284 buffer_index = LLVMBuildAdd(gallivm->builder, base_vertex, vertex_id, "");
285 }
286
287 vec4_type = LLVMVectorType(base->elem_type, 4);
288 args[0] = t_list;
289 args[1] = attribute_offset;
290 args[2] = buffer_index;
291 input = build_intrinsic(gallivm->builder,
292 "llvm.SI.vs.load.input", vec4_type, args, 3,
293 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
294
295 /* Break up the vec4 into individual components */
296 for (chan = 0; chan < 4; chan++) {
297 LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan);
298 /* XXX: Use a helper function for this. There is one in
299 * tgsi_llvm.c. */
300 si_shader_ctx->radeon_bld.inputs[radeon_llvm_reg_index_soa(input_index, chan)] =
301 LLVMBuildExtractElement(gallivm->builder,
302 input, llvm_chan, "");
303 }
304 }
305
306 static LLVMValueRef fetch_input_gs(
307 struct lp_build_tgsi_context *bld_base,
308 const struct tgsi_full_src_register *reg,
309 enum tgsi_opcode_type type,
310 unsigned swizzle)
311 {
312 struct lp_build_context *base = &bld_base->base;
313 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
314 struct si_shader *shader = si_shader_ctx->shader;
315 struct lp_build_context *uint = &si_shader_ctx->radeon_bld.soa.bld_base.uint_bld;
316 struct gallivm_state *gallivm = base->gallivm;
317 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
318 LLVMValueRef vtx_offset;
319 LLVMValueRef args[9];
320 unsigned vtx_offset_param;
321 struct tgsi_shader_info *info = &shader->selector->info;
322 unsigned semantic_name = info->input_semantic_name[reg->Register.Index];
323 unsigned semantic_index = info->input_semantic_index[reg->Register.Index];
324
325 if (swizzle != ~0 && semantic_name == TGSI_SEMANTIC_PRIMID) {
326 if (swizzle == 0)
327 return LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
328 SI_PARAM_PRIMITIVE_ID);
329 else
330 return uint->zero;
331 }
332
333 if (!reg->Register.Dimension)
334 return NULL;
335
336 if (swizzle == ~0) {
337 LLVMValueRef values[TGSI_NUM_CHANNELS];
338 unsigned chan;
339 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
340 values[chan] = fetch_input_gs(bld_base, reg, type, chan);
341 }
342 return lp_build_gather_values(bld_base->base.gallivm, values,
343 TGSI_NUM_CHANNELS);
344 }
345
346 /* Get the vertex offset parameter */
347 vtx_offset_param = reg->Dimension.Index;
348 if (vtx_offset_param < 2) {
349 vtx_offset_param += SI_PARAM_VTX0_OFFSET;
350 } else {
351 assert(vtx_offset_param < 6);
352 vtx_offset_param += SI_PARAM_VTX2_OFFSET - 2;
353 }
354 vtx_offset = lp_build_mul_imm(uint,
355 LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
356 vtx_offset_param),
357 4);
358
359 args[0] = si_shader_ctx->esgs_ring;
360 args[1] = vtx_offset;
361 args[2] = lp_build_const_int32(gallivm,
362 (get_param_index(semantic_name, semantic_index,
363 shader->selector->gs_used_inputs) * 4 +
364 swizzle) * 256);
365 args[3] = uint->zero;
366 args[4] = uint->one; /* OFFEN */
367 args[5] = uint->zero; /* IDXEN */
368 args[6] = uint->one; /* GLC */
369 args[7] = uint->zero; /* SLC */
370 args[8] = uint->zero; /* TFE */
371
372 return LLVMBuildBitCast(gallivm->builder,
373 build_intrinsic(gallivm->builder,
374 "llvm.SI.buffer.load.dword.i32.i32",
375 i32, args, 9,
376 LLVMReadOnlyAttribute | LLVMNoUnwindAttribute),
377 tgsi2llvmtype(bld_base, type), "");
378 }
379
380 static void declare_input_fs(
381 struct radeon_llvm_context *radeon_bld,
382 unsigned input_index,
383 const struct tgsi_full_declaration *decl)
384 {
385 struct lp_build_context *base = &radeon_bld->soa.bld_base.base;
386 struct si_shader_context *si_shader_ctx =
387 si_shader_context(&radeon_bld->soa.bld_base);
388 struct si_shader *shader = si_shader_ctx->shader;
389 struct lp_build_context *uint = &radeon_bld->soa.bld_base.uint_bld;
390 struct gallivm_state *gallivm = base->gallivm;
391 LLVMTypeRef input_type = LLVMFloatTypeInContext(gallivm->context);
392 LLVMValueRef main_fn = radeon_bld->main_fn;
393
394 LLVMValueRef interp_param;
395 const char * intr_name;
396
397 /* This value is:
398 * [15:0] NewPrimMask (Bit mask for each quad. It is set it the
399 * quad begins a new primitive. Bit 0 always needs
400 * to be unset)
401 * [32:16] ParamOffset
402 *
403 */
404 LLVMValueRef params = LLVMGetParam(main_fn, SI_PARAM_PRIM_MASK);
405 LLVMValueRef attr_number;
406
407 unsigned chan;
408
409 if (decl->Semantic.Name == TGSI_SEMANTIC_POSITION) {
410 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
411 unsigned soa_index =
412 radeon_llvm_reg_index_soa(input_index, chan);
413 radeon_bld->inputs[soa_index] =
414 LLVMGetParam(main_fn, SI_PARAM_POS_X_FLOAT + chan);
415
416 if (chan == 3)
417 /* RCP for fragcoord.w */
418 radeon_bld->inputs[soa_index] =
419 LLVMBuildFDiv(gallivm->builder,
420 lp_build_const_float(gallivm, 1.0f),
421 radeon_bld->inputs[soa_index],
422 "");
423 }
424 return;
425 }
426
427 if (decl->Semantic.Name == TGSI_SEMANTIC_FACE) {
428 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 0)] =
429 LLVMGetParam(main_fn, SI_PARAM_FRONT_FACE);
430 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 1)] =
431 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 2)] =
432 lp_build_const_float(gallivm, 0.0f);
433 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 3)] =
434 lp_build_const_float(gallivm, 1.0f);
435
436 return;
437 }
438
439 shader->ps_input_param_offset[input_index] = shader->nparam++;
440 attr_number = lp_build_const_int32(gallivm,
441 shader->ps_input_param_offset[input_index]);
442
443 switch (decl->Interp.Interpolate) {
444 case TGSI_INTERPOLATE_CONSTANT:
445 interp_param = 0;
446 break;
447 case TGSI_INTERPOLATE_LINEAR:
448 if (decl->Interp.Location == TGSI_INTERPOLATE_LOC_SAMPLE)
449 interp_param = LLVMGetParam(main_fn, SI_PARAM_LINEAR_SAMPLE);
450 else if (decl->Interp.Location == TGSI_INTERPOLATE_LOC_CENTROID)
451 interp_param = LLVMGetParam(main_fn, SI_PARAM_LINEAR_CENTROID);
452 else
453 interp_param = LLVMGetParam(main_fn, SI_PARAM_LINEAR_CENTER);
454 break;
455 case TGSI_INTERPOLATE_COLOR:
456 if (si_shader_ctx->shader->key.ps.flatshade) {
457 interp_param = 0;
458 break;
459 }
460 /* fall through to perspective */
461 case TGSI_INTERPOLATE_PERSPECTIVE:
462 if (decl->Interp.Location == TGSI_INTERPOLATE_LOC_SAMPLE)
463 interp_param = LLVMGetParam(main_fn, SI_PARAM_PERSP_SAMPLE);
464 else if (decl->Interp.Location == TGSI_INTERPOLATE_LOC_CENTROID)
465 interp_param = LLVMGetParam(main_fn, SI_PARAM_PERSP_CENTROID);
466 else
467 interp_param = LLVMGetParam(main_fn, SI_PARAM_PERSP_CENTER);
468 break;
469 default:
470 fprintf(stderr, "Warning: Unhandled interpolation mode.\n");
471 return;
472 }
473
474 intr_name = interp_param ? "llvm.SI.fs.interp" : "llvm.SI.fs.constant";
475
476 /* XXX: Could there be more than TGSI_NUM_CHANNELS (4) ? */
477 if (decl->Semantic.Name == TGSI_SEMANTIC_COLOR &&
478 si_shader_ctx->shader->key.ps.color_two_side) {
479 LLVMValueRef args[4];
480 LLVMValueRef face, is_face_positive;
481 LLVMValueRef back_attr_number =
482 lp_build_const_int32(gallivm,
483 shader->ps_input_param_offset[input_index] + 1);
484
485 face = LLVMGetParam(main_fn, SI_PARAM_FRONT_FACE);
486
487 is_face_positive = LLVMBuildFCmp(gallivm->builder,
488 LLVMRealOGT, face,
489 lp_build_const_float(gallivm, 0.0f),
490 "");
491
492 args[2] = params;
493 args[3] = interp_param;
494 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
495 LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan);
496 unsigned soa_index = radeon_llvm_reg_index_soa(input_index, chan);
497 LLVMValueRef front, back;
498
499 args[0] = llvm_chan;
500 args[1] = attr_number;
501 front = build_intrinsic(gallivm->builder, intr_name,
502 input_type, args, args[3] ? 4 : 3,
503 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
504
505 args[1] = back_attr_number;
506 back = build_intrinsic(gallivm->builder, intr_name,
507 input_type, args, args[3] ? 4 : 3,
508 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
509
510 radeon_bld->inputs[soa_index] =
511 LLVMBuildSelect(gallivm->builder,
512 is_face_positive,
513 front,
514 back,
515 "");
516 }
517
518 shader->nparam++;
519 } else if (decl->Semantic.Name == TGSI_SEMANTIC_FOG) {
520 LLVMValueRef args[4];
521
522 args[0] = uint->zero;
523 args[1] = attr_number;
524 args[2] = params;
525 args[3] = interp_param;
526 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 0)] =
527 build_intrinsic(gallivm->builder, intr_name,
528 input_type, args, args[3] ? 4 : 3,
529 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
530 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 1)] =
531 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 2)] =
532 lp_build_const_float(gallivm, 0.0f);
533 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 3)] =
534 lp_build_const_float(gallivm, 1.0f);
535 } else {
536 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
537 LLVMValueRef args[4];
538 LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan);
539 unsigned soa_index = radeon_llvm_reg_index_soa(input_index, chan);
540 args[0] = llvm_chan;
541 args[1] = attr_number;
542 args[2] = params;
543 args[3] = interp_param;
544 radeon_bld->inputs[soa_index] =
545 build_intrinsic(gallivm->builder, intr_name,
546 input_type, args, args[3] ? 4 : 3,
547 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
548 }
549 }
550 }
551
552 static LLVMValueRef get_sample_id(struct radeon_llvm_context *radeon_bld)
553 {
554 struct gallivm_state *gallivm = &radeon_bld->gallivm;
555 LLVMValueRef value = LLVMGetParam(radeon_bld->main_fn,
556 SI_PARAM_ANCILLARY);
557 value = LLVMBuildLShr(gallivm->builder, value,
558 lp_build_const_int32(gallivm, 8), "");
559 value = LLVMBuildAnd(gallivm->builder, value,
560 lp_build_const_int32(gallivm, 0xf), "");
561 return value;
562 }
563
564 /**
565 * Load a dword from a constant buffer.
566 */
567 static LLVMValueRef buffer_load_const(LLVMBuilderRef builder, LLVMValueRef resource,
568 LLVMValueRef offset, LLVMTypeRef return_type)
569 {
570 LLVMValueRef args[2] = {resource, offset};
571
572 return build_intrinsic(builder, "llvm.SI.load.const", return_type, args, 2,
573 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
574 }
575
576 static void declare_system_value(
577 struct radeon_llvm_context * radeon_bld,
578 unsigned index,
579 const struct tgsi_full_declaration *decl)
580 {
581 struct si_shader_context *si_shader_ctx =
582 si_shader_context(&radeon_bld->soa.bld_base);
583 struct lp_build_context *uint_bld = &radeon_bld->soa.bld_base.uint_bld;
584 struct gallivm_state *gallivm = &radeon_bld->gallivm;
585 LLVMValueRef value = 0;
586
587 switch (decl->Semantic.Name) {
588 case TGSI_SEMANTIC_INSTANCEID:
589 value = LLVMGetParam(radeon_bld->main_fn,
590 si_shader_ctx->param_instance_id);
591 break;
592
593 case TGSI_SEMANTIC_VERTEXID:
594 value = LLVMBuildAdd(gallivm->builder,
595 LLVMGetParam(radeon_bld->main_fn,
596 si_shader_ctx->param_vertex_id),
597 LLVMGetParam(radeon_bld->main_fn,
598 SI_PARAM_BASE_VERTEX), "");
599 break;
600
601 case TGSI_SEMANTIC_VERTEXID_NOBASE:
602 value = LLVMGetParam(radeon_bld->main_fn,
603 si_shader_ctx->param_vertex_id);
604 break;
605
606 case TGSI_SEMANTIC_BASEVERTEX:
607 value = LLVMGetParam(radeon_bld->main_fn,
608 SI_PARAM_BASE_VERTEX);
609 break;
610
611 case TGSI_SEMANTIC_SAMPLEID:
612 value = get_sample_id(radeon_bld);
613 break;
614
615 case TGSI_SEMANTIC_SAMPLEPOS:
616 {
617 LLVMBuilderRef builder = gallivm->builder;
618 LLVMValueRef desc = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_CONST);
619 LLVMValueRef buf_index = lp_build_const_int32(gallivm, SI_DRIVER_STATE_CONST_BUF);
620 LLVMValueRef resource = build_indexed_load_const(si_shader_ctx, desc, buf_index);
621
622 /* offset = sample_id * 8 (8 = 2 floats containing samplepos.xy) */
623 LLVMValueRef offset0 = lp_build_mul_imm(uint_bld, get_sample_id(radeon_bld), 8);
624 LLVMValueRef offset1 = LLVMBuildAdd(builder, offset0, lp_build_const_int32(gallivm, 4), "");
625
626 LLVMValueRef pos[4] = {
627 buffer_load_const(builder, resource, offset0, radeon_bld->soa.bld_base.base.elem_type),
628 buffer_load_const(builder, resource, offset1, radeon_bld->soa.bld_base.base.elem_type),
629 lp_build_const_float(gallivm, 0),
630 lp_build_const_float(gallivm, 0)
631 };
632 value = lp_build_gather_values(gallivm, pos, 4);
633 break;
634 }
635
636 default:
637 assert(!"unknown system value");
638 return;
639 }
640
641 radeon_bld->system_values[index] = value;
642 }
643
644 static LLVMValueRef fetch_constant(
645 struct lp_build_tgsi_context * bld_base,
646 const struct tgsi_full_src_register *reg,
647 enum tgsi_opcode_type type,
648 unsigned swizzle)
649 {
650 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
651 struct lp_build_context * base = &bld_base->base;
652 const struct tgsi_ind_register *ireg = &reg->Indirect;
653 unsigned buf, idx;
654
655 LLVMValueRef addr;
656 LLVMValueRef result;
657
658 if (swizzle == LP_CHAN_ALL) {
659 unsigned chan;
660 LLVMValueRef values[4];
661 for (chan = 0; chan < TGSI_NUM_CHANNELS; ++chan)
662 values[chan] = fetch_constant(bld_base, reg, type, chan);
663
664 return lp_build_gather_values(bld_base->base.gallivm, values, 4);
665 }
666
667 buf = reg->Register.Dimension ? reg->Dimension.Index : 0;
668 idx = reg->Register.Index * 4 + swizzle;
669
670 if (!reg->Register.Indirect)
671 return bitcast(bld_base, type, si_shader_ctx->constants[buf][idx]);
672
673 addr = si_shader_ctx->radeon_bld.soa.addr[ireg->Index][ireg->Swizzle];
674 addr = LLVMBuildLoad(base->gallivm->builder, addr, "load addr reg");
675 addr = lp_build_mul_imm(&bld_base->uint_bld, addr, 16);
676 addr = lp_build_add(&bld_base->uint_bld, addr,
677 lp_build_const_int32(base->gallivm, idx * 4));
678
679 result = buffer_load_const(base->gallivm->builder, si_shader_ctx->const_resource[buf],
680 addr, base->elem_type);
681
682 return bitcast(bld_base, type, result);
683 }
684
685 /* Initialize arguments for the shader export intrinsic */
686 static void si_llvm_init_export_args(struct lp_build_tgsi_context *bld_base,
687 LLVMValueRef *values,
688 unsigned target,
689 LLVMValueRef *args)
690 {
691 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
692 struct lp_build_context *uint =
693 &si_shader_ctx->radeon_bld.soa.bld_base.uint_bld;
694 struct lp_build_context *base = &bld_base->base;
695 unsigned compressed = 0;
696 unsigned chan;
697
698 if (si_shader_ctx->type == TGSI_PROCESSOR_FRAGMENT) {
699 int cbuf = target - V_008DFC_SQ_EXP_MRT;
700
701 if (cbuf >= 0 && cbuf < 8) {
702 compressed = (si_shader_ctx->shader->key.ps.export_16bpc >> cbuf) & 0x1;
703
704 if (compressed)
705 si_shader_ctx->shader->spi_shader_col_format |=
706 V_028714_SPI_SHADER_FP16_ABGR << (4 * cbuf);
707 else
708 si_shader_ctx->shader->spi_shader_col_format |=
709 V_028714_SPI_SHADER_32_ABGR << (4 * cbuf);
710
711 si_shader_ctx->shader->cb_shader_mask |= 0xf << (4 * cbuf);
712 }
713 }
714
715 if (compressed) {
716 /* Pixel shader needs to pack output values before export */
717 for (chan = 0; chan < 2; chan++ ) {
718 args[0] = values[2 * chan];
719 args[1] = values[2 * chan + 1];
720 args[chan + 5] =
721 build_intrinsic(base->gallivm->builder,
722 "llvm.SI.packf16",
723 LLVMInt32TypeInContext(base->gallivm->context),
724 args, 2,
725 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
726 args[chan + 7] = args[chan + 5] =
727 LLVMBuildBitCast(base->gallivm->builder,
728 args[chan + 5],
729 LLVMFloatTypeInContext(base->gallivm->context),
730 "");
731 }
732
733 /* Set COMPR flag */
734 args[4] = uint->one;
735 } else {
736 for (chan = 0; chan < 4; chan++ )
737 /* +5 because the first output value will be
738 * the 6th argument to the intrinsic. */
739 args[chan + 5] = values[chan];
740
741 /* Clear COMPR flag */
742 args[4] = uint->zero;
743 }
744
745 /* XXX: This controls which components of the output
746 * registers actually get exported. (e.g bit 0 means export
747 * X component, bit 1 means export Y component, etc.) I'm
748 * hard coding this to 0xf for now. In the future, we might
749 * want to do something else. */
750 args[0] = lp_build_const_int32(base->gallivm, 0xf);
751
752 /* Specify whether the EXEC mask represents the valid mask */
753 args[1] = uint->zero;
754
755 /* Specify whether this is the last export */
756 args[2] = uint->zero;
757
758 /* Specify the target we are exporting */
759 args[3] = lp_build_const_int32(base->gallivm, target);
760
761 /* XXX: We probably need to keep track of the output
762 * values, so we know what we are passing to the next
763 * stage. */
764 }
765
766 /* Load from output pointers and initialize arguments for the shader export intrinsic */
767 static void si_llvm_init_export_args_load(struct lp_build_tgsi_context *bld_base,
768 LLVMValueRef *out_ptr,
769 unsigned target,
770 LLVMValueRef *args)
771 {
772 struct gallivm_state *gallivm = bld_base->base.gallivm;
773 LLVMValueRef values[4];
774 int i;
775
776 for (i = 0; i < 4; i++)
777 values[i] = LLVMBuildLoad(gallivm->builder, out_ptr[i], "");
778
779 si_llvm_init_export_args(bld_base, values, target, args);
780 }
781
782 static void si_alpha_test(struct lp_build_tgsi_context *bld_base,
783 LLVMValueRef *out_ptr)
784 {
785 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
786 struct gallivm_state *gallivm = bld_base->base.gallivm;
787
788 if (si_shader_ctx->shader->key.ps.alpha_func != PIPE_FUNC_NEVER) {
789 LLVMValueRef alpha_ref = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
790 SI_PARAM_ALPHA_REF);
791
792 LLVMValueRef alpha_pass =
793 lp_build_cmp(&bld_base->base,
794 si_shader_ctx->shader->key.ps.alpha_func,
795 LLVMBuildLoad(gallivm->builder, out_ptr[3], ""),
796 alpha_ref);
797 LLVMValueRef arg =
798 lp_build_select(&bld_base->base,
799 alpha_pass,
800 lp_build_const_float(gallivm, 1.0f),
801 lp_build_const_float(gallivm, -1.0f));
802
803 build_intrinsic(gallivm->builder,
804 "llvm.AMDGPU.kill",
805 LLVMVoidTypeInContext(gallivm->context),
806 &arg, 1, 0);
807 } else {
808 build_intrinsic(gallivm->builder,
809 "llvm.AMDGPU.kilp",
810 LLVMVoidTypeInContext(gallivm->context),
811 NULL, 0, 0);
812 }
813
814 si_shader_ctx->shader->db_shader_control |= S_02880C_KILL_ENABLE(1);
815 }
816
817 static void si_llvm_emit_clipvertex(struct lp_build_tgsi_context * bld_base,
818 LLVMValueRef (*pos)[9], LLVMValueRef *out_elts)
819 {
820 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
821 struct lp_build_context *base = &bld_base->base;
822 struct lp_build_context *uint = &si_shader_ctx->radeon_bld.soa.bld_base.uint_bld;
823 unsigned reg_index;
824 unsigned chan;
825 unsigned const_chan;
826 LLVMValueRef base_elt;
827 LLVMValueRef ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_CONST);
828 LLVMValueRef constbuf_index = lp_build_const_int32(base->gallivm, SI_DRIVER_STATE_CONST_BUF);
829 LLVMValueRef const_resource = build_indexed_load_const(si_shader_ctx, ptr, constbuf_index);
830
831 for (reg_index = 0; reg_index < 2; reg_index ++) {
832 LLVMValueRef *args = pos[2 + reg_index];
833
834 args[5] =
835 args[6] =
836 args[7] =
837 args[8] = lp_build_const_float(base->gallivm, 0.0f);
838
839 /* Compute dot products of position and user clip plane vectors */
840 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
841 for (const_chan = 0; const_chan < TGSI_NUM_CHANNELS; const_chan++) {
842 args[1] = lp_build_const_int32(base->gallivm,
843 ((reg_index * 4 + chan) * 4 +
844 const_chan) * 4);
845 base_elt = buffer_load_const(base->gallivm->builder, const_resource,
846 args[1], base->elem_type);
847 args[5 + chan] =
848 lp_build_add(base, args[5 + chan],
849 lp_build_mul(base, base_elt,
850 out_elts[const_chan]));
851 }
852 }
853
854 args[0] = lp_build_const_int32(base->gallivm, 0xf);
855 args[1] = uint->zero;
856 args[2] = uint->zero;
857 args[3] = lp_build_const_int32(base->gallivm,
858 V_008DFC_SQ_EXP_POS + 2 + reg_index);
859 args[4] = uint->zero;
860 }
861 }
862
863 static void si_dump_streamout(struct pipe_stream_output_info *so)
864 {
865 unsigned i;
866
867 if (so->num_outputs)
868 fprintf(stderr, "STREAMOUT\n");
869
870 for (i = 0; i < so->num_outputs; i++) {
871 unsigned mask = ((1 << so->output[i].num_components) - 1) <<
872 so->output[i].start_component;
873 fprintf(stderr, " %i: BUF%i[%i..%i] <- OUT[%i].%s%s%s%s\n",
874 i, so->output[i].output_buffer,
875 so->output[i].dst_offset, so->output[i].dst_offset + so->output[i].num_components - 1,
876 so->output[i].register_index,
877 mask & 1 ? "x" : "",
878 mask & 2 ? "y" : "",
879 mask & 4 ? "z" : "",
880 mask & 8 ? "w" : "");
881 }
882 }
883
884 /* TBUFFER_STORE_FORMAT_{X,XY,XYZ,XYZW} <- the suffix is selected by num_channels=1..4.
885 * The type of vdata must be one of i32 (num_channels=1), v2i32 (num_channels=2),
886 * or v4i32 (num_channels=3,4). */
887 static void build_tbuffer_store(struct si_shader_context *shader,
888 LLVMValueRef rsrc,
889 LLVMValueRef vdata,
890 unsigned num_channels,
891 LLVMValueRef vaddr,
892 LLVMValueRef soffset,
893 unsigned inst_offset,
894 unsigned dfmt,
895 unsigned nfmt,
896 unsigned offen,
897 unsigned idxen,
898 unsigned glc,
899 unsigned slc,
900 unsigned tfe)
901 {
902 struct gallivm_state *gallivm = &shader->radeon_bld.gallivm;
903 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
904 LLVMValueRef args[] = {
905 rsrc,
906 vdata,
907 LLVMConstInt(i32, num_channels, 0),
908 vaddr,
909 soffset,
910 LLVMConstInt(i32, inst_offset, 0),
911 LLVMConstInt(i32, dfmt, 0),
912 LLVMConstInt(i32, nfmt, 0),
913 LLVMConstInt(i32, offen, 0),
914 LLVMConstInt(i32, idxen, 0),
915 LLVMConstInt(i32, glc, 0),
916 LLVMConstInt(i32, slc, 0),
917 LLVMConstInt(i32, tfe, 0)
918 };
919
920 /* The instruction offset field has 12 bits */
921 assert(offen || inst_offset < (1 << 12));
922
923 /* The intrinsic is overloaded, we need to add a type suffix for overloading to work. */
924 unsigned func = CLAMP(num_channels, 1, 3) - 1;
925 const char *types[] = {"i32", "v2i32", "v4i32"};
926 char name[256];
927 snprintf(name, sizeof(name), "llvm.SI.tbuffer.store.%s", types[func]);
928
929 lp_build_intrinsic(gallivm->builder, name,
930 LLVMVoidTypeInContext(gallivm->context),
931 args, Elements(args));
932 }
933
934 static void build_streamout_store(struct si_shader_context *shader,
935 LLVMValueRef rsrc,
936 LLVMValueRef vdata,
937 unsigned num_channels,
938 LLVMValueRef vaddr,
939 LLVMValueRef soffset,
940 unsigned inst_offset)
941 {
942 static unsigned dfmt[] = {
943 V_008F0C_BUF_DATA_FORMAT_32,
944 V_008F0C_BUF_DATA_FORMAT_32_32,
945 V_008F0C_BUF_DATA_FORMAT_32_32_32,
946 V_008F0C_BUF_DATA_FORMAT_32_32_32_32
947 };
948 assert(num_channels >= 1 && num_channels <= 4);
949
950 build_tbuffer_store(shader, rsrc, vdata, num_channels, vaddr, soffset,
951 inst_offset, dfmt[num_channels-1],
952 V_008F0C_BUF_NUM_FORMAT_UINT, 1, 0, 1, 1, 0);
953 }
954
955 /* On SI, the vertex shader is responsible for writing streamout data
956 * to buffers. */
957 static void si_llvm_emit_streamout(struct si_shader_context *shader,
958 struct si_shader_output_values *outputs,
959 unsigned noutput)
960 {
961 struct pipe_stream_output_info *so = &shader->shader->selector->so;
962 struct gallivm_state *gallivm = &shader->radeon_bld.gallivm;
963 LLVMBuilderRef builder = gallivm->builder;
964 int i, j;
965 struct lp_build_if_state if_ctx;
966
967 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
968
969 LLVMValueRef so_param =
970 LLVMGetParam(shader->radeon_bld.main_fn,
971 shader->param_streamout_config);
972
973 /* Get bits [22:16], i.e. (so_param >> 16) & 127; */
974 LLVMValueRef so_vtx_count =
975 LLVMBuildAnd(builder,
976 LLVMBuildLShr(builder, so_param,
977 LLVMConstInt(i32, 16, 0), ""),
978 LLVMConstInt(i32, 127, 0), "");
979
980 LLVMValueRef tid = build_intrinsic(builder, "llvm.SI.tid", i32,
981 NULL, 0, LLVMReadNoneAttribute);
982
983 /* can_emit = tid < so_vtx_count; */
984 LLVMValueRef can_emit =
985 LLVMBuildICmp(builder, LLVMIntULT, tid, so_vtx_count, "");
986
987 /* Emit the streamout code conditionally. This actually avoids
988 * out-of-bounds buffer access. The hw tells us via the SGPR
989 * (so_vtx_count) which threads are allowed to emit streamout data. */
990 lp_build_if(&if_ctx, gallivm, can_emit);
991 {
992 /* The buffer offset is computed as follows:
993 * ByteOffset = streamout_offset[buffer_id]*4 +
994 * (streamout_write_index + thread_id)*stride[buffer_id] +
995 * attrib_offset
996 */
997
998 LLVMValueRef so_write_index =
999 LLVMGetParam(shader->radeon_bld.main_fn,
1000 shader->param_streamout_write_index);
1001
1002 /* Compute (streamout_write_index + thread_id). */
1003 so_write_index = LLVMBuildAdd(builder, so_write_index, tid, "");
1004
1005 /* Compute the write offset for each enabled buffer. */
1006 LLVMValueRef so_write_offset[4] = {};
1007 for (i = 0; i < 4; i++) {
1008 if (!so->stride[i])
1009 continue;
1010
1011 LLVMValueRef so_offset = LLVMGetParam(shader->radeon_bld.main_fn,
1012 shader->param_streamout_offset[i]);
1013 so_offset = LLVMBuildMul(builder, so_offset, LLVMConstInt(i32, 4, 0), "");
1014
1015 so_write_offset[i] = LLVMBuildMul(builder, so_write_index,
1016 LLVMConstInt(i32, so->stride[i]*4, 0), "");
1017 so_write_offset[i] = LLVMBuildAdd(builder, so_write_offset[i], so_offset, "");
1018 }
1019
1020 /* Write streamout data. */
1021 for (i = 0; i < so->num_outputs; i++) {
1022 unsigned buf_idx = so->output[i].output_buffer;
1023 unsigned reg = so->output[i].register_index;
1024 unsigned start = so->output[i].start_component;
1025 unsigned num_comps = so->output[i].num_components;
1026 LLVMValueRef out[4];
1027
1028 assert(num_comps && num_comps <= 4);
1029 if (!num_comps || num_comps > 4)
1030 continue;
1031
1032 if (reg >= noutput)
1033 continue;
1034
1035 /* Load the output as int. */
1036 for (j = 0; j < num_comps; j++) {
1037 out[j] = LLVMBuildBitCast(builder,
1038 outputs[reg].values[start+j],
1039 i32, "");
1040 }
1041
1042 /* Pack the output. */
1043 LLVMValueRef vdata = NULL;
1044
1045 switch (num_comps) {
1046 case 1: /* as i32 */
1047 vdata = out[0];
1048 break;
1049 case 2: /* as v2i32 */
1050 case 3: /* as v4i32 (aligned to 4) */
1051 case 4: /* as v4i32 */
1052 vdata = LLVMGetUndef(LLVMVectorType(i32, util_next_power_of_two(num_comps)));
1053 for (j = 0; j < num_comps; j++) {
1054 vdata = LLVMBuildInsertElement(builder, vdata, out[j],
1055 LLVMConstInt(i32, j, 0), "");
1056 }
1057 break;
1058 }
1059
1060 build_streamout_store(shader, shader->so_buffers[buf_idx],
1061 vdata, num_comps,
1062 so_write_offset[buf_idx],
1063 LLVMConstInt(i32, 0, 0),
1064 so->output[i].dst_offset*4);
1065 }
1066 }
1067 lp_build_endif(&if_ctx);
1068 }
1069
1070
1071 /* Generate export instructions for hardware VS shader stage */
1072 static void si_llvm_export_vs(struct lp_build_tgsi_context *bld_base,
1073 struct si_shader_output_values *outputs,
1074 unsigned noutput)
1075 {
1076 struct si_shader_context * si_shader_ctx = si_shader_context(bld_base);
1077 struct si_shader * shader = si_shader_ctx->shader;
1078 struct lp_build_context * base = &bld_base->base;
1079 struct lp_build_context * uint =
1080 &si_shader_ctx->radeon_bld.soa.bld_base.uint_bld;
1081 LLVMValueRef args[9];
1082 LLVMValueRef pos_args[4][9] = { { 0 } };
1083 LLVMValueRef psize_value = NULL, edgeflag_value = NULL, layer_value = NULL;
1084 unsigned semantic_name, semantic_index;
1085 unsigned target;
1086 unsigned param_count = 0;
1087 unsigned pos_idx;
1088 int i;
1089
1090 if (outputs && si_shader_ctx->shader->selector->so.num_outputs) {
1091 si_llvm_emit_streamout(si_shader_ctx, outputs, noutput);
1092 }
1093
1094 for (i = 0; i < noutput; i++) {
1095 semantic_name = outputs[i].name;
1096 semantic_index = outputs[i].sid;
1097
1098 handle_semantic:
1099 /* Select the correct target */
1100 switch(semantic_name) {
1101 case TGSI_SEMANTIC_PSIZE:
1102 psize_value = outputs[i].values[0];
1103 continue;
1104 case TGSI_SEMANTIC_EDGEFLAG:
1105 edgeflag_value = outputs[i].values[0];
1106 continue;
1107 case TGSI_SEMANTIC_LAYER:
1108 layer_value = outputs[i].values[0];
1109 continue;
1110 case TGSI_SEMANTIC_POSITION:
1111 target = V_008DFC_SQ_EXP_POS;
1112 break;
1113 case TGSI_SEMANTIC_COLOR:
1114 case TGSI_SEMANTIC_BCOLOR:
1115 target = V_008DFC_SQ_EXP_PARAM + param_count;
1116 shader->vs_output_param_offset[i] = param_count;
1117 param_count++;
1118 break;
1119 case TGSI_SEMANTIC_CLIPDIST:
1120 target = V_008DFC_SQ_EXP_POS + 2 + semantic_index;
1121 break;
1122 case TGSI_SEMANTIC_CLIPVERTEX:
1123 si_llvm_emit_clipvertex(bld_base, pos_args, outputs[i].values);
1124 continue;
1125 case TGSI_SEMANTIC_PRIMID:
1126 case TGSI_SEMANTIC_FOG:
1127 case TGSI_SEMANTIC_GENERIC:
1128 target = V_008DFC_SQ_EXP_PARAM + param_count;
1129 shader->vs_output_param_offset[i] = param_count;
1130 param_count++;
1131 break;
1132 default:
1133 target = 0;
1134 fprintf(stderr,
1135 "Warning: SI unhandled vs output type:%d\n",
1136 semantic_name);
1137 }
1138
1139 si_llvm_init_export_args(bld_base, outputs[i].values, target, args);
1140
1141 if (target >= V_008DFC_SQ_EXP_POS &&
1142 target <= (V_008DFC_SQ_EXP_POS + 3)) {
1143 memcpy(pos_args[target - V_008DFC_SQ_EXP_POS],
1144 args, sizeof(args));
1145 } else {
1146 lp_build_intrinsic(base->gallivm->builder,
1147 "llvm.SI.export",
1148 LLVMVoidTypeInContext(base->gallivm->context),
1149 args, 9);
1150 }
1151
1152 if (semantic_name == TGSI_SEMANTIC_CLIPDIST) {
1153 semantic_name = TGSI_SEMANTIC_GENERIC;
1154 goto handle_semantic;
1155 }
1156 }
1157
1158 /* We need to add the position output manually if it's missing. */
1159 if (!pos_args[0][0]) {
1160 pos_args[0][0] = lp_build_const_int32(base->gallivm, 0xf); /* writemask */
1161 pos_args[0][1] = uint->zero; /* EXEC mask */
1162 pos_args[0][2] = uint->zero; /* last export? */
1163 pos_args[0][3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_POS);
1164 pos_args[0][4] = uint->zero; /* COMPR flag */
1165 pos_args[0][5] = base->zero; /* X */
1166 pos_args[0][6] = base->zero; /* Y */
1167 pos_args[0][7] = base->zero; /* Z */
1168 pos_args[0][8] = base->one; /* W */
1169 }
1170
1171 /* Write the misc vector (point size, edgeflag, layer, viewport). */
1172 if (shader->selector->info.writes_psize ||
1173 shader->selector->info.writes_edgeflag ||
1174 shader->selector->info.writes_layer) {
1175 pos_args[1][0] = lp_build_const_int32(base->gallivm, /* writemask */
1176 shader->selector->info.writes_psize |
1177 (shader->selector->info.writes_edgeflag << 1) |
1178 (shader->selector->info.writes_layer << 2));
1179 pos_args[1][1] = uint->zero; /* EXEC mask */
1180 pos_args[1][2] = uint->zero; /* last export? */
1181 pos_args[1][3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_POS + 1);
1182 pos_args[1][4] = uint->zero; /* COMPR flag */
1183 pos_args[1][5] = base->zero; /* X */
1184 pos_args[1][6] = base->zero; /* Y */
1185 pos_args[1][7] = base->zero; /* Z */
1186 pos_args[1][8] = base->zero; /* W */
1187
1188 if (shader->selector->info.writes_psize)
1189 pos_args[1][5] = psize_value;
1190
1191 if (shader->selector->info.writes_edgeflag) {
1192 /* The output is a float, but the hw expects an integer
1193 * with the first bit containing the edge flag. */
1194 edgeflag_value = LLVMBuildFPToUI(base->gallivm->builder,
1195 edgeflag_value,
1196 bld_base->uint_bld.elem_type, "");
1197 edgeflag_value = lp_build_min(&bld_base->int_bld,
1198 edgeflag_value,
1199 bld_base->int_bld.one);
1200
1201 /* The LLVM intrinsic expects a float. */
1202 pos_args[1][6] = LLVMBuildBitCast(base->gallivm->builder,
1203 edgeflag_value,
1204 base->elem_type, "");
1205 }
1206
1207 if (shader->selector->info.writes_layer)
1208 pos_args[1][7] = layer_value;
1209 }
1210
1211 for (i = 0; i < 4; i++)
1212 if (pos_args[i][0])
1213 shader->nr_pos_exports++;
1214
1215 pos_idx = 0;
1216 for (i = 0; i < 4; i++) {
1217 if (!pos_args[i][0])
1218 continue;
1219
1220 /* Specify the target we are exporting */
1221 pos_args[i][3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_POS + pos_idx++);
1222
1223 if (pos_idx == shader->nr_pos_exports)
1224 /* Specify that this is the last export */
1225 pos_args[i][2] = uint->one;
1226
1227 lp_build_intrinsic(base->gallivm->builder,
1228 "llvm.SI.export",
1229 LLVMVoidTypeInContext(base->gallivm->context),
1230 pos_args[i], 9);
1231 }
1232 }
1233
1234 static void si_llvm_emit_es_epilogue(struct lp_build_tgsi_context * bld_base)
1235 {
1236 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
1237 struct gallivm_state *gallivm = bld_base->base.gallivm;
1238 struct si_shader *es = si_shader_ctx->shader;
1239 struct tgsi_shader_info *info = &es->selector->info;
1240 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
1241 LLVMValueRef soffset = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
1242 SI_PARAM_ES2GS_OFFSET);
1243 unsigned chan;
1244 int i;
1245
1246 for (i = 0; i < info->num_outputs; i++) {
1247 LLVMValueRef *out_ptr =
1248 si_shader_ctx->radeon_bld.soa.outputs[i];
1249 int param_index = get_param_index(info->output_semantic_name[i],
1250 info->output_semantic_index[i],
1251 es->key.vs.gs_used_inputs);
1252
1253 if (param_index < 0)
1254 continue;
1255
1256 for (chan = 0; chan < 4; chan++) {
1257 LLVMValueRef out_val = LLVMBuildLoad(gallivm->builder, out_ptr[chan], "");
1258 out_val = LLVMBuildBitCast(gallivm->builder, out_val, i32, "");
1259
1260 build_tbuffer_store(si_shader_ctx,
1261 si_shader_ctx->esgs_ring,
1262 out_val, 1,
1263 LLVMGetUndef(i32), soffset,
1264 (4 * param_index + chan) * 4,
1265 V_008F0C_BUF_DATA_FORMAT_32,
1266 V_008F0C_BUF_NUM_FORMAT_UINT,
1267 0, 0, 1, 1, 0);
1268 }
1269 }
1270 }
1271
1272 static void si_llvm_emit_gs_epilogue(struct lp_build_tgsi_context *bld_base)
1273 {
1274 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
1275 struct gallivm_state *gallivm = bld_base->base.gallivm;
1276 LLVMValueRef args[2];
1277
1278 args[0] = lp_build_const_int32(gallivm, SENDMSG_GS_OP_NOP | SENDMSG_GS_DONE);
1279 args[1] = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_GS_WAVE_ID);
1280 build_intrinsic(gallivm->builder, "llvm.SI.sendmsg",
1281 LLVMVoidTypeInContext(gallivm->context), args, 2,
1282 LLVMNoUnwindAttribute);
1283 }
1284
1285 static void si_llvm_emit_vs_epilogue(struct lp_build_tgsi_context * bld_base)
1286 {
1287 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
1288 struct gallivm_state *gallivm = bld_base->base.gallivm;
1289 struct tgsi_shader_info *info = &si_shader_ctx->shader->selector->info;
1290 struct si_shader_output_values *outputs = NULL;
1291 int i,j;
1292
1293 outputs = MALLOC(info->num_outputs * sizeof(outputs[0]));
1294
1295 for (i = 0; i < info->num_outputs; i++) {
1296 outputs[i].name = info->output_semantic_name[i];
1297 outputs[i].sid = info->output_semantic_index[i];
1298
1299 for (j = 0; j < 4; j++)
1300 outputs[i].values[j] =
1301 LLVMBuildLoad(gallivm->builder,
1302 si_shader_ctx->radeon_bld.soa.outputs[i][j],
1303 "");
1304 }
1305
1306 si_llvm_export_vs(bld_base, outputs, info->num_outputs);
1307 FREE(outputs);
1308 }
1309
1310 static void si_llvm_emit_fs_epilogue(struct lp_build_tgsi_context * bld_base)
1311 {
1312 struct si_shader_context * si_shader_ctx = si_shader_context(bld_base);
1313 struct si_shader * shader = si_shader_ctx->shader;
1314 struct lp_build_context * base = &bld_base->base;
1315 struct lp_build_context * uint = &bld_base->uint_bld;
1316 struct tgsi_shader_info *info = &shader->selector->info;
1317 LLVMValueRef args[9];
1318 LLVMValueRef last_args[9] = { 0 };
1319 int depth_index = -1, stencil_index = -1, samplemask_index = -1;
1320 int i;
1321
1322 for (i = 0; i < info->num_outputs; i++) {
1323 unsigned semantic_name = info->output_semantic_name[i];
1324 unsigned semantic_index = info->output_semantic_index[i];
1325 unsigned target;
1326
1327 /* Select the correct target */
1328 switch (semantic_name) {
1329 case TGSI_SEMANTIC_POSITION:
1330 depth_index = i;
1331 continue;
1332 case TGSI_SEMANTIC_STENCIL:
1333 stencil_index = i;
1334 continue;
1335 case TGSI_SEMANTIC_SAMPLEMASK:
1336 samplemask_index = i;
1337 continue;
1338 case TGSI_SEMANTIC_COLOR:
1339 target = V_008DFC_SQ_EXP_MRT + semantic_index;
1340 if (si_shader_ctx->shader->key.ps.alpha_to_one)
1341 LLVMBuildStore(bld_base->base.gallivm->builder,
1342 bld_base->base.one,
1343 si_shader_ctx->radeon_bld.soa.outputs[i][3]);
1344
1345 if (semantic_index == 0 &&
1346 si_shader_ctx->shader->key.ps.alpha_func != PIPE_FUNC_ALWAYS)
1347 si_alpha_test(bld_base,
1348 si_shader_ctx->radeon_bld.soa.outputs[i]);
1349 break;
1350 default:
1351 target = 0;
1352 fprintf(stderr,
1353 "Warning: SI unhandled fs output type:%d\n",
1354 semantic_name);
1355 }
1356
1357 si_llvm_init_export_args_load(bld_base,
1358 si_shader_ctx->radeon_bld.soa.outputs[i],
1359 target, args);
1360
1361 if (semantic_name == TGSI_SEMANTIC_COLOR) {
1362 /* If there is an export instruction waiting to be emitted, do so now. */
1363 if (last_args[0]) {
1364 lp_build_intrinsic(base->gallivm->builder,
1365 "llvm.SI.export",
1366 LLVMVoidTypeInContext(base->gallivm->context),
1367 last_args, 9);
1368 }
1369
1370 /* This instruction will be emitted at the end of the shader. */
1371 memcpy(last_args, args, sizeof(args));
1372
1373 /* Handle FS_COLOR0_WRITES_ALL_CBUFS. */
1374 if (shader->selector->info.properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS] &&
1375 semantic_index == 0 &&
1376 si_shader_ctx->shader->key.ps.last_cbuf > 0) {
1377 for (int c = 1; c <= si_shader_ctx->shader->key.ps.last_cbuf; c++) {
1378 si_llvm_init_export_args_load(bld_base,
1379 si_shader_ctx->radeon_bld.soa.outputs[i],
1380 V_008DFC_SQ_EXP_MRT + c, args);
1381 lp_build_intrinsic(base->gallivm->builder,
1382 "llvm.SI.export",
1383 LLVMVoidTypeInContext(base->gallivm->context),
1384 args, 9);
1385 }
1386 }
1387 } else {
1388 lp_build_intrinsic(base->gallivm->builder,
1389 "llvm.SI.export",
1390 LLVMVoidTypeInContext(base->gallivm->context),
1391 args, 9);
1392 }
1393 }
1394
1395 if (depth_index >= 0 || stencil_index >= 0 || samplemask_index >= 0) {
1396 LLVMValueRef out_ptr;
1397 unsigned mask = 0;
1398
1399 /* Specify the target we are exporting */
1400 args[3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_MRTZ);
1401
1402 args[5] = base->zero; /* R, depth */
1403 args[6] = base->zero; /* G, stencil test value[0:7], stencil op value[8:15] */
1404 args[7] = base->zero; /* B, sample mask */
1405 args[8] = base->zero; /* A, alpha to mask */
1406
1407 if (depth_index >= 0) {
1408 out_ptr = si_shader_ctx->radeon_bld.soa.outputs[depth_index][2];
1409 args[5] = LLVMBuildLoad(base->gallivm->builder, out_ptr, "");
1410 mask |= 0x1;
1411 si_shader_ctx->shader->db_shader_control |= S_02880C_Z_EXPORT_ENABLE(1);
1412 }
1413
1414 if (stencil_index >= 0) {
1415 out_ptr = si_shader_ctx->radeon_bld.soa.outputs[stencil_index][1];
1416 args[6] = LLVMBuildLoad(base->gallivm->builder, out_ptr, "");
1417 mask |= 0x2;
1418 si_shader_ctx->shader->db_shader_control |=
1419 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(1);
1420 }
1421
1422 if (samplemask_index >= 0) {
1423 out_ptr = si_shader_ctx->radeon_bld.soa.outputs[samplemask_index][0];
1424 args[7] = LLVMBuildLoad(base->gallivm->builder, out_ptr, "");
1425 mask |= 0x4;
1426 si_shader_ctx->shader->db_shader_control |= S_02880C_MASK_EXPORT_ENABLE(1);
1427 }
1428
1429 /* SI (except OLAND) has a bug that it only looks
1430 * at the X writemask component. */
1431 if (si_shader_ctx->screen->b.chip_class == SI &&
1432 si_shader_ctx->screen->b.family != CHIP_OLAND)
1433 mask |= 0x1;
1434
1435 if (samplemask_index >= 0)
1436 si_shader_ctx->shader->spi_shader_z_format = V_028710_SPI_SHADER_32_ABGR;
1437 else if (stencil_index >= 0)
1438 si_shader_ctx->shader->spi_shader_z_format = V_028710_SPI_SHADER_32_GR;
1439 else
1440 si_shader_ctx->shader->spi_shader_z_format = V_028710_SPI_SHADER_32_R;
1441
1442 /* Specify which components to enable */
1443 args[0] = lp_build_const_int32(base->gallivm, mask);
1444
1445 args[1] =
1446 args[2] =
1447 args[4] = uint->zero;
1448
1449 if (last_args[0])
1450 lp_build_intrinsic(base->gallivm->builder,
1451 "llvm.SI.export",
1452 LLVMVoidTypeInContext(base->gallivm->context),
1453 args, 9);
1454 else
1455 memcpy(last_args, args, sizeof(args));
1456 }
1457
1458 if (!last_args[0]) {
1459 /* Specify which components to enable */
1460 last_args[0] = lp_build_const_int32(base->gallivm, 0x0);
1461
1462 /* Specify the target we are exporting */
1463 last_args[3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_MRT);
1464
1465 /* Set COMPR flag to zero to export data as 32-bit */
1466 last_args[4] = uint->zero;
1467
1468 /* dummy bits */
1469 last_args[5]= uint->zero;
1470 last_args[6]= uint->zero;
1471 last_args[7]= uint->zero;
1472 last_args[8]= uint->zero;
1473 }
1474
1475 /* Specify whether the EXEC mask represents the valid mask */
1476 last_args[1] = uint->one;
1477
1478 /* Specify that this is the last export */
1479 last_args[2] = lp_build_const_int32(base->gallivm, 1);
1480
1481 lp_build_intrinsic(base->gallivm->builder,
1482 "llvm.SI.export",
1483 LLVMVoidTypeInContext(base->gallivm->context),
1484 last_args, 9);
1485 }
1486
1487 static void build_tex_intrinsic(const struct lp_build_tgsi_action * action,
1488 struct lp_build_tgsi_context * bld_base,
1489 struct lp_build_emit_data * emit_data);
1490
1491 static bool tgsi_is_shadow_sampler(unsigned target)
1492 {
1493 return target == TGSI_TEXTURE_SHADOW1D ||
1494 target == TGSI_TEXTURE_SHADOW1D_ARRAY ||
1495 target == TGSI_TEXTURE_SHADOW2D ||
1496 target == TGSI_TEXTURE_SHADOW2D_ARRAY ||
1497 target == TGSI_TEXTURE_SHADOWCUBE ||
1498 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY ||
1499 target == TGSI_TEXTURE_SHADOWRECT;
1500 }
1501
1502 static const struct lp_build_tgsi_action tex_action;
1503
1504 static void tex_fetch_args(
1505 struct lp_build_tgsi_context * bld_base,
1506 struct lp_build_emit_data * emit_data)
1507 {
1508 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
1509 struct gallivm_state *gallivm = bld_base->base.gallivm;
1510 const struct tgsi_full_instruction * inst = emit_data->inst;
1511 unsigned opcode = inst->Instruction.Opcode;
1512 unsigned target = inst->Texture.Texture;
1513 LLVMValueRef coords[4];
1514 LLVMValueRef address[16];
1515 int ref_pos;
1516 unsigned num_coords = tgsi_util_get_texture_coord_dim(target, &ref_pos);
1517 unsigned count = 0;
1518 unsigned chan;
1519 unsigned sampler_src = emit_data->inst->Instruction.NumSrcRegs - 1;
1520 unsigned sampler_index = emit_data->inst->Src[sampler_src].Register.Index;
1521 bool has_offset = HAVE_LLVM >= 0x0305 ? inst->Texture.NumOffsets > 0 : false;
1522
1523 if (target == TGSI_TEXTURE_BUFFER) {
1524 LLVMTypeRef i128 = LLVMIntTypeInContext(gallivm->context, 128);
1525 LLVMTypeRef v2i128 = LLVMVectorType(i128, 2);
1526 LLVMTypeRef i8 = LLVMInt8TypeInContext(gallivm->context);
1527 LLVMTypeRef v16i8 = LLVMVectorType(i8, 16);
1528
1529 /* Bitcast and truncate v8i32 to v16i8. */
1530 LLVMValueRef res = si_shader_ctx->resources[sampler_index];
1531 res = LLVMBuildBitCast(gallivm->builder, res, v2i128, "");
1532 res = LLVMBuildExtractElement(gallivm->builder, res, bld_base->uint_bld.zero, "");
1533 res = LLVMBuildBitCast(gallivm->builder, res, v16i8, "");
1534
1535 emit_data->dst_type = LLVMVectorType(bld_base->base.elem_type, 4);
1536 emit_data->args[0] = res;
1537 emit_data->args[1] = bld_base->uint_bld.zero;
1538 emit_data->args[2] = lp_build_emit_fetch(bld_base, emit_data->inst, 0, 0);
1539 emit_data->arg_count = 3;
1540 return;
1541 }
1542
1543 /* Fetch and project texture coordinates */
1544 coords[3] = lp_build_emit_fetch(bld_base, emit_data->inst, 0, TGSI_CHAN_W);
1545 for (chan = 0; chan < 3; chan++ ) {
1546 coords[chan] = lp_build_emit_fetch(bld_base,
1547 emit_data->inst, 0,
1548 chan);
1549 if (opcode == TGSI_OPCODE_TXP)
1550 coords[chan] = lp_build_emit_llvm_binary(bld_base,
1551 TGSI_OPCODE_DIV,
1552 coords[chan],
1553 coords[3]);
1554 }
1555
1556 if (opcode == TGSI_OPCODE_TXP)
1557 coords[3] = bld_base->base.one;
1558
1559 /* Pack offsets. */
1560 if (has_offset && opcode != TGSI_OPCODE_TXF) {
1561 /* The offsets are six-bit signed integers packed like this:
1562 * X=[5:0], Y=[13:8], and Z=[21:16].
1563 */
1564 LLVMValueRef offset[3], pack;
1565
1566 assert(inst->Texture.NumOffsets == 1);
1567
1568 for (chan = 0; chan < 3; chan++) {
1569 offset[chan] = lp_build_emit_fetch_texoffset(bld_base,
1570 emit_data->inst, 0, chan);
1571 offset[chan] = LLVMBuildAnd(gallivm->builder, offset[chan],
1572 lp_build_const_int32(gallivm, 0x3f), "");
1573 if (chan)
1574 offset[chan] = LLVMBuildShl(gallivm->builder, offset[chan],
1575 lp_build_const_int32(gallivm, chan*8), "");
1576 }
1577
1578 pack = LLVMBuildOr(gallivm->builder, offset[0], offset[1], "");
1579 pack = LLVMBuildOr(gallivm->builder, pack, offset[2], "");
1580 address[count++] = pack;
1581 }
1582
1583 /* Pack LOD bias value */
1584 if (opcode == TGSI_OPCODE_TXB)
1585 address[count++] = coords[3];
1586 if (opcode == TGSI_OPCODE_TXB2)
1587 address[count++] = lp_build_emit_fetch(bld_base, inst, 1, 0);
1588
1589 /* Pack depth comparison value */
1590 if (tgsi_is_shadow_sampler(target) && opcode != TGSI_OPCODE_LODQ) {
1591 if (target == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
1592 address[count++] = lp_build_emit_fetch(bld_base, inst, 1, 0);
1593 } else {
1594 assert(ref_pos >= 0);
1595 address[count++] = coords[ref_pos];
1596 }
1597 }
1598
1599 if (target == TGSI_TEXTURE_CUBE ||
1600 target == TGSI_TEXTURE_CUBE_ARRAY ||
1601 target == TGSI_TEXTURE_SHADOWCUBE ||
1602 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY)
1603 radeon_llvm_emit_prepare_cube_coords(bld_base, emit_data, coords);
1604
1605 /* Pack user derivatives */
1606 if (opcode == TGSI_OPCODE_TXD) {
1607 int num_deriv_channels, param;
1608
1609 switch (target) {
1610 case TGSI_TEXTURE_3D:
1611 num_deriv_channels = 3;
1612 break;
1613 case TGSI_TEXTURE_2D:
1614 case TGSI_TEXTURE_SHADOW2D:
1615 case TGSI_TEXTURE_RECT:
1616 case TGSI_TEXTURE_SHADOWRECT:
1617 case TGSI_TEXTURE_2D_ARRAY:
1618 case TGSI_TEXTURE_SHADOW2D_ARRAY:
1619 case TGSI_TEXTURE_CUBE:
1620 case TGSI_TEXTURE_SHADOWCUBE:
1621 case TGSI_TEXTURE_CUBE_ARRAY:
1622 case TGSI_TEXTURE_SHADOWCUBE_ARRAY:
1623 num_deriv_channels = 2;
1624 break;
1625 case TGSI_TEXTURE_1D:
1626 case TGSI_TEXTURE_SHADOW1D:
1627 case TGSI_TEXTURE_1D_ARRAY:
1628 case TGSI_TEXTURE_SHADOW1D_ARRAY:
1629 num_deriv_channels = 1;
1630 break;
1631 default:
1632 assert(0); /* no other targets are valid here */
1633 }
1634
1635 for (param = 1; param <= 2; param++)
1636 for (chan = 0; chan < num_deriv_channels; chan++)
1637 address[count++] = lp_build_emit_fetch(bld_base, inst, param, chan);
1638 }
1639
1640 /* Pack texture coordinates */
1641 address[count++] = coords[0];
1642 if (num_coords > 1)
1643 address[count++] = coords[1];
1644 if (num_coords > 2)
1645 address[count++] = coords[2];
1646
1647 /* Pack LOD or sample index */
1648 if (opcode == TGSI_OPCODE_TXL || opcode == TGSI_OPCODE_TXF)
1649 address[count++] = coords[3];
1650 else if (opcode == TGSI_OPCODE_TXL2)
1651 address[count++] = lp_build_emit_fetch(bld_base, inst, 1, 0);
1652
1653 if (count > 16) {
1654 assert(!"Cannot handle more than 16 texture address parameters");
1655 count = 16;
1656 }
1657
1658 for (chan = 0; chan < count; chan++ ) {
1659 address[chan] = LLVMBuildBitCast(gallivm->builder,
1660 address[chan],
1661 LLVMInt32TypeInContext(gallivm->context),
1662 "");
1663 }
1664
1665 /* Adjust the sample index according to FMASK.
1666 *
1667 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
1668 * which is the identity mapping. Each nibble says which physical sample
1669 * should be fetched to get that sample.
1670 *
1671 * For example, 0x11111100 means there are only 2 samples stored and
1672 * the second sample covers 3/4 of the pixel. When reading samples 0
1673 * and 1, return physical sample 0 (determined by the first two 0s
1674 * in FMASK), otherwise return physical sample 1.
1675 *
1676 * The sample index should be adjusted as follows:
1677 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
1678 */
1679 if (target == TGSI_TEXTURE_2D_MSAA ||
1680 target == TGSI_TEXTURE_2D_ARRAY_MSAA) {
1681 struct lp_build_context *uint_bld = &bld_base->uint_bld;
1682 struct lp_build_emit_data txf_emit_data = *emit_data;
1683 LLVMValueRef txf_address[4];
1684 unsigned txf_count = count;
1685 struct tgsi_full_instruction inst = {};
1686
1687 memcpy(txf_address, address, sizeof(txf_address));
1688
1689 if (target == TGSI_TEXTURE_2D_MSAA) {
1690 txf_address[2] = bld_base->uint_bld.zero;
1691 }
1692 txf_address[3] = bld_base->uint_bld.zero;
1693
1694 /* Pad to a power-of-two size. */
1695 while (txf_count < util_next_power_of_two(txf_count))
1696 txf_address[txf_count++] = LLVMGetUndef(LLVMInt32TypeInContext(gallivm->context));
1697
1698 /* Read FMASK using TXF. */
1699 inst.Instruction.Opcode = TGSI_OPCODE_TXF;
1700 inst.Texture.Texture = target == TGSI_TEXTURE_2D_MSAA ? TGSI_TEXTURE_2D : TGSI_TEXTURE_2D_ARRAY;
1701 txf_emit_data.inst = &inst;
1702 txf_emit_data.chan = 0;
1703 txf_emit_data.dst_type = LLVMVectorType(
1704 LLVMInt32TypeInContext(gallivm->context), 4);
1705 txf_emit_data.args[0] = lp_build_gather_values(gallivm, txf_address, txf_count);
1706 txf_emit_data.args[1] = si_shader_ctx->resources[SI_FMASK_TEX_OFFSET + sampler_index];
1707 txf_emit_data.args[2] = lp_build_const_int32(gallivm, inst.Texture.Texture);
1708 txf_emit_data.arg_count = 3;
1709
1710 build_tex_intrinsic(&tex_action, bld_base, &txf_emit_data);
1711
1712 /* Initialize some constants. */
1713 LLVMValueRef four = LLVMConstInt(uint_bld->elem_type, 4, 0);
1714 LLVMValueRef F = LLVMConstInt(uint_bld->elem_type, 0xF, 0);
1715
1716 /* Apply the formula. */
1717 LLVMValueRef fmask =
1718 LLVMBuildExtractElement(gallivm->builder,
1719 txf_emit_data.output[0],
1720 uint_bld->zero, "");
1721
1722 unsigned sample_chan = target == TGSI_TEXTURE_2D_MSAA ? 2 : 3;
1723
1724 LLVMValueRef sample_index4 =
1725 LLVMBuildMul(gallivm->builder, address[sample_chan], four, "");
1726
1727 LLVMValueRef shifted_fmask =
1728 LLVMBuildLShr(gallivm->builder, fmask, sample_index4, "");
1729
1730 LLVMValueRef final_sample =
1731 LLVMBuildAnd(gallivm->builder, shifted_fmask, F, "");
1732
1733 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
1734 * resource descriptor is 0 (invalid),
1735 */
1736 LLVMValueRef fmask_desc =
1737 LLVMBuildBitCast(gallivm->builder,
1738 si_shader_ctx->resources[SI_FMASK_TEX_OFFSET + sampler_index],
1739 LLVMVectorType(uint_bld->elem_type, 8), "");
1740
1741 LLVMValueRef fmask_word1 =
1742 LLVMBuildExtractElement(gallivm->builder, fmask_desc,
1743 uint_bld->one, "");
1744
1745 LLVMValueRef word1_is_nonzero =
1746 LLVMBuildICmp(gallivm->builder, LLVMIntNE,
1747 fmask_word1, uint_bld->zero, "");
1748
1749 /* Replace the MSAA sample index. */
1750 address[sample_chan] =
1751 LLVMBuildSelect(gallivm->builder, word1_is_nonzero,
1752 final_sample, address[sample_chan], "");
1753 }
1754
1755 /* Resource */
1756 emit_data->args[1] = si_shader_ctx->resources[sampler_index];
1757
1758 if (opcode == TGSI_OPCODE_TXF) {
1759 /* add tex offsets */
1760 if (inst->Texture.NumOffsets) {
1761 struct lp_build_context *uint_bld = &bld_base->uint_bld;
1762 struct lp_build_tgsi_soa_context *bld = lp_soa_context(bld_base);
1763 const struct tgsi_texture_offset * off = inst->TexOffsets;
1764
1765 assert(inst->Texture.NumOffsets == 1);
1766
1767 switch (target) {
1768 case TGSI_TEXTURE_3D:
1769 address[2] = lp_build_add(uint_bld, address[2],
1770 bld->immediates[off->Index][off->SwizzleZ]);
1771 /* fall through */
1772 case TGSI_TEXTURE_2D:
1773 case TGSI_TEXTURE_SHADOW2D:
1774 case TGSI_TEXTURE_RECT:
1775 case TGSI_TEXTURE_SHADOWRECT:
1776 case TGSI_TEXTURE_2D_ARRAY:
1777 case TGSI_TEXTURE_SHADOW2D_ARRAY:
1778 address[1] =
1779 lp_build_add(uint_bld, address[1],
1780 bld->immediates[off->Index][off->SwizzleY]);
1781 /* fall through */
1782 case TGSI_TEXTURE_1D:
1783 case TGSI_TEXTURE_SHADOW1D:
1784 case TGSI_TEXTURE_1D_ARRAY:
1785 case TGSI_TEXTURE_SHADOW1D_ARRAY:
1786 address[0] =
1787 lp_build_add(uint_bld, address[0],
1788 bld->immediates[off->Index][off->SwizzleX]);
1789 break;
1790 /* texture offsets do not apply to other texture targets */
1791 }
1792 }
1793
1794 emit_data->args[2] = lp_build_const_int32(gallivm, target);
1795 emit_data->arg_count = 3;
1796
1797 emit_data->dst_type = LLVMVectorType(
1798 LLVMInt32TypeInContext(gallivm->context),
1799 4);
1800 } else if (opcode == TGSI_OPCODE_TG4 ||
1801 opcode == TGSI_OPCODE_LODQ ||
1802 has_offset) {
1803 unsigned is_array = target == TGSI_TEXTURE_1D_ARRAY ||
1804 target == TGSI_TEXTURE_SHADOW1D_ARRAY ||
1805 target == TGSI_TEXTURE_2D_ARRAY ||
1806 target == TGSI_TEXTURE_SHADOW2D_ARRAY ||
1807 target == TGSI_TEXTURE_CUBE_ARRAY ||
1808 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY;
1809 unsigned is_rect = target == TGSI_TEXTURE_RECT;
1810 unsigned dmask = 0xf;
1811
1812 if (opcode == TGSI_OPCODE_TG4) {
1813 unsigned gather_comp = 0;
1814
1815 /* DMASK was repurposed for GATHER4. 4 components are always
1816 * returned and DMASK works like a swizzle - it selects
1817 * the component to fetch. The only valid DMASK values are
1818 * 1=red, 2=green, 4=blue, 8=alpha. (e.g. 1 returns
1819 * (red,red,red,red) etc.) The ISA document doesn't mention
1820 * this.
1821 */
1822
1823 /* Get the component index from src1.x for Gather4. */
1824 if (!tgsi_is_shadow_sampler(target)) {
1825 LLVMValueRef (*imms)[4] = lp_soa_context(bld_base)->immediates;
1826 LLVMValueRef comp_imm;
1827 struct tgsi_src_register src1 = inst->Src[1].Register;
1828
1829 assert(src1.File == TGSI_FILE_IMMEDIATE);
1830
1831 comp_imm = imms[src1.Index][src1.SwizzleX];
1832 gather_comp = LLVMConstIntGetZExtValue(comp_imm);
1833 gather_comp = CLAMP(gather_comp, 0, 3);
1834 }
1835
1836 dmask = 1 << gather_comp;
1837 }
1838
1839 emit_data->args[2] = si_shader_ctx->samplers[sampler_index];
1840 emit_data->args[3] = lp_build_const_int32(gallivm, dmask);
1841 emit_data->args[4] = lp_build_const_int32(gallivm, is_rect); /* unorm */
1842 emit_data->args[5] = lp_build_const_int32(gallivm, 0); /* r128 */
1843 emit_data->args[6] = lp_build_const_int32(gallivm, is_array); /* da */
1844 emit_data->args[7] = lp_build_const_int32(gallivm, 0); /* glc */
1845 emit_data->args[8] = lp_build_const_int32(gallivm, 0); /* slc */
1846 emit_data->args[9] = lp_build_const_int32(gallivm, 0); /* tfe */
1847 emit_data->args[10] = lp_build_const_int32(gallivm, 0); /* lwe */
1848
1849 emit_data->arg_count = 11;
1850
1851 emit_data->dst_type = LLVMVectorType(
1852 LLVMFloatTypeInContext(gallivm->context),
1853 4);
1854 } else {
1855 emit_data->args[2] = si_shader_ctx->samplers[sampler_index];
1856 emit_data->args[3] = lp_build_const_int32(gallivm, target);
1857 emit_data->arg_count = 4;
1858
1859 emit_data->dst_type = LLVMVectorType(
1860 LLVMFloatTypeInContext(gallivm->context),
1861 4);
1862 }
1863
1864 /* The fetch opcode has been converted to a 2D array fetch.
1865 * This simplifies the LLVM backend. */
1866 if (target == TGSI_TEXTURE_CUBE_ARRAY)
1867 target = TGSI_TEXTURE_2D_ARRAY;
1868 else if (target == TGSI_TEXTURE_SHADOWCUBE_ARRAY)
1869 target = TGSI_TEXTURE_SHADOW2D_ARRAY;
1870
1871 /* Pad to power of two vector */
1872 while (count < util_next_power_of_two(count))
1873 address[count++] = LLVMGetUndef(LLVMInt32TypeInContext(gallivm->context));
1874
1875 emit_data->args[0] = lp_build_gather_values(gallivm, address, count);
1876 }
1877
1878 static void build_tex_intrinsic(const struct lp_build_tgsi_action * action,
1879 struct lp_build_tgsi_context * bld_base,
1880 struct lp_build_emit_data * emit_data)
1881 {
1882 struct lp_build_context * base = &bld_base->base;
1883 unsigned opcode = emit_data->inst->Instruction.Opcode;
1884 unsigned target = emit_data->inst->Texture.Texture;
1885 char intr_name[127];
1886 bool has_offset = HAVE_LLVM >= 0x0305 ?
1887 emit_data->inst->Texture.NumOffsets > 0 : false;
1888
1889 if (target == TGSI_TEXTURE_BUFFER) {
1890 emit_data->output[emit_data->chan] = build_intrinsic(
1891 base->gallivm->builder,
1892 "llvm.SI.vs.load.input", emit_data->dst_type,
1893 emit_data->args, emit_data->arg_count,
1894 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
1895 return;
1896 }
1897
1898 if (opcode == TGSI_OPCODE_TG4 ||
1899 opcode == TGSI_OPCODE_LODQ ||
1900 (opcode != TGSI_OPCODE_TXF && has_offset)) {
1901 bool is_shadow = tgsi_is_shadow_sampler(target);
1902 const char *name = "llvm.SI.image.sample";
1903 const char *infix = "";
1904
1905 switch (opcode) {
1906 case TGSI_OPCODE_TEX:
1907 case TGSI_OPCODE_TEX2:
1908 case TGSI_OPCODE_TXP:
1909 break;
1910 case TGSI_OPCODE_TXB:
1911 case TGSI_OPCODE_TXB2:
1912 infix = ".b";
1913 break;
1914 case TGSI_OPCODE_TXL:
1915 case TGSI_OPCODE_TXL2:
1916 infix = ".l";
1917 break;
1918 case TGSI_OPCODE_TXD:
1919 infix = ".d";
1920 break;
1921 case TGSI_OPCODE_TG4:
1922 name = "llvm.SI.gather4";
1923 break;
1924 case TGSI_OPCODE_LODQ:
1925 name = "llvm.SI.getlod";
1926 is_shadow = false;
1927 has_offset = false;
1928 break;
1929 default:
1930 assert(0);
1931 return;
1932 }
1933
1934 /* Add the type and suffixes .c, .o if needed. */
1935 sprintf(intr_name, "%s%s%s%s.v%ui32", name,
1936 is_shadow ? ".c" : "", infix, has_offset ? ".o" : "",
1937 LLVMGetVectorSize(LLVMTypeOf(emit_data->args[0])));
1938
1939 emit_data->output[emit_data->chan] = build_intrinsic(
1940 base->gallivm->builder, intr_name, emit_data->dst_type,
1941 emit_data->args, emit_data->arg_count,
1942 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
1943 } else {
1944 LLVMTypeRef i8, v16i8, v32i8;
1945 const char *name;
1946
1947 switch (opcode) {
1948 case TGSI_OPCODE_TEX:
1949 case TGSI_OPCODE_TEX2:
1950 case TGSI_OPCODE_TXP:
1951 name = "llvm.SI.sample";
1952 break;
1953 case TGSI_OPCODE_TXB:
1954 case TGSI_OPCODE_TXB2:
1955 name = "llvm.SI.sampleb";
1956 break;
1957 case TGSI_OPCODE_TXD:
1958 name = "llvm.SI.sampled";
1959 break;
1960 case TGSI_OPCODE_TXF:
1961 name = "llvm.SI.imageload";
1962 break;
1963 case TGSI_OPCODE_TXL:
1964 case TGSI_OPCODE_TXL2:
1965 name = "llvm.SI.samplel";
1966 break;
1967 default:
1968 assert(0);
1969 return;
1970 }
1971
1972 i8 = LLVMInt8TypeInContext(base->gallivm->context);
1973 v16i8 = LLVMVectorType(i8, 16);
1974 v32i8 = LLVMVectorType(i8, 32);
1975
1976 emit_data->args[1] = LLVMBuildBitCast(base->gallivm->builder,
1977 emit_data->args[1], v32i8, "");
1978 if (opcode != TGSI_OPCODE_TXF) {
1979 emit_data->args[2] = LLVMBuildBitCast(base->gallivm->builder,
1980 emit_data->args[2], v16i8, "");
1981 }
1982
1983 sprintf(intr_name, "%s.v%ui32", name,
1984 LLVMGetVectorSize(LLVMTypeOf(emit_data->args[0])));
1985
1986 emit_data->output[emit_data->chan] = build_intrinsic(
1987 base->gallivm->builder, intr_name, emit_data->dst_type,
1988 emit_data->args, emit_data->arg_count,
1989 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
1990 }
1991 }
1992
1993 static void txq_fetch_args(
1994 struct lp_build_tgsi_context * bld_base,
1995 struct lp_build_emit_data * emit_data)
1996 {
1997 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
1998 const struct tgsi_full_instruction *inst = emit_data->inst;
1999 struct gallivm_state *gallivm = bld_base->base.gallivm;
2000 unsigned target = inst->Texture.Texture;
2001
2002 if (target == TGSI_TEXTURE_BUFFER) {
2003 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
2004 LLVMTypeRef v8i32 = LLVMVectorType(i32, 8);
2005
2006 /* Read the size from the buffer descriptor directly. */
2007 LLVMValueRef size = si_shader_ctx->resources[inst->Src[1].Register.Index];
2008 size = LLVMBuildBitCast(gallivm->builder, size, v8i32, "");
2009 size = LLVMBuildExtractElement(gallivm->builder, size,
2010 lp_build_const_int32(gallivm, 2), "");
2011 emit_data->args[0] = size;
2012 return;
2013 }
2014
2015 /* Mip level */
2016 emit_data->args[0] = lp_build_emit_fetch(bld_base, inst, 0, TGSI_CHAN_X);
2017
2018 /* Resource */
2019 emit_data->args[1] = si_shader_ctx->resources[inst->Src[1].Register.Index];
2020
2021 /* Texture target */
2022 if (target == TGSI_TEXTURE_CUBE_ARRAY ||
2023 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY)
2024 target = TGSI_TEXTURE_2D_ARRAY;
2025
2026 emit_data->args[2] = lp_build_const_int32(bld_base->base.gallivm,
2027 target);
2028
2029 emit_data->arg_count = 3;
2030
2031 emit_data->dst_type = LLVMVectorType(
2032 LLVMInt32TypeInContext(bld_base->base.gallivm->context),
2033 4);
2034 }
2035
2036 static void build_txq_intrinsic(const struct lp_build_tgsi_action * action,
2037 struct lp_build_tgsi_context * bld_base,
2038 struct lp_build_emit_data * emit_data)
2039 {
2040 unsigned target = emit_data->inst->Texture.Texture;
2041
2042 if (target == TGSI_TEXTURE_BUFFER) {
2043 /* Just return the buffer size. */
2044 emit_data->output[emit_data->chan] = emit_data->args[0];
2045 return;
2046 }
2047
2048 build_tgsi_intrinsic_nomem(action, bld_base, emit_data);
2049
2050 /* Divide the number of layers by 6 to get the number of cubes. */
2051 if (target == TGSI_TEXTURE_CUBE_ARRAY ||
2052 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
2053 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
2054 LLVMValueRef two = lp_build_const_int32(bld_base->base.gallivm, 2);
2055 LLVMValueRef six = lp_build_const_int32(bld_base->base.gallivm, 6);
2056
2057 LLVMValueRef v4 = emit_data->output[emit_data->chan];
2058 LLVMValueRef z = LLVMBuildExtractElement(builder, v4, two, "");
2059 z = LLVMBuildSDiv(builder, z, six, "");
2060
2061 emit_data->output[emit_data->chan] =
2062 LLVMBuildInsertElement(builder, v4, z, two, "");
2063 }
2064 }
2065
2066 static void si_llvm_emit_ddxy(
2067 const struct lp_build_tgsi_action * action,
2068 struct lp_build_tgsi_context * bld_base,
2069 struct lp_build_emit_data * emit_data)
2070 {
2071 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
2072 struct gallivm_state *gallivm = bld_base->base.gallivm;
2073 struct lp_build_context * base = &bld_base->base;
2074 const struct tgsi_full_instruction *inst = emit_data->inst;
2075 unsigned opcode = inst->Instruction.Opcode;
2076 LLVMValueRef indices[2];
2077 LLVMValueRef store_ptr, load_ptr0, load_ptr1;
2078 LLVMValueRef tl, trbl, result[4];
2079 LLVMTypeRef i32;
2080 unsigned swizzle[4];
2081 unsigned c;
2082
2083 i32 = LLVMInt32TypeInContext(gallivm->context);
2084
2085 indices[0] = bld_base->uint_bld.zero;
2086 indices[1] = build_intrinsic(gallivm->builder, "llvm.SI.tid", i32,
2087 NULL, 0, LLVMReadNoneAttribute);
2088 store_ptr = LLVMBuildGEP(gallivm->builder, si_shader_ctx->ddxy_lds,
2089 indices, 2, "");
2090
2091 indices[1] = LLVMBuildAnd(gallivm->builder, indices[1],
2092 lp_build_const_int32(gallivm, 0xfffffffc), "");
2093 load_ptr0 = LLVMBuildGEP(gallivm->builder, si_shader_ctx->ddxy_lds,
2094 indices, 2, "");
2095
2096 indices[1] = LLVMBuildAdd(gallivm->builder, indices[1],
2097 lp_build_const_int32(gallivm,
2098 opcode == TGSI_OPCODE_DDX ? 1 : 2),
2099 "");
2100 load_ptr1 = LLVMBuildGEP(gallivm->builder, si_shader_ctx->ddxy_lds,
2101 indices, 2, "");
2102
2103 for (c = 0; c < 4; ++c) {
2104 unsigned i;
2105
2106 swizzle[c] = tgsi_util_get_full_src_register_swizzle(&inst->Src[0], c);
2107 for (i = 0; i < c; ++i) {
2108 if (swizzle[i] == swizzle[c]) {
2109 result[c] = result[i];
2110 break;
2111 }
2112 }
2113 if (i != c)
2114 continue;
2115
2116 LLVMBuildStore(gallivm->builder,
2117 LLVMBuildBitCast(gallivm->builder,
2118 lp_build_emit_fetch(bld_base, inst, 0, c),
2119 i32, ""),
2120 store_ptr);
2121
2122 tl = LLVMBuildLoad(gallivm->builder, load_ptr0, "");
2123 tl = LLVMBuildBitCast(gallivm->builder, tl, base->elem_type, "");
2124
2125 trbl = LLVMBuildLoad(gallivm->builder, load_ptr1, "");
2126 trbl = LLVMBuildBitCast(gallivm->builder, trbl, base->elem_type, "");
2127
2128 result[c] = LLVMBuildFSub(gallivm->builder, trbl, tl, "");
2129 }
2130
2131 emit_data->output[0] = lp_build_gather_values(gallivm, result, 4);
2132 }
2133
2134 /* Emit one vertex from the geometry shader */
2135 static void si_llvm_emit_vertex(
2136 const struct lp_build_tgsi_action *action,
2137 struct lp_build_tgsi_context *bld_base,
2138 struct lp_build_emit_data *emit_data)
2139 {
2140 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
2141 struct lp_build_context *uint = &bld_base->uint_bld;
2142 struct si_shader *shader = si_shader_ctx->shader;
2143 struct tgsi_shader_info *info = &shader->selector->info;
2144 struct gallivm_state *gallivm = bld_base->base.gallivm;
2145 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
2146 LLVMValueRef soffset = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
2147 SI_PARAM_GS2VS_OFFSET);
2148 LLVMValueRef gs_next_vertex;
2149 LLVMValueRef can_emit, kill;
2150 LLVMValueRef args[2];
2151 unsigned chan;
2152 int i;
2153
2154 /* Write vertex attribute values to GSVS ring */
2155 gs_next_vertex = LLVMBuildLoad(gallivm->builder, si_shader_ctx->gs_next_vertex, "");
2156
2157 /* If this thread has already emitted the declared maximum number of
2158 * vertices, kill it: excessive vertex emissions are not supposed to
2159 * have any effect, and GS threads have no externally observable
2160 * effects other than emitting vertices.
2161 */
2162 can_emit = LLVMBuildICmp(gallivm->builder, LLVMIntULE, gs_next_vertex,
2163 lp_build_const_int32(gallivm,
2164 shader->selector->gs_max_out_vertices), "");
2165 kill = lp_build_select(&bld_base->base, can_emit,
2166 lp_build_const_float(gallivm, 1.0f),
2167 lp_build_const_float(gallivm, -1.0f));
2168 build_intrinsic(gallivm->builder, "llvm.AMDGPU.kill",
2169 LLVMVoidTypeInContext(gallivm->context), &kill, 1, 0);
2170
2171 for (i = 0; i < info->num_outputs; i++) {
2172 LLVMValueRef *out_ptr =
2173 si_shader_ctx->radeon_bld.soa.outputs[i];
2174
2175 for (chan = 0; chan < 4; chan++) {
2176 LLVMValueRef out_val = LLVMBuildLoad(gallivm->builder, out_ptr[chan], "");
2177 LLVMValueRef voffset =
2178 lp_build_const_int32(gallivm, (i * 4 + chan) *
2179 shader->selector->gs_max_out_vertices);
2180
2181 voffset = lp_build_add(uint, voffset, gs_next_vertex);
2182 voffset = lp_build_mul_imm(uint, voffset, 4);
2183
2184 out_val = LLVMBuildBitCast(gallivm->builder, out_val, i32, "");
2185
2186 build_tbuffer_store(si_shader_ctx,
2187 si_shader_ctx->gsvs_ring,
2188 out_val, 1,
2189 voffset, soffset, 0,
2190 V_008F0C_BUF_DATA_FORMAT_32,
2191 V_008F0C_BUF_NUM_FORMAT_UINT,
2192 1, 0, 1, 1, 0);
2193 }
2194 }
2195 gs_next_vertex = lp_build_add(uint, gs_next_vertex,
2196 lp_build_const_int32(gallivm, 1));
2197 LLVMBuildStore(gallivm->builder, gs_next_vertex, si_shader_ctx->gs_next_vertex);
2198
2199 /* Signal vertex emission */
2200 args[0] = lp_build_const_int32(gallivm, SENDMSG_GS_OP_EMIT | SENDMSG_GS);
2201 args[1] = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_GS_WAVE_ID);
2202 build_intrinsic(gallivm->builder, "llvm.SI.sendmsg",
2203 LLVMVoidTypeInContext(gallivm->context), args, 2,
2204 LLVMNoUnwindAttribute);
2205 }
2206
2207 /* Cut one primitive from the geometry shader */
2208 static void si_llvm_emit_primitive(
2209 const struct lp_build_tgsi_action *action,
2210 struct lp_build_tgsi_context *bld_base,
2211 struct lp_build_emit_data *emit_data)
2212 {
2213 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
2214 struct gallivm_state *gallivm = bld_base->base.gallivm;
2215 LLVMValueRef args[2];
2216
2217 /* Signal primitive cut */
2218 args[0] = lp_build_const_int32(gallivm, SENDMSG_GS_OP_CUT | SENDMSG_GS);
2219 args[1] = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_GS_WAVE_ID);
2220 build_intrinsic(gallivm->builder, "llvm.SI.sendmsg",
2221 LLVMVoidTypeInContext(gallivm->context), args, 2,
2222 LLVMNoUnwindAttribute);
2223 }
2224
2225 static const struct lp_build_tgsi_action tex_action = {
2226 .fetch_args = tex_fetch_args,
2227 .emit = build_tex_intrinsic,
2228 };
2229
2230 static const struct lp_build_tgsi_action txq_action = {
2231 .fetch_args = txq_fetch_args,
2232 .emit = build_txq_intrinsic,
2233 .intr_name = "llvm.SI.resinfo"
2234 };
2235
2236 static void create_meta_data(struct si_shader_context *si_shader_ctx)
2237 {
2238 struct gallivm_state *gallivm = si_shader_ctx->radeon_bld.soa.bld_base.base.gallivm;
2239 LLVMValueRef args[3];
2240
2241 args[0] = LLVMMDStringInContext(gallivm->context, "const", 5);
2242 args[1] = 0;
2243 args[2] = lp_build_const_int32(gallivm, 1);
2244
2245 si_shader_ctx->const_md = LLVMMDNodeInContext(gallivm->context, args, 3);
2246 }
2247
2248 static LLVMTypeRef const_array(LLVMTypeRef elem_type, int num_elements)
2249 {
2250 return LLVMPointerType(LLVMArrayType(elem_type, num_elements),
2251 CONST_ADDR_SPACE);
2252 }
2253
2254 static void create_function(struct si_shader_context *si_shader_ctx)
2255 {
2256 struct lp_build_tgsi_context *bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
2257 struct gallivm_state *gallivm = bld_base->base.gallivm;
2258 struct si_shader *shader = si_shader_ctx->shader;
2259 LLVMTypeRef params[SI_NUM_PARAMS], f32, i8, i32, v2i32, v3i32, v16i8, v4i32, v8i32;
2260 unsigned i, last_array_pointer, last_sgpr, num_params;
2261
2262 i8 = LLVMInt8TypeInContext(gallivm->context);
2263 i32 = LLVMInt32TypeInContext(gallivm->context);
2264 f32 = LLVMFloatTypeInContext(gallivm->context);
2265 v2i32 = LLVMVectorType(i32, 2);
2266 v3i32 = LLVMVectorType(i32, 3);
2267 v4i32 = LLVMVectorType(i32, 4);
2268 v8i32 = LLVMVectorType(i32, 8);
2269 v16i8 = LLVMVectorType(i8, 16);
2270
2271 params[SI_PARAM_RW_BUFFERS] = const_array(v16i8, SI_NUM_RW_BUFFERS);
2272 params[SI_PARAM_CONST] = const_array(v16i8, SI_NUM_CONST_BUFFERS);
2273 params[SI_PARAM_SAMPLER] = const_array(v4i32, SI_NUM_SAMPLER_STATES);
2274 params[SI_PARAM_RESOURCE] = const_array(v8i32, SI_NUM_SAMPLER_VIEWS);
2275 last_array_pointer = SI_PARAM_RESOURCE;
2276
2277 switch (si_shader_ctx->type) {
2278 case TGSI_PROCESSOR_VERTEX:
2279 params[SI_PARAM_VERTEX_BUFFER] = const_array(v16i8, SI_NUM_VERTEX_BUFFERS);
2280 last_array_pointer = SI_PARAM_VERTEX_BUFFER;
2281 params[SI_PARAM_BASE_VERTEX] = i32;
2282 params[SI_PARAM_START_INSTANCE] = i32;
2283 num_params = SI_PARAM_START_INSTANCE+1;
2284
2285 if (shader->key.vs.as_es) {
2286 params[SI_PARAM_ES2GS_OFFSET] = i32;
2287 num_params++;
2288 } else {
2289 if (shader->is_gs_copy_shader) {
2290 last_array_pointer = SI_PARAM_CONST;
2291 num_params = SI_PARAM_CONST+1;
2292 }
2293
2294 /* The locations of the other parameters are assigned dynamically. */
2295
2296 /* Streamout SGPRs. */
2297 if (shader->selector->so.num_outputs) {
2298 params[si_shader_ctx->param_streamout_config = num_params++] = i32;
2299 params[si_shader_ctx->param_streamout_write_index = num_params++] = i32;
2300 }
2301 /* A streamout buffer offset is loaded if the stride is non-zero. */
2302 for (i = 0; i < 4; i++) {
2303 if (!shader->selector->so.stride[i])
2304 continue;
2305
2306 params[si_shader_ctx->param_streamout_offset[i] = num_params++] = i32;
2307 }
2308 }
2309
2310 last_sgpr = num_params-1;
2311
2312 /* VGPRs */
2313 params[si_shader_ctx->param_vertex_id = num_params++] = i32;
2314 params[num_params++] = i32; /* unused*/
2315 params[num_params++] = i32; /* unused */
2316 params[si_shader_ctx->param_instance_id = num_params++] = i32;
2317 break;
2318
2319 case TGSI_PROCESSOR_GEOMETRY:
2320 params[SI_PARAM_GS2VS_OFFSET] = i32;
2321 params[SI_PARAM_GS_WAVE_ID] = i32;
2322 last_sgpr = SI_PARAM_GS_WAVE_ID;
2323
2324 /* VGPRs */
2325 params[SI_PARAM_VTX0_OFFSET] = i32;
2326 params[SI_PARAM_VTX1_OFFSET] = i32;
2327 params[SI_PARAM_PRIMITIVE_ID] = i32;
2328 params[SI_PARAM_VTX2_OFFSET] = i32;
2329 params[SI_PARAM_VTX3_OFFSET] = i32;
2330 params[SI_PARAM_VTX4_OFFSET] = i32;
2331 params[SI_PARAM_VTX5_OFFSET] = i32;
2332 params[SI_PARAM_GS_INSTANCE_ID] = i32;
2333 num_params = SI_PARAM_GS_INSTANCE_ID+1;
2334 break;
2335
2336 case TGSI_PROCESSOR_FRAGMENT:
2337 params[SI_PARAM_ALPHA_REF] = f32;
2338 params[SI_PARAM_PRIM_MASK] = i32;
2339 last_sgpr = SI_PARAM_PRIM_MASK;
2340 params[SI_PARAM_PERSP_SAMPLE] = v2i32;
2341 params[SI_PARAM_PERSP_CENTER] = v2i32;
2342 params[SI_PARAM_PERSP_CENTROID] = v2i32;
2343 params[SI_PARAM_PERSP_PULL_MODEL] = v3i32;
2344 params[SI_PARAM_LINEAR_SAMPLE] = v2i32;
2345 params[SI_PARAM_LINEAR_CENTER] = v2i32;
2346 params[SI_PARAM_LINEAR_CENTROID] = v2i32;
2347 params[SI_PARAM_LINE_STIPPLE_TEX] = f32;
2348 params[SI_PARAM_POS_X_FLOAT] = f32;
2349 params[SI_PARAM_POS_Y_FLOAT] = f32;
2350 params[SI_PARAM_POS_Z_FLOAT] = f32;
2351 params[SI_PARAM_POS_W_FLOAT] = f32;
2352 params[SI_PARAM_FRONT_FACE] = f32;
2353 params[SI_PARAM_ANCILLARY] = i32;
2354 params[SI_PARAM_SAMPLE_COVERAGE] = f32;
2355 params[SI_PARAM_POS_FIXED_PT] = f32;
2356 num_params = SI_PARAM_POS_FIXED_PT+1;
2357 break;
2358
2359 default:
2360 assert(0 && "unimplemented shader");
2361 return;
2362 }
2363
2364 assert(num_params <= Elements(params));
2365 radeon_llvm_create_func(&si_shader_ctx->radeon_bld, params, num_params);
2366 radeon_llvm_shader_type(si_shader_ctx->radeon_bld.main_fn, si_shader_ctx->type);
2367
2368 for (i = 0; i <= last_sgpr; ++i) {
2369 LLVMValueRef P = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, i);
2370
2371 /* We tell llvm that array inputs are passed by value to allow Sinking pass
2372 * to move load. Inputs are constant so this is fine. */
2373 if (i <= last_array_pointer)
2374 LLVMAddAttribute(P, LLVMByValAttribute);
2375 else
2376 LLVMAddAttribute(P, LLVMInRegAttribute);
2377 }
2378
2379 if (bld_base->info &&
2380 (bld_base->info->opcode_count[TGSI_OPCODE_DDX] > 0 ||
2381 bld_base->info->opcode_count[TGSI_OPCODE_DDY] > 0))
2382 si_shader_ctx->ddxy_lds =
2383 LLVMAddGlobalInAddressSpace(gallivm->module,
2384 LLVMArrayType(i32, 64),
2385 "ddxy_lds",
2386 LOCAL_ADDR_SPACE);
2387 }
2388
2389 static void preload_constants(struct si_shader_context *si_shader_ctx)
2390 {
2391 struct lp_build_tgsi_context * bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
2392 struct gallivm_state * gallivm = bld_base->base.gallivm;
2393 const struct tgsi_shader_info * info = bld_base->info;
2394 unsigned buf;
2395 LLVMValueRef ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_CONST);
2396
2397 for (buf = 0; buf < SI_NUM_CONST_BUFFERS; buf++) {
2398 unsigned i, num_const = info->const_file_max[buf] + 1;
2399
2400 if (num_const == 0)
2401 continue;
2402
2403 /* Allocate space for the constant values */
2404 si_shader_ctx->constants[buf] = CALLOC(num_const * 4, sizeof(LLVMValueRef));
2405
2406 /* Load the resource descriptor */
2407 si_shader_ctx->const_resource[buf] =
2408 build_indexed_load_const(si_shader_ctx, ptr, lp_build_const_int32(gallivm, buf));
2409
2410 /* Load the constants, we rely on the code sinking to do the rest */
2411 for (i = 0; i < num_const * 4; ++i) {
2412 si_shader_ctx->constants[buf][i] =
2413 buffer_load_const(gallivm->builder,
2414 si_shader_ctx->const_resource[buf],
2415 lp_build_const_int32(gallivm, i * 4),
2416 bld_base->base.elem_type);
2417 }
2418 }
2419 }
2420
2421 static void preload_samplers(struct si_shader_context *si_shader_ctx)
2422 {
2423 struct lp_build_tgsi_context * bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
2424 struct gallivm_state * gallivm = bld_base->base.gallivm;
2425 const struct tgsi_shader_info * info = bld_base->info;
2426
2427 unsigned i, num_samplers = info->file_max[TGSI_FILE_SAMPLER] + 1;
2428
2429 LLVMValueRef res_ptr, samp_ptr;
2430 LLVMValueRef offset;
2431
2432 if (num_samplers == 0)
2433 return;
2434
2435 res_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_RESOURCE);
2436 samp_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_SAMPLER);
2437
2438 /* Load the resources and samplers, we rely on the code sinking to do the rest */
2439 for (i = 0; i < num_samplers; ++i) {
2440 /* Resource */
2441 offset = lp_build_const_int32(gallivm, i);
2442 si_shader_ctx->resources[i] = build_indexed_load_const(si_shader_ctx, res_ptr, offset);
2443
2444 /* Sampler */
2445 offset = lp_build_const_int32(gallivm, i);
2446 si_shader_ctx->samplers[i] = build_indexed_load_const(si_shader_ctx, samp_ptr, offset);
2447
2448 /* FMASK resource */
2449 if (info->is_msaa_sampler[i]) {
2450 offset = lp_build_const_int32(gallivm, SI_FMASK_TEX_OFFSET + i);
2451 si_shader_ctx->resources[SI_FMASK_TEX_OFFSET + i] =
2452 build_indexed_load_const(si_shader_ctx, res_ptr, offset);
2453 }
2454 }
2455 }
2456
2457 static void preload_streamout_buffers(struct si_shader_context *si_shader_ctx)
2458 {
2459 struct lp_build_tgsi_context * bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
2460 struct gallivm_state * gallivm = bld_base->base.gallivm;
2461 unsigned i;
2462
2463 if (si_shader_ctx->type != TGSI_PROCESSOR_VERTEX ||
2464 si_shader_ctx->shader->key.vs.as_es ||
2465 !si_shader_ctx->shader->selector->so.num_outputs)
2466 return;
2467
2468 LLVMValueRef buf_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
2469 SI_PARAM_RW_BUFFERS);
2470
2471 /* Load the resources, we rely on the code sinking to do the rest */
2472 for (i = 0; i < 4; ++i) {
2473 if (si_shader_ctx->shader->selector->so.stride[i]) {
2474 LLVMValueRef offset = lp_build_const_int32(gallivm,
2475 SI_SO_BUF_OFFSET + i);
2476
2477 si_shader_ctx->so_buffers[i] = build_indexed_load_const(si_shader_ctx, buf_ptr, offset);
2478 }
2479 }
2480 }
2481
2482 /**
2483 * Load ESGS and GSVS ring buffer resource descriptors and save the variables
2484 * for later use.
2485 */
2486 static void preload_ring_buffers(struct si_shader_context *si_shader_ctx)
2487 {
2488 struct gallivm_state *gallivm =
2489 si_shader_ctx->radeon_bld.soa.bld_base.base.gallivm;
2490
2491 LLVMValueRef buf_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
2492 SI_PARAM_RW_BUFFERS);
2493
2494 if ((si_shader_ctx->type == TGSI_PROCESSOR_VERTEX &&
2495 si_shader_ctx->shader->key.vs.as_es) ||
2496 si_shader_ctx->type == TGSI_PROCESSOR_GEOMETRY) {
2497 LLVMValueRef offset = lp_build_const_int32(gallivm, SI_RING_ESGS);
2498
2499 si_shader_ctx->esgs_ring =
2500 build_indexed_load_const(si_shader_ctx, buf_ptr, offset);
2501 }
2502
2503 if (si_shader_ctx->type == TGSI_PROCESSOR_GEOMETRY ||
2504 si_shader_ctx->shader->is_gs_copy_shader) {
2505 LLVMValueRef offset = lp_build_const_int32(gallivm, SI_RING_GSVS);
2506
2507 si_shader_ctx->gsvs_ring =
2508 build_indexed_load_const(si_shader_ctx, buf_ptr, offset);
2509 }
2510 }
2511
2512 void si_shader_binary_read_config(const struct radeon_shader_binary *binary,
2513 struct si_shader *shader,
2514 unsigned symbol_offset)
2515 {
2516 unsigned i;
2517 const unsigned char *config =
2518 radeon_shader_binary_config_start(binary, symbol_offset);
2519
2520 /* XXX: We may be able to emit some of these values directly rather than
2521 * extracting fields to be emitted later.
2522 */
2523
2524 for (i = 0; i < binary->config_size_per_symbol; i+= 8) {
2525 unsigned reg = util_le32_to_cpu(*(uint32_t*)(config + i));
2526 unsigned value = util_le32_to_cpu(*(uint32_t*)(config + i + 4));
2527 switch (reg) {
2528 case R_00B028_SPI_SHADER_PGM_RSRC1_PS:
2529 case R_00B128_SPI_SHADER_PGM_RSRC1_VS:
2530 case R_00B228_SPI_SHADER_PGM_RSRC1_GS:
2531 case R_00B848_COMPUTE_PGM_RSRC1:
2532 shader->num_sgprs = MAX2(shader->num_sgprs, (G_00B028_SGPRS(value) + 1) * 8);
2533 shader->num_vgprs = MAX2(shader->num_vgprs, (G_00B028_VGPRS(value) + 1) * 4);
2534 break;
2535 case R_00B02C_SPI_SHADER_PGM_RSRC2_PS:
2536 shader->lds_size = MAX2(shader->lds_size, G_00B02C_EXTRA_LDS_SIZE(value));
2537 break;
2538 case R_00B84C_COMPUTE_PGM_RSRC2:
2539 shader->lds_size = MAX2(shader->lds_size, G_00B84C_LDS_SIZE(value));
2540 break;
2541 case R_0286CC_SPI_PS_INPUT_ENA:
2542 shader->spi_ps_input_ena = value;
2543 break;
2544 case R_00B860_COMPUTE_TMPRING_SIZE:
2545 /* WAVESIZE is in units of 256 dwords. */
2546 shader->scratch_bytes_per_wave =
2547 G_00B860_WAVESIZE(value) * 256 * 4 * 1;
2548 break;
2549 default:
2550 fprintf(stderr, "Warning: Compiler emitted unknown "
2551 "config register: 0x%x\n", reg);
2552 break;
2553 }
2554 }
2555 }
2556
2557 int si_shader_binary_read(struct si_screen *sscreen,
2558 struct si_shader *shader,
2559 const struct radeon_shader_binary *binary)
2560 {
2561
2562 unsigned i;
2563 unsigned code_size;
2564 unsigned char *ptr;
2565 bool dump = r600_can_dump_shader(&sscreen->b,
2566 shader->selector ? shader->selector->tokens : NULL);
2567
2568 if (dump && !binary->disassembled) {
2569 fprintf(stderr, "SI CODE:\n");
2570 for (i = 0; i < binary->code_size; i+=4 ) {
2571 fprintf(stderr, "@0x%x: %02x%02x%02x%02x\n", i, binary->code[i + 3],
2572 binary->code[i + 2], binary->code[i + 1],
2573 binary->code[i]);
2574 }
2575 }
2576
2577 si_shader_binary_read_config(binary, shader, 0);
2578
2579 /* copy new shader */
2580 code_size = binary->code_size + binary->rodata_size;
2581 r600_resource_reference(&shader->bo, NULL);
2582 shader->bo = si_resource_create_custom(&sscreen->b.b, PIPE_USAGE_IMMUTABLE,
2583 code_size);
2584 if (shader->bo == NULL) {
2585 return -ENOMEM;
2586 }
2587
2588
2589 ptr = sscreen->b.ws->buffer_map(shader->bo->cs_buf, NULL, PIPE_TRANSFER_READ_WRITE);
2590 util_memcpy_cpu_to_le32(ptr, binary->code, binary->code_size);
2591 if (binary->rodata_size > 0) {
2592 ptr += binary->code_size;
2593 util_memcpy_cpu_to_le32(ptr, binary->rodata, binary->rodata_size);
2594 }
2595
2596 sscreen->b.ws->buffer_unmap(shader->bo->cs_buf);
2597
2598 return 0;
2599 }
2600
2601 int si_compile_llvm(struct si_screen *sscreen, struct si_shader *shader,
2602 LLVMModuleRef mod)
2603 {
2604 int r = 0;
2605 struct radeon_shader_binary binary;
2606 bool dump = r600_can_dump_shader(&sscreen->b,
2607 shader->selector ? shader->selector->tokens : NULL);
2608 memset(&binary, 0, sizeof(binary));
2609 r = radeon_llvm_compile(mod, &binary,
2610 r600_get_llvm_processor_name(sscreen->b.family), dump, sscreen->tm);
2611
2612 if (r) {
2613 return r;
2614 }
2615 r = si_shader_binary_read(sscreen, shader, &binary);
2616 FREE(binary.code);
2617 FREE(binary.config);
2618 FREE(binary.rodata);
2619 return r;
2620 }
2621
2622 /* Generate code for the hardware VS shader stage to go with a geometry shader */
2623 static int si_generate_gs_copy_shader(struct si_screen *sscreen,
2624 struct si_shader_context *si_shader_ctx,
2625 struct si_shader *gs, bool dump)
2626 {
2627 struct gallivm_state *gallivm = &si_shader_ctx->radeon_bld.gallivm;
2628 struct lp_build_tgsi_context *bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
2629 struct lp_build_context *base = &bld_base->base;
2630 struct lp_build_context *uint = &bld_base->uint_bld;
2631 struct si_shader *shader = si_shader_ctx->shader;
2632 struct si_shader_output_values *outputs;
2633 struct tgsi_shader_info *gsinfo = &gs->selector->info;
2634 LLVMValueRef args[9];
2635 int i, r;
2636
2637 outputs = MALLOC(gsinfo->num_outputs * sizeof(outputs[0]));
2638
2639 si_shader_ctx->type = TGSI_PROCESSOR_VERTEX;
2640 shader->is_gs_copy_shader = true;
2641
2642 radeon_llvm_context_init(&si_shader_ctx->radeon_bld);
2643
2644 create_meta_data(si_shader_ctx);
2645 create_function(si_shader_ctx);
2646 preload_streamout_buffers(si_shader_ctx);
2647 preload_ring_buffers(si_shader_ctx);
2648
2649 args[0] = si_shader_ctx->gsvs_ring;
2650 args[1] = lp_build_mul_imm(uint,
2651 LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
2652 si_shader_ctx->param_vertex_id),
2653 4);
2654 args[3] = uint->zero;
2655 args[4] = uint->one; /* OFFEN */
2656 args[5] = uint->zero; /* IDXEN */
2657 args[6] = uint->one; /* GLC */
2658 args[7] = uint->one; /* SLC */
2659 args[8] = uint->zero; /* TFE */
2660
2661 /* Fetch vertex data from GSVS ring */
2662 for (i = 0; i < gsinfo->num_outputs; ++i) {
2663 unsigned chan;
2664
2665 outputs[i].name = gsinfo->output_semantic_name[i];
2666 outputs[i].sid = gsinfo->output_semantic_index[i];
2667
2668 for (chan = 0; chan < 4; chan++) {
2669 args[2] = lp_build_const_int32(gallivm,
2670 (i * 4 + chan) *
2671 gs->selector->gs_max_out_vertices * 16 * 4);
2672
2673 outputs[i].values[chan] =
2674 LLVMBuildBitCast(gallivm->builder,
2675 build_intrinsic(gallivm->builder,
2676 "llvm.SI.buffer.load.dword.i32.i32",
2677 LLVMInt32TypeInContext(gallivm->context),
2678 args, 9,
2679 LLVMReadOnlyAttribute | LLVMNoUnwindAttribute),
2680 base->elem_type, "");
2681 }
2682 }
2683
2684 si_llvm_export_vs(bld_base, outputs, gsinfo->num_outputs);
2685
2686 radeon_llvm_finalize_module(&si_shader_ctx->radeon_bld);
2687
2688 if (dump)
2689 fprintf(stderr, "Copy Vertex Shader for Geometry Shader:\n\n");
2690
2691 r = si_compile_llvm(sscreen, si_shader_ctx->shader,
2692 bld_base->base.gallivm->module);
2693
2694 radeon_llvm_dispose(&si_shader_ctx->radeon_bld);
2695
2696 FREE(outputs);
2697 return r;
2698 }
2699
2700 int si_shader_create(struct si_screen *sscreen, struct si_shader *shader)
2701 {
2702 struct si_shader_selector *sel = shader->selector;
2703 struct si_shader_context si_shader_ctx;
2704 struct lp_build_tgsi_context * bld_base;
2705 LLVMModuleRef mod;
2706 int r = 0;
2707 bool dump = r600_can_dump_shader(&sscreen->b, sel->tokens);
2708
2709 /* Dump TGSI code before doing TGSI->LLVM conversion in case the
2710 * conversion fails. */
2711 if (dump) {
2712 tgsi_dump(sel->tokens, 0);
2713 si_dump_streamout(&sel->so);
2714 }
2715
2716 assert(shader->nparam == 0);
2717
2718 memset(&si_shader_ctx, 0, sizeof(si_shader_ctx));
2719 radeon_llvm_context_init(&si_shader_ctx.radeon_bld);
2720 bld_base = &si_shader_ctx.radeon_bld.soa.bld_base;
2721
2722 if (sel->info.uses_kill)
2723 shader->db_shader_control |= S_02880C_KILL_ENABLE(1);
2724
2725 shader->uses_instanceid = sel->info.uses_instanceid;
2726 bld_base->info = &sel->info;
2727 bld_base->emit_fetch_funcs[TGSI_FILE_CONSTANT] = fetch_constant;
2728
2729 bld_base->op_actions[TGSI_OPCODE_TEX] = tex_action;
2730 bld_base->op_actions[TGSI_OPCODE_TEX2] = tex_action;
2731 bld_base->op_actions[TGSI_OPCODE_TXB] = tex_action;
2732 bld_base->op_actions[TGSI_OPCODE_TXB2] = tex_action;
2733 bld_base->op_actions[TGSI_OPCODE_TXD] = tex_action;
2734 bld_base->op_actions[TGSI_OPCODE_TXF] = tex_action;
2735 bld_base->op_actions[TGSI_OPCODE_TXL] = tex_action;
2736 bld_base->op_actions[TGSI_OPCODE_TXL2] = tex_action;
2737 bld_base->op_actions[TGSI_OPCODE_TXP] = tex_action;
2738 bld_base->op_actions[TGSI_OPCODE_TXQ] = txq_action;
2739 bld_base->op_actions[TGSI_OPCODE_TG4] = tex_action;
2740 bld_base->op_actions[TGSI_OPCODE_LODQ] = tex_action;
2741
2742 bld_base->op_actions[TGSI_OPCODE_DDX].emit = si_llvm_emit_ddxy;
2743 bld_base->op_actions[TGSI_OPCODE_DDY].emit = si_llvm_emit_ddxy;
2744
2745 bld_base->op_actions[TGSI_OPCODE_EMIT].emit = si_llvm_emit_vertex;
2746 bld_base->op_actions[TGSI_OPCODE_ENDPRIM].emit = si_llvm_emit_primitive;
2747
2748 if (HAVE_LLVM >= 0x0306) {
2749 bld_base->op_actions[TGSI_OPCODE_MAX].emit = build_tgsi_intrinsic_nomem;
2750 bld_base->op_actions[TGSI_OPCODE_MAX].intr_name = "llvm.maxnum.f32";
2751 bld_base->op_actions[TGSI_OPCODE_MIN].emit = build_tgsi_intrinsic_nomem;
2752 bld_base->op_actions[TGSI_OPCODE_MIN].intr_name = "llvm.minnum.f32";
2753 }
2754
2755 si_shader_ctx.radeon_bld.load_system_value = declare_system_value;
2756 si_shader_ctx.tokens = sel->tokens;
2757 tgsi_parse_init(&si_shader_ctx.parse, si_shader_ctx.tokens);
2758 si_shader_ctx.shader = shader;
2759 si_shader_ctx.type = si_shader_ctx.parse.FullHeader.Processor.Processor;
2760 si_shader_ctx.screen = sscreen;
2761
2762 switch (si_shader_ctx.type) {
2763 case TGSI_PROCESSOR_VERTEX:
2764 si_shader_ctx.radeon_bld.load_input = declare_input_vs;
2765 if (shader->key.vs.as_es) {
2766 bld_base->emit_epilogue = si_llvm_emit_es_epilogue;
2767 } else {
2768 bld_base->emit_epilogue = si_llvm_emit_vs_epilogue;
2769 }
2770 break;
2771 case TGSI_PROCESSOR_GEOMETRY:
2772 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_gs;
2773 bld_base->emit_epilogue = si_llvm_emit_gs_epilogue;
2774 break;
2775 case TGSI_PROCESSOR_FRAGMENT:
2776 si_shader_ctx.radeon_bld.load_input = declare_input_fs;
2777 bld_base->emit_epilogue = si_llvm_emit_fs_epilogue;
2778
2779 switch (sel->info.properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT]) {
2780 case TGSI_FS_DEPTH_LAYOUT_GREATER:
2781 shader->db_shader_control |=
2782 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_GREATER_THAN_Z);
2783 break;
2784 case TGSI_FS_DEPTH_LAYOUT_LESS:
2785 shader->db_shader_control |=
2786 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_LESS_THAN_Z);
2787 break;
2788 }
2789 break;
2790 default:
2791 assert(!"Unsupported shader type");
2792 return -1;
2793 }
2794
2795 create_meta_data(&si_shader_ctx);
2796 create_function(&si_shader_ctx);
2797 preload_constants(&si_shader_ctx);
2798 preload_samplers(&si_shader_ctx);
2799 preload_streamout_buffers(&si_shader_ctx);
2800 preload_ring_buffers(&si_shader_ctx);
2801
2802 if (si_shader_ctx.type == TGSI_PROCESSOR_GEOMETRY) {
2803 si_shader_ctx.gs_next_vertex =
2804 lp_build_alloca(bld_base->base.gallivm,
2805 bld_base->uint_bld.elem_type, "");
2806 }
2807
2808 if (!lp_build_tgsi_llvm(bld_base, sel->tokens)) {
2809 fprintf(stderr, "Failed to translate shader from TGSI to LLVM\n");
2810 goto out;
2811 }
2812
2813 radeon_llvm_finalize_module(&si_shader_ctx.radeon_bld);
2814
2815 mod = bld_base->base.gallivm->module;
2816 r = si_compile_llvm(sscreen, shader, mod);
2817 if (r) {
2818 fprintf(stderr, "LLVM failed to compile shader\n");
2819 goto out;
2820 }
2821
2822 radeon_llvm_dispose(&si_shader_ctx.radeon_bld);
2823
2824 if (si_shader_ctx.type == TGSI_PROCESSOR_GEOMETRY) {
2825 shader->gs_copy_shader = CALLOC_STRUCT(si_shader);
2826 shader->gs_copy_shader->selector = shader->selector;
2827 shader->gs_copy_shader->key = shader->key;
2828 si_shader_ctx.shader = shader->gs_copy_shader;
2829 if ((r = si_generate_gs_copy_shader(sscreen, &si_shader_ctx,
2830 shader, dump))) {
2831 free(shader->gs_copy_shader);
2832 shader->gs_copy_shader = NULL;
2833 goto out;
2834 }
2835 }
2836
2837 tgsi_parse_free(&si_shader_ctx.parse);
2838
2839 out:
2840 for (int i = 0; i < SI_NUM_CONST_BUFFERS; i++)
2841 FREE(si_shader_ctx.constants[i]);
2842
2843 return r;
2844 }
2845
2846 void si_shader_destroy(struct pipe_context *ctx, struct si_shader *shader)
2847 {
2848 if (shader->gs_copy_shader)
2849 si_shader_destroy(ctx, shader->gs_copy_shader);
2850
2851 r600_resource_reference(&shader->bo, NULL);
2852 r600_resource_reference(&shader->scratch_bo, NULL);
2853 }