projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
radeonsi: add nir support for gs epilogue
[mesa.git] / src / gallium / drivers / radeonsi / si_shader.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23
24 #include "gallivm/lp_bld_const.h"
25 #include "gallivm/lp_bld_gather.h"
26 #include "gallivm/lp_bld_intr.h"
27 #include "gallivm/lp_bld_logic.h"
28 #include "gallivm/lp_bld_arit.h"
29 #include "gallivm/lp_bld_flow.h"
30 #include "gallivm/lp_bld_misc.h"
31 #include "util/u_memory.h"
32 #include "util/u_string.h"
33 #include "tgsi/tgsi_build.h"
34 #include "tgsi/tgsi_util.h"
35 #include "tgsi/tgsi_dump.h"
36
37 #include "ac_binary.h"
38 #include "ac_llvm_util.h"
39 #include "ac_exp_param.h"
40 #include "si_shader_internal.h"
41 #include "si_pipe.h"
42 #include "sid.h"
43
44 #include "compiler/nir/nir.h"
45
46 static const char *scratch_rsrc_dword0_symbol =
47 "SCRATCH_RSRC_DWORD0";
48
49 static const char *scratch_rsrc_dword1_symbol =
50 "SCRATCH_RSRC_DWORD1";
51
52 struct si_shader_output_values
53 {
54 LLVMValueRef values[4];
55 unsigned semantic_name;
56 unsigned semantic_index;
57 ubyte vertex_stream[4];
58 };
59
60 /**
61 * Used to collect types and other info about arguments of the LLVM function
62 * before the function is created.
63 */
64 struct si_function_info {
65 LLVMTypeRef types[100];
66 LLVMValueRef *assign[100];
67 unsigned num_sgpr_params;
68 unsigned num_params;
69 };
70
71 enum si_arg_regfile {
72 ARG_SGPR,
73 ARG_VGPR
74 };
75
76 static void si_init_shader_ctx(struct si_shader_context *ctx,
77 struct si_screen *sscreen,
78 LLVMTargetMachineRef tm);
79
80 static void si_llvm_emit_barrier(const struct lp_build_tgsi_action *action,
81 struct lp_build_tgsi_context *bld_base,
82 struct lp_build_emit_data *emit_data);
83
84 static void si_dump_shader_key(unsigned processor, const struct si_shader *shader,
85 FILE *f);
86
87 static void si_build_vs_prolog_function(struct si_shader_context *ctx,
88 union si_shader_part_key *key);
89 static void si_build_tcs_epilog_function(struct si_shader_context *ctx,
90 union si_shader_part_key *key);
91 static void si_build_ps_prolog_function(struct si_shader_context *ctx,
92 union si_shader_part_key *key);
93 static void si_build_ps_epilog_function(struct si_shader_context *ctx,
94 union si_shader_part_key *key);
95
96 /* Ideally pass the sample mask input to the PS epilog as v14, which
97 * is its usual location, so that the shader doesn't have to add v_mov.
98 */
99 #define PS_EPILOG_SAMPLEMASK_MIN_LOC 14
100
101 enum {
102 CONST_ADDR_SPACE = 2,
103 LOCAL_ADDR_SPACE = 3,
104 };
105
106 static bool is_merged_shader(struct si_shader *shader)
107 {
108 if (shader->selector->screen->info.chip_class <= VI)
109 return false;
110
111 return shader->key.as_ls ||
112 shader->key.as_es ||
113 shader->selector->type == PIPE_SHADER_TESS_CTRL ||
114 shader->selector->type == PIPE_SHADER_GEOMETRY;
115 }
116
117 static void si_init_function_info(struct si_function_info *fninfo)
118 {
119 fninfo->num_params = 0;
120 fninfo->num_sgpr_params = 0;
121 }
122
123 static unsigned add_arg_assign(struct si_function_info *fninfo,
124 enum si_arg_regfile regfile, LLVMTypeRef type,
125 LLVMValueRef *assign)
126 {
127 assert(regfile != ARG_SGPR || fninfo->num_sgpr_params == fninfo->num_params);
128
129 unsigned idx = fninfo->num_params++;
130 assert(idx < ARRAY_SIZE(fninfo->types));
131
132 if (regfile == ARG_SGPR)
133 fninfo->num_sgpr_params = fninfo->num_params;
134
135 fninfo->types[idx] = type;
136 fninfo->assign[idx] = assign;
137 return idx;
138 }
139
140 static unsigned add_arg(struct si_function_info *fninfo,
141 enum si_arg_regfile regfile, LLVMTypeRef type)
142 {
143 return add_arg_assign(fninfo, regfile, type, NULL);
144 }
145
146 static void add_arg_assign_checked(struct si_function_info *fninfo,
147 enum si_arg_regfile regfile, LLVMTypeRef type,
148 LLVMValueRef *assign, unsigned idx)
149 {
150 MAYBE_UNUSED unsigned actual = add_arg_assign(fninfo, regfile, type, assign);
151 assert(actual == idx);
152 }
153
154 static void add_arg_checked(struct si_function_info *fninfo,
155 enum si_arg_regfile regfile, LLVMTypeRef type,
156 unsigned idx)
157 {
158 add_arg_assign_checked(fninfo, regfile, type, NULL, idx);
159 }
160
161 /**
162 * Returns a unique index for a per-patch semantic name and index. The index
163 * must be less than 32, so that a 32-bit bitmask of used inputs or outputs
164 * can be calculated.
165 */
166 unsigned si_shader_io_get_unique_index_patch(unsigned semantic_name, unsigned index)
167 {
168 switch (semantic_name) {
169 case TGSI_SEMANTIC_TESSOUTER:
170 return 0;
171 case TGSI_SEMANTIC_TESSINNER:
172 return 1;
173 case TGSI_SEMANTIC_PATCH:
174 assert(index < 30);
175 return 2 + index;
176
177 default:
178 assert(!"invalid semantic name");
179 return 0;
180 }
181 }
182
183 /**
184 * Returns a unique index for a semantic name and index. The index must be
185 * less than 64, so that a 64-bit bitmask of used inputs or outputs can be
186 * calculated.
187 */
188 unsigned si_shader_io_get_unique_index(unsigned semantic_name, unsigned index)
189 {
190 switch (semantic_name) {
191 case TGSI_SEMANTIC_POSITION:
192 return 0;
193 case TGSI_SEMANTIC_GENERIC:
194 /* Since some shader stages use the the highest used IO index
195 * to determine the size to allocate for inputs/outputs
196 * (in LDS, tess and GS rings). GENERIC should be placed right
197 * after POSITION to make that size as small as possible.
198 */
199 if (index < SI_MAX_IO_GENERIC)
200 return 1 + index;
201
202 assert(!"invalid generic index");
203 return 0;
204 case TGSI_SEMANTIC_PSIZE:
205 return SI_MAX_IO_GENERIC + 1;
206 case TGSI_SEMANTIC_CLIPDIST:
207 assert(index <= 1);
208 return SI_MAX_IO_GENERIC + 2 + index;
209 case TGSI_SEMANTIC_FOG:
210 return SI_MAX_IO_GENERIC + 4;
211 case TGSI_SEMANTIC_LAYER:
212 return SI_MAX_IO_GENERIC + 5;
213 case TGSI_SEMANTIC_VIEWPORT_INDEX:
214 return SI_MAX_IO_GENERIC + 6;
215 case TGSI_SEMANTIC_PRIMID:
216 return SI_MAX_IO_GENERIC + 7;
217 case TGSI_SEMANTIC_COLOR: /* these alias */
218 case TGSI_SEMANTIC_BCOLOR:
219 assert(index < 2);
220 return SI_MAX_IO_GENERIC + 8 + index;
221 case TGSI_SEMANTIC_TEXCOORD:
222 assert(index < 8);
223 assert(SI_MAX_IO_GENERIC + 10 + index < 64);
224 return SI_MAX_IO_GENERIC + 10 + index;
225 default:
226 assert(!"invalid semantic name");
227 return 0;
228 }
229 }
230
231 /**
232 * Get the value of a shader input parameter and extract a bitfield.
233 */
234 static LLVMValueRef unpack_param(struct si_shader_context *ctx,
235 unsigned param, unsigned rshift,
236 unsigned bitwidth)
237 {
238 LLVMValueRef value = LLVMGetParam(ctx->main_fn,
239 param);
240
241 if (LLVMGetTypeKind(LLVMTypeOf(value)) == LLVMFloatTypeKind)
242 value = ac_to_integer(&ctx->ac, value);
243
244 if (rshift)
245 value = LLVMBuildLShr(ctx->ac.builder, value,
246 LLVMConstInt(ctx->i32, rshift, 0), "");
247
248 if (rshift + bitwidth < 32) {
249 unsigned mask = (1 << bitwidth) - 1;
250 value = LLVMBuildAnd(ctx->ac.builder, value,
251 LLVMConstInt(ctx->i32, mask, 0), "");
252 }
253
254 return value;
255 }
256
257 static LLVMValueRef get_rel_patch_id(struct si_shader_context *ctx)
258 {
259 switch (ctx->type) {
260 case PIPE_SHADER_TESS_CTRL:
261 return unpack_param(ctx, ctx->param_tcs_rel_ids, 0, 8);
262
263 case PIPE_SHADER_TESS_EVAL:
264 return LLVMGetParam(ctx->main_fn,
265 ctx->param_tes_rel_patch_id);
266
267 default:
268 assert(0);
269 return NULL;
270 }
271 }
272
273 /* Tessellation shaders pass outputs to the next shader using LDS.
274 *
275 * LS outputs = TCS inputs
276 * TCS outputs = TES inputs
277 *
278 * The LDS layout is:
279 * - TCS inputs for patch 0
280 * - TCS inputs for patch 1
281 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
282 * - ...
283 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
284 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
285 * - TCS outputs for patch 1
286 * - Per-patch TCS outputs for patch 1
287 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
288 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
289 * - ...
290 *
291 * All three shaders VS(LS), TCS, TES share the same LDS space.
292 */
293
294 static LLVMValueRef
295 get_tcs_in_patch_stride(struct si_shader_context *ctx)
296 {
297 return unpack_param(ctx, ctx->param_vs_state_bits, 8, 13);
298 }
299
300 static unsigned get_tcs_out_vertex_dw_stride_constant(struct si_shader_context *ctx)
301 {
302 assert(ctx->type == PIPE_SHADER_TESS_CTRL);
303
304 if (ctx->shader->key.mono.u.ff_tcs_inputs_to_copy)
305 return util_last_bit64(ctx->shader->key.mono.u.ff_tcs_inputs_to_copy) * 4;
306
307 return util_last_bit64(ctx->shader->selector->outputs_written) * 4;
308 }
309
310 static LLVMValueRef get_tcs_out_vertex_dw_stride(struct si_shader_context *ctx)
311 {
312 unsigned stride = get_tcs_out_vertex_dw_stride_constant(ctx);
313
314 return LLVMConstInt(ctx->i32, stride, 0);
315 }
316
317 static LLVMValueRef get_tcs_out_patch_stride(struct si_shader_context *ctx)
318 {
319 if (ctx->shader->key.mono.u.ff_tcs_inputs_to_copy)
320 return unpack_param(ctx, ctx->param_tcs_out_lds_layout, 0, 13);
321
322 const struct tgsi_shader_info *info = &ctx->shader->selector->info;
323 unsigned tcs_out_vertices = info->properties[TGSI_PROPERTY_TCS_VERTICES_OUT];
324 unsigned vertex_dw_stride = get_tcs_out_vertex_dw_stride_constant(ctx);
325 unsigned num_patch_outputs = util_last_bit64(ctx->shader->selector->patch_outputs_written);
326 unsigned patch_dw_stride = tcs_out_vertices * vertex_dw_stride +
327 num_patch_outputs * 4;
328 return LLVMConstInt(ctx->i32, patch_dw_stride, 0);
329 }
330
331 static LLVMValueRef
332 get_tcs_out_patch0_offset(struct si_shader_context *ctx)
333 {
334 return lp_build_mul_imm(&ctx->bld_base.uint_bld,
335 unpack_param(ctx,
336 ctx->param_tcs_out_lds_offsets,
337 0, 16),
338 4);
339 }
340
341 static LLVMValueRef
342 get_tcs_out_patch0_patch_data_offset(struct si_shader_context *ctx)
343 {
344 return lp_build_mul_imm(&ctx->bld_base.uint_bld,
345 unpack_param(ctx,
346 ctx->param_tcs_out_lds_offsets,
347 16, 16),
348 4);
349 }
350
351 static LLVMValueRef
352 get_tcs_in_current_patch_offset(struct si_shader_context *ctx)
353 {
354 LLVMValueRef patch_stride = get_tcs_in_patch_stride(ctx);
355 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
356
357 return LLVMBuildMul(ctx->ac.builder, patch_stride, rel_patch_id, "");
358 }
359
360 static LLVMValueRef
361 get_tcs_out_current_patch_offset(struct si_shader_context *ctx)
362 {
363 LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(ctx);
364 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
365 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
366
367 return LLVMBuildAdd(ctx->ac.builder, patch0_offset,
368 LLVMBuildMul(ctx->ac.builder, patch_stride,
369 rel_patch_id, ""),
370 "");
371 }
372
373 static LLVMValueRef
374 get_tcs_out_current_patch_data_offset(struct si_shader_context *ctx)
375 {
376 LLVMValueRef patch0_patch_data_offset =
377 get_tcs_out_patch0_patch_data_offset(ctx);
378 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
379 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
380
381 return LLVMBuildAdd(ctx->ac.builder, patch0_patch_data_offset,
382 LLVMBuildMul(ctx->ac.builder, patch_stride,
383 rel_patch_id, ""),
384 "");
385 }
386
387 static LLVMValueRef get_num_tcs_out_vertices(struct si_shader_context *ctx)
388 {
389 unsigned tcs_out_vertices =
390 ctx->shader->selector ?
391 ctx->shader->selector->info.properties[TGSI_PROPERTY_TCS_VERTICES_OUT] : 0;
392
393 /* If !tcs_out_vertices, it's either the fixed-func TCS or the TCS epilog. */
394 if (ctx->type == PIPE_SHADER_TESS_CTRL && tcs_out_vertices)
395 return LLVMConstInt(ctx->i32, tcs_out_vertices, 0);
396
397 return unpack_param(ctx, ctx->param_tcs_offchip_layout, 6, 6);
398 }
399
400 static LLVMValueRef get_tcs_in_vertex_dw_stride(struct si_shader_context *ctx)
401 {
402 unsigned stride;
403
404 switch (ctx->type) {
405 case PIPE_SHADER_VERTEX:
406 stride = util_last_bit64(ctx->shader->selector->outputs_written);
407 return LLVMConstInt(ctx->i32, stride * 4, 0);
408
409 case PIPE_SHADER_TESS_CTRL:
410 if (ctx->screen->info.chip_class >= GFX9 &&
411 ctx->shader->is_monolithic) {
412 stride = util_last_bit64(ctx->shader->key.part.tcs.ls->outputs_written);
413 return LLVMConstInt(ctx->i32, stride * 4, 0);
414 }
415 return unpack_param(ctx, ctx->param_vs_state_bits, 24, 8);
416
417 default:
418 assert(0);
419 return NULL;
420 }
421 }
422
423 static LLVMValueRef get_instance_index_for_fetch(
424 struct si_shader_context *ctx,
425 unsigned param_start_instance, LLVMValueRef divisor)
426 {
427 LLVMValueRef result = ctx->abi.instance_id;
428
429 /* The division must be done before START_INSTANCE is added. */
430 if (divisor != ctx->i32_1)
431 result = LLVMBuildUDiv(ctx->ac.builder, result, divisor, "");
432
433 return LLVMBuildAdd(ctx->ac.builder, result,
434 LLVMGetParam(ctx->main_fn, param_start_instance), "");
435 }
436
437 /* Bitcast <4 x float> to <2 x double>, extract the component, and convert
438 * to float. */
439 static LLVMValueRef extract_double_to_float(struct si_shader_context *ctx,
440 LLVMValueRef vec4,
441 unsigned double_index)
442 {
443 LLVMBuilderRef builder = ctx->ac.builder;
444 LLVMTypeRef f64 = LLVMDoubleTypeInContext(ctx->ac.context);
445 LLVMValueRef dvec2 = LLVMBuildBitCast(builder, vec4,
446 LLVMVectorType(f64, 2), "");
447 LLVMValueRef index = LLVMConstInt(ctx->i32, double_index, 0);
448 LLVMValueRef value = LLVMBuildExtractElement(builder, dvec2, index, "");
449 return LLVMBuildFPTrunc(builder, value, ctx->f32, "");
450 }
451
452 static LLVMValueRef unpack_sint16(struct si_shader_context *ctx,
453 LLVMValueRef i32, unsigned index)
454 {
455 assert(index <= 1);
456
457 if (index == 1)
458 return LLVMBuildAShr(ctx->ac.builder, i32,
459 LLVMConstInt(ctx->i32, 16, 0), "");
460
461 return LLVMBuildSExt(ctx->ac.builder,
462 LLVMBuildTrunc(ctx->ac.builder, i32,
463 ctx->ac.i16, ""),
464 ctx->i32, "");
465 }
466
467 void si_llvm_load_input_vs(
468 struct si_shader_context *ctx,
469 unsigned input_index,
470 LLVMValueRef out[4])
471 {
472 unsigned vs_blit_property =
473 ctx->shader->selector->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS];
474
475 if (vs_blit_property) {
476 LLVMValueRef vertex_id = ctx->abi.vertex_id;
477 LLVMValueRef sel_x1 = LLVMBuildICmp(ctx->ac.builder,
478 LLVMIntULE, vertex_id,
479 ctx->i32_1, "");
480 /* Use LLVMIntNE, because we have 3 vertices and only
481 * the middle one should use y2.
482 */
483 LLVMValueRef sel_y1 = LLVMBuildICmp(ctx->ac.builder,
484 LLVMIntNE, vertex_id,
485 ctx->i32_1, "");
486
487 if (input_index == 0) {
488 /* Position: */
489 LLVMValueRef x1y1 = LLVMGetParam(ctx->main_fn,
490 ctx->param_vs_blit_inputs);
491 LLVMValueRef x2y2 = LLVMGetParam(ctx->main_fn,
492 ctx->param_vs_blit_inputs + 1);
493
494 LLVMValueRef x1 = unpack_sint16(ctx, x1y1, 0);
495 LLVMValueRef y1 = unpack_sint16(ctx, x1y1, 1);
496 LLVMValueRef x2 = unpack_sint16(ctx, x2y2, 0);
497 LLVMValueRef y2 = unpack_sint16(ctx, x2y2, 1);
498
499 LLVMValueRef x = LLVMBuildSelect(ctx->ac.builder, sel_x1,
500 x1, x2, "");
501 LLVMValueRef y = LLVMBuildSelect(ctx->ac.builder, sel_y1,
502 y1, y2, "");
503
504 out[0] = LLVMBuildSIToFP(ctx->ac.builder, x, ctx->f32, "");
505 out[1] = LLVMBuildSIToFP(ctx->ac.builder, y, ctx->f32, "");
506 out[2] = LLVMGetParam(ctx->main_fn,
507 ctx->param_vs_blit_inputs + 2);
508 out[3] = ctx->ac.f32_1;
509 return;
510 }
511
512 /* Color or texture coordinates: */
513 assert(input_index == 1);
514
515 if (vs_blit_property == SI_VS_BLIT_SGPRS_POS_COLOR) {
516 for (int i = 0; i < 4; i++) {
517 out[i] = LLVMGetParam(ctx->main_fn,
518 ctx->param_vs_blit_inputs + 3 + i);
519 }
520 } else {
521 assert(vs_blit_property == SI_VS_BLIT_SGPRS_POS_TEXCOORD);
522 LLVMValueRef x1 = LLVMGetParam(ctx->main_fn,
523 ctx->param_vs_blit_inputs + 3);
524 LLVMValueRef y1 = LLVMGetParam(ctx->main_fn,
525 ctx->param_vs_blit_inputs + 4);
526 LLVMValueRef x2 = LLVMGetParam(ctx->main_fn,
527 ctx->param_vs_blit_inputs + 5);
528 LLVMValueRef y2 = LLVMGetParam(ctx->main_fn,
529 ctx->param_vs_blit_inputs + 6);
530
531 out[0] = LLVMBuildSelect(ctx->ac.builder, sel_x1,
532 x1, x2, "");
533 out[1] = LLVMBuildSelect(ctx->ac.builder, sel_y1,
534 y1, y2, "");
535 out[2] = LLVMGetParam(ctx->main_fn,
536 ctx->param_vs_blit_inputs + 7);
537 out[3] = LLVMGetParam(ctx->main_fn,
538 ctx->param_vs_blit_inputs + 8);
539 }
540 return;
541 }
542
543 unsigned chan;
544 unsigned fix_fetch;
545 unsigned num_fetches;
546 unsigned fetch_stride;
547
548 LLVMValueRef t_list_ptr;
549 LLVMValueRef t_offset;
550 LLVMValueRef t_list;
551 LLVMValueRef vertex_index;
552 LLVMValueRef input[3];
553
554 /* Load the T list */
555 t_list_ptr = LLVMGetParam(ctx->main_fn, ctx->param_vertex_buffers);
556
557 t_offset = LLVMConstInt(ctx->i32, input_index, 0);
558
559 t_list = ac_build_load_to_sgpr(&ctx->ac, t_list_ptr, t_offset);
560
561 vertex_index = LLVMGetParam(ctx->main_fn,
562 ctx->param_vertex_index0 +
563 input_index);
564
565 fix_fetch = ctx->shader->key.mono.vs_fix_fetch[input_index];
566
567 /* Do multiple loads for special formats. */
568 switch (fix_fetch) {
569 case SI_FIX_FETCH_RGB_64_FLOAT:
570 num_fetches = 3; /* 3 2-dword loads */
571 fetch_stride = 8;
572 break;
573 case SI_FIX_FETCH_RGBA_64_FLOAT:
574 num_fetches = 2; /* 2 4-dword loads */
575 fetch_stride = 16;
576 break;
577 case SI_FIX_FETCH_RGB_8:
578 case SI_FIX_FETCH_RGB_8_INT:
579 num_fetches = 3;
580 fetch_stride = 1;
581 break;
582 case SI_FIX_FETCH_RGB_16:
583 case SI_FIX_FETCH_RGB_16_INT:
584 num_fetches = 3;
585 fetch_stride = 2;
586 break;
587 default:
588 num_fetches = 1;
589 fetch_stride = 0;
590 }
591
592 for (unsigned i = 0; i < num_fetches; i++) {
593 LLVMValueRef voffset = LLVMConstInt(ctx->i32, fetch_stride * i, 0);
594
595 input[i] = ac_build_buffer_load_format(&ctx->ac, t_list,
596 vertex_index, voffset,
597 true);
598 }
599
600 /* Break up the vec4 into individual components */
601 for (chan = 0; chan < 4; chan++) {
602 LLVMValueRef llvm_chan = LLVMConstInt(ctx->i32, chan, 0);
603 out[chan] = LLVMBuildExtractElement(ctx->ac.builder,
604 input[0], llvm_chan, "");
605 }
606
607 switch (fix_fetch) {
608 case SI_FIX_FETCH_A2_SNORM:
609 case SI_FIX_FETCH_A2_SSCALED:
610 case SI_FIX_FETCH_A2_SINT: {
611 /* The hardware returns an unsigned value; convert it to a
612 * signed one.
613 */
614 LLVMValueRef tmp = out[3];
615 LLVMValueRef c30 = LLVMConstInt(ctx->i32, 30, 0);
616
617 /* First, recover the sign-extended signed integer value. */
618 if (fix_fetch == SI_FIX_FETCH_A2_SSCALED)
619 tmp = LLVMBuildFPToUI(ctx->ac.builder, tmp, ctx->i32, "");
620 else
621 tmp = ac_to_integer(&ctx->ac, tmp);
622
623 /* For the integer-like cases, do a natural sign extension.
624 *
625 * For the SNORM case, the values are 0.0, 0.333, 0.666, 1.0
626 * and happen to contain 0, 1, 2, 3 as the two LSBs of the
627 * exponent.
628 */
629 tmp = LLVMBuildShl(ctx->ac.builder, tmp,
630 fix_fetch == SI_FIX_FETCH_A2_SNORM ?
631 LLVMConstInt(ctx->i32, 7, 0) : c30, "");
632 tmp = LLVMBuildAShr(ctx->ac.builder, tmp, c30, "");
633
634 /* Convert back to the right type. */
635 if (fix_fetch == SI_FIX_FETCH_A2_SNORM) {
636 LLVMValueRef clamp;
637 LLVMValueRef neg_one = LLVMConstReal(ctx->f32, -1.0);
638 tmp = LLVMBuildSIToFP(ctx->ac.builder, tmp, ctx->f32, "");
639 clamp = LLVMBuildFCmp(ctx->ac.builder, LLVMRealULT, tmp, neg_one, "");
640 tmp = LLVMBuildSelect(ctx->ac.builder, clamp, neg_one, tmp, "");
641 } else if (fix_fetch == SI_FIX_FETCH_A2_SSCALED) {
642 tmp = LLVMBuildSIToFP(ctx->ac.builder, tmp, ctx->f32, "");
643 }
644
645 out[3] = tmp;
646 break;
647 }
648 case SI_FIX_FETCH_RGBA_32_UNORM:
649 case SI_FIX_FETCH_RGBX_32_UNORM:
650 for (chan = 0; chan < 4; chan++) {
651 out[chan] = ac_to_integer(&ctx->ac, out[chan]);
652 out[chan] = LLVMBuildUIToFP(ctx->ac.builder,
653 out[chan], ctx->f32, "");
654 out[chan] = LLVMBuildFMul(ctx->ac.builder, out[chan],
655 LLVMConstReal(ctx->f32, 1.0 / UINT_MAX), "");
656 }
657 /* RGBX UINT returns 1 in alpha, which would be rounded to 0 by normalizing. */
658 if (fix_fetch == SI_FIX_FETCH_RGBX_32_UNORM)
659 out[3] = LLVMConstReal(ctx->f32, 1);
660 break;
661 case SI_FIX_FETCH_RGBA_32_SNORM:
662 case SI_FIX_FETCH_RGBX_32_SNORM:
663 case SI_FIX_FETCH_RGBA_32_FIXED:
664 case SI_FIX_FETCH_RGBX_32_FIXED: {
665 double scale;
666 if (fix_fetch >= SI_FIX_FETCH_RGBA_32_FIXED)
667 scale = 1.0 / 0x10000;
668 else
669 scale = 1.0 / INT_MAX;
670
671 for (chan = 0; chan < 4; chan++) {
672 out[chan] = ac_to_integer(&ctx->ac, out[chan]);
673 out[chan] = LLVMBuildSIToFP(ctx->ac.builder,
674 out[chan], ctx->f32, "");
675 out[chan] = LLVMBuildFMul(ctx->ac.builder, out[chan],
676 LLVMConstReal(ctx->f32, scale), "");
677 }
678 /* RGBX SINT returns 1 in alpha, which would be rounded to 0 by normalizing. */
679 if (fix_fetch == SI_FIX_FETCH_RGBX_32_SNORM ||
680 fix_fetch == SI_FIX_FETCH_RGBX_32_FIXED)
681 out[3] = LLVMConstReal(ctx->f32, 1);
682 break;
683 }
684 case SI_FIX_FETCH_RGBA_32_USCALED:
685 for (chan = 0; chan < 4; chan++) {
686 out[chan] = ac_to_integer(&ctx->ac, out[chan]);
687 out[chan] = LLVMBuildUIToFP(ctx->ac.builder,
688 out[chan], ctx->f32, "");
689 }
690 break;
691 case SI_FIX_FETCH_RGBA_32_SSCALED:
692 for (chan = 0; chan < 4; chan++) {
693 out[chan] = ac_to_integer(&ctx->ac, out[chan]);
694 out[chan] = LLVMBuildSIToFP(ctx->ac.builder,
695 out[chan], ctx->f32, "");
696 }
697 break;
698 case SI_FIX_FETCH_RG_64_FLOAT:
699 for (chan = 0; chan < 2; chan++)
700 out[chan] = extract_double_to_float(ctx, input[0], chan);
701
702 out[2] = LLVMConstReal(ctx->f32, 0);
703 out[3] = LLVMConstReal(ctx->f32, 1);
704 break;
705 case SI_FIX_FETCH_RGB_64_FLOAT:
706 for (chan = 0; chan < 3; chan++)
707 out[chan] = extract_double_to_float(ctx, input[chan], 0);
708
709 out[3] = LLVMConstReal(ctx->f32, 1);
710 break;
711 case SI_FIX_FETCH_RGBA_64_FLOAT:
712 for (chan = 0; chan < 4; chan++) {
713 out[chan] = extract_double_to_float(ctx, input[chan / 2],
714 chan % 2);
715 }
716 break;
717 case SI_FIX_FETCH_RGB_8:
718 case SI_FIX_FETCH_RGB_8_INT:
719 case SI_FIX_FETCH_RGB_16:
720 case SI_FIX_FETCH_RGB_16_INT:
721 for (chan = 0; chan < 3; chan++) {
722 out[chan] = LLVMBuildExtractElement(ctx->ac.builder,
723 input[chan],
724 ctx->i32_0, "");
725 }
726 if (fix_fetch == SI_FIX_FETCH_RGB_8 ||
727 fix_fetch == SI_FIX_FETCH_RGB_16) {
728 out[3] = LLVMConstReal(ctx->f32, 1);
729 } else {
730 out[3] = ac_to_float(&ctx->ac, ctx->i32_1);
731 }
732 break;
733 }
734 }
735
736 static void declare_input_vs(
737 struct si_shader_context *ctx,
738 unsigned input_index,
739 const struct tgsi_full_declaration *decl,
740 LLVMValueRef out[4])
741 {
742 si_llvm_load_input_vs(ctx, input_index, out);
743 }
744
745 static LLVMValueRef get_primitive_id(struct si_shader_context *ctx,
746 unsigned swizzle)
747 {
748 if (swizzle > 0)
749 return ctx->i32_0;
750
751 switch (ctx->type) {
752 case PIPE_SHADER_VERTEX:
753 return LLVMGetParam(ctx->main_fn,
754 ctx->param_vs_prim_id);
755 case PIPE_SHADER_TESS_CTRL:
756 return LLVMGetParam(ctx->main_fn,
757 ctx->param_tcs_patch_id);
758 case PIPE_SHADER_TESS_EVAL:
759 return LLVMGetParam(ctx->main_fn,
760 ctx->param_tes_patch_id);
761 case PIPE_SHADER_GEOMETRY:
762 return ctx->abi.gs_prim_id;
763 default:
764 assert(0);
765 return ctx->i32_0;
766 }
767 }
768
769 /**
770 * Return the value of tgsi_ind_register for indexing.
771 * This is the indirect index with the constant offset added to it.
772 */
773 LLVMValueRef si_get_indirect_index(struct si_shader_context *ctx,
774 const struct tgsi_ind_register *ind,
775 unsigned addr_mul,
776 int rel_index)
777 {
778 LLVMValueRef result;
779
780 if (ind->File == TGSI_FILE_ADDRESS) {
781 result = ctx->addrs[ind->Index][ind->Swizzle];
782 result = LLVMBuildLoad(ctx->ac.builder, result, "");
783 } else {
784 struct tgsi_full_src_register src = {};
785
786 src.Register.File = ind->File;
787 src.Register.Index = ind->Index;
788
789 /* Set the second index to 0 for constants. */
790 if (ind->File == TGSI_FILE_CONSTANT)
791 src.Register.Dimension = 1;
792
793 result = ctx->bld_base.emit_fetch_funcs[ind->File](&ctx->bld_base, &src,
794 TGSI_TYPE_SIGNED,
795 ind->Swizzle);
796 result = ac_to_integer(&ctx->ac, result);
797 }
798
799 if (addr_mul != 1)
800 result = LLVMBuildMul(ctx->ac.builder, result,
801 LLVMConstInt(ctx->i32, addr_mul, 0), "");
802 result = LLVMBuildAdd(ctx->ac.builder, result,
803 LLVMConstInt(ctx->i32, rel_index, 0), "");
804 return result;
805 }
806
807 /**
808 * Like si_get_indirect_index, but restricts the return value to a (possibly
809 * undefined) value inside [0..num).
810 */
811 LLVMValueRef si_get_bounded_indirect_index(struct si_shader_context *ctx,
812 const struct tgsi_ind_register *ind,
813 int rel_index, unsigned num)
814 {
815 LLVMValueRef result = si_get_indirect_index(ctx, ind, 1, rel_index);
816
817 return si_llvm_bound_index(ctx, result, num);
818 }
819
820
821 /**
822 * Calculate a dword address given an input or output register and a stride.
823 */
824 static LLVMValueRef get_dw_address(struct si_shader_context *ctx,
825 const struct tgsi_full_dst_register *dst,
826 const struct tgsi_full_src_register *src,
827 LLVMValueRef vertex_dw_stride,
828 LLVMValueRef base_addr)
829 {
830 struct tgsi_shader_info *info = &ctx->shader->selector->info;
831 ubyte *name, *index, *array_first;
832 int first, param;
833 struct tgsi_full_dst_register reg;
834
835 /* Set the register description. The address computation is the same
836 * for sources and destinations. */
837 if (src) {
838 reg.Register.File = src->Register.File;
839 reg.Register.Index = src->Register.Index;
840 reg.Register.Indirect = src->Register.Indirect;
841 reg.Register.Dimension = src->Register.Dimension;
842 reg.Indirect = src->Indirect;
843 reg.Dimension = src->Dimension;
844 reg.DimIndirect = src->DimIndirect;
845 } else
846 reg = *dst;
847
848 /* If the register is 2-dimensional (e.g. an array of vertices
849 * in a primitive), calculate the base address of the vertex. */
850 if (reg.Register.Dimension) {
851 LLVMValueRef index;
852
853 if (reg.Dimension.Indirect)
854 index = si_get_indirect_index(ctx, &reg.DimIndirect,
855 1, reg.Dimension.Index);
856 else
857 index = LLVMConstInt(ctx->i32, reg.Dimension.Index, 0);
858
859 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
860 LLVMBuildMul(ctx->ac.builder, index,
861 vertex_dw_stride, ""), "");
862 }
863
864 /* Get information about the register. */
865 if (reg.Register.File == TGSI_FILE_INPUT) {
866 name = info->input_semantic_name;
867 index = info->input_semantic_index;
868 array_first = info->input_array_first;
869 } else if (reg.Register.File == TGSI_FILE_OUTPUT) {
870 name = info->output_semantic_name;
871 index = info->output_semantic_index;
872 array_first = info->output_array_first;
873 } else {
874 assert(0);
875 return NULL;
876 }
877
878 if (reg.Register.Indirect) {
879 /* Add the relative address of the element. */
880 LLVMValueRef ind_index;
881
882 if (reg.Indirect.ArrayID)
883 first = array_first[reg.Indirect.ArrayID];
884 else
885 first = reg.Register.Index;
886
887 ind_index = si_get_indirect_index(ctx, &reg.Indirect,
888 1, reg.Register.Index - first);
889
890 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
891 LLVMBuildMul(ctx->ac.builder, ind_index,
892 LLVMConstInt(ctx->i32, 4, 0), ""), "");
893
894 param = reg.Register.Dimension ?
895 si_shader_io_get_unique_index(name[first], index[first]) :
896 si_shader_io_get_unique_index_patch(name[first], index[first]);
897 } else {
898 param = reg.Register.Dimension ?
899 si_shader_io_get_unique_index(name[reg.Register.Index],
900 index[reg.Register.Index]) :
901 si_shader_io_get_unique_index_patch(name[reg.Register.Index],
902 index[reg.Register.Index]);
903 }
904
905 /* Add the base address of the element. */
906 return LLVMBuildAdd(ctx->ac.builder, base_addr,
907 LLVMConstInt(ctx->i32, param * 4, 0), "");
908 }
909
910 /* The offchip buffer layout for TCS->TES is
911 *
912 * - attribute 0 of patch 0 vertex 0
913 * - attribute 0 of patch 0 vertex 1
914 * - attribute 0 of patch 0 vertex 2
915 * ...
916 * - attribute 0 of patch 1 vertex 0
917 * - attribute 0 of patch 1 vertex 1
918 * ...
919 * - attribute 1 of patch 0 vertex 0
920 * - attribute 1 of patch 0 vertex 1
921 * ...
922 * - per patch attribute 0 of patch 0
923 * - per patch attribute 0 of patch 1
924 * ...
925 *
926 * Note that every attribute has 4 components.
927 */
928 static LLVMValueRef get_tcs_tes_buffer_address(struct si_shader_context *ctx,
929 LLVMValueRef rel_patch_id,
930 LLVMValueRef vertex_index,
931 LLVMValueRef param_index)
932 {
933 LLVMValueRef base_addr, vertices_per_patch, num_patches, total_vertices;
934 LLVMValueRef param_stride, constant16;
935
936 vertices_per_patch = get_num_tcs_out_vertices(ctx);
937 num_patches = unpack_param(ctx, ctx->param_tcs_offchip_layout, 0, 6);
938 total_vertices = LLVMBuildMul(ctx->ac.builder, vertices_per_patch,
939 num_patches, "");
940
941 constant16 = LLVMConstInt(ctx->i32, 16, 0);
942 if (vertex_index) {
943 base_addr = LLVMBuildMul(ctx->ac.builder, rel_patch_id,
944 vertices_per_patch, "");
945
946 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
947 vertex_index, "");
948
949 param_stride = total_vertices;
950 } else {
951 base_addr = rel_patch_id;
952 param_stride = num_patches;
953 }
954
955 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
956 LLVMBuildMul(ctx->ac.builder, param_index,
957 param_stride, ""), "");
958
959 base_addr = LLVMBuildMul(ctx->ac.builder, base_addr, constant16, "");
960
961 if (!vertex_index) {
962 LLVMValueRef patch_data_offset =
963 unpack_param(ctx, ctx->param_tcs_offchip_layout, 12, 20);
964
965 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
966 patch_data_offset, "");
967 }
968 return base_addr;
969 }
970
971 static LLVMValueRef get_tcs_tes_buffer_address_from_reg(
972 struct si_shader_context *ctx,
973 const struct tgsi_full_dst_register *dst,
974 const struct tgsi_full_src_register *src)
975 {
976 struct tgsi_shader_info *info = &ctx->shader->selector->info;
977 ubyte *name, *index, *array_first;
978 struct tgsi_full_src_register reg;
979 LLVMValueRef vertex_index = NULL;
980 LLVMValueRef param_index = NULL;
981 unsigned param_index_base, param_base;
982
983 reg = src ? *src : tgsi_full_src_register_from_dst(dst);
984
985 if (reg.Register.Dimension) {
986
987 if (reg.Dimension.Indirect)
988 vertex_index = si_get_indirect_index(ctx, &reg.DimIndirect,
989 1, reg.Dimension.Index);
990 else
991 vertex_index = LLVMConstInt(ctx->i32, reg.Dimension.Index, 0);
992 }
993
994 /* Get information about the register. */
995 if (reg.Register.File == TGSI_FILE_INPUT) {
996 name = info->input_semantic_name;
997 index = info->input_semantic_index;
998 array_first = info->input_array_first;
999 } else if (reg.Register.File == TGSI_FILE_OUTPUT) {
1000 name = info->output_semantic_name;
1001 index = info->output_semantic_index;
1002 array_first = info->output_array_first;
1003 } else {
1004 assert(0);
1005 return NULL;
1006 }
1007
1008 if (reg.Register.Indirect) {
1009 if (reg.Indirect.ArrayID)
1010 param_base = array_first[reg.Indirect.ArrayID];
1011 else
1012 param_base = reg.Register.Index;
1013
1014 param_index = si_get_indirect_index(ctx, &reg.Indirect,
1015 1, reg.Register.Index - param_base);
1016
1017 } else {
1018 param_base = reg.Register.Index;
1019 param_index = ctx->i32_0;
1020 }
1021
1022 param_index_base = reg.Register.Dimension ?
1023 si_shader_io_get_unique_index(name[param_base], index[param_base]) :
1024 si_shader_io_get_unique_index_patch(name[param_base], index[param_base]);
1025
1026 param_index = LLVMBuildAdd(ctx->ac.builder, param_index,
1027 LLVMConstInt(ctx->i32, param_index_base, 0),
1028 "");
1029
1030 return get_tcs_tes_buffer_address(ctx, get_rel_patch_id(ctx),
1031 vertex_index, param_index);
1032 }
1033
1034 static LLVMValueRef buffer_load(struct lp_build_tgsi_context *bld_base,
1035 enum tgsi_opcode_type type, unsigned swizzle,
1036 LLVMValueRef buffer, LLVMValueRef offset,
1037 LLVMValueRef base, bool can_speculate)
1038 {
1039 struct si_shader_context *ctx = si_shader_context(bld_base);
1040 LLVMValueRef value, value2;
1041 LLVMTypeRef llvm_type = tgsi2llvmtype(bld_base, type);
1042 LLVMTypeRef vec_type = LLVMVectorType(llvm_type, 4);
1043
1044 if (swizzle == ~0) {
1045 value = ac_build_buffer_load(&ctx->ac, buffer, 4, NULL, base, offset,
1046 0, 1, 0, can_speculate, false);
1047
1048 return LLVMBuildBitCast(ctx->ac.builder, value, vec_type, "");
1049 }
1050
1051 if (!tgsi_type_is_64bit(type)) {
1052 value = ac_build_buffer_load(&ctx->ac, buffer, 4, NULL, base, offset,
1053 0, 1, 0, can_speculate, false);
1054
1055 value = LLVMBuildBitCast(ctx->ac.builder, value, vec_type, "");
1056 return LLVMBuildExtractElement(ctx->ac.builder, value,
1057 LLVMConstInt(ctx->i32, swizzle, 0), "");
1058 }
1059
1060 value = ac_build_buffer_load(&ctx->ac, buffer, 1, NULL, base, offset,
1061 swizzle * 4, 1, 0, can_speculate, false);
1062
1063 value2 = ac_build_buffer_load(&ctx->ac, buffer, 1, NULL, base, offset,
1064 swizzle * 4 + 4, 1, 0, can_speculate, false);
1065
1066 return si_llvm_emit_fetch_64bit(bld_base, type, value, value2);
1067 }
1068
1069 /**
1070 * Load from LDS.
1071 *
1072 * \param type output value type
1073 * \param swizzle offset (typically 0..3); it can be ~0, which loads a vec4
1074 * \param dw_addr address in dwords
1075 */
1076 static LLVMValueRef lds_load(struct lp_build_tgsi_context *bld_base,
1077 enum tgsi_opcode_type type, unsigned swizzle,
1078 LLVMValueRef dw_addr)
1079 {
1080 struct si_shader_context *ctx = si_shader_context(bld_base);
1081 LLVMValueRef value;
1082
1083 if (swizzle == ~0) {
1084 LLVMValueRef values[TGSI_NUM_CHANNELS];
1085
1086 for (unsigned chan = 0; chan < TGSI_NUM_CHANNELS; chan++)
1087 values[chan] = lds_load(bld_base, type, chan, dw_addr);
1088
1089 return lp_build_gather_values(&ctx->gallivm, values,
1090 TGSI_NUM_CHANNELS);
1091 }
1092
1093 /* Split 64-bit loads. */
1094 if (tgsi_type_is_64bit(type)) {
1095 LLVMValueRef lo, hi;
1096
1097 lo = lds_load(bld_base, TGSI_TYPE_UNSIGNED, swizzle, dw_addr);
1098 hi = lds_load(bld_base, TGSI_TYPE_UNSIGNED, swizzle + 1, dw_addr);
1099 return si_llvm_emit_fetch_64bit(bld_base, type, lo, hi);
1100 }
1101
1102 dw_addr = lp_build_add(&bld_base->uint_bld, dw_addr,
1103 LLVMConstInt(ctx->i32, swizzle, 0));
1104
1105 value = ac_lds_load(&ctx->ac, dw_addr);
1106
1107 return bitcast(bld_base, type, value);
1108 }
1109
1110 /**
1111 * Store to LDS.
1112 *
1113 * \param swizzle offset (typically 0..3)
1114 * \param dw_addr address in dwords
1115 * \param value value to store
1116 */
1117 static void lds_store(struct si_shader_context *ctx,
1118 unsigned dw_offset_imm, LLVMValueRef dw_addr,
1119 LLVMValueRef value)
1120 {
1121 dw_addr = lp_build_add(&ctx->bld_base.uint_bld, dw_addr,
1122 LLVMConstInt(ctx->i32, dw_offset_imm, 0));
1123
1124 ac_lds_store(&ctx->ac, dw_addr, value);
1125 }
1126
1127 static LLVMValueRef desc_from_addr_base64k(struct si_shader_context *ctx,
1128 unsigned param)
1129 {
1130 LLVMBuilderRef builder = ctx->ac.builder;
1131
1132 LLVMValueRef addr = LLVMGetParam(ctx->main_fn, param);
1133 addr = LLVMBuildZExt(builder, addr, ctx->i64, "");
1134 addr = LLVMBuildShl(builder, addr, LLVMConstInt(ctx->i64, 16, 0), "");
1135
1136 uint64_t desc2 = 0xffffffff;
1137 uint64_t desc3 = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1138 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1139 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1140 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1141 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1142 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
1143 LLVMValueRef hi = LLVMConstInt(ctx->i64, desc2 | (desc3 << 32), 0);
1144
1145 LLVMValueRef desc = LLVMGetUndef(LLVMVectorType(ctx->i64, 2));
1146 desc = LLVMBuildInsertElement(builder, desc, addr, ctx->i32_0, "");
1147 desc = LLVMBuildInsertElement(builder, desc, hi, ctx->i32_1, "");
1148 return LLVMBuildBitCast(builder, desc, ctx->v4i32, "");
1149 }
1150
1151 static LLVMValueRef fetch_input_tcs(
1152 struct lp_build_tgsi_context *bld_base,
1153 const struct tgsi_full_src_register *reg,
1154 enum tgsi_opcode_type type, unsigned swizzle)
1155 {
1156 struct si_shader_context *ctx = si_shader_context(bld_base);
1157 LLVMValueRef dw_addr, stride;
1158
1159 stride = get_tcs_in_vertex_dw_stride(ctx);
1160 dw_addr = get_tcs_in_current_patch_offset(ctx);
1161 dw_addr = get_dw_address(ctx, NULL, reg, stride, dw_addr);
1162
1163 return lds_load(bld_base, type, swizzle, dw_addr);
1164 }
1165
1166 static LLVMValueRef fetch_output_tcs(
1167 struct lp_build_tgsi_context *bld_base,
1168 const struct tgsi_full_src_register *reg,
1169 enum tgsi_opcode_type type, unsigned swizzle)
1170 {
1171 struct si_shader_context *ctx = si_shader_context(bld_base);
1172 LLVMValueRef dw_addr, stride;
1173
1174 if (reg->Register.Dimension) {
1175 stride = get_tcs_out_vertex_dw_stride(ctx);
1176 dw_addr = get_tcs_out_current_patch_offset(ctx);
1177 dw_addr = get_dw_address(ctx, NULL, reg, stride, dw_addr);
1178 } else {
1179 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1180 dw_addr = get_dw_address(ctx, NULL, reg, NULL, dw_addr);
1181 }
1182
1183 return lds_load(bld_base, type, swizzle, dw_addr);
1184 }
1185
1186 static LLVMValueRef fetch_input_tes(
1187 struct lp_build_tgsi_context *bld_base,
1188 const struct tgsi_full_src_register *reg,
1189 enum tgsi_opcode_type type, unsigned swizzle)
1190 {
1191 struct si_shader_context *ctx = si_shader_context(bld_base);
1192 LLVMValueRef buffer, base, addr;
1193
1194 buffer = desc_from_addr_base64k(ctx, ctx->param_tcs_offchip_addr_base64k);
1195
1196 base = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
1197 addr = get_tcs_tes_buffer_address_from_reg(ctx, NULL, reg);
1198
1199 return buffer_load(bld_base, type, swizzle, buffer, base, addr, true);
1200 }
1201
1202 static void store_output_tcs(struct lp_build_tgsi_context *bld_base,
1203 const struct tgsi_full_instruction *inst,
1204 const struct tgsi_opcode_info *info,
1205 unsigned index,
1206 LLVMValueRef dst[4])
1207 {
1208 struct si_shader_context *ctx = si_shader_context(bld_base);
1209 const struct tgsi_full_dst_register *reg = &inst->Dst[index];
1210 const struct tgsi_shader_info *sh_info = &ctx->shader->selector->info;
1211 unsigned chan_index;
1212 LLVMValueRef dw_addr, stride;
1213 LLVMValueRef buffer, base, buf_addr;
1214 LLVMValueRef values[4];
1215 bool skip_lds_store;
1216 bool is_tess_factor = false, is_tess_inner = false;
1217
1218 /* Only handle per-patch and per-vertex outputs here.
1219 * Vectors will be lowered to scalars and this function will be called again.
1220 */
1221 if (reg->Register.File != TGSI_FILE_OUTPUT ||
1222 (dst[0] && LLVMGetTypeKind(LLVMTypeOf(dst[0])) == LLVMVectorTypeKind)) {
1223 si_llvm_emit_store(bld_base, inst, info, index, dst);
1224 return;
1225 }
1226
1227 if (reg->Register.Dimension) {
1228 stride = get_tcs_out_vertex_dw_stride(ctx);
1229 dw_addr = get_tcs_out_current_patch_offset(ctx);
1230 dw_addr = get_dw_address(ctx, reg, NULL, stride, dw_addr);
1231 skip_lds_store = !sh_info->reads_pervertex_outputs;
1232 } else {
1233 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1234 dw_addr = get_dw_address(ctx, reg, NULL, NULL, dw_addr);
1235 skip_lds_store = !sh_info->reads_perpatch_outputs;
1236
1237 if (!reg->Register.Indirect) {
1238 int name = sh_info->output_semantic_name[reg->Register.Index];
1239
1240 /* Always write tess factors into LDS for the TCS epilog. */
1241 if (name == TGSI_SEMANTIC_TESSINNER ||
1242 name == TGSI_SEMANTIC_TESSOUTER) {
1243 /* The epilog doesn't read LDS if invocation 0 defines tess factors. */
1244 skip_lds_store = !sh_info->reads_tessfactor_outputs &&
1245 ctx->shader->selector->tcs_info.tessfactors_are_def_in_all_invocs;
1246 is_tess_factor = true;
1247 is_tess_inner = name == TGSI_SEMANTIC_TESSINNER;
1248 }
1249 }
1250 }
1251
1252 buffer = desc_from_addr_base64k(ctx, ctx->param_tcs_offchip_addr_base64k);
1253
1254 base = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
1255 buf_addr = get_tcs_tes_buffer_address_from_reg(ctx, reg, NULL);
1256
1257 uint32_t writemask = reg->Register.WriteMask;
1258 while (writemask) {
1259 chan_index = u_bit_scan(&writemask);
1260 LLVMValueRef value = dst[chan_index];
1261
1262 if (inst->Instruction.Saturate)
1263 value = ac_build_clamp(&ctx->ac, value);
1264
1265 /* Skip LDS stores if there is no LDS read of this output. */
1266 if (!skip_lds_store)
1267 lds_store(ctx, chan_index, dw_addr, value);
1268
1269 value = ac_to_integer(&ctx->ac, value);
1270 values[chan_index] = value;
1271
1272 if (reg->Register.WriteMask != 0xF && !is_tess_factor) {
1273 ac_build_buffer_store_dword(&ctx->ac, buffer, value, 1,
1274 buf_addr, base,
1275 4 * chan_index, 1, 0, true, false);
1276 }
1277
1278 /* Write tess factors into VGPRs for the epilog. */
1279 if (is_tess_factor &&
1280 ctx->shader->selector->tcs_info.tessfactors_are_def_in_all_invocs) {
1281 if (!is_tess_inner) {
1282 LLVMBuildStore(ctx->ac.builder, value, /* outer */
1283 ctx->invoc0_tess_factors[chan_index]);
1284 } else if (chan_index < 2) {
1285 LLVMBuildStore(ctx->ac.builder, value, /* inner */
1286 ctx->invoc0_tess_factors[4 + chan_index]);
1287 }
1288 }
1289 }
1290
1291 if (reg->Register.WriteMask == 0xF && !is_tess_factor) {
1292 LLVMValueRef value = lp_build_gather_values(&ctx->gallivm,
1293 values, 4);
1294 ac_build_buffer_store_dword(&ctx->ac, buffer, value, 4, buf_addr,
1295 base, 0, 1, 0, true, false);
1296 }
1297 }
1298
1299 static LLVMValueRef fetch_input_gs(
1300 struct lp_build_tgsi_context *bld_base,
1301 const struct tgsi_full_src_register *reg,
1302 enum tgsi_opcode_type type,
1303 unsigned swizzle)
1304 {
1305 struct si_shader_context *ctx = si_shader_context(bld_base);
1306 struct si_shader *shader = ctx->shader;
1307 struct lp_build_context *uint = &ctx->bld_base.uint_bld;
1308 LLVMValueRef vtx_offset, soffset;
1309 struct tgsi_shader_info *info = &shader->selector->info;
1310 unsigned semantic_name = info->input_semantic_name[reg->Register.Index];
1311 unsigned semantic_index = info->input_semantic_index[reg->Register.Index];
1312 unsigned param;
1313 LLVMValueRef value;
1314
1315 if (swizzle != ~0 && semantic_name == TGSI_SEMANTIC_PRIMID)
1316 return get_primitive_id(ctx, swizzle);
1317
1318 if (!reg->Register.Dimension)
1319 return NULL;
1320
1321 param = si_shader_io_get_unique_index(semantic_name, semantic_index);
1322
1323 /* GFX9 has the ESGS ring in LDS. */
1324 if (ctx->screen->info.chip_class >= GFX9) {
1325 unsigned index = reg->Dimension.Index;
1326
1327 switch (index / 2) {
1328 case 0:
1329 vtx_offset = unpack_param(ctx, ctx->param_gs_vtx01_offset,
1330 index % 2 ? 16 : 0, 16);
1331 break;
1332 case 1:
1333 vtx_offset = unpack_param(ctx, ctx->param_gs_vtx23_offset,
1334 index % 2 ? 16 : 0, 16);
1335 break;
1336 case 2:
1337 vtx_offset = unpack_param(ctx, ctx->param_gs_vtx45_offset,
1338 index % 2 ? 16 : 0, 16);
1339 break;
1340 default:
1341 assert(0);
1342 return NULL;
1343 }
1344
1345 vtx_offset = LLVMBuildAdd(ctx->ac.builder, vtx_offset,
1346 LLVMConstInt(ctx->i32, param * 4, 0), "");
1347 return lds_load(bld_base, type, swizzle, vtx_offset);
1348 }
1349
1350 /* GFX6: input load from the ESGS ring in memory. */
1351 if (swizzle == ~0) {
1352 LLVMValueRef values[TGSI_NUM_CHANNELS];
1353 unsigned chan;
1354 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1355 values[chan] = fetch_input_gs(bld_base, reg, type, chan);
1356 }
1357 return lp_build_gather_values(&ctx->gallivm, values,
1358 TGSI_NUM_CHANNELS);
1359 }
1360
1361 /* Get the vertex offset parameter on GFX6. */
1362 unsigned vtx_offset_param = reg->Dimension.Index;
1363 LLVMValueRef gs_vtx_offset = ctx->gs_vtx_offset[vtx_offset_param];
1364
1365 vtx_offset = lp_build_mul_imm(uint, gs_vtx_offset, 4);
1366
1367 soffset = LLVMConstInt(ctx->i32, (param * 4 + swizzle) * 256, 0);
1368
1369 value = ac_build_buffer_load(&ctx->ac, ctx->esgs_ring, 1, ctx->i32_0,
1370 vtx_offset, soffset, 0, 1, 0, true, false);
1371 if (tgsi_type_is_64bit(type)) {
1372 LLVMValueRef value2;
1373 soffset = LLVMConstInt(ctx->i32, (param * 4 + swizzle + 1) * 256, 0);
1374
1375 value2 = ac_build_buffer_load(&ctx->ac, ctx->esgs_ring, 1,
1376 ctx->i32_0, vtx_offset, soffset,
1377 0, 1, 0, true, false);
1378 return si_llvm_emit_fetch_64bit(bld_base, type,
1379 value, value2);
1380 }
1381 return bitcast(bld_base, type, value);
1382 }
1383
1384 static int lookup_interp_param_index(unsigned interpolate, unsigned location)
1385 {
1386 switch (interpolate) {
1387 case TGSI_INTERPOLATE_CONSTANT:
1388 return 0;
1389
1390 case TGSI_INTERPOLATE_LINEAR:
1391 if (location == TGSI_INTERPOLATE_LOC_SAMPLE)
1392 return SI_PARAM_LINEAR_SAMPLE;
1393 else if (location == TGSI_INTERPOLATE_LOC_CENTROID)
1394 return SI_PARAM_LINEAR_CENTROID;
1395 else
1396 return SI_PARAM_LINEAR_CENTER;
1397 break;
1398 case TGSI_INTERPOLATE_COLOR:
1399 case TGSI_INTERPOLATE_PERSPECTIVE:
1400 if (location == TGSI_INTERPOLATE_LOC_SAMPLE)
1401 return SI_PARAM_PERSP_SAMPLE;
1402 else if (location == TGSI_INTERPOLATE_LOC_CENTROID)
1403 return SI_PARAM_PERSP_CENTROID;
1404 else
1405 return SI_PARAM_PERSP_CENTER;
1406 break;
1407 default:
1408 fprintf(stderr, "Warning: Unhandled interpolation mode.\n");
1409 return -1;
1410 }
1411 }
1412
1413 static LLVMValueRef si_build_fs_interp(struct si_shader_context *ctx,
1414 unsigned attr_index, unsigned chan,
1415 LLVMValueRef prim_mask,
1416 LLVMValueRef i, LLVMValueRef j)
1417 {
1418 if (i || j) {
1419 return ac_build_fs_interp(&ctx->ac,
1420 LLVMConstInt(ctx->i32, chan, 0),
1421 LLVMConstInt(ctx->i32, attr_index, 0),
1422 prim_mask, i, j);
1423 }
1424 return ac_build_fs_interp_mov(&ctx->ac,
1425 LLVMConstInt(ctx->i32, 2, 0), /* P0 */
1426 LLVMConstInt(ctx->i32, chan, 0),
1427 LLVMConstInt(ctx->i32, attr_index, 0),
1428 prim_mask);
1429 }
1430
1431 /**
1432 * Interpolate a fragment shader input.
1433 *
1434 * @param ctx context
1435 * @param input_index index of the input in hardware
1436 * @param semantic_name TGSI_SEMANTIC_*
1437 * @param semantic_index semantic index
1438 * @param num_interp_inputs number of all interpolated inputs (= BCOLOR offset)
1439 * @param colors_read_mask color components read (4 bits for each color, 8 bits in total)
1440 * @param interp_param interpolation weights (i,j)
1441 * @param prim_mask SI_PARAM_PRIM_MASK
1442 * @param face SI_PARAM_FRONT_FACE
1443 * @param result the return value (4 components)
1444 */
1445 static void interp_fs_input(struct si_shader_context *ctx,
1446 unsigned input_index,
1447 unsigned semantic_name,
1448 unsigned semantic_index,
1449 unsigned num_interp_inputs,
1450 unsigned colors_read_mask,
1451 LLVMValueRef interp_param,
1452 LLVMValueRef prim_mask,
1453 LLVMValueRef face,
1454 LLVMValueRef result[4])
1455 {
1456 LLVMValueRef i = NULL, j = NULL;
1457 unsigned chan;
1458
1459 /* fs.constant returns the param from the middle vertex, so it's not
1460 * really useful for flat shading. It's meant to be used for custom
1461 * interpolation (but the intrinsic can't fetch from the other two
1462 * vertices).
1463 *
1464 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
1465 * to do the right thing. The only reason we use fs.constant is that
1466 * fs.interp cannot be used on integers, because they can be equal
1467 * to NaN.
1468 *
1469 * When interp is false we will use fs.constant or for newer llvm,
1470 * amdgcn.interp.mov.
1471 */
1472 bool interp = interp_param != NULL;
1473
1474 if (interp) {
1475 interp_param = LLVMBuildBitCast(ctx->ac.builder, interp_param,
1476 LLVMVectorType(ctx->f32, 2), "");
1477
1478 i = LLVMBuildExtractElement(ctx->ac.builder, interp_param,
1479 ctx->i32_0, "");
1480 j = LLVMBuildExtractElement(ctx->ac.builder, interp_param,
1481 ctx->i32_1, "");
1482 }
1483
1484 if (semantic_name == TGSI_SEMANTIC_COLOR &&
1485 ctx->shader->key.part.ps.prolog.color_two_side) {
1486 LLVMValueRef is_face_positive;
1487
1488 /* If BCOLOR0 is used, BCOLOR1 is at offset "num_inputs + 1",
1489 * otherwise it's at offset "num_inputs".
1490 */
1491 unsigned back_attr_offset = num_interp_inputs;
1492 if (semantic_index == 1 && colors_read_mask & 0xf)
1493 back_attr_offset += 1;
1494
1495 is_face_positive = LLVMBuildICmp(ctx->ac.builder, LLVMIntNE,
1496 face, ctx->i32_0, "");
1497
1498 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1499 LLVMValueRef front, back;
1500
1501 front = si_build_fs_interp(ctx,
1502 input_index, chan,
1503 prim_mask, i, j);
1504 back = si_build_fs_interp(ctx,
1505 back_attr_offset, chan,
1506 prim_mask, i, j);
1507
1508 result[chan] = LLVMBuildSelect(ctx->ac.builder,
1509 is_face_positive,
1510 front,
1511 back,
1512 "");
1513 }
1514 } else if (semantic_name == TGSI_SEMANTIC_FOG) {
1515 result[0] = si_build_fs_interp(ctx, input_index,
1516 0, prim_mask, i, j);
1517 result[1] =
1518 result[2] = LLVMConstReal(ctx->f32, 0.0f);
1519 result[3] = LLVMConstReal(ctx->f32, 1.0f);
1520 } else {
1521 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1522 result[chan] = si_build_fs_interp(ctx,
1523 input_index, chan,
1524 prim_mask, i, j);
1525 }
1526 }
1527 }
1528
1529 void si_llvm_load_input_fs(
1530 struct si_shader_context *ctx,
1531 unsigned input_index,
1532 LLVMValueRef out[4])
1533 {
1534 struct lp_build_context *base = &ctx->bld_base.base;
1535 struct si_shader *shader = ctx->shader;
1536 struct tgsi_shader_info *info = &shader->selector->info;
1537 LLVMValueRef main_fn = ctx->main_fn;
1538 LLVMValueRef interp_param = NULL;
1539 int interp_param_idx;
1540 enum tgsi_semantic semantic_name = info->input_semantic_name[input_index];
1541 unsigned semantic_index = info->input_semantic_index[input_index];
1542 enum tgsi_interpolate_mode interp_mode = info->input_interpolate[input_index];
1543 enum tgsi_interpolate_loc interp_loc = info->input_interpolate_loc[input_index];
1544
1545 /* Get colors from input VGPRs (set by the prolog). */
1546 if (semantic_name == TGSI_SEMANTIC_COLOR) {
1547 unsigned colors_read = shader->selector->info.colors_read;
1548 unsigned mask = colors_read >> (semantic_index * 4);
1549 unsigned offset = SI_PARAM_POS_FIXED_PT + 1 +
1550 (semantic_index ? util_bitcount(colors_read & 0xf) : 0);
1551
1552 out[0] = mask & 0x1 ? LLVMGetParam(main_fn, offset++) : base->undef;
1553 out[1] = mask & 0x2 ? LLVMGetParam(main_fn, offset++) : base->undef;
1554 out[2] = mask & 0x4 ? LLVMGetParam(main_fn, offset++) : base->undef;
1555 out[3] = mask & 0x8 ? LLVMGetParam(main_fn, offset++) : base->undef;
1556 return;
1557 }
1558
1559 interp_param_idx = lookup_interp_param_index(interp_mode, interp_loc);
1560 if (interp_param_idx == -1)
1561 return;
1562 else if (interp_param_idx) {
1563 interp_param = LLVMGetParam(ctx->main_fn, interp_param_idx);
1564 }
1565
1566 interp_fs_input(ctx, input_index, semantic_name,
1567 semantic_index, 0, /* this param is unused */
1568 shader->selector->info.colors_read, interp_param,
1569 LLVMGetParam(main_fn, SI_PARAM_PRIM_MASK),
1570 LLVMGetParam(main_fn, SI_PARAM_FRONT_FACE),
1571 &out[0]);
1572 }
1573
1574 static void declare_input_fs(
1575 struct si_shader_context *ctx,
1576 unsigned input_index,
1577 const struct tgsi_full_declaration *decl,
1578 LLVMValueRef out[4])
1579 {
1580 si_llvm_load_input_fs(ctx, input_index, out);
1581 }
1582
1583 static LLVMValueRef get_sample_id(struct si_shader_context *ctx)
1584 {
1585 return unpack_param(ctx, SI_PARAM_ANCILLARY, 8, 4);
1586 }
1587
1588
1589 /**
1590 * Load a dword from a constant buffer.
1591 */
1592 static LLVMValueRef buffer_load_const(struct si_shader_context *ctx,
1593 LLVMValueRef resource,
1594 LLVMValueRef offset)
1595 {
1596 return ac_build_buffer_load(&ctx->ac, resource, 1, NULL, offset, NULL,
1597 0, 0, 0, true, true);
1598 }
1599
1600 static LLVMValueRef load_sample_position(struct si_shader_context *ctx, LLVMValueRef sample_id)
1601 {
1602 struct lp_build_context *uint_bld = &ctx->bld_base.uint_bld;
1603 LLVMValueRef desc = LLVMGetParam(ctx->main_fn, ctx->param_rw_buffers);
1604 LLVMValueRef buf_index = LLVMConstInt(ctx->i32, SI_PS_CONST_SAMPLE_POSITIONS, 0);
1605 LLVMValueRef resource = ac_build_load_to_sgpr(&ctx->ac, desc, buf_index);
1606
1607 /* offset = sample_id * 8 (8 = 2 floats containing samplepos.xy) */
1608 LLVMValueRef offset0 = lp_build_mul_imm(uint_bld, sample_id, 8);
1609 LLVMValueRef offset1 = LLVMBuildAdd(ctx->ac.builder, offset0, LLVMConstInt(ctx->i32, 4, 0), "");
1610
1611 LLVMValueRef pos[4] = {
1612 buffer_load_const(ctx, resource, offset0),
1613 buffer_load_const(ctx, resource, offset1),
1614 LLVMConstReal(ctx->f32, 0),
1615 LLVMConstReal(ctx->f32, 0)
1616 };
1617
1618 return lp_build_gather_values(&ctx->gallivm, pos, 4);
1619 }
1620
1621 void si_load_system_value(struct si_shader_context *ctx,
1622 unsigned index,
1623 const struct tgsi_full_declaration *decl)
1624 {
1625 struct lp_build_context *bld = &ctx->bld_base.base;
1626 LLVMValueRef value = 0;
1627
1628 assert(index < RADEON_LLVM_MAX_SYSTEM_VALUES);
1629
1630 switch (decl->Semantic.Name) {
1631 case TGSI_SEMANTIC_INSTANCEID:
1632 value = ctx->abi.instance_id;
1633 break;
1634
1635 case TGSI_SEMANTIC_VERTEXID:
1636 value = LLVMBuildAdd(ctx->ac.builder,
1637 ctx->abi.vertex_id,
1638 ctx->abi.base_vertex, "");
1639 break;
1640
1641 case TGSI_SEMANTIC_VERTEXID_NOBASE:
1642 /* Unused. Clarify the meaning in indexed vs. non-indexed
1643 * draws if this is ever used again. */
1644 assert(false);
1645 break;
1646
1647 case TGSI_SEMANTIC_BASEVERTEX:
1648 {
1649 /* For non-indexed draws, the base vertex set by the driver
1650 * (for direct draws) or the CP (for indirect draws) is the
1651 * first vertex ID, but GLSL expects 0 to be returned.
1652 */
1653 LLVMValueRef vs_state = LLVMGetParam(ctx->main_fn, ctx->param_vs_state_bits);
1654 LLVMValueRef indexed;
1655
1656 indexed = LLVMBuildLShr(ctx->ac.builder, vs_state, ctx->i32_1, "");
1657 indexed = LLVMBuildTrunc(ctx->ac.builder, indexed, ctx->i1, "");
1658
1659 value = LLVMBuildSelect(ctx->ac.builder, indexed,
1660 ctx->abi.base_vertex, ctx->i32_0, "");
1661 break;
1662 }
1663
1664 case TGSI_SEMANTIC_BASEINSTANCE:
1665 value = ctx->abi.start_instance;
1666 break;
1667
1668 case TGSI_SEMANTIC_DRAWID:
1669 value = ctx->abi.draw_id;
1670 break;
1671
1672 case TGSI_SEMANTIC_INVOCATIONID:
1673 if (ctx->type == PIPE_SHADER_TESS_CTRL)
1674 value = unpack_param(ctx, ctx->param_tcs_rel_ids, 8, 5);
1675 else if (ctx->type == PIPE_SHADER_GEOMETRY)
1676 value = ctx->abi.gs_invocation_id;
1677 else
1678 assert(!"INVOCATIONID not implemented");
1679 break;
1680
1681 case TGSI_SEMANTIC_POSITION:
1682 {
1683 LLVMValueRef pos[4] = {
1684 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_X_FLOAT),
1685 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_Y_FLOAT),
1686 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_Z_FLOAT),
1687 lp_build_emit_llvm_unary(&ctx->bld_base, TGSI_OPCODE_RCP,
1688 LLVMGetParam(ctx->main_fn,
1689 SI_PARAM_POS_W_FLOAT)),
1690 };
1691 value = lp_build_gather_values(&ctx->gallivm, pos, 4);
1692 break;
1693 }
1694
1695 case TGSI_SEMANTIC_FACE:
1696 value = ctx->abi.front_face;
1697 break;
1698
1699 case TGSI_SEMANTIC_SAMPLEID:
1700 value = get_sample_id(ctx);
1701 break;
1702
1703 case TGSI_SEMANTIC_SAMPLEPOS: {
1704 LLVMValueRef pos[4] = {
1705 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_X_FLOAT),
1706 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_Y_FLOAT),
1707 LLVMConstReal(ctx->f32, 0),
1708 LLVMConstReal(ctx->f32, 0)
1709 };
1710 pos[0] = lp_build_emit_llvm_unary(&ctx->bld_base,
1711 TGSI_OPCODE_FRC, pos[0]);
1712 pos[1] = lp_build_emit_llvm_unary(&ctx->bld_base,
1713 TGSI_OPCODE_FRC, pos[1]);
1714 value = lp_build_gather_values(&ctx->gallivm, pos, 4);
1715 break;
1716 }
1717
1718 case TGSI_SEMANTIC_SAMPLEMASK:
1719 /* This can only occur with the OpenGL Core profile, which
1720 * doesn't support smoothing.
1721 */
1722 value = LLVMGetParam(ctx->main_fn, SI_PARAM_SAMPLE_COVERAGE);
1723 break;
1724
1725 case TGSI_SEMANTIC_TESSCOORD:
1726 {
1727 LLVMValueRef coord[4] = {
1728 LLVMGetParam(ctx->main_fn, ctx->param_tes_u),
1729 LLVMGetParam(ctx->main_fn, ctx->param_tes_v),
1730 ctx->ac.f32_0,
1731 ctx->ac.f32_0
1732 };
1733
1734 /* For triangles, the vector should be (u, v, 1-u-v). */
1735 if (ctx->shader->selector->info.properties[TGSI_PROPERTY_TES_PRIM_MODE] ==
1736 PIPE_PRIM_TRIANGLES)
1737 coord[2] = lp_build_sub(bld, ctx->ac.f32_1,
1738 lp_build_add(bld, coord[0], coord[1]));
1739
1740 value = lp_build_gather_values(&ctx->gallivm, coord, 4);
1741 break;
1742 }
1743
1744 case TGSI_SEMANTIC_VERTICESIN:
1745 if (ctx->type == PIPE_SHADER_TESS_CTRL)
1746 value = unpack_param(ctx, ctx->param_tcs_out_lds_layout, 26, 6);
1747 else if (ctx->type == PIPE_SHADER_TESS_EVAL)
1748 value = get_num_tcs_out_vertices(ctx);
1749 else
1750 assert(!"invalid shader stage for TGSI_SEMANTIC_VERTICESIN");
1751 break;
1752
1753 case TGSI_SEMANTIC_TESSINNER:
1754 case TGSI_SEMANTIC_TESSOUTER:
1755 {
1756 LLVMValueRef buffer, base, addr;
1757 int param = si_shader_io_get_unique_index_patch(decl->Semantic.Name, 0);
1758
1759 buffer = desc_from_addr_base64k(ctx, ctx->param_tcs_offchip_addr_base64k);
1760
1761 base = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
1762 addr = get_tcs_tes_buffer_address(ctx, get_rel_patch_id(ctx), NULL,
1763 LLVMConstInt(ctx->i32, param, 0));
1764
1765 value = buffer_load(&ctx->bld_base, TGSI_TYPE_FLOAT,
1766 ~0, buffer, base, addr, true);
1767
1768 break;
1769 }
1770
1771 case TGSI_SEMANTIC_DEFAULT_TESSOUTER_SI:
1772 case TGSI_SEMANTIC_DEFAULT_TESSINNER_SI:
1773 {
1774 LLVMValueRef buf, slot, val[4];
1775 int i, offset;
1776
1777 slot = LLVMConstInt(ctx->i32, SI_HS_CONST_DEFAULT_TESS_LEVELS, 0);
1778 buf = LLVMGetParam(ctx->main_fn, ctx->param_rw_buffers);
1779 buf = ac_build_load_to_sgpr(&ctx->ac, buf, slot);
1780 offset = decl->Semantic.Name == TGSI_SEMANTIC_DEFAULT_TESSINNER_SI ? 4 : 0;
1781
1782 for (i = 0; i < 4; i++)
1783 val[i] = buffer_load_const(ctx, buf,
1784 LLVMConstInt(ctx->i32, (offset + i) * 4, 0));
1785 value = lp_build_gather_values(&ctx->gallivm, val, 4);
1786 break;
1787 }
1788
1789 case TGSI_SEMANTIC_PRIMID:
1790 value = get_primitive_id(ctx, 0);
1791 break;
1792
1793 case TGSI_SEMANTIC_GRID_SIZE:
1794 value = LLVMGetParam(ctx->main_fn, ctx->param_grid_size);
1795 break;
1796
1797 case TGSI_SEMANTIC_BLOCK_SIZE:
1798 {
1799 LLVMValueRef values[3];
1800 unsigned i;
1801 unsigned *properties = ctx->shader->selector->info.properties;
1802
1803 if (properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] != 0) {
1804 unsigned sizes[3] = {
1805 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH],
1806 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT],
1807 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH]
1808 };
1809
1810 for (i = 0; i < 3; ++i)
1811 values[i] = LLVMConstInt(ctx->i32, sizes[i], 0);
1812
1813 value = lp_build_gather_values(&ctx->gallivm, values, 3);
1814 } else {
1815 value = LLVMGetParam(ctx->main_fn, ctx->param_block_size);
1816 }
1817 break;
1818 }
1819
1820 case TGSI_SEMANTIC_BLOCK_ID:
1821 {
1822 LLVMValueRef values[3];
1823
1824 for (int i = 0; i < 3; i++) {
1825 values[i] = ctx->i32_0;
1826 if (ctx->param_block_id[i] >= 0) {
1827 values[i] = LLVMGetParam(ctx->main_fn,
1828 ctx->param_block_id[i]);
1829 }
1830 }
1831 value = lp_build_gather_values(&ctx->gallivm, values, 3);
1832 break;
1833 }
1834
1835 case TGSI_SEMANTIC_THREAD_ID:
1836 value = LLVMGetParam(ctx->main_fn, ctx->param_thread_id);
1837 break;
1838
1839 case TGSI_SEMANTIC_HELPER_INVOCATION:
1840 value = lp_build_intrinsic(ctx->ac.builder,
1841 "llvm.amdgcn.ps.live",
1842 ctx->i1, NULL, 0,
1843 LP_FUNC_ATTR_READNONE);
1844 value = LLVMBuildNot(ctx->ac.builder, value, "");
1845 value = LLVMBuildSExt(ctx->ac.builder, value, ctx->i32, "");
1846 break;
1847
1848 case TGSI_SEMANTIC_SUBGROUP_SIZE:
1849 value = LLVMConstInt(ctx->i32, 64, 0);
1850 break;
1851
1852 case TGSI_SEMANTIC_SUBGROUP_INVOCATION:
1853 value = ac_get_thread_id(&ctx->ac);
1854 break;
1855
1856 case TGSI_SEMANTIC_SUBGROUP_EQ_MASK:
1857 {
1858 LLVMValueRef id = ac_get_thread_id(&ctx->ac);
1859 id = LLVMBuildZExt(ctx->ac.builder, id, ctx->i64, "");
1860 value = LLVMBuildShl(ctx->ac.builder, LLVMConstInt(ctx->i64, 1, 0), id, "");
1861 value = LLVMBuildBitCast(ctx->ac.builder, value, ctx->v2i32, "");
1862 break;
1863 }
1864
1865 case TGSI_SEMANTIC_SUBGROUP_GE_MASK:
1866 case TGSI_SEMANTIC_SUBGROUP_GT_MASK:
1867 case TGSI_SEMANTIC_SUBGROUP_LE_MASK:
1868 case TGSI_SEMANTIC_SUBGROUP_LT_MASK:
1869 {
1870 LLVMValueRef id = ac_get_thread_id(&ctx->ac);
1871 if (decl->Semantic.Name == TGSI_SEMANTIC_SUBGROUP_GT_MASK ||
1872 decl->Semantic.Name == TGSI_SEMANTIC_SUBGROUP_LE_MASK) {
1873 /* All bits set except LSB */
1874 value = LLVMConstInt(ctx->i64, -2, 0);
1875 } else {
1876 /* All bits set */
1877 value = LLVMConstInt(ctx->i64, -1, 0);
1878 }
1879 id = LLVMBuildZExt(ctx->ac.builder, id, ctx->i64, "");
1880 value = LLVMBuildShl(ctx->ac.builder, value, id, "");
1881 if (decl->Semantic.Name == TGSI_SEMANTIC_SUBGROUP_LE_MASK ||
1882 decl->Semantic.Name == TGSI_SEMANTIC_SUBGROUP_LT_MASK)
1883 value = LLVMBuildNot(ctx->ac.builder, value, "");
1884 value = LLVMBuildBitCast(ctx->ac.builder, value, ctx->v2i32, "");
1885 break;
1886 }
1887
1888 default:
1889 assert(!"unknown system value");
1890 return;
1891 }
1892
1893 ctx->system_values[index] = value;
1894 }
1895
1896 void si_declare_compute_memory(struct si_shader_context *ctx,
1897 const struct tgsi_full_declaration *decl)
1898 {
1899 struct si_shader_selector *sel = ctx->shader->selector;
1900
1901 LLVMTypeRef i8p = LLVMPointerType(ctx->i8, LOCAL_ADDR_SPACE);
1902 LLVMValueRef var;
1903
1904 assert(decl->Declaration.MemType == TGSI_MEMORY_TYPE_SHARED);
1905 assert(decl->Range.First == decl->Range.Last);
1906 assert(!ctx->ac.lds);
1907
1908 var = LLVMAddGlobalInAddressSpace(ctx->ac.module,
1909 LLVMArrayType(ctx->i8, sel->local_size),
1910 "compute_lds",
1911 LOCAL_ADDR_SPACE);
1912 LLVMSetAlignment(var, 4);
1913
1914 ctx->ac.lds = LLVMBuildBitCast(ctx->ac.builder, var, i8p, "");
1915 }
1916
1917 static LLVMValueRef load_const_buffer_desc(struct si_shader_context *ctx, int i)
1918 {
1919 LLVMValueRef list_ptr = LLVMGetParam(ctx->main_fn,
1920 ctx->param_const_and_shader_buffers);
1921
1922 return ac_build_load_to_sgpr(&ctx->ac, list_ptr,
1923 LLVMConstInt(ctx->i32, si_get_constbuf_slot(i), 0));
1924 }
1925
1926 static LLVMValueRef load_ubo(struct ac_shader_abi *abi, LLVMValueRef index)
1927 {
1928 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1929 LLVMValueRef ptr = LLVMGetParam(ctx->main_fn, ctx->param_const_and_shader_buffers);
1930
1931 index = si_llvm_bound_index(ctx, index, ctx->num_const_buffers);
1932 index = LLVMBuildAdd(ctx->ac.builder, index,
1933 LLVMConstInt(ctx->i32, SI_NUM_SHADER_BUFFERS, 0), "");
1934
1935 return ac_build_load_to_sgpr(&ctx->ac, ptr, index);
1936 }
1937
1938 static LLVMValueRef
1939 load_ssbo(struct ac_shader_abi *abi, LLVMValueRef index, bool write)
1940 {
1941 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1942 LLVMValueRef rsrc_ptr = LLVMGetParam(ctx->main_fn,
1943 ctx->param_const_and_shader_buffers);
1944
1945 index = si_llvm_bound_index(ctx, index, ctx->num_shader_buffers);
1946 index = LLVMBuildSub(ctx->ac.builder,
1947 LLVMConstInt(ctx->i32, SI_NUM_SHADER_BUFFERS - 1, 0),
1948 index, "");
1949
1950 return ac_build_load_to_sgpr(&ctx->ac, rsrc_ptr, index);
1951 }
1952
1953 static LLVMValueRef fetch_constant(
1954 struct lp_build_tgsi_context *bld_base,
1955 const struct tgsi_full_src_register *reg,
1956 enum tgsi_opcode_type type,
1957 unsigned swizzle)
1958 {
1959 struct si_shader_context *ctx = si_shader_context(bld_base);
1960 struct si_shader_selector *sel = ctx->shader->selector;
1961 const struct tgsi_ind_register *ireg = &reg->Indirect;
1962 unsigned buf, idx;
1963
1964 LLVMValueRef addr, bufp;
1965
1966 if (swizzle == LP_CHAN_ALL) {
1967 unsigned chan;
1968 LLVMValueRef values[4];
1969 for (chan = 0; chan < TGSI_NUM_CHANNELS; ++chan)
1970 values[chan] = fetch_constant(bld_base, reg, type, chan);
1971
1972 return lp_build_gather_values(&ctx->gallivm, values, 4);
1973 }
1974
1975 /* Split 64-bit loads. */
1976 if (tgsi_type_is_64bit(type)) {
1977 LLVMValueRef lo, hi;
1978
1979 lo = fetch_constant(bld_base, reg, TGSI_TYPE_UNSIGNED, swizzle);
1980 hi = fetch_constant(bld_base, reg, TGSI_TYPE_UNSIGNED, swizzle + 1);
1981 return si_llvm_emit_fetch_64bit(bld_base, type, lo, hi);
1982 }
1983
1984 idx = reg->Register.Index * 4 + swizzle;
1985 if (reg->Register.Indirect) {
1986 addr = si_get_indirect_index(ctx, ireg, 16, idx * 4);
1987 } else {
1988 addr = LLVMConstInt(ctx->i32, idx * 4, 0);
1989 }
1990
1991 /* Fast path when user data SGPRs point to constant buffer 0 directly. */
1992 if (sel->info.const_buffers_declared == 1 &&
1993 sel->info.shader_buffers_declared == 0) {
1994 LLVMValueRef ptr =
1995 LLVMGetParam(ctx->main_fn, ctx->param_const_and_shader_buffers);
1996
1997 /* This enables use of s_load_dword and flat_load_dword for const buffer 0
1998 * loads, and up to x4 load opcode merging. However, it leads to horrible
1999 * code reducing SIMD wave occupancy from 8 to 2 in many cases.
2000 *
2001 * Using s_buffer_load_dword (x1) seems to be the best option right now.
2002 *
2003 * LLVM 5.0 on SI doesn't insert a required s_nop between SALU setting
2004 * a descriptor and s_buffer_load_dword using it, so we can't expand
2005 * the pointer into a full descriptor like below. We have to use
2006 * s_load_dword instead. The only case when LLVM 5.0 would select
2007 * s_buffer_load_dword (that we have to prevent) is when we use use
2008 * a literal offset where we don't need bounds checking.
2009 */
2010 if (ctx->screen->info.chip_class == SI &&
2011 HAVE_LLVM < 0x0600 &&
2012 !reg->Register.Indirect) {
2013 addr = LLVMBuildLShr(ctx->ac.builder, addr, LLVMConstInt(ctx->i32, 2, 0), "");
2014 LLVMValueRef result = ac_build_load_invariant(&ctx->ac, ptr, addr);
2015 return bitcast(bld_base, type, result);
2016 }
2017
2018 /* Do the bounds checking with a descriptor, because
2019 * doing computation and manual bounds checking of 64-bit
2020 * addresses generates horrible VALU code with very high
2021 * VGPR usage and very low SIMD occupancy.
2022 */
2023 ptr = LLVMBuildPtrToInt(ctx->ac.builder, ptr, ctx->i64, "");
2024 ptr = LLVMBuildBitCast(ctx->ac.builder, ptr, ctx->v2i32, "");
2025
2026 LLVMValueRef desc_elems[] = {
2027 LLVMBuildExtractElement(ctx->ac.builder, ptr, ctx->i32_0, ""),
2028 LLVMBuildExtractElement(ctx->ac.builder, ptr, ctx->i32_1, ""),
2029 LLVMConstInt(ctx->i32, (sel->info.const_file_max[0] + 1) * 16, 0),
2030 LLVMConstInt(ctx->i32,
2031 S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2032 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2033 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2034 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2035 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2036 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32), 0)
2037 };
2038 LLVMValueRef desc = ac_build_gather_values(&ctx->ac, desc_elems, 4);
2039 LLVMValueRef result = buffer_load_const(ctx, desc, addr);
2040 return bitcast(bld_base, type, result);
2041 }
2042
2043 assert(reg->Register.Dimension);
2044 buf = reg->Dimension.Index;
2045
2046 if (reg->Dimension.Indirect) {
2047 LLVMValueRef ptr = LLVMGetParam(ctx->main_fn, ctx->param_const_and_shader_buffers);
2048 LLVMValueRef index;
2049 index = si_get_bounded_indirect_index(ctx, &reg->DimIndirect,
2050 reg->Dimension.Index,
2051 ctx->num_const_buffers);
2052 index = LLVMBuildAdd(ctx->ac.builder, index,
2053 LLVMConstInt(ctx->i32, SI_NUM_SHADER_BUFFERS, 0), "");
2054 bufp = ac_build_load_to_sgpr(&ctx->ac, ptr, index);
2055 } else
2056 bufp = load_const_buffer_desc(ctx, buf);
2057
2058 return bitcast(bld_base, type, buffer_load_const(ctx, bufp, addr));
2059 }
2060
2061 /* Upper 16 bits must be zero. */
2062 static LLVMValueRef si_llvm_pack_two_int16(struct si_shader_context *ctx,
2063 LLVMValueRef val[2])
2064 {
2065 return LLVMBuildOr(ctx->ac.builder, val[0],
2066 LLVMBuildShl(ctx->ac.builder, val[1],
2067 LLVMConstInt(ctx->i32, 16, 0),
2068 ""), "");
2069 }
2070
2071 /* Upper 16 bits are ignored and will be dropped. */
2072 static LLVMValueRef si_llvm_pack_two_int32_as_int16(struct si_shader_context *ctx,
2073 LLVMValueRef val[2])
2074 {
2075 LLVMValueRef v[2] = {
2076 LLVMBuildAnd(ctx->ac.builder, val[0],
2077 LLVMConstInt(ctx->i32, 0xffff, 0), ""),
2078 val[1],
2079 };
2080 return si_llvm_pack_two_int16(ctx, v);
2081 }
2082
2083 /* Initialize arguments for the shader export intrinsic */
2084 static void si_llvm_init_export_args(struct si_shader_context *ctx,
2085 LLVMValueRef *values,
2086 unsigned target,
2087 struct ac_export_args *args)
2088 {
2089 LLVMValueRef f32undef = LLVMGetUndef(ctx->ac.f32);
2090 LLVMBuilderRef builder = ctx->ac.builder;
2091 LLVMValueRef val[4];
2092 unsigned spi_shader_col_format = V_028714_SPI_SHADER_32_ABGR;
2093 unsigned chan;
2094 bool is_int8, is_int10;
2095
2096 /* Default is 0xf. Adjusted below depending on the format. */
2097 args->enabled_channels = 0xf; /* writemask */
2098
2099 /* Specify whether the EXEC mask represents the valid mask */
2100 args->valid_mask = 0;
2101
2102 /* Specify whether this is the last export */
2103 args->done = 0;
2104
2105 /* Specify the target we are exporting */
2106 args->target = target;
2107
2108 if (ctx->type == PIPE_SHADER_FRAGMENT) {
2109 const struct si_shader_key *key = &ctx->shader->key;
2110 unsigned col_formats = key->part.ps.epilog.spi_shader_col_format;
2111 int cbuf = target - V_008DFC_SQ_EXP_MRT;
2112
2113 assert(cbuf >= 0 && cbuf < 8);
2114 spi_shader_col_format = (col_formats >> (cbuf * 4)) & 0xf;
2115 is_int8 = (key->part.ps.epilog.color_is_int8 >> cbuf) & 0x1;
2116 is_int10 = (key->part.ps.epilog.color_is_int10 >> cbuf) & 0x1;
2117 }
2118
2119 args->compr = false;
2120 args->out[0] = f32undef;
2121 args->out[1] = f32undef;
2122 args->out[2] = f32undef;
2123 args->out[3] = f32undef;
2124
2125 switch (spi_shader_col_format) {
2126 case V_028714_SPI_SHADER_ZERO:
2127 args->enabled_channels = 0; /* writemask */
2128 args->target = V_008DFC_SQ_EXP_NULL;
2129 break;
2130
2131 case V_028714_SPI_SHADER_32_R:
2132 args->enabled_channels = 1; /* writemask */
2133 args->out[0] = values[0];
2134 break;
2135
2136 case V_028714_SPI_SHADER_32_GR:
2137 args->enabled_channels = 0x3; /* writemask */
2138 args->out[0] = values[0];
2139 args->out[1] = values[1];
2140 break;
2141
2142 case V_028714_SPI_SHADER_32_AR:
2143 args->enabled_channels = 0x9; /* writemask */
2144 args->out[0] = values[0];
2145 args->out[3] = values[3];
2146 break;
2147
2148 case V_028714_SPI_SHADER_FP16_ABGR:
2149 args->compr = 1; /* COMPR flag */
2150
2151 for (chan = 0; chan < 2; chan++) {
2152 LLVMValueRef pack_args[2] = {
2153 values[2 * chan],
2154 values[2 * chan + 1]
2155 };
2156 LLVMValueRef packed;
2157
2158 packed = ac_build_cvt_pkrtz_f16(&ctx->ac, pack_args);
2159 args->out[chan] = ac_to_float(&ctx->ac, packed);
2160 }
2161 break;
2162
2163 case V_028714_SPI_SHADER_UNORM16_ABGR:
2164 for (chan = 0; chan < 4; chan++) {
2165 val[chan] = ac_build_clamp(&ctx->ac, values[chan]);
2166 val[chan] = LLVMBuildFMul(builder, val[chan],
2167 LLVMConstReal(ctx->f32, 65535), "");
2168 val[chan] = LLVMBuildFAdd(builder, val[chan],
2169 LLVMConstReal(ctx->f32, 0.5), "");
2170 val[chan] = LLVMBuildFPToUI(builder, val[chan],
2171 ctx->i32, "");
2172 }
2173
2174 args->compr = 1; /* COMPR flag */
2175 args->out[0] = ac_to_float(&ctx->ac, si_llvm_pack_two_int16(ctx, val));
2176 args->out[1] = ac_to_float(&ctx->ac, si_llvm_pack_two_int16(ctx, val+2));
2177 break;
2178
2179 case V_028714_SPI_SHADER_SNORM16_ABGR:
2180 for (chan = 0; chan < 4; chan++) {
2181 /* Clamp between [-1, 1]. */
2182 val[chan] = lp_build_emit_llvm_binary(&ctx->bld_base, TGSI_OPCODE_MIN,
2183 values[chan],
2184 LLVMConstReal(ctx->f32, 1));
2185 val[chan] = lp_build_emit_llvm_binary(&ctx->bld_base, TGSI_OPCODE_MAX,
2186 val[chan],
2187 LLVMConstReal(ctx->f32, -1));
2188 /* Convert to a signed integer in [-32767, 32767]. */
2189 val[chan] = LLVMBuildFMul(builder, val[chan],
2190 LLVMConstReal(ctx->f32, 32767), "");
2191 /* If positive, add 0.5, else add -0.5. */
2192 val[chan] = LLVMBuildFAdd(builder, val[chan],
2193 LLVMBuildSelect(builder,
2194 LLVMBuildFCmp(builder, LLVMRealOGE,
2195 val[chan], ctx->ac.f32_0, ""),
2196 LLVMConstReal(ctx->f32, 0.5),
2197 LLVMConstReal(ctx->f32, -0.5), ""), "");
2198 val[chan] = LLVMBuildFPToSI(builder, val[chan], ctx->i32, "");
2199 }
2200
2201 args->compr = 1; /* COMPR flag */
2202 args->out[0] = ac_to_float(&ctx->ac, si_llvm_pack_two_int32_as_int16(ctx, val));
2203 args->out[1] = ac_to_float(&ctx->ac, si_llvm_pack_two_int32_as_int16(ctx, val+2));
2204 break;
2205
2206 case V_028714_SPI_SHADER_UINT16_ABGR: {
2207 LLVMValueRef max_rgb = LLVMConstInt(ctx->i32,
2208 is_int8 ? 255 : is_int10 ? 1023 : 65535, 0);
2209 LLVMValueRef max_alpha =
2210 !is_int10 ? max_rgb : LLVMConstInt(ctx->i32, 3, 0);
2211
2212 /* Clamp. */
2213 for (chan = 0; chan < 4; chan++) {
2214 val[chan] = ac_to_integer(&ctx->ac, values[chan]);
2215 val[chan] = lp_build_emit_llvm_binary(&ctx->bld_base, TGSI_OPCODE_UMIN,
2216 val[chan],
2217 chan == 3 ? max_alpha : max_rgb);
2218 }
2219
2220 args->compr = 1; /* COMPR flag */
2221 args->out[0] = ac_to_float(&ctx->ac, si_llvm_pack_two_int16(ctx, val));
2222 args->out[1] = ac_to_float(&ctx->ac, si_llvm_pack_two_int16(ctx, val+2));
2223 break;
2224 }
2225
2226 case V_028714_SPI_SHADER_SINT16_ABGR: {
2227 LLVMValueRef max_rgb = LLVMConstInt(ctx->i32,
2228 is_int8 ? 127 : is_int10 ? 511 : 32767, 0);
2229 LLVMValueRef min_rgb = LLVMConstInt(ctx->i32,
2230 is_int8 ? -128 : is_int10 ? -512 : -32768, 0);
2231 LLVMValueRef max_alpha =
2232 !is_int10 ? max_rgb : ctx->i32_1;
2233 LLVMValueRef min_alpha =
2234 !is_int10 ? min_rgb : LLVMConstInt(ctx->i32, -2, 0);
2235
2236 /* Clamp. */
2237 for (chan = 0; chan < 4; chan++) {
2238 val[chan] = ac_to_integer(&ctx->ac, values[chan]);
2239 val[chan] = lp_build_emit_llvm_binary(&ctx->bld_base,
2240 TGSI_OPCODE_IMIN,
2241 val[chan], chan == 3 ? max_alpha : max_rgb);
2242 val[chan] = lp_build_emit_llvm_binary(&ctx->bld_base,
2243 TGSI_OPCODE_IMAX,
2244 val[chan], chan == 3 ? min_alpha : min_rgb);
2245 }
2246
2247 args->compr = 1; /* COMPR flag */
2248 args->out[0] = ac_to_float(&ctx->ac, si_llvm_pack_two_int32_as_int16(ctx, val));
2249 args->out[1] = ac_to_float(&ctx->ac, si_llvm_pack_two_int32_as_int16(ctx, val+2));
2250 break;
2251 }
2252
2253 case V_028714_SPI_SHADER_32_ABGR:
2254 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
2255 break;
2256 }
2257 }
2258
2259 static void si_alpha_test(struct lp_build_tgsi_context *bld_base,
2260 LLVMValueRef alpha)
2261 {
2262 struct si_shader_context *ctx = si_shader_context(bld_base);
2263
2264 if (ctx->shader->key.part.ps.epilog.alpha_func != PIPE_FUNC_NEVER) {
2265 static LLVMRealPredicate cond_map[PIPE_FUNC_ALWAYS + 1] = {
2266 [PIPE_FUNC_LESS] = LLVMRealOLT,
2267 [PIPE_FUNC_EQUAL] = LLVMRealOEQ,
2268 [PIPE_FUNC_LEQUAL] = LLVMRealOLE,
2269 [PIPE_FUNC_GREATER] = LLVMRealOGT,
2270 [PIPE_FUNC_NOTEQUAL] = LLVMRealONE,
2271 [PIPE_FUNC_GEQUAL] = LLVMRealOGE,
2272 };
2273 LLVMRealPredicate cond = cond_map[ctx->shader->key.part.ps.epilog.alpha_func];
2274 assert(cond);
2275
2276 LLVMValueRef alpha_ref = LLVMGetParam(ctx->main_fn,
2277 SI_PARAM_ALPHA_REF);
2278 LLVMValueRef alpha_pass =
2279 LLVMBuildFCmp(ctx->ac.builder, cond, alpha, alpha_ref, "");
2280 ac_build_kill_if_false(&ctx->ac, alpha_pass);
2281 } else {
2282 ac_build_kill_if_false(&ctx->ac, LLVMConstInt(ctx->i1, 0, 0));
2283 }
2284 }
2285
2286 static LLVMValueRef si_scale_alpha_by_sample_mask(struct lp_build_tgsi_context *bld_base,
2287 LLVMValueRef alpha,
2288 unsigned samplemask_param)
2289 {
2290 struct si_shader_context *ctx = si_shader_context(bld_base);
2291 LLVMValueRef coverage;
2292
2293 /* alpha = alpha * popcount(coverage) / SI_NUM_SMOOTH_AA_SAMPLES */
2294 coverage = LLVMGetParam(ctx->main_fn,
2295 samplemask_param);
2296 coverage = ac_to_integer(&ctx->ac, coverage);
2297
2298 coverage = lp_build_intrinsic(ctx->ac.builder, "llvm.ctpop.i32",
2299 ctx->i32,
2300 &coverage, 1, LP_FUNC_ATTR_READNONE);
2301
2302 coverage = LLVMBuildUIToFP(ctx->ac.builder, coverage,
2303 ctx->f32, "");
2304
2305 coverage = LLVMBuildFMul(ctx->ac.builder, coverage,
2306 LLVMConstReal(ctx->f32,
2307 1.0 / SI_NUM_SMOOTH_AA_SAMPLES), "");
2308
2309 return LLVMBuildFMul(ctx->ac.builder, alpha, coverage, "");
2310 }
2311
2312 static void si_llvm_emit_clipvertex(struct si_shader_context *ctx,
2313 struct ac_export_args *pos, LLVMValueRef *out_elts)
2314 {
2315 unsigned reg_index;
2316 unsigned chan;
2317 unsigned const_chan;
2318 LLVMValueRef base_elt;
2319 LLVMValueRef ptr = LLVMGetParam(ctx->main_fn, ctx->param_rw_buffers);
2320 LLVMValueRef constbuf_index = LLVMConstInt(ctx->i32,
2321 SI_VS_CONST_CLIP_PLANES, 0);
2322 LLVMValueRef const_resource = ac_build_load_to_sgpr(&ctx->ac, ptr, constbuf_index);
2323
2324 for (reg_index = 0; reg_index < 2; reg_index ++) {
2325 struct ac_export_args *args = &pos[2 + reg_index];
2326
2327 args->out[0] =
2328 args->out[1] =
2329 args->out[2] =
2330 args->out[3] = LLVMConstReal(ctx->f32, 0.0f);
2331
2332 /* Compute dot products of position and user clip plane vectors */
2333 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2334 for (const_chan = 0; const_chan < TGSI_NUM_CHANNELS; const_chan++) {
2335 LLVMValueRef addr =
2336 LLVMConstInt(ctx->i32, ((reg_index * 4 + chan) * 4 +
2337 const_chan) * 4, 0);
2338 base_elt = buffer_load_const(ctx, const_resource,
2339 addr);
2340 args->out[chan] =
2341 lp_build_add(&ctx->bld_base.base, args->out[chan],
2342 lp_build_mul(&ctx->bld_base.base, base_elt,
2343 out_elts[const_chan]));
2344 }
2345 }
2346
2347 args->enabled_channels = 0xf;
2348 args->valid_mask = 0;
2349 args->done = 0;
2350 args->target = V_008DFC_SQ_EXP_POS + 2 + reg_index;
2351 args->compr = 0;
2352 }
2353 }
2354
2355 static void si_dump_streamout(struct pipe_stream_output_info *so)
2356 {
2357 unsigned i;
2358
2359 if (so->num_outputs)
2360 fprintf(stderr, "STREAMOUT\n");
2361
2362 for (i = 0; i < so->num_outputs; i++) {
2363 unsigned mask = ((1 << so->output[i].num_components) - 1) <<
2364 so->output[i].start_component;
2365 fprintf(stderr, " %i: BUF%i[%i..%i] <- OUT[%i].%s%s%s%s\n",
2366 i, so->output[i].output_buffer,
2367 so->output[i].dst_offset, so->output[i].dst_offset + so->output[i].num_components - 1,
2368 so->output[i].register_index,
2369 mask & 1 ? "x" : "",
2370 mask & 2 ? "y" : "",
2371 mask & 4 ? "z" : "",
2372 mask & 8 ? "w" : "");
2373 }
2374 }
2375
2376 static void emit_streamout_output(struct si_shader_context *ctx,
2377 LLVMValueRef const *so_buffers,
2378 LLVMValueRef const *so_write_offsets,
2379 struct pipe_stream_output *stream_out,
2380 struct si_shader_output_values *shader_out)
2381 {
2382 unsigned buf_idx = stream_out->output_buffer;
2383 unsigned start = stream_out->start_component;
2384 unsigned num_comps = stream_out->num_components;
2385 LLVMValueRef out[4];
2386
2387 assert(num_comps && num_comps <= 4);
2388 if (!num_comps || num_comps > 4)
2389 return;
2390
2391 /* Load the output as int. */
2392 for (int j = 0; j < num_comps; j++) {
2393 assert(stream_out->stream == shader_out->vertex_stream[start + j]);
2394
2395 out[j] = ac_to_integer(&ctx->ac, shader_out->values[start + j]);
2396 }
2397
2398 /* Pack the output. */
2399 LLVMValueRef vdata = NULL;
2400
2401 switch (num_comps) {
2402 case 1: /* as i32 */
2403 vdata = out[0];
2404 break;
2405 case 2: /* as v2i32 */
2406 case 3: /* as v4i32 (aligned to 4) */
2407 case 4: /* as v4i32 */
2408 vdata = LLVMGetUndef(LLVMVectorType(ctx->i32, util_next_power_of_two(num_comps)));
2409 for (int j = 0; j < num_comps; j++) {
2410 vdata = LLVMBuildInsertElement(ctx->ac.builder, vdata, out[j],
2411 LLVMConstInt(ctx->i32, j, 0), "");
2412 }
2413 break;
2414 }
2415
2416 ac_build_buffer_store_dword(&ctx->ac, so_buffers[buf_idx],
2417 vdata, num_comps,
2418 so_write_offsets[buf_idx],
2419 ctx->i32_0,
2420 stream_out->dst_offset * 4, 1, 1, true, false);
2421 }
2422
2423 /**
2424 * Write streamout data to buffers for vertex stream @p stream (different
2425 * vertex streams can occur for GS copy shaders).
2426 */
2427 static void si_llvm_emit_streamout(struct si_shader_context *ctx,
2428 struct si_shader_output_values *outputs,
2429 unsigned noutput, unsigned stream)
2430 {
2431 struct si_shader_selector *sel = ctx->shader->selector;
2432 struct pipe_stream_output_info *so = &sel->so;
2433 LLVMBuilderRef builder = ctx->ac.builder;
2434 int i;
2435 struct lp_build_if_state if_ctx;
2436
2437 /* Get bits [22:16], i.e. (so_param >> 16) & 127; */
2438 LLVMValueRef so_vtx_count =
2439 unpack_param(ctx, ctx->param_streamout_config, 16, 7);
2440
2441 LLVMValueRef tid = ac_get_thread_id(&ctx->ac);
2442
2443 /* can_emit = tid < so_vtx_count; */
2444 LLVMValueRef can_emit =
2445 LLVMBuildICmp(builder, LLVMIntULT, tid, so_vtx_count, "");
2446
2447 /* Emit the streamout code conditionally. This actually avoids
2448 * out-of-bounds buffer access. The hw tells us via the SGPR
2449 * (so_vtx_count) which threads are allowed to emit streamout data. */
2450 lp_build_if(&if_ctx, &ctx->gallivm, can_emit);
2451 {
2452 /* The buffer offset is computed as follows:
2453 * ByteOffset = streamout_offset[buffer_id]*4 +
2454 * (streamout_write_index + thread_id)*stride[buffer_id] +
2455 * attrib_offset
2456 */
2457
2458 LLVMValueRef so_write_index =
2459 LLVMGetParam(ctx->main_fn,
2460 ctx->param_streamout_write_index);
2461
2462 /* Compute (streamout_write_index + thread_id). */
2463 so_write_index = LLVMBuildAdd(builder, so_write_index, tid, "");
2464
2465 /* Load the descriptor and compute the write offset for each
2466 * enabled buffer. */
2467 LLVMValueRef so_write_offset[4] = {};
2468 LLVMValueRef so_buffers[4];
2469 LLVMValueRef buf_ptr = LLVMGetParam(ctx->main_fn,
2470 ctx->param_rw_buffers);
2471
2472 for (i = 0; i < 4; i++) {
2473 if (!so->stride[i])
2474 continue;
2475
2476 LLVMValueRef offset = LLVMConstInt(ctx->i32,
2477 SI_VS_STREAMOUT_BUF0 + i, 0);
2478
2479 so_buffers[i] = ac_build_load_to_sgpr(&ctx->ac, buf_ptr, offset);
2480
2481 LLVMValueRef so_offset = LLVMGetParam(ctx->main_fn,
2482 ctx->param_streamout_offset[i]);
2483 so_offset = LLVMBuildMul(builder, so_offset, LLVMConstInt(ctx->i32, 4, 0), "");
2484
2485 so_write_offset[i] = LLVMBuildMul(builder, so_write_index,
2486 LLVMConstInt(ctx->i32, so->stride[i]*4, 0), "");
2487 so_write_offset[i] = LLVMBuildAdd(builder, so_write_offset[i], so_offset, "");
2488 }
2489
2490 /* Write streamout data. */
2491 for (i = 0; i < so->num_outputs; i++) {
2492 unsigned reg = so->output[i].register_index;
2493
2494 if (reg >= noutput)
2495 continue;
2496
2497 if (stream != so->output[i].stream)
2498 continue;
2499
2500 emit_streamout_output(ctx, so_buffers, so_write_offset,
2501 &so->output[i], &outputs[reg]);
2502 }
2503 }
2504 lp_build_endif(&if_ctx);
2505 }
2506
2507 static void si_export_param(struct si_shader_context *ctx, unsigned index,
2508 LLVMValueRef *values)
2509 {
2510 struct ac_export_args args;
2511
2512 si_llvm_init_export_args(ctx, values,
2513 V_008DFC_SQ_EXP_PARAM + index, &args);
2514 ac_build_export(&ctx->ac, &args);
2515 }
2516
2517 static void si_build_param_exports(struct si_shader_context *ctx,
2518 struct si_shader_output_values *outputs,
2519 unsigned noutput)
2520 {
2521 struct si_shader *shader = ctx->shader;
2522 unsigned param_count = 0;
2523
2524 for (unsigned i = 0; i < noutput; i++) {
2525 unsigned semantic_name = outputs[i].semantic_name;
2526 unsigned semantic_index = outputs[i].semantic_index;
2527
2528 if (outputs[i].vertex_stream[0] != 0 &&
2529 outputs[i].vertex_stream[1] != 0 &&
2530 outputs[i].vertex_stream[2] != 0 &&
2531 outputs[i].vertex_stream[3] != 0)
2532 continue;
2533
2534 switch (semantic_name) {
2535 case TGSI_SEMANTIC_LAYER:
2536 case TGSI_SEMANTIC_VIEWPORT_INDEX:
2537 case TGSI_SEMANTIC_CLIPDIST:
2538 case TGSI_SEMANTIC_COLOR:
2539 case TGSI_SEMANTIC_BCOLOR:
2540 case TGSI_SEMANTIC_PRIMID:
2541 case TGSI_SEMANTIC_FOG:
2542 case TGSI_SEMANTIC_TEXCOORD:
2543 case TGSI_SEMANTIC_GENERIC:
2544 break;
2545 default:
2546 continue;
2547 }
2548
2549 if ((semantic_name != TGSI_SEMANTIC_GENERIC ||
2550 semantic_index < SI_MAX_IO_GENERIC) &&
2551 shader->key.opt.kill_outputs &
2552 (1ull << si_shader_io_get_unique_index(semantic_name, semantic_index)))
2553 continue;
2554
2555 si_export_param(ctx, param_count, outputs[i].values);
2556
2557 assert(i < ARRAY_SIZE(shader->info.vs_output_param_offset));
2558 shader->info.vs_output_param_offset[i] = param_count++;
2559 }
2560
2561 shader->info.nr_param_exports = param_count;
2562 }
2563
2564 /* Generate export instructions for hardware VS shader stage */
2565 static void si_llvm_export_vs(struct si_shader_context *ctx,
2566 struct si_shader_output_values *outputs,
2567 unsigned noutput)
2568 {
2569 struct si_shader *shader = ctx->shader;
2570 struct ac_export_args pos_args[4] = {};
2571 LLVMValueRef psize_value = NULL, edgeflag_value = NULL, layer_value = NULL, viewport_index_value = NULL;
2572 unsigned pos_idx;
2573 int i;
2574
2575 /* Build position exports. */
2576 for (i = 0; i < noutput; i++) {
2577 switch (outputs[i].semantic_name) {
2578 case TGSI_SEMANTIC_POSITION:
2579 si_llvm_init_export_args(ctx, outputs[i].values,
2580 V_008DFC_SQ_EXP_POS, &pos_args[0]);
2581 break;
2582 case TGSI_SEMANTIC_PSIZE:
2583 psize_value = outputs[i].values[0];
2584 break;
2585 case TGSI_SEMANTIC_LAYER:
2586 layer_value = outputs[i].values[0];
2587 break;
2588 case TGSI_SEMANTIC_VIEWPORT_INDEX:
2589 viewport_index_value = outputs[i].values[0];
2590 break;
2591 case TGSI_SEMANTIC_EDGEFLAG:
2592 edgeflag_value = outputs[i].values[0];
2593 break;
2594 case TGSI_SEMANTIC_CLIPDIST:
2595 if (!shader->key.opt.clip_disable) {
2596 unsigned index = 2 + outputs[i].semantic_index;
2597 si_llvm_init_export_args(ctx, outputs[i].values,
2598 V_008DFC_SQ_EXP_POS + index,
2599 &pos_args[index]);
2600 }
2601 break;
2602 case TGSI_SEMANTIC_CLIPVERTEX:
2603 if (!shader->key.opt.clip_disable) {
2604 si_llvm_emit_clipvertex(ctx, pos_args,
2605 outputs[i].values);
2606 }
2607 break;
2608 }
2609 }
2610
2611 /* We need to add the position output manually if it's missing. */
2612 if (!pos_args[0].out[0]) {
2613 pos_args[0].enabled_channels = 0xf; /* writemask */
2614 pos_args[0].valid_mask = 0; /* EXEC mask */
2615 pos_args[0].done = 0; /* last export? */
2616 pos_args[0].target = V_008DFC_SQ_EXP_POS;
2617 pos_args[0].compr = 0; /* COMPR flag */
2618 pos_args[0].out[0] = ctx->ac.f32_0; /* X */
2619 pos_args[0].out[1] = ctx->ac.f32_0; /* Y */
2620 pos_args[0].out[2] = ctx->ac.f32_0; /* Z */
2621 pos_args[0].out[3] = ctx->ac.f32_1; /* W */
2622 }
2623
2624 /* Write the misc vector (point size, edgeflag, layer, viewport). */
2625 if (shader->selector->info.writes_psize ||
2626 shader->selector->info.writes_edgeflag ||
2627 shader->selector->info.writes_viewport_index ||
2628 shader->selector->info.writes_layer) {
2629 pos_args[1].enabled_channels = shader->selector->info.writes_psize |
2630 (shader->selector->info.writes_edgeflag << 1) |
2631 (shader->selector->info.writes_layer << 2);
2632
2633 pos_args[1].valid_mask = 0; /* EXEC mask */
2634 pos_args[1].done = 0; /* last export? */
2635 pos_args[1].target = V_008DFC_SQ_EXP_POS + 1;
2636 pos_args[1].compr = 0; /* COMPR flag */
2637 pos_args[1].out[0] = ctx->ac.f32_0; /* X */
2638 pos_args[1].out[1] = ctx->ac.f32_0; /* Y */
2639 pos_args[1].out[2] = ctx->ac.f32_0; /* Z */
2640 pos_args[1].out[3] = ctx->ac.f32_0; /* W */
2641
2642 if (shader->selector->info.writes_psize)
2643 pos_args[1].out[0] = psize_value;
2644
2645 if (shader->selector->info.writes_edgeflag) {
2646 /* The output is a float, but the hw expects an integer
2647 * with the first bit containing the edge flag. */
2648 edgeflag_value = LLVMBuildFPToUI(ctx->ac.builder,
2649 edgeflag_value,
2650 ctx->i32, "");
2651 edgeflag_value = ac_build_umin(&ctx->ac,
2652 edgeflag_value,
2653 ctx->i32_1);
2654
2655 /* The LLVM intrinsic expects a float. */
2656 pos_args[1].out[1] = ac_to_float(&ctx->ac, edgeflag_value);
2657 }
2658
2659 if (ctx->screen->info.chip_class >= GFX9) {
2660 /* GFX9 has the layer in out.z[10:0] and the viewport
2661 * index in out.z[19:16].
2662 */
2663 if (shader->selector->info.writes_layer)
2664 pos_args[1].out[2] = layer_value;
2665
2666 if (shader->selector->info.writes_viewport_index) {
2667 LLVMValueRef v = viewport_index_value;
2668
2669 v = ac_to_integer(&ctx->ac, v);
2670 v = LLVMBuildShl(ctx->ac.builder, v,
2671 LLVMConstInt(ctx->i32, 16, 0), "");
2672 v = LLVMBuildOr(ctx->ac.builder, v,
2673 ac_to_integer(&ctx->ac, pos_args[1].out[2]), "");
2674 pos_args[1].out[2] = ac_to_float(&ctx->ac, v);
2675 pos_args[1].enabled_channels |= 1 << 2;
2676 }
2677 } else {
2678 if (shader->selector->info.writes_layer)
2679 pos_args[1].out[2] = layer_value;
2680
2681 if (shader->selector->info.writes_viewport_index) {
2682 pos_args[1].out[3] = viewport_index_value;
2683 pos_args[1].enabled_channels |= 1 << 3;
2684 }
2685 }
2686 }
2687
2688 for (i = 0; i < 4; i++)
2689 if (pos_args[i].out[0])
2690 shader->info.nr_pos_exports++;
2691
2692 pos_idx = 0;
2693 for (i = 0; i < 4; i++) {
2694 if (!pos_args[i].out[0])
2695 continue;
2696
2697 /* Specify the target we are exporting */
2698 pos_args[i].target = V_008DFC_SQ_EXP_POS + pos_idx++;
2699
2700 if (pos_idx == shader->info.nr_pos_exports)
2701 /* Specify that this is the last export */
2702 pos_args[i].done = 1;
2703
2704 ac_build_export(&ctx->ac, &pos_args[i]);
2705 }
2706
2707 /* Build parameter exports. */
2708 si_build_param_exports(ctx, outputs, noutput);
2709 }
2710
2711 /**
2712 * Forward all outputs from the vertex shader to the TES. This is only used
2713 * for the fixed function TCS.
2714 */
2715 static void si_copy_tcs_inputs(struct lp_build_tgsi_context *bld_base)
2716 {
2717 struct si_shader_context *ctx = si_shader_context(bld_base);
2718 LLVMValueRef invocation_id, buffer, buffer_offset;
2719 LLVMValueRef lds_vertex_stride, lds_vertex_offset, lds_base;
2720 uint64_t inputs;
2721
2722 invocation_id = unpack_param(ctx, ctx->param_tcs_rel_ids, 8, 5);
2723 buffer = desc_from_addr_base64k(ctx, ctx->param_tcs_offchip_addr_base64k);
2724 buffer_offset = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
2725
2726 lds_vertex_stride = get_tcs_in_vertex_dw_stride(ctx);
2727 lds_vertex_offset = LLVMBuildMul(ctx->ac.builder, invocation_id,
2728 lds_vertex_stride, "");
2729 lds_base = get_tcs_in_current_patch_offset(ctx);
2730 lds_base = LLVMBuildAdd(ctx->ac.builder, lds_base, lds_vertex_offset, "");
2731
2732 inputs = ctx->shader->key.mono.u.ff_tcs_inputs_to_copy;
2733 while (inputs) {
2734 unsigned i = u_bit_scan64(&inputs);
2735
2736 LLVMValueRef lds_ptr = LLVMBuildAdd(ctx->ac.builder, lds_base,
2737 LLVMConstInt(ctx->i32, 4 * i, 0),
2738 "");
2739
2740 LLVMValueRef buffer_addr = get_tcs_tes_buffer_address(ctx,
2741 get_rel_patch_id(ctx),
2742 invocation_id,
2743 LLVMConstInt(ctx->i32, i, 0));
2744
2745 LLVMValueRef value = lds_load(bld_base, TGSI_TYPE_SIGNED, ~0,
2746 lds_ptr);
2747
2748 ac_build_buffer_store_dword(&ctx->ac, buffer, value, 4, buffer_addr,
2749 buffer_offset, 0, 1, 0, true, false);
2750 }
2751 }
2752
2753 static void si_write_tess_factors(struct lp_build_tgsi_context *bld_base,
2754 LLVMValueRef rel_patch_id,
2755 LLVMValueRef invocation_id,
2756 LLVMValueRef tcs_out_current_patch_data_offset,
2757 LLVMValueRef invoc0_tf_outer[4],
2758 LLVMValueRef invoc0_tf_inner[2])
2759 {
2760 struct si_shader_context *ctx = si_shader_context(bld_base);
2761 struct si_shader *shader = ctx->shader;
2762 unsigned tess_inner_index, tess_outer_index;
2763 LLVMValueRef lds_base, lds_inner, lds_outer, byteoffset, buffer;
2764 LLVMValueRef out[6], vec0, vec1, tf_base, inner[4], outer[4];
2765 unsigned stride, outer_comps, inner_comps, i, offset;
2766 struct lp_build_if_state if_ctx, inner_if_ctx;
2767
2768 /* Add a barrier before loading tess factors from LDS. */
2769 if (!shader->key.part.tcs.epilog.invoc0_tess_factors_are_def)
2770 si_llvm_emit_barrier(NULL, bld_base, NULL);
2771
2772 /* Do this only for invocation 0, because the tess levels are per-patch,
2773 * not per-vertex.
2774 *
2775 * This can't jump, because invocation 0 executes this. It should
2776 * at least mask out the loads and stores for other invocations.
2777 */
2778 lp_build_if(&if_ctx, &ctx->gallivm,
2779 LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
2780 invocation_id, ctx->i32_0, ""));
2781
2782 /* Determine the layout of one tess factor element in the buffer. */
2783 switch (shader->key.part.tcs.epilog.prim_mode) {
2784 case PIPE_PRIM_LINES:
2785 stride = 2; /* 2 dwords, 1 vec2 store */
2786 outer_comps = 2;
2787 inner_comps = 0;
2788 break;
2789 case PIPE_PRIM_TRIANGLES:
2790 stride = 4; /* 4 dwords, 1 vec4 store */
2791 outer_comps = 3;
2792 inner_comps = 1;
2793 break;
2794 case PIPE_PRIM_QUADS:
2795 stride = 6; /* 6 dwords, 2 stores (vec4 + vec2) */
2796 outer_comps = 4;
2797 inner_comps = 2;
2798 break;
2799 default:
2800 assert(0);
2801 return;
2802 }
2803
2804 for (i = 0; i < 4; i++) {
2805 inner[i] = LLVMGetUndef(ctx->i32);
2806 outer[i] = LLVMGetUndef(ctx->i32);
2807 }
2808
2809 if (shader->key.part.tcs.epilog.invoc0_tess_factors_are_def) {
2810 /* Tess factors are in VGPRs. */
2811 for (i = 0; i < outer_comps; i++)
2812 outer[i] = out[i] = invoc0_tf_outer[i];
2813 for (i = 0; i < inner_comps; i++)
2814 inner[i] = out[outer_comps+i] = invoc0_tf_inner[i];
2815 } else {
2816 /* Load tess_inner and tess_outer from LDS.
2817 * Any invocation can write them, so we can't get them from a temporary.
2818 */
2819 tess_inner_index = si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSINNER, 0);
2820 tess_outer_index = si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSOUTER, 0);
2821
2822 lds_base = tcs_out_current_patch_data_offset;
2823 lds_inner = LLVMBuildAdd(ctx->ac.builder, lds_base,
2824 LLVMConstInt(ctx->i32,
2825 tess_inner_index * 4, 0), "");
2826 lds_outer = LLVMBuildAdd(ctx->ac.builder, lds_base,
2827 LLVMConstInt(ctx->i32,
2828 tess_outer_index * 4, 0), "");
2829
2830 for (i = 0; i < outer_comps; i++) {
2831 outer[i] = out[i] =
2832 lds_load(bld_base, TGSI_TYPE_SIGNED, i, lds_outer);
2833 }
2834 for (i = 0; i < inner_comps; i++) {
2835 inner[i] = out[outer_comps+i] =
2836 lds_load(bld_base, TGSI_TYPE_SIGNED, i, lds_inner);
2837 }
2838 }
2839
2840 if (shader->key.part.tcs.epilog.prim_mode == PIPE_PRIM_LINES) {
2841 /* For isolines, the hardware expects tess factors in the
2842 * reverse order from what GLSL / TGSI specify.
2843 */
2844 LLVMValueRef tmp = out[0];
2845 out[0] = out[1];
2846 out[1] = tmp;
2847 }
2848
2849 /* Convert the outputs to vectors for stores. */
2850 vec0 = lp_build_gather_values(&ctx->gallivm, out, MIN2(stride, 4));
2851 vec1 = NULL;
2852
2853 if (stride > 4)
2854 vec1 = lp_build_gather_values(&ctx->gallivm, out+4, stride - 4);
2855
2856 /* Get the buffer. */
2857 buffer = desc_from_addr_base64k(ctx, ctx->param_tcs_factor_addr_base64k);
2858
2859 /* Get the offset. */
2860 tf_base = LLVMGetParam(ctx->main_fn,
2861 ctx->param_tcs_factor_offset);
2862 byteoffset = LLVMBuildMul(ctx->ac.builder, rel_patch_id,
2863 LLVMConstInt(ctx->i32, 4 * stride, 0), "");
2864
2865 lp_build_if(&inner_if_ctx, &ctx->gallivm,
2866 LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
2867 rel_patch_id, ctx->i32_0, ""));
2868
2869 /* Store the dynamic HS control word. */
2870 offset = 0;
2871 if (ctx->screen->info.chip_class <= VI) {
2872 ac_build_buffer_store_dword(&ctx->ac, buffer,
2873 LLVMConstInt(ctx->i32, 0x80000000, 0),
2874 1, ctx->i32_0, tf_base,
2875 offset, 1, 0, true, false);
2876 offset += 4;
2877 }
2878
2879 lp_build_endif(&inner_if_ctx);
2880
2881 /* Store the tessellation factors. */
2882 ac_build_buffer_store_dword(&ctx->ac, buffer, vec0,
2883 MIN2(stride, 4), byteoffset, tf_base,
2884 offset, 1, 0, true, false);
2885 offset += 16;
2886 if (vec1)
2887 ac_build_buffer_store_dword(&ctx->ac, buffer, vec1,
2888 stride - 4, byteoffset, tf_base,
2889 offset, 1, 0, true, false);
2890
2891 /* Store the tess factors into the offchip buffer if TES reads them. */
2892 if (shader->key.part.tcs.epilog.tes_reads_tess_factors) {
2893 LLVMValueRef buf, base, inner_vec, outer_vec, tf_outer_offset;
2894 LLVMValueRef tf_inner_offset;
2895 unsigned param_outer, param_inner;
2896
2897 buf = desc_from_addr_base64k(ctx, ctx->param_tcs_offchip_addr_base64k);
2898 base = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
2899
2900 param_outer = si_shader_io_get_unique_index_patch(
2901 TGSI_SEMANTIC_TESSOUTER, 0);
2902 tf_outer_offset = get_tcs_tes_buffer_address(ctx, rel_patch_id, NULL,
2903 LLVMConstInt(ctx->i32, param_outer, 0));
2904
2905 outer_vec = lp_build_gather_values(&ctx->gallivm, outer,
2906 util_next_power_of_two(outer_comps));
2907
2908 ac_build_buffer_store_dword(&ctx->ac, buf, outer_vec,
2909 outer_comps, tf_outer_offset,
2910 base, 0, 1, 0, true, false);
2911 if (inner_comps) {
2912 param_inner = si_shader_io_get_unique_index_patch(
2913 TGSI_SEMANTIC_TESSINNER, 0);
2914 tf_inner_offset = get_tcs_tes_buffer_address(ctx, rel_patch_id, NULL,
2915 LLVMConstInt(ctx->i32, param_inner, 0));
2916
2917 inner_vec = inner_comps == 1 ? inner[0] :
2918 lp_build_gather_values(&ctx->gallivm, inner, inner_comps);
2919 ac_build_buffer_store_dword(&ctx->ac, buf, inner_vec,
2920 inner_comps, tf_inner_offset,
2921 base, 0, 1, 0, true, false);
2922 }
2923 }
2924
2925 lp_build_endif(&if_ctx);
2926 }
2927
2928 static LLVMValueRef
2929 si_insert_input_ret(struct si_shader_context *ctx, LLVMValueRef ret,
2930 unsigned param, unsigned return_index)
2931 {
2932 return LLVMBuildInsertValue(ctx->ac.builder, ret,
2933 LLVMGetParam(ctx->main_fn, param),
2934 return_index, "");
2935 }
2936
2937 static LLVMValueRef
2938 si_insert_input_ret_float(struct si_shader_context *ctx, LLVMValueRef ret,
2939 unsigned param, unsigned return_index)
2940 {
2941 LLVMBuilderRef builder = ctx->ac.builder;
2942 LLVMValueRef p = LLVMGetParam(ctx->main_fn, param);
2943
2944 return LLVMBuildInsertValue(builder, ret,
2945 ac_to_float(&ctx->ac, p),
2946 return_index, "");
2947 }
2948
2949 static LLVMValueRef
2950 si_insert_input_ptr_as_2xi32(struct si_shader_context *ctx, LLVMValueRef ret,
2951 unsigned param, unsigned return_index)
2952 {
2953 LLVMBuilderRef builder = ctx->ac.builder;
2954 LLVMValueRef ptr, lo, hi;
2955
2956 ptr = LLVMGetParam(ctx->main_fn, param);
2957 ptr = LLVMBuildPtrToInt(builder, ptr, ctx->i64, "");
2958 ptr = LLVMBuildBitCast(builder, ptr, ctx->v2i32, "");
2959 lo = LLVMBuildExtractElement(builder, ptr, ctx->i32_0, "");
2960 hi = LLVMBuildExtractElement(builder, ptr, ctx->i32_1, "");
2961 ret = LLVMBuildInsertValue(builder, ret, lo, return_index, "");
2962 return LLVMBuildInsertValue(builder, ret, hi, return_index + 1, "");
2963 }
2964
2965 /* This only writes the tessellation factor levels. */
2966 static void si_llvm_emit_tcs_epilogue(struct lp_build_tgsi_context *bld_base)
2967 {
2968 struct si_shader_context *ctx = si_shader_context(bld_base);
2969 LLVMBuilderRef builder = ctx->ac.builder;
2970 LLVMValueRef rel_patch_id, invocation_id, tf_lds_offset;
2971
2972 si_copy_tcs_inputs(bld_base);
2973
2974 rel_patch_id = get_rel_patch_id(ctx);
2975 invocation_id = unpack_param(ctx, ctx->param_tcs_rel_ids, 8, 5);
2976 tf_lds_offset = get_tcs_out_current_patch_data_offset(ctx);
2977
2978 if (ctx->screen->info.chip_class >= GFX9) {
2979 LLVMBasicBlockRef blocks[2] = {
2980 LLVMGetInsertBlock(builder),
2981 ctx->merged_wrap_if_state.entry_block
2982 };
2983 LLVMValueRef values[2];
2984
2985 lp_build_endif(&ctx->merged_wrap_if_state);
2986
2987 values[0] = rel_patch_id;
2988 values[1] = LLVMGetUndef(ctx->i32);
2989 rel_patch_id = ac_build_phi(&ctx->ac, ctx->i32, 2, values, blocks);
2990
2991 values[0] = tf_lds_offset;
2992 values[1] = LLVMGetUndef(ctx->i32);
2993 tf_lds_offset = ac_build_phi(&ctx->ac, ctx->i32, 2, values, blocks);
2994
2995 values[0] = invocation_id;
2996 values[1] = ctx->i32_1; /* cause the epilog to skip threads */
2997 invocation_id = ac_build_phi(&ctx->ac, ctx->i32, 2, values, blocks);
2998 }
2999
3000 /* Return epilog parameters from this function. */
3001 LLVMValueRef ret = ctx->return_value;
3002 unsigned vgpr;
3003
3004 if (ctx->screen->info.chip_class >= GFX9) {
3005 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_layout,
3006 8 + GFX9_SGPR_TCS_OFFCHIP_LAYOUT);
3007 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_addr_base64k,
3008 8 + GFX9_SGPR_TCS_OFFCHIP_ADDR_BASE64K);
3009 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_factor_addr_base64k,
3010 8 + GFX9_SGPR_TCS_FACTOR_ADDR_BASE64K);
3011 /* Tess offchip and tess factor offsets are at the beginning. */
3012 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_offset, 2);
3013 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_factor_offset, 4);
3014 vgpr = 8 + GFX9_SGPR_TCS_FACTOR_ADDR_BASE64K + 1;
3015 } else {
3016 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_layout,
3017 GFX6_SGPR_TCS_OFFCHIP_LAYOUT);
3018 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_addr_base64k,
3019 GFX6_SGPR_TCS_OFFCHIP_ADDR_BASE64K);
3020 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_factor_addr_base64k,
3021 GFX6_SGPR_TCS_FACTOR_ADDR_BASE64K);
3022 /* Tess offchip and tess factor offsets are after user SGPRs. */
3023 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_offset,
3024 GFX6_TCS_NUM_USER_SGPR);
3025 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_factor_offset,
3026 GFX6_TCS_NUM_USER_SGPR + 1);
3027 vgpr = GFX6_TCS_NUM_USER_SGPR + 2;
3028 }
3029
3030 /* VGPRs */
3031 rel_patch_id = ac_to_float(&ctx->ac, rel_patch_id);
3032 invocation_id = ac_to_float(&ctx->ac, invocation_id);
3033 tf_lds_offset = ac_to_float(&ctx->ac, tf_lds_offset);
3034
3035 /* Leave a hole corresponding to the two input VGPRs. This ensures that
3036 * the invocation_id output does not alias the param_tcs_rel_ids input,
3037 * which saves a V_MOV on gfx9.
3038 */
3039 vgpr += 2;
3040
3041 ret = LLVMBuildInsertValue(builder, ret, rel_patch_id, vgpr++, "");
3042 ret = LLVMBuildInsertValue(builder, ret, invocation_id, vgpr++, "");
3043
3044 if (ctx->shader->selector->tcs_info.tessfactors_are_def_in_all_invocs) {
3045 vgpr++; /* skip the tess factor LDS offset */
3046 for (unsigned i = 0; i < 6; i++) {
3047 LLVMValueRef value =
3048 LLVMBuildLoad(builder, ctx->invoc0_tess_factors[i], "");
3049 value = ac_to_float(&ctx->ac, value);
3050 ret = LLVMBuildInsertValue(builder, ret, value, vgpr++, "");
3051 }
3052 } else {
3053 ret = LLVMBuildInsertValue(builder, ret, tf_lds_offset, vgpr++, "");
3054 }
3055 ctx->return_value = ret;
3056 }
3057
3058 /* Pass TCS inputs from LS to TCS on GFX9. */
3059 static void si_set_ls_return_value_for_tcs(struct si_shader_context *ctx)
3060 {
3061 LLVMValueRef ret = ctx->return_value;
3062
3063 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_offset, 2);
3064 ret = si_insert_input_ret(ctx, ret, ctx->param_merged_wave_info, 3);
3065 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_factor_offset, 4);
3066 ret = si_insert_input_ret(ctx, ret, ctx->param_merged_scratch_offset, 5);
3067
3068 ret = si_insert_input_ptr_as_2xi32(ctx, ret, ctx->param_rw_buffers,
3069 8 + SI_SGPR_RW_BUFFERS);
3070 ret = si_insert_input_ptr_as_2xi32(ctx, ret,
3071 ctx->param_bindless_samplers_and_images,
3072 8 + SI_SGPR_BINDLESS_SAMPLERS_AND_IMAGES);
3073
3074 ret = si_insert_input_ret(ctx, ret, ctx->param_vs_state_bits,
3075 8 + SI_SGPR_VS_STATE_BITS);
3076 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_layout,
3077 8 + GFX9_SGPR_TCS_OFFCHIP_LAYOUT);
3078 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_out_lds_offsets,
3079 8 + GFX9_SGPR_TCS_OUT_OFFSETS);
3080 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_out_lds_layout,
3081 8 + GFX9_SGPR_TCS_OUT_LAYOUT);
3082 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_addr_base64k,
3083 8 + GFX9_SGPR_TCS_OFFCHIP_ADDR_BASE64K);
3084 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_factor_addr_base64k,
3085 8 + GFX9_SGPR_TCS_FACTOR_ADDR_BASE64K);
3086
3087 unsigned desc_param = ctx->param_tcs_factor_addr_base64k + 2;
3088 ret = si_insert_input_ptr_as_2xi32(ctx, ret, desc_param,
3089 8 + GFX9_SGPR_TCS_CONST_AND_SHADER_BUFFERS);
3090 ret = si_insert_input_ptr_as_2xi32(ctx, ret, desc_param + 1,
3091 8 + GFX9_SGPR_TCS_SAMPLERS_AND_IMAGES);
3092
3093 unsigned vgpr = 8 + GFX9_TCS_NUM_USER_SGPR;
3094 ret = si_insert_input_ret_float(ctx, ret,
3095 ctx->param_tcs_patch_id, vgpr++);
3096 ret = si_insert_input_ret_float(ctx, ret,
3097 ctx->param_tcs_rel_ids, vgpr++);
3098 ctx->return_value = ret;
3099 }
3100
3101 /* Pass GS inputs from ES to GS on GFX9. */
3102 static void si_set_es_return_value_for_gs(struct si_shader_context *ctx)
3103 {
3104 LLVMValueRef ret = ctx->return_value;
3105
3106 ret = si_insert_input_ret(ctx, ret, ctx->param_gs2vs_offset, 2);
3107 ret = si_insert_input_ret(ctx, ret, ctx->param_merged_wave_info, 3);
3108 ret = si_insert_input_ret(ctx, ret, ctx->param_merged_scratch_offset, 5);
3109
3110 ret = si_insert_input_ptr_as_2xi32(ctx, ret, ctx->param_rw_buffers,
3111 8 + SI_SGPR_RW_BUFFERS);
3112 ret = si_insert_input_ptr_as_2xi32(ctx, ret,
3113 ctx->param_bindless_samplers_and_images,
3114 8 + SI_SGPR_BINDLESS_SAMPLERS_AND_IMAGES);
3115
3116 unsigned desc_param = ctx->param_vs_state_bits + 1;
3117 ret = si_insert_input_ptr_as_2xi32(ctx, ret, desc_param,
3118 8 + GFX9_SGPR_GS_CONST_AND_SHADER_BUFFERS);
3119 ret = si_insert_input_ptr_as_2xi32(ctx, ret, desc_param + 1,
3120 8 + GFX9_SGPR_GS_SAMPLERS_AND_IMAGES);
3121
3122 unsigned vgpr = 8 + GFX9_GS_NUM_USER_SGPR;
3123 for (unsigned i = 0; i < 5; i++) {
3124 unsigned param = ctx->param_gs_vtx01_offset + i;
3125 ret = si_insert_input_ret_float(ctx, ret, param, vgpr++);
3126 }
3127 ctx->return_value = ret;
3128 }
3129
3130 static void si_llvm_emit_ls_epilogue(struct ac_shader_abi *abi,
3131 unsigned max_outputs,
3132 LLVMValueRef *addrs)
3133 {
3134 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
3135 struct si_shader *shader = ctx->shader;
3136 struct tgsi_shader_info *info = &shader->selector->info;
3137 unsigned i, chan;
3138 LLVMValueRef vertex_id = LLVMGetParam(ctx->main_fn,
3139 ctx->param_rel_auto_id);
3140 LLVMValueRef vertex_dw_stride = get_tcs_in_vertex_dw_stride(ctx);
3141 LLVMValueRef base_dw_addr = LLVMBuildMul(ctx->ac.builder, vertex_id,
3142 vertex_dw_stride, "");
3143
3144 /* Write outputs to LDS. The next shader (TCS aka HS) will read
3145 * its inputs from it. */
3146 for (i = 0; i < info->num_outputs; i++) {
3147 unsigned name = info->output_semantic_name[i];
3148 unsigned index = info->output_semantic_index[i];
3149
3150 /* The ARB_shader_viewport_layer_array spec contains the
3151 * following issue:
3152 *
3153 * 2) What happens if gl_ViewportIndex or gl_Layer is
3154 * written in the vertex shader and a geometry shader is
3155 * present?
3156 *
3157 * RESOLVED: The value written by the last vertex processing
3158 * stage is used. If the last vertex processing stage
3159 * (vertex, tessellation evaluation or geometry) does not
3160 * statically assign to gl_ViewportIndex or gl_Layer, index
3161 * or layer zero is assumed.
3162 *
3163 * So writes to those outputs in VS-as-LS are simply ignored.
3164 */
3165 if (name == TGSI_SEMANTIC_LAYER ||
3166 name == TGSI_SEMANTIC_VIEWPORT_INDEX)
3167 continue;
3168
3169 int param = si_shader_io_get_unique_index(name, index);
3170 LLVMValueRef dw_addr = LLVMBuildAdd(ctx->ac.builder, base_dw_addr,
3171 LLVMConstInt(ctx->i32, param * 4, 0), "");
3172
3173 for (chan = 0; chan < 4; chan++) {
3174 if (!(info->output_usagemask[i] & (1 << chan)))
3175 continue;
3176
3177 lds_store(ctx, chan, dw_addr,
3178 LLVMBuildLoad(ctx->ac.builder, addrs[4 * i + chan], ""));
3179 }
3180 }
3181
3182 if (ctx->screen->info.chip_class >= GFX9)
3183 si_set_ls_return_value_for_tcs(ctx);
3184 }
3185
3186 static void si_llvm_emit_es_epilogue(struct ac_shader_abi *abi,
3187 unsigned max_outputs,
3188 LLVMValueRef *addrs)
3189 {
3190 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
3191 struct si_shader *es = ctx->shader;
3192 struct tgsi_shader_info *info = &es->selector->info;
3193 LLVMValueRef soffset = LLVMGetParam(ctx->main_fn,
3194 ctx->param_es2gs_offset);
3195 LLVMValueRef lds_base = NULL;
3196 unsigned chan;
3197 int i;
3198
3199 if (ctx->screen->info.chip_class >= GFX9 && info->num_outputs) {
3200 unsigned itemsize_dw = es->selector->esgs_itemsize / 4;
3201 LLVMValueRef vertex_idx = ac_get_thread_id(&ctx->ac);
3202 LLVMValueRef wave_idx = unpack_param(ctx, ctx->param_merged_wave_info, 24, 4);
3203 vertex_idx = LLVMBuildOr(ctx->ac.builder, vertex_idx,
3204 LLVMBuildMul(ctx->ac.builder, wave_idx,
3205 LLVMConstInt(ctx->i32, 64, false), ""), "");
3206 lds_base = LLVMBuildMul(ctx->ac.builder, vertex_idx,
3207 LLVMConstInt(ctx->i32, itemsize_dw, 0), "");
3208 }
3209
3210 for (i = 0; i < info->num_outputs; i++) {
3211 int param;
3212
3213 if (info->output_semantic_name[i] == TGSI_SEMANTIC_VIEWPORT_INDEX ||
3214 info->output_semantic_name[i] == TGSI_SEMANTIC_LAYER)
3215 continue;
3216
3217 param = si_shader_io_get_unique_index(info->output_semantic_name[i],
3218 info->output_semantic_index[i]);
3219
3220 for (chan = 0; chan < 4; chan++) {
3221 LLVMValueRef out_val = LLVMBuildLoad(ctx->ac.builder, addrs[4 * i + chan], "");
3222 out_val = ac_to_integer(&ctx->ac, out_val);
3223
3224 /* GFX9 has the ESGS ring in LDS. */
3225 if (ctx->screen->info.chip_class >= GFX9) {
3226 lds_store(ctx, param * 4 + chan, lds_base, out_val);
3227 continue;
3228 }
3229
3230 ac_build_buffer_store_dword(&ctx->ac,
3231 ctx->esgs_ring,
3232 out_val, 1, NULL, soffset,
3233 (4 * param + chan) * 4,
3234 1, 1, true, true);
3235 }
3236 }
3237
3238 if (ctx->screen->info.chip_class >= GFX9)
3239 si_set_es_return_value_for_gs(ctx);
3240 }
3241
3242 static LLVMValueRef si_get_gs_wave_id(struct si_shader_context *ctx)
3243 {
3244 if (ctx->screen->info.chip_class >= GFX9)
3245 return unpack_param(ctx, ctx->param_merged_wave_info, 16, 8);
3246 else
3247 return LLVMGetParam(ctx->main_fn, ctx->param_gs_wave_id);
3248 }
3249
3250 static void emit_gs_epilogue(struct si_shader_context *ctx)
3251 {
3252 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_NOP | AC_SENDMSG_GS_DONE,
3253 si_get_gs_wave_id(ctx));
3254
3255 if (ctx->screen->info.chip_class >= GFX9)
3256 lp_build_endif(&ctx->merged_wrap_if_state);
3257 }
3258
3259 static void si_llvm_emit_gs_epilogue(struct ac_shader_abi *abi,
3260 unsigned max_outputs,
3261 LLVMValueRef *addrs)
3262 {
3263 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
3264 struct tgsi_shader_info UNUSED *info = &ctx->shader->selector->info;
3265
3266 assert(info->num_outputs <= max_outputs);
3267
3268 emit_gs_epilogue(ctx);
3269 }
3270
3271 static void si_tgsi_emit_gs_epilogue(struct lp_build_tgsi_context *bld_base)
3272 {
3273 struct si_shader_context *ctx = si_shader_context(bld_base);
3274 emit_gs_epilogue(ctx);
3275 }
3276
3277 static void si_llvm_emit_vs_epilogue(struct ac_shader_abi *abi,
3278 unsigned max_outputs,
3279 LLVMValueRef *addrs)
3280 {
3281 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
3282 struct tgsi_shader_info *info = &ctx->shader->selector->info;
3283 struct si_shader_output_values *outputs = NULL;
3284 int i,j;
3285
3286 assert(!ctx->shader->is_gs_copy_shader);
3287 assert(info->num_outputs <= max_outputs);
3288
3289 outputs = MALLOC((info->num_outputs + 1) * sizeof(outputs[0]));
3290
3291 /* Vertex color clamping.
3292 *
3293 * This uses a state constant loaded in a user data SGPR and
3294 * an IF statement is added that clamps all colors if the constant
3295 * is true.
3296 */
3297 if (ctx->type == PIPE_SHADER_VERTEX) {
3298 struct lp_build_if_state if_ctx;
3299 LLVMValueRef cond = NULL;
3300 LLVMValueRef addr, val;
3301
3302 for (i = 0; i < info->num_outputs; i++) {
3303 if (info->output_semantic_name[i] != TGSI_SEMANTIC_COLOR &&
3304 info->output_semantic_name[i] != TGSI_SEMANTIC_BCOLOR)
3305 continue;
3306
3307 /* We've found a color. */
3308 if (!cond) {
3309 /* The state is in the first bit of the user SGPR. */
3310 cond = LLVMGetParam(ctx->main_fn,
3311 ctx->param_vs_state_bits);
3312 cond = LLVMBuildTrunc(ctx->ac.builder, cond,
3313 ctx->i1, "");
3314 lp_build_if(&if_ctx, &ctx->gallivm, cond);
3315 }
3316
3317 for (j = 0; j < 4; j++) {
3318 addr = addrs[4 * i + j];
3319 val = LLVMBuildLoad(ctx->ac.builder, addr, "");
3320 val = ac_build_clamp(&ctx->ac, val);
3321 LLVMBuildStore(ctx->ac.builder, val, addr);
3322 }
3323 }
3324
3325 if (cond)
3326 lp_build_endif(&if_ctx);
3327 }
3328
3329 for (i = 0; i < info->num_outputs; i++) {
3330 outputs[i].semantic_name = info->output_semantic_name[i];
3331 outputs[i].semantic_index = info->output_semantic_index[i];
3332
3333 for (j = 0; j < 4; j++) {
3334 outputs[i].values[j] =
3335 LLVMBuildLoad(ctx->ac.builder,
3336 addrs[4 * i + j],
3337 "");
3338 outputs[i].vertex_stream[j] =
3339 (info->output_streams[i] >> (2 * j)) & 3;
3340 }
3341 }
3342
3343 if (ctx->shader->selector->so.num_outputs)
3344 si_llvm_emit_streamout(ctx, outputs, i, 0);
3345
3346 /* Export PrimitiveID. */
3347 if (ctx->shader->key.mono.u.vs_export_prim_id) {
3348 outputs[i].semantic_name = TGSI_SEMANTIC_PRIMID;
3349 outputs[i].semantic_index = 0;
3350 outputs[i].values[0] = ac_to_float(&ctx->ac, get_primitive_id(ctx, 0));
3351 for (j = 1; j < 4; j++)
3352 outputs[i].values[j] = LLVMConstReal(ctx->f32, 0);
3353
3354 memset(outputs[i].vertex_stream, 0,
3355 sizeof(outputs[i].vertex_stream));
3356 i++;
3357 }
3358
3359 si_llvm_export_vs(ctx, outputs, i);
3360 FREE(outputs);
3361 }
3362
3363 static void si_tgsi_emit_epilogue(struct lp_build_tgsi_context *bld_base)
3364 {
3365 struct si_shader_context *ctx = si_shader_context(bld_base);
3366
3367 ctx->abi.emit_outputs(&ctx->abi, RADEON_LLVM_MAX_OUTPUTS,
3368 &ctx->outputs[0][0]);
3369 }
3370
3371 struct si_ps_exports {
3372 unsigned num;
3373 struct ac_export_args args[10];
3374 };
3375
3376 unsigned si_get_spi_shader_z_format(bool writes_z, bool writes_stencil,
3377 bool writes_samplemask)
3378 {
3379 if (writes_z) {
3380 /* Z needs 32 bits. */
3381 if (writes_samplemask)
3382 return V_028710_SPI_SHADER_32_ABGR;
3383 else if (writes_stencil)
3384 return V_028710_SPI_SHADER_32_GR;
3385 else
3386 return V_028710_SPI_SHADER_32_R;
3387 } else if (writes_stencil || writes_samplemask) {
3388 /* Both stencil and sample mask need only 16 bits. */
3389 return V_028710_SPI_SHADER_UINT16_ABGR;
3390 } else {
3391 return V_028710_SPI_SHADER_ZERO;
3392 }
3393 }
3394
3395 static void si_export_mrt_z(struct lp_build_tgsi_context *bld_base,
3396 LLVMValueRef depth, LLVMValueRef stencil,
3397 LLVMValueRef samplemask, struct si_ps_exports *exp)
3398 {
3399 struct si_shader_context *ctx = si_shader_context(bld_base);
3400 struct lp_build_context *base = &bld_base->base;
3401 struct ac_export_args args;
3402 unsigned mask = 0;
3403 unsigned format = si_get_spi_shader_z_format(depth != NULL,
3404 stencil != NULL,
3405 samplemask != NULL);
3406
3407 assert(depth || stencil || samplemask);
3408
3409 args.valid_mask = 1; /* whether the EXEC mask is valid */
3410 args.done = 1; /* DONE bit */
3411
3412 /* Specify the target we are exporting */
3413 args.target = V_008DFC_SQ_EXP_MRTZ;
3414
3415 args.compr = 0; /* COMP flag */
3416 args.out[0] = base->undef; /* R, depth */
3417 args.out[1] = base->undef; /* G, stencil test value[0:7], stencil op value[8:15] */
3418 args.out[2] = base->undef; /* B, sample mask */
3419 args.out[3] = base->undef; /* A, alpha to mask */
3420
3421 if (format == V_028710_SPI_SHADER_UINT16_ABGR) {
3422 assert(!depth);
3423 args.compr = 1; /* COMPR flag */
3424
3425 if (stencil) {
3426 /* Stencil should be in X[23:16]. */
3427 stencil = ac_to_integer(&ctx->ac, stencil);
3428 stencil = LLVMBuildShl(ctx->ac.builder, stencil,
3429 LLVMConstInt(ctx->i32, 16, 0), "");
3430 args.out[0] = ac_to_float(&ctx->ac, stencil);
3431 mask |= 0x3;
3432 }
3433 if (samplemask) {
3434 /* SampleMask should be in Y[15:0]. */
3435 args.out[1] = samplemask;
3436 mask |= 0xc;
3437 }
3438 } else {
3439 if (depth) {
3440 args.out[0] = depth;
3441 mask |= 0x1;
3442 }
3443 if (stencil) {
3444 args.out[1] = stencil;
3445 mask |= 0x2;
3446 }
3447 if (samplemask) {
3448 args.out[2] = samplemask;
3449 mask |= 0x4;
3450 }
3451 }
3452
3453 /* SI (except OLAND and HAINAN) has a bug that it only looks
3454 * at the X writemask component. */
3455 if (ctx->screen->info.chip_class == SI &&
3456 ctx->screen->info.family != CHIP_OLAND &&
3457 ctx->screen->info.family != CHIP_HAINAN)
3458 mask |= 0x1;
3459
3460 /* Specify which components to enable */
3461 args.enabled_channels = mask;
3462
3463 memcpy(&exp->args[exp->num++], &args, sizeof(args));
3464 }
3465
3466 static void si_export_mrt_color(struct lp_build_tgsi_context *bld_base,
3467 LLVMValueRef *color, unsigned index,
3468 unsigned samplemask_param,
3469 bool is_last, struct si_ps_exports *exp)
3470 {
3471 struct si_shader_context *ctx = si_shader_context(bld_base);
3472 int i;
3473
3474 /* Clamp color */
3475 if (ctx->shader->key.part.ps.epilog.clamp_color)
3476 for (i = 0; i < 4; i++)
3477 color[i] = ac_build_clamp(&ctx->ac, color[i]);
3478
3479 /* Alpha to one */
3480 if (ctx->shader->key.part.ps.epilog.alpha_to_one)
3481 color[3] = ctx->ac.f32_1;
3482
3483 /* Alpha test */
3484 if (index == 0 &&
3485 ctx->shader->key.part.ps.epilog.alpha_func != PIPE_FUNC_ALWAYS)
3486 si_alpha_test(bld_base, color[3]);
3487
3488 /* Line & polygon smoothing */
3489 if (ctx->shader->key.part.ps.epilog.poly_line_smoothing)
3490 color[3] = si_scale_alpha_by_sample_mask(bld_base, color[3],
3491 samplemask_param);
3492
3493 /* If last_cbuf > 0, FS_COLOR0_WRITES_ALL_CBUFS is true. */
3494 if (ctx->shader->key.part.ps.epilog.last_cbuf > 0) {
3495 struct ac_export_args args[8];
3496 int c, last = -1;
3497
3498 /* Get the export arguments, also find out what the last one is. */
3499 for (c = 0; c <= ctx->shader->key.part.ps.epilog.last_cbuf; c++) {
3500 si_llvm_init_export_args(ctx, color,
3501 V_008DFC_SQ_EXP_MRT + c, &args[c]);
3502 if (args[c].enabled_channels)
3503 last = c;
3504 }
3505
3506 /* Emit all exports. */
3507 for (c = 0; c <= ctx->shader->key.part.ps.epilog.last_cbuf; c++) {
3508 if (is_last && last == c) {
3509 args[c].valid_mask = 1; /* whether the EXEC mask is valid */
3510 args[c].done = 1; /* DONE bit */
3511 } else if (!args[c].enabled_channels)
3512 continue; /* unnecessary NULL export */
3513
3514 memcpy(&exp->args[exp->num++], &args[c], sizeof(args[c]));
3515 }
3516 } else {
3517 struct ac_export_args args;
3518
3519 /* Export */
3520 si_llvm_init_export_args(ctx, color, V_008DFC_SQ_EXP_MRT + index,
3521 &args);
3522 if (is_last) {
3523 args.valid_mask = 1; /* whether the EXEC mask is valid */
3524 args.done = 1; /* DONE bit */
3525 } else if (!args.enabled_channels)
3526 return; /* unnecessary NULL export */
3527
3528 memcpy(&exp->args[exp->num++], &args, sizeof(args));
3529 }
3530 }
3531
3532 static void si_emit_ps_exports(struct si_shader_context *ctx,
3533 struct si_ps_exports *exp)
3534 {
3535 for (unsigned i = 0; i < exp->num; i++)
3536 ac_build_export(&ctx->ac, &exp->args[i]);
3537 }
3538
3539 static void si_export_null(struct lp_build_tgsi_context *bld_base)
3540 {
3541 struct si_shader_context *ctx = si_shader_context(bld_base);
3542 struct lp_build_context *base = &bld_base->base;
3543 struct ac_export_args args;
3544
3545 args.enabled_channels = 0x0; /* enabled channels */
3546 args.valid_mask = 1; /* whether the EXEC mask is valid */
3547 args.done = 1; /* DONE bit */
3548 args.target = V_008DFC_SQ_EXP_NULL;
3549 args.compr = 0; /* COMPR flag (0 = 32-bit export) */
3550 args.out[0] = base->undef; /* R */
3551 args.out[1] = base->undef; /* G */
3552 args.out[2] = base->undef; /* B */
3553 args.out[3] = base->undef; /* A */
3554
3555 ac_build_export(&ctx->ac, &args);
3556 }
3557
3558 /**
3559 * Return PS outputs in this order:
3560 *
3561 * v[0:3] = color0.xyzw
3562 * v[4:7] = color1.xyzw
3563 * ...
3564 * vN+0 = Depth
3565 * vN+1 = Stencil
3566 * vN+2 = SampleMask
3567 * vN+3 = SampleMaskIn (used for OpenGL smoothing)
3568 *
3569 * The alpha-ref SGPR is returned via its original location.
3570 */
3571 static void si_llvm_return_fs_outputs(struct ac_shader_abi *abi,
3572 unsigned max_outputs,
3573 LLVMValueRef *addrs)
3574 {
3575 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
3576 struct si_shader *shader = ctx->shader;
3577 struct tgsi_shader_info *info = &shader->selector->info;
3578 LLVMBuilderRef builder = ctx->ac.builder;
3579 unsigned i, j, first_vgpr, vgpr;
3580
3581 LLVMValueRef color[8][4] = {};
3582 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
3583 LLVMValueRef ret;
3584
3585 if (ctx->postponed_kill)
3586 ac_build_kill_if_false(&ctx->ac, LLVMBuildLoad(builder, ctx->postponed_kill, ""));
3587
3588 /* Read the output values. */
3589 for (i = 0; i < info->num_outputs; i++) {
3590 unsigned semantic_name = info->output_semantic_name[i];
3591 unsigned semantic_index = info->output_semantic_index[i];
3592
3593 switch (semantic_name) {
3594 case TGSI_SEMANTIC_COLOR:
3595 assert(semantic_index < 8);
3596 for (j = 0; j < 4; j++) {
3597 LLVMValueRef ptr = addrs[4 * i + j];
3598 LLVMValueRef result = LLVMBuildLoad(builder, ptr, "");
3599 color[semantic_index][j] = result;
3600 }
3601 break;
3602 case TGSI_SEMANTIC_POSITION:
3603 depth = LLVMBuildLoad(builder,
3604 addrs[4 * i + 2], "");
3605 break;
3606 case TGSI_SEMANTIC_STENCIL:
3607 stencil = LLVMBuildLoad(builder,
3608 addrs[4 * i + 1], "");
3609 break;
3610 case TGSI_SEMANTIC_SAMPLEMASK:
3611 samplemask = LLVMBuildLoad(builder,
3612 addrs[4 * i + 0], "");
3613 break;
3614 default:
3615 fprintf(stderr, "Warning: SI unhandled fs output type:%d\n",
3616 semantic_name);
3617 }
3618 }
3619
3620 /* Fill the return structure. */
3621 ret = ctx->return_value;
3622
3623 /* Set SGPRs. */
3624 ret = LLVMBuildInsertValue(builder, ret,
3625 ac_to_integer(&ctx->ac,
3626 LLVMGetParam(ctx->main_fn,
3627 SI_PARAM_ALPHA_REF)),
3628 SI_SGPR_ALPHA_REF, "");
3629
3630 /* Set VGPRs */
3631 first_vgpr = vgpr = SI_SGPR_ALPHA_REF + 1;
3632 for (i = 0; i < ARRAY_SIZE(color); i++) {
3633 if (!color[i][0])
3634 continue;
3635
3636 for (j = 0; j < 4; j++)
3637 ret = LLVMBuildInsertValue(builder, ret, color[i][j], vgpr++, "");
3638 }
3639 if (depth)
3640 ret = LLVMBuildInsertValue(builder, ret, depth, vgpr++, "");
3641 if (stencil)
3642 ret = LLVMBuildInsertValue(builder, ret, stencil, vgpr++, "");
3643 if (samplemask)
3644 ret = LLVMBuildInsertValue(builder, ret, samplemask, vgpr++, "");
3645
3646 /* Add the input sample mask for smoothing at the end. */
3647 if (vgpr < first_vgpr + PS_EPILOG_SAMPLEMASK_MIN_LOC)
3648 vgpr = first_vgpr + PS_EPILOG_SAMPLEMASK_MIN_LOC;
3649 ret = LLVMBuildInsertValue(builder, ret,
3650 LLVMGetParam(ctx->main_fn,
3651 SI_PARAM_SAMPLE_COVERAGE), vgpr++, "");
3652
3653 ctx->return_value = ret;
3654 }
3655
3656 void si_emit_waitcnt(struct si_shader_context *ctx, unsigned simm16)
3657 {
3658 LLVMValueRef args[1] = {
3659 LLVMConstInt(ctx->i32, simm16, 0)
3660 };
3661 lp_build_intrinsic(ctx->ac.builder, "llvm.amdgcn.s.waitcnt",
3662 ctx->voidt, args, 1, 0);
3663 }
3664
3665 static void membar_emit(
3666 const struct lp_build_tgsi_action *action,
3667 struct lp_build_tgsi_context *bld_base,
3668 struct lp_build_emit_data *emit_data)
3669 {
3670 struct si_shader_context *ctx = si_shader_context(bld_base);
3671 LLVMValueRef src0 = lp_build_emit_fetch(bld_base, emit_data->inst, 0, 0);
3672 unsigned flags = LLVMConstIntGetZExtValue(src0);
3673 unsigned waitcnt = NOOP_WAITCNT;
3674
3675 if (flags & TGSI_MEMBAR_THREAD_GROUP)
3676 waitcnt &= VM_CNT & LGKM_CNT;
3677
3678 if (flags & (TGSI_MEMBAR_ATOMIC_BUFFER |
3679 TGSI_MEMBAR_SHADER_BUFFER |
3680 TGSI_MEMBAR_SHADER_IMAGE))
3681 waitcnt &= VM_CNT;
3682
3683 if (flags & TGSI_MEMBAR_SHARED)
3684 waitcnt &= LGKM_CNT;
3685
3686 if (waitcnt != NOOP_WAITCNT)
3687 si_emit_waitcnt(ctx, waitcnt);
3688 }
3689
3690 static void clock_emit(
3691 const struct lp_build_tgsi_action *action,
3692 struct lp_build_tgsi_context *bld_base,
3693 struct lp_build_emit_data *emit_data)
3694 {
3695 struct si_shader_context *ctx = si_shader_context(bld_base);
3696 LLVMValueRef tmp;
3697
3698 tmp = lp_build_intrinsic(ctx->ac.builder, "llvm.readcyclecounter",
3699 ctx->i64, NULL, 0, 0);
3700 tmp = LLVMBuildBitCast(ctx->ac.builder, tmp, ctx->v2i32, "");
3701
3702 emit_data->output[0] =
3703 LLVMBuildExtractElement(ctx->ac.builder, tmp, ctx->i32_0, "");
3704 emit_data->output[1] =
3705 LLVMBuildExtractElement(ctx->ac.builder, tmp, ctx->i32_1, "");
3706 }
3707
3708 LLVMTypeRef si_const_array(LLVMTypeRef elem_type, int num_elements)
3709 {
3710 return LLVMPointerType(LLVMArrayType(elem_type, num_elements),
3711 CONST_ADDR_SPACE);
3712 }
3713
3714 static void si_llvm_emit_ddxy(
3715 const struct lp_build_tgsi_action *action,
3716 struct lp_build_tgsi_context *bld_base,
3717 struct lp_build_emit_data *emit_data)
3718 {
3719 struct si_shader_context *ctx = si_shader_context(bld_base);
3720 unsigned opcode = emit_data->info->opcode;
3721 LLVMValueRef val;
3722 int idx;
3723 unsigned mask;
3724
3725 if (opcode == TGSI_OPCODE_DDX_FINE)
3726 mask = AC_TID_MASK_LEFT;
3727 else if (opcode == TGSI_OPCODE_DDY_FINE)
3728 mask = AC_TID_MASK_TOP;
3729 else
3730 mask = AC_TID_MASK_TOP_LEFT;
3731
3732 /* for DDX we want to next X pixel, DDY next Y pixel. */
3733 idx = (opcode == TGSI_OPCODE_DDX || opcode == TGSI_OPCODE_DDX_FINE) ? 1 : 2;
3734
3735 val = ac_to_integer(&ctx->ac, emit_data->args[0]);
3736 val = ac_build_ddxy(&ctx->ac, mask, idx, val);
3737 emit_data->output[emit_data->chan] = val;
3738 }
3739
3740 /*
3741 * this takes an I,J coordinate pair,
3742 * and works out the X and Y derivatives.
3743 * it returns DDX(I), DDX(J), DDY(I), DDY(J).
3744 */
3745 static LLVMValueRef si_llvm_emit_ddxy_interp(
3746 struct lp_build_tgsi_context *bld_base,
3747 LLVMValueRef interp_ij)
3748 {
3749 struct si_shader_context *ctx = si_shader_context(bld_base);
3750 LLVMValueRef result[4], a;
3751 unsigned i;
3752
3753 for (i = 0; i < 2; i++) {
3754 a = LLVMBuildExtractElement(ctx->ac.builder, interp_ij,
3755 LLVMConstInt(ctx->i32, i, 0), "");
3756 result[i] = lp_build_emit_llvm_unary(bld_base, TGSI_OPCODE_DDX, a);
3757 result[2+i] = lp_build_emit_llvm_unary(bld_base, TGSI_OPCODE_DDY, a);
3758 }
3759
3760 return lp_build_gather_values(&ctx->gallivm, result, 4);
3761 }
3762
3763 static void interp_fetch_args(
3764 struct lp_build_tgsi_context *bld_base,
3765 struct lp_build_emit_data *emit_data)
3766 {
3767 struct si_shader_context *ctx = si_shader_context(bld_base);
3768 const struct tgsi_full_instruction *inst = emit_data->inst;
3769
3770 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET) {
3771 /* offset is in second src, first two channels */
3772 emit_data->args[0] = lp_build_emit_fetch(bld_base,
3773 emit_data->inst, 1,
3774 TGSI_CHAN_X);
3775 emit_data->args[1] = lp_build_emit_fetch(bld_base,
3776 emit_data->inst, 1,
3777 TGSI_CHAN_Y);
3778 emit_data->arg_count = 2;
3779 } else if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
3780 LLVMValueRef sample_position;
3781 LLVMValueRef sample_id;
3782 LLVMValueRef halfval = LLVMConstReal(ctx->f32, 0.5f);
3783
3784 /* fetch sample ID, then fetch its sample position,
3785 * and place into first two channels.
3786 */
3787 sample_id = lp_build_emit_fetch(bld_base,
3788 emit_data->inst, 1, TGSI_CHAN_X);
3789 sample_id = ac_to_integer(&ctx->ac, sample_id);
3790
3791 /* Section 8.13.2 (Interpolation Functions) of the OpenGL Shading
3792 * Language 4.50 spec says about interpolateAtSample:
3793 *
3794 * "Returns the value of the input interpolant variable at
3795 * the location of sample number sample. If multisample
3796 * buffers are not available, the input variable will be
3797 * evaluated at the center of the pixel. If sample sample
3798 * does not exist, the position used to interpolate the
3799 * input variable is undefined."
3800 *
3801 * This means that sample_id values outside of the valid are
3802 * in fact valid input, and the usual mechanism for loading the
3803 * sample position doesn't work.
3804 */
3805 if (ctx->shader->key.mono.u.ps.interpolate_at_sample_force_center) {
3806 LLVMValueRef center[4] = {
3807 LLVMConstReal(ctx->f32, 0.5),
3808 LLVMConstReal(ctx->f32, 0.5),
3809 ctx->ac.f32_0,
3810 ctx->ac.f32_0,
3811 };
3812
3813 sample_position = lp_build_gather_values(&ctx->gallivm, center, 4);
3814 } else {
3815 sample_position = load_sample_position(ctx, sample_id);
3816 }
3817
3818 emit_data->args[0] = LLVMBuildExtractElement(ctx->ac.builder,
3819 sample_position,
3820 ctx->i32_0, "");
3821
3822 emit_data->args[0] = LLVMBuildFSub(ctx->ac.builder, emit_data->args[0], halfval, "");
3823 emit_data->args[1] = LLVMBuildExtractElement(ctx->ac.builder,
3824 sample_position,
3825 ctx->i32_1, "");
3826 emit_data->args[1] = LLVMBuildFSub(ctx->ac.builder, emit_data->args[1], halfval, "");
3827 emit_data->arg_count = 2;
3828 }
3829 }
3830
3831 static void build_interp_intrinsic(const struct lp_build_tgsi_action *action,
3832 struct lp_build_tgsi_context *bld_base,
3833 struct lp_build_emit_data *emit_data)
3834 {
3835 struct si_shader_context *ctx = si_shader_context(bld_base);
3836 struct si_shader *shader = ctx->shader;
3837 const struct tgsi_shader_info *info = &shader->selector->info;
3838 LLVMValueRef interp_param;
3839 const struct tgsi_full_instruction *inst = emit_data->inst;
3840 const struct tgsi_full_src_register *input = &inst->Src[0];
3841 int input_base, input_array_size;
3842 int chan;
3843 int i;
3844 LLVMValueRef prim_mask = LLVMGetParam(ctx->main_fn, SI_PARAM_PRIM_MASK);
3845 LLVMValueRef array_idx;
3846 int interp_param_idx;
3847 unsigned interp;
3848 unsigned location;
3849
3850 assert(input->Register.File == TGSI_FILE_INPUT);
3851
3852 if (input->Register.Indirect) {
3853 unsigned array_id = input->Indirect.ArrayID;
3854
3855 if (array_id) {
3856 input_base = info->input_array_first[array_id];
3857 input_array_size = info->input_array_last[array_id] - input_base + 1;
3858 } else {
3859 input_base = inst->Src[0].Register.Index;
3860 input_array_size = info->num_inputs - input_base;
3861 }
3862
3863 array_idx = si_get_indirect_index(ctx, &input->Indirect,
3864 1, input->Register.Index - input_base);
3865 } else {
3866 input_base = inst->Src[0].Register.Index;
3867 input_array_size = 1;
3868 array_idx = ctx->i32_0;
3869 }
3870
3871 interp = shader->selector->info.input_interpolate[input_base];
3872
3873 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
3874 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE)
3875 location = TGSI_INTERPOLATE_LOC_CENTER;
3876 else
3877 location = TGSI_INTERPOLATE_LOC_CENTROID;
3878
3879 interp_param_idx = lookup_interp_param_index(interp, location);
3880 if (interp_param_idx == -1)
3881 return;
3882 else if (interp_param_idx)
3883 interp_param = LLVMGetParam(ctx->main_fn, interp_param_idx);
3884 else
3885 interp_param = NULL;
3886
3887 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
3888 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
3889 LLVMValueRef ij_out[2];
3890 LLVMValueRef ddxy_out = si_llvm_emit_ddxy_interp(bld_base, interp_param);
3891
3892 /*
3893 * take the I then J parameters, and the DDX/Y for it, and
3894 * calculate the IJ inputs for the interpolator.
3895 * temp1 = ddx * offset/sample.x + I;
3896 * interp_param.I = ddy * offset/sample.y + temp1;
3897 * temp1 = ddx * offset/sample.x + J;
3898 * interp_param.J = ddy * offset/sample.y + temp1;
3899 */
3900 for (i = 0; i < 2; i++) {
3901 LLVMValueRef ix_ll = LLVMConstInt(ctx->i32, i, 0);
3902 LLVMValueRef iy_ll = LLVMConstInt(ctx->i32, i + 2, 0);
3903 LLVMValueRef ddx_el = LLVMBuildExtractElement(ctx->ac.builder,
3904 ddxy_out, ix_ll, "");
3905 LLVMValueRef ddy_el = LLVMBuildExtractElement(ctx->ac.builder,
3906 ddxy_out, iy_ll, "");
3907 LLVMValueRef interp_el = LLVMBuildExtractElement(ctx->ac.builder,
3908 interp_param, ix_ll, "");
3909 LLVMValueRef temp1, temp2;
3910
3911 interp_el = ac_to_float(&ctx->ac, interp_el);
3912
3913 temp1 = LLVMBuildFMul(ctx->ac.builder, ddx_el, emit_data->args[0], "");
3914
3915 temp1 = LLVMBuildFAdd(ctx->ac.builder, temp1, interp_el, "");
3916
3917 temp2 = LLVMBuildFMul(ctx->ac.builder, ddy_el, emit_data->args[1], "");
3918
3919 ij_out[i] = LLVMBuildFAdd(ctx->ac.builder, temp2, temp1, "");
3920 }
3921 interp_param = lp_build_gather_values(&ctx->gallivm, ij_out, 2);
3922 }
3923
3924 if (interp_param)
3925 interp_param = ac_to_float(&ctx->ac, interp_param);
3926
3927 for (chan = 0; chan < 4; chan++) {
3928 LLVMValueRef gather = LLVMGetUndef(LLVMVectorType(ctx->f32, input_array_size));
3929 unsigned schan = tgsi_util_get_full_src_register_swizzle(&inst->Src[0], chan);
3930
3931 for (unsigned idx = 0; idx < input_array_size; ++idx) {
3932 LLVMValueRef v, i = NULL, j = NULL;
3933
3934 if (interp_param) {
3935 i = LLVMBuildExtractElement(
3936 ctx->ac.builder, interp_param, ctx->i32_0, "");
3937 j = LLVMBuildExtractElement(
3938 ctx->ac.builder, interp_param, ctx->i32_1, "");
3939 }
3940 v = si_build_fs_interp(ctx, input_base + idx, schan,
3941 prim_mask, i, j);
3942
3943 gather = LLVMBuildInsertElement(ctx->ac.builder,
3944 gather, v, LLVMConstInt(ctx->i32, idx, false), "");
3945 }
3946
3947 emit_data->output[chan] = LLVMBuildExtractElement(
3948 ctx->ac.builder, gather, array_idx, "");
3949 }
3950 }
3951
3952 static void vote_all_emit(
3953 const struct lp_build_tgsi_action *action,
3954 struct lp_build_tgsi_context *bld_base,
3955 struct lp_build_emit_data *emit_data)
3956 {
3957 struct si_shader_context *ctx = si_shader_context(bld_base);
3958
3959 LLVMValueRef tmp = ac_build_vote_all(&ctx->ac, emit_data->args[0]);
3960 emit_data->output[emit_data->chan] =
3961 LLVMBuildSExt(ctx->ac.builder, tmp, ctx->i32, "");
3962 }
3963
3964 static void vote_any_emit(
3965 const struct lp_build_tgsi_action *action,
3966 struct lp_build_tgsi_context *bld_base,
3967 struct lp_build_emit_data *emit_data)
3968 {
3969 struct si_shader_context *ctx = si_shader_context(bld_base);
3970
3971 LLVMValueRef tmp = ac_build_vote_any(&ctx->ac, emit_data->args[0]);
3972 emit_data->output[emit_data->chan] =
3973 LLVMBuildSExt(ctx->ac.builder, tmp, ctx->i32, "");
3974 }
3975
3976 static void vote_eq_emit(
3977 const struct lp_build_tgsi_action *action,
3978 struct lp_build_tgsi_context *bld_base,
3979 struct lp_build_emit_data *emit_data)
3980 {
3981 struct si_shader_context *ctx = si_shader_context(bld_base);
3982
3983 LLVMValueRef tmp = ac_build_vote_eq(&ctx->ac, emit_data->args[0]);
3984 emit_data->output[emit_data->chan] =
3985 LLVMBuildSExt(ctx->ac.builder, tmp, ctx->i32, "");
3986 }
3987
3988 static void ballot_emit(
3989 const struct lp_build_tgsi_action *action,
3990 struct lp_build_tgsi_context *bld_base,
3991 struct lp_build_emit_data *emit_data)
3992 {
3993 struct si_shader_context *ctx = si_shader_context(bld_base);
3994 LLVMBuilderRef builder = ctx->ac.builder;
3995 LLVMValueRef tmp;
3996
3997 tmp = lp_build_emit_fetch(bld_base, emit_data->inst, 0, TGSI_CHAN_X);
3998 tmp = ac_build_ballot(&ctx->ac, tmp);
3999 tmp = LLVMBuildBitCast(builder, tmp, ctx->v2i32, "");
4000
4001 emit_data->output[0] = LLVMBuildExtractElement(builder, tmp, ctx->i32_0, "");
4002 emit_data->output[1] = LLVMBuildExtractElement(builder, tmp, ctx->i32_1, "");
4003 }
4004
4005 static void read_invoc_fetch_args(
4006 struct lp_build_tgsi_context *bld_base,
4007 struct lp_build_emit_data *emit_data)
4008 {
4009 emit_data->args[0] = lp_build_emit_fetch(bld_base, emit_data->inst,
4010 0, emit_data->src_chan);
4011
4012 /* Always read the source invocation (= lane) from the X channel. */
4013 emit_data->args[1] = lp_build_emit_fetch(bld_base, emit_data->inst,
4014 1, TGSI_CHAN_X);
4015 emit_data->arg_count = 2;
4016 }
4017
4018 static void read_lane_emit(
4019 const struct lp_build_tgsi_action *action,
4020 struct lp_build_tgsi_context *bld_base,
4021 struct lp_build_emit_data *emit_data)
4022 {
4023 struct si_shader_context *ctx = si_shader_context(bld_base);
4024
4025 /* We currently have no other way to prevent LLVM from lifting the icmp
4026 * calls to a dominating basic block.
4027 */
4028 ac_build_optimization_barrier(&ctx->ac, &emit_data->args[0]);
4029
4030 for (unsigned i = 0; i < emit_data->arg_count; ++i)
4031 emit_data->args[i] = ac_to_integer(&ctx->ac, emit_data->args[i]);
4032
4033 emit_data->output[emit_data->chan] =
4034 ac_build_intrinsic(&ctx->ac, action->intr_name,
4035 ctx->i32, emit_data->args, emit_data->arg_count,
4036 AC_FUNC_ATTR_READNONE |
4037 AC_FUNC_ATTR_CONVERGENT);
4038 }
4039
4040 static unsigned si_llvm_get_stream(struct lp_build_tgsi_context *bld_base,
4041 struct lp_build_emit_data *emit_data)
4042 {
4043 struct si_shader_context *ctx = si_shader_context(bld_base);
4044 struct tgsi_src_register src0 = emit_data->inst->Src[0].Register;
4045 LLVMValueRef imm;
4046 unsigned stream;
4047
4048 assert(src0.File == TGSI_FILE_IMMEDIATE);
4049
4050 imm = ctx->imms[src0.Index * TGSI_NUM_CHANNELS + src0.SwizzleX];
4051 stream = LLVMConstIntGetZExtValue(imm) & 0x3;
4052 return stream;
4053 }
4054
4055 /* Emit one vertex from the geometry shader */
4056 static void si_llvm_emit_vertex(struct ac_shader_abi *abi,
4057 unsigned stream,
4058 LLVMValueRef *addrs)
4059 {
4060 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
4061 struct tgsi_shader_info *info = &ctx->shader->selector->info;
4062 struct lp_build_context *uint = &ctx->bld_base.uint_bld;
4063 struct si_shader *shader = ctx->shader;
4064 struct lp_build_if_state if_state;
4065 LLVMValueRef soffset = LLVMGetParam(ctx->main_fn,
4066 ctx->param_gs2vs_offset);
4067 LLVMValueRef gs_next_vertex;
4068 LLVMValueRef can_emit;
4069 unsigned chan, offset;
4070 int i;
4071
4072 /* Write vertex attribute values to GSVS ring */
4073 gs_next_vertex = LLVMBuildLoad(ctx->ac.builder,
4074 ctx->gs_next_vertex[stream],
4075 "");
4076
4077 /* If this thread has already emitted the declared maximum number of
4078 * vertices, skip the write: excessive vertex emissions are not
4079 * supposed to have any effect.
4080 *
4081 * If the shader has no writes to memory, kill it instead. This skips
4082 * further memory loads and may allow LLVM to skip to the end
4083 * altogether.
4084 */
4085 can_emit = LLVMBuildICmp(ctx->ac.builder, LLVMIntULT, gs_next_vertex,
4086 LLVMConstInt(ctx->i32,
4087 shader->selector->gs_max_out_vertices, 0), "");
4088
4089 bool use_kill = !info->writes_memory;
4090 if (use_kill) {
4091 ac_build_kill_if_false(&ctx->ac, can_emit);
4092 } else {
4093 lp_build_if(&if_state, &ctx->gallivm, can_emit);
4094 }
4095
4096 offset = 0;
4097 for (i = 0; i < info->num_outputs; i++) {
4098 for (chan = 0; chan < 4; chan++) {
4099 if (!(info->output_usagemask[i] & (1 << chan)) ||
4100 ((info->output_streams[i] >> (2 * chan)) & 3) != stream)
4101 continue;
4102
4103 LLVMValueRef out_val = LLVMBuildLoad(ctx->ac.builder, addrs[4 * i + chan], "");
4104 LLVMValueRef voffset =
4105 LLVMConstInt(ctx->i32, offset *
4106 shader->selector->gs_max_out_vertices, 0);
4107 offset++;
4108
4109 voffset = lp_build_add(uint, voffset, gs_next_vertex);
4110 voffset = lp_build_mul_imm(uint, voffset, 4);
4111
4112 out_val = ac_to_integer(&ctx->ac, out_val);
4113
4114 ac_build_buffer_store_dword(&ctx->ac,
4115 ctx->gsvs_ring[stream],
4116 out_val, 1,
4117 voffset, soffset, 0,
4118 1, 1, true, true);
4119 }
4120 }
4121
4122 gs_next_vertex = lp_build_add(uint, gs_next_vertex,
4123 ctx->i32_1);
4124
4125 LLVMBuildStore(ctx->ac.builder, gs_next_vertex, ctx->gs_next_vertex[stream]);
4126
4127 /* Signal vertex emission */
4128 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_EMIT | AC_SENDMSG_GS | (stream << 8),
4129 si_get_gs_wave_id(ctx));
4130 if (!use_kill)
4131 lp_build_endif(&if_state);
4132 }
4133
4134 /* Emit one vertex from the geometry shader */
4135 static void si_tgsi_emit_vertex(
4136 const struct lp_build_tgsi_action *action,
4137 struct lp_build_tgsi_context *bld_base,
4138 struct lp_build_emit_data *emit_data)
4139 {
4140 struct si_shader_context *ctx = si_shader_context(bld_base);
4141 unsigned stream = si_llvm_get_stream(bld_base, emit_data);
4142
4143 si_llvm_emit_vertex(&ctx->abi, stream, ctx->outputs[0]);
4144 }
4145
4146 /* Cut one primitive from the geometry shader */
4147 static void si_llvm_emit_primitive(
4148 const struct lp_build_tgsi_action *action,
4149 struct lp_build_tgsi_context *bld_base,
4150 struct lp_build_emit_data *emit_data)
4151 {
4152 struct si_shader_context *ctx = si_shader_context(bld_base);
4153 unsigned stream;
4154
4155 /* Signal primitive cut */
4156 stream = si_llvm_get_stream(bld_base, emit_data);
4157 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_CUT | AC_SENDMSG_GS | (stream << 8),
4158 si_get_gs_wave_id(ctx));
4159 }
4160
4161 static void si_llvm_emit_barrier(const struct lp_build_tgsi_action *action,
4162 struct lp_build_tgsi_context *bld_base,
4163 struct lp_build_emit_data *emit_data)
4164 {
4165 struct si_shader_context *ctx = si_shader_context(bld_base);
4166
4167 /* SI only (thanks to a hw bug workaround):
4168 * The real barrier instruction isn’t needed, because an entire patch
4169 * always fits into a single wave.
4170 */
4171 if (ctx->screen->info.chip_class == SI &&
4172 ctx->type == PIPE_SHADER_TESS_CTRL) {
4173 si_emit_waitcnt(ctx, LGKM_CNT & VM_CNT);
4174 return;
4175 }
4176
4177 lp_build_intrinsic(ctx->ac.builder,
4178 "llvm.amdgcn.s.barrier",
4179 ctx->voidt, NULL, 0, LP_FUNC_ATTR_CONVERGENT);
4180 }
4181
4182 static const struct lp_build_tgsi_action interp_action = {
4183 .fetch_args = interp_fetch_args,
4184 .emit = build_interp_intrinsic,
4185 };
4186
4187 static void si_create_function(struct si_shader_context *ctx,
4188 const char *name,
4189 LLVMTypeRef *returns, unsigned num_returns,
4190 struct si_function_info *fninfo,
4191 unsigned max_workgroup_size)
4192 {
4193 int i;
4194
4195 si_llvm_create_func(ctx, name, returns, num_returns,
4196 fninfo->types, fninfo->num_params);
4197 ctx->return_value = LLVMGetUndef(ctx->return_type);
4198
4199 for (i = 0; i < fninfo->num_sgpr_params; ++i) {
4200 LLVMValueRef P = LLVMGetParam(ctx->main_fn, i);
4201
4202 /* The combination of:
4203 * - ByVal
4204 * - dereferenceable
4205 * - invariant.load
4206 * allows the optimization passes to move loads and reduces
4207 * SGPR spilling significantly.
4208 */
4209 if (LLVMGetTypeKind(LLVMTypeOf(P)) == LLVMPointerTypeKind) {
4210 lp_add_function_attr(ctx->main_fn, i + 1, LP_FUNC_ATTR_BYVAL);
4211 lp_add_function_attr(ctx->main_fn, i + 1, LP_FUNC_ATTR_NOALIAS);
4212 ac_add_attr_dereferenceable(P, UINT64_MAX);
4213 } else
4214 lp_add_function_attr(ctx->main_fn, i + 1, LP_FUNC_ATTR_INREG);
4215 }
4216
4217 for (i = 0; i < fninfo->num_params; ++i) {
4218 if (fninfo->assign[i])
4219 *fninfo->assign[i] = LLVMGetParam(ctx->main_fn, i);
4220 }
4221
4222 if (max_workgroup_size) {
4223 si_llvm_add_attribute(ctx->main_fn, "amdgpu-max-work-group-size",
4224 max_workgroup_size);
4225 }
4226 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
4227 "no-signed-zeros-fp-math",
4228 "true");
4229
4230 if (ctx->screen->debug_flags & DBG(UNSAFE_MATH)) {
4231 /* These were copied from some LLVM test. */
4232 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
4233 "less-precise-fpmad",
4234 "true");
4235 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
4236 "no-infs-fp-math",
4237 "true");
4238 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
4239 "no-nans-fp-math",
4240 "true");
4241 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
4242 "unsafe-fp-math",
4243 "true");
4244 }
4245 }
4246
4247 static void declare_streamout_params(struct si_shader_context *ctx,
4248 struct pipe_stream_output_info *so,
4249 struct si_function_info *fninfo)
4250 {
4251 int i;
4252
4253 /* Streamout SGPRs. */
4254 if (so->num_outputs) {
4255 if (ctx->type != PIPE_SHADER_TESS_EVAL)
4256 ctx->param_streamout_config = add_arg(fninfo, ARG_SGPR, ctx->ac.i32);
4257 else
4258 ctx->param_streamout_config = fninfo->num_params - 1;
4259
4260 ctx->param_streamout_write_index = add_arg(fninfo, ARG_SGPR, ctx->ac.i32);
4261 }
4262 /* A streamout buffer offset is loaded if the stride is non-zero. */
4263 for (i = 0; i < 4; i++) {
4264 if (!so->stride[i])
4265 continue;
4266
4267 ctx->param_streamout_offset[i] = add_arg(fninfo, ARG_SGPR, ctx->ac.i32);
4268 }
4269 }
4270
4271 static unsigned si_get_max_workgroup_size(const struct si_shader *shader)
4272 {
4273 switch (shader->selector->type) {
4274 case PIPE_SHADER_TESS_CTRL:
4275 /* Return this so that LLVM doesn't remove s_barrier
4276 * instructions on chips where we use s_barrier. */
4277 return shader->selector->screen->info.chip_class >= CIK ? 128 : 64;
4278
4279 case PIPE_SHADER_GEOMETRY:
4280 return shader->selector->screen->info.chip_class >= GFX9 ? 128 : 64;
4281
4282 case PIPE_SHADER_COMPUTE:
4283 break; /* see below */
4284
4285 default:
4286 return 0;
4287 }
4288
4289 const unsigned *properties = shader->selector->info.properties;
4290 unsigned max_work_group_size =
4291 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] *
4292 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT] *
4293 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH];
4294
4295 if (!max_work_group_size) {
4296 /* This is a variable group size compute shader,
4297 * compile it for the maximum possible group size.
4298 */
4299 max_work_group_size = SI_MAX_VARIABLE_THREADS_PER_BLOCK;
4300 }
4301 return max_work_group_size;
4302 }
4303
4304 static void declare_per_stage_desc_pointers(struct si_shader_context *ctx,
4305 struct si_function_info *fninfo,
4306 bool assign_params)
4307 {
4308 LLVMTypeRef const_shader_buf_type;
4309
4310 if (ctx->shader->selector->info.const_buffers_declared == 1 &&
4311 ctx->shader->selector->info.shader_buffers_declared == 0)
4312 const_shader_buf_type = ctx->f32;
4313 else
4314 const_shader_buf_type = ctx->v4i32;
4315
4316 unsigned const_and_shader_buffers =
4317 add_arg(fninfo, ARG_SGPR,
4318 si_const_array(const_shader_buf_type, 0));
4319
4320 unsigned samplers_and_images =
4321 add_arg(fninfo, ARG_SGPR,
4322 si_const_array(ctx->v8i32,
4323 SI_NUM_IMAGES + SI_NUM_SAMPLERS * 2));
4324
4325 if (assign_params) {
4326 ctx->param_const_and_shader_buffers = const_and_shader_buffers;
4327 ctx->param_samplers_and_images = samplers_and_images;
4328 }
4329 }
4330
4331 static void declare_global_desc_pointers(struct si_shader_context *ctx,
4332 struct si_function_info *fninfo)
4333 {
4334 ctx->param_rw_buffers = add_arg(fninfo, ARG_SGPR,
4335 si_const_array(ctx->v4i32, SI_NUM_RW_BUFFERS));
4336 ctx->param_bindless_samplers_and_images = add_arg(fninfo, ARG_SGPR,
4337 si_const_array(ctx->v8i32, 0));
4338 }
4339
4340 static void declare_vs_specific_input_sgprs(struct si_shader_context *ctx,
4341 struct si_function_info *fninfo)
4342 {
4343 ctx->param_vertex_buffers = add_arg(fninfo, ARG_SGPR,
4344 si_const_array(ctx->v4i32, SI_NUM_VERTEX_BUFFERS));
4345 add_arg_assign(fninfo, ARG_SGPR, ctx->i32, &ctx->abi.base_vertex);
4346 add_arg_assign(fninfo, ARG_SGPR, ctx->i32, &ctx->abi.start_instance);
4347 add_arg_assign(fninfo, ARG_SGPR, ctx->i32, &ctx->abi.draw_id);
4348 ctx->param_vs_state_bits = add_arg(fninfo, ARG_SGPR, ctx->i32);
4349 }
4350
4351 static void declare_vs_input_vgprs(struct si_shader_context *ctx,
4352 struct si_function_info *fninfo,
4353 unsigned *num_prolog_vgprs)
4354 {
4355 struct si_shader *shader = ctx->shader;
4356
4357 add_arg_assign(fninfo, ARG_VGPR, ctx->i32, &ctx->abi.vertex_id);
4358 if (shader->key.as_ls) {
4359 ctx->param_rel_auto_id = add_arg(fninfo, ARG_VGPR, ctx->i32);
4360 add_arg_assign(fninfo, ARG_VGPR, ctx->i32, &ctx->abi.instance_id);
4361 } else {
4362 add_arg_assign(fninfo, ARG_VGPR, ctx->i32, &ctx->abi.instance_id);
4363 ctx->param_vs_prim_id = add_arg(fninfo, ARG_VGPR, ctx->i32);
4364 }
4365 add_arg(fninfo, ARG_VGPR, ctx->i32); /* unused */
4366
4367 if (!shader->is_gs_copy_shader) {
4368 /* Vertex load indices. */
4369 ctx->param_vertex_index0 = fninfo->num_params;
4370 for (unsigned i = 0; i < shader->selector->info.num_inputs; i++)
4371 add_arg(fninfo, ARG_VGPR, ctx->i32);
4372 *num_prolog_vgprs += shader->selector->info.num_inputs;
4373 }
4374 }
4375
4376 static void declare_tes_input_vgprs(struct si_shader_context *ctx,
4377 struct si_function_info *fninfo)
4378 {
4379 ctx->param_tes_u = add_arg(fninfo, ARG_VGPR, ctx->f32);
4380 ctx->param_tes_v = add_arg(fninfo, ARG_VGPR, ctx->f32);
4381 ctx->param_tes_rel_patch_id = add_arg(fninfo, ARG_VGPR, ctx->i32);
4382 ctx->param_tes_patch_id = add_arg(fninfo, ARG_VGPR, ctx->i32);
4383 }
4384
4385 enum {
4386 /* Convenient merged shader definitions. */
4387 SI_SHADER_MERGED_VERTEX_TESSCTRL = PIPE_SHADER_TYPES,
4388 SI_SHADER_MERGED_VERTEX_OR_TESSEVAL_GEOMETRY,
4389 };
4390
4391 static void create_function(struct si_shader_context *ctx)
4392 {
4393 struct si_shader *shader = ctx->shader;
4394 struct si_function_info fninfo;
4395 LLVMTypeRef returns[16+32*4];
4396 unsigned i, num_return_sgprs;
4397 unsigned num_returns = 0;
4398 unsigned num_prolog_vgprs = 0;
4399 unsigned type = ctx->type;
4400 unsigned vs_blit_property =
4401 shader->selector->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS];
4402
4403 si_init_function_info(&fninfo);
4404
4405 /* Set MERGED shaders. */
4406 if (ctx->screen->info.chip_class >= GFX9) {
4407 if (shader->key.as_ls || type == PIPE_SHADER_TESS_CTRL)
4408 type = SI_SHADER_MERGED_VERTEX_TESSCTRL; /* LS or HS */
4409 else if (shader->key.as_es || type == PIPE_SHADER_GEOMETRY)
4410 type = SI_SHADER_MERGED_VERTEX_OR_TESSEVAL_GEOMETRY;
4411 }
4412
4413 LLVMTypeRef v3i32 = LLVMVectorType(ctx->i32, 3);
4414
4415 switch (type) {
4416 case PIPE_SHADER_VERTEX:
4417 declare_global_desc_pointers(ctx, &fninfo);
4418
4419 if (vs_blit_property) {
4420 ctx->param_vs_blit_inputs = fninfo.num_params;
4421 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* i16 x1, y1 */
4422 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* i16 x2, y2 */
4423 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* depth */
4424
4425 if (vs_blit_property == SI_VS_BLIT_SGPRS_POS_COLOR) {
4426 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* color0 */
4427 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* color1 */
4428 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* color2 */
4429 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* color3 */
4430 } else if (vs_blit_property == SI_VS_BLIT_SGPRS_POS_TEXCOORD) {
4431 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* texcoord.x1 */
4432 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* texcoord.y1 */
4433 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* texcoord.x2 */
4434 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* texcoord.y2 */
4435 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* texcoord.z */
4436 add_arg(&fninfo, ARG_SGPR, ctx->f32); /* texcoord.w */
4437 }
4438
4439 /* VGPRs */
4440 declare_vs_input_vgprs(ctx, &fninfo, &num_prolog_vgprs);
4441 break;
4442 }
4443
4444 declare_per_stage_desc_pointers(ctx, &fninfo, true);
4445 declare_vs_specific_input_sgprs(ctx, &fninfo);
4446
4447 if (shader->key.as_es) {
4448 ctx->param_es2gs_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4449 } else if (shader->key.as_ls) {
4450 /* no extra parameters */
4451 } else {
4452 if (shader->is_gs_copy_shader) {
4453 fninfo.num_params = ctx->param_rw_buffers + 1;
4454 fninfo.num_sgpr_params = fninfo.num_params;
4455 }
4456
4457 /* The locations of the other parameters are assigned dynamically. */
4458 declare_streamout_params(ctx, &shader->selector->so,
4459 &fninfo);
4460 }
4461
4462 /* VGPRs */
4463 declare_vs_input_vgprs(ctx, &fninfo, &num_prolog_vgprs);
4464 break;
4465
4466 case PIPE_SHADER_TESS_CTRL: /* SI-CI-VI */
4467 declare_global_desc_pointers(ctx, &fninfo);
4468 declare_per_stage_desc_pointers(ctx, &fninfo, true);
4469 ctx->param_tcs_offchip_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4470 ctx->param_tcs_out_lds_offsets = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4471 ctx->param_tcs_out_lds_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4472 ctx->param_vs_state_bits = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4473 ctx->param_tcs_offchip_addr_base64k = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4474 ctx->param_tcs_factor_addr_base64k = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4475 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4476 ctx->param_tcs_factor_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4477
4478 /* VGPRs */
4479 ctx->param_tcs_patch_id = add_arg(&fninfo, ARG_VGPR, ctx->i32);
4480 ctx->param_tcs_rel_ids = add_arg(&fninfo, ARG_VGPR, ctx->i32);
4481
4482 /* param_tcs_offchip_offset and param_tcs_factor_offset are
4483 * placed after the user SGPRs.
4484 */
4485 for (i = 0; i < GFX6_TCS_NUM_USER_SGPR + 2; i++)
4486 returns[num_returns++] = ctx->i32; /* SGPRs */
4487 for (i = 0; i < 11; i++)
4488 returns[num_returns++] = ctx->f32; /* VGPRs */
4489 break;
4490
4491 case SI_SHADER_MERGED_VERTEX_TESSCTRL:
4492 /* Merged stages have 8 system SGPRs at the beginning. */
4493 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* SPI_SHADER_USER_DATA_ADDR_LO_HS */
4494 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* SPI_SHADER_USER_DATA_ADDR_HI_HS */
4495 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4496 ctx->param_merged_wave_info = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4497 ctx->param_tcs_factor_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4498 ctx->param_merged_scratch_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4499 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused */
4500 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused */
4501
4502 declare_global_desc_pointers(ctx, &fninfo);
4503 declare_per_stage_desc_pointers(ctx, &fninfo,
4504 ctx->type == PIPE_SHADER_VERTEX);
4505 declare_vs_specific_input_sgprs(ctx, &fninfo);
4506
4507 ctx->param_tcs_offchip_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4508 ctx->param_tcs_out_lds_offsets = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4509 ctx->param_tcs_out_lds_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4510 ctx->param_tcs_offchip_addr_base64k = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4511 ctx->param_tcs_factor_addr_base64k = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4512 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused */
4513
4514 declare_per_stage_desc_pointers(ctx, &fninfo,
4515 ctx->type == PIPE_SHADER_TESS_CTRL);
4516
4517 /* VGPRs (first TCS, then VS) */
4518 ctx->param_tcs_patch_id = add_arg(&fninfo, ARG_VGPR, ctx->i32);
4519 ctx->param_tcs_rel_ids = add_arg(&fninfo, ARG_VGPR, ctx->i32);
4520
4521 if (ctx->type == PIPE_SHADER_VERTEX) {
4522 declare_vs_input_vgprs(ctx, &fninfo,
4523 &num_prolog_vgprs);
4524
4525 /* LS return values are inputs to the TCS main shader part. */
4526 for (i = 0; i < 8 + GFX9_TCS_NUM_USER_SGPR; i++)
4527 returns[num_returns++] = ctx->i32; /* SGPRs */
4528 for (i = 0; i < 2; i++)
4529 returns[num_returns++] = ctx->f32; /* VGPRs */
4530 } else {
4531 /* TCS return values are inputs to the TCS epilog.
4532 *
4533 * param_tcs_offchip_offset, param_tcs_factor_offset,
4534 * param_tcs_offchip_layout, and param_rw_buffers
4535 * should be passed to the epilog.
4536 */
4537 for (i = 0; i <= 8 + GFX9_SGPR_TCS_FACTOR_ADDR_BASE64K; i++)
4538 returns[num_returns++] = ctx->i32; /* SGPRs */
4539 for (i = 0; i < 11; i++)
4540 returns[num_returns++] = ctx->f32; /* VGPRs */
4541 }
4542 break;
4543
4544 case SI_SHADER_MERGED_VERTEX_OR_TESSEVAL_GEOMETRY:
4545 /* Merged stages have 8 system SGPRs at the beginning. */
4546 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused (SPI_SHADER_USER_DATA_ADDR_LO_GS) */
4547 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused (SPI_SHADER_USER_DATA_ADDR_HI_GS) */
4548 ctx->param_gs2vs_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4549 ctx->param_merged_wave_info = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4550 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4551 ctx->param_merged_scratch_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4552 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused (SPI_SHADER_PGM_LO/HI_GS << 8) */
4553 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused (SPI_SHADER_PGM_LO/HI_GS >> 24) */
4554
4555 declare_global_desc_pointers(ctx, &fninfo);
4556 declare_per_stage_desc_pointers(ctx, &fninfo,
4557 (ctx->type == PIPE_SHADER_VERTEX ||
4558 ctx->type == PIPE_SHADER_TESS_EVAL));
4559 if (ctx->type == PIPE_SHADER_VERTEX) {
4560 declare_vs_specific_input_sgprs(ctx, &fninfo);
4561 } else {
4562 /* TESS_EVAL (and also GEOMETRY):
4563 * Declare as many input SGPRs as the VS has. */
4564 ctx->param_tcs_offchip_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4565 ctx->param_tcs_offchip_addr_base64k = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4566 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused */
4567 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused */
4568 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused */
4569 ctx->param_vs_state_bits = add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused */
4570 }
4571
4572 declare_per_stage_desc_pointers(ctx, &fninfo,
4573 ctx->type == PIPE_SHADER_GEOMETRY);
4574
4575 /* VGPRs (first GS, then VS/TES) */
4576 ctx->param_gs_vtx01_offset = add_arg(&fninfo, ARG_VGPR, ctx->i32);
4577 ctx->param_gs_vtx23_offset = add_arg(&fninfo, ARG_VGPR, ctx->i32);
4578 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->abi.gs_prim_id);
4579 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->abi.gs_invocation_id);
4580 ctx->param_gs_vtx45_offset = add_arg(&fninfo, ARG_VGPR, ctx->i32);
4581
4582 if (ctx->type == PIPE_SHADER_VERTEX) {
4583 declare_vs_input_vgprs(ctx, &fninfo,
4584 &num_prolog_vgprs);
4585 } else if (ctx->type == PIPE_SHADER_TESS_EVAL) {
4586 declare_tes_input_vgprs(ctx, &fninfo);
4587 }
4588
4589 if (ctx->type == PIPE_SHADER_VERTEX ||
4590 ctx->type == PIPE_SHADER_TESS_EVAL) {
4591 /* ES return values are inputs to GS. */
4592 for (i = 0; i < 8 + GFX9_GS_NUM_USER_SGPR; i++)
4593 returns[num_returns++] = ctx->i32; /* SGPRs */
4594 for (i = 0; i < 5; i++)
4595 returns[num_returns++] = ctx->f32; /* VGPRs */
4596 }
4597 break;
4598
4599 case PIPE_SHADER_TESS_EVAL:
4600 declare_global_desc_pointers(ctx, &fninfo);
4601 declare_per_stage_desc_pointers(ctx, &fninfo, true);
4602 ctx->param_tcs_offchip_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4603 ctx->param_tcs_offchip_addr_base64k = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4604
4605 if (shader->key.as_es) {
4606 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4607 add_arg(&fninfo, ARG_SGPR, ctx->i32);
4608 ctx->param_es2gs_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4609 } else {
4610 add_arg(&fninfo, ARG_SGPR, ctx->i32);
4611 declare_streamout_params(ctx, &shader->selector->so,
4612 &fninfo);
4613 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4614 }
4615
4616 /* VGPRs */
4617 declare_tes_input_vgprs(ctx, &fninfo);
4618 break;
4619
4620 case PIPE_SHADER_GEOMETRY:
4621 declare_global_desc_pointers(ctx, &fninfo);
4622 declare_per_stage_desc_pointers(ctx, &fninfo, true);
4623 ctx->param_gs2vs_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4624 ctx->param_gs_wave_id = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4625
4626 /* VGPRs */
4627 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->gs_vtx_offset[0]);
4628 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->gs_vtx_offset[1]);
4629 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->abi.gs_prim_id);
4630 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->gs_vtx_offset[2]);
4631 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->gs_vtx_offset[3]);
4632 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->gs_vtx_offset[4]);
4633 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->gs_vtx_offset[5]);
4634 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->abi.gs_invocation_id);
4635 break;
4636
4637 case PIPE_SHADER_FRAGMENT:
4638 declare_global_desc_pointers(ctx, &fninfo);
4639 declare_per_stage_desc_pointers(ctx, &fninfo, true);
4640 add_arg_checked(&fninfo, ARG_SGPR, ctx->f32, SI_PARAM_ALPHA_REF);
4641 add_arg_checked(&fninfo, ARG_SGPR, ctx->i32, SI_PARAM_PRIM_MASK);
4642
4643 add_arg_checked(&fninfo, ARG_VGPR, ctx->v2i32, SI_PARAM_PERSP_SAMPLE);
4644 add_arg_checked(&fninfo, ARG_VGPR, ctx->v2i32, SI_PARAM_PERSP_CENTER);
4645 add_arg_checked(&fninfo, ARG_VGPR, ctx->v2i32, SI_PARAM_PERSP_CENTROID);
4646 add_arg_checked(&fninfo, ARG_VGPR, v3i32, SI_PARAM_PERSP_PULL_MODEL);
4647 add_arg_checked(&fninfo, ARG_VGPR, ctx->v2i32, SI_PARAM_LINEAR_SAMPLE);
4648 add_arg_checked(&fninfo, ARG_VGPR, ctx->v2i32, SI_PARAM_LINEAR_CENTER);
4649 add_arg_checked(&fninfo, ARG_VGPR, ctx->v2i32, SI_PARAM_LINEAR_CENTROID);
4650 add_arg_checked(&fninfo, ARG_VGPR, ctx->f32, SI_PARAM_LINE_STIPPLE_TEX);
4651 add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->f32,
4652 &ctx->abi.frag_pos[0], SI_PARAM_POS_X_FLOAT);
4653 add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->f32,
4654 &ctx->abi.frag_pos[1], SI_PARAM_POS_Y_FLOAT);
4655 add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->f32,
4656 &ctx->abi.frag_pos[2], SI_PARAM_POS_Z_FLOAT);
4657 add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->f32,
4658 &ctx->abi.frag_pos[3], SI_PARAM_POS_W_FLOAT);
4659 add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->i32,
4660 &ctx->abi.front_face, SI_PARAM_FRONT_FACE);
4661 shader->info.face_vgpr_index = 20;
4662 add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->i32,
4663 &ctx->abi.ancillary, SI_PARAM_ANCILLARY);
4664 shader->info.ancillary_vgpr_index = 21;
4665 add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->f32,
4666 &ctx->abi.sample_coverage, SI_PARAM_SAMPLE_COVERAGE);
4667 add_arg_checked(&fninfo, ARG_VGPR, ctx->i32, SI_PARAM_POS_FIXED_PT);
4668
4669 /* Color inputs from the prolog. */
4670 if (shader->selector->info.colors_read) {
4671 unsigned num_color_elements =
4672 util_bitcount(shader->selector->info.colors_read);
4673
4674 assert(fninfo.num_params + num_color_elements <= ARRAY_SIZE(fninfo.types));
4675 for (i = 0; i < num_color_elements; i++)
4676 add_arg(&fninfo, ARG_VGPR, ctx->f32);
4677
4678 num_prolog_vgprs += num_color_elements;
4679 }
4680
4681 /* Outputs for the epilog. */
4682 num_return_sgprs = SI_SGPR_ALPHA_REF + 1;
4683 num_returns =
4684 num_return_sgprs +
4685 util_bitcount(shader->selector->info.colors_written) * 4 +
4686 shader->selector->info.writes_z +
4687 shader->selector->info.writes_stencil +
4688 shader->selector->info.writes_samplemask +
4689 1 /* SampleMaskIn */;
4690
4691 num_returns = MAX2(num_returns,
4692 num_return_sgprs +
4693 PS_EPILOG_SAMPLEMASK_MIN_LOC + 1);
4694
4695 for (i = 0; i < num_return_sgprs; i++)
4696 returns[i] = ctx->i32;
4697 for (; i < num_returns; i++)
4698 returns[i] = ctx->f32;
4699 break;
4700
4701 case PIPE_SHADER_COMPUTE:
4702 declare_global_desc_pointers(ctx, &fninfo);
4703 declare_per_stage_desc_pointers(ctx, &fninfo, true);
4704 if (shader->selector->info.uses_grid_size)
4705 ctx->param_grid_size = add_arg(&fninfo, ARG_SGPR, v3i32);
4706 if (shader->selector->info.uses_block_size)
4707 ctx->param_block_size = add_arg(&fninfo, ARG_SGPR, v3i32);
4708
4709 for (i = 0; i < 3; i++) {
4710 ctx->param_block_id[i] = -1;
4711 if (shader->selector->info.uses_block_id[i])
4712 ctx->param_block_id[i] = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4713 }
4714
4715 ctx->param_thread_id = add_arg(&fninfo, ARG_VGPR, v3i32);
4716 break;
4717 default:
4718 assert(0 && "unimplemented shader");
4719 return;
4720 }
4721
4722 si_create_function(ctx, "main", returns, num_returns, &fninfo,
4723 si_get_max_workgroup_size(shader));
4724
4725 /* Reserve register locations for VGPR inputs the PS prolog may need. */
4726 if (ctx->type == PIPE_SHADER_FRAGMENT &&
4727 ctx->separate_prolog) {
4728 si_llvm_add_attribute(ctx->main_fn,
4729 "InitialPSInputAddr",
4730 S_0286D0_PERSP_SAMPLE_ENA(1) |
4731 S_0286D0_PERSP_CENTER_ENA(1) |
4732 S_0286D0_PERSP_CENTROID_ENA(1) |
4733 S_0286D0_LINEAR_SAMPLE_ENA(1) |
4734 S_0286D0_LINEAR_CENTER_ENA(1) |
4735 S_0286D0_LINEAR_CENTROID_ENA(1) |
4736 S_0286D0_FRONT_FACE_ENA(1) |
4737 S_0286D0_ANCILLARY_ENA(1) |
4738 S_0286D0_POS_FIXED_PT_ENA(1));
4739 }
4740
4741 shader->info.num_input_sgprs = 0;
4742 shader->info.num_input_vgprs = 0;
4743
4744 for (i = 0; i < fninfo.num_sgpr_params; ++i)
4745 shader->info.num_input_sgprs += ac_get_type_size(fninfo.types[i]) / 4;
4746
4747 for (; i < fninfo.num_params; ++i)
4748 shader->info.num_input_vgprs += ac_get_type_size(fninfo.types[i]) / 4;
4749
4750 assert(shader->info.num_input_vgprs >= num_prolog_vgprs);
4751 shader->info.num_input_vgprs -= num_prolog_vgprs;
4752
4753 if (shader->key.as_ls ||
4754 ctx->type == PIPE_SHADER_TESS_CTRL ||
4755 /* GFX9 has the ESGS ring buffer in LDS. */
4756 type == SI_SHADER_MERGED_VERTEX_OR_TESSEVAL_GEOMETRY)
4757 ac_declare_lds_as_pointer(&ctx->ac);
4758 }
4759
4760 /**
4761 * Load ESGS and GSVS ring buffer resource descriptors and save the variables
4762 * for later use.
4763 */
4764 static void preload_ring_buffers(struct si_shader_context *ctx)
4765 {
4766 LLVMBuilderRef builder = ctx->ac.builder;
4767
4768 LLVMValueRef buf_ptr = LLVMGetParam(ctx->main_fn,
4769 ctx->param_rw_buffers);
4770
4771 if (ctx->screen->info.chip_class <= VI &&
4772 (ctx->shader->key.as_es || ctx->type == PIPE_SHADER_GEOMETRY)) {
4773 unsigned ring =
4774 ctx->type == PIPE_SHADER_GEOMETRY ? SI_GS_RING_ESGS
4775 : SI_ES_RING_ESGS;
4776 LLVMValueRef offset = LLVMConstInt(ctx->i32, ring, 0);
4777
4778 ctx->esgs_ring =
4779 ac_build_load_to_sgpr(&ctx->ac, buf_ptr, offset);
4780 }
4781
4782 if (ctx->shader->is_gs_copy_shader) {
4783 LLVMValueRef offset = LLVMConstInt(ctx->i32, SI_RING_GSVS, 0);
4784
4785 ctx->gsvs_ring[0] =
4786 ac_build_load_to_sgpr(&ctx->ac, buf_ptr, offset);
4787 } else if (ctx->type == PIPE_SHADER_GEOMETRY) {
4788 const struct si_shader_selector *sel = ctx->shader->selector;
4789 LLVMValueRef offset = LLVMConstInt(ctx->i32, SI_RING_GSVS, 0);
4790 LLVMValueRef base_ring;
4791
4792 base_ring = ac_build_load_to_sgpr(&ctx->ac, buf_ptr, offset);
4793
4794 /* The conceptual layout of the GSVS ring is
4795 * v0c0 .. vLv0 v0c1 .. vLc1 ..
4796 * but the real memory layout is swizzled across
4797 * threads:
4798 * t0v0c0 .. t15v0c0 t0v1c0 .. t15v1c0 ... t15vLcL
4799 * t16v0c0 ..
4800 * Override the buffer descriptor accordingly.
4801 */
4802 LLVMTypeRef v2i64 = LLVMVectorType(ctx->i64, 2);
4803 uint64_t stream_offset = 0;
4804
4805 for (unsigned stream = 0; stream < 4; ++stream) {
4806 unsigned num_components;
4807 unsigned stride;
4808 unsigned num_records;
4809 LLVMValueRef ring, tmp;
4810
4811 num_components = sel->info.num_stream_output_components[stream];
4812 if (!num_components)
4813 continue;
4814
4815 stride = 4 * num_components * sel->gs_max_out_vertices;
4816
4817 /* Limit on the stride field for <= CIK. */
4818 assert(stride < (1 << 14));
4819
4820 num_records = 64;
4821
4822 ring = LLVMBuildBitCast(builder, base_ring, v2i64, "");
4823 tmp = LLVMBuildExtractElement(builder, ring, ctx->i32_0, "");
4824 tmp = LLVMBuildAdd(builder, tmp,
4825 LLVMConstInt(ctx->i64,
4826 stream_offset, 0), "");
4827 stream_offset += stride * 64;
4828
4829 ring = LLVMBuildInsertElement(builder, ring, tmp, ctx->i32_0, "");
4830 ring = LLVMBuildBitCast(builder, ring, ctx->v4i32, "");
4831 tmp = LLVMBuildExtractElement(builder, ring, ctx->i32_1, "");
4832 tmp = LLVMBuildOr(builder, tmp,
4833 LLVMConstInt(ctx->i32,
4834 S_008F04_STRIDE(stride) |
4835 S_008F04_SWIZZLE_ENABLE(1), 0), "");
4836 ring = LLVMBuildInsertElement(builder, ring, tmp, ctx->i32_1, "");
4837 ring = LLVMBuildInsertElement(builder, ring,
4838 LLVMConstInt(ctx->i32, num_records, 0),
4839 LLVMConstInt(ctx->i32, 2, 0), "");
4840 ring = LLVMBuildInsertElement(builder, ring,
4841 LLVMConstInt(ctx->i32,
4842 S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
4843 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
4844 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
4845 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
4846 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
4847 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
4848 S_008F0C_ELEMENT_SIZE(1) | /* element_size = 4 (bytes) */
4849 S_008F0C_INDEX_STRIDE(1) | /* index_stride = 16 (elements) */
4850 S_008F0C_ADD_TID_ENABLE(1),
4851 0),
4852 LLVMConstInt(ctx->i32, 3, 0), "");
4853
4854 ctx->gsvs_ring[stream] = ring;
4855 }
4856 }
4857 }
4858
4859 static void si_llvm_emit_polygon_stipple(struct si_shader_context *ctx,
4860 LLVMValueRef param_rw_buffers,
4861 unsigned param_pos_fixed_pt)
4862 {
4863 LLVMBuilderRef builder = ctx->ac.builder;
4864 LLVMValueRef slot, desc, offset, row, bit, address[2];
4865
4866 /* Use the fixed-point gl_FragCoord input.
4867 * Since the stipple pattern is 32x32 and it repeats, just get 5 bits
4868 * per coordinate to get the repeating effect.
4869 */
4870 address[0] = unpack_param(ctx, param_pos_fixed_pt, 0, 5);
4871 address[1] = unpack_param(ctx, param_pos_fixed_pt, 16, 5);
4872
4873 /* Load the buffer descriptor. */
4874 slot = LLVMConstInt(ctx->i32, SI_PS_CONST_POLY_STIPPLE, 0);
4875 desc = ac_build_load_to_sgpr(&ctx->ac, param_rw_buffers, slot);
4876
4877 /* The stipple pattern is 32x32, each row has 32 bits. */
4878 offset = LLVMBuildMul(builder, address[1],
4879 LLVMConstInt(ctx->i32, 4, 0), "");
4880 row = buffer_load_const(ctx, desc, offset);
4881 row = ac_to_integer(&ctx->ac, row);
4882 bit = LLVMBuildLShr(builder, row, address[0], "");
4883 bit = LLVMBuildTrunc(builder, bit, ctx->i1, "");
4884 ac_build_kill_if_false(&ctx->ac, bit);
4885 }
4886
4887 void si_shader_binary_read_config(struct ac_shader_binary *binary,
4888 struct si_shader_config *conf,
4889 unsigned symbol_offset)
4890 {
4891 unsigned i;
4892 const unsigned char *config =
4893 ac_shader_binary_config_start(binary, symbol_offset);
4894 bool really_needs_scratch = false;
4895
4896 /* LLVM adds SGPR spills to the scratch size.
4897 * Find out if we really need the scratch buffer.
4898 */
4899 for (i = 0; i < binary->reloc_count; i++) {
4900 const struct ac_shader_reloc *reloc = &binary->relocs[i];
4901
4902 if (!strcmp(scratch_rsrc_dword0_symbol, reloc->name) ||
4903 !strcmp(scratch_rsrc_dword1_symbol, reloc->name)) {
4904 really_needs_scratch = true;
4905 break;
4906 }
4907 }
4908
4909 /* XXX: We may be able to emit some of these values directly rather than
4910 * extracting fields to be emitted later.
4911 */
4912
4913 for (i = 0; i < binary->config_size_per_symbol; i+= 8) {
4914 unsigned reg = util_le32_to_cpu(*(uint32_t*)(config + i));
4915 unsigned value = util_le32_to_cpu(*(uint32_t*)(config + i + 4));
4916 switch (reg) {
4917 case R_00B028_SPI_SHADER_PGM_RSRC1_PS:
4918 case R_00B128_SPI_SHADER_PGM_RSRC1_VS:
4919 case R_00B228_SPI_SHADER_PGM_RSRC1_GS:
4920 case R_00B428_SPI_SHADER_PGM_RSRC1_HS:
4921 case R_00B848_COMPUTE_PGM_RSRC1:
4922 conf->num_sgprs = MAX2(conf->num_sgprs, (G_00B028_SGPRS(value) + 1) * 8);
4923 conf->num_vgprs = MAX2(conf->num_vgprs, (G_00B028_VGPRS(value) + 1) * 4);
4924 conf->float_mode = G_00B028_FLOAT_MODE(value);
4925 conf->rsrc1 = value;
4926 break;
4927 case R_00B02C_SPI_SHADER_PGM_RSRC2_PS:
4928 conf->lds_size = MAX2(conf->lds_size, G_00B02C_EXTRA_LDS_SIZE(value));
4929 break;
4930 case R_00B84C_COMPUTE_PGM_RSRC2:
4931 conf->lds_size = MAX2(conf->lds_size, G_00B84C_LDS_SIZE(value));
4932 conf->rsrc2 = value;
4933 break;
4934 case R_0286CC_SPI_PS_INPUT_ENA:
4935 conf->spi_ps_input_ena = value;
4936 break;
4937 case R_0286D0_SPI_PS_INPUT_ADDR:
4938 conf->spi_ps_input_addr = value;
4939 break;
4940 case R_0286E8_SPI_TMPRING_SIZE:
4941 case R_00B860_COMPUTE_TMPRING_SIZE:
4942 /* WAVESIZE is in units of 256 dwords. */
4943 if (really_needs_scratch)
4944 conf->scratch_bytes_per_wave =
4945 G_00B860_WAVESIZE(value) * 256 * 4;
4946 break;
4947 case 0x4: /* SPILLED_SGPRS */
4948 conf->spilled_sgprs = value;
4949 break;
4950 case 0x8: /* SPILLED_VGPRS */
4951 conf->spilled_vgprs = value;
4952 break;
4953 default:
4954 {
4955 static bool printed;
4956
4957 if (!printed) {
4958 fprintf(stderr, "Warning: LLVM emitted unknown "
4959 "config register: 0x%x\n", reg);
4960 printed = true;
4961 }
4962 }
4963 break;
4964 }
4965 }
4966
4967 if (!conf->spi_ps_input_addr)
4968 conf->spi_ps_input_addr = conf->spi_ps_input_ena;
4969 }
4970
4971 void si_shader_apply_scratch_relocs(struct si_shader *shader,
4972 uint64_t scratch_va)
4973 {
4974 unsigned i;
4975 uint32_t scratch_rsrc_dword0 = scratch_va;
4976 uint32_t scratch_rsrc_dword1 =
4977 S_008F04_BASE_ADDRESS_HI(scratch_va >> 32);
4978
4979 /* Enable scratch coalescing. */
4980 scratch_rsrc_dword1 |= S_008F04_SWIZZLE_ENABLE(1);
4981
4982 for (i = 0 ; i < shader->binary.reloc_count; i++) {
4983 const struct ac_shader_reloc *reloc =
4984 &shader->binary.relocs[i];
4985 if (!strcmp(scratch_rsrc_dword0_symbol, reloc->name)) {
4986 util_memcpy_cpu_to_le32(shader->binary.code + reloc->offset,
4987 &scratch_rsrc_dword0, 4);
4988 } else if (!strcmp(scratch_rsrc_dword1_symbol, reloc->name)) {
4989 util_memcpy_cpu_to_le32(shader->binary.code + reloc->offset,
4990 &scratch_rsrc_dword1, 4);
4991 }
4992 }
4993 }
4994
4995 static unsigned si_get_shader_binary_size(const struct si_shader *shader)
4996 {
4997 unsigned size = shader->binary.code_size;
4998
4999 if (shader->prolog)
5000 size += shader->prolog->binary.code_size;
5001 if (shader->previous_stage)
5002 size += shader->previous_stage->binary.code_size;
5003 if (shader->prolog2)
5004 size += shader->prolog2->binary.code_size;
5005 if (shader->epilog)
5006 size += shader->epilog->binary.code_size;
5007 return size;
5008 }
5009
5010 int si_shader_binary_upload(struct si_screen *sscreen, struct si_shader *shader)
5011 {
5012 const struct ac_shader_binary *prolog =
5013 shader->prolog ? &shader->prolog->binary : NULL;
5014 const struct ac_shader_binary *previous_stage =
5015 shader->previous_stage ? &shader->previous_stage->binary : NULL;
5016 const struct ac_shader_binary *prolog2 =
5017 shader->prolog2 ? &shader->prolog2->binary : NULL;
5018 const struct ac_shader_binary *epilog =
5019 shader->epilog ? &shader->epilog->binary : NULL;
5020 const struct ac_shader_binary *mainb = &shader->binary;
5021 unsigned bo_size = si_get_shader_binary_size(shader) +
5022 (!epilog ? mainb->rodata_size : 0);
5023 unsigned char *ptr;
5024
5025 assert(!prolog || !prolog->rodata_size);
5026 assert(!previous_stage || !previous_stage->rodata_size);
5027 assert(!prolog2 || !prolog2->rodata_size);
5028 assert((!prolog && !previous_stage && !prolog2 && !epilog) ||
5029 !mainb->rodata_size);
5030 assert(!epilog || !epilog->rodata_size);
5031
5032 r600_resource_reference(&shader->bo, NULL);
5033 shader->bo = (struct r600_resource*)
5034 pipe_buffer_create(&sscreen->b, 0,
5035 PIPE_USAGE_IMMUTABLE,
5036 align(bo_size, SI_CPDMA_ALIGNMENT));
5037 if (!shader->bo)
5038 return -ENOMEM;
5039
5040 /* Upload. */
5041 ptr = sscreen->ws->buffer_map(shader->bo->buf, NULL,
5042 PIPE_TRANSFER_READ_WRITE |
5043 PIPE_TRANSFER_UNSYNCHRONIZED);
5044
5045 /* Don't use util_memcpy_cpu_to_le32. LLVM binaries are
5046 * endian-independent. */
5047 if (prolog) {
5048 memcpy(ptr, prolog->code, prolog->code_size);
5049 ptr += prolog->code_size;
5050 }
5051 if (previous_stage) {
5052 memcpy(ptr, previous_stage->code, previous_stage->code_size);
5053 ptr += previous_stage->code_size;
5054 }
5055 if (prolog2) {
5056 memcpy(ptr, prolog2->code, prolog2->code_size);
5057 ptr += prolog2->code_size;
5058 }
5059
5060 memcpy(ptr, mainb->code, mainb->code_size);
5061 ptr += mainb->code_size;
5062
5063 if (epilog)
5064 memcpy(ptr, epilog->code, epilog->code_size);
5065 else if (mainb->rodata_size > 0)
5066 memcpy(ptr, mainb->rodata, mainb->rodata_size);
5067
5068 sscreen->ws->buffer_unmap(shader->bo->buf);
5069 return 0;
5070 }
5071
5072 static void si_shader_dump_disassembly(const struct ac_shader_binary *binary,
5073 struct pipe_debug_callback *debug,
5074 const char *name, FILE *file)
5075 {
5076 char *line, *p;
5077 unsigned i, count;
5078
5079 if (binary->disasm_string) {
5080 fprintf(file, "Shader %s disassembly:\n", name);
5081 fprintf(file, "%s", binary->disasm_string);
5082
5083 if (debug && debug->debug_message) {
5084 /* Very long debug messages are cut off, so send the
5085 * disassembly one line at a time. This causes more
5086 * overhead, but on the plus side it simplifies
5087 * parsing of resulting logs.
5088 */
5089 pipe_debug_message(debug, SHADER_INFO,
5090 "Shader Disassembly Begin");
5091
5092 line = binary->disasm_string;
5093 while (*line) {
5094 p = util_strchrnul(line, '\n');
5095 count = p - line;
5096
5097 if (count) {
5098 pipe_debug_message(debug, SHADER_INFO,
5099 "%.*s", count, line);
5100 }
5101
5102 if (!*p)
5103 break;
5104 line = p + 1;
5105 }
5106
5107 pipe_debug_message(debug, SHADER_INFO,
5108 "Shader Disassembly End");
5109 }
5110 } else {
5111 fprintf(file, "Shader %s binary:\n", name);
5112 for (i = 0; i < binary->code_size; i += 4) {
5113 fprintf(file, "@0x%x: %02x%02x%02x%02x\n", i,
5114 binary->code[i + 3], binary->code[i + 2],
5115 binary->code[i + 1], binary->code[i]);
5116 }
5117 }
5118 }
5119
5120 static void si_shader_dump_stats(struct si_screen *sscreen,
5121 const struct si_shader *shader,
5122 struct pipe_debug_callback *debug,
5123 unsigned processor,
5124 FILE *file,
5125 bool check_debug_option)
5126 {
5127 const struct si_shader_config *conf = &shader->config;
5128 unsigned num_inputs = shader->selector ? shader->selector->info.num_inputs : 0;
5129 unsigned code_size = si_get_shader_binary_size(shader);
5130 unsigned lds_increment = sscreen->info.chip_class >= CIK ? 512 : 256;
5131 unsigned lds_per_wave = 0;
5132 unsigned max_simd_waves;
5133
5134 switch (sscreen->info.family) {
5135 /* These always have 8 waves: */
5136 case CHIP_POLARIS10:
5137 case CHIP_POLARIS11:
5138 case CHIP_POLARIS12:
5139 max_simd_waves = 8;
5140 break;
5141 default:
5142 max_simd_waves = 10;
5143 }
5144
5145 /* Compute LDS usage for PS. */
5146 switch (processor) {
5147 case PIPE_SHADER_FRAGMENT:
5148 /* The minimum usage per wave is (num_inputs * 48). The maximum
5149 * usage is (num_inputs * 48 * 16).
5150 * We can get anything in between and it varies between waves.
5151 *
5152 * The 48 bytes per input for a single primitive is equal to
5153 * 4 bytes/component * 4 components/input * 3 points.
5154 *
5155 * Other stages don't know the size at compile time or don't
5156 * allocate LDS per wave, but instead they do it per thread group.
5157 */
5158 lds_per_wave = conf->lds_size * lds_increment +
5159 align(num_inputs * 48, lds_increment);
5160 break;
5161 case PIPE_SHADER_COMPUTE:
5162 if (shader->selector) {
5163 unsigned max_workgroup_size =
5164 si_get_max_workgroup_size(shader);
5165 lds_per_wave = (conf->lds_size * lds_increment) /
5166 DIV_ROUND_UP(max_workgroup_size, 64);
5167 }
5168 break;
5169 }
5170
5171 /* Compute the per-SIMD wave counts. */
5172 if (conf->num_sgprs) {
5173 if (sscreen->info.chip_class >= VI)
5174 max_simd_waves = MIN2(max_simd_waves, 800 / conf->num_sgprs);
5175 else
5176 max_simd_waves = MIN2(max_simd_waves, 512 / conf->num_sgprs);
5177 }
5178
5179 if (conf->num_vgprs)
5180 max_simd_waves = MIN2(max_simd_waves, 256 / conf->num_vgprs);
5181
5182 /* LDS is 64KB per CU (4 SIMDs), which is 16KB per SIMD (usage above
5183 * 16KB makes some SIMDs unoccupied). */
5184 if (lds_per_wave)
5185 max_simd_waves = MIN2(max_simd_waves, 16384 / lds_per_wave);
5186
5187 if (!check_debug_option ||
5188 si_can_dump_shader(sscreen, processor)) {
5189 if (processor == PIPE_SHADER_FRAGMENT) {
5190 fprintf(file, "*** SHADER CONFIG ***\n"
5191 "SPI_PS_INPUT_ADDR = 0x%04x\n"
5192 "SPI_PS_INPUT_ENA = 0x%04x\n",
5193 conf->spi_ps_input_addr, conf->spi_ps_input_ena);
5194 }
5195
5196 fprintf(file, "*** SHADER STATS ***\n"
5197 "SGPRS: %d\n"
5198 "VGPRS: %d\n"
5199 "Spilled SGPRs: %d\n"
5200 "Spilled VGPRs: %d\n"
5201 "Private memory VGPRs: %d\n"
5202 "Code Size: %d bytes\n"
5203 "LDS: %d blocks\n"
5204 "Scratch: %d bytes per wave\n"
5205 "Max Waves: %d\n"
5206 "********************\n\n\n",
5207 conf->num_sgprs, conf->num_vgprs,
5208 conf->spilled_sgprs, conf->spilled_vgprs,
5209 conf->private_mem_vgprs, code_size,
5210 conf->lds_size, conf->scratch_bytes_per_wave,
5211 max_simd_waves);
5212 }
5213
5214 pipe_debug_message(debug, SHADER_INFO,
5215 "Shader Stats: SGPRS: %d VGPRS: %d Code Size: %d "
5216 "LDS: %d Scratch: %d Max Waves: %d Spilled SGPRs: %d "
5217 "Spilled VGPRs: %d PrivMem VGPRs: %d",
5218 conf->num_sgprs, conf->num_vgprs, code_size,
5219 conf->lds_size, conf->scratch_bytes_per_wave,
5220 max_simd_waves, conf->spilled_sgprs,
5221 conf->spilled_vgprs, conf->private_mem_vgprs);
5222 }
5223
5224 const char *si_get_shader_name(const struct si_shader *shader, unsigned processor)
5225 {
5226 switch (processor) {
5227 case PIPE_SHADER_VERTEX:
5228 if (shader->key.as_es)
5229 return "Vertex Shader as ES";
5230 else if (shader->key.as_ls)
5231 return "Vertex Shader as LS";
5232 else
5233 return "Vertex Shader as VS";
5234 case PIPE_SHADER_TESS_CTRL:
5235 return "Tessellation Control Shader";
5236 case PIPE_SHADER_TESS_EVAL:
5237 if (shader->key.as_es)
5238 return "Tessellation Evaluation Shader as ES";
5239 else
5240 return "Tessellation Evaluation Shader as VS";
5241 case PIPE_SHADER_GEOMETRY:
5242 if (shader->is_gs_copy_shader)
5243 return "GS Copy Shader as VS";
5244 else
5245 return "Geometry Shader";
5246 case PIPE_SHADER_FRAGMENT:
5247 return "Pixel Shader";
5248 case PIPE_SHADER_COMPUTE:
5249 return "Compute Shader";
5250 default:
5251 return "Unknown Shader";
5252 }
5253 }
5254
5255 void si_shader_dump(struct si_screen *sscreen, const struct si_shader *shader,
5256 struct pipe_debug_callback *debug, unsigned processor,
5257 FILE *file, bool check_debug_option)
5258 {
5259 if (!check_debug_option ||
5260 si_can_dump_shader(sscreen, processor))
5261 si_dump_shader_key(processor, shader, file);
5262
5263 if (!check_debug_option && shader->binary.llvm_ir_string) {
5264 if (shader->previous_stage &&
5265 shader->previous_stage->binary.llvm_ir_string) {
5266 fprintf(file, "\n%s - previous stage - LLVM IR:\n\n",
5267 si_get_shader_name(shader, processor));
5268 fprintf(file, "%s\n", shader->previous_stage->binary.llvm_ir_string);
5269 }
5270
5271 fprintf(file, "\n%s - main shader part - LLVM IR:\n\n",
5272 si_get_shader_name(shader, processor));
5273 fprintf(file, "%s\n", shader->binary.llvm_ir_string);
5274 }
5275
5276 if (!check_debug_option ||
5277 (si_can_dump_shader(sscreen, processor) &&
5278 !(sscreen->debug_flags & DBG(NO_ASM)))) {
5279 fprintf(file, "\n%s:\n", si_get_shader_name(shader, processor));
5280
5281 if (shader->prolog)
5282 si_shader_dump_disassembly(&shader->prolog->binary,
5283 debug, "prolog", file);
5284 if (shader->previous_stage)
5285 si_shader_dump_disassembly(&shader->previous_stage->binary,
5286 debug, "previous stage", file);
5287 if (shader->prolog2)
5288 si_shader_dump_disassembly(&shader->prolog2->binary,
5289 debug, "prolog2", file);
5290
5291 si_shader_dump_disassembly(&shader->binary, debug, "main", file);
5292
5293 if (shader->epilog)
5294 si_shader_dump_disassembly(&shader->epilog->binary,
5295 debug, "epilog", file);
5296 fprintf(file, "\n");
5297 }
5298
5299 si_shader_dump_stats(sscreen, shader, debug, processor, file,
5300 check_debug_option);
5301 }
5302
5303 static int si_compile_llvm(struct si_screen *sscreen,
5304 struct ac_shader_binary *binary,
5305 struct si_shader_config *conf,
5306 LLVMTargetMachineRef tm,
5307 LLVMModuleRef mod,
5308 struct pipe_debug_callback *debug,
5309 unsigned processor,
5310 const char *name)
5311 {
5312 int r = 0;
5313 unsigned count = p_atomic_inc_return(&sscreen->num_compilations);
5314
5315 if (si_can_dump_shader(sscreen, processor)) {
5316 fprintf(stderr, "radeonsi: Compiling shader %d\n", count);
5317
5318 if (!(sscreen->debug_flags & (DBG(NO_IR) | DBG(PREOPT_IR)))) {
5319 fprintf(stderr, "%s LLVM IR:\n\n", name);
5320 ac_dump_module(mod);
5321 fprintf(stderr, "\n");
5322 }
5323 }
5324
5325 if (sscreen->record_llvm_ir) {
5326 char *ir = LLVMPrintModuleToString(mod);
5327 binary->llvm_ir_string = strdup(ir);
5328 LLVMDisposeMessage(ir);
5329 }
5330
5331 if (!si_replace_shader(count, binary)) {
5332 r = si_llvm_compile(mod, binary, tm, debug);
5333 if (r)
5334 return r;
5335 }
5336
5337 si_shader_binary_read_config(binary, conf, 0);
5338
5339 /* Enable 64-bit and 16-bit denormals, because there is no performance
5340 * cost.
5341 *
5342 * If denormals are enabled, all floating-point output modifiers are
5343 * ignored.
5344 *
5345 * Don't enable denormals for 32-bit floats, because:
5346 * - Floating-point output modifiers would be ignored by the hw.
5347 * - Some opcodes don't support denormals, such as v_mad_f32. We would
5348 * have to stop using those.
5349 * - SI & CI would be very slow.
5350 */
5351 conf->float_mode |= V_00B028_FP_64_DENORMS;
5352
5353 FREE(binary->config);
5354 FREE(binary->global_symbol_offsets);
5355 binary->config = NULL;
5356 binary->global_symbol_offsets = NULL;
5357
5358 /* Some shaders can't have rodata because their binaries can be
5359 * concatenated.
5360 */
5361 if (binary->rodata_size &&
5362 (processor == PIPE_SHADER_VERTEX ||
5363 processor == PIPE_SHADER_TESS_CTRL ||
5364 processor == PIPE_SHADER_TESS_EVAL ||
5365 processor == PIPE_SHADER_FRAGMENT)) {
5366 fprintf(stderr, "radeonsi: The shader can't have rodata.");
5367 return -EINVAL;
5368 }
5369
5370 return r;
5371 }
5372
5373 static void si_llvm_build_ret(struct si_shader_context *ctx, LLVMValueRef ret)
5374 {
5375 if (LLVMGetTypeKind(LLVMTypeOf(ret)) == LLVMVoidTypeKind)
5376 LLVMBuildRetVoid(ctx->ac.builder);
5377 else
5378 LLVMBuildRet(ctx->ac.builder, ret);
5379 }
5380
5381 /* Generate code for the hardware VS shader stage to go with a geometry shader */
5382 struct si_shader *
5383 si_generate_gs_copy_shader(struct si_screen *sscreen,
5384 LLVMTargetMachineRef tm,
5385 struct si_shader_selector *gs_selector,
5386 struct pipe_debug_callback *debug)
5387 {
5388 struct si_shader_context ctx;
5389 struct si_shader *shader;
5390 LLVMBuilderRef builder;
5391 struct lp_build_tgsi_context *bld_base = &ctx.bld_base;
5392 struct lp_build_context *uint = &bld_base->uint_bld;
5393 struct si_shader_output_values *outputs;
5394 struct tgsi_shader_info *gsinfo = &gs_selector->info;
5395 int i, r;
5396
5397 outputs = MALLOC(gsinfo->num_outputs * sizeof(outputs[0]));
5398
5399 if (!outputs)
5400 return NULL;
5401
5402 shader = CALLOC_STRUCT(si_shader);
5403 if (!shader) {
5404 FREE(outputs);
5405 return NULL;
5406 }
5407
5408 /* We can leave the fence as permanently signaled because the GS copy
5409 * shader only becomes visible globally after it has been compiled. */
5410 util_queue_fence_init(&shader->ready);
5411
5412 shader->selector = gs_selector;
5413 shader->is_gs_copy_shader = true;
5414
5415 si_init_shader_ctx(&ctx, sscreen, tm);
5416 ctx.shader = shader;
5417 ctx.type = PIPE_SHADER_VERTEX;
5418
5419 builder = ctx.ac.builder;
5420
5421 create_function(&ctx);
5422 preload_ring_buffers(&ctx);
5423
5424 LLVMValueRef voffset =
5425 lp_build_mul_imm(uint, ctx.abi.vertex_id, 4);
5426
5427 /* Fetch the vertex stream ID.*/
5428 LLVMValueRef stream_id;
5429
5430 if (gs_selector->so.num_outputs)
5431 stream_id = unpack_param(&ctx, ctx.param_streamout_config, 24, 2);
5432 else
5433 stream_id = ctx.i32_0;
5434
5435 /* Fill in output information. */
5436 for (i = 0; i < gsinfo->num_outputs; ++i) {
5437 outputs[i].semantic_name = gsinfo->output_semantic_name[i];
5438 outputs[i].semantic_index = gsinfo->output_semantic_index[i];
5439
5440 for (int chan = 0; chan < 4; chan++) {
5441 outputs[i].vertex_stream[chan] =
5442 (gsinfo->output_streams[i] >> (2 * chan)) & 3;
5443 }
5444 }
5445
5446 LLVMBasicBlockRef end_bb;
5447 LLVMValueRef switch_inst;
5448
5449 end_bb = LLVMAppendBasicBlockInContext(ctx.ac.context, ctx.main_fn, "end");
5450 switch_inst = LLVMBuildSwitch(builder, stream_id, end_bb, 4);
5451
5452 for (int stream = 0; stream < 4; stream++) {
5453 LLVMBasicBlockRef bb;
5454 unsigned offset;
5455
5456 if (!gsinfo->num_stream_output_components[stream])
5457 continue;
5458
5459 if (stream > 0 && !gs_selector->so.num_outputs)
5460 continue;
5461
5462 bb = LLVMInsertBasicBlockInContext(ctx.ac.context, end_bb, "out");
5463 LLVMAddCase(switch_inst, LLVMConstInt(ctx.i32, stream, 0), bb);
5464 LLVMPositionBuilderAtEnd(builder, bb);
5465
5466 /* Fetch vertex data from GSVS ring */
5467 offset = 0;
5468 for (i = 0; i < gsinfo->num_outputs; ++i) {
5469 for (unsigned chan = 0; chan < 4; chan++) {
5470 if (!(gsinfo->output_usagemask[i] & (1 << chan)) ||
5471 outputs[i].vertex_stream[chan] != stream) {
5472 outputs[i].values[chan] = ctx.bld_base.base.undef;
5473 continue;
5474 }
5475
5476 LLVMValueRef soffset = LLVMConstInt(ctx.i32,
5477 offset * gs_selector->gs_max_out_vertices * 16 * 4, 0);
5478 offset++;
5479
5480 outputs[i].values[chan] =
5481 ac_build_buffer_load(&ctx.ac,
5482 ctx.gsvs_ring[0], 1,
5483 ctx.i32_0, voffset,
5484 soffset, 0, 1, 1,
5485 true, false);
5486 }
5487 }
5488
5489 /* Streamout and exports. */
5490 if (gs_selector->so.num_outputs) {
5491 si_llvm_emit_streamout(&ctx, outputs,
5492 gsinfo->num_outputs,
5493 stream);
5494 }
5495
5496 if (stream == 0)
5497 si_llvm_export_vs(&ctx, outputs, gsinfo->num_outputs);
5498
5499 LLVMBuildBr(builder, end_bb);
5500 }
5501
5502 LLVMPositionBuilderAtEnd(builder, end_bb);
5503
5504 LLVMBuildRetVoid(ctx.ac.builder);
5505
5506 ctx.type = PIPE_SHADER_GEOMETRY; /* override for shader dumping */
5507 si_llvm_optimize_module(&ctx);
5508
5509 r = si_compile_llvm(sscreen, &ctx.shader->binary,
5510 &ctx.shader->config, ctx.tm,
5511 ctx.gallivm.module,
5512 debug, PIPE_SHADER_GEOMETRY,
5513 "GS Copy Shader");
5514 if (!r) {
5515 if (si_can_dump_shader(sscreen, PIPE_SHADER_GEOMETRY))
5516 fprintf(stderr, "GS Copy Shader:\n");
5517 si_shader_dump(sscreen, ctx.shader, debug,
5518 PIPE_SHADER_GEOMETRY, stderr, true);
5519 r = si_shader_binary_upload(sscreen, ctx.shader);
5520 }
5521
5522 si_llvm_dispose(&ctx);
5523
5524 FREE(outputs);
5525
5526 if (r != 0) {
5527 FREE(shader);
5528 shader = NULL;
5529 }
5530 return shader;
5531 }
5532
5533 static void si_dump_shader_key_vs(const struct si_shader_key *key,
5534 const struct si_vs_prolog_bits *prolog,
5535 const char *prefix, FILE *f)
5536 {
5537 fprintf(f, " %s.instance_divisor_is_one = %u\n",
5538 prefix, prolog->instance_divisor_is_one);
5539 fprintf(f, " %s.instance_divisor_is_fetched = %u\n",
5540 prefix, prolog->instance_divisor_is_fetched);
5541 fprintf(f, " %s.ls_vgpr_fix = %u\n",
5542 prefix, prolog->ls_vgpr_fix);
5543
5544 fprintf(f, " mono.vs.fix_fetch = {");
5545 for (int i = 0; i < SI_MAX_ATTRIBS; i++)
5546 fprintf(f, !i ? "%u" : ", %u", key->mono.vs_fix_fetch[i]);
5547 fprintf(f, "}\n");
5548 }
5549
5550 static void si_dump_shader_key(unsigned processor, const struct si_shader *shader,
5551 FILE *f)
5552 {
5553 const struct si_shader_key *key = &shader->key;
5554
5555 fprintf(f, "SHADER KEY\n");
5556
5557 switch (processor) {
5558 case PIPE_SHADER_VERTEX:
5559 si_dump_shader_key_vs(key, &key->part.vs.prolog,
5560 "part.vs.prolog", f);
5561 fprintf(f, " as_es = %u\n", key->as_es);
5562 fprintf(f, " as_ls = %u\n", key->as_ls);
5563 fprintf(f, " mono.u.vs_export_prim_id = %u\n",
5564 key->mono.u.vs_export_prim_id);
5565 break;
5566
5567 case PIPE_SHADER_TESS_CTRL:
5568 if (shader->selector->screen->info.chip_class >= GFX9) {
5569 si_dump_shader_key_vs(key, &key->part.tcs.ls_prolog,
5570 "part.tcs.ls_prolog", f);
5571 }
5572 fprintf(f, " part.tcs.epilog.prim_mode = %u\n", key->part.tcs.epilog.prim_mode);
5573 fprintf(f, " mono.u.ff_tcs_inputs_to_copy = 0x%"PRIx64"\n", key->mono.u.ff_tcs_inputs_to_copy);
5574 break;
5575
5576 case PIPE_SHADER_TESS_EVAL:
5577 fprintf(f, " as_es = %u\n", key->as_es);
5578 fprintf(f, " mono.u.vs_export_prim_id = %u\n",
5579 key->mono.u.vs_export_prim_id);
5580 break;
5581
5582 case PIPE_SHADER_GEOMETRY:
5583 if (shader->is_gs_copy_shader)
5584 break;
5585
5586 if (shader->selector->screen->info.chip_class >= GFX9 &&
5587 key->part.gs.es->type == PIPE_SHADER_VERTEX) {
5588 si_dump_shader_key_vs(key, &key->part.gs.vs_prolog,
5589 "part.gs.vs_prolog", f);
5590 }
5591 fprintf(f, " part.gs.prolog.tri_strip_adj_fix = %u\n", key->part.gs.prolog.tri_strip_adj_fix);
5592 break;
5593
5594 case PIPE_SHADER_COMPUTE:
5595 break;
5596
5597 case PIPE_SHADER_FRAGMENT:
5598 fprintf(f, " part.ps.prolog.color_two_side = %u\n", key->part.ps.prolog.color_two_side);
5599 fprintf(f, " part.ps.prolog.flatshade_colors = %u\n", key->part.ps.prolog.flatshade_colors);
5600 fprintf(f, " part.ps.prolog.poly_stipple = %u\n", key->part.ps.prolog.poly_stipple);
5601 fprintf(f, " part.ps.prolog.force_persp_sample_interp = %u\n", key->part.ps.prolog.force_persp_sample_interp);
5602 fprintf(f, " part.ps.prolog.force_linear_sample_interp = %u\n", key->part.ps.prolog.force_linear_sample_interp);
5603 fprintf(f, " part.ps.prolog.force_persp_center_interp = %u\n", key->part.ps.prolog.force_persp_center_interp);
5604 fprintf(f, " part.ps.prolog.force_linear_center_interp = %u\n", key->part.ps.prolog.force_linear_center_interp);
5605 fprintf(f, " part.ps.prolog.bc_optimize_for_persp = %u\n", key->part.ps.prolog.bc_optimize_for_persp);
5606 fprintf(f, " part.ps.prolog.bc_optimize_for_linear = %u\n", key->part.ps.prolog.bc_optimize_for_linear);
5607 fprintf(f, " part.ps.epilog.spi_shader_col_format = 0x%x\n", key->part.ps.epilog.spi_shader_col_format);
5608 fprintf(f, " part.ps.epilog.color_is_int8 = 0x%X\n", key->part.ps.epilog.color_is_int8);
5609 fprintf(f, " part.ps.epilog.color_is_int10 = 0x%X\n", key->part.ps.epilog.color_is_int10);
5610 fprintf(f, " part.ps.epilog.last_cbuf = %u\n", key->part.ps.epilog.last_cbuf);
5611 fprintf(f, " part.ps.epilog.alpha_func = %u\n", key->part.ps.epilog.alpha_func);
5612 fprintf(f, " part.ps.epilog.alpha_to_one = %u\n", key->part.ps.epilog.alpha_to_one);
5613 fprintf(f, " part.ps.epilog.poly_line_smoothing = %u\n", key->part.ps.epilog.poly_line_smoothing);
5614 fprintf(f, " part.ps.epilog.clamp_color = %u\n", key->part.ps.epilog.clamp_color);
5615 break;
5616
5617 default:
5618 assert(0);
5619 }
5620
5621 if ((processor == PIPE_SHADER_GEOMETRY ||
5622 processor == PIPE_SHADER_TESS_EVAL ||
5623 processor == PIPE_SHADER_VERTEX) &&
5624 !key->as_es && !key->as_ls) {
5625 fprintf(f, " opt.kill_outputs = 0x%"PRIx64"\n", key->opt.kill_outputs);
5626 fprintf(f, " opt.clip_disable = %u\n", key->opt.clip_disable);
5627 }
5628 }
5629
5630 static void si_init_shader_ctx(struct si_shader_context *ctx,
5631 struct si_screen *sscreen,
5632 LLVMTargetMachineRef tm)
5633 {
5634 struct lp_build_tgsi_context *bld_base;
5635
5636 si_llvm_context_init(ctx, sscreen, tm);
5637
5638 bld_base = &ctx->bld_base;
5639 bld_base->emit_fetch_funcs[TGSI_FILE_CONSTANT] = fetch_constant;
5640
5641 bld_base->op_actions[TGSI_OPCODE_INTERP_CENTROID] = interp_action;
5642 bld_base->op_actions[TGSI_OPCODE_INTERP_SAMPLE] = interp_action;
5643 bld_base->op_actions[TGSI_OPCODE_INTERP_OFFSET] = interp_action;
5644
5645 bld_base->op_actions[TGSI_OPCODE_MEMBAR].emit = membar_emit;
5646
5647 bld_base->op_actions[TGSI_OPCODE_CLOCK].emit = clock_emit;
5648
5649 bld_base->op_actions[TGSI_OPCODE_DDX].emit = si_llvm_emit_ddxy;
5650 bld_base->op_actions[TGSI_OPCODE_DDY].emit = si_llvm_emit_ddxy;
5651 bld_base->op_actions[TGSI_OPCODE_DDX_FINE].emit = si_llvm_emit_ddxy;
5652 bld_base->op_actions[TGSI_OPCODE_DDY_FINE].emit = si_llvm_emit_ddxy;
5653
5654 bld_base->op_actions[TGSI_OPCODE_VOTE_ALL].emit = vote_all_emit;
5655 bld_base->op_actions[TGSI_OPCODE_VOTE_ANY].emit = vote_any_emit;
5656 bld_base->op_actions[TGSI_OPCODE_VOTE_EQ].emit = vote_eq_emit;
5657 bld_base->op_actions[TGSI_OPCODE_BALLOT].emit = ballot_emit;
5658 bld_base->op_actions[TGSI_OPCODE_READ_FIRST].intr_name = "llvm.amdgcn.readfirstlane";
5659 bld_base->op_actions[TGSI_OPCODE_READ_FIRST].emit = read_lane_emit;
5660 bld_base->op_actions[TGSI_OPCODE_READ_INVOC].intr_name = "llvm.amdgcn.readlane";
5661 bld_base->op_actions[TGSI_OPCODE_READ_INVOC].fetch_args = read_invoc_fetch_args;
5662 bld_base->op_actions[TGSI_OPCODE_READ_INVOC].emit = read_lane_emit;
5663
5664 bld_base->op_actions[TGSI_OPCODE_EMIT].emit = si_tgsi_emit_vertex;
5665 bld_base->op_actions[TGSI_OPCODE_ENDPRIM].emit = si_llvm_emit_primitive;
5666 bld_base->op_actions[TGSI_OPCODE_BARRIER].emit = si_llvm_emit_barrier;
5667 }
5668
5669 static void si_optimize_vs_outputs(struct si_shader_context *ctx)
5670 {
5671 struct si_shader *shader = ctx->shader;
5672 struct tgsi_shader_info *info = &shader->selector->info;
5673
5674 if ((ctx->type != PIPE_SHADER_VERTEX &&
5675 ctx->type != PIPE_SHADER_TESS_EVAL) ||
5676 shader->key.as_ls ||
5677 shader->key.as_es)
5678 return;
5679
5680 ac_optimize_vs_outputs(&ctx->ac,
5681 ctx->main_fn,
5682 shader->info.vs_output_param_offset,
5683 info->num_outputs,
5684 &shader->info.nr_param_exports);
5685 }
5686
5687 static void si_count_scratch_private_memory(struct si_shader_context *ctx)
5688 {
5689 ctx->shader->config.private_mem_vgprs = 0;
5690
5691 /* Process all LLVM instructions. */
5692 LLVMBasicBlockRef bb = LLVMGetFirstBasicBlock(ctx->main_fn);
5693 while (bb) {
5694 LLVMValueRef next = LLVMGetFirstInstruction(bb);
5695
5696 while (next) {
5697 LLVMValueRef inst = next;
5698 next = LLVMGetNextInstruction(next);
5699
5700 if (LLVMGetInstructionOpcode(inst) != LLVMAlloca)
5701 continue;
5702
5703 LLVMTypeRef type = LLVMGetElementType(LLVMTypeOf(inst));
5704 /* No idea why LLVM aligns allocas to 4 elements. */
5705 unsigned alignment = LLVMGetAlignment(inst);
5706 unsigned dw_size = align(ac_get_type_size(type) / 4, alignment);
5707 ctx->shader->config.private_mem_vgprs += dw_size;
5708 }
5709 bb = LLVMGetNextBasicBlock(bb);
5710 }
5711 }
5712
5713 static void si_init_exec_full_mask(struct si_shader_context *ctx)
5714 {
5715 LLVMValueRef full_mask = LLVMConstInt(ctx->i64, ~0ull, 0);
5716 lp_build_intrinsic(ctx->ac.builder,
5717 "llvm.amdgcn.init.exec", ctx->voidt,
5718 &full_mask, 1, LP_FUNC_ATTR_CONVERGENT);
5719 }
5720
5721 static void si_init_exec_from_input(struct si_shader_context *ctx,
5722 unsigned param, unsigned bitoffset)
5723 {
5724 LLVMValueRef args[] = {
5725 LLVMGetParam(ctx->main_fn, param),
5726 LLVMConstInt(ctx->i32, bitoffset, 0),
5727 };
5728 lp_build_intrinsic(ctx->ac.builder,
5729 "llvm.amdgcn.init.exec.from.input",
5730 ctx->voidt, args, 2, LP_FUNC_ATTR_CONVERGENT);
5731 }
5732
5733 static bool si_vs_needs_prolog(const struct si_shader_selector *sel,
5734 const struct si_vs_prolog_bits *key)
5735 {
5736 /* VGPR initialization fixup for Vega10 and Raven is always done in the
5737 * VS prolog. */
5738 return sel->vs_needs_prolog || key->ls_vgpr_fix;
5739 }
5740
5741 static bool si_compile_tgsi_main(struct si_shader_context *ctx,
5742 bool is_monolithic)
5743 {
5744 struct si_shader *shader = ctx->shader;
5745 struct si_shader_selector *sel = shader->selector;
5746 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
5747
5748 // TODO clean all this up!
5749 switch (ctx->type) {
5750 case PIPE_SHADER_VERTEX:
5751 ctx->load_input = declare_input_vs;
5752 if (shader->key.as_ls)
5753 ctx->abi.emit_outputs = si_llvm_emit_ls_epilogue;
5754 else if (shader->key.as_es)
5755 ctx->abi.emit_outputs = si_llvm_emit_es_epilogue;
5756 else
5757 ctx->abi.emit_outputs = si_llvm_emit_vs_epilogue;
5758 bld_base->emit_epilogue = si_tgsi_emit_epilogue;
5759 break;
5760 case PIPE_SHADER_TESS_CTRL:
5761 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_tcs;
5762 bld_base->emit_fetch_funcs[TGSI_FILE_OUTPUT] = fetch_output_tcs;
5763 bld_base->emit_store = store_output_tcs;
5764 bld_base->emit_epilogue = si_llvm_emit_tcs_epilogue;
5765 break;
5766 case PIPE_SHADER_TESS_EVAL:
5767 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_tes;
5768 if (shader->key.as_es)
5769 ctx->abi.emit_outputs = si_llvm_emit_es_epilogue;
5770 else
5771 ctx->abi.emit_outputs = si_llvm_emit_vs_epilogue;
5772 bld_base->emit_epilogue = si_tgsi_emit_epilogue;
5773 break;
5774 case PIPE_SHADER_GEOMETRY:
5775 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_gs;
5776 ctx->abi.emit_vertex = si_llvm_emit_vertex;
5777 ctx->abi.emit_outputs = si_llvm_emit_gs_epilogue;
5778 bld_base->emit_epilogue = si_tgsi_emit_gs_epilogue;
5779 break;
5780 case PIPE_SHADER_FRAGMENT:
5781 ctx->load_input = declare_input_fs;
5782 ctx->abi.emit_outputs = si_llvm_return_fs_outputs;
5783 bld_base->emit_epilogue = si_tgsi_emit_epilogue;
5784 break;
5785 case PIPE_SHADER_COMPUTE:
5786 break;
5787 default:
5788 assert(!"Unsupported shader type");
5789 return false;
5790 }
5791
5792 ctx->abi.load_ubo = load_ubo;
5793 ctx->abi.load_ssbo = load_ssbo;
5794
5795 create_function(ctx);
5796 preload_ring_buffers(ctx);
5797
5798 /* For GFX9 merged shaders:
5799 * - Set EXEC for the first shader. If the prolog is present, set
5800 * EXEC there instead.
5801 * - Add a barrier before the second shader.
5802 * - In the second shader, reset EXEC to ~0 and wrap the main part in
5803 * an if-statement. This is required for correctness in geometry
5804 * shaders, to ensure that empty GS waves do not send GS_EMIT and
5805 * GS_CUT messages.
5806 *
5807 * For monolithic merged shaders, the first shader is wrapped in an
5808 * if-block together with its prolog in si_build_wrapper_function.
5809 */
5810 if (ctx->screen->info.chip_class >= GFX9) {
5811 if (!is_monolithic &&
5812 sel->info.num_instructions > 1 && /* not empty shader */
5813 (shader->key.as_es || shader->key.as_ls) &&
5814 (ctx->type == PIPE_SHADER_TESS_EVAL ||
5815 (ctx->type == PIPE_SHADER_VERTEX &&
5816 !si_vs_needs_prolog(sel, &shader->key.part.vs.prolog)))) {
5817 si_init_exec_from_input(ctx,
5818 ctx->param_merged_wave_info, 0);
5819 } else if (ctx->type == PIPE_SHADER_TESS_CTRL ||
5820 ctx->type == PIPE_SHADER_GEOMETRY) {
5821 if (!is_monolithic)
5822 si_init_exec_full_mask(ctx);
5823
5824 /* The barrier must execute for all shaders in a
5825 * threadgroup.
5826 */
5827 si_llvm_emit_barrier(NULL, bld_base, NULL);
5828
5829 LLVMValueRef num_threads = unpack_param(ctx, ctx->param_merged_wave_info, 8, 8);
5830 LLVMValueRef ena =
5831 LLVMBuildICmp(ctx->ac.builder, LLVMIntULT,
5832 ac_get_thread_id(&ctx->ac), num_threads, "");
5833 lp_build_if(&ctx->merged_wrap_if_state, &ctx->gallivm, ena);
5834 }
5835 }
5836
5837 if (ctx->type == PIPE_SHADER_TESS_CTRL &&
5838 sel->tcs_info.tessfactors_are_def_in_all_invocs) {
5839 for (unsigned i = 0; i < 6; i++) {
5840 ctx->invoc0_tess_factors[i] =
5841 lp_build_alloca_undef(&ctx->gallivm, ctx->i32, "");
5842 }
5843 }
5844
5845 if (ctx->type == PIPE_SHADER_GEOMETRY) {
5846 int i;
5847 for (i = 0; i < 4; i++) {
5848 ctx->gs_next_vertex[i] =
5849 lp_build_alloca(&ctx->gallivm,
5850 ctx->i32, "");
5851 }
5852 }
5853
5854 if (sel->force_correct_derivs_after_kill) {
5855 ctx->postponed_kill = lp_build_alloca_undef(&ctx->gallivm, ctx->i1, "");
5856 /* true = don't kill. */
5857 LLVMBuildStore(ctx->ac.builder, LLVMConstInt(ctx->i1, 1, 0),
5858 ctx->postponed_kill);
5859 }
5860
5861 if (sel->tokens) {
5862 if (!lp_build_tgsi_llvm(bld_base, sel->tokens)) {
5863 fprintf(stderr, "Failed to translate shader from TGSI to LLVM\n");
5864 return false;
5865 }
5866 } else {
5867 if (!si_nir_build_llvm(ctx, sel->nir)) {
5868 fprintf(stderr, "Failed to translate shader from NIR to LLVM\n");
5869 return false;
5870 }
5871 }
5872
5873 si_llvm_build_ret(ctx, ctx->return_value);
5874 return true;
5875 }
5876
5877 /**
5878 * Compute the VS prolog key, which contains all the information needed to
5879 * build the VS prolog function, and set shader->info bits where needed.
5880 *
5881 * \param info Shader info of the vertex shader.
5882 * \param num_input_sgprs Number of input SGPRs for the vertex shader.
5883 * \param prolog_key Key of the VS prolog
5884 * \param shader_out The vertex shader, or the next shader if merging LS+HS or ES+GS.
5885 * \param key Output shader part key.
5886 */
5887 static void si_get_vs_prolog_key(const struct tgsi_shader_info *info,
5888 unsigned num_input_sgprs,
5889 const struct si_vs_prolog_bits *prolog_key,
5890 struct si_shader *shader_out,
5891 union si_shader_part_key *key)
5892 {
5893 memset(key, 0, sizeof(*key));
5894 key->vs_prolog.states = *prolog_key;
5895 key->vs_prolog.num_input_sgprs = num_input_sgprs;
5896 key->vs_prolog.last_input = MAX2(1, info->num_inputs) - 1;
5897 key->vs_prolog.as_ls = shader_out->key.as_ls;
5898 key->vs_prolog.as_es = shader_out->key.as_es;
5899
5900 if (shader_out->selector->type == PIPE_SHADER_TESS_CTRL) {
5901 key->vs_prolog.as_ls = 1;
5902 key->vs_prolog.num_merged_next_stage_vgprs = 2;
5903 } else if (shader_out->selector->type == PIPE_SHADER_GEOMETRY) {
5904 key->vs_prolog.as_es = 1;
5905 key->vs_prolog.num_merged_next_stage_vgprs = 5;
5906 }
5907
5908 /* Enable loading the InstanceID VGPR. */
5909 uint16_t input_mask = u_bit_consecutive(0, info->num_inputs);
5910
5911 if ((key->vs_prolog.states.instance_divisor_is_one |
5912 key->vs_prolog.states.instance_divisor_is_fetched) & input_mask)
5913 shader_out->info.uses_instanceid = true;
5914 }
5915
5916 /**
5917 * Compute the PS prolog key, which contains all the information needed to
5918 * build the PS prolog function, and set related bits in shader->config.
5919 */
5920 static void si_get_ps_prolog_key(struct si_shader *shader,
5921 union si_shader_part_key *key,
5922 bool separate_prolog)
5923 {
5924 struct tgsi_shader_info *info = &shader->selector->info;
5925
5926 memset(key, 0, sizeof(*key));
5927 key->ps_prolog.states = shader->key.part.ps.prolog;
5928 key->ps_prolog.colors_read = info->colors_read;
5929 key->ps_prolog.num_input_sgprs = shader->info.num_input_sgprs;
5930 key->ps_prolog.num_input_vgprs = shader->info.num_input_vgprs;
5931 key->ps_prolog.wqm = info->uses_derivatives &&
5932 (key->ps_prolog.colors_read ||
5933 key->ps_prolog.states.force_persp_sample_interp ||
5934 key->ps_prolog.states.force_linear_sample_interp ||
5935 key->ps_prolog.states.force_persp_center_interp ||
5936 key->ps_prolog.states.force_linear_center_interp ||
5937 key->ps_prolog.states.bc_optimize_for_persp ||
5938 key->ps_prolog.states.bc_optimize_for_linear);
5939 key->ps_prolog.ancillary_vgpr_index = shader->info.ancillary_vgpr_index;
5940
5941 if (info->colors_read) {
5942 unsigned *color = shader->selector->color_attr_index;
5943
5944 if (shader->key.part.ps.prolog.color_two_side) {
5945 /* BCOLORs are stored after the last input. */
5946 key->ps_prolog.num_interp_inputs = info->num_inputs;
5947 key->ps_prolog.face_vgpr_index = shader->info.face_vgpr_index;
5948 shader->config.spi_ps_input_ena |= S_0286CC_FRONT_FACE_ENA(1);
5949 }
5950
5951 for (unsigned i = 0; i < 2; i++) {
5952 unsigned interp = info->input_interpolate[color[i]];
5953 unsigned location = info->input_interpolate_loc[color[i]];
5954
5955 if (!(info->colors_read & (0xf << i*4)))
5956 continue;
5957
5958 key->ps_prolog.color_attr_index[i] = color[i];
5959
5960 if (shader->key.part.ps.prolog.flatshade_colors &&
5961 interp == TGSI_INTERPOLATE_COLOR)
5962 interp = TGSI_INTERPOLATE_CONSTANT;
5963
5964 switch (interp) {
5965 case TGSI_INTERPOLATE_CONSTANT:
5966 key->ps_prolog.color_interp_vgpr_index[i] = -1;
5967 break;
5968 case TGSI_INTERPOLATE_PERSPECTIVE:
5969 case TGSI_INTERPOLATE_COLOR:
5970 /* Force the interpolation location for colors here. */
5971 if (shader->key.part.ps.prolog.force_persp_sample_interp)
5972 location = TGSI_INTERPOLATE_LOC_SAMPLE;
5973 if (shader->key.part.ps.prolog.force_persp_center_interp)
5974 location = TGSI_INTERPOLATE_LOC_CENTER;
5975
5976 switch (location) {
5977 case TGSI_INTERPOLATE_LOC_SAMPLE:
5978 key->ps_prolog.color_interp_vgpr_index[i] = 0;
5979 shader->config.spi_ps_input_ena |=
5980 S_0286CC_PERSP_SAMPLE_ENA(1);
5981 break;
5982 case TGSI_INTERPOLATE_LOC_CENTER:
5983 key->ps_prolog.color_interp_vgpr_index[i] = 2;
5984 shader->config.spi_ps_input_ena |=
5985 S_0286CC_PERSP_CENTER_ENA(1);
5986 break;
5987 case TGSI_INTERPOLATE_LOC_CENTROID:
5988 key->ps_prolog.color_interp_vgpr_index[i] = 4;
5989 shader->config.spi_ps_input_ena |=
5990 S_0286CC_PERSP_CENTROID_ENA(1);
5991 break;
5992 default:
5993 assert(0);
5994 }
5995 break;
5996 case TGSI_INTERPOLATE_LINEAR:
5997 /* Force the interpolation location for colors here. */
5998 if (shader->key.part.ps.prolog.force_linear_sample_interp)
5999 location = TGSI_INTERPOLATE_LOC_SAMPLE;
6000 if (shader->key.part.ps.prolog.force_linear_center_interp)
6001 location = TGSI_INTERPOLATE_LOC_CENTER;
6002
6003 /* The VGPR assignment for non-monolithic shaders
6004 * works because InitialPSInputAddr is set on the
6005 * main shader and PERSP_PULL_MODEL is never used.
6006 */
6007 switch (location) {
6008 case TGSI_INTERPOLATE_LOC_SAMPLE:
6009 key->ps_prolog.color_interp_vgpr_index[i] =
6010 separate_prolog ? 6 : 9;
6011 shader->config.spi_ps_input_ena |=
6012 S_0286CC_LINEAR_SAMPLE_ENA(1);
6013 break;
6014 case TGSI_INTERPOLATE_LOC_CENTER:
6015 key->ps_prolog.color_interp_vgpr_index[i] =
6016 separate_prolog ? 8 : 11;
6017 shader->config.spi_ps_input_ena |=
6018 S_0286CC_LINEAR_CENTER_ENA(1);
6019 break;
6020 case TGSI_INTERPOLATE_LOC_CENTROID:
6021 key->ps_prolog.color_interp_vgpr_index[i] =
6022 separate_prolog ? 10 : 13;
6023 shader->config.spi_ps_input_ena |=
6024 S_0286CC_LINEAR_CENTROID_ENA(1);
6025 break;
6026 default:
6027 assert(0);
6028 }
6029 break;
6030 default:
6031 assert(0);
6032 }
6033 }
6034 }
6035 }
6036
6037 /**
6038 * Check whether a PS prolog is required based on the key.
6039 */
6040 static bool si_need_ps_prolog(const union si_shader_part_key *key)
6041 {
6042 return key->ps_prolog.colors_read ||
6043 key->ps_prolog.states.force_persp_sample_interp ||
6044 key->ps_prolog.states.force_linear_sample_interp ||
6045 key->ps_prolog.states.force_persp_center_interp ||
6046 key->ps_prolog.states.force_linear_center_interp ||
6047 key->ps_prolog.states.bc_optimize_for_persp ||
6048 key->ps_prolog.states.bc_optimize_for_linear ||
6049 key->ps_prolog.states.poly_stipple ||
6050 key->ps_prolog.states.samplemask_log_ps_iter;
6051 }
6052
6053 /**
6054 * Compute the PS epilog key, which contains all the information needed to
6055 * build the PS epilog function.
6056 */
6057 static void si_get_ps_epilog_key(struct si_shader *shader,
6058 union si_shader_part_key *key)
6059 {
6060 struct tgsi_shader_info *info = &shader->selector->info;
6061 memset(key, 0, sizeof(*key));
6062 key->ps_epilog.colors_written = info->colors_written;
6063 key->ps_epilog.writes_z = info->writes_z;
6064 key->ps_epilog.writes_stencil = info->writes_stencil;
6065 key->ps_epilog.writes_samplemask = info->writes_samplemask;
6066 key->ps_epilog.states = shader->key.part.ps.epilog;
6067 }
6068
6069 /**
6070 * Build the GS prolog function. Rotate the input vertices for triangle strips
6071 * with adjacency.
6072 */
6073 static void si_build_gs_prolog_function(struct si_shader_context *ctx,
6074 union si_shader_part_key *key)
6075 {
6076 unsigned num_sgprs, num_vgprs;
6077 struct si_function_info fninfo;
6078 LLVMBuilderRef builder = ctx->ac.builder;
6079 LLVMTypeRef returns[48];
6080 LLVMValueRef func, ret;
6081
6082 si_init_function_info(&fninfo);
6083
6084 if (ctx->screen->info.chip_class >= GFX9) {
6085 num_sgprs = 8 + GFX9_GS_NUM_USER_SGPR;
6086 num_vgprs = 5; /* ES inputs are not needed by GS */
6087 } else {
6088 num_sgprs = GFX6_GS_NUM_USER_SGPR + 2;
6089 num_vgprs = 8;
6090 }
6091
6092 for (unsigned i = 0; i < num_sgprs; ++i) {
6093 add_arg(&fninfo, ARG_SGPR, ctx->i32);
6094 returns[i] = ctx->i32;
6095 }
6096
6097 for (unsigned i = 0; i < num_vgprs; ++i) {
6098 add_arg(&fninfo, ARG_VGPR, ctx->i32);
6099 returns[num_sgprs + i] = ctx->f32;
6100 }
6101
6102 /* Create the function. */
6103 si_create_function(ctx, "gs_prolog", returns, num_sgprs + num_vgprs,
6104 &fninfo, 0);
6105 func = ctx->main_fn;
6106
6107 /* Set the full EXEC mask for the prolog, because we are only fiddling
6108 * with registers here. The main shader part will set the correct EXEC
6109 * mask.
6110 */
6111 if (ctx->screen->info.chip_class >= GFX9 && !key->gs_prolog.is_monolithic)
6112 si_init_exec_full_mask(ctx);
6113
6114 /* Copy inputs to outputs. This should be no-op, as the registers match,
6115 * but it will prevent the compiler from overwriting them unintentionally.
6116 */
6117 ret = ctx->return_value;
6118 for (unsigned i = 0; i < num_sgprs; i++) {
6119 LLVMValueRef p = LLVMGetParam(func, i);
6120 ret = LLVMBuildInsertValue(builder, ret, p, i, "");
6121 }
6122 for (unsigned i = 0; i < num_vgprs; i++) {
6123 LLVMValueRef p = LLVMGetParam(func, num_sgprs + i);
6124 p = ac_to_float(&ctx->ac, p);
6125 ret = LLVMBuildInsertValue(builder, ret, p, num_sgprs + i, "");
6126 }
6127
6128 if (key->gs_prolog.states.tri_strip_adj_fix) {
6129 /* Remap the input vertices for every other primitive. */
6130 const unsigned gfx6_vtx_params[6] = {
6131 num_sgprs,
6132 num_sgprs + 1,
6133 num_sgprs + 3,
6134 num_sgprs + 4,
6135 num_sgprs + 5,
6136 num_sgprs + 6
6137 };
6138 const unsigned gfx9_vtx_params[3] = {
6139 num_sgprs,
6140 num_sgprs + 1,
6141 num_sgprs + 4,
6142 };
6143 LLVMValueRef vtx_in[6], vtx_out[6];
6144 LLVMValueRef prim_id, rotate;
6145
6146 if (ctx->screen->info.chip_class >= GFX9) {
6147 for (unsigned i = 0; i < 3; i++) {
6148 vtx_in[i*2] = unpack_param(ctx, gfx9_vtx_params[i], 0, 16);
6149 vtx_in[i*2+1] = unpack_param(ctx, gfx9_vtx_params[i], 16, 16);
6150 }
6151 } else {
6152 for (unsigned i = 0; i < 6; i++)
6153 vtx_in[i] = LLVMGetParam(func, gfx6_vtx_params[i]);
6154 }
6155
6156 prim_id = LLVMGetParam(func, num_sgprs + 2);
6157 rotate = LLVMBuildTrunc(builder, prim_id, ctx->i1, "");
6158
6159 for (unsigned i = 0; i < 6; ++i) {
6160 LLVMValueRef base, rotated;
6161 base = vtx_in[i];
6162 rotated = vtx_in[(i + 4) % 6];
6163 vtx_out[i] = LLVMBuildSelect(builder, rotate, rotated, base, "");
6164 }
6165
6166 if (ctx->screen->info.chip_class >= GFX9) {
6167 for (unsigned i = 0; i < 3; i++) {
6168 LLVMValueRef hi, out;
6169
6170 hi = LLVMBuildShl(builder, vtx_out[i*2+1],
6171 LLVMConstInt(ctx->i32, 16, 0), "");
6172 out = LLVMBuildOr(builder, vtx_out[i*2], hi, "");
6173 out = ac_to_float(&ctx->ac, out);
6174 ret = LLVMBuildInsertValue(builder, ret, out,
6175 gfx9_vtx_params[i], "");
6176 }
6177 } else {
6178 for (unsigned i = 0; i < 6; i++) {
6179 LLVMValueRef out;
6180
6181 out = ac_to_float(&ctx->ac, vtx_out[i]);
6182 ret = LLVMBuildInsertValue(builder, ret, out,
6183 gfx6_vtx_params[i], "");
6184 }
6185 }
6186 }
6187
6188 LLVMBuildRet(builder, ret);
6189 }
6190
6191 /**
6192 * Given a list of shader part functions, build a wrapper function that
6193 * runs them in sequence to form a monolithic shader.
6194 */
6195 static void si_build_wrapper_function(struct si_shader_context *ctx,
6196 LLVMValueRef *parts,
6197 unsigned num_parts,
6198 unsigned main_part,
6199 unsigned next_shader_first_part)
6200 {
6201 LLVMBuilderRef builder = ctx->ac.builder;
6202 /* PS epilog has one arg per color component; gfx9 merged shader
6203 * prologs need to forward 32 user SGPRs.
6204 */
6205 struct si_function_info fninfo;
6206 LLVMValueRef initial[64], out[64];
6207 LLVMTypeRef function_type;
6208 unsigned num_first_params;
6209 unsigned num_out, initial_num_out;
6210 MAYBE_UNUSED unsigned num_out_sgpr; /* used in debug checks */
6211 MAYBE_UNUSED unsigned initial_num_out_sgpr; /* used in debug checks */
6212 unsigned num_sgprs, num_vgprs;
6213 unsigned gprs;
6214 struct lp_build_if_state if_state;
6215
6216 si_init_function_info(&fninfo);
6217
6218 for (unsigned i = 0; i < num_parts; ++i) {
6219 lp_add_function_attr(parts[i], -1, LP_FUNC_ATTR_ALWAYSINLINE);
6220 LLVMSetLinkage(parts[i], LLVMPrivateLinkage);
6221 }
6222
6223 /* The parameters of the wrapper function correspond to those of the
6224 * first part in terms of SGPRs and VGPRs, but we use the types of the
6225 * main part to get the right types. This is relevant for the
6226 * dereferenceable attribute on descriptor table pointers.
6227 */
6228 num_sgprs = 0;
6229 num_vgprs = 0;
6230
6231 function_type = LLVMGetElementType(LLVMTypeOf(parts[0]));
6232 num_first_params = LLVMCountParamTypes(function_type);
6233
6234 for (unsigned i = 0; i < num_first_params; ++i) {
6235 LLVMValueRef param = LLVMGetParam(parts[0], i);
6236
6237 if (ac_is_sgpr_param(param)) {
6238 assert(num_vgprs == 0);
6239 num_sgprs += ac_get_type_size(LLVMTypeOf(param)) / 4;
6240 } else {
6241 num_vgprs += ac_get_type_size(LLVMTypeOf(param)) / 4;
6242 }
6243 }
6244
6245 gprs = 0;
6246 while (gprs < num_sgprs + num_vgprs) {
6247 LLVMValueRef param = LLVMGetParam(parts[main_part], fninfo.num_params);
6248 LLVMTypeRef type = LLVMTypeOf(param);
6249 unsigned size = ac_get_type_size(type) / 4;
6250
6251 add_arg(&fninfo, gprs < num_sgprs ? ARG_SGPR : ARG_VGPR, type);
6252
6253 assert(ac_is_sgpr_param(param) == (gprs < num_sgprs));
6254 assert(gprs + size <= num_sgprs + num_vgprs &&
6255 (gprs >= num_sgprs || gprs + size <= num_sgprs));
6256
6257 gprs += size;
6258 }
6259
6260 si_create_function(ctx, "wrapper", NULL, 0, &fninfo,
6261 si_get_max_workgroup_size(ctx->shader));
6262
6263 if (is_merged_shader(ctx->shader))
6264 si_init_exec_full_mask(ctx);
6265
6266 /* Record the arguments of the function as if they were an output of
6267 * a previous part.
6268 */
6269 num_out = 0;
6270 num_out_sgpr = 0;
6271
6272 for (unsigned i = 0; i < fninfo.num_params; ++i) {
6273 LLVMValueRef param = LLVMGetParam(ctx->main_fn, i);
6274 LLVMTypeRef param_type = LLVMTypeOf(param);
6275 LLVMTypeRef out_type = i < fninfo.num_sgpr_params ? ctx->i32 : ctx->f32;
6276 unsigned size = ac_get_type_size(param_type) / 4;
6277
6278 if (size == 1) {
6279 if (param_type != out_type)
6280 param = LLVMBuildBitCast(builder, param, out_type, "");
6281 out[num_out++] = param;
6282 } else {
6283 LLVMTypeRef vector_type = LLVMVectorType(out_type, size);
6284
6285 if (LLVMGetTypeKind(param_type) == LLVMPointerTypeKind) {
6286 param = LLVMBuildPtrToInt(builder, param, ctx->i64, "");
6287 param_type = ctx->i64;
6288 }
6289
6290 if (param_type != vector_type)
6291 param = LLVMBuildBitCast(builder, param, vector_type, "");
6292
6293 for (unsigned j = 0; j < size; ++j)
6294 out[num_out++] = LLVMBuildExtractElement(
6295 builder, param, LLVMConstInt(ctx->i32, j, 0), "");
6296 }
6297
6298 if (i < fninfo.num_sgpr_params)
6299 num_out_sgpr = num_out;
6300 }
6301
6302 memcpy(initial, out, sizeof(out));
6303 initial_num_out = num_out;
6304 initial_num_out_sgpr = num_out_sgpr;
6305
6306 /* Now chain the parts. */
6307 for (unsigned part = 0; part < num_parts; ++part) {
6308 LLVMValueRef in[48];
6309 LLVMValueRef ret;
6310 LLVMTypeRef ret_type;
6311 unsigned out_idx = 0;
6312 unsigned num_params = LLVMCountParams(parts[part]);
6313
6314 /* Merged shaders are executed conditionally depending
6315 * on the number of enabled threads passed in the input SGPRs. */
6316 if (is_merged_shader(ctx->shader) && part == 0) {
6317 LLVMValueRef ena, count = initial[3];
6318
6319 count = LLVMBuildAnd(builder, count,
6320 LLVMConstInt(ctx->i32, 0x7f, 0), "");
6321 ena = LLVMBuildICmp(builder, LLVMIntULT,
6322 ac_get_thread_id(&ctx->ac), count, "");
6323 lp_build_if(&if_state, &ctx->gallivm, ena);
6324 }
6325
6326 /* Derive arguments for the next part from outputs of the
6327 * previous one.
6328 */
6329 for (unsigned param_idx = 0; param_idx < num_params; ++param_idx) {
6330 LLVMValueRef param;
6331 LLVMTypeRef param_type;
6332 bool is_sgpr;
6333 unsigned param_size;
6334 LLVMValueRef arg = NULL;
6335
6336 param = LLVMGetParam(parts[part], param_idx);
6337 param_type = LLVMTypeOf(param);
6338 param_size = ac_get_type_size(param_type) / 4;
6339 is_sgpr = ac_is_sgpr_param(param);
6340
6341 if (is_sgpr) {
6342 #if HAVE_LLVM < 0x0400
6343 LLVMRemoveAttribute(param, LLVMByValAttribute);
6344 #else
6345 unsigned kind_id = LLVMGetEnumAttributeKindForName("byval", 5);
6346 LLVMRemoveEnumAttributeAtIndex(parts[part], param_idx + 1, kind_id);
6347 #endif
6348 lp_add_function_attr(parts[part], param_idx + 1, LP_FUNC_ATTR_INREG);
6349 }
6350
6351 assert(out_idx + param_size <= (is_sgpr ? num_out_sgpr : num_out));
6352 assert(is_sgpr || out_idx >= num_out_sgpr);
6353
6354 if (param_size == 1)
6355 arg = out[out_idx];
6356 else
6357 arg = lp_build_gather_values(&ctx->gallivm, &out[out_idx], param_size);
6358
6359 if (LLVMTypeOf(arg) != param_type) {
6360 if (LLVMGetTypeKind(param_type) == LLVMPointerTypeKind) {
6361 arg = LLVMBuildBitCast(builder, arg, ctx->i64, "");
6362 arg = LLVMBuildIntToPtr(builder, arg, param_type, "");
6363 } else {
6364 arg = LLVMBuildBitCast(builder, arg, param_type, "");
6365 }
6366 }
6367
6368 in[param_idx] = arg;
6369 out_idx += param_size;
6370 }
6371
6372 ret = LLVMBuildCall(builder, parts[part], in, num_params, "");
6373
6374 if (is_merged_shader(ctx->shader) &&
6375 part + 1 == next_shader_first_part) {
6376 lp_build_endif(&if_state);
6377
6378 /* The second half of the merged shader should use
6379 * the inputs from the toplevel (wrapper) function,
6380 * not the return value from the last call.
6381 *
6382 * That's because the last call was executed condi-
6383 * tionally, so we can't consume it in the main
6384 * block.
6385 */
6386 memcpy(out, initial, sizeof(initial));
6387 num_out = initial_num_out;
6388 num_out_sgpr = initial_num_out_sgpr;
6389 continue;
6390 }
6391
6392 /* Extract the returned GPRs. */
6393 ret_type = LLVMTypeOf(ret);
6394 num_out = 0;
6395 num_out_sgpr = 0;
6396
6397 if (LLVMGetTypeKind(ret_type) != LLVMVoidTypeKind) {
6398 assert(LLVMGetTypeKind(ret_type) == LLVMStructTypeKind);
6399
6400 unsigned ret_size = LLVMCountStructElementTypes(ret_type);
6401
6402 for (unsigned i = 0; i < ret_size; ++i) {
6403 LLVMValueRef val =
6404 LLVMBuildExtractValue(builder, ret, i, "");
6405
6406 assert(num_out < ARRAY_SIZE(out));
6407 out[num_out++] = val;
6408
6409 if (LLVMTypeOf(val) == ctx->i32) {
6410 assert(num_out_sgpr + 1 == num_out);
6411 num_out_sgpr = num_out;
6412 }
6413 }
6414 }
6415 }
6416
6417 LLVMBuildRetVoid(builder);
6418 }
6419
6420 int si_compile_tgsi_shader(struct si_screen *sscreen,
6421 LLVMTargetMachineRef tm,
6422 struct si_shader *shader,
6423 bool is_monolithic,
6424 struct pipe_debug_callback *debug)
6425 {
6426 struct si_shader_selector *sel = shader->selector;
6427 struct si_shader_context ctx;
6428 int r = -1;
6429
6430 /* Dump TGSI code before doing TGSI->LLVM conversion in case the
6431 * conversion fails. */
6432 if (si_can_dump_shader(sscreen, sel->info.processor) &&
6433 !(sscreen->debug_flags & DBG(NO_TGSI))) {
6434 if (sel->tokens)
6435 tgsi_dump(sel->tokens, 0);
6436 else
6437 nir_print_shader(sel->nir, stderr);
6438 si_dump_streamout(&sel->so);
6439 }
6440
6441 si_init_shader_ctx(&ctx, sscreen, tm);
6442 si_llvm_context_set_tgsi(&ctx, shader);
6443 ctx.separate_prolog = !is_monolithic;
6444
6445 memset(shader->info.vs_output_param_offset, AC_EXP_PARAM_UNDEFINED,
6446 sizeof(shader->info.vs_output_param_offset));
6447
6448 shader->info.uses_instanceid = sel->info.uses_instanceid;
6449
6450 if (!si_compile_tgsi_main(&ctx, is_monolithic)) {
6451 si_llvm_dispose(&ctx);
6452 return -1;
6453 }
6454
6455 if (is_monolithic && ctx.type == PIPE_SHADER_VERTEX) {
6456 LLVMValueRef parts[2];
6457 bool need_prolog = sel->vs_needs_prolog;
6458
6459 parts[1] = ctx.main_fn;
6460
6461 if (need_prolog) {
6462 union si_shader_part_key prolog_key;
6463 si_get_vs_prolog_key(&sel->info,
6464 shader->info.num_input_sgprs,
6465 &shader->key.part.vs.prolog,
6466 shader, &prolog_key);
6467 si_build_vs_prolog_function(&ctx, &prolog_key);
6468 parts[0] = ctx.main_fn;
6469 }
6470
6471 si_build_wrapper_function(&ctx, parts + !need_prolog,
6472 1 + need_prolog, need_prolog, 0);
6473 } else if (is_monolithic && ctx.type == PIPE_SHADER_TESS_CTRL) {
6474 if (sscreen->info.chip_class >= GFX9) {
6475 struct si_shader_selector *ls = shader->key.part.tcs.ls;
6476 LLVMValueRef parts[4];
6477 bool vs_needs_prolog =
6478 si_vs_needs_prolog(ls, &shader->key.part.tcs.ls_prolog);
6479
6480 /* TCS main part */
6481 parts[2] = ctx.main_fn;
6482
6483 /* TCS epilog */
6484 union si_shader_part_key tcs_epilog_key;
6485 memset(&tcs_epilog_key, 0, sizeof(tcs_epilog_key));
6486 tcs_epilog_key.tcs_epilog.states = shader->key.part.tcs.epilog;
6487 si_build_tcs_epilog_function(&ctx, &tcs_epilog_key);
6488 parts[3] = ctx.main_fn;
6489
6490 /* VS prolog */
6491 if (vs_needs_prolog) {
6492 union si_shader_part_key vs_prolog_key;
6493 si_get_vs_prolog_key(&ls->info,
6494 shader->info.num_input_sgprs,
6495 &shader->key.part.tcs.ls_prolog,
6496 shader, &vs_prolog_key);
6497 vs_prolog_key.vs_prolog.is_monolithic = true;
6498 si_build_vs_prolog_function(&ctx, &vs_prolog_key);
6499 parts[0] = ctx.main_fn;
6500 }
6501
6502 /* VS as LS main part */
6503 struct si_shader shader_ls = {};
6504 shader_ls.selector = ls;
6505 shader_ls.key.as_ls = 1;
6506 shader_ls.key.mono = shader->key.mono;
6507 shader_ls.key.opt = shader->key.opt;
6508 si_llvm_context_set_tgsi(&ctx, &shader_ls);
6509
6510 if (!si_compile_tgsi_main(&ctx, true)) {
6511 si_llvm_dispose(&ctx);
6512 return -1;
6513 }
6514 shader->info.uses_instanceid |= ls->info.uses_instanceid;
6515 parts[1] = ctx.main_fn;
6516
6517 /* Reset the shader context. */
6518 ctx.shader = shader;
6519 ctx.type = PIPE_SHADER_TESS_CTRL;
6520
6521 si_build_wrapper_function(&ctx,
6522 parts + !vs_needs_prolog,
6523 4 - !vs_needs_prolog, 0,
6524 vs_needs_prolog ? 2 : 1);
6525 } else {
6526 LLVMValueRef parts[2];
6527 union si_shader_part_key epilog_key;
6528
6529 parts[0] = ctx.main_fn;
6530
6531 memset(&epilog_key, 0, sizeof(epilog_key));
6532 epilog_key.tcs_epilog.states = shader->key.part.tcs.epilog;
6533 si_build_tcs_epilog_function(&ctx, &epilog_key);
6534 parts[1] = ctx.main_fn;
6535
6536 si_build_wrapper_function(&ctx, parts, 2, 0, 0);
6537 }
6538 } else if (is_monolithic && ctx.type == PIPE_SHADER_GEOMETRY) {
6539 if (ctx.screen->info.chip_class >= GFX9) {
6540 struct si_shader_selector *es = shader->key.part.gs.es;
6541 LLVMValueRef es_prolog = NULL;
6542 LLVMValueRef es_main = NULL;
6543 LLVMValueRef gs_prolog = NULL;
6544 LLVMValueRef gs_main = ctx.main_fn;
6545
6546 /* GS prolog */
6547 union si_shader_part_key gs_prolog_key;
6548 memset(&gs_prolog_key, 0, sizeof(gs_prolog_key));
6549 gs_prolog_key.gs_prolog.states = shader->key.part.gs.prolog;
6550 gs_prolog_key.gs_prolog.is_monolithic = true;
6551 si_build_gs_prolog_function(&ctx, &gs_prolog_key);
6552 gs_prolog = ctx.main_fn;
6553
6554 /* ES prolog */
6555 if (es->vs_needs_prolog) {
6556 union si_shader_part_key vs_prolog_key;
6557 si_get_vs_prolog_key(&es->info,
6558 shader->info.num_input_sgprs,
6559 &shader->key.part.gs.vs_prolog,
6560 shader, &vs_prolog_key);
6561 vs_prolog_key.vs_prolog.is_monolithic = true;
6562 si_build_vs_prolog_function(&ctx, &vs_prolog_key);
6563 es_prolog = ctx.main_fn;
6564 }
6565
6566 /* ES main part */
6567 struct si_shader shader_es = {};
6568 shader_es.selector = es;
6569 shader_es.key.as_es = 1;
6570 shader_es.key.mono = shader->key.mono;
6571 shader_es.key.opt = shader->key.opt;
6572 si_llvm_context_set_tgsi(&ctx, &shader_es);
6573
6574 if (!si_compile_tgsi_main(&ctx, true)) {
6575 si_llvm_dispose(&ctx);
6576 return -1;
6577 }
6578 shader->info.uses_instanceid |= es->info.uses_instanceid;
6579 es_main = ctx.main_fn;
6580
6581 /* Reset the shader context. */
6582 ctx.shader = shader;
6583 ctx.type = PIPE_SHADER_GEOMETRY;
6584
6585 /* Prepare the array of shader parts. */
6586 LLVMValueRef parts[4];
6587 unsigned num_parts = 0, main_part, next_first_part;
6588
6589 if (es_prolog)
6590 parts[num_parts++] = es_prolog;
6591
6592 parts[main_part = num_parts++] = es_main;
6593 parts[next_first_part = num_parts++] = gs_prolog;
6594 parts[num_parts++] = gs_main;
6595
6596 si_build_wrapper_function(&ctx, parts, num_parts,
6597 main_part, next_first_part);
6598 } else {
6599 LLVMValueRef parts[2];
6600 union si_shader_part_key prolog_key;
6601
6602 parts[1] = ctx.main_fn;
6603
6604 memset(&prolog_key, 0, sizeof(prolog_key));
6605 prolog_key.gs_prolog.states = shader->key.part.gs.prolog;
6606 si_build_gs_prolog_function(&ctx, &prolog_key);
6607 parts[0] = ctx.main_fn;
6608
6609 si_build_wrapper_function(&ctx, parts, 2, 1, 0);
6610 }
6611 } else if (is_monolithic && ctx.type == PIPE_SHADER_FRAGMENT) {
6612 LLVMValueRef parts[3];
6613 union si_shader_part_key prolog_key;
6614 union si_shader_part_key epilog_key;
6615 bool need_prolog;
6616
6617 si_get_ps_prolog_key(shader, &prolog_key, false);
6618 need_prolog = si_need_ps_prolog(&prolog_key);
6619
6620 parts[need_prolog ? 1 : 0] = ctx.main_fn;
6621
6622 if (need_prolog) {
6623 si_build_ps_prolog_function(&ctx, &prolog_key);
6624 parts[0] = ctx.main_fn;
6625 }
6626
6627 si_get_ps_epilog_key(shader, &epilog_key);
6628 si_build_ps_epilog_function(&ctx, &epilog_key);
6629 parts[need_prolog ? 2 : 1] = ctx.main_fn;
6630
6631 si_build_wrapper_function(&ctx, parts, need_prolog ? 3 : 2,
6632 need_prolog ? 1 : 0, 0);
6633 }
6634
6635 si_llvm_optimize_module(&ctx);
6636
6637 /* Post-optimization transformations and analysis. */
6638 si_optimize_vs_outputs(&ctx);
6639
6640 if ((debug && debug->debug_message) ||
6641 si_can_dump_shader(sscreen, ctx.type))
6642 si_count_scratch_private_memory(&ctx);
6643
6644 /* Compile to bytecode. */
6645 r = si_compile_llvm(sscreen, &shader->binary, &shader->config, tm,
6646 ctx.gallivm.module, debug, ctx.type, "TGSI shader");
6647 si_llvm_dispose(&ctx);
6648 if (r) {
6649 fprintf(stderr, "LLVM failed to compile shader\n");
6650 return r;
6651 }
6652
6653 /* Validate SGPR and VGPR usage for compute to detect compiler bugs.
6654 * LLVM 3.9svn has this bug.
6655 */
6656 if (sel->type == PIPE_SHADER_COMPUTE) {
6657 unsigned wave_size = 64;
6658 unsigned max_vgprs = 256;
6659 unsigned max_sgprs = sscreen->info.chip_class >= VI ? 800 : 512;
6660 unsigned max_sgprs_per_wave = 128;
6661 unsigned max_block_threads = si_get_max_workgroup_size(shader);
6662 unsigned min_waves_per_cu = DIV_ROUND_UP(max_block_threads, wave_size);
6663 unsigned min_waves_per_simd = DIV_ROUND_UP(min_waves_per_cu, 4);
6664
6665 max_vgprs = max_vgprs / min_waves_per_simd;
6666 max_sgprs = MIN2(max_sgprs / min_waves_per_simd, max_sgprs_per_wave);
6667
6668 if (shader->config.num_sgprs > max_sgprs ||
6669 shader->config.num_vgprs > max_vgprs) {
6670 fprintf(stderr, "LLVM failed to compile a shader correctly: "
6671 "SGPR:VGPR usage is %u:%u, but the hw limit is %u:%u\n",
6672 shader->config.num_sgprs, shader->config.num_vgprs,
6673 max_sgprs, max_vgprs);
6674
6675 /* Just terminate the process, because dependent
6676 * shaders can hang due to bad input data, but use
6677 * the env var to allow shader-db to work.
6678 */
6679 if (!debug_get_bool_option("SI_PASS_BAD_SHADERS", false))
6680 abort();
6681 }
6682 }
6683
6684 /* Add the scratch offset to input SGPRs. */
6685 if (shader->config.scratch_bytes_per_wave && !is_merged_shader(shader))
6686 shader->info.num_input_sgprs += 1; /* scratch byte offset */
6687
6688 /* Calculate the number of fragment input VGPRs. */
6689 if (ctx.type == PIPE_SHADER_FRAGMENT) {
6690 shader->info.num_input_vgprs = 0;
6691 shader->info.face_vgpr_index = -1;
6692 shader->info.ancillary_vgpr_index = -1;
6693
6694 if (G_0286CC_PERSP_SAMPLE_ENA(shader->config.spi_ps_input_addr))
6695 shader->info.num_input_vgprs += 2;
6696 if (G_0286CC_PERSP_CENTER_ENA(shader->config.spi_ps_input_addr))
6697 shader->info.num_input_vgprs += 2;
6698 if (G_0286CC_PERSP_CENTROID_ENA(shader->config.spi_ps_input_addr))
6699 shader->info.num_input_vgprs += 2;
6700 if (G_0286CC_PERSP_PULL_MODEL_ENA(shader->config.spi_ps_input_addr))
6701 shader->info.num_input_vgprs += 3;
6702 if (G_0286CC_LINEAR_SAMPLE_ENA(shader->config.spi_ps_input_addr))
6703 shader->info.num_input_vgprs += 2;
6704 if (G_0286CC_LINEAR_CENTER_ENA(shader->config.spi_ps_input_addr))
6705 shader->info.num_input_vgprs += 2;
6706 if (G_0286CC_LINEAR_CENTROID_ENA(shader->config.spi_ps_input_addr))
6707 shader->info.num_input_vgprs += 2;
6708 if (G_0286CC_LINE_STIPPLE_TEX_ENA(shader->config.spi_ps_input_addr))
6709 shader->info.num_input_vgprs += 1;
6710 if (G_0286CC_POS_X_FLOAT_ENA(shader->config.spi_ps_input_addr))
6711 shader->info.num_input_vgprs += 1;
6712 if (G_0286CC_POS_Y_FLOAT_ENA(shader->config.spi_ps_input_addr))
6713 shader->info.num_input_vgprs += 1;
6714 if (G_0286CC_POS_Z_FLOAT_ENA(shader->config.spi_ps_input_addr))
6715 shader->info.num_input_vgprs += 1;
6716 if (G_0286CC_POS_W_FLOAT_ENA(shader->config.spi_ps_input_addr))
6717 shader->info.num_input_vgprs += 1;
6718 if (G_0286CC_FRONT_FACE_ENA(shader->config.spi_ps_input_addr)) {
6719 shader->info.face_vgpr_index = shader->info.num_input_vgprs;
6720 shader->info.num_input_vgprs += 1;
6721 }
6722 if (G_0286CC_ANCILLARY_ENA(shader->config.spi_ps_input_addr)) {
6723 shader->info.ancillary_vgpr_index = shader->info.num_input_vgprs;
6724 shader->info.num_input_vgprs += 1;
6725 }
6726 if (G_0286CC_SAMPLE_COVERAGE_ENA(shader->config.spi_ps_input_addr))
6727 shader->info.num_input_vgprs += 1;
6728 if (G_0286CC_POS_FIXED_PT_ENA(shader->config.spi_ps_input_addr))
6729 shader->info.num_input_vgprs += 1;
6730 }
6731
6732 return 0;
6733 }
6734
6735 /**
6736 * Create, compile and return a shader part (prolog or epilog).
6737 *
6738 * \param sscreen screen
6739 * \param list list of shader parts of the same category
6740 * \param type shader type
6741 * \param key shader part key
6742 * \param prolog whether the part being requested is a prolog
6743 * \param tm LLVM target machine
6744 * \param debug debug callback
6745 * \param build the callback responsible for building the main function
6746 * \return non-NULL on success
6747 */
6748 static struct si_shader_part *
6749 si_get_shader_part(struct si_screen *sscreen,
6750 struct si_shader_part **list,
6751 enum pipe_shader_type type,
6752 bool prolog,
6753 union si_shader_part_key *key,
6754 LLVMTargetMachineRef tm,
6755 struct pipe_debug_callback *debug,
6756 void (*build)(struct si_shader_context *,
6757 union si_shader_part_key *),
6758 const char *name)
6759 {
6760 struct si_shader_part *result;
6761
6762 mtx_lock(&sscreen->shader_parts_mutex);
6763
6764 /* Find existing. */
6765 for (result = *list; result; result = result->next) {
6766 if (memcmp(&result->key, key, sizeof(*key)) == 0) {
6767 mtx_unlock(&sscreen->shader_parts_mutex);
6768 return result;
6769 }
6770 }
6771
6772 /* Compile a new one. */
6773 result = CALLOC_STRUCT(si_shader_part);
6774 result->key = *key;
6775
6776 struct si_shader shader = {};
6777 struct si_shader_context ctx;
6778
6779 si_init_shader_ctx(&ctx, sscreen, tm);
6780 ctx.shader = &shader;
6781 ctx.type = type;
6782
6783 switch (type) {
6784 case PIPE_SHADER_VERTEX:
6785 shader.key.as_ls = key->vs_prolog.as_ls;
6786 shader.key.as_es = key->vs_prolog.as_es;
6787 break;
6788 case PIPE_SHADER_TESS_CTRL:
6789 assert(!prolog);
6790 shader.key.part.tcs.epilog = key->tcs_epilog.states;
6791 break;
6792 case PIPE_SHADER_GEOMETRY:
6793 assert(prolog);
6794 break;
6795 case PIPE_SHADER_FRAGMENT:
6796 if (prolog)
6797 shader.key.part.ps.prolog = key->ps_prolog.states;
6798 else
6799 shader.key.part.ps.epilog = key->ps_epilog.states;
6800 break;
6801 default:
6802 unreachable("bad shader part");
6803 }
6804
6805 build(&ctx, key);
6806
6807 /* Compile. */
6808 si_llvm_optimize_module(&ctx);
6809
6810 if (si_compile_llvm(sscreen, &result->binary, &result->config, tm,
6811 ctx.ac.module, debug, ctx.type, name)) {
6812 FREE(result);
6813 result = NULL;
6814 goto out;
6815 }
6816
6817 result->next = *list;
6818 *list = result;
6819
6820 out:
6821 si_llvm_dispose(&ctx);
6822 mtx_unlock(&sscreen->shader_parts_mutex);
6823 return result;
6824 }
6825
6826 static LLVMValueRef si_prolog_get_rw_buffers(struct si_shader_context *ctx)
6827 {
6828 LLVMValueRef ptr[2], list;
6829 bool is_merged_shader =
6830 ctx->screen->info.chip_class >= GFX9 &&
6831 (ctx->type == PIPE_SHADER_TESS_CTRL ||
6832 ctx->type == PIPE_SHADER_GEOMETRY ||
6833 ctx->shader->key.as_ls || ctx->shader->key.as_es);
6834
6835 /* Get the pointer to rw buffers. */
6836 ptr[0] = LLVMGetParam(ctx->main_fn, (is_merged_shader ? 8 : 0) + SI_SGPR_RW_BUFFERS);
6837 ptr[1] = LLVMGetParam(ctx->main_fn, (is_merged_shader ? 8 : 0) + SI_SGPR_RW_BUFFERS_HI);
6838 list = lp_build_gather_values(&ctx->gallivm, ptr, 2);
6839 list = LLVMBuildBitCast(ctx->ac.builder, list, ctx->i64, "");
6840 list = LLVMBuildIntToPtr(ctx->ac.builder, list,
6841 si_const_array(ctx->v4i32, SI_NUM_RW_BUFFERS), "");
6842 return list;
6843 }
6844
6845 /**
6846 * Build the vertex shader prolog function.
6847 *
6848 * The inputs are the same as VS (a lot of SGPRs and 4 VGPR system values).
6849 * All inputs are returned unmodified. The vertex load indices are
6850 * stored after them, which will be used by the API VS for fetching inputs.
6851 *
6852 * For example, the expected outputs for instance_divisors[] = {0, 1, 2} are:
6853 * input_v0,
6854 * input_v1,
6855 * input_v2,
6856 * input_v3,
6857 * (VertexID + BaseVertex),
6858 * (InstanceID + StartInstance),
6859 * (InstanceID / 2 + StartInstance)
6860 */
6861 static void si_build_vs_prolog_function(struct si_shader_context *ctx,
6862 union si_shader_part_key *key)
6863 {
6864 struct si_function_info fninfo;
6865 LLVMTypeRef *returns;
6866 LLVMValueRef ret, func;
6867 int num_returns, i;
6868 unsigned first_vs_vgpr = key->vs_prolog.num_merged_next_stage_vgprs;
6869 unsigned num_input_vgprs = key->vs_prolog.num_merged_next_stage_vgprs + 4;
6870 LLVMValueRef input_vgprs[9];
6871 unsigned num_all_input_regs = key->vs_prolog.num_input_sgprs +
6872 num_input_vgprs;
6873 unsigned user_sgpr_base = key->vs_prolog.num_merged_next_stage_vgprs ? 8 : 0;
6874
6875 si_init_function_info(&fninfo);
6876
6877 /* 4 preloaded VGPRs + vertex load indices as prolog outputs */
6878 returns = alloca((num_all_input_regs + key->vs_prolog.last_input + 1) *
6879 sizeof(LLVMTypeRef));
6880 num_returns = 0;
6881
6882 /* Declare input and output SGPRs. */
6883 for (i = 0; i < key->vs_prolog.num_input_sgprs; i++) {
6884 add_arg(&fninfo, ARG_SGPR, ctx->i32);
6885 returns[num_returns++] = ctx->i32;
6886 }
6887
6888 /* Preloaded VGPRs (outputs must be floats) */
6889 for (i = 0; i < num_input_vgprs; i++) {
6890 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &input_vgprs[i]);
6891 returns[num_returns++] = ctx->f32;
6892 }
6893
6894 /* Vertex load indices. */
6895 for (i = 0; i <= key->vs_prolog.last_input; i++)
6896 returns[num_returns++] = ctx->f32;
6897
6898 /* Create the function. */
6899 si_create_function(ctx, "vs_prolog", returns, num_returns, &fninfo, 0);
6900 func = ctx->main_fn;
6901
6902 if (key->vs_prolog.num_merged_next_stage_vgprs) {
6903 if (!key->vs_prolog.is_monolithic)
6904 si_init_exec_from_input(ctx, 3, 0);
6905
6906 if (key->vs_prolog.as_ls &&
6907 ctx->screen->has_ls_vgpr_init_bug) {
6908 /* If there are no HS threads, SPI loads the LS VGPRs
6909 * starting at VGPR 0. Shift them back to where they
6910 * belong.
6911 */
6912 LLVMValueRef has_hs_threads =
6913 LLVMBuildICmp(ctx->ac.builder, LLVMIntNE,
6914 unpack_param(ctx, 3, 8, 8),
6915 ctx->i32_0, "");
6916
6917 for (i = 4; i > 0; --i) {
6918 input_vgprs[i + 1] =
6919 LLVMBuildSelect(ctx->ac.builder, has_hs_threads,
6920 input_vgprs[i + 1],
6921 input_vgprs[i - 1], "");
6922 }
6923 }
6924 }
6925
6926 ctx->abi.vertex_id = input_vgprs[first_vs_vgpr];
6927 ctx->abi.instance_id = input_vgprs[first_vs_vgpr + (key->vs_prolog.as_ls ? 2 : 1)];
6928
6929 /* Copy inputs to outputs. This should be no-op, as the registers match,
6930 * but it will prevent the compiler from overwriting them unintentionally.
6931 */
6932 ret = ctx->return_value;
6933 for (i = 0; i < key->vs_prolog.num_input_sgprs; i++) {
6934 LLVMValueRef p = LLVMGetParam(func, i);
6935 ret = LLVMBuildInsertValue(ctx->ac.builder, ret, p, i, "");
6936 }
6937 for (i = 0; i < num_input_vgprs; i++) {
6938 LLVMValueRef p = input_vgprs[i];
6939 p = ac_to_float(&ctx->ac, p);
6940 ret = LLVMBuildInsertValue(ctx->ac.builder, ret, p,
6941 key->vs_prolog.num_input_sgprs + i, "");
6942 }
6943
6944 /* Compute vertex load indices from instance divisors. */
6945 LLVMValueRef instance_divisor_constbuf = NULL;
6946
6947 if (key->vs_prolog.states.instance_divisor_is_fetched) {
6948 LLVMValueRef list = si_prolog_get_rw_buffers(ctx);
6949 LLVMValueRef buf_index =
6950 LLVMConstInt(ctx->i32, SI_VS_CONST_INSTANCE_DIVISORS, 0);
6951 instance_divisor_constbuf =
6952 ac_build_load_to_sgpr(&ctx->ac, list, buf_index);
6953 }
6954
6955 for (i = 0; i <= key->vs_prolog.last_input; i++) {
6956 bool divisor_is_one =
6957 key->vs_prolog.states.instance_divisor_is_one & (1u << i);
6958 bool divisor_is_fetched =
6959 key->vs_prolog.states.instance_divisor_is_fetched & (1u << i);
6960 LLVMValueRef index;
6961
6962 if (divisor_is_one || divisor_is_fetched) {
6963 LLVMValueRef divisor = ctx->i32_1;
6964
6965 if (divisor_is_fetched) {
6966 divisor = buffer_load_const(ctx, instance_divisor_constbuf,
6967 LLVMConstInt(ctx->i32, i * 4, 0));
6968 divisor = ac_to_integer(&ctx->ac, divisor);
6969 }
6970
6971 /* InstanceID / Divisor + StartInstance */
6972 index = get_instance_index_for_fetch(ctx,
6973 user_sgpr_base +
6974 SI_SGPR_START_INSTANCE,
6975 divisor);
6976 } else {
6977 /* VertexID + BaseVertex */
6978 index = LLVMBuildAdd(ctx->ac.builder,
6979 ctx->abi.vertex_id,
6980 LLVMGetParam(func, user_sgpr_base +
6981 SI_SGPR_BASE_VERTEX), "");
6982 }
6983
6984 index = ac_to_float(&ctx->ac, index);
6985 ret = LLVMBuildInsertValue(ctx->ac.builder, ret, index,
6986 fninfo.num_params + i, "");
6987 }
6988
6989 si_llvm_build_ret(ctx, ret);
6990 }
6991
6992 static bool si_get_vs_prolog(struct si_screen *sscreen,
6993 LLVMTargetMachineRef tm,
6994 struct si_shader *shader,
6995 struct pipe_debug_callback *debug,
6996 struct si_shader *main_part,
6997 const struct si_vs_prolog_bits *key)
6998 {
6999 struct si_shader_selector *vs = main_part->selector;
7000
7001 if (!si_vs_needs_prolog(vs, key))
7002 return true;
7003
7004 /* Get the prolog. */
7005 union si_shader_part_key prolog_key;
7006 si_get_vs_prolog_key(&vs->info, main_part->info.num_input_sgprs,
7007 key, shader, &prolog_key);
7008
7009 shader->prolog =
7010 si_get_shader_part(sscreen, &sscreen->vs_prologs,
7011 PIPE_SHADER_VERTEX, true, &prolog_key, tm,
7012 debug, si_build_vs_prolog_function,
7013 "Vertex Shader Prolog");
7014 return shader->prolog != NULL;
7015 }
7016
7017 /**
7018 * Select and compile (or reuse) vertex shader parts (prolog & epilog).
7019 */
7020 static bool si_shader_select_vs_parts(struct si_screen *sscreen,
7021 LLVMTargetMachineRef tm,
7022 struct si_shader *shader,
7023 struct pipe_debug_callback *debug)
7024 {
7025 return si_get_vs_prolog(sscreen, tm, shader, debug, shader,
7026 &shader->key.part.vs.prolog);
7027 }
7028
7029 /**
7030 * Compile the TCS epilog function. This writes tesselation factors to memory
7031 * based on the output primitive type of the tesselator (determined by TES).
7032 */
7033 static void si_build_tcs_epilog_function(struct si_shader_context *ctx,
7034 union si_shader_part_key *key)
7035 {
7036 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
7037 struct si_function_info fninfo;
7038 LLVMValueRef func;
7039
7040 si_init_function_info(&fninfo);
7041
7042 if (ctx->screen->info.chip_class >= GFX9) {
7043 add_arg(&fninfo, ARG_SGPR, ctx->i64);
7044 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7045 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* wave info */
7046 ctx->param_tcs_factor_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7047 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7048 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7049 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7050 add_arg(&fninfo, ARG_SGPR, ctx->i64);
7051 add_arg(&fninfo, ARG_SGPR, ctx->i64);
7052 add_arg(&fninfo, ARG_SGPR, ctx->i64);
7053 add_arg(&fninfo, ARG_SGPR, ctx->i64);
7054 add_arg(&fninfo, ARG_SGPR, ctx->i64);
7055 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7056 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7057 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7058 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7059 ctx->param_tcs_offchip_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7060 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7061 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7062 ctx->param_tcs_offchip_addr_base64k = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7063 ctx->param_tcs_factor_addr_base64k = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7064 } else {
7065 add_arg(&fninfo, ARG_SGPR, ctx->i64);
7066 add_arg(&fninfo, ARG_SGPR, ctx->i64);
7067 add_arg(&fninfo, ARG_SGPR, ctx->i64);
7068 add_arg(&fninfo, ARG_SGPR, ctx->i64);
7069 ctx->param_tcs_offchip_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7070 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7071 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7072 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7073 ctx->param_tcs_offchip_addr_base64k = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7074 ctx->param_tcs_factor_addr_base64k = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7075 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7076 ctx->param_tcs_factor_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7077 }
7078
7079 add_arg(&fninfo, ARG_VGPR, ctx->i32); /* VGPR gap */
7080 add_arg(&fninfo, ARG_VGPR, ctx->i32); /* VGPR gap */
7081 unsigned tess_factors_idx =
7082 add_arg(&fninfo, ARG_VGPR, ctx->i32); /* patch index within the wave (REL_PATCH_ID) */
7083 add_arg(&fninfo, ARG_VGPR, ctx->i32); /* invocation ID within the patch */
7084 add_arg(&fninfo, ARG_VGPR, ctx->i32); /* LDS offset where tess factors should be loaded from */
7085
7086 for (unsigned i = 0; i < 6; i++)
7087 add_arg(&fninfo, ARG_VGPR, ctx->i32); /* tess factors */
7088
7089 /* Create the function. */
7090 si_create_function(ctx, "tcs_epilog", NULL, 0, &fninfo,
7091 ctx->screen->info.chip_class >= CIK ? 128 : 64);
7092 ac_declare_lds_as_pointer(&ctx->ac);
7093 func = ctx->main_fn;
7094
7095 LLVMValueRef invoc0_tess_factors[6];
7096 for (unsigned i = 0; i < 6; i++)
7097 invoc0_tess_factors[i] = LLVMGetParam(func, tess_factors_idx + 3 + i);
7098
7099 si_write_tess_factors(bld_base,
7100 LLVMGetParam(func, tess_factors_idx),
7101 LLVMGetParam(func, tess_factors_idx + 1),
7102 LLVMGetParam(func, tess_factors_idx + 2),
7103 invoc0_tess_factors, invoc0_tess_factors + 4);
7104
7105 LLVMBuildRetVoid(ctx->ac.builder);
7106 }
7107
7108 /**
7109 * Select and compile (or reuse) TCS parts (epilog).
7110 */
7111 static bool si_shader_select_tcs_parts(struct si_screen *sscreen,
7112 LLVMTargetMachineRef tm,
7113 struct si_shader *shader,
7114 struct pipe_debug_callback *debug)
7115 {
7116 if (sscreen->info.chip_class >= GFX9) {
7117 struct si_shader *ls_main_part =
7118 shader->key.part.tcs.ls->main_shader_part_ls;
7119
7120 if (!si_get_vs_prolog(sscreen, tm, shader, debug, ls_main_part,
7121 &shader->key.part.tcs.ls_prolog))
7122 return false;
7123
7124 shader->previous_stage = ls_main_part;
7125 }
7126
7127 /* Get the epilog. */
7128 union si_shader_part_key epilog_key;
7129 memset(&epilog_key, 0, sizeof(epilog_key));
7130 epilog_key.tcs_epilog.states = shader->key.part.tcs.epilog;
7131
7132 shader->epilog = si_get_shader_part(sscreen, &sscreen->tcs_epilogs,
7133 PIPE_SHADER_TESS_CTRL, false,
7134 &epilog_key, tm, debug,
7135 si_build_tcs_epilog_function,
7136 "Tessellation Control Shader Epilog");
7137 return shader->epilog != NULL;
7138 }
7139
7140 /**
7141 * Select and compile (or reuse) GS parts (prolog).
7142 */
7143 static bool si_shader_select_gs_parts(struct si_screen *sscreen,
7144 LLVMTargetMachineRef tm,
7145 struct si_shader *shader,
7146 struct pipe_debug_callback *debug)
7147 {
7148 if (sscreen->info.chip_class >= GFX9) {
7149 struct si_shader *es_main_part =
7150 shader->key.part.gs.es->main_shader_part_es;
7151
7152 if (shader->key.part.gs.es->type == PIPE_SHADER_VERTEX &&
7153 !si_get_vs_prolog(sscreen, tm, shader, debug, es_main_part,
7154 &shader->key.part.gs.vs_prolog))
7155 return false;
7156
7157 shader->previous_stage = es_main_part;
7158 }
7159
7160 if (!shader->key.part.gs.prolog.tri_strip_adj_fix)
7161 return true;
7162
7163 union si_shader_part_key prolog_key;
7164 memset(&prolog_key, 0, sizeof(prolog_key));
7165 prolog_key.gs_prolog.states = shader->key.part.gs.prolog;
7166
7167 shader->prolog2 = si_get_shader_part(sscreen, &sscreen->gs_prologs,
7168 PIPE_SHADER_GEOMETRY, true,
7169 &prolog_key, tm, debug,
7170 si_build_gs_prolog_function,
7171 "Geometry Shader Prolog");
7172 return shader->prolog2 != NULL;
7173 }
7174
7175 /**
7176 * Build the pixel shader prolog function. This handles:
7177 * - two-side color selection and interpolation
7178 * - overriding interpolation parameters for the API PS
7179 * - polygon stippling
7180 *
7181 * All preloaded SGPRs and VGPRs are passed through unmodified unless they are
7182 * overriden by other states. (e.g. per-sample interpolation)
7183 * Interpolated colors are stored after the preloaded VGPRs.
7184 */
7185 static void si_build_ps_prolog_function(struct si_shader_context *ctx,
7186 union si_shader_part_key *key)
7187 {
7188 struct si_function_info fninfo;
7189 LLVMValueRef ret, func;
7190 int num_returns, i, num_color_channels;
7191
7192 assert(si_need_ps_prolog(key));
7193
7194 si_init_function_info(&fninfo);
7195
7196 /* Declare inputs. */
7197 for (i = 0; i < key->ps_prolog.num_input_sgprs; i++)
7198 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7199
7200 for (i = 0; i < key->ps_prolog.num_input_vgprs; i++)
7201 add_arg(&fninfo, ARG_VGPR, ctx->f32);
7202
7203 /* Declare outputs (same as inputs + add colors if needed) */
7204 num_returns = fninfo.num_params;
7205 num_color_channels = util_bitcount(key->ps_prolog.colors_read);
7206 for (i = 0; i < num_color_channels; i++)
7207 fninfo.types[num_returns++] = ctx->f32;
7208
7209 /* Create the function. */
7210 si_create_function(ctx, "ps_prolog", fninfo.types, num_returns,
7211 &fninfo, 0);
7212 func = ctx->main_fn;
7213
7214 /* Copy inputs to outputs. This should be no-op, as the registers match,
7215 * but it will prevent the compiler from overwriting them unintentionally.
7216 */
7217 ret = ctx->return_value;
7218 for (i = 0; i < fninfo.num_params; i++) {
7219 LLVMValueRef p = LLVMGetParam(func, i);
7220 ret = LLVMBuildInsertValue(ctx->ac.builder, ret, p, i, "");
7221 }
7222
7223 /* Polygon stippling. */
7224 if (key->ps_prolog.states.poly_stipple) {
7225 /* POS_FIXED_PT is always last. */
7226 unsigned pos = key->ps_prolog.num_input_sgprs +
7227 key->ps_prolog.num_input_vgprs - 1;
7228 LLVMValueRef list = si_prolog_get_rw_buffers(ctx);
7229
7230 si_llvm_emit_polygon_stipple(ctx, list, pos);
7231 }
7232
7233 if (key->ps_prolog.states.bc_optimize_for_persp ||
7234 key->ps_prolog.states.bc_optimize_for_linear) {
7235 unsigned i, base = key->ps_prolog.num_input_sgprs;
7236 LLVMValueRef center[2], centroid[2], tmp, bc_optimize;
7237
7238 /* The shader should do: if (PRIM_MASK[31]) CENTROID = CENTER;
7239 * The hw doesn't compute CENTROID if the whole wave only
7240 * contains fully-covered quads.
7241 *
7242 * PRIM_MASK is after user SGPRs.
7243 */
7244 bc_optimize = LLVMGetParam(func, SI_PS_NUM_USER_SGPR);
7245 bc_optimize = LLVMBuildLShr(ctx->ac.builder, bc_optimize,
7246 LLVMConstInt(ctx->i32, 31, 0), "");
7247 bc_optimize = LLVMBuildTrunc(ctx->ac.builder, bc_optimize,
7248 ctx->i1, "");
7249
7250 if (key->ps_prolog.states.bc_optimize_for_persp) {
7251 /* Read PERSP_CENTER. */
7252 for (i = 0; i < 2; i++)
7253 center[i] = LLVMGetParam(func, base + 2 + i);
7254 /* Read PERSP_CENTROID. */
7255 for (i = 0; i < 2; i++)
7256 centroid[i] = LLVMGetParam(func, base + 4 + i);
7257 /* Select PERSP_CENTROID. */
7258 for (i = 0; i < 2; i++) {
7259 tmp = LLVMBuildSelect(ctx->ac.builder, bc_optimize,
7260 center[i], centroid[i], "");
7261 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7262 tmp, base + 4 + i, "");
7263 }
7264 }
7265 if (key->ps_prolog.states.bc_optimize_for_linear) {
7266 /* Read LINEAR_CENTER. */
7267 for (i = 0; i < 2; i++)
7268 center[i] = LLVMGetParam(func, base + 8 + i);
7269 /* Read LINEAR_CENTROID. */
7270 for (i = 0; i < 2; i++)
7271 centroid[i] = LLVMGetParam(func, base + 10 + i);
7272 /* Select LINEAR_CENTROID. */
7273 for (i = 0; i < 2; i++) {
7274 tmp = LLVMBuildSelect(ctx->ac.builder, bc_optimize,
7275 center[i], centroid[i], "");
7276 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7277 tmp, base + 10 + i, "");
7278 }
7279 }
7280 }
7281
7282 /* Force per-sample interpolation. */
7283 if (key->ps_prolog.states.force_persp_sample_interp) {
7284 unsigned i, base = key->ps_prolog.num_input_sgprs;
7285 LLVMValueRef persp_sample[2];
7286
7287 /* Read PERSP_SAMPLE. */
7288 for (i = 0; i < 2; i++)
7289 persp_sample[i] = LLVMGetParam(func, base + i);
7290 /* Overwrite PERSP_CENTER. */
7291 for (i = 0; i < 2; i++)
7292 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7293 persp_sample[i], base + 2 + i, "");
7294 /* Overwrite PERSP_CENTROID. */
7295 for (i = 0; i < 2; i++)
7296 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7297 persp_sample[i], base + 4 + i, "");
7298 }
7299 if (key->ps_prolog.states.force_linear_sample_interp) {
7300 unsigned i, base = key->ps_prolog.num_input_sgprs;
7301 LLVMValueRef linear_sample[2];
7302
7303 /* Read LINEAR_SAMPLE. */
7304 for (i = 0; i < 2; i++)
7305 linear_sample[i] = LLVMGetParam(func, base + 6 + i);
7306 /* Overwrite LINEAR_CENTER. */
7307 for (i = 0; i < 2; i++)
7308 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7309 linear_sample[i], base + 8 + i, "");
7310 /* Overwrite LINEAR_CENTROID. */
7311 for (i = 0; i < 2; i++)
7312 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7313 linear_sample[i], base + 10 + i, "");
7314 }
7315
7316 /* Force center interpolation. */
7317 if (key->ps_prolog.states.force_persp_center_interp) {
7318 unsigned i, base = key->ps_prolog.num_input_sgprs;
7319 LLVMValueRef persp_center[2];
7320
7321 /* Read PERSP_CENTER. */
7322 for (i = 0; i < 2; i++)
7323 persp_center[i] = LLVMGetParam(func, base + 2 + i);
7324 /* Overwrite PERSP_SAMPLE. */
7325 for (i = 0; i < 2; i++)
7326 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7327 persp_center[i], base + i, "");
7328 /* Overwrite PERSP_CENTROID. */
7329 for (i = 0; i < 2; i++)
7330 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7331 persp_center[i], base + 4 + i, "");
7332 }
7333 if (key->ps_prolog.states.force_linear_center_interp) {
7334 unsigned i, base = key->ps_prolog.num_input_sgprs;
7335 LLVMValueRef linear_center[2];
7336
7337 /* Read LINEAR_CENTER. */
7338 for (i = 0; i < 2; i++)
7339 linear_center[i] = LLVMGetParam(func, base + 8 + i);
7340 /* Overwrite LINEAR_SAMPLE. */
7341 for (i = 0; i < 2; i++)
7342 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7343 linear_center[i], base + 6 + i, "");
7344 /* Overwrite LINEAR_CENTROID. */
7345 for (i = 0; i < 2; i++)
7346 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7347 linear_center[i], base + 10 + i, "");
7348 }
7349
7350 /* Interpolate colors. */
7351 unsigned color_out_idx = 0;
7352 for (i = 0; i < 2; i++) {
7353 unsigned writemask = (key->ps_prolog.colors_read >> (i * 4)) & 0xf;
7354 unsigned face_vgpr = key->ps_prolog.num_input_sgprs +
7355 key->ps_prolog.face_vgpr_index;
7356 LLVMValueRef interp[2], color[4];
7357 LLVMValueRef interp_ij = NULL, prim_mask = NULL, face = NULL;
7358
7359 if (!writemask)
7360 continue;
7361
7362 /* If the interpolation qualifier is not CONSTANT (-1). */
7363 if (key->ps_prolog.color_interp_vgpr_index[i] != -1) {
7364 unsigned interp_vgpr = key->ps_prolog.num_input_sgprs +
7365 key->ps_prolog.color_interp_vgpr_index[i];
7366
7367 /* Get the (i,j) updated by bc_optimize handling. */
7368 interp[0] = LLVMBuildExtractValue(ctx->ac.builder, ret,
7369 interp_vgpr, "");
7370 interp[1] = LLVMBuildExtractValue(ctx->ac.builder, ret,
7371 interp_vgpr + 1, "");
7372 interp_ij = lp_build_gather_values(&ctx->gallivm, interp, 2);
7373 }
7374
7375 /* Use the absolute location of the input. */
7376 prim_mask = LLVMGetParam(func, SI_PS_NUM_USER_SGPR);
7377
7378 if (key->ps_prolog.states.color_two_side) {
7379 face = LLVMGetParam(func, face_vgpr);
7380 face = ac_to_integer(&ctx->ac, face);
7381 }
7382
7383 interp_fs_input(ctx,
7384 key->ps_prolog.color_attr_index[i],
7385 TGSI_SEMANTIC_COLOR, i,
7386 key->ps_prolog.num_interp_inputs,
7387 key->ps_prolog.colors_read, interp_ij,
7388 prim_mask, face, color);
7389
7390 while (writemask) {
7391 unsigned chan = u_bit_scan(&writemask);
7392 ret = LLVMBuildInsertValue(ctx->ac.builder, ret, color[chan],
7393 fninfo.num_params + color_out_idx++, "");
7394 }
7395 }
7396
7397 /* Section 15.2.2 (Shader Inputs) of the OpenGL 4.5 (Core Profile) spec
7398 * says:
7399 *
7400 * "When per-sample shading is active due to the use of a fragment
7401 * input qualified by sample or due to the use of the gl_SampleID
7402 * or gl_SamplePosition variables, only the bit for the current
7403 * sample is set in gl_SampleMaskIn. When state specifies multiple
7404 * fragment shader invocations for a given fragment, the sample
7405 * mask for any single fragment shader invocation may specify a
7406 * subset of the covered samples for the fragment. In this case,
7407 * the bit corresponding to each covered sample will be set in
7408 * exactly one fragment shader invocation."
7409 *
7410 * The samplemask loaded by hardware is always the coverage of the
7411 * entire pixel/fragment, so mask bits out based on the sample ID.
7412 */
7413 if (key->ps_prolog.states.samplemask_log_ps_iter) {
7414 /* The bit pattern matches that used by fixed function fragment
7415 * processing. */
7416 static const uint16_t ps_iter_masks[] = {
7417 0xffff, /* not used */
7418 0x5555,
7419 0x1111,
7420 0x0101,
7421 0x0001,
7422 };
7423 assert(key->ps_prolog.states.samplemask_log_ps_iter < ARRAY_SIZE(ps_iter_masks));
7424
7425 uint32_t ps_iter_mask = ps_iter_masks[key->ps_prolog.states.samplemask_log_ps_iter];
7426 unsigned ancillary_vgpr = key->ps_prolog.num_input_sgprs +
7427 key->ps_prolog.ancillary_vgpr_index;
7428 LLVMValueRef sampleid = unpack_param(ctx, ancillary_vgpr, 8, 4);
7429 LLVMValueRef samplemask = LLVMGetParam(func, ancillary_vgpr + 1);
7430
7431 samplemask = ac_to_integer(&ctx->ac, samplemask);
7432 samplemask = LLVMBuildAnd(
7433 ctx->ac.builder,
7434 samplemask,
7435 LLVMBuildShl(ctx->ac.builder,
7436 LLVMConstInt(ctx->i32, ps_iter_mask, false),
7437 sampleid, ""),
7438 "");
7439 samplemask = ac_to_float(&ctx->ac, samplemask);
7440
7441 ret = LLVMBuildInsertValue(ctx->ac.builder, ret, samplemask,
7442 ancillary_vgpr + 1, "");
7443 }
7444
7445 /* Tell LLVM to insert WQM instruction sequence when needed. */
7446 if (key->ps_prolog.wqm) {
7447 LLVMAddTargetDependentFunctionAttr(func,
7448 "amdgpu-ps-wqm-outputs", "");
7449 }
7450
7451 si_llvm_build_ret(ctx, ret);
7452 }
7453
7454 /**
7455 * Build the pixel shader epilog function. This handles everything that must be
7456 * emulated for pixel shader exports. (alpha-test, format conversions, etc)
7457 */
7458 static void si_build_ps_epilog_function(struct si_shader_context *ctx,
7459 union si_shader_part_key *key)
7460 {
7461 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
7462 struct si_function_info fninfo;
7463 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
7464 int i;
7465 struct si_ps_exports exp = {};
7466
7467 si_init_function_info(&fninfo);
7468
7469 /* Declare input SGPRs. */
7470 ctx->param_rw_buffers = add_arg(&fninfo, ARG_SGPR, ctx->i64);
7471 ctx->param_bindless_samplers_and_images = add_arg(&fninfo, ARG_SGPR, ctx->i64);
7472 ctx->param_const_and_shader_buffers = add_arg(&fninfo, ARG_SGPR, ctx->i64);
7473 ctx->param_samplers_and_images = add_arg(&fninfo, ARG_SGPR, ctx->i64);
7474 add_arg_checked(&fninfo, ARG_SGPR, ctx->f32, SI_PARAM_ALPHA_REF);
7475
7476 /* Declare input VGPRs. */
7477 unsigned required_num_params =
7478 fninfo.num_sgpr_params +
7479 util_bitcount(key->ps_epilog.colors_written) * 4 +
7480 key->ps_epilog.writes_z +
7481 key->ps_epilog.writes_stencil +
7482 key->ps_epilog.writes_samplemask;
7483
7484 required_num_params = MAX2(required_num_params,
7485 fninfo.num_sgpr_params + PS_EPILOG_SAMPLEMASK_MIN_LOC + 1);
7486
7487 while (fninfo.num_params < required_num_params)
7488 add_arg(&fninfo, ARG_VGPR, ctx->f32);
7489
7490 /* Create the function. */
7491 si_create_function(ctx, "ps_epilog", NULL, 0, &fninfo, 0);
7492 /* Disable elimination of unused inputs. */
7493 si_llvm_add_attribute(ctx->main_fn,
7494 "InitialPSInputAddr", 0xffffff);
7495
7496 /* Process colors. */
7497 unsigned vgpr = fninfo.num_sgpr_params;
7498 unsigned colors_written = key->ps_epilog.colors_written;
7499 int last_color_export = -1;
7500
7501 /* Find the last color export. */
7502 if (!key->ps_epilog.writes_z &&
7503 !key->ps_epilog.writes_stencil &&
7504 !key->ps_epilog.writes_samplemask) {
7505 unsigned spi_format = key->ps_epilog.states.spi_shader_col_format;
7506
7507 /* If last_cbuf > 0, FS_COLOR0_WRITES_ALL_CBUFS is true. */
7508 if (colors_written == 0x1 && key->ps_epilog.states.last_cbuf > 0) {
7509 /* Just set this if any of the colorbuffers are enabled. */
7510 if (spi_format &
7511 ((1ull << (4 * (key->ps_epilog.states.last_cbuf + 1))) - 1))
7512 last_color_export = 0;
7513 } else {
7514 for (i = 0; i < 8; i++)
7515 if (colors_written & (1 << i) &&
7516 (spi_format >> (i * 4)) & 0xf)
7517 last_color_export = i;
7518 }
7519 }
7520
7521 while (colors_written) {
7522 LLVMValueRef color[4];
7523 int mrt = u_bit_scan(&colors_written);
7524
7525 for (i = 0; i < 4; i++)
7526 color[i] = LLVMGetParam(ctx->main_fn, vgpr++);
7527
7528 si_export_mrt_color(bld_base, color, mrt,
7529 fninfo.num_params - 1,
7530 mrt == last_color_export, &exp);
7531 }
7532
7533 /* Process depth, stencil, samplemask. */
7534 if (key->ps_epilog.writes_z)
7535 depth = LLVMGetParam(ctx->main_fn, vgpr++);
7536 if (key->ps_epilog.writes_stencil)
7537 stencil = LLVMGetParam(ctx->main_fn, vgpr++);
7538 if (key->ps_epilog.writes_samplemask)
7539 samplemask = LLVMGetParam(ctx->main_fn, vgpr++);
7540
7541 if (depth || stencil || samplemask)
7542 si_export_mrt_z(bld_base, depth, stencil, samplemask, &exp);
7543 else if (last_color_export == -1)
7544 si_export_null(bld_base);
7545
7546 if (exp.num)
7547 si_emit_ps_exports(ctx, &exp);
7548
7549 /* Compile. */
7550 LLVMBuildRetVoid(ctx->ac.builder);
7551 }
7552
7553 /**
7554 * Select and compile (or reuse) pixel shader parts (prolog & epilog).
7555 */
7556 static bool si_shader_select_ps_parts(struct si_screen *sscreen,
7557 LLVMTargetMachineRef tm,
7558 struct si_shader *shader,
7559 struct pipe_debug_callback *debug)
7560 {
7561 union si_shader_part_key prolog_key;
7562 union si_shader_part_key epilog_key;
7563
7564 /* Get the prolog. */
7565 si_get_ps_prolog_key(shader, &prolog_key, true);
7566
7567 /* The prolog is a no-op if these aren't set. */
7568 if (si_need_ps_prolog(&prolog_key)) {
7569 shader->prolog =
7570 si_get_shader_part(sscreen, &sscreen->ps_prologs,
7571 PIPE_SHADER_FRAGMENT, true,
7572 &prolog_key, tm, debug,
7573 si_build_ps_prolog_function,
7574 "Fragment Shader Prolog");
7575 if (!shader->prolog)
7576 return false;
7577 }
7578
7579 /* Get the epilog. */
7580 si_get_ps_epilog_key(shader, &epilog_key);
7581
7582 shader->epilog =
7583 si_get_shader_part(sscreen, &sscreen->ps_epilogs,
7584 PIPE_SHADER_FRAGMENT, false,
7585 &epilog_key, tm, debug,
7586 si_build_ps_epilog_function,
7587 "Fragment Shader Epilog");
7588 if (!shader->epilog)
7589 return false;
7590
7591 /* Enable POS_FIXED_PT if polygon stippling is enabled. */
7592 if (shader->key.part.ps.prolog.poly_stipple) {
7593 shader->config.spi_ps_input_ena |= S_0286CC_POS_FIXED_PT_ENA(1);
7594 assert(G_0286CC_POS_FIXED_PT_ENA(shader->config.spi_ps_input_addr));
7595 }
7596
7597 /* Set up the enable bits for per-sample shading if needed. */
7598 if (shader->key.part.ps.prolog.force_persp_sample_interp &&
7599 (G_0286CC_PERSP_CENTER_ENA(shader->config.spi_ps_input_ena) ||
7600 G_0286CC_PERSP_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
7601 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_CENTER_ENA;
7602 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_CENTROID_ENA;
7603 shader->config.spi_ps_input_ena |= S_0286CC_PERSP_SAMPLE_ENA(1);
7604 }
7605 if (shader->key.part.ps.prolog.force_linear_sample_interp &&
7606 (G_0286CC_LINEAR_CENTER_ENA(shader->config.spi_ps_input_ena) ||
7607 G_0286CC_LINEAR_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
7608 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_CENTER_ENA;
7609 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_CENTROID_ENA;
7610 shader->config.spi_ps_input_ena |= S_0286CC_LINEAR_SAMPLE_ENA(1);
7611 }
7612 if (shader->key.part.ps.prolog.force_persp_center_interp &&
7613 (G_0286CC_PERSP_SAMPLE_ENA(shader->config.spi_ps_input_ena) ||
7614 G_0286CC_PERSP_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
7615 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_SAMPLE_ENA;
7616 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_CENTROID_ENA;
7617 shader->config.spi_ps_input_ena |= S_0286CC_PERSP_CENTER_ENA(1);
7618 }
7619 if (shader->key.part.ps.prolog.force_linear_center_interp &&
7620 (G_0286CC_LINEAR_SAMPLE_ENA(shader->config.spi_ps_input_ena) ||
7621 G_0286CC_LINEAR_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
7622 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_SAMPLE_ENA;
7623 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_CENTROID_ENA;
7624 shader->config.spi_ps_input_ena |= S_0286CC_LINEAR_CENTER_ENA(1);
7625 }
7626
7627 /* POW_W_FLOAT requires that one of the perspective weights is enabled. */
7628 if (G_0286CC_POS_W_FLOAT_ENA(shader->config.spi_ps_input_ena) &&
7629 !(shader->config.spi_ps_input_ena & 0xf)) {
7630 shader->config.spi_ps_input_ena |= S_0286CC_PERSP_CENTER_ENA(1);
7631 assert(G_0286CC_PERSP_CENTER_ENA(shader->config.spi_ps_input_addr));
7632 }
7633
7634 /* At least one pair of interpolation weights must be enabled. */
7635 if (!(shader->config.spi_ps_input_ena & 0x7f)) {
7636 shader->config.spi_ps_input_ena |= S_0286CC_LINEAR_CENTER_ENA(1);
7637 assert(G_0286CC_LINEAR_CENTER_ENA(shader->config.spi_ps_input_addr));
7638 }
7639
7640 /* Samplemask fixup requires the sample ID. */
7641 if (shader->key.part.ps.prolog.samplemask_log_ps_iter) {
7642 shader->config.spi_ps_input_ena |= S_0286CC_ANCILLARY_ENA(1);
7643 assert(G_0286CC_ANCILLARY_ENA(shader->config.spi_ps_input_addr));
7644 }
7645
7646 /* The sample mask input is always enabled, because the API shader always
7647 * passes it through to the epilog. Disable it here if it's unused.
7648 */
7649 if (!shader->key.part.ps.epilog.poly_line_smoothing &&
7650 !shader->selector->info.reads_samplemask)
7651 shader->config.spi_ps_input_ena &= C_0286CC_SAMPLE_COVERAGE_ENA;
7652
7653 return true;
7654 }
7655
7656 void si_multiwave_lds_size_workaround(struct si_screen *sscreen,
7657 unsigned *lds_size)
7658 {
7659 /* SPI barrier management bug:
7660 * Make sure we have at least 4k of LDS in use to avoid the bug.
7661 * It applies to workgroup sizes of more than one wavefront.
7662 */
7663 if (sscreen->info.family == CHIP_BONAIRE ||
7664 sscreen->info.family == CHIP_KABINI ||
7665 sscreen->info.family == CHIP_MULLINS)
7666 *lds_size = MAX2(*lds_size, 8);
7667 }
7668
7669 static void si_fix_resource_usage(struct si_screen *sscreen,
7670 struct si_shader *shader)
7671 {
7672 unsigned min_sgprs = shader->info.num_input_sgprs + 2; /* VCC */
7673
7674 shader->config.num_sgprs = MAX2(shader->config.num_sgprs, min_sgprs);
7675
7676 if (shader->selector->type == PIPE_SHADER_COMPUTE &&
7677 si_get_max_workgroup_size(shader) > 64) {
7678 si_multiwave_lds_size_workaround(sscreen,
7679 &shader->config.lds_size);
7680 }
7681 }
7682
7683 int si_shader_create(struct si_screen *sscreen, LLVMTargetMachineRef tm,
7684 struct si_shader *shader,
7685 struct pipe_debug_callback *debug)
7686 {
7687 struct si_shader_selector *sel = shader->selector;
7688 struct si_shader *mainp = *si_get_main_shader_part(sel, &shader->key);
7689 int r;
7690
7691 /* LS, ES, VS are compiled on demand if the main part hasn't been
7692 * compiled for that stage.
7693 *
7694 * Vertex shaders are compiled on demand when a vertex fetch
7695 * workaround must be applied.
7696 */
7697 if (shader->is_monolithic) {
7698 /* Monolithic shader (compiled as a whole, has many variants,
7699 * may take a long time to compile).
7700 */
7701 r = si_compile_tgsi_shader(sscreen, tm, shader, true, debug);
7702 if (r)
7703 return r;
7704 } else {
7705 /* The shader consists of several parts:
7706 *
7707 * - the middle part is the user shader, it has 1 variant only
7708 * and it was compiled during the creation of the shader
7709 * selector
7710 * - the prolog part is inserted at the beginning
7711 * - the epilog part is inserted at the end
7712 *
7713 * The prolog and epilog have many (but simple) variants.
7714 *
7715 * Starting with gfx9, geometry and tessellation control
7716 * shaders also contain the prolog and user shader parts of
7717 * the previous shader stage.
7718 */
7719
7720 if (!mainp)
7721 return -1;
7722
7723 /* Copy the compiled TGSI shader data over. */
7724 shader->is_binary_shared = true;
7725 shader->binary = mainp->binary;
7726 shader->config = mainp->config;
7727 shader->info.num_input_sgprs = mainp->info.num_input_sgprs;
7728 shader->info.num_input_vgprs = mainp->info.num_input_vgprs;
7729 shader->info.face_vgpr_index = mainp->info.face_vgpr_index;
7730 shader->info.ancillary_vgpr_index = mainp->info.ancillary_vgpr_index;
7731 memcpy(shader->info.vs_output_param_offset,
7732 mainp->info.vs_output_param_offset,
7733 sizeof(mainp->info.vs_output_param_offset));
7734 shader->info.uses_instanceid = mainp->info.uses_instanceid;
7735 shader->info.nr_pos_exports = mainp->info.nr_pos_exports;
7736 shader->info.nr_param_exports = mainp->info.nr_param_exports;
7737
7738 /* Select prologs and/or epilogs. */
7739 switch (sel->type) {
7740 case PIPE_SHADER_VERTEX:
7741 if (!si_shader_select_vs_parts(sscreen, tm, shader, debug))
7742 return -1;
7743 break;
7744 case PIPE_SHADER_TESS_CTRL:
7745 if (!si_shader_select_tcs_parts(sscreen, tm, shader, debug))
7746 return -1;
7747 break;
7748 case PIPE_SHADER_TESS_EVAL:
7749 break;
7750 case PIPE_SHADER_GEOMETRY:
7751 if (!si_shader_select_gs_parts(sscreen, tm, shader, debug))
7752 return -1;
7753 break;
7754 case PIPE_SHADER_FRAGMENT:
7755 if (!si_shader_select_ps_parts(sscreen, tm, shader, debug))
7756 return -1;
7757
7758 /* Make sure we have at least as many VGPRs as there
7759 * are allocated inputs.
7760 */
7761 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
7762 shader->info.num_input_vgprs);
7763 break;
7764 }
7765
7766 /* Update SGPR and VGPR counts. */
7767 if (shader->prolog) {
7768 shader->config.num_sgprs = MAX2(shader->config.num_sgprs,
7769 shader->prolog->config.num_sgprs);
7770 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
7771 shader->prolog->config.num_vgprs);
7772 }
7773 if (shader->previous_stage) {
7774 shader->config.num_sgprs = MAX2(shader->config.num_sgprs,
7775 shader->previous_stage->config.num_sgprs);
7776 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
7777 shader->previous_stage->config.num_vgprs);
7778 shader->config.spilled_sgprs =
7779 MAX2(shader->config.spilled_sgprs,
7780 shader->previous_stage->config.spilled_sgprs);
7781 shader->config.spilled_vgprs =
7782 MAX2(shader->config.spilled_vgprs,
7783 shader->previous_stage->config.spilled_vgprs);
7784 shader->config.private_mem_vgprs =
7785 MAX2(shader->config.private_mem_vgprs,
7786 shader->previous_stage->config.private_mem_vgprs);
7787 shader->config.scratch_bytes_per_wave =
7788 MAX2(shader->config.scratch_bytes_per_wave,
7789 shader->previous_stage->config.scratch_bytes_per_wave);
7790 shader->info.uses_instanceid |=
7791 shader->previous_stage->info.uses_instanceid;
7792 }
7793 if (shader->prolog2) {
7794 shader->config.num_sgprs = MAX2(shader->config.num_sgprs,
7795 shader->prolog2->config.num_sgprs);
7796 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
7797 shader->prolog2->config.num_vgprs);
7798 }
7799 if (shader->epilog) {
7800 shader->config.num_sgprs = MAX2(shader->config.num_sgprs,
7801 shader->epilog->config.num_sgprs);
7802 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
7803 shader->epilog->config.num_vgprs);
7804 }
7805 }
7806
7807 si_fix_resource_usage(sscreen, shader);
7808 si_shader_dump(sscreen, shader, debug, sel->info.processor,
7809 stderr, true);
7810
7811 /* Upload. */
7812 r = si_shader_binary_upload(sscreen, shader);
7813 if (r) {
7814 fprintf(stderr, "LLVM failed to upload shader\n");
7815 return r;
7816 }
7817
7818 return 0;
7819 }
7820
7821 void si_shader_destroy(struct si_shader *shader)
7822 {
7823 if (shader->scratch_bo)
7824 r600_resource_reference(&shader->scratch_bo, NULL);
7825
7826 r600_resource_reference(&shader->bo, NULL);
7827
7828 if (!shader->is_binary_shared)
7829 ac_shader_binary_clean(&shader->binary);
7830
7831 free(shader->shader_log);
7832 }