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radeonsi: Properly match ES outputs to GS inputs
[mesa.git] / src / gallium / drivers / radeonsi / si_shader.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Tom Stellard <thomas.stellard@amd.com>
25 * Michel Dänzer <michel.daenzer@amd.com>
26 * Christian König <christian.koenig@amd.com>
27 */
28
29 #include "gallivm/lp_bld_const.h"
30 #include "gallivm/lp_bld_gather.h"
31 #include "gallivm/lp_bld_intr.h"
32 #include "gallivm/lp_bld_logic.h"
33 #include "gallivm/lp_bld_arit.h"
34 #include "gallivm/lp_bld_flow.h"
35 #include "radeon_llvm.h"
36 #include "radeon_llvm_emit.h"
37 #include "util/u_memory.h"
38 #include "tgsi/tgsi_parse.h"
39 #include "tgsi/tgsi_util.h"
40 #include "tgsi/tgsi_dump.h"
41
42 #include "si_pipe.h"
43 #include "si_shader.h"
44 #include "sid.h"
45
46 #include <errno.h>
47
48 struct si_shader_output_values
49 {
50 LLVMValueRef values[4];
51 unsigned name;
52 unsigned index;
53 unsigned usage;
54 };
55
56 struct si_shader_context
57 {
58 struct radeon_llvm_context radeon_bld;
59 struct tgsi_parse_context parse;
60 struct tgsi_token * tokens;
61 struct si_pipe_shader *shader;
62 struct si_shader *gs_for_vs;
63 unsigned type; /* TGSI_PROCESSOR_* specifies the type of shader. */
64 int param_streamout_config;
65 int param_streamout_write_index;
66 int param_streamout_offset[4];
67 int param_vertex_id;
68 int param_instance_id;
69 LLVMValueRef const_md;
70 LLVMValueRef const_resource[NUM_CONST_BUFFERS];
71 #if HAVE_LLVM >= 0x0304
72 LLVMValueRef ddxy_lds;
73 #endif
74 LLVMValueRef *constants[NUM_CONST_BUFFERS];
75 LLVMValueRef *resources;
76 LLVMValueRef *samplers;
77 LLVMValueRef so_buffers[4];
78 LLVMValueRef gs_next_vertex;
79 };
80
81 static struct si_shader_context * si_shader_context(
82 struct lp_build_tgsi_context * bld_base)
83 {
84 return (struct si_shader_context *)bld_base;
85 }
86
87
88 #define PERSPECTIVE_BASE 0
89 #define LINEAR_BASE 9
90
91 #define SAMPLE_OFFSET 0
92 #define CENTER_OFFSET 2
93 #define CENTROID_OFSET 4
94
95 #define USE_SGPR_MAX_SUFFIX_LEN 5
96 #define CONST_ADDR_SPACE 2
97 #define LOCAL_ADDR_SPACE 3
98 #define USER_SGPR_ADDR_SPACE 8
99
100
101 #define SENDMSG_GS 2
102 #define SENDMSG_GS_DONE 3
103
104 #define SENDMSG_GS_OP_NOP (0 << 4)
105 #define SENDMSG_GS_OP_CUT (1 << 4)
106 #define SENDMSG_GS_OP_EMIT (2 << 4)
107 #define SENDMSG_GS_OP_EMIT_CUT (3 << 4)
108
109
110 /**
111 * Build an LLVM bytecode indexed load using LLVMBuildGEP + LLVMBuildLoad
112 *
113 * @param offset The offset parameter specifies the number of
114 * elements to offset, not the number of bytes or dwords. An element is the
115 * the type pointed to by the base_ptr parameter (e.g. int is the element of
116 * an int* pointer)
117 *
118 * When LLVM lowers the load instruction, it will convert the element offset
119 * into a dword offset automatically.
120 *
121 */
122 static LLVMValueRef build_indexed_load(
123 struct si_shader_context * si_shader_ctx,
124 LLVMValueRef base_ptr,
125 LLVMValueRef offset)
126 {
127 struct lp_build_context * base = &si_shader_ctx->radeon_bld.soa.bld_base.base;
128
129 LLVMValueRef indices[2] = {
130 LLVMConstInt(LLVMInt64TypeInContext(base->gallivm->context), 0, false),
131 offset
132 };
133 LLVMValueRef computed_ptr = LLVMBuildGEP(
134 base->gallivm->builder, base_ptr, indices, 2, "");
135
136 LLVMValueRef result = LLVMBuildLoad(base->gallivm->builder, computed_ptr, "");
137 LLVMSetMetadata(result, 1, si_shader_ctx->const_md);
138 return result;
139 }
140
141 static LLVMValueRef get_instance_index_for_fetch(
142 struct radeon_llvm_context * radeon_bld,
143 unsigned divisor)
144 {
145 struct si_shader_context *si_shader_ctx =
146 si_shader_context(&radeon_bld->soa.bld_base);
147 struct gallivm_state * gallivm = radeon_bld->soa.bld_base.base.gallivm;
148
149 LLVMValueRef result = LLVMGetParam(radeon_bld->main_fn,
150 si_shader_ctx->param_instance_id);
151 result = LLVMBuildAdd(gallivm->builder, result, LLVMGetParam(
152 radeon_bld->main_fn, SI_PARAM_START_INSTANCE), "");
153
154 if (divisor > 1)
155 result = LLVMBuildUDiv(gallivm->builder, result,
156 lp_build_const_int32(gallivm, divisor), "");
157
158 return result;
159 }
160
161 static int si_store_shader_io_attribs(struct si_shader *shader,
162 const struct tgsi_full_declaration *d)
163 {
164 int i = -1;
165
166 switch (d->Declaration.File) {
167 case TGSI_FILE_INPUT:
168 i = shader->ninput++;
169 assert(i < Elements(shader->input));
170 shader->input[i].name = d->Semantic.Name;
171 shader->input[i].sid = d->Semantic.Index;
172 shader->input[i].index = d->Range.First;
173 shader->input[i].interpolate = d->Interp.Interpolate;
174 shader->input[i].centroid = d->Interp.Centroid;
175 return -1;
176
177 case TGSI_FILE_OUTPUT:
178 i = shader->noutput++;
179 assert(i < Elements(shader->output));
180 shader->output[i].name = d->Semantic.Name;
181 shader->output[i].sid = d->Semantic.Index;
182 shader->output[i].index = d->Range.First;
183 shader->output[i].usage = d->Declaration.UsageMask;
184 break;
185 }
186
187 return i;
188 }
189
190 static void declare_input_vs(
191 struct radeon_llvm_context *radeon_bld,
192 unsigned input_index,
193 const struct tgsi_full_declaration *decl)
194 {
195 struct lp_build_context *base = &radeon_bld->soa.bld_base.base;
196 struct gallivm_state *gallivm = base->gallivm;
197 struct si_shader_context *si_shader_ctx =
198 si_shader_context(&radeon_bld->soa.bld_base);
199 unsigned divisor = si_shader_ctx->shader->key.vs.instance_divisors[input_index];
200
201 unsigned chan;
202
203 LLVMValueRef t_list_ptr;
204 LLVMValueRef t_offset;
205 LLVMValueRef t_list;
206 LLVMValueRef attribute_offset;
207 LLVMValueRef buffer_index;
208 LLVMValueRef args[3];
209 LLVMTypeRef vec4_type;
210 LLVMValueRef input;
211
212 /* Load the T list */
213 t_list_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_VERTEX_BUFFER);
214
215 t_offset = lp_build_const_int32(gallivm, input_index);
216
217 t_list = build_indexed_load(si_shader_ctx, t_list_ptr, t_offset);
218
219 /* Build the attribute offset */
220 attribute_offset = lp_build_const_int32(gallivm, 0);
221
222 if (divisor) {
223 /* Build index from instance ID, start instance and divisor */
224 si_shader_ctx->shader->shader.uses_instanceid = true;
225 buffer_index = get_instance_index_for_fetch(&si_shader_ctx->radeon_bld, divisor);
226 } else {
227 /* Load the buffer index, which is always stored in VGPR0
228 * for Vertex Shaders */
229 buffer_index = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
230 si_shader_ctx->param_vertex_id);
231 }
232
233 vec4_type = LLVMVectorType(base->elem_type, 4);
234 args[0] = t_list;
235 args[1] = attribute_offset;
236 args[2] = buffer_index;
237 input = build_intrinsic(gallivm->builder,
238 "llvm.SI.vs.load.input", vec4_type, args, 3,
239 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
240
241 /* Break up the vec4 into individual components */
242 for (chan = 0; chan < 4; chan++) {
243 LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan);
244 /* XXX: Use a helper function for this. There is one in
245 * tgsi_llvm.c. */
246 si_shader_ctx->radeon_bld.inputs[radeon_llvm_reg_index_soa(input_index, chan)] =
247 LLVMBuildExtractElement(gallivm->builder,
248 input, llvm_chan, "");
249 }
250 }
251
252 static void declare_input_gs(
253 struct radeon_llvm_context *radeon_bld,
254 unsigned input_index,
255 const struct tgsi_full_declaration *decl)
256 {
257 struct si_shader_context *si_shader_ctx =
258 si_shader_context(&radeon_bld->soa.bld_base);
259 struct si_shader *shader = &si_shader_ctx->shader->shader;
260
261 si_store_shader_io_attribs(shader, decl);
262
263 if (decl->Semantic.Name != TGSI_SEMANTIC_PRIMID)
264 shader->input[input_index].param_offset = shader->nparam++;
265 }
266
267 static LLVMValueRef fetch_input_gs(
268 struct lp_build_tgsi_context *bld_base,
269 const struct tgsi_full_src_register *reg,
270 enum tgsi_opcode_type type,
271 unsigned swizzle)
272 {
273 struct lp_build_context *base = &bld_base->base;
274 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
275 struct si_shader *shader = &si_shader_ctx->shader->shader;
276 struct lp_build_context *uint = &si_shader_ctx->radeon_bld.soa.bld_base.uint_bld;
277 struct gallivm_state *gallivm = base->gallivm;
278 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
279 LLVMValueRef vtx_offset;
280 LLVMValueRef t_list_ptr;
281 LLVMValueRef t_list;
282 LLVMValueRef args[9];
283 unsigned vtx_offset_param;
284
285 if (swizzle != ~0 &&
286 shader->input[reg->Register.Index].name == TGSI_SEMANTIC_PRIMID) {
287 if (swizzle == 0)
288 return LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
289 SI_PARAM_PRIMITIVE_ID);
290 else
291 return uint->zero;
292 }
293
294 if (!reg->Register.Dimension)
295 return NULL;
296
297 if (swizzle == ~0) {
298 LLVMValueRef values[TGSI_NUM_CHANNELS];
299 unsigned chan;
300 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
301 values[chan] = fetch_input_gs(bld_base, reg, type, chan);
302 }
303 return lp_build_gather_values(bld_base->base.gallivm, values,
304 TGSI_NUM_CHANNELS);
305 }
306
307 /* Get the vertex offset parameter */
308 vtx_offset_param = reg->Dimension.Index;
309 if (vtx_offset_param < 2) {
310 vtx_offset_param += SI_PARAM_VTX0_OFFSET;
311 } else {
312 assert(vtx_offset_param < 6);
313 vtx_offset_param += SI_PARAM_VTX2_OFFSET - 2;
314 }
315 vtx_offset = lp_build_mul_imm(uint,
316 LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
317 vtx_offset_param),
318 4);
319
320 /* Load the ESGS ring resource descriptor */
321 t_list_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_CONST);
322 t_list = build_indexed_load(si_shader_ctx, t_list_ptr,
323 lp_build_const_int32(gallivm,
324 NUM_PIPE_CONST_BUFFERS + 1));
325
326 args[0] = t_list;
327 args[1] = vtx_offset;
328 args[2] = lp_build_const_int32(gallivm,
329 ((shader->input[reg->Register.Index].param_offset * 4) +
330 swizzle) * 256);
331 args[3] = uint->zero;
332 args[4] = uint->one; /* OFFEN */
333 args[5] = uint->zero; /* IDXEN */
334 args[6] = uint->one; /* GLC */
335 args[7] = uint->zero; /* SLC */
336 args[8] = uint->zero; /* TFE */
337
338 return LLVMBuildBitCast(gallivm->builder,
339 build_intrinsic(gallivm->builder,
340 "llvm.SI.buffer.load.dword.i32.i32",
341 i32, args, 9,
342 LLVMReadOnlyAttribute | LLVMNoUnwindAttribute),
343 tgsi2llvmtype(bld_base, type), "");
344 }
345
346 static void declare_input_fs(
347 struct radeon_llvm_context *radeon_bld,
348 unsigned input_index,
349 const struct tgsi_full_declaration *decl)
350 {
351 struct lp_build_context *base = &radeon_bld->soa.bld_base.base;
352 struct si_shader_context *si_shader_ctx =
353 si_shader_context(&radeon_bld->soa.bld_base);
354 struct si_shader *shader = &si_shader_ctx->shader->shader;
355 struct lp_build_context *uint = &radeon_bld->soa.bld_base.uint_bld;
356 struct gallivm_state *gallivm = base->gallivm;
357 LLVMTypeRef input_type = LLVMFloatTypeInContext(gallivm->context);
358 LLVMValueRef main_fn = radeon_bld->main_fn;
359
360 LLVMValueRef interp_param;
361 const char * intr_name;
362
363 /* This value is:
364 * [15:0] NewPrimMask (Bit mask for each quad. It is set it the
365 * quad begins a new primitive. Bit 0 always needs
366 * to be unset)
367 * [32:16] ParamOffset
368 *
369 */
370 LLVMValueRef params = LLVMGetParam(main_fn, SI_PARAM_PRIM_MASK);
371 LLVMValueRef attr_number;
372
373 unsigned chan;
374
375 if (decl->Semantic.Name == TGSI_SEMANTIC_POSITION) {
376 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
377 unsigned soa_index =
378 radeon_llvm_reg_index_soa(input_index, chan);
379 radeon_bld->inputs[soa_index] =
380 LLVMGetParam(main_fn, SI_PARAM_POS_X_FLOAT + chan);
381
382 if (chan == 3)
383 /* RCP for fragcoord.w */
384 radeon_bld->inputs[soa_index] =
385 LLVMBuildFDiv(gallivm->builder,
386 lp_build_const_float(gallivm, 1.0f),
387 radeon_bld->inputs[soa_index],
388 "");
389 }
390 return;
391 }
392
393 if (decl->Semantic.Name == TGSI_SEMANTIC_FACE) {
394 LLVMValueRef face, is_face_positive;
395
396 face = LLVMGetParam(main_fn, SI_PARAM_FRONT_FACE);
397
398 is_face_positive = LLVMBuildFCmp(gallivm->builder,
399 LLVMRealUGT, face,
400 lp_build_const_float(gallivm, 0.0f),
401 "");
402
403 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 0)] =
404 LLVMBuildSelect(gallivm->builder,
405 is_face_positive,
406 lp_build_const_float(gallivm, 1.0f),
407 lp_build_const_float(gallivm, 0.0f),
408 "");
409 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 1)] =
410 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 2)] =
411 lp_build_const_float(gallivm, 0.0f);
412 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 3)] =
413 lp_build_const_float(gallivm, 1.0f);
414
415 return;
416 }
417
418 shader->input[input_index].param_offset = shader->nparam++;
419 attr_number = lp_build_const_int32(gallivm,
420 shader->input[input_index].param_offset);
421
422 switch (decl->Interp.Interpolate) {
423 case TGSI_INTERPOLATE_COLOR:
424 if (si_shader_ctx->shader->key.ps.flatshade) {
425 interp_param = 0;
426 } else {
427 if (decl->Interp.Centroid)
428 interp_param = LLVMGetParam(main_fn, SI_PARAM_PERSP_CENTROID);
429 else
430 interp_param = LLVMGetParam(main_fn, SI_PARAM_PERSP_CENTER);
431 }
432 break;
433 case TGSI_INTERPOLATE_CONSTANT:
434 interp_param = 0;
435 break;
436 case TGSI_INTERPOLATE_LINEAR:
437 if (decl->Interp.Centroid)
438 interp_param = LLVMGetParam(main_fn, SI_PARAM_LINEAR_CENTROID);
439 else
440 interp_param = LLVMGetParam(main_fn, SI_PARAM_LINEAR_CENTER);
441 break;
442 case TGSI_INTERPOLATE_PERSPECTIVE:
443 if (decl->Interp.Centroid)
444 interp_param = LLVMGetParam(main_fn, SI_PARAM_PERSP_CENTROID);
445 else
446 interp_param = LLVMGetParam(main_fn, SI_PARAM_PERSP_CENTER);
447 break;
448 default:
449 fprintf(stderr, "Warning: Unhandled interpolation mode.\n");
450 return;
451 }
452
453 intr_name = interp_param ? "llvm.SI.fs.interp" : "llvm.SI.fs.constant";
454
455 /* XXX: Could there be more than TGSI_NUM_CHANNELS (4) ? */
456 if (decl->Semantic.Name == TGSI_SEMANTIC_COLOR &&
457 si_shader_ctx->shader->key.ps.color_two_side) {
458 LLVMValueRef args[4];
459 LLVMValueRef face, is_face_positive;
460 LLVMValueRef back_attr_number =
461 lp_build_const_int32(gallivm,
462 shader->input[input_index].param_offset + 1);
463
464 face = LLVMGetParam(main_fn, SI_PARAM_FRONT_FACE);
465
466 is_face_positive = LLVMBuildFCmp(gallivm->builder,
467 LLVMRealUGT, face,
468 lp_build_const_float(gallivm, 0.0f),
469 "");
470
471 args[2] = params;
472 args[3] = interp_param;
473 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
474 LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan);
475 unsigned soa_index = radeon_llvm_reg_index_soa(input_index, chan);
476 LLVMValueRef front, back;
477
478 args[0] = llvm_chan;
479 args[1] = attr_number;
480 front = build_intrinsic(gallivm->builder, intr_name,
481 input_type, args, args[3] ? 4 : 3,
482 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
483
484 args[1] = back_attr_number;
485 back = build_intrinsic(gallivm->builder, intr_name,
486 input_type, args, args[3] ? 4 : 3,
487 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
488
489 radeon_bld->inputs[soa_index] =
490 LLVMBuildSelect(gallivm->builder,
491 is_face_positive,
492 front,
493 back,
494 "");
495 }
496
497 shader->nparam++;
498 } else if (decl->Semantic.Name == TGSI_SEMANTIC_FOG) {
499 LLVMValueRef args[4];
500
501 args[0] = uint->zero;
502 args[1] = attr_number;
503 args[2] = params;
504 args[3] = interp_param;
505 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 0)] =
506 build_intrinsic(gallivm->builder, intr_name,
507 input_type, args, args[3] ? 4 : 3,
508 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
509 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 1)] =
510 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 2)] =
511 lp_build_const_float(gallivm, 0.0f);
512 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 3)] =
513 lp_build_const_float(gallivm, 1.0f);
514 } else {
515 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
516 LLVMValueRef args[4];
517 LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan);
518 unsigned soa_index = radeon_llvm_reg_index_soa(input_index, chan);
519 args[0] = llvm_chan;
520 args[1] = attr_number;
521 args[2] = params;
522 args[3] = interp_param;
523 radeon_bld->inputs[soa_index] =
524 build_intrinsic(gallivm->builder, intr_name,
525 input_type, args, args[3] ? 4 : 3,
526 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
527 }
528 }
529 }
530
531 static void declare_system_value(
532 struct radeon_llvm_context * radeon_bld,
533 unsigned index,
534 const struct tgsi_full_declaration *decl)
535 {
536 struct si_shader_context *si_shader_ctx =
537 si_shader_context(&radeon_bld->soa.bld_base);
538 LLVMValueRef value = 0;
539
540 switch (decl->Semantic.Name) {
541 case TGSI_SEMANTIC_INSTANCEID:
542 value = LLVMGetParam(radeon_bld->main_fn,
543 si_shader_ctx->param_instance_id);
544 break;
545
546 case TGSI_SEMANTIC_VERTEXID:
547 value = LLVMGetParam(radeon_bld->main_fn,
548 si_shader_ctx->param_vertex_id);
549 break;
550
551 default:
552 assert(!"unknown system value");
553 return;
554 }
555
556 radeon_bld->system_values[index] = value;
557 }
558
559 static LLVMValueRef fetch_constant(
560 struct lp_build_tgsi_context * bld_base,
561 const struct tgsi_full_src_register *reg,
562 enum tgsi_opcode_type type,
563 unsigned swizzle)
564 {
565 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
566 struct lp_build_context * base = &bld_base->base;
567 const struct tgsi_ind_register *ireg = &reg->Indirect;
568 unsigned buf, idx;
569
570 LLVMValueRef args[2];
571 LLVMValueRef addr;
572 LLVMValueRef result;
573
574 if (swizzle == LP_CHAN_ALL) {
575 unsigned chan;
576 LLVMValueRef values[4];
577 for (chan = 0; chan < TGSI_NUM_CHANNELS; ++chan)
578 values[chan] = fetch_constant(bld_base, reg, type, chan);
579
580 return lp_build_gather_values(bld_base->base.gallivm, values, 4);
581 }
582
583 buf = reg->Register.Dimension ? reg->Dimension.Index : 0;
584 idx = reg->Register.Index * 4 + swizzle;
585
586 if (!reg->Register.Indirect)
587 return bitcast(bld_base, type, si_shader_ctx->constants[buf][idx]);
588
589 args[0] = si_shader_ctx->const_resource[buf];
590 args[1] = lp_build_const_int32(base->gallivm, idx * 4);
591 addr = si_shader_ctx->radeon_bld.soa.addr[ireg->Index][ireg->Swizzle];
592 addr = LLVMBuildLoad(base->gallivm->builder, addr, "load addr reg");
593 addr = lp_build_mul_imm(&bld_base->uint_bld, addr, 16);
594 args[1] = lp_build_add(&bld_base->uint_bld, addr, args[1]);
595
596 result = build_intrinsic(base->gallivm->builder, "llvm.SI.load.const", base->elem_type,
597 args, 2, LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
598
599 return bitcast(bld_base, type, result);
600 }
601
602 /* Initialize arguments for the shader export intrinsic */
603 static void si_llvm_init_export_args(struct lp_build_tgsi_context *bld_base,
604 LLVMValueRef *values,
605 unsigned target,
606 LLVMValueRef *args)
607 {
608 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
609 struct lp_build_context *uint =
610 &si_shader_ctx->radeon_bld.soa.bld_base.uint_bld;
611 struct lp_build_context *base = &bld_base->base;
612 unsigned compressed = 0;
613 unsigned chan;
614
615 if (si_shader_ctx->type == TGSI_PROCESSOR_FRAGMENT) {
616 int cbuf = target - V_008DFC_SQ_EXP_MRT;
617
618 if (cbuf >= 0 && cbuf < 8) {
619 compressed = (si_shader_ctx->shader->key.ps.export_16bpc >> cbuf) & 0x1;
620
621 if (compressed)
622 si_shader_ctx->shader->spi_shader_col_format |=
623 V_028714_SPI_SHADER_FP16_ABGR << (4 * cbuf);
624 else
625 si_shader_ctx->shader->spi_shader_col_format |=
626 V_028714_SPI_SHADER_32_ABGR << (4 * cbuf);
627
628 si_shader_ctx->shader->cb_shader_mask |= 0xf << (4 * cbuf);
629 }
630 }
631
632 if (compressed) {
633 /* Pixel shader needs to pack output values before export */
634 for (chan = 0; chan < 2; chan++ ) {
635 args[0] = values[2 * chan];
636 args[1] = values[2 * chan + 1];
637 args[chan + 5] =
638 build_intrinsic(base->gallivm->builder,
639 "llvm.SI.packf16",
640 LLVMInt32TypeInContext(base->gallivm->context),
641 args, 2,
642 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
643 args[chan + 7] = args[chan + 5] =
644 LLVMBuildBitCast(base->gallivm->builder,
645 args[chan + 5],
646 LLVMFloatTypeInContext(base->gallivm->context),
647 "");
648 }
649
650 /* Set COMPR flag */
651 args[4] = uint->one;
652 } else {
653 for (chan = 0; chan < 4; chan++ )
654 /* +5 because the first output value will be
655 * the 6th argument to the intrinsic. */
656 args[chan + 5] = values[chan];
657
658 /* Clear COMPR flag */
659 args[4] = uint->zero;
660 }
661
662 /* XXX: This controls which components of the output
663 * registers actually get exported. (e.g bit 0 means export
664 * X component, bit 1 means export Y component, etc.) I'm
665 * hard coding this to 0xf for now. In the future, we might
666 * want to do something else. */
667 args[0] = lp_build_const_int32(base->gallivm, 0xf);
668
669 /* Specify whether the EXEC mask represents the valid mask */
670 args[1] = uint->zero;
671
672 /* Specify whether this is the last export */
673 args[2] = uint->zero;
674
675 /* Specify the target we are exporting */
676 args[3] = lp_build_const_int32(base->gallivm, target);
677
678 /* XXX: We probably need to keep track of the output
679 * values, so we know what we are passing to the next
680 * stage. */
681 }
682
683 /* Load from output pointers and initialize arguments for the shader export intrinsic */
684 static void si_llvm_init_export_args_load(struct lp_build_tgsi_context *bld_base,
685 LLVMValueRef *out_ptr,
686 unsigned target,
687 LLVMValueRef *args)
688 {
689 struct gallivm_state *gallivm = bld_base->base.gallivm;
690 LLVMValueRef values[4];
691 int i;
692
693 for (i = 0; i < 4; i++)
694 values[i] = LLVMBuildLoad(gallivm->builder, out_ptr[i], "");
695
696 si_llvm_init_export_args(bld_base, values, target, args);
697 }
698
699 static void si_alpha_test(struct lp_build_tgsi_context *bld_base,
700 LLVMValueRef *out_ptr)
701 {
702 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
703 struct gallivm_state *gallivm = bld_base->base.gallivm;
704
705 if (si_shader_ctx->shader->key.ps.alpha_func != PIPE_FUNC_NEVER) {
706 LLVMValueRef alpha_ref = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
707 SI_PARAM_ALPHA_REF);
708
709 LLVMValueRef alpha_pass =
710 lp_build_cmp(&bld_base->base,
711 si_shader_ctx->shader->key.ps.alpha_func,
712 LLVMBuildLoad(gallivm->builder, out_ptr[3], ""),
713 alpha_ref);
714 LLVMValueRef arg =
715 lp_build_select(&bld_base->base,
716 alpha_pass,
717 lp_build_const_float(gallivm, 1.0f),
718 lp_build_const_float(gallivm, -1.0f));
719
720 build_intrinsic(gallivm->builder,
721 "llvm.AMDGPU.kill",
722 LLVMVoidTypeInContext(gallivm->context),
723 &arg, 1, 0);
724 } else {
725 build_intrinsic(gallivm->builder,
726 "llvm.AMDGPU.kilp",
727 LLVMVoidTypeInContext(gallivm->context),
728 NULL, 0, 0);
729 }
730 }
731
732 static void si_llvm_emit_clipvertex(struct lp_build_tgsi_context * bld_base,
733 LLVMValueRef (*pos)[9], LLVMValueRef *out_elts)
734 {
735 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
736 struct si_pipe_shader *shader = si_shader_ctx->shader;
737 struct lp_build_context *base = &bld_base->base;
738 struct lp_build_context *uint = &si_shader_ctx->radeon_bld.soa.bld_base.uint_bld;
739 unsigned reg_index;
740 unsigned chan;
741 unsigned const_chan;
742 LLVMValueRef base_elt;
743 LLVMValueRef ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_CONST);
744 LLVMValueRef constbuf_index = lp_build_const_int32(base->gallivm, NUM_PIPE_CONST_BUFFERS);
745 LLVMValueRef const_resource = build_indexed_load(si_shader_ctx, ptr, constbuf_index);
746
747 for (reg_index = 0; reg_index < 2; reg_index ++) {
748 LLVMValueRef *args = pos[2 + reg_index];
749
750 if (!(shader->key.vs.ucps_enabled & (1 << reg_index)))
751 continue;
752
753 shader->shader.clip_dist_write |= 0xf << (4 * reg_index);
754
755 args[5] =
756 args[6] =
757 args[7] =
758 args[8] = lp_build_const_float(base->gallivm, 0.0f);
759
760 /* Compute dot products of position and user clip plane vectors */
761 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
762 for (const_chan = 0; const_chan < TGSI_NUM_CHANNELS; const_chan++) {
763 args[0] = const_resource;
764 args[1] = lp_build_const_int32(base->gallivm,
765 ((reg_index * 4 + chan) * 4 +
766 const_chan) * 4);
767 base_elt = build_intrinsic(base->gallivm->builder,
768 "llvm.SI.load.const",
769 base->elem_type,
770 args, 2,
771 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
772 args[5 + chan] =
773 lp_build_add(base, args[5 + chan],
774 lp_build_mul(base, base_elt,
775 out_elts[const_chan]));
776 }
777 }
778
779 args[0] = lp_build_const_int32(base->gallivm, 0xf);
780 args[1] = uint->zero;
781 args[2] = uint->zero;
782 args[3] = lp_build_const_int32(base->gallivm,
783 V_008DFC_SQ_EXP_POS + 2 + reg_index);
784 args[4] = uint->zero;
785 }
786 }
787
788 static void si_dump_streamout(struct pipe_stream_output_info *so)
789 {
790 unsigned i;
791
792 if (so->num_outputs)
793 fprintf(stderr, "STREAMOUT\n");
794
795 for (i = 0; i < so->num_outputs; i++) {
796 unsigned mask = ((1 << so->output[i].num_components) - 1) <<
797 so->output[i].start_component;
798 fprintf(stderr, " %i: BUF%i[%i..%i] <- OUT[%i].%s%s%s%s\n",
799 i, so->output[i].output_buffer,
800 so->output[i].dst_offset, so->output[i].dst_offset + so->output[i].num_components - 1,
801 so->output[i].register_index,
802 mask & 1 ? "x" : "",
803 mask & 2 ? "y" : "",
804 mask & 4 ? "z" : "",
805 mask & 8 ? "w" : "");
806 }
807 }
808
809 /* TBUFFER_STORE_FORMAT_{X,XY,XYZ,XYZW} <- the suffix is selected by num_channels=1..4.
810 * The type of vdata must be one of i32 (num_channels=1), v2i32 (num_channels=2),
811 * or v4i32 (num_channels=3,4). */
812 static void build_tbuffer_store(struct si_shader_context *shader,
813 LLVMValueRef rsrc,
814 LLVMValueRef vdata,
815 unsigned num_channels,
816 LLVMValueRef vaddr,
817 LLVMValueRef soffset,
818 unsigned inst_offset,
819 unsigned dfmt,
820 unsigned nfmt,
821 unsigned offen,
822 unsigned idxen,
823 unsigned glc,
824 unsigned slc,
825 unsigned tfe)
826 {
827 struct gallivm_state *gallivm = &shader->radeon_bld.gallivm;
828 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
829 LLVMValueRef args[] = {
830 rsrc,
831 vdata,
832 LLVMConstInt(i32, num_channels, 0),
833 vaddr,
834 soffset,
835 LLVMConstInt(i32, inst_offset, 0),
836 LLVMConstInt(i32, dfmt, 0),
837 LLVMConstInt(i32, nfmt, 0),
838 LLVMConstInt(i32, offen, 0),
839 LLVMConstInt(i32, idxen, 0),
840 LLVMConstInt(i32, glc, 0),
841 LLVMConstInt(i32, slc, 0),
842 LLVMConstInt(i32, tfe, 0)
843 };
844
845 /* The intrinsic is overloaded, we need to add a type suffix for overloading to work. */
846 unsigned func = CLAMP(num_channels, 1, 3) - 1;
847 const char *types[] = {"i32", "v2i32", "v4i32"};
848 char name[256];
849 snprintf(name, sizeof(name), "llvm.SI.tbuffer.store.%s", types[func]);
850
851 lp_build_intrinsic(gallivm->builder, name,
852 LLVMVoidTypeInContext(gallivm->context),
853 args, Elements(args));
854 }
855
856 static void build_streamout_store(struct si_shader_context *shader,
857 LLVMValueRef rsrc,
858 LLVMValueRef vdata,
859 unsigned num_channels,
860 LLVMValueRef vaddr,
861 LLVMValueRef soffset,
862 unsigned inst_offset)
863 {
864 static unsigned dfmt[] = {
865 V_008F0C_BUF_DATA_FORMAT_32,
866 V_008F0C_BUF_DATA_FORMAT_32_32,
867 V_008F0C_BUF_DATA_FORMAT_32_32_32,
868 V_008F0C_BUF_DATA_FORMAT_32_32_32_32
869 };
870 assert(num_channels >= 1 && num_channels <= 4);
871
872 build_tbuffer_store(shader, rsrc, vdata, num_channels, vaddr, soffset,
873 inst_offset, dfmt[num_channels-1],
874 V_008F0C_BUF_NUM_FORMAT_UINT, 1, 0, 1, 1, 0);
875 }
876
877 /* On SI, the vertex shader is responsible for writing streamout data
878 * to buffers. */
879 static void si_llvm_emit_streamout(struct si_shader_context *shader)
880 {
881 struct pipe_stream_output_info *so = &shader->shader->selector->so;
882 struct gallivm_state *gallivm = &shader->radeon_bld.gallivm;
883 LLVMBuilderRef builder = gallivm->builder;
884 int i, j;
885 struct lp_build_if_state if_ctx;
886
887 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
888
889 LLVMValueRef so_param =
890 LLVMGetParam(shader->radeon_bld.main_fn,
891 shader->param_streamout_config);
892
893 /* Get bits [22:16], i.e. (so_param >> 16) & 127; */
894 LLVMValueRef so_vtx_count =
895 LLVMBuildAnd(builder,
896 LLVMBuildLShr(builder, so_param,
897 LLVMConstInt(i32, 16, 0), ""),
898 LLVMConstInt(i32, 127, 0), "");
899
900 LLVMValueRef tid = build_intrinsic(builder, "llvm.SI.tid", i32,
901 NULL, 0, LLVMReadNoneAttribute);
902
903 /* can_emit = tid < so_vtx_count; */
904 LLVMValueRef can_emit =
905 LLVMBuildICmp(builder, LLVMIntULT, tid, so_vtx_count, "");
906
907 /* Emit the streamout code conditionally. This actually avoids
908 * out-of-bounds buffer access. The hw tells us via the SGPR
909 * (so_vtx_count) which threads are allowed to emit streamout data. */
910 lp_build_if(&if_ctx, gallivm, can_emit);
911 {
912 /* The buffer offset is computed as follows:
913 * ByteOffset = streamout_offset[buffer_id]*4 +
914 * (streamout_write_index + thread_id)*stride[buffer_id] +
915 * attrib_offset
916 */
917
918 LLVMValueRef so_write_index =
919 LLVMGetParam(shader->radeon_bld.main_fn,
920 shader->param_streamout_write_index);
921
922 /* Compute (streamout_write_index + thread_id). */
923 so_write_index = LLVMBuildAdd(builder, so_write_index, tid, "");
924
925 /* Compute the write offset for each enabled buffer. */
926 LLVMValueRef so_write_offset[4] = {};
927 for (i = 0; i < 4; i++) {
928 if (!so->stride[i])
929 continue;
930
931 LLVMValueRef so_offset = LLVMGetParam(shader->radeon_bld.main_fn,
932 shader->param_streamout_offset[i]);
933 so_offset = LLVMBuildMul(builder, so_offset, LLVMConstInt(i32, 4, 0), "");
934
935 so_write_offset[i] = LLVMBuildMul(builder, so_write_index,
936 LLVMConstInt(i32, so->stride[i]*4, 0), "");
937 so_write_offset[i] = LLVMBuildAdd(builder, so_write_offset[i], so_offset, "");
938 }
939
940 LLVMValueRef (*outputs)[TGSI_NUM_CHANNELS] = shader->radeon_bld.soa.outputs;
941
942 /* Write streamout data. */
943 for (i = 0; i < so->num_outputs; i++) {
944 unsigned buf_idx = so->output[i].output_buffer;
945 unsigned reg = so->output[i].register_index;
946 unsigned start = so->output[i].start_component;
947 unsigned num_comps = so->output[i].num_components;
948 LLVMValueRef out[4];
949
950 assert(num_comps && num_comps <= 4);
951 if (!num_comps || num_comps > 4)
952 continue;
953
954 /* Load the output as int. */
955 for (j = 0; j < num_comps; j++) {
956 out[j] = LLVMBuildLoad(builder, outputs[reg][start+j], "");
957 out[j] = LLVMBuildBitCast(builder, out[j], i32, "");
958 }
959
960 /* Pack the output. */
961 LLVMValueRef vdata = NULL;
962
963 switch (num_comps) {
964 case 1: /* as i32 */
965 vdata = out[0];
966 break;
967 case 2: /* as v2i32 */
968 case 3: /* as v4i32 (aligned to 4) */
969 case 4: /* as v4i32 */
970 vdata = LLVMGetUndef(LLVMVectorType(i32, util_next_power_of_two(num_comps)));
971 for (j = 0; j < num_comps; j++) {
972 vdata = LLVMBuildInsertElement(builder, vdata, out[j],
973 LLVMConstInt(i32, j, 0), "");
974 }
975 break;
976 }
977
978 build_streamout_store(shader, shader->so_buffers[buf_idx],
979 vdata, num_comps,
980 so_write_offset[buf_idx],
981 LLVMConstInt(i32, 0, 0),
982 so->output[i].dst_offset*4);
983 }
984 }
985 lp_build_endif(&if_ctx);
986 }
987
988
989 /* Generate export instructions for hardware VS shader stage */
990 static void si_llvm_export_vs(struct lp_build_tgsi_context *bld_base,
991 struct si_shader_output_values *outputs,
992 unsigned noutput)
993 {
994 struct si_shader_context * si_shader_ctx = si_shader_context(bld_base);
995 struct si_shader * shader = &si_shader_ctx->shader->shader;
996 struct lp_build_context * base = &bld_base->base;
997 struct lp_build_context * uint =
998 &si_shader_ctx->radeon_bld.soa.bld_base.uint_bld;
999 LLVMValueRef args[9];
1000 LLVMValueRef pos_args[4][9] = { { 0 } };
1001 LLVMValueRef psize_value = NULL, edgeflag_value = NULL, layer_value = NULL;
1002 unsigned semantic_name, semantic_index, semantic_usage;
1003 unsigned target;
1004 unsigned param_count = 0;
1005 unsigned pos_idx;
1006 int i;
1007
1008 if (si_shader_ctx->shader->selector->so.num_outputs) {
1009 si_llvm_emit_streamout(si_shader_ctx);
1010 }
1011
1012 for (i = 0; i < noutput; i++) {
1013 semantic_name = outputs[i].name;
1014 semantic_index = outputs[i].index;
1015 semantic_usage = outputs[i].usage;
1016
1017 handle_semantic:
1018 /* Select the correct target */
1019 switch(semantic_name) {
1020 case TGSI_SEMANTIC_PSIZE:
1021 shader->vs_out_misc_write = true;
1022 shader->vs_out_point_size = true;
1023 psize_value = outputs[i].values[0];
1024 continue;
1025 case TGSI_SEMANTIC_EDGEFLAG:
1026 shader->vs_out_misc_write = true;
1027 shader->vs_out_edgeflag = true;
1028 edgeflag_value = outputs[i].values[0];
1029 continue;
1030 case TGSI_SEMANTIC_LAYER:
1031 shader->vs_out_misc_write = true;
1032 shader->vs_out_layer = true;
1033 layer_value = outputs[i].values[0];
1034 continue;
1035 case TGSI_SEMANTIC_POSITION:
1036 target = V_008DFC_SQ_EXP_POS;
1037 break;
1038 case TGSI_SEMANTIC_COLOR:
1039 case TGSI_SEMANTIC_BCOLOR:
1040 target = V_008DFC_SQ_EXP_PARAM + param_count;
1041 shader->output[i].param_offset = param_count;
1042 param_count++;
1043 break;
1044 case TGSI_SEMANTIC_CLIPDIST:
1045 if (!(si_shader_ctx->shader->key.vs.ucps_enabled &
1046 (1 << semantic_index)))
1047 continue;
1048 shader->clip_dist_write |=
1049 semantic_usage << (semantic_index << 2);
1050 target = V_008DFC_SQ_EXP_POS + 2 + semantic_index;
1051 break;
1052 case TGSI_SEMANTIC_CLIPVERTEX:
1053 si_llvm_emit_clipvertex(bld_base, pos_args, outputs[i].values);
1054 continue;
1055 case TGSI_SEMANTIC_PRIMID:
1056 case TGSI_SEMANTIC_FOG:
1057 case TGSI_SEMANTIC_GENERIC:
1058 target = V_008DFC_SQ_EXP_PARAM + param_count;
1059 shader->output[i].param_offset = param_count;
1060 param_count++;
1061 break;
1062 default:
1063 target = 0;
1064 fprintf(stderr,
1065 "Warning: SI unhandled vs output type:%d\n",
1066 semantic_name);
1067 }
1068
1069 si_llvm_init_export_args(bld_base, outputs[i].values, target, args);
1070
1071 if (target >= V_008DFC_SQ_EXP_POS &&
1072 target <= (V_008DFC_SQ_EXP_POS + 3)) {
1073 memcpy(pos_args[target - V_008DFC_SQ_EXP_POS],
1074 args, sizeof(args));
1075 } else {
1076 lp_build_intrinsic(base->gallivm->builder,
1077 "llvm.SI.export",
1078 LLVMVoidTypeInContext(base->gallivm->context),
1079 args, 9);
1080 }
1081
1082 if (semantic_name == TGSI_SEMANTIC_CLIPDIST) {
1083 semantic_name = TGSI_SEMANTIC_GENERIC;
1084 goto handle_semantic;
1085 }
1086 }
1087
1088 /* We need to add the position output manually if it's missing. */
1089 if (!pos_args[0][0]) {
1090 pos_args[0][0] = lp_build_const_int32(base->gallivm, 0xf); /* writemask */
1091 pos_args[0][1] = uint->zero; /* EXEC mask */
1092 pos_args[0][2] = uint->zero; /* last export? */
1093 pos_args[0][3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_POS);
1094 pos_args[0][4] = uint->zero; /* COMPR flag */
1095 pos_args[0][5] = base->zero; /* X */
1096 pos_args[0][6] = base->zero; /* Y */
1097 pos_args[0][7] = base->zero; /* Z */
1098 pos_args[0][8] = base->one; /* W */
1099 }
1100
1101 /* Write the misc vector (point size, edgeflag, layer, viewport). */
1102 if (shader->vs_out_misc_write) {
1103 pos_args[1][0] = lp_build_const_int32(base->gallivm, /* writemask */
1104 shader->vs_out_point_size |
1105 (shader->vs_out_edgeflag << 1) |
1106 (shader->vs_out_layer << 2));
1107 pos_args[1][1] = uint->zero; /* EXEC mask */
1108 pos_args[1][2] = uint->zero; /* last export? */
1109 pos_args[1][3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_POS + 1);
1110 pos_args[1][4] = uint->zero; /* COMPR flag */
1111 pos_args[1][5] = base->zero; /* X */
1112 pos_args[1][6] = base->zero; /* Y */
1113 pos_args[1][7] = base->zero; /* Z */
1114 pos_args[1][8] = base->zero; /* W */
1115
1116 if (shader->vs_out_point_size)
1117 pos_args[1][5] = psize_value;
1118
1119 if (shader->vs_out_edgeflag) {
1120 /* The output is a float, but the hw expects an integer
1121 * with the first bit containing the edge flag. */
1122 edgeflag_value = LLVMBuildFPToUI(base->gallivm->builder,
1123 edgeflag_value,
1124 bld_base->uint_bld.elem_type, "");
1125 edgeflag_value = lp_build_min(&bld_base->int_bld,
1126 edgeflag_value,
1127 bld_base->int_bld.one);
1128
1129 /* The LLVM intrinsic expects a float. */
1130 pos_args[1][6] = LLVMBuildBitCast(base->gallivm->builder,
1131 edgeflag_value,
1132 base->elem_type, "");
1133 }
1134
1135 if (shader->vs_out_layer)
1136 pos_args[1][7] = layer_value;
1137 }
1138
1139 for (i = 0; i < 4; i++)
1140 if (pos_args[i][0])
1141 shader->nr_pos_exports++;
1142
1143 pos_idx = 0;
1144 for (i = 0; i < 4; i++) {
1145 if (!pos_args[i][0])
1146 continue;
1147
1148 /* Specify the target we are exporting */
1149 pos_args[i][3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_POS + pos_idx++);
1150
1151 if (pos_idx == shader->nr_pos_exports)
1152 /* Specify that this is the last export */
1153 pos_args[i][2] = uint->one;
1154
1155 lp_build_intrinsic(base->gallivm->builder,
1156 "llvm.SI.export",
1157 LLVMVoidTypeInContext(base->gallivm->context),
1158 pos_args[i], 9);
1159 }
1160 }
1161
1162 static void si_llvm_emit_es_epilogue(struct lp_build_tgsi_context * bld_base)
1163 {
1164 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
1165 struct gallivm_state *gallivm = bld_base->base.gallivm;
1166 struct si_shader *es = &si_shader_ctx->shader->shader;
1167 struct si_shader *gs = si_shader_ctx->gs_for_vs;
1168 struct tgsi_parse_context *parse = &si_shader_ctx->parse;
1169 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
1170 LLVMValueRef t_list_ptr;
1171 LLVMValueRef t_list;
1172 unsigned chan;
1173 int i;
1174
1175 while (!tgsi_parse_end_of_tokens(parse)) {
1176 struct tgsi_full_declaration *d =
1177 &parse->FullToken.FullDeclaration;
1178
1179 tgsi_parse_token(parse);
1180
1181 if (parse->FullToken.Token.Type != TGSI_TOKEN_TYPE_DECLARATION)
1182 continue;
1183
1184 si_store_shader_io_attribs(es, d);
1185 }
1186
1187 /* Load the ESGS ring resource descriptor */
1188 t_list_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_CONST);
1189 t_list = build_indexed_load(si_shader_ctx, t_list_ptr,
1190 lp_build_const_int32(gallivm,
1191 NUM_PIPE_CONST_BUFFERS + 1));
1192
1193 for (i = 0; i < es->noutput; i++) {
1194 LLVMValueRef *out_ptr =
1195 si_shader_ctx->radeon_bld.soa.outputs[es->output[i].index];
1196 int j;
1197
1198 for (j = 0; j < gs->ninput; j++) {
1199 if (gs->input[j].name == es->output[i].name &&
1200 gs->input[j].sid == es->output[i].sid)
1201 break;
1202 }
1203 if (j == gs->ninput)
1204 continue;
1205
1206 for (chan = 0; chan < 4; chan++) {
1207 LLVMValueRef out_val = LLVMBuildLoad(gallivm->builder, out_ptr[chan], "");
1208 LLVMValueRef voffset =
1209 lp_build_const_int32(gallivm,
1210 (4 * gs->input[j].param_offset + chan) * 4);
1211 LLVMValueRef soffset =
1212 LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
1213 SI_PARAM_ES2GS_OFFSET);
1214
1215 out_val = LLVMBuildBitCast(gallivm->builder, out_val, i32, "");
1216
1217 build_tbuffer_store(si_shader_ctx, t_list, out_val, 1,
1218 voffset, soffset, 0,
1219 V_008F0C_BUF_DATA_FORMAT_32,
1220 V_008F0C_BUF_NUM_FORMAT_UINT,
1221 1, 0, 1, 1, 0);
1222 }
1223 }
1224 }
1225
1226 static void si_llvm_emit_gs_epilogue(struct lp_build_tgsi_context *bld_base)
1227 {
1228 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
1229 struct gallivm_state *gallivm = bld_base->base.gallivm;
1230 LLVMValueRef args[2];
1231
1232 args[0] = lp_build_const_int32(gallivm, SENDMSG_GS_OP_NOP | SENDMSG_GS_DONE);
1233 args[1] = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_GS_WAVE_ID);
1234 build_intrinsic(gallivm->builder, "llvm.SI.sendmsg",
1235 LLVMVoidTypeInContext(gallivm->context), args, 2,
1236 LLVMNoUnwindAttribute);
1237 }
1238
1239 static void si_llvm_emit_vs_epilogue(struct lp_build_tgsi_context * bld_base)
1240 {
1241 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
1242 struct gallivm_state *gallivm = bld_base->base.gallivm;
1243 struct si_pipe_shader *shader = si_shader_ctx->shader;
1244 struct tgsi_parse_context *parse = &si_shader_ctx->parse;
1245 struct si_shader_output_values *outputs = NULL;
1246 unsigned noutput = 0;
1247 int i;
1248
1249 while (!tgsi_parse_end_of_tokens(parse)) {
1250 struct tgsi_full_declaration *d =
1251 &parse->FullToken.FullDeclaration;
1252 unsigned index;
1253
1254 tgsi_parse_token(parse);
1255
1256 if (parse->FullToken.Token.Type != TGSI_TOKEN_TYPE_DECLARATION)
1257 continue;
1258
1259 i = si_store_shader_io_attribs(&shader->shader, d);
1260 if (i < 0)
1261 continue;
1262
1263 outputs = REALLOC(outputs, noutput * sizeof(outputs[0]),
1264 (noutput + 1) * sizeof(outputs[0]));
1265 for (index = d->Range.First; index <= d->Range.Last; index++) {
1266 outputs[noutput].name = d->Semantic.Name;
1267 outputs[noutput].index = d->Semantic.Index;
1268 outputs[noutput].usage = d->Declaration.UsageMask;
1269
1270 for (i = 0; i < 4; i++)
1271 outputs[noutput].values[i] =
1272 LLVMBuildLoad(gallivm->builder,
1273 si_shader_ctx->radeon_bld.soa.outputs[index][i],
1274 "");
1275 }
1276 noutput++;
1277 }
1278
1279 si_llvm_export_vs(bld_base, outputs, noutput);
1280 FREE(outputs);
1281 }
1282
1283 static void si_llvm_emit_fs_epilogue(struct lp_build_tgsi_context * bld_base)
1284 {
1285 struct si_shader_context * si_shader_ctx = si_shader_context(bld_base);
1286 struct si_shader * shader = &si_shader_ctx->shader->shader;
1287 struct lp_build_context * base = &bld_base->base;
1288 struct lp_build_context * uint =
1289 &si_shader_ctx->radeon_bld.soa.bld_base.uint_bld;
1290 struct tgsi_parse_context *parse = &si_shader_ctx->parse;
1291 LLVMValueRef args[9];
1292 LLVMValueRef last_args[9] = { 0 };
1293 unsigned semantic_name;
1294 int depth_index = -1, stencil_index = -1;
1295 int i;
1296
1297 while (!tgsi_parse_end_of_tokens(parse)) {
1298 struct tgsi_full_declaration *d =
1299 &parse->FullToken.FullDeclaration;
1300 unsigned target;
1301 unsigned index;
1302
1303 tgsi_parse_token(parse);
1304
1305 if (parse->FullToken.Token.Type == TGSI_TOKEN_TYPE_PROPERTY &&
1306 parse->FullToken.FullProperty.Property.PropertyName ==
1307 TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS)
1308 shader->fs_write_all = TRUE;
1309
1310 if (parse->FullToken.Token.Type != TGSI_TOKEN_TYPE_DECLARATION)
1311 continue;
1312
1313 i = si_store_shader_io_attribs(shader, d);
1314 if (i < 0)
1315 continue;
1316
1317 semantic_name = d->Semantic.Name;
1318 for (index = d->Range.First; index <= d->Range.Last; index++) {
1319 /* Select the correct target */
1320 switch(semantic_name) {
1321 case TGSI_SEMANTIC_POSITION:
1322 depth_index = index;
1323 continue;
1324 case TGSI_SEMANTIC_STENCIL:
1325 stencil_index = index;
1326 continue;
1327 case TGSI_SEMANTIC_COLOR:
1328 target = V_008DFC_SQ_EXP_MRT + d->Semantic.Index;
1329 if (si_shader_ctx->shader->key.ps.alpha_to_one)
1330 LLVMBuildStore(bld_base->base.gallivm->builder,
1331 bld_base->base.one,
1332 si_shader_ctx->radeon_bld.soa.outputs[index][3]);
1333
1334 if (d->Semantic.Index == 0 &&
1335 si_shader_ctx->shader->key.ps.alpha_func != PIPE_FUNC_ALWAYS)
1336 si_alpha_test(bld_base,
1337 si_shader_ctx->radeon_bld.soa.outputs[index]);
1338 break;
1339 default:
1340 target = 0;
1341 fprintf(stderr,
1342 "Warning: SI unhandled fs output type:%d\n",
1343 semantic_name);
1344 }
1345
1346 si_llvm_init_export_args_load(bld_base,
1347 si_shader_ctx->radeon_bld.soa.outputs[index],
1348 target, args);
1349
1350 if (semantic_name == TGSI_SEMANTIC_COLOR) {
1351 /* If there is an export instruction waiting to be emitted, do so now. */
1352 if (last_args[0]) {
1353 lp_build_intrinsic(base->gallivm->builder,
1354 "llvm.SI.export",
1355 LLVMVoidTypeInContext(base->gallivm->context),
1356 last_args, 9);
1357 }
1358
1359 /* This instruction will be emitted at the end of the shader. */
1360 memcpy(last_args, args, sizeof(args));
1361
1362 /* Handle FS_COLOR0_WRITES_ALL_CBUFS. */
1363 if (shader->fs_write_all && shader->output[i].sid == 0 &&
1364 si_shader_ctx->shader->key.ps.nr_cbufs > 1) {
1365 for (int c = 1; c < si_shader_ctx->shader->key.ps.nr_cbufs; c++) {
1366 si_llvm_init_export_args_load(bld_base,
1367 si_shader_ctx->radeon_bld.soa.outputs[index],
1368 V_008DFC_SQ_EXP_MRT + c, args);
1369 lp_build_intrinsic(base->gallivm->builder,
1370 "llvm.SI.export",
1371 LLVMVoidTypeInContext(base->gallivm->context),
1372 args, 9);
1373 }
1374 }
1375 } else {
1376 lp_build_intrinsic(base->gallivm->builder,
1377 "llvm.SI.export",
1378 LLVMVoidTypeInContext(base->gallivm->context),
1379 args, 9);
1380 }
1381 }
1382 }
1383
1384 if (depth_index >= 0 || stencil_index >= 0) {
1385 LLVMValueRef out_ptr;
1386 unsigned mask = 0;
1387
1388 /* Specify the target we are exporting */
1389 args[3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_MRTZ);
1390
1391 if (depth_index >= 0) {
1392 out_ptr = si_shader_ctx->radeon_bld.soa.outputs[depth_index][2];
1393 args[5] = LLVMBuildLoad(base->gallivm->builder, out_ptr, "");
1394 mask |= 0x1;
1395
1396 if (stencil_index < 0) {
1397 args[6] =
1398 args[7] =
1399 args[8] = args[5];
1400 }
1401 }
1402
1403 if (stencil_index >= 0) {
1404 out_ptr = si_shader_ctx->radeon_bld.soa.outputs[stencil_index][1];
1405 args[7] =
1406 args[8] =
1407 args[6] = LLVMBuildLoad(base->gallivm->builder, out_ptr, "");
1408 /* Only setting the stencil component bit (0x2) here
1409 * breaks some stencil piglit tests
1410 */
1411 mask |= 0x3;
1412
1413 if (depth_index < 0)
1414 args[5] = args[6];
1415 }
1416
1417 /* Specify which components to enable */
1418 args[0] = lp_build_const_int32(base->gallivm, mask);
1419
1420 args[1] =
1421 args[2] =
1422 args[4] = uint->zero;
1423
1424 if (last_args[0])
1425 lp_build_intrinsic(base->gallivm->builder,
1426 "llvm.SI.export",
1427 LLVMVoidTypeInContext(base->gallivm->context),
1428 args, 9);
1429 else
1430 memcpy(last_args, args, sizeof(args));
1431 }
1432
1433 if (!last_args[0]) {
1434 /* Specify which components to enable */
1435 last_args[0] = lp_build_const_int32(base->gallivm, 0x0);
1436
1437 /* Specify the target we are exporting */
1438 last_args[3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_MRT);
1439
1440 /* Set COMPR flag to zero to export data as 32-bit */
1441 last_args[4] = uint->zero;
1442
1443 /* dummy bits */
1444 last_args[5]= uint->zero;
1445 last_args[6]= uint->zero;
1446 last_args[7]= uint->zero;
1447 last_args[8]= uint->zero;
1448
1449 si_shader_ctx->shader->spi_shader_col_format |=
1450 V_028714_SPI_SHADER_32_ABGR;
1451 si_shader_ctx->shader->cb_shader_mask |= S_02823C_OUTPUT0_ENABLE(0xf);
1452 }
1453
1454 /* Specify whether the EXEC mask represents the valid mask */
1455 last_args[1] = uint->one;
1456
1457 /* Specify that this is the last export */
1458 last_args[2] = lp_build_const_int32(base->gallivm, 1);
1459
1460 lp_build_intrinsic(base->gallivm->builder,
1461 "llvm.SI.export",
1462 LLVMVoidTypeInContext(base->gallivm->context),
1463 last_args, 9);
1464 }
1465
1466 static const struct lp_build_tgsi_action txf_action;
1467
1468 static void build_tex_intrinsic(const struct lp_build_tgsi_action * action,
1469 struct lp_build_tgsi_context * bld_base,
1470 struct lp_build_emit_data * emit_data);
1471
1472 static void tex_fetch_args(
1473 struct lp_build_tgsi_context * bld_base,
1474 struct lp_build_emit_data * emit_data)
1475 {
1476 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
1477 struct gallivm_state *gallivm = bld_base->base.gallivm;
1478 const struct tgsi_full_instruction * inst = emit_data->inst;
1479 unsigned opcode = inst->Instruction.Opcode;
1480 unsigned target = inst->Texture.Texture;
1481 LLVMValueRef coords[4];
1482 LLVMValueRef address[16];
1483 int ref_pos;
1484 unsigned num_coords = tgsi_util_get_texture_coord_dim(target, &ref_pos);
1485 unsigned count = 0;
1486 unsigned chan;
1487 unsigned sampler_src = emit_data->inst->Instruction.NumSrcRegs - 1;
1488 unsigned sampler_index = emit_data->inst->Src[sampler_src].Register.Index;
1489
1490 if (target == TGSI_TEXTURE_BUFFER) {
1491 LLVMTypeRef i128 = LLVMIntTypeInContext(gallivm->context, 128);
1492 LLVMTypeRef v2i128 = LLVMVectorType(i128, 2);
1493 LLVMTypeRef i8 = LLVMInt8TypeInContext(gallivm->context);
1494 LLVMTypeRef v16i8 = LLVMVectorType(i8, 16);
1495
1496 /* Truncate v32i8 to v16i8. */
1497 LLVMValueRef res = si_shader_ctx->resources[sampler_index];
1498 res = LLVMBuildBitCast(gallivm->builder, res, v2i128, "");
1499 res = LLVMBuildExtractElement(gallivm->builder, res, bld_base->uint_bld.zero, "");
1500 res = LLVMBuildBitCast(gallivm->builder, res, v16i8, "");
1501
1502 emit_data->dst_type = LLVMVectorType(bld_base->base.elem_type, 4);
1503 emit_data->args[0] = res;
1504 emit_data->args[1] = bld_base->uint_bld.zero;
1505 emit_data->args[2] = lp_build_emit_fetch(bld_base, emit_data->inst, 0, 0);
1506 emit_data->arg_count = 3;
1507 return;
1508 }
1509
1510 /* Fetch and project texture coordinates */
1511 coords[3] = lp_build_emit_fetch(bld_base, emit_data->inst, 0, TGSI_CHAN_W);
1512 for (chan = 0; chan < 3; chan++ ) {
1513 coords[chan] = lp_build_emit_fetch(bld_base,
1514 emit_data->inst, 0,
1515 chan);
1516 if (opcode == TGSI_OPCODE_TXP)
1517 coords[chan] = lp_build_emit_llvm_binary(bld_base,
1518 TGSI_OPCODE_DIV,
1519 coords[chan],
1520 coords[3]);
1521 }
1522
1523 if (opcode == TGSI_OPCODE_TXP)
1524 coords[3] = bld_base->base.one;
1525
1526 /* Pack LOD bias value */
1527 if (opcode == TGSI_OPCODE_TXB)
1528 address[count++] = coords[3];
1529
1530 if (target == TGSI_TEXTURE_CUBE || target == TGSI_TEXTURE_SHADOWCUBE)
1531 radeon_llvm_emit_prepare_cube_coords(bld_base, emit_data, coords);
1532
1533 /* Pack depth comparison value */
1534 switch (target) {
1535 case TGSI_TEXTURE_SHADOW1D:
1536 case TGSI_TEXTURE_SHADOW1D_ARRAY:
1537 case TGSI_TEXTURE_SHADOW2D:
1538 case TGSI_TEXTURE_SHADOWRECT:
1539 case TGSI_TEXTURE_SHADOWCUBE:
1540 case TGSI_TEXTURE_SHADOW2D_ARRAY:
1541 assert(ref_pos >= 0);
1542 address[count++] = coords[ref_pos];
1543 break;
1544 case TGSI_TEXTURE_SHADOWCUBE_ARRAY:
1545 address[count++] = lp_build_emit_fetch(bld_base, inst, 1, 0);
1546 }
1547
1548 /* Pack user derivatives */
1549 if (opcode == TGSI_OPCODE_TXD) {
1550 for (chan = 0; chan < 2; chan++) {
1551 address[count++] = lp_build_emit_fetch(bld_base, inst, 1, chan);
1552 if (num_coords > 1)
1553 address[count++] = lp_build_emit_fetch(bld_base, inst, 2, chan);
1554 }
1555 }
1556
1557 /* Pack texture coordinates */
1558 address[count++] = coords[0];
1559 if (num_coords > 1)
1560 address[count++] = coords[1];
1561 if (num_coords > 2)
1562 address[count++] = coords[2];
1563
1564 /* Pack LOD or sample index */
1565 if (opcode == TGSI_OPCODE_TXL || opcode == TGSI_OPCODE_TXF)
1566 address[count++] = coords[3];
1567
1568 if (count > 16) {
1569 assert(!"Cannot handle more than 16 texture address parameters");
1570 count = 16;
1571 }
1572
1573 for (chan = 0; chan < count; chan++ ) {
1574 address[chan] = LLVMBuildBitCast(gallivm->builder,
1575 address[chan],
1576 LLVMInt32TypeInContext(gallivm->context),
1577 "");
1578 }
1579
1580 /* Adjust the sample index according to FMASK.
1581 *
1582 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
1583 * which is the identity mapping. Each nibble says which physical sample
1584 * should be fetched to get that sample.
1585 *
1586 * For example, 0x11111100 means there are only 2 samples stored and
1587 * the second sample covers 3/4 of the pixel. When reading samples 0
1588 * and 1, return physical sample 0 (determined by the first two 0s
1589 * in FMASK), otherwise return physical sample 1.
1590 *
1591 * The sample index should be adjusted as follows:
1592 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
1593 */
1594 if (target == TGSI_TEXTURE_2D_MSAA ||
1595 target == TGSI_TEXTURE_2D_ARRAY_MSAA) {
1596 struct lp_build_context *uint_bld = &bld_base->uint_bld;
1597 struct lp_build_emit_data txf_emit_data = *emit_data;
1598 LLVMValueRef txf_address[4];
1599 unsigned txf_count = count;
1600
1601 memcpy(txf_address, address, sizeof(txf_address));
1602
1603 if (target == TGSI_TEXTURE_2D_MSAA) {
1604 txf_address[2] = bld_base->uint_bld.zero;
1605 }
1606 txf_address[3] = bld_base->uint_bld.zero;
1607
1608 /* Pad to a power-of-two size. */
1609 while (txf_count < util_next_power_of_two(txf_count))
1610 txf_address[txf_count++] = LLVMGetUndef(LLVMInt32TypeInContext(gallivm->context));
1611
1612 /* Read FMASK using TXF. */
1613 txf_emit_data.chan = 0;
1614 txf_emit_data.dst_type = LLVMVectorType(
1615 LLVMInt32TypeInContext(bld_base->base.gallivm->context), 4);
1616 txf_emit_data.args[0] = lp_build_gather_values(gallivm, txf_address, txf_count);
1617 txf_emit_data.args[1] = si_shader_ctx->resources[FMASK_TEX_OFFSET + sampler_index];
1618 txf_emit_data.args[2] = lp_build_const_int32(bld_base->base.gallivm,
1619 target == TGSI_TEXTURE_2D_MSAA ? TGSI_TEXTURE_2D : TGSI_TEXTURE_2D_ARRAY);
1620 txf_emit_data.arg_count = 3;
1621
1622 build_tex_intrinsic(&txf_action, bld_base, &txf_emit_data);
1623
1624 /* Initialize some constants. */
1625 LLVMValueRef four = LLVMConstInt(uint_bld->elem_type, 4, 0);
1626 LLVMValueRef F = LLVMConstInt(uint_bld->elem_type, 0xF, 0);
1627
1628 /* Apply the formula. */
1629 LLVMValueRef fmask =
1630 LLVMBuildExtractElement(gallivm->builder,
1631 txf_emit_data.output[0],
1632 uint_bld->zero, "");
1633
1634 unsigned sample_chan = target == TGSI_TEXTURE_2D_MSAA ? 2 : 3;
1635
1636 LLVMValueRef sample_index4 =
1637 LLVMBuildMul(gallivm->builder, address[sample_chan], four, "");
1638
1639 LLVMValueRef shifted_fmask =
1640 LLVMBuildLShr(gallivm->builder, fmask, sample_index4, "");
1641
1642 LLVMValueRef final_sample =
1643 LLVMBuildAnd(gallivm->builder, shifted_fmask, F, "");
1644
1645 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
1646 * resource descriptor is 0 (invalid),
1647 */
1648 LLVMValueRef fmask_desc =
1649 LLVMBuildBitCast(gallivm->builder,
1650 si_shader_ctx->resources[FMASK_TEX_OFFSET + sampler_index],
1651 LLVMVectorType(uint_bld->elem_type, 8), "");
1652
1653 LLVMValueRef fmask_word1 =
1654 LLVMBuildExtractElement(gallivm->builder, fmask_desc,
1655 uint_bld->one, "");
1656
1657 LLVMValueRef word1_is_nonzero =
1658 LLVMBuildICmp(gallivm->builder, LLVMIntNE,
1659 fmask_word1, uint_bld->zero, "");
1660
1661 /* Replace the MSAA sample index. */
1662 address[sample_chan] =
1663 LLVMBuildSelect(gallivm->builder, word1_is_nonzero,
1664 final_sample, address[sample_chan], "");
1665 }
1666
1667 /* Resource */
1668 emit_data->args[1] = si_shader_ctx->resources[sampler_index];
1669
1670 if (opcode == TGSI_OPCODE_TXF) {
1671 /* add tex offsets */
1672 if (inst->Texture.NumOffsets) {
1673 struct lp_build_context *uint_bld = &bld_base->uint_bld;
1674 struct lp_build_tgsi_soa_context *bld = lp_soa_context(bld_base);
1675 const struct tgsi_texture_offset * off = inst->TexOffsets;
1676
1677 assert(inst->Texture.NumOffsets == 1);
1678
1679 switch (target) {
1680 case TGSI_TEXTURE_3D:
1681 address[2] = lp_build_add(uint_bld, address[2],
1682 bld->immediates[off->Index][off->SwizzleZ]);
1683 /* fall through */
1684 case TGSI_TEXTURE_2D:
1685 case TGSI_TEXTURE_SHADOW2D:
1686 case TGSI_TEXTURE_RECT:
1687 case TGSI_TEXTURE_SHADOWRECT:
1688 case TGSI_TEXTURE_2D_ARRAY:
1689 case TGSI_TEXTURE_SHADOW2D_ARRAY:
1690 address[1] =
1691 lp_build_add(uint_bld, address[1],
1692 bld->immediates[off->Index][off->SwizzleY]);
1693 /* fall through */
1694 case TGSI_TEXTURE_1D:
1695 case TGSI_TEXTURE_SHADOW1D:
1696 case TGSI_TEXTURE_1D_ARRAY:
1697 case TGSI_TEXTURE_SHADOW1D_ARRAY:
1698 address[0] =
1699 lp_build_add(uint_bld, address[0],
1700 bld->immediates[off->Index][off->SwizzleX]);
1701 break;
1702 /* texture offsets do not apply to other texture targets */
1703 }
1704 }
1705
1706 emit_data->dst_type = LLVMVectorType(
1707 LLVMInt32TypeInContext(bld_base->base.gallivm->context),
1708 4);
1709
1710 emit_data->arg_count = 3;
1711 } else {
1712 /* Sampler */
1713 emit_data->args[2] = si_shader_ctx->samplers[sampler_index];
1714
1715 emit_data->dst_type = LLVMVectorType(
1716 LLVMFloatTypeInContext(bld_base->base.gallivm->context),
1717 4);
1718
1719 emit_data->arg_count = 4;
1720 }
1721
1722 /* Dimensions */
1723 emit_data->args[emit_data->arg_count - 1] =
1724 lp_build_const_int32(bld_base->base.gallivm, target);
1725
1726 /* Pad to power of two vector */
1727 while (count < util_next_power_of_two(count))
1728 address[count++] = LLVMGetUndef(LLVMInt32TypeInContext(gallivm->context));
1729
1730 emit_data->args[0] = lp_build_gather_values(gallivm, address, count);
1731 }
1732
1733 static void build_tex_intrinsic(const struct lp_build_tgsi_action * action,
1734 struct lp_build_tgsi_context * bld_base,
1735 struct lp_build_emit_data * emit_data)
1736 {
1737 struct lp_build_context * base = &bld_base->base;
1738 char intr_name[127];
1739
1740 if (emit_data->inst->Texture.Texture == TGSI_TEXTURE_BUFFER) {
1741 emit_data->output[emit_data->chan] = build_intrinsic(
1742 base->gallivm->builder,
1743 "llvm.SI.vs.load.input", emit_data->dst_type,
1744 emit_data->args, emit_data->arg_count,
1745 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
1746 return;
1747 }
1748
1749 sprintf(intr_name, "%sv%ui32", action->intr_name,
1750 LLVMGetVectorSize(LLVMTypeOf(emit_data->args[0])));
1751
1752 emit_data->output[emit_data->chan] = build_intrinsic(
1753 base->gallivm->builder, intr_name, emit_data->dst_type,
1754 emit_data->args, emit_data->arg_count,
1755 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
1756 }
1757
1758 static void txq_fetch_args(
1759 struct lp_build_tgsi_context * bld_base,
1760 struct lp_build_emit_data * emit_data)
1761 {
1762 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
1763 const struct tgsi_full_instruction *inst = emit_data->inst;
1764 struct gallivm_state *gallivm = bld_base->base.gallivm;
1765
1766 if (inst->Texture.Texture == TGSI_TEXTURE_BUFFER) {
1767 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
1768 LLVMTypeRef v8i32 = LLVMVectorType(i32, 8);
1769
1770 /* Read the size from the buffer descriptor directly. */
1771 LLVMValueRef size = si_shader_ctx->resources[inst->Src[1].Register.Index];
1772 size = LLVMBuildBitCast(gallivm->builder, size, v8i32, "");
1773 size = LLVMBuildExtractElement(gallivm->builder, size,
1774 lp_build_const_int32(gallivm, 2), "");
1775 emit_data->args[0] = size;
1776 return;
1777 }
1778
1779 /* Mip level */
1780 emit_data->args[0] = lp_build_emit_fetch(bld_base, inst, 0, TGSI_CHAN_X);
1781
1782 /* Resource */
1783 emit_data->args[1] = si_shader_ctx->resources[inst->Src[1].Register.Index];
1784
1785 /* Dimensions */
1786 emit_data->args[2] = lp_build_const_int32(bld_base->base.gallivm,
1787 inst->Texture.Texture);
1788
1789 emit_data->arg_count = 3;
1790
1791 emit_data->dst_type = LLVMVectorType(
1792 LLVMInt32TypeInContext(bld_base->base.gallivm->context),
1793 4);
1794 }
1795
1796 static void build_txq_intrinsic(const struct lp_build_tgsi_action * action,
1797 struct lp_build_tgsi_context * bld_base,
1798 struct lp_build_emit_data * emit_data)
1799 {
1800 if (emit_data->inst->Texture.Texture == TGSI_TEXTURE_BUFFER) {
1801 /* Just return the buffer size. */
1802 emit_data->output[emit_data->chan] = emit_data->args[0];
1803 return;
1804 }
1805
1806 build_tgsi_intrinsic_nomem(action, bld_base, emit_data);
1807 }
1808
1809 #if HAVE_LLVM >= 0x0304
1810
1811 static void si_llvm_emit_ddxy(
1812 const struct lp_build_tgsi_action * action,
1813 struct lp_build_tgsi_context * bld_base,
1814 struct lp_build_emit_data * emit_data)
1815 {
1816 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
1817 struct gallivm_state *gallivm = bld_base->base.gallivm;
1818 struct lp_build_context * base = &bld_base->base;
1819 const struct tgsi_full_instruction *inst = emit_data->inst;
1820 unsigned opcode = inst->Instruction.Opcode;
1821 LLVMValueRef indices[2];
1822 LLVMValueRef store_ptr, load_ptr0, load_ptr1;
1823 LLVMValueRef tl, trbl, result[4];
1824 LLVMTypeRef i32;
1825 unsigned swizzle[4];
1826 unsigned c;
1827
1828 i32 = LLVMInt32TypeInContext(gallivm->context);
1829
1830 indices[0] = bld_base->uint_bld.zero;
1831 indices[1] = build_intrinsic(gallivm->builder, "llvm.SI.tid", i32,
1832 NULL, 0, LLVMReadNoneAttribute);
1833 store_ptr = LLVMBuildGEP(gallivm->builder, si_shader_ctx->ddxy_lds,
1834 indices, 2, "");
1835
1836 indices[1] = LLVMBuildAnd(gallivm->builder, indices[1],
1837 lp_build_const_int32(gallivm, 0xfffffffc), "");
1838 load_ptr0 = LLVMBuildGEP(gallivm->builder, si_shader_ctx->ddxy_lds,
1839 indices, 2, "");
1840
1841 indices[1] = LLVMBuildAdd(gallivm->builder, indices[1],
1842 lp_build_const_int32(gallivm,
1843 opcode == TGSI_OPCODE_DDX ? 1 : 2),
1844 "");
1845 load_ptr1 = LLVMBuildGEP(gallivm->builder, si_shader_ctx->ddxy_lds,
1846 indices, 2, "");
1847
1848 for (c = 0; c < 4; ++c) {
1849 unsigned i;
1850
1851 swizzle[c] = tgsi_util_get_full_src_register_swizzle(&inst->Src[0], c);
1852 for (i = 0; i < c; ++i) {
1853 if (swizzle[i] == swizzle[c]) {
1854 result[c] = result[i];
1855 break;
1856 }
1857 }
1858 if (i != c)
1859 continue;
1860
1861 LLVMBuildStore(gallivm->builder,
1862 LLVMBuildBitCast(gallivm->builder,
1863 lp_build_emit_fetch(bld_base, inst, 0, c),
1864 i32, ""),
1865 store_ptr);
1866
1867 tl = LLVMBuildLoad(gallivm->builder, load_ptr0, "");
1868 tl = LLVMBuildBitCast(gallivm->builder, tl, base->elem_type, "");
1869
1870 trbl = LLVMBuildLoad(gallivm->builder, load_ptr1, "");
1871 trbl = LLVMBuildBitCast(gallivm->builder, trbl, base->elem_type, "");
1872
1873 result[c] = LLVMBuildFSub(gallivm->builder, trbl, tl, "");
1874 }
1875
1876 emit_data->output[0] = lp_build_gather_values(gallivm, result, 4);
1877 }
1878
1879 #endif /* HAVE_LLVM >= 0x0304 */
1880
1881 /* Emit one vertex from the geometry shader */
1882 static void si_llvm_emit_vertex(
1883 const struct lp_build_tgsi_action *action,
1884 struct lp_build_tgsi_context *bld_base,
1885 struct lp_build_emit_data *emit_data)
1886 {
1887 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
1888 struct lp_build_context *uint = &bld_base->uint_bld;
1889 struct si_shader *shader = &si_shader_ctx->shader->shader;
1890 struct gallivm_state *gallivm = bld_base->base.gallivm;
1891 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
1892 LLVMValueRef gs_next_vertex;
1893 LLVMValueRef t_list_ptr;
1894 LLVMValueRef t_list;
1895 LLVMValueRef args[2];
1896 unsigned chan;
1897 int i;
1898
1899 /* Load the GSVS ring resource descriptor */
1900 t_list_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_CONST);
1901 t_list = build_indexed_load(si_shader_ctx, t_list_ptr,
1902 lp_build_const_int32(gallivm,
1903 NUM_PIPE_CONST_BUFFERS + 2));
1904
1905 if (shader->noutput == 0) {
1906 struct tgsi_parse_context *parse = &si_shader_ctx->parse;
1907
1908 while (!tgsi_parse_end_of_tokens(parse)) {
1909 tgsi_parse_token(parse);
1910
1911 if (parse->FullToken.Token.Type == TGSI_TOKEN_TYPE_DECLARATION) {
1912 struct tgsi_full_declaration *d = &parse->FullToken.FullDeclaration;
1913
1914 if (d->Declaration.File == TGSI_FILE_OUTPUT)
1915 si_store_shader_io_attribs(shader, d);
1916 }
1917 }
1918 }
1919
1920 /* Write vertex attribute values to GSVS ring */
1921 gs_next_vertex = LLVMBuildLoad(gallivm->builder, si_shader_ctx->gs_next_vertex, "");
1922 for (i = 0; i < shader->noutput; i++) {
1923 LLVMValueRef *out_ptr =
1924 si_shader_ctx->radeon_bld.soa.outputs[shader->output[i].index];
1925
1926 for (chan = 0; chan < 4; chan++) {
1927 LLVMValueRef out_val = LLVMBuildLoad(gallivm->builder, out_ptr[chan], "");
1928 LLVMValueRef soffset =
1929 LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
1930 SI_PARAM_GS2VS_OFFSET);
1931 LLVMValueRef voffset =
1932 lp_build_const_int32(gallivm, (i * 4 + chan) *
1933 shader->gs_max_out_vertices);
1934
1935 voffset = lp_build_add(uint, voffset, gs_next_vertex);
1936 voffset = lp_build_mul_imm(uint, voffset, 4);
1937
1938 out_val = LLVMBuildBitCast(gallivm->builder, out_val, i32, "");
1939
1940 build_tbuffer_store(si_shader_ctx, t_list, out_val, 1,
1941 voffset, soffset, 0,
1942 V_008F0C_BUF_DATA_FORMAT_32,
1943 V_008F0C_BUF_NUM_FORMAT_UINT,
1944 1, 0, 1, 1, 0);
1945 }
1946 }
1947 gs_next_vertex = lp_build_add(uint, gs_next_vertex,
1948 lp_build_const_int32(gallivm, 1));
1949 LLVMBuildStore(gallivm->builder, gs_next_vertex, si_shader_ctx->gs_next_vertex);
1950
1951 /* Signal vertex emission */
1952 args[0] = lp_build_const_int32(gallivm, SENDMSG_GS_OP_EMIT | SENDMSG_GS);
1953 args[1] = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_GS_WAVE_ID);
1954 build_intrinsic(gallivm->builder, "llvm.SI.sendmsg",
1955 LLVMVoidTypeInContext(gallivm->context), args, 2,
1956 LLVMNoUnwindAttribute);
1957 }
1958
1959 /* Cut one primitive from the geometry shader */
1960 static void si_llvm_emit_primitive(
1961 const struct lp_build_tgsi_action *action,
1962 struct lp_build_tgsi_context *bld_base,
1963 struct lp_build_emit_data *emit_data)
1964 {
1965 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
1966 struct gallivm_state *gallivm = bld_base->base.gallivm;
1967 LLVMValueRef args[2];
1968
1969 /* Signal primitive cut */
1970 args[0] = lp_build_const_int32(gallivm, SENDMSG_GS_OP_CUT | SENDMSG_GS);
1971 args[1] = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_GS_WAVE_ID);
1972 build_intrinsic(gallivm->builder, "llvm.SI.sendmsg",
1973 LLVMVoidTypeInContext(gallivm->context), args, 2,
1974 LLVMNoUnwindAttribute);
1975 }
1976
1977 static const struct lp_build_tgsi_action tex_action = {
1978 .fetch_args = tex_fetch_args,
1979 .emit = build_tex_intrinsic,
1980 .intr_name = "llvm.SI.sample."
1981 };
1982
1983 static const struct lp_build_tgsi_action txb_action = {
1984 .fetch_args = tex_fetch_args,
1985 .emit = build_tex_intrinsic,
1986 .intr_name = "llvm.SI.sampleb."
1987 };
1988
1989 #if HAVE_LLVM >= 0x0304
1990 static const struct lp_build_tgsi_action txd_action = {
1991 .fetch_args = tex_fetch_args,
1992 .emit = build_tex_intrinsic,
1993 .intr_name = "llvm.SI.sampled."
1994 };
1995 #endif
1996
1997 static const struct lp_build_tgsi_action txf_action = {
1998 .fetch_args = tex_fetch_args,
1999 .emit = build_tex_intrinsic,
2000 .intr_name = "llvm.SI.imageload."
2001 };
2002
2003 static const struct lp_build_tgsi_action txl_action = {
2004 .fetch_args = tex_fetch_args,
2005 .emit = build_tex_intrinsic,
2006 .intr_name = "llvm.SI.samplel."
2007 };
2008
2009 static const struct lp_build_tgsi_action txq_action = {
2010 .fetch_args = txq_fetch_args,
2011 .emit = build_txq_intrinsic,
2012 .intr_name = "llvm.SI.resinfo"
2013 };
2014
2015 static void create_meta_data(struct si_shader_context *si_shader_ctx)
2016 {
2017 struct gallivm_state *gallivm = si_shader_ctx->radeon_bld.soa.bld_base.base.gallivm;
2018 LLVMValueRef args[3];
2019
2020 args[0] = LLVMMDStringInContext(gallivm->context, "const", 5);
2021 args[1] = 0;
2022 args[2] = lp_build_const_int32(gallivm, 1);
2023
2024 si_shader_ctx->const_md = LLVMMDNodeInContext(gallivm->context, args, 3);
2025 }
2026
2027 static void create_function(struct si_shader_context *si_shader_ctx)
2028 {
2029 struct lp_build_tgsi_context *bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
2030 struct gallivm_state *gallivm = bld_base->base.gallivm;
2031 struct si_pipe_shader *shader = si_shader_ctx->shader;
2032 LLVMTypeRef params[21], f32, i8, i32, v2i32, v3i32;
2033 unsigned i, last_sgpr, num_params;
2034
2035 i8 = LLVMInt8TypeInContext(gallivm->context);
2036 i32 = LLVMInt32TypeInContext(gallivm->context);
2037 f32 = LLVMFloatTypeInContext(gallivm->context);
2038 v2i32 = LLVMVectorType(i32, 2);
2039 v3i32 = LLVMVectorType(i32, 3);
2040
2041 params[SI_PARAM_CONST] = LLVMPointerType(
2042 LLVMArrayType(LLVMVectorType(i8, 16), NUM_CONST_BUFFERS), CONST_ADDR_SPACE);
2043 /* We assume at most 16 textures per program at the moment.
2044 * This need probably need to be changed to support bindless textures */
2045 params[SI_PARAM_SAMPLER] = LLVMPointerType(
2046 LLVMArrayType(LLVMVectorType(i8, 16), NUM_SAMPLER_VIEWS), CONST_ADDR_SPACE);
2047 params[SI_PARAM_RESOURCE] = LLVMPointerType(
2048 LLVMArrayType(LLVMVectorType(i8, 32), NUM_SAMPLER_STATES), CONST_ADDR_SPACE);
2049
2050 switch (si_shader_ctx->type) {
2051 case TGSI_PROCESSOR_VERTEX:
2052 params[SI_PARAM_VERTEX_BUFFER] = params[SI_PARAM_CONST];
2053 params[SI_PARAM_SO_BUFFER] = params[SI_PARAM_CONST];
2054 params[SI_PARAM_START_INSTANCE] = i32;
2055 num_params = SI_PARAM_START_INSTANCE+1;
2056 if (shader->key.vs.as_es) {
2057 params[SI_PARAM_ES2GS_OFFSET] = i32;
2058 num_params++;
2059 } else {
2060 /* The locations of the other parameters are assigned dynamically. */
2061
2062 /* Streamout SGPRs. */
2063 if (shader->selector->so.num_outputs) {
2064 params[si_shader_ctx->param_streamout_config = num_params++] = i32;
2065 params[si_shader_ctx->param_streamout_write_index = num_params++] = i32;
2066 }
2067 /* A streamout buffer offset is loaded if the stride is non-zero. */
2068 for (i = 0; i < 4; i++) {
2069 if (!shader->selector->so.stride[i])
2070 continue;
2071
2072 params[si_shader_ctx->param_streamout_offset[i] = num_params++] = i32;
2073 }
2074 }
2075
2076 last_sgpr = num_params-1;
2077
2078 /* VGPRs */
2079 params[si_shader_ctx->param_vertex_id = num_params++] = i32;
2080 params[num_params++] = i32; /* unused*/
2081 params[num_params++] = i32; /* unused */
2082 params[si_shader_ctx->param_instance_id = num_params++] = i32;
2083 break;
2084
2085 case TGSI_PROCESSOR_GEOMETRY:
2086 params[SI_PARAM_GS2VS_OFFSET] = i32;
2087 params[SI_PARAM_GS_WAVE_ID] = i32;
2088 last_sgpr = SI_PARAM_GS_WAVE_ID;
2089
2090 /* VGPRs */
2091 params[SI_PARAM_VTX0_OFFSET] = i32;
2092 params[SI_PARAM_VTX1_OFFSET] = i32;
2093 params[SI_PARAM_PRIMITIVE_ID] = i32;
2094 params[SI_PARAM_VTX2_OFFSET] = i32;
2095 params[SI_PARAM_VTX3_OFFSET] = i32;
2096 params[SI_PARAM_VTX4_OFFSET] = i32;
2097 params[SI_PARAM_VTX5_OFFSET] = i32;
2098 params[SI_PARAM_GS_INSTANCE_ID] = i32;
2099 num_params = SI_PARAM_GS_INSTANCE_ID+1;
2100 break;
2101
2102 case TGSI_PROCESSOR_FRAGMENT:
2103 params[SI_PARAM_ALPHA_REF] = f32;
2104 params[SI_PARAM_PRIM_MASK] = i32;
2105 last_sgpr = SI_PARAM_PRIM_MASK;
2106 params[SI_PARAM_PERSP_SAMPLE] = v2i32;
2107 params[SI_PARAM_PERSP_CENTER] = v2i32;
2108 params[SI_PARAM_PERSP_CENTROID] = v2i32;
2109 params[SI_PARAM_PERSP_PULL_MODEL] = v3i32;
2110 params[SI_PARAM_LINEAR_SAMPLE] = v2i32;
2111 params[SI_PARAM_LINEAR_CENTER] = v2i32;
2112 params[SI_PARAM_LINEAR_CENTROID] = v2i32;
2113 params[SI_PARAM_LINE_STIPPLE_TEX] = f32;
2114 params[SI_PARAM_POS_X_FLOAT] = f32;
2115 params[SI_PARAM_POS_Y_FLOAT] = f32;
2116 params[SI_PARAM_POS_Z_FLOAT] = f32;
2117 params[SI_PARAM_POS_W_FLOAT] = f32;
2118 params[SI_PARAM_FRONT_FACE] = f32;
2119 params[SI_PARAM_ANCILLARY] = f32;
2120 params[SI_PARAM_SAMPLE_COVERAGE] = f32;
2121 params[SI_PARAM_POS_FIXED_PT] = f32;
2122 num_params = SI_PARAM_POS_FIXED_PT+1;
2123 break;
2124
2125 default:
2126 assert(0 && "unimplemented shader");
2127 return;
2128 }
2129
2130 assert(num_params <= Elements(params));
2131 radeon_llvm_create_func(&si_shader_ctx->radeon_bld, params, num_params);
2132 radeon_llvm_shader_type(si_shader_ctx->radeon_bld.main_fn, si_shader_ctx->type);
2133
2134 for (i = 0; i <= last_sgpr; ++i) {
2135 LLVMValueRef P = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, i);
2136 switch (i) {
2137 default:
2138 LLVMAddAttribute(P, LLVMInRegAttribute);
2139 break;
2140 #if HAVE_LLVM >= 0x0304
2141 /* We tell llvm that array inputs are passed by value to allow Sinking pass
2142 * to move load. Inputs are constant so this is fine. */
2143 case SI_PARAM_CONST:
2144 case SI_PARAM_SAMPLER:
2145 case SI_PARAM_RESOURCE:
2146 LLVMAddAttribute(P, LLVMByValAttribute);
2147 break;
2148 #endif
2149 }
2150 }
2151
2152 #if HAVE_LLVM >= 0x0304
2153 if (bld_base->info &&
2154 (bld_base->info->opcode_count[TGSI_OPCODE_DDX] > 0 ||
2155 bld_base->info->opcode_count[TGSI_OPCODE_DDY] > 0))
2156 si_shader_ctx->ddxy_lds =
2157 LLVMAddGlobalInAddressSpace(gallivm->module,
2158 LLVMArrayType(i32, 64),
2159 "ddxy_lds",
2160 LOCAL_ADDR_SPACE);
2161 #endif
2162 }
2163
2164 static void preload_constants(struct si_shader_context *si_shader_ctx)
2165 {
2166 struct lp_build_tgsi_context * bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
2167 struct gallivm_state * gallivm = bld_base->base.gallivm;
2168 const struct tgsi_shader_info * info = bld_base->info;
2169 unsigned buf;
2170 LLVMValueRef ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_CONST);
2171
2172 for (buf = 0; buf < NUM_CONST_BUFFERS; buf++) {
2173 unsigned i, num_const = info->const_file_max[buf] + 1;
2174
2175 if (num_const == 0)
2176 continue;
2177
2178 /* Allocate space for the constant values */
2179 si_shader_ctx->constants[buf] = CALLOC(num_const * 4, sizeof(LLVMValueRef));
2180
2181 /* Load the resource descriptor */
2182 si_shader_ctx->const_resource[buf] =
2183 build_indexed_load(si_shader_ctx, ptr, lp_build_const_int32(gallivm, buf));
2184
2185 /* Load the constants, we rely on the code sinking to do the rest */
2186 for (i = 0; i < num_const * 4; ++i) {
2187 LLVMValueRef args[2] = {
2188 si_shader_ctx->const_resource[buf],
2189 lp_build_const_int32(gallivm, i * 4)
2190 };
2191 si_shader_ctx->constants[buf][i] =
2192 build_intrinsic(gallivm->builder, "llvm.SI.load.const",
2193 bld_base->base.elem_type, args, 2,
2194 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
2195 }
2196 }
2197 }
2198
2199 static void preload_samplers(struct si_shader_context *si_shader_ctx)
2200 {
2201 struct lp_build_tgsi_context * bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
2202 struct gallivm_state * gallivm = bld_base->base.gallivm;
2203 const struct tgsi_shader_info * info = bld_base->info;
2204
2205 unsigned i, num_samplers = info->file_max[TGSI_FILE_SAMPLER] + 1;
2206
2207 LLVMValueRef res_ptr, samp_ptr;
2208 LLVMValueRef offset;
2209
2210 if (num_samplers == 0)
2211 return;
2212
2213 /* Allocate space for the values */
2214 si_shader_ctx->resources = CALLOC(NUM_SAMPLER_VIEWS, sizeof(LLVMValueRef));
2215 si_shader_ctx->samplers = CALLOC(num_samplers, sizeof(LLVMValueRef));
2216
2217 res_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_RESOURCE);
2218 samp_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_SAMPLER);
2219
2220 /* Load the resources and samplers, we rely on the code sinking to do the rest */
2221 for (i = 0; i < num_samplers; ++i) {
2222 /* Resource */
2223 offset = lp_build_const_int32(gallivm, i);
2224 si_shader_ctx->resources[i] = build_indexed_load(si_shader_ctx, res_ptr, offset);
2225
2226 /* Sampler */
2227 offset = lp_build_const_int32(gallivm, i);
2228 si_shader_ctx->samplers[i] = build_indexed_load(si_shader_ctx, samp_ptr, offset);
2229
2230 /* FMASK resource */
2231 if (info->is_msaa_sampler[i]) {
2232 offset = lp_build_const_int32(gallivm, FMASK_TEX_OFFSET + i);
2233 si_shader_ctx->resources[FMASK_TEX_OFFSET + i] =
2234 build_indexed_load(si_shader_ctx, res_ptr, offset);
2235 }
2236 }
2237 }
2238
2239 static void preload_streamout_buffers(struct si_shader_context *si_shader_ctx)
2240 {
2241 struct lp_build_tgsi_context * bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
2242 struct gallivm_state * gallivm = bld_base->base.gallivm;
2243 unsigned i;
2244
2245 if (!si_shader_ctx->shader->selector->so.num_outputs)
2246 return;
2247
2248 LLVMValueRef buf_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
2249 SI_PARAM_SO_BUFFER);
2250
2251 /* Load the resources, we rely on the code sinking to do the rest */
2252 for (i = 0; i < 4; ++i) {
2253 if (si_shader_ctx->shader->selector->so.stride[i]) {
2254 LLVMValueRef offset = lp_build_const_int32(gallivm, i);
2255
2256 si_shader_ctx->so_buffers[i] = build_indexed_load(si_shader_ctx, buf_ptr, offset);
2257 }
2258 }
2259 }
2260
2261 int si_compile_llvm(struct si_context *sctx, struct si_pipe_shader *shader,
2262 LLVMModuleRef mod)
2263 {
2264 unsigned i;
2265 uint32_t *ptr;
2266 struct radeon_llvm_binary binary;
2267 bool dump = r600_can_dump_shader(&sctx->screen->b,
2268 shader->selector ? shader->selector->tokens : NULL);
2269 memset(&binary, 0, sizeof(binary));
2270 radeon_llvm_compile(mod, &binary,
2271 r600_get_llvm_processor_name(sctx->screen->b.family), dump);
2272 if (dump && ! binary.disassembled) {
2273 fprintf(stderr, "SI CODE:\n");
2274 for (i = 0; i < binary.code_size; i+=4 ) {
2275 fprintf(stderr, "%02x%02x%02x%02x\n", binary.code[i + 3],
2276 binary.code[i + 2], binary.code[i + 1],
2277 binary.code[i]);
2278 }
2279 }
2280
2281 /* XXX: We may be able to emit some of these values directly rather than
2282 * extracting fields to be emitted later.
2283 */
2284 for (i = 0; i < binary.config_size; i+= 8) {
2285 unsigned reg = util_le32_to_cpu(*(uint32_t*)(binary.config + i));
2286 unsigned value = util_le32_to_cpu(*(uint32_t*)(binary.config + i + 4));
2287 switch (reg) {
2288 case R_00B028_SPI_SHADER_PGM_RSRC1_PS:
2289 case R_00B128_SPI_SHADER_PGM_RSRC1_VS:
2290 case R_00B228_SPI_SHADER_PGM_RSRC1_GS:
2291 case R_00B848_COMPUTE_PGM_RSRC1:
2292 shader->num_sgprs = (G_00B028_SGPRS(value) + 1) * 8;
2293 shader->num_vgprs = (G_00B028_VGPRS(value) + 1) * 4;
2294 break;
2295 case R_00B02C_SPI_SHADER_PGM_RSRC2_PS:
2296 shader->lds_size = G_00B02C_EXTRA_LDS_SIZE(value);
2297 break;
2298 case R_00B84C_COMPUTE_PGM_RSRC2:
2299 shader->lds_size = G_00B84C_LDS_SIZE(value);
2300 break;
2301 case R_0286CC_SPI_PS_INPUT_ENA:
2302 shader->spi_ps_input_ena = value;
2303 break;
2304 default:
2305 fprintf(stderr, "Warning: Compiler emitted unknown "
2306 "config register: 0x%x\n", reg);
2307 break;
2308 }
2309 }
2310
2311 /* copy new shader */
2312 r600_resource_reference(&shader->bo, NULL);
2313 shader->bo = si_resource_create_custom(sctx->b.b.screen, PIPE_USAGE_IMMUTABLE,
2314 binary.code_size);
2315 if (shader->bo == NULL) {
2316 return -ENOMEM;
2317 }
2318
2319 ptr = (uint32_t*)sctx->b.ws->buffer_map(shader->bo->cs_buf, sctx->b.rings.gfx.cs, PIPE_TRANSFER_WRITE);
2320 if (0 /*SI_BIG_ENDIAN*/) {
2321 for (i = 0; i < binary.code_size / 4; ++i) {
2322 ptr[i] = util_bswap32(*(uint32_t*)(binary.code + i*4));
2323 }
2324 } else {
2325 memcpy(ptr, binary.code, binary.code_size);
2326 }
2327 sctx->b.ws->buffer_unmap(shader->bo->cs_buf);
2328
2329 free(binary.code);
2330 free(binary.config);
2331
2332 return 0;
2333 }
2334
2335 /* Generate code for the hardware VS shader stage to go with a geometry shader */
2336 static int si_generate_gs_copy_shader(struct si_context *sctx,
2337 struct si_shader_context *si_shader_ctx,
2338 bool dump)
2339 {
2340 struct gallivm_state *gallivm = &si_shader_ctx->radeon_bld.gallivm;
2341 struct lp_build_tgsi_context *bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
2342 struct lp_build_context *base = &bld_base->base;
2343 struct lp_build_context *uint = &bld_base->uint_bld;
2344 struct si_shader *shader = &si_shader_ctx->shader->shader;
2345 struct si_shader *gs = &si_shader_ctx->shader->selector->current->shader;
2346 struct si_shader_output_values *outputs;
2347 LLVMValueRef t_list_ptr, t_list;
2348 LLVMValueRef args[9];
2349 int i, r;
2350
2351 outputs = MALLOC(gs->noutput * sizeof(outputs[0]));
2352
2353 si_shader_ctx->type = TGSI_PROCESSOR_VERTEX;
2354 si_shader_ctx->gs_for_vs = gs;
2355
2356 radeon_llvm_context_init(&si_shader_ctx->radeon_bld);
2357
2358 create_meta_data(si_shader_ctx);
2359 create_function(si_shader_ctx);
2360 preload_streamout_buffers(si_shader_ctx);
2361
2362 /* Load the GSVS ring resource descriptor */
2363 t_list_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_CONST);
2364 t_list = build_indexed_load(si_shader_ctx, t_list_ptr,
2365 lp_build_const_int32(gallivm,
2366 NUM_PIPE_CONST_BUFFERS + 1));
2367
2368 args[0] = t_list;
2369 args[1] = lp_build_mul_imm(uint,
2370 LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
2371 si_shader_ctx->param_vertex_id),
2372 4);
2373 args[3] = uint->zero;
2374 args[4] = uint->one; /* OFFEN */
2375 args[5] = uint->zero; /* IDXEN */
2376 args[6] = uint->one; /* GLC */
2377 args[7] = uint->one; /* SLC */
2378 args[8] = uint->zero; /* TFE */
2379
2380 /* Fetch vertex data from GSVS ring */
2381 for (i = 0; i < gs->noutput; ++i) {
2382 struct si_shader_output *out = gs->output + i;
2383 unsigned chan;
2384
2385 shader->output[i] = *out;
2386
2387 outputs[i].name = out->name;
2388 outputs[i].index = out->index;
2389 outputs[i].usage = out->usage;
2390
2391 for (chan = 0; chan < 4; chan++) {
2392 args[2] = lp_build_const_int32(gallivm,
2393 (i * 4 + chan) *
2394 gs->gs_max_out_vertices * 16 * 4);
2395
2396 outputs[i].values[chan] =
2397 LLVMBuildBitCast(gallivm->builder,
2398 build_intrinsic(gallivm->builder,
2399 "llvm.SI.buffer.load.dword.i32.i32",
2400 LLVMInt32TypeInContext(gallivm->context),
2401 args, 9,
2402 LLVMReadOnlyAttribute | LLVMNoUnwindAttribute),
2403 base->elem_type, "");
2404 }
2405 }
2406 shader->noutput = gs->noutput;
2407
2408 si_llvm_export_vs(bld_base, outputs, gs->noutput);
2409
2410 radeon_llvm_finalize_module(&si_shader_ctx->radeon_bld);
2411
2412 if (dump)
2413 fprintf(stderr, "Copy Vertex Shader for Geometry Shader:\n\n");
2414
2415 r = si_compile_llvm(sctx, si_shader_ctx->shader,
2416 bld_base->base.gallivm->module);
2417
2418 radeon_llvm_dispose(&si_shader_ctx->radeon_bld);
2419
2420 FREE(outputs);
2421 return r;
2422 }
2423
2424 int si_pipe_shader_create(
2425 struct pipe_context *ctx,
2426 struct si_pipe_shader *shader)
2427 {
2428 struct si_context *sctx = (struct si_context*)ctx;
2429 struct si_pipe_shader_selector *sel = shader->selector;
2430 struct si_shader_context si_shader_ctx;
2431 struct tgsi_shader_info shader_info;
2432 struct lp_build_tgsi_context * bld_base;
2433 LLVMModuleRef mod;
2434 int r = 0;
2435 bool dump = r600_can_dump_shader(&sctx->screen->b, sel->tokens);
2436
2437 /* Dump TGSI code before doing TGSI->LLVM conversion in case the
2438 * conversion fails. */
2439 if (dump) {
2440 tgsi_dump(sel->tokens, 0);
2441 si_dump_streamout(&sel->so);
2442 }
2443
2444 assert(shader->shader.noutput == 0);
2445 assert(shader->shader.nparam == 0);
2446 assert(shader->shader.ninput == 0);
2447
2448 memset(&si_shader_ctx, 0, sizeof(si_shader_ctx));
2449 radeon_llvm_context_init(&si_shader_ctx.radeon_bld);
2450 bld_base = &si_shader_ctx.radeon_bld.soa.bld_base;
2451
2452 tgsi_scan_shader(sel->tokens, &shader_info);
2453
2454 shader->shader.uses_kill = shader_info.uses_kill;
2455 shader->shader.uses_instanceid = shader_info.uses_instanceid;
2456 bld_base->info = &shader_info;
2457 bld_base->emit_fetch_funcs[TGSI_FILE_CONSTANT] = fetch_constant;
2458
2459 bld_base->op_actions[TGSI_OPCODE_TEX] = tex_action;
2460 bld_base->op_actions[TGSI_OPCODE_TXB] = txb_action;
2461 #if HAVE_LLVM >= 0x0304
2462 bld_base->op_actions[TGSI_OPCODE_TXD] = txd_action;
2463 #endif
2464 bld_base->op_actions[TGSI_OPCODE_TXF] = txf_action;
2465 bld_base->op_actions[TGSI_OPCODE_TXL] = txl_action;
2466 bld_base->op_actions[TGSI_OPCODE_TXP] = tex_action;
2467 bld_base->op_actions[TGSI_OPCODE_TXQ] = txq_action;
2468
2469 #if HAVE_LLVM >= 0x0304
2470 bld_base->op_actions[TGSI_OPCODE_DDX].emit = si_llvm_emit_ddxy;
2471 bld_base->op_actions[TGSI_OPCODE_DDY].emit = si_llvm_emit_ddxy;
2472 #endif
2473
2474 bld_base->op_actions[TGSI_OPCODE_EMIT].emit = si_llvm_emit_vertex;
2475 bld_base->op_actions[TGSI_OPCODE_ENDPRIM].emit = si_llvm_emit_primitive;
2476
2477 si_shader_ctx.radeon_bld.load_system_value = declare_system_value;
2478 si_shader_ctx.tokens = sel->tokens;
2479 tgsi_parse_init(&si_shader_ctx.parse, si_shader_ctx.tokens);
2480 si_shader_ctx.shader = shader;
2481 si_shader_ctx.type = si_shader_ctx.parse.FullHeader.Processor.Processor;
2482
2483 switch (si_shader_ctx.type) {
2484 case TGSI_PROCESSOR_VERTEX:
2485 si_shader_ctx.radeon_bld.load_input = declare_input_vs;
2486 if (shader->key.vs.as_es) {
2487 si_shader_ctx.gs_for_vs = &sctx->gs_shader->current->shader;
2488 bld_base->emit_epilogue = si_llvm_emit_es_epilogue;
2489 } else {
2490 bld_base->emit_epilogue = si_llvm_emit_vs_epilogue;
2491 }
2492 break;
2493 case TGSI_PROCESSOR_GEOMETRY: {
2494 int i;
2495
2496 si_shader_ctx.radeon_bld.load_input = declare_input_gs;
2497 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_gs;
2498 bld_base->emit_epilogue = si_llvm_emit_gs_epilogue;
2499
2500 for (i = 0; i < shader_info.num_properties; i++) {
2501 switch (shader_info.properties[i].name) {
2502 case TGSI_PROPERTY_GS_INPUT_PRIM:
2503 shader->shader.gs_input_prim = shader_info.properties[i].data[0];
2504 break;
2505 case TGSI_PROPERTY_GS_OUTPUT_PRIM:
2506 shader->shader.gs_output_prim = shader_info.properties[i].data[0];
2507 break;
2508 case TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES:
2509 shader->shader.gs_max_out_vertices = shader_info.properties[i].data[0];
2510 break;
2511 }
2512 }
2513 break;
2514 }
2515 case TGSI_PROCESSOR_FRAGMENT:
2516 si_shader_ctx.radeon_bld.load_input = declare_input_fs;
2517 bld_base->emit_epilogue = si_llvm_emit_fs_epilogue;
2518 break;
2519 default:
2520 assert(!"Unsupported shader type");
2521 return -1;
2522 }
2523
2524 create_meta_data(&si_shader_ctx);
2525 create_function(&si_shader_ctx);
2526 preload_constants(&si_shader_ctx);
2527 preload_samplers(&si_shader_ctx);
2528 preload_streamout_buffers(&si_shader_ctx);
2529
2530 if (si_shader_ctx.type == TGSI_PROCESSOR_GEOMETRY) {
2531 si_shader_ctx.gs_next_vertex =
2532 lp_build_alloca(bld_base->base.gallivm,
2533 bld_base->uint_bld.elem_type, "");
2534 }
2535
2536 if (!lp_build_tgsi_llvm(bld_base, sel->tokens)) {
2537 fprintf(stderr, "Failed to translate shader from TGSI to LLVM\n");
2538 goto out;
2539 }
2540
2541 radeon_llvm_finalize_module(&si_shader_ctx.radeon_bld);
2542
2543 mod = bld_base->base.gallivm->module;
2544 r = si_compile_llvm(sctx, shader, mod);
2545 if (r) {
2546 fprintf(stderr, "LLVM failed to compile shader\n");
2547 goto out;
2548 }
2549
2550 radeon_llvm_dispose(&si_shader_ctx.radeon_bld);
2551
2552 if (si_shader_ctx.type == TGSI_PROCESSOR_GEOMETRY) {
2553 shader->gs_copy_shader = CALLOC_STRUCT(si_pipe_shader);
2554 shader->gs_copy_shader->selector = shader->selector;
2555 shader->gs_copy_shader->key = shader->key;
2556 si_shader_ctx.shader = shader->gs_copy_shader;
2557 if ((r = si_generate_gs_copy_shader(sctx, &si_shader_ctx, dump))) {
2558 free(shader->gs_copy_shader);
2559 shader->gs_copy_shader = NULL;
2560 goto out;
2561 }
2562 }
2563
2564 tgsi_parse_free(&si_shader_ctx.parse);
2565
2566 out:
2567 for (int i = 0; i < NUM_CONST_BUFFERS; i++)
2568 FREE(si_shader_ctx.constants[i]);
2569 FREE(si_shader_ctx.resources);
2570 FREE(si_shader_ctx.samplers);
2571
2572 return r;
2573 }
2574
2575 void si_pipe_shader_destroy(struct pipe_context *ctx, struct si_pipe_shader *shader)
2576 {
2577 r600_resource_reference(&shader->bo, NULL);
2578 }