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radeonsi: consolidate max-work-group-size computation
[mesa.git] / src / gallium / drivers / radeonsi / si_shader.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Tom Stellard <thomas.stellard@amd.com>
25 * Michel Dänzer <michel.daenzer@amd.com>
26 * Christian König <christian.koenig@amd.com>
27 */
28
29 #include "gallivm/lp_bld_const.h"
30 #include "gallivm/lp_bld_gather.h"
31 #include "gallivm/lp_bld_intr.h"
32 #include "gallivm/lp_bld_logic.h"
33 #include "gallivm/lp_bld_arit.h"
34 #include "gallivm/lp_bld_flow.h"
35 #include "gallivm/lp_bld_misc.h"
36 #include "radeon/radeon_elf_util.h"
37 #include "util/u_memory.h"
38 #include "util/u_string.h"
39 #include "tgsi/tgsi_build.h"
40 #include "tgsi/tgsi_util.h"
41 #include "tgsi/tgsi_dump.h"
42
43 #include "ac_llvm_util.h"
44 #include "si_shader_internal.h"
45 #include "si_pipe.h"
46 #include "sid.h"
47
48
49 static const char *scratch_rsrc_dword0_symbol =
50 "SCRATCH_RSRC_DWORD0";
51
52 static const char *scratch_rsrc_dword1_symbol =
53 "SCRATCH_RSRC_DWORD1";
54
55 struct si_shader_output_values
56 {
57 LLVMValueRef values[4];
58 unsigned name;
59 unsigned sid;
60 };
61
62 static void si_init_shader_ctx(struct si_shader_context *ctx,
63 struct si_screen *sscreen,
64 struct si_shader *shader,
65 LLVMTargetMachineRef tm);
66
67 static void si_llvm_emit_barrier(const struct lp_build_tgsi_action *action,
68 struct lp_build_tgsi_context *bld_base,
69 struct lp_build_emit_data *emit_data);
70
71 static void si_dump_shader_key(unsigned shader, struct si_shader_key *key,
72 FILE *f);
73
74 static void si_build_vs_prolog_function(struct si_shader_context *ctx,
75 union si_shader_part_key *key);
76 static void si_build_vs_epilog_function(struct si_shader_context *ctx,
77 union si_shader_part_key *key);
78 static void si_build_tcs_epilog_function(struct si_shader_context *ctx,
79 union si_shader_part_key *key);
80 static void si_build_ps_prolog_function(struct si_shader_context *ctx,
81 union si_shader_part_key *key);
82 static void si_build_ps_epilog_function(struct si_shader_context *ctx,
83 union si_shader_part_key *key);
84
85 /* Ideally pass the sample mask input to the PS epilog as v13, which
86 * is its usual location, so that the shader doesn't have to add v_mov.
87 */
88 #define PS_EPILOG_SAMPLEMASK_MIN_LOC 13
89
90 /* The VS location of the PrimitiveID input is the same in the epilog,
91 * so that the main shader part doesn't have to move it.
92 */
93 #define VS_EPILOG_PRIMID_LOC 2
94
95 enum {
96 CONST_ADDR_SPACE = 2,
97 LOCAL_ADDR_SPACE = 3,
98 };
99
100 #define SENDMSG_GS 2
101 #define SENDMSG_GS_DONE 3
102
103 #define SENDMSG_GS_OP_NOP (0 << 4)
104 #define SENDMSG_GS_OP_CUT (1 << 4)
105 #define SENDMSG_GS_OP_EMIT (2 << 4)
106 #define SENDMSG_GS_OP_EMIT_CUT (3 << 4)
107
108 /**
109 * Returns a unique index for a semantic name and index. The index must be
110 * less than 64, so that a 64-bit bitmask of used inputs or outputs can be
111 * calculated.
112 */
113 unsigned si_shader_io_get_unique_index(unsigned semantic_name, unsigned index)
114 {
115 switch (semantic_name) {
116 case TGSI_SEMANTIC_POSITION:
117 return 0;
118 case TGSI_SEMANTIC_PSIZE:
119 return 1;
120 case TGSI_SEMANTIC_CLIPDIST:
121 assert(index <= 1);
122 return 2 + index;
123 case TGSI_SEMANTIC_GENERIC:
124 if (index <= 63-4)
125 return 4 + index;
126
127 assert(!"invalid generic index");
128 return 0;
129
130 /* patch indices are completely separate and thus start from 0 */
131 case TGSI_SEMANTIC_TESSOUTER:
132 return 0;
133 case TGSI_SEMANTIC_TESSINNER:
134 return 1;
135 case TGSI_SEMANTIC_PATCH:
136 return 2 + index;
137
138 default:
139 assert(!"invalid semantic name");
140 return 0;
141 }
142 }
143
144 unsigned si_shader_io_get_unique_index2(unsigned name, unsigned index)
145 {
146 switch (name) {
147 case TGSI_SEMANTIC_FOG:
148 return 0;
149 case TGSI_SEMANTIC_LAYER:
150 return 1;
151 case TGSI_SEMANTIC_VIEWPORT_INDEX:
152 return 2;
153 case TGSI_SEMANTIC_PRIMID:
154 return 3;
155 case TGSI_SEMANTIC_COLOR: /* these alias */
156 case TGSI_SEMANTIC_BCOLOR:
157 return 4 + index;
158 case TGSI_SEMANTIC_TEXCOORD:
159 return 6 + index;
160 default:
161 assert(!"invalid semantic name");
162 return 0;
163 }
164 }
165
166 /**
167 * Get the value of a shader input parameter and extract a bitfield.
168 */
169 static LLVMValueRef unpack_param(struct si_shader_context *ctx,
170 unsigned param, unsigned rshift,
171 unsigned bitwidth)
172 {
173 struct gallivm_state *gallivm = &ctx->gallivm;
174 LLVMValueRef value = LLVMGetParam(ctx->main_fn,
175 param);
176
177 if (LLVMGetTypeKind(LLVMTypeOf(value)) == LLVMFloatTypeKind)
178 value = bitcast(&ctx->soa.bld_base,
179 TGSI_TYPE_UNSIGNED, value);
180
181 if (rshift)
182 value = LLVMBuildLShr(gallivm->builder, value,
183 lp_build_const_int32(gallivm, rshift), "");
184
185 if (rshift + bitwidth < 32) {
186 unsigned mask = (1 << bitwidth) - 1;
187 value = LLVMBuildAnd(gallivm->builder, value,
188 lp_build_const_int32(gallivm, mask), "");
189 }
190
191 return value;
192 }
193
194 static LLVMValueRef get_rel_patch_id(struct si_shader_context *ctx)
195 {
196 switch (ctx->type) {
197 case PIPE_SHADER_TESS_CTRL:
198 return unpack_param(ctx, SI_PARAM_REL_IDS, 0, 8);
199
200 case PIPE_SHADER_TESS_EVAL:
201 return LLVMGetParam(ctx->main_fn,
202 ctx->param_tes_rel_patch_id);
203
204 default:
205 assert(0);
206 return NULL;
207 }
208 }
209
210 /* Tessellation shaders pass outputs to the next shader using LDS.
211 *
212 * LS outputs = TCS inputs
213 * TCS outputs = TES inputs
214 *
215 * The LDS layout is:
216 * - TCS inputs for patch 0
217 * - TCS inputs for patch 1
218 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
219 * - ...
220 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
221 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
222 * - TCS outputs for patch 1
223 * - Per-patch TCS outputs for patch 1
224 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
225 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
226 * - ...
227 *
228 * All three shaders VS(LS), TCS, TES share the same LDS space.
229 */
230
231 static LLVMValueRef
232 get_tcs_in_patch_stride(struct si_shader_context *ctx)
233 {
234 if (ctx->type == PIPE_SHADER_VERTEX)
235 return unpack_param(ctx, SI_PARAM_LS_OUT_LAYOUT, 0, 13);
236 else if (ctx->type == PIPE_SHADER_TESS_CTRL)
237 return unpack_param(ctx, SI_PARAM_TCS_IN_LAYOUT, 0, 13);
238 else {
239 assert(0);
240 return NULL;
241 }
242 }
243
244 static LLVMValueRef
245 get_tcs_out_patch_stride(struct si_shader_context *ctx)
246 {
247 return unpack_param(ctx, SI_PARAM_TCS_OUT_LAYOUT, 0, 13);
248 }
249
250 static LLVMValueRef
251 get_tcs_out_patch0_offset(struct si_shader_context *ctx)
252 {
253 return lp_build_mul_imm(&ctx->soa.bld_base.uint_bld,
254 unpack_param(ctx,
255 SI_PARAM_TCS_OUT_OFFSETS,
256 0, 16),
257 4);
258 }
259
260 static LLVMValueRef
261 get_tcs_out_patch0_patch_data_offset(struct si_shader_context *ctx)
262 {
263 return lp_build_mul_imm(&ctx->soa.bld_base.uint_bld,
264 unpack_param(ctx,
265 SI_PARAM_TCS_OUT_OFFSETS,
266 16, 16),
267 4);
268 }
269
270 static LLVMValueRef
271 get_tcs_in_current_patch_offset(struct si_shader_context *ctx)
272 {
273 struct gallivm_state *gallivm = &ctx->gallivm;
274 LLVMValueRef patch_stride = get_tcs_in_patch_stride(ctx);
275 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
276
277 return LLVMBuildMul(gallivm->builder, patch_stride, rel_patch_id, "");
278 }
279
280 static LLVMValueRef
281 get_tcs_out_current_patch_offset(struct si_shader_context *ctx)
282 {
283 struct gallivm_state *gallivm = &ctx->gallivm;
284 LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(ctx);
285 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
286 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
287
288 return LLVMBuildAdd(gallivm->builder, patch0_offset,
289 LLVMBuildMul(gallivm->builder, patch_stride,
290 rel_patch_id, ""),
291 "");
292 }
293
294 static LLVMValueRef
295 get_tcs_out_current_patch_data_offset(struct si_shader_context *ctx)
296 {
297 struct gallivm_state *gallivm = &ctx->gallivm;
298 LLVMValueRef patch0_patch_data_offset =
299 get_tcs_out_patch0_patch_data_offset(ctx);
300 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
301 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
302
303 return LLVMBuildAdd(gallivm->builder, patch0_patch_data_offset,
304 LLVMBuildMul(gallivm->builder, patch_stride,
305 rel_patch_id, ""),
306 "");
307 }
308
309 static LLVMValueRef build_gep0(struct si_shader_context *ctx,
310 LLVMValueRef base_ptr, LLVMValueRef index)
311 {
312 LLVMValueRef indices[2] = {
313 LLVMConstInt(ctx->i32, 0, 0),
314 index,
315 };
316 return LLVMBuildGEP(ctx->gallivm.builder, base_ptr,
317 indices, 2, "");
318 }
319
320 static void build_indexed_store(struct si_shader_context *ctx,
321 LLVMValueRef base_ptr, LLVMValueRef index,
322 LLVMValueRef value)
323 {
324 struct lp_build_tgsi_context *bld_base = &ctx->soa.bld_base;
325 struct gallivm_state *gallivm = bld_base->base.gallivm;
326
327 LLVMBuildStore(gallivm->builder, value,
328 build_gep0(ctx, base_ptr, index));
329 }
330
331 /**
332 * Build an LLVM bytecode indexed load using LLVMBuildGEP + LLVMBuildLoad.
333 * It's equivalent to doing a load from &base_ptr[index].
334 *
335 * \param base_ptr Where the array starts.
336 * \param index The element index into the array.
337 * \param uniform Whether the base_ptr and index can be assumed to be
338 * dynamically uniform
339 */
340 static LLVMValueRef build_indexed_load(struct si_shader_context *ctx,
341 LLVMValueRef base_ptr, LLVMValueRef index,
342 bool uniform)
343 {
344 struct lp_build_tgsi_context *bld_base = &ctx->soa.bld_base;
345 struct gallivm_state *gallivm = bld_base->base.gallivm;
346 LLVMValueRef pointer;
347
348 pointer = build_gep0(ctx, base_ptr, index);
349 if (uniform)
350 LLVMSetMetadata(pointer, ctx->uniform_md_kind, ctx->empty_md);
351 return LLVMBuildLoad(gallivm->builder, pointer, "");
352 }
353
354 /**
355 * Do a load from &base_ptr[index], but also add a flag that it's loading
356 * a constant from a dynamically uniform index.
357 */
358 static LLVMValueRef build_indexed_load_const(
359 struct si_shader_context *ctx,
360 LLVMValueRef base_ptr, LLVMValueRef index)
361 {
362 LLVMValueRef result = build_indexed_load(ctx, base_ptr, index, true);
363 LLVMSetMetadata(result, ctx->invariant_load_md_kind, ctx->empty_md);
364 return result;
365 }
366
367 static LLVMValueRef get_instance_index_for_fetch(
368 struct si_shader_context *radeon_bld,
369 unsigned param_start_instance, unsigned divisor)
370 {
371 struct si_shader_context *ctx =
372 si_shader_context(&radeon_bld->soa.bld_base);
373 struct gallivm_state *gallivm = radeon_bld->soa.bld_base.base.gallivm;
374
375 LLVMValueRef result = LLVMGetParam(radeon_bld->main_fn,
376 ctx->param_instance_id);
377
378 /* The division must be done before START_INSTANCE is added. */
379 if (divisor > 1)
380 result = LLVMBuildUDiv(gallivm->builder, result,
381 lp_build_const_int32(gallivm, divisor), "");
382
383 return LLVMBuildAdd(gallivm->builder, result,
384 LLVMGetParam(radeon_bld->main_fn, param_start_instance), "");
385 }
386
387 static void declare_input_vs(
388 struct si_shader_context *ctx,
389 unsigned input_index,
390 const struct tgsi_full_declaration *decl,
391 LLVMValueRef out[4])
392 {
393 struct lp_build_context *base = &ctx->soa.bld_base.base;
394 struct gallivm_state *gallivm = base->gallivm;
395
396 unsigned chan;
397 unsigned fix_fetch;
398
399 LLVMValueRef t_list_ptr;
400 LLVMValueRef t_offset;
401 LLVMValueRef t_list;
402 LLVMValueRef attribute_offset;
403 LLVMValueRef buffer_index;
404 LLVMValueRef args[3];
405 LLVMValueRef input;
406
407 /* Load the T list */
408 t_list_ptr = LLVMGetParam(ctx->main_fn, SI_PARAM_VERTEX_BUFFERS);
409
410 t_offset = lp_build_const_int32(gallivm, input_index);
411
412 t_list = build_indexed_load_const(ctx, t_list_ptr, t_offset);
413
414 /* Build the attribute offset */
415 attribute_offset = lp_build_const_int32(gallivm, 0);
416
417 buffer_index = LLVMGetParam(ctx->main_fn,
418 ctx->param_vertex_index0 +
419 input_index);
420
421 args[0] = t_list;
422 args[1] = attribute_offset;
423 args[2] = buffer_index;
424 input = lp_build_intrinsic(gallivm->builder,
425 "llvm.SI.vs.load.input", ctx->v4f32, args, 3,
426 LP_FUNC_ATTR_READNONE);
427
428 /* Break up the vec4 into individual components */
429 for (chan = 0; chan < 4; chan++) {
430 LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan);
431 out[chan] = LLVMBuildExtractElement(gallivm->builder,
432 input, llvm_chan, "");
433 }
434
435 fix_fetch = (ctx->shader->key.mono.vs.fix_fetch >> (2 * input_index)) & 3;
436 if (fix_fetch) {
437 /* The hardware returns an unsigned value; convert it to a
438 * signed one.
439 */
440 LLVMValueRef tmp = out[3];
441 LLVMValueRef c30 = LLVMConstInt(ctx->i32, 30, 0);
442
443 /* First, recover the sign-extended signed integer value. */
444 if (fix_fetch == SI_FIX_FETCH_A2_SSCALED)
445 tmp = LLVMBuildFPToUI(gallivm->builder, tmp, ctx->i32, "");
446 else
447 tmp = LLVMBuildBitCast(gallivm->builder, tmp, ctx->i32, "");
448
449 /* For the integer-like cases, do a natural sign extension.
450 *
451 * For the SNORM case, the values are 0.0, 0.333, 0.666, 1.0
452 * and happen to contain 0, 1, 2, 3 as the two LSBs of the
453 * exponent.
454 */
455 tmp = LLVMBuildShl(gallivm->builder, tmp,
456 fix_fetch == SI_FIX_FETCH_A2_SNORM ?
457 LLVMConstInt(ctx->i32, 7, 0) : c30, "");
458 tmp = LLVMBuildAShr(gallivm->builder, tmp, c30, "");
459
460 /* Convert back to the right type. */
461 if (fix_fetch == SI_FIX_FETCH_A2_SNORM) {
462 LLVMValueRef clamp;
463 LLVMValueRef neg_one = LLVMConstReal(ctx->f32, -1.0);
464 tmp = LLVMBuildSIToFP(gallivm->builder, tmp, ctx->f32, "");
465 clamp = LLVMBuildFCmp(gallivm->builder, LLVMRealULT, tmp, neg_one, "");
466 tmp = LLVMBuildSelect(gallivm->builder, clamp, neg_one, tmp, "");
467 } else if (fix_fetch == SI_FIX_FETCH_A2_SSCALED) {
468 tmp = LLVMBuildSIToFP(gallivm->builder, tmp, ctx->f32, "");
469 }
470
471 out[3] = tmp;
472 }
473 }
474
475 static LLVMValueRef get_primitive_id(struct lp_build_tgsi_context *bld_base,
476 unsigned swizzle)
477 {
478 struct si_shader_context *ctx = si_shader_context(bld_base);
479
480 if (swizzle > 0)
481 return bld_base->uint_bld.zero;
482
483 switch (ctx->type) {
484 case PIPE_SHADER_VERTEX:
485 return LLVMGetParam(ctx->main_fn,
486 ctx->param_vs_prim_id);
487 case PIPE_SHADER_TESS_CTRL:
488 return LLVMGetParam(ctx->main_fn,
489 SI_PARAM_PATCH_ID);
490 case PIPE_SHADER_TESS_EVAL:
491 return LLVMGetParam(ctx->main_fn,
492 ctx->param_tes_patch_id);
493 case PIPE_SHADER_GEOMETRY:
494 return LLVMGetParam(ctx->main_fn,
495 SI_PARAM_PRIMITIVE_ID);
496 default:
497 assert(0);
498 return bld_base->uint_bld.zero;
499 }
500 }
501
502 /**
503 * Return the value of tgsi_ind_register for indexing.
504 * This is the indirect index with the constant offset added to it.
505 */
506 static LLVMValueRef get_indirect_index(struct si_shader_context *ctx,
507 const struct tgsi_ind_register *ind,
508 int rel_index)
509 {
510 struct gallivm_state *gallivm = ctx->soa.bld_base.base.gallivm;
511 LLVMValueRef result;
512
513 result = ctx->soa.addr[ind->Index][ind->Swizzle];
514 result = LLVMBuildLoad(gallivm->builder, result, "");
515 result = LLVMBuildAdd(gallivm->builder, result,
516 lp_build_const_int32(gallivm, rel_index), "");
517 return result;
518 }
519
520 /**
521 * Like get_indirect_index, but restricts the return value to a (possibly
522 * undefined) value inside [0..num).
523 */
524 static LLVMValueRef get_bounded_indirect_index(struct si_shader_context *ctx,
525 const struct tgsi_ind_register *ind,
526 int rel_index, unsigned num)
527 {
528 LLVMValueRef result = get_indirect_index(ctx, ind, rel_index);
529
530 /* LLVM 3.8: If indirect resource indexing is used:
531 * - SI & CIK hang
532 * - VI crashes
533 */
534 if (HAVE_LLVM <= 0x0308)
535 return LLVMGetUndef(ctx->i32);
536
537 return si_llvm_bound_index(ctx, result, num);
538 }
539
540
541 /**
542 * Calculate a dword address given an input or output register and a stride.
543 */
544 static LLVMValueRef get_dw_address(struct si_shader_context *ctx,
545 const struct tgsi_full_dst_register *dst,
546 const struct tgsi_full_src_register *src,
547 LLVMValueRef vertex_dw_stride,
548 LLVMValueRef base_addr)
549 {
550 struct gallivm_state *gallivm = ctx->soa.bld_base.base.gallivm;
551 struct tgsi_shader_info *info = &ctx->shader->selector->info;
552 ubyte *name, *index, *array_first;
553 int first, param;
554 struct tgsi_full_dst_register reg;
555
556 /* Set the register description. The address computation is the same
557 * for sources and destinations. */
558 if (src) {
559 reg.Register.File = src->Register.File;
560 reg.Register.Index = src->Register.Index;
561 reg.Register.Indirect = src->Register.Indirect;
562 reg.Register.Dimension = src->Register.Dimension;
563 reg.Indirect = src->Indirect;
564 reg.Dimension = src->Dimension;
565 reg.DimIndirect = src->DimIndirect;
566 } else
567 reg = *dst;
568
569 /* If the register is 2-dimensional (e.g. an array of vertices
570 * in a primitive), calculate the base address of the vertex. */
571 if (reg.Register.Dimension) {
572 LLVMValueRef index;
573
574 if (reg.Dimension.Indirect)
575 index = get_indirect_index(ctx, &reg.DimIndirect,
576 reg.Dimension.Index);
577 else
578 index = lp_build_const_int32(gallivm, reg.Dimension.Index);
579
580 base_addr = LLVMBuildAdd(gallivm->builder, base_addr,
581 LLVMBuildMul(gallivm->builder, index,
582 vertex_dw_stride, ""), "");
583 }
584
585 /* Get information about the register. */
586 if (reg.Register.File == TGSI_FILE_INPUT) {
587 name = info->input_semantic_name;
588 index = info->input_semantic_index;
589 array_first = info->input_array_first;
590 } else if (reg.Register.File == TGSI_FILE_OUTPUT) {
591 name = info->output_semantic_name;
592 index = info->output_semantic_index;
593 array_first = info->output_array_first;
594 } else {
595 assert(0);
596 return NULL;
597 }
598
599 if (reg.Register.Indirect) {
600 /* Add the relative address of the element. */
601 LLVMValueRef ind_index;
602
603 if (reg.Indirect.ArrayID)
604 first = array_first[reg.Indirect.ArrayID];
605 else
606 first = reg.Register.Index;
607
608 ind_index = get_indirect_index(ctx, &reg.Indirect,
609 reg.Register.Index - first);
610
611 base_addr = LLVMBuildAdd(gallivm->builder, base_addr,
612 LLVMBuildMul(gallivm->builder, ind_index,
613 lp_build_const_int32(gallivm, 4), ""), "");
614
615 param = si_shader_io_get_unique_index(name[first], index[first]);
616 } else {
617 param = si_shader_io_get_unique_index(name[reg.Register.Index],
618 index[reg.Register.Index]);
619 }
620
621 /* Add the base address of the element. */
622 return LLVMBuildAdd(gallivm->builder, base_addr,
623 lp_build_const_int32(gallivm, param * 4), "");
624 }
625
626 /* The offchip buffer layout for TCS->TES is
627 *
628 * - attribute 0 of patch 0 vertex 0
629 * - attribute 0 of patch 0 vertex 1
630 * - attribute 0 of patch 0 vertex 2
631 * ...
632 * - attribute 0 of patch 1 vertex 0
633 * - attribute 0 of patch 1 vertex 1
634 * ...
635 * - attribute 1 of patch 0 vertex 0
636 * - attribute 1 of patch 0 vertex 1
637 * ...
638 * - per patch attribute 0 of patch 0
639 * - per patch attribute 0 of patch 1
640 * ...
641 *
642 * Note that every attribute has 4 components.
643 */
644 static LLVMValueRef get_tcs_tes_buffer_address(struct si_shader_context *ctx,
645 LLVMValueRef vertex_index,
646 LLVMValueRef param_index)
647 {
648 struct gallivm_state *gallivm = ctx->soa.bld_base.base.gallivm;
649 LLVMValueRef base_addr, vertices_per_patch, num_patches, total_vertices;
650 LLVMValueRef param_stride, constant16;
651
652 vertices_per_patch = unpack_param(ctx, SI_PARAM_TCS_OFFCHIP_LAYOUT, 9, 6);
653 num_patches = unpack_param(ctx, SI_PARAM_TCS_OFFCHIP_LAYOUT, 0, 9);
654 total_vertices = LLVMBuildMul(gallivm->builder, vertices_per_patch,
655 num_patches, "");
656
657 constant16 = lp_build_const_int32(gallivm, 16);
658 if (vertex_index) {
659 base_addr = LLVMBuildMul(gallivm->builder, get_rel_patch_id(ctx),
660 vertices_per_patch, "");
661
662 base_addr = LLVMBuildAdd(gallivm->builder, base_addr,
663 vertex_index, "");
664
665 param_stride = total_vertices;
666 } else {
667 base_addr = get_rel_patch_id(ctx);
668 param_stride = num_patches;
669 }
670
671 base_addr = LLVMBuildAdd(gallivm->builder, base_addr,
672 LLVMBuildMul(gallivm->builder, param_index,
673 param_stride, ""), "");
674
675 base_addr = LLVMBuildMul(gallivm->builder, base_addr, constant16, "");
676
677 if (!vertex_index) {
678 LLVMValueRef patch_data_offset =
679 unpack_param(ctx, SI_PARAM_TCS_OFFCHIP_LAYOUT, 16, 16);
680
681 base_addr = LLVMBuildAdd(gallivm->builder, base_addr,
682 patch_data_offset, "");
683 }
684 return base_addr;
685 }
686
687 static LLVMValueRef get_tcs_tes_buffer_address_from_reg(
688 struct si_shader_context *ctx,
689 const struct tgsi_full_dst_register *dst,
690 const struct tgsi_full_src_register *src)
691 {
692 struct gallivm_state *gallivm = ctx->soa.bld_base.base.gallivm;
693 struct tgsi_shader_info *info = &ctx->shader->selector->info;
694 ubyte *name, *index, *array_first;
695 struct tgsi_full_src_register reg;
696 LLVMValueRef vertex_index = NULL;
697 LLVMValueRef param_index = NULL;
698 unsigned param_index_base, param_base;
699
700 reg = src ? *src : tgsi_full_src_register_from_dst(dst);
701
702 if (reg.Register.Dimension) {
703
704 if (reg.Dimension.Indirect)
705 vertex_index = get_indirect_index(ctx, &reg.DimIndirect,
706 reg.Dimension.Index);
707 else
708 vertex_index = lp_build_const_int32(gallivm,
709 reg.Dimension.Index);
710 }
711
712 /* Get information about the register. */
713 if (reg.Register.File == TGSI_FILE_INPUT) {
714 name = info->input_semantic_name;
715 index = info->input_semantic_index;
716 array_first = info->input_array_first;
717 } else if (reg.Register.File == TGSI_FILE_OUTPUT) {
718 name = info->output_semantic_name;
719 index = info->output_semantic_index;
720 array_first = info->output_array_first;
721 } else {
722 assert(0);
723 return NULL;
724 }
725
726 if (reg.Register.Indirect) {
727 if (reg.Indirect.ArrayID)
728 param_base = array_first[reg.Indirect.ArrayID];
729 else
730 param_base = reg.Register.Index;
731
732 param_index = get_indirect_index(ctx, &reg.Indirect,
733 reg.Register.Index - param_base);
734
735 } else {
736 param_base = reg.Register.Index;
737 param_index = lp_build_const_int32(gallivm, 0);
738 }
739
740 param_index_base = si_shader_io_get_unique_index(name[param_base],
741 index[param_base]);
742
743 param_index = LLVMBuildAdd(gallivm->builder, param_index,
744 lp_build_const_int32(gallivm, param_index_base),
745 "");
746
747 return get_tcs_tes_buffer_address(ctx, vertex_index, param_index);
748 }
749
750 /* TBUFFER_STORE_FORMAT_{X,XY,XYZ,XYZW} <- the suffix is selected by num_channels=1..4.
751 * The type of vdata must be one of i32 (num_channels=1), v2i32 (num_channels=2),
752 * or v4i32 (num_channels=3,4). */
753 static void build_tbuffer_store(struct si_shader_context *ctx,
754 LLVMValueRef rsrc,
755 LLVMValueRef vdata,
756 unsigned num_channels,
757 LLVMValueRef vaddr,
758 LLVMValueRef soffset,
759 unsigned inst_offset,
760 unsigned dfmt,
761 unsigned nfmt,
762 unsigned offen,
763 unsigned idxen,
764 unsigned glc,
765 unsigned slc,
766 unsigned tfe)
767 {
768 struct gallivm_state *gallivm = &ctx->gallivm;
769 LLVMValueRef args[] = {
770 rsrc,
771 vdata,
772 LLVMConstInt(ctx->i32, num_channels, 0),
773 vaddr,
774 soffset,
775 LLVMConstInt(ctx->i32, inst_offset, 0),
776 LLVMConstInt(ctx->i32, dfmt, 0),
777 LLVMConstInt(ctx->i32, nfmt, 0),
778 LLVMConstInt(ctx->i32, offen, 0),
779 LLVMConstInt(ctx->i32, idxen, 0),
780 LLVMConstInt(ctx->i32, glc, 0),
781 LLVMConstInt(ctx->i32, slc, 0),
782 LLVMConstInt(ctx->i32, tfe, 0)
783 };
784
785 /* The instruction offset field has 12 bits */
786 assert(offen || inst_offset < (1 << 12));
787
788 /* The intrinsic is overloaded, we need to add a type suffix for overloading to work. */
789 unsigned func = CLAMP(num_channels, 1, 3) - 1;
790 const char *types[] = {"i32", "v2i32", "v4i32"};
791 char name[256];
792 snprintf(name, sizeof(name), "llvm.SI.tbuffer.store.%s", types[func]);
793
794 lp_build_intrinsic(gallivm->builder, name, ctx->voidt,
795 args, ARRAY_SIZE(args), 0);
796 }
797
798 static void build_tbuffer_store_dwords(struct si_shader_context *ctx,
799 LLVMValueRef rsrc,
800 LLVMValueRef vdata,
801 unsigned num_channels,
802 LLVMValueRef vaddr,
803 LLVMValueRef soffset,
804 unsigned inst_offset)
805 {
806 static unsigned dfmt[] = {
807 V_008F0C_BUF_DATA_FORMAT_32,
808 V_008F0C_BUF_DATA_FORMAT_32_32,
809 V_008F0C_BUF_DATA_FORMAT_32_32_32,
810 V_008F0C_BUF_DATA_FORMAT_32_32_32_32
811 };
812 assert(num_channels >= 1 && num_channels <= 4);
813
814 build_tbuffer_store(ctx, rsrc, vdata, num_channels, vaddr, soffset,
815 inst_offset, dfmt[num_channels-1],
816 V_008F0C_BUF_NUM_FORMAT_UINT, 1, 0, 1, 1, 0);
817 }
818
819 static LLVMValueRef build_buffer_load(struct si_shader_context *ctx,
820 LLVMValueRef rsrc,
821 int num_channels,
822 LLVMValueRef vindex,
823 LLVMValueRef voffset,
824 LLVMValueRef soffset,
825 unsigned inst_offset,
826 unsigned glc,
827 unsigned slc)
828 {
829 struct gallivm_state *gallivm = &ctx->gallivm;
830 unsigned func = CLAMP(num_channels, 1, 3) - 1;
831
832 if (HAVE_LLVM >= 0x309) {
833 LLVMValueRef args[] = {
834 LLVMBuildBitCast(gallivm->builder, rsrc, ctx->v4i32, ""),
835 vindex ? vindex : LLVMConstInt(ctx->i32, 0, 0),
836 LLVMConstInt(ctx->i32, inst_offset, 0),
837 LLVMConstInt(ctx->i1, glc, 0),
838 LLVMConstInt(ctx->i1, slc, 0)
839 };
840
841 LLVMTypeRef types[] = {ctx->f32, LLVMVectorType(ctx->f32, 2),
842 ctx->v4f32};
843 const char *type_names[] = {"f32", "v2f32", "v4f32"};
844 char name[256];
845
846 if (voffset) {
847 args[2] = LLVMBuildAdd(gallivm->builder, args[2], voffset,
848 "");
849 }
850
851 if (soffset) {
852 args[2] = LLVMBuildAdd(gallivm->builder, args[2], soffset,
853 "");
854 }
855
856 snprintf(name, sizeof(name), "llvm.amdgcn.buffer.load.%s",
857 type_names[func]);
858
859 return lp_build_intrinsic(gallivm->builder, name, types[func], args,
860 ARRAY_SIZE(args), LP_FUNC_ATTR_READONLY);
861 } else {
862 LLVMValueRef args[] = {
863 LLVMBuildBitCast(gallivm->builder, rsrc, ctx->v16i8, ""),
864 voffset ? voffset : vindex,
865 soffset,
866 LLVMConstInt(ctx->i32, inst_offset, 0),
867 LLVMConstInt(ctx->i32, voffset ? 1 : 0, 0), // offen
868 LLVMConstInt(ctx->i32, vindex ? 1 : 0, 0), //idxen
869 LLVMConstInt(ctx->i32, glc, 0),
870 LLVMConstInt(ctx->i32, slc, 0),
871 LLVMConstInt(ctx->i32, 0, 0), // TFE
872 };
873
874 LLVMTypeRef types[] = {ctx->i32, LLVMVectorType(ctx->i32, 2),
875 ctx->v4i32};
876 const char *type_names[] = {"i32", "v2i32", "v4i32"};
877 const char *arg_type = "i32";
878 char name[256];
879
880 if (voffset && vindex) {
881 LLVMValueRef vaddr[] = {vindex, voffset};
882
883 arg_type = "v2i32";
884 args[1] = lp_build_gather_values(gallivm, vaddr, 2);
885 }
886
887 snprintf(name, sizeof(name), "llvm.SI.buffer.load.dword.%s.%s",
888 type_names[func], arg_type);
889
890 return lp_build_intrinsic(gallivm->builder, name, types[func], args,
891 ARRAY_SIZE(args), LP_FUNC_ATTR_READONLY);
892 }
893 }
894
895 static LLVMValueRef buffer_load(struct lp_build_tgsi_context *bld_base,
896 enum tgsi_opcode_type type, unsigned swizzle,
897 LLVMValueRef buffer, LLVMValueRef offset,
898 LLVMValueRef base)
899 {
900 struct si_shader_context *ctx = si_shader_context(bld_base);
901 struct gallivm_state *gallivm = bld_base->base.gallivm;
902 LLVMValueRef value, value2;
903 LLVMTypeRef llvm_type = tgsi2llvmtype(bld_base, type);
904 LLVMTypeRef vec_type = LLVMVectorType(llvm_type, 4);
905
906 if (swizzle == ~0) {
907 value = build_buffer_load(ctx, buffer, 4, NULL, base, offset,
908 0, 1, 0);
909
910 return LLVMBuildBitCast(gallivm->builder, value, vec_type, "");
911 }
912
913 if (!tgsi_type_is_64bit(type)) {
914 value = build_buffer_load(ctx, buffer, 4, NULL, base, offset,
915 0, 1, 0);
916
917 value = LLVMBuildBitCast(gallivm->builder, value, vec_type, "");
918 return LLVMBuildExtractElement(gallivm->builder, value,
919 lp_build_const_int32(gallivm, swizzle), "");
920 }
921
922 value = build_buffer_load(ctx, buffer, 1, NULL, base, offset,
923 swizzle * 4, 1, 0);
924
925 value2 = build_buffer_load(ctx, buffer, 1, NULL, base, offset,
926 swizzle * 4 + 4, 1, 0);
927
928 return si_llvm_emit_fetch_64bit(bld_base, type, value, value2);
929 }
930
931 /**
932 * Load from LDS.
933 *
934 * \param type output value type
935 * \param swizzle offset (typically 0..3); it can be ~0, which loads a vec4
936 * \param dw_addr address in dwords
937 */
938 static LLVMValueRef lds_load(struct lp_build_tgsi_context *bld_base,
939 enum tgsi_opcode_type type, unsigned swizzle,
940 LLVMValueRef dw_addr)
941 {
942 struct si_shader_context *ctx = si_shader_context(bld_base);
943 struct gallivm_state *gallivm = bld_base->base.gallivm;
944 LLVMValueRef value;
945
946 if (swizzle == ~0) {
947 LLVMValueRef values[TGSI_NUM_CHANNELS];
948
949 for (unsigned chan = 0; chan < TGSI_NUM_CHANNELS; chan++)
950 values[chan] = lds_load(bld_base, type, chan, dw_addr);
951
952 return lp_build_gather_values(bld_base->base.gallivm, values,
953 TGSI_NUM_CHANNELS);
954 }
955
956 dw_addr = lp_build_add(&bld_base->uint_bld, dw_addr,
957 lp_build_const_int32(gallivm, swizzle));
958
959 value = build_indexed_load(ctx, ctx->lds, dw_addr, false);
960 if (tgsi_type_is_64bit(type)) {
961 LLVMValueRef value2;
962 dw_addr = lp_build_add(&bld_base->uint_bld, dw_addr,
963 lp_build_const_int32(gallivm, 1));
964 value2 = build_indexed_load(ctx, ctx->lds, dw_addr, false);
965 return si_llvm_emit_fetch_64bit(bld_base, type, value, value2);
966 }
967
968 return LLVMBuildBitCast(gallivm->builder, value,
969 tgsi2llvmtype(bld_base, type), "");
970 }
971
972 /**
973 * Store to LDS.
974 *
975 * \param swizzle offset (typically 0..3)
976 * \param dw_addr address in dwords
977 * \param value value to store
978 */
979 static void lds_store(struct lp_build_tgsi_context *bld_base,
980 unsigned swizzle, LLVMValueRef dw_addr,
981 LLVMValueRef value)
982 {
983 struct si_shader_context *ctx = si_shader_context(bld_base);
984 struct gallivm_state *gallivm = bld_base->base.gallivm;
985
986 dw_addr = lp_build_add(&bld_base->uint_bld, dw_addr,
987 lp_build_const_int32(gallivm, swizzle));
988
989 value = LLVMBuildBitCast(gallivm->builder, value, ctx->i32, "");
990 build_indexed_store(ctx, ctx->lds,
991 dw_addr, value);
992 }
993
994 static LLVMValueRef fetch_input_tcs(
995 struct lp_build_tgsi_context *bld_base,
996 const struct tgsi_full_src_register *reg,
997 enum tgsi_opcode_type type, unsigned swizzle)
998 {
999 struct si_shader_context *ctx = si_shader_context(bld_base);
1000 LLVMValueRef dw_addr, stride;
1001
1002 stride = unpack_param(ctx, SI_PARAM_TCS_IN_LAYOUT, 13, 8);
1003 dw_addr = get_tcs_in_current_patch_offset(ctx);
1004 dw_addr = get_dw_address(ctx, NULL, reg, stride, dw_addr);
1005
1006 return lds_load(bld_base, type, swizzle, dw_addr);
1007 }
1008
1009 static LLVMValueRef fetch_output_tcs(
1010 struct lp_build_tgsi_context *bld_base,
1011 const struct tgsi_full_src_register *reg,
1012 enum tgsi_opcode_type type, unsigned swizzle)
1013 {
1014 struct si_shader_context *ctx = si_shader_context(bld_base);
1015 LLVMValueRef dw_addr, stride;
1016
1017 if (reg->Register.Dimension) {
1018 stride = unpack_param(ctx, SI_PARAM_TCS_OUT_LAYOUT, 13, 8);
1019 dw_addr = get_tcs_out_current_patch_offset(ctx);
1020 dw_addr = get_dw_address(ctx, NULL, reg, stride, dw_addr);
1021 } else {
1022 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1023 dw_addr = get_dw_address(ctx, NULL, reg, NULL, dw_addr);
1024 }
1025
1026 return lds_load(bld_base, type, swizzle, dw_addr);
1027 }
1028
1029 static LLVMValueRef fetch_input_tes(
1030 struct lp_build_tgsi_context *bld_base,
1031 const struct tgsi_full_src_register *reg,
1032 enum tgsi_opcode_type type, unsigned swizzle)
1033 {
1034 struct si_shader_context *ctx = si_shader_context(bld_base);
1035 struct gallivm_state *gallivm = bld_base->base.gallivm;
1036 LLVMValueRef rw_buffers, buffer, base, addr;
1037
1038 rw_buffers = LLVMGetParam(ctx->main_fn,
1039 SI_PARAM_RW_BUFFERS);
1040 buffer = build_indexed_load_const(ctx, rw_buffers,
1041 lp_build_const_int32(gallivm, SI_HS_RING_TESS_OFFCHIP));
1042
1043 base = LLVMGetParam(ctx->main_fn, ctx->param_oc_lds);
1044 addr = get_tcs_tes_buffer_address_from_reg(ctx, NULL, reg);
1045
1046 return buffer_load(bld_base, type, swizzle, buffer, base, addr);
1047 }
1048
1049 static void store_output_tcs(struct lp_build_tgsi_context *bld_base,
1050 const struct tgsi_full_instruction *inst,
1051 const struct tgsi_opcode_info *info,
1052 LLVMValueRef dst[4])
1053 {
1054 struct si_shader_context *ctx = si_shader_context(bld_base);
1055 struct gallivm_state *gallivm = bld_base->base.gallivm;
1056 const struct tgsi_full_dst_register *reg = &inst->Dst[0];
1057 unsigned chan_index;
1058 LLVMValueRef dw_addr, stride;
1059 LLVMValueRef rw_buffers, buffer, base, buf_addr;
1060 LLVMValueRef values[4];
1061
1062 /* Only handle per-patch and per-vertex outputs here.
1063 * Vectors will be lowered to scalars and this function will be called again.
1064 */
1065 if (reg->Register.File != TGSI_FILE_OUTPUT ||
1066 (dst[0] && LLVMGetTypeKind(LLVMTypeOf(dst[0])) == LLVMVectorTypeKind)) {
1067 si_llvm_emit_store(bld_base, inst, info, dst);
1068 return;
1069 }
1070
1071 if (reg->Register.Dimension) {
1072 stride = unpack_param(ctx, SI_PARAM_TCS_OUT_LAYOUT, 13, 8);
1073 dw_addr = get_tcs_out_current_patch_offset(ctx);
1074 dw_addr = get_dw_address(ctx, reg, NULL, stride, dw_addr);
1075 } else {
1076 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1077 dw_addr = get_dw_address(ctx, reg, NULL, NULL, dw_addr);
1078 }
1079
1080 rw_buffers = LLVMGetParam(ctx->main_fn,
1081 SI_PARAM_RW_BUFFERS);
1082 buffer = build_indexed_load_const(ctx, rw_buffers,
1083 lp_build_const_int32(gallivm, SI_HS_RING_TESS_OFFCHIP));
1084
1085 base = LLVMGetParam(ctx->main_fn, ctx->param_oc_lds);
1086 buf_addr = get_tcs_tes_buffer_address_from_reg(ctx, reg, NULL);
1087
1088
1089 TGSI_FOR_EACH_DST0_ENABLED_CHANNEL(inst, chan_index) {
1090 LLVMValueRef value = dst[chan_index];
1091
1092 if (inst->Instruction.Saturate)
1093 value = si_llvm_saturate(bld_base, value);
1094
1095 lds_store(bld_base, chan_index, dw_addr, value);
1096
1097 value = LLVMBuildBitCast(gallivm->builder, value, ctx->i32, "");
1098 values[chan_index] = value;
1099
1100 if (inst->Dst[0].Register.WriteMask != 0xF) {
1101 build_tbuffer_store_dwords(ctx, buffer, value, 1,
1102 buf_addr, base,
1103 4 * chan_index);
1104 }
1105 }
1106
1107 if (inst->Dst[0].Register.WriteMask == 0xF) {
1108 LLVMValueRef value = lp_build_gather_values(bld_base->base.gallivm,
1109 values, 4);
1110 build_tbuffer_store_dwords(ctx, buffer, value, 4, buf_addr,
1111 base, 0);
1112 }
1113 }
1114
1115 static LLVMValueRef fetch_input_gs(
1116 struct lp_build_tgsi_context *bld_base,
1117 const struct tgsi_full_src_register *reg,
1118 enum tgsi_opcode_type type,
1119 unsigned swizzle)
1120 {
1121 struct lp_build_context *base = &bld_base->base;
1122 struct si_shader_context *ctx = si_shader_context(bld_base);
1123 struct si_shader *shader = ctx->shader;
1124 struct lp_build_context *uint = &ctx->soa.bld_base.uint_bld;
1125 struct gallivm_state *gallivm = base->gallivm;
1126 LLVMValueRef vtx_offset;
1127 LLVMValueRef args[9];
1128 unsigned vtx_offset_param;
1129 struct tgsi_shader_info *info = &shader->selector->info;
1130 unsigned semantic_name = info->input_semantic_name[reg->Register.Index];
1131 unsigned semantic_index = info->input_semantic_index[reg->Register.Index];
1132 unsigned param;
1133 LLVMValueRef value;
1134
1135 if (swizzle != ~0 && semantic_name == TGSI_SEMANTIC_PRIMID)
1136 return get_primitive_id(bld_base, swizzle);
1137
1138 if (!reg->Register.Dimension)
1139 return NULL;
1140
1141 if (swizzle == ~0) {
1142 LLVMValueRef values[TGSI_NUM_CHANNELS];
1143 unsigned chan;
1144 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1145 values[chan] = fetch_input_gs(bld_base, reg, type, chan);
1146 }
1147 return lp_build_gather_values(bld_base->base.gallivm, values,
1148 TGSI_NUM_CHANNELS);
1149 }
1150
1151 /* Get the vertex offset parameter */
1152 vtx_offset_param = reg->Dimension.Index;
1153 if (vtx_offset_param < 2) {
1154 vtx_offset_param += SI_PARAM_VTX0_OFFSET;
1155 } else {
1156 assert(vtx_offset_param < 6);
1157 vtx_offset_param += SI_PARAM_VTX2_OFFSET - 2;
1158 }
1159 vtx_offset = lp_build_mul_imm(uint,
1160 LLVMGetParam(ctx->main_fn,
1161 vtx_offset_param),
1162 4);
1163
1164 param = si_shader_io_get_unique_index(semantic_name, semantic_index);
1165 args[0] = ctx->esgs_ring;
1166 args[1] = vtx_offset;
1167 args[2] = lp_build_const_int32(gallivm, (param * 4 + swizzle) * 256);
1168 args[3] = uint->zero;
1169 args[4] = uint->one; /* OFFEN */
1170 args[5] = uint->zero; /* IDXEN */
1171 args[6] = uint->one; /* GLC */
1172 args[7] = uint->zero; /* SLC */
1173 args[8] = uint->zero; /* TFE */
1174
1175 value = lp_build_intrinsic(gallivm->builder,
1176 "llvm.SI.buffer.load.dword.i32.i32",
1177 ctx->i32, args, 9,
1178 LP_FUNC_ATTR_READONLY);
1179 if (tgsi_type_is_64bit(type)) {
1180 LLVMValueRef value2;
1181 args[2] = lp_build_const_int32(gallivm, (param * 4 + swizzle + 1) * 256);
1182 value2 = lp_build_intrinsic(gallivm->builder,
1183 "llvm.SI.buffer.load.dword.i32.i32",
1184 ctx->i32, args, 9,
1185 LP_FUNC_ATTR_READONLY);
1186 return si_llvm_emit_fetch_64bit(bld_base, type,
1187 value, value2);
1188 }
1189 return LLVMBuildBitCast(gallivm->builder,
1190 value,
1191 tgsi2llvmtype(bld_base, type), "");
1192 }
1193
1194 static int lookup_interp_param_index(unsigned interpolate, unsigned location)
1195 {
1196 switch (interpolate) {
1197 case TGSI_INTERPOLATE_CONSTANT:
1198 return 0;
1199
1200 case TGSI_INTERPOLATE_LINEAR:
1201 if (location == TGSI_INTERPOLATE_LOC_SAMPLE)
1202 return SI_PARAM_LINEAR_SAMPLE;
1203 else if (location == TGSI_INTERPOLATE_LOC_CENTROID)
1204 return SI_PARAM_LINEAR_CENTROID;
1205 else
1206 return SI_PARAM_LINEAR_CENTER;
1207 break;
1208 case TGSI_INTERPOLATE_COLOR:
1209 case TGSI_INTERPOLATE_PERSPECTIVE:
1210 if (location == TGSI_INTERPOLATE_LOC_SAMPLE)
1211 return SI_PARAM_PERSP_SAMPLE;
1212 else if (location == TGSI_INTERPOLATE_LOC_CENTROID)
1213 return SI_PARAM_PERSP_CENTROID;
1214 else
1215 return SI_PARAM_PERSP_CENTER;
1216 break;
1217 default:
1218 fprintf(stderr, "Warning: Unhandled interpolation mode.\n");
1219 return -1;
1220 }
1221 }
1222
1223 /**
1224 * Interpolate a fragment shader input.
1225 *
1226 * @param ctx context
1227 * @param input_index index of the input in hardware
1228 * @param semantic_name TGSI_SEMANTIC_*
1229 * @param semantic_index semantic index
1230 * @param num_interp_inputs number of all interpolated inputs (= BCOLOR offset)
1231 * @param colors_read_mask color components read (4 bits for each color, 8 bits in total)
1232 * @param interp_param interpolation weights (i,j)
1233 * @param prim_mask SI_PARAM_PRIM_MASK
1234 * @param face SI_PARAM_FRONT_FACE
1235 * @param result the return value (4 components)
1236 */
1237 static void interp_fs_input(struct si_shader_context *ctx,
1238 unsigned input_index,
1239 unsigned semantic_name,
1240 unsigned semantic_index,
1241 unsigned num_interp_inputs,
1242 unsigned colors_read_mask,
1243 LLVMValueRef interp_param,
1244 LLVMValueRef prim_mask,
1245 LLVMValueRef face,
1246 LLVMValueRef result[4])
1247 {
1248 struct lp_build_context *base = &ctx->soa.bld_base.base;
1249 struct lp_build_context *uint = &ctx->soa.bld_base.uint_bld;
1250 struct gallivm_state *gallivm = base->gallivm;
1251 const char *intr_name;
1252 LLVMValueRef attr_number;
1253
1254 unsigned chan;
1255
1256 attr_number = lp_build_const_int32(gallivm, input_index);
1257
1258 /* fs.constant returns the param from the middle vertex, so it's not
1259 * really useful for flat shading. It's meant to be used for custom
1260 * interpolation (but the intrinsic can't fetch from the other two
1261 * vertices).
1262 *
1263 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
1264 * to do the right thing. The only reason we use fs.constant is that
1265 * fs.interp cannot be used on integers, because they can be equal
1266 * to NaN.
1267 */
1268 intr_name = interp_param ? "llvm.SI.fs.interp" : "llvm.SI.fs.constant";
1269
1270 if (semantic_name == TGSI_SEMANTIC_COLOR &&
1271 ctx->shader->key.part.ps.prolog.color_two_side) {
1272 LLVMValueRef args[4];
1273 LLVMValueRef is_face_positive;
1274 LLVMValueRef back_attr_number;
1275
1276 /* If BCOLOR0 is used, BCOLOR1 is at offset "num_inputs + 1",
1277 * otherwise it's at offset "num_inputs".
1278 */
1279 unsigned back_attr_offset = num_interp_inputs;
1280 if (semantic_index == 1 && colors_read_mask & 0xf)
1281 back_attr_offset += 1;
1282
1283 back_attr_number = lp_build_const_int32(gallivm, back_attr_offset);
1284
1285 is_face_positive = LLVMBuildICmp(gallivm->builder, LLVMIntNE,
1286 face, uint->zero, "");
1287
1288 args[2] = prim_mask;
1289 args[3] = interp_param;
1290 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1291 LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan);
1292 LLVMValueRef front, back;
1293
1294 args[0] = llvm_chan;
1295 args[1] = attr_number;
1296 front = lp_build_intrinsic(gallivm->builder, intr_name,
1297 ctx->f32, args, args[3] ? 4 : 3,
1298 LP_FUNC_ATTR_READNONE);
1299
1300 args[1] = back_attr_number;
1301 back = lp_build_intrinsic(gallivm->builder, intr_name,
1302 ctx->f32, args, args[3] ? 4 : 3,
1303 LP_FUNC_ATTR_READNONE);
1304
1305 result[chan] = LLVMBuildSelect(gallivm->builder,
1306 is_face_positive,
1307 front,
1308 back,
1309 "");
1310 }
1311 } else if (semantic_name == TGSI_SEMANTIC_FOG) {
1312 LLVMValueRef args[4];
1313
1314 args[0] = uint->zero;
1315 args[1] = attr_number;
1316 args[2] = prim_mask;
1317 args[3] = interp_param;
1318 result[0] = lp_build_intrinsic(gallivm->builder, intr_name,
1319 ctx->f32, args, args[3] ? 4 : 3,
1320 LP_FUNC_ATTR_READNONE);
1321 result[1] =
1322 result[2] = lp_build_const_float(gallivm, 0.0f);
1323 result[3] = lp_build_const_float(gallivm, 1.0f);
1324 } else {
1325 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1326 LLVMValueRef args[4];
1327 LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan);
1328
1329 args[0] = llvm_chan;
1330 args[1] = attr_number;
1331 args[2] = prim_mask;
1332 args[3] = interp_param;
1333 result[chan] = lp_build_intrinsic(gallivm->builder, intr_name,
1334 ctx->f32, args, args[3] ? 4 : 3,
1335 LP_FUNC_ATTR_READNONE);
1336 }
1337 }
1338 }
1339
1340 static void declare_input_fs(
1341 struct si_shader_context *radeon_bld,
1342 unsigned input_index,
1343 const struct tgsi_full_declaration *decl,
1344 LLVMValueRef out[4])
1345 {
1346 struct lp_build_context *base = &radeon_bld->soa.bld_base.base;
1347 struct si_shader_context *ctx =
1348 si_shader_context(&radeon_bld->soa.bld_base);
1349 struct si_shader *shader = ctx->shader;
1350 LLVMValueRef main_fn = radeon_bld->main_fn;
1351 LLVMValueRef interp_param = NULL;
1352 int interp_param_idx;
1353
1354 /* Get colors from input VGPRs (set by the prolog). */
1355 if (decl->Semantic.Name == TGSI_SEMANTIC_COLOR) {
1356 unsigned i = decl->Semantic.Index;
1357 unsigned colors_read = shader->selector->info.colors_read;
1358 unsigned mask = colors_read >> (i * 4);
1359 unsigned offset = SI_PARAM_POS_FIXED_PT + 1 +
1360 (i ? util_bitcount(colors_read & 0xf) : 0);
1361
1362 out[0] = mask & 0x1 ? LLVMGetParam(main_fn, offset++) : base->undef;
1363 out[1] = mask & 0x2 ? LLVMGetParam(main_fn, offset++) : base->undef;
1364 out[2] = mask & 0x4 ? LLVMGetParam(main_fn, offset++) : base->undef;
1365 out[3] = mask & 0x8 ? LLVMGetParam(main_fn, offset++) : base->undef;
1366 return;
1367 }
1368
1369 interp_param_idx = lookup_interp_param_index(decl->Interp.Interpolate,
1370 decl->Interp.Location);
1371 if (interp_param_idx == -1)
1372 return;
1373 else if (interp_param_idx) {
1374 interp_param = LLVMGetParam(ctx->main_fn, interp_param_idx);
1375 }
1376
1377 if (decl->Semantic.Name == TGSI_SEMANTIC_COLOR &&
1378 decl->Interp.Interpolate == TGSI_INTERPOLATE_COLOR &&
1379 ctx->shader->key.part.ps.prolog.flatshade_colors)
1380 interp_param = NULL; /* load the constant color */
1381
1382 interp_fs_input(ctx, input_index, decl->Semantic.Name,
1383 decl->Semantic.Index, shader->selector->info.num_inputs,
1384 shader->selector->info.colors_read, interp_param,
1385 LLVMGetParam(main_fn, SI_PARAM_PRIM_MASK),
1386 LLVMGetParam(main_fn, SI_PARAM_FRONT_FACE),
1387 &out[0]);
1388 }
1389
1390 static LLVMValueRef get_sample_id(struct si_shader_context *radeon_bld)
1391 {
1392 return unpack_param(si_shader_context(&radeon_bld->soa.bld_base),
1393 SI_PARAM_ANCILLARY, 8, 4);
1394 }
1395
1396 /**
1397 * Set range metadata on an instruction. This can only be used on load and
1398 * call instructions. If you know an instruction can only produce the values
1399 * 0, 1, 2, you would do set_range_metadata(value, 0, 3);
1400 * \p lo is the minimum value inclusive.
1401 * \p hi is the maximum value exclusive.
1402 */
1403 static void set_range_metadata(struct si_shader_context *ctx,
1404 LLVMValueRef value, unsigned lo, unsigned hi)
1405 {
1406 LLVMValueRef range_md, md_args[2];
1407 LLVMTypeRef type = LLVMTypeOf(value);
1408 LLVMContextRef context = LLVMGetTypeContext(type);
1409
1410 md_args[0] = LLVMConstInt(type, lo, false);
1411 md_args[1] = LLVMConstInt(type, hi, false);
1412 range_md = LLVMMDNodeInContext(context, md_args, 2);
1413 LLVMSetMetadata(value, ctx->range_md_kind, range_md);
1414 }
1415
1416 static LLVMValueRef get_thread_id(struct si_shader_context *ctx)
1417 {
1418 struct gallivm_state *gallivm = &ctx->gallivm;
1419 LLVMValueRef tid;
1420
1421 if (HAVE_LLVM < 0x0308) {
1422 tid = lp_build_intrinsic(gallivm->builder, "llvm.SI.tid",
1423 ctx->i32, NULL, 0, LP_FUNC_ATTR_READNONE);
1424 } else {
1425 LLVMValueRef tid_args[2];
1426 tid_args[0] = lp_build_const_int32(gallivm, 0xffffffff);
1427 tid_args[1] = lp_build_const_int32(gallivm, 0);
1428 tid_args[1] = lp_build_intrinsic(gallivm->builder,
1429 "llvm.amdgcn.mbcnt.lo", ctx->i32,
1430 tid_args, 2, LP_FUNC_ATTR_READNONE);
1431
1432 tid = lp_build_intrinsic(gallivm->builder,
1433 "llvm.amdgcn.mbcnt.hi", ctx->i32,
1434 tid_args, 2, LP_FUNC_ATTR_READNONE);
1435 }
1436 set_range_metadata(ctx, tid, 0, 64);
1437 return tid;
1438 }
1439
1440 /**
1441 * Load a dword from a constant buffer.
1442 */
1443 static LLVMValueRef buffer_load_const(struct si_shader_context *ctx,
1444 LLVMValueRef resource,
1445 LLVMValueRef offset)
1446 {
1447 LLVMBuilderRef builder = ctx->gallivm.builder;
1448 LLVMValueRef args[2] = {resource, offset};
1449
1450 return lp_build_intrinsic(builder, "llvm.SI.load.const", ctx->f32, args, 2,
1451 LP_FUNC_ATTR_READNONE);
1452 }
1453
1454 static LLVMValueRef load_sample_position(struct si_shader_context *radeon_bld, LLVMValueRef sample_id)
1455 {
1456 struct si_shader_context *ctx =
1457 si_shader_context(&radeon_bld->soa.bld_base);
1458 struct lp_build_context *uint_bld = &radeon_bld->soa.bld_base.uint_bld;
1459 struct gallivm_state *gallivm = &radeon_bld->gallivm;
1460 LLVMBuilderRef builder = gallivm->builder;
1461 LLVMValueRef desc = LLVMGetParam(ctx->main_fn, SI_PARAM_RW_BUFFERS);
1462 LLVMValueRef buf_index = lp_build_const_int32(gallivm, SI_PS_CONST_SAMPLE_POSITIONS);
1463 LLVMValueRef resource = build_indexed_load_const(ctx, desc, buf_index);
1464
1465 /* offset = sample_id * 8 (8 = 2 floats containing samplepos.xy) */
1466 LLVMValueRef offset0 = lp_build_mul_imm(uint_bld, sample_id, 8);
1467 LLVMValueRef offset1 = LLVMBuildAdd(builder, offset0, lp_build_const_int32(gallivm, 4), "");
1468
1469 LLVMValueRef pos[4] = {
1470 buffer_load_const(ctx, resource, offset0),
1471 buffer_load_const(ctx, resource, offset1),
1472 lp_build_const_float(gallivm, 0),
1473 lp_build_const_float(gallivm, 0)
1474 };
1475
1476 return lp_build_gather_values(gallivm, pos, 4);
1477 }
1478
1479 static void declare_system_value(
1480 struct si_shader_context *radeon_bld,
1481 unsigned index,
1482 const struct tgsi_full_declaration *decl)
1483 {
1484 struct si_shader_context *ctx =
1485 si_shader_context(&radeon_bld->soa.bld_base);
1486 struct lp_build_context *bld = &radeon_bld->soa.bld_base.base;
1487 struct gallivm_state *gallivm = &radeon_bld->gallivm;
1488 LLVMValueRef value = 0;
1489
1490 switch (decl->Semantic.Name) {
1491 case TGSI_SEMANTIC_INSTANCEID:
1492 value = LLVMGetParam(radeon_bld->main_fn,
1493 ctx->param_instance_id);
1494 break;
1495
1496 case TGSI_SEMANTIC_VERTEXID:
1497 value = LLVMBuildAdd(gallivm->builder,
1498 LLVMGetParam(radeon_bld->main_fn,
1499 ctx->param_vertex_id),
1500 LLVMGetParam(radeon_bld->main_fn,
1501 SI_PARAM_BASE_VERTEX), "");
1502 break;
1503
1504 case TGSI_SEMANTIC_VERTEXID_NOBASE:
1505 value = LLVMGetParam(radeon_bld->main_fn,
1506 ctx->param_vertex_id);
1507 break;
1508
1509 case TGSI_SEMANTIC_BASEVERTEX:
1510 value = LLVMGetParam(radeon_bld->main_fn,
1511 SI_PARAM_BASE_VERTEX);
1512 break;
1513
1514 case TGSI_SEMANTIC_BASEINSTANCE:
1515 value = LLVMGetParam(radeon_bld->main_fn,
1516 SI_PARAM_START_INSTANCE);
1517 break;
1518
1519 case TGSI_SEMANTIC_DRAWID:
1520 value = LLVMGetParam(radeon_bld->main_fn,
1521 SI_PARAM_DRAWID);
1522 break;
1523
1524 case TGSI_SEMANTIC_INVOCATIONID:
1525 if (ctx->type == PIPE_SHADER_TESS_CTRL)
1526 value = unpack_param(ctx, SI_PARAM_REL_IDS, 8, 5);
1527 else if (ctx->type == PIPE_SHADER_GEOMETRY)
1528 value = LLVMGetParam(radeon_bld->main_fn,
1529 SI_PARAM_GS_INSTANCE_ID);
1530 else
1531 assert(!"INVOCATIONID not implemented");
1532 break;
1533
1534 case TGSI_SEMANTIC_POSITION:
1535 {
1536 LLVMValueRef pos[4] = {
1537 LLVMGetParam(radeon_bld->main_fn, SI_PARAM_POS_X_FLOAT),
1538 LLVMGetParam(radeon_bld->main_fn, SI_PARAM_POS_Y_FLOAT),
1539 LLVMGetParam(radeon_bld->main_fn, SI_PARAM_POS_Z_FLOAT),
1540 lp_build_emit_llvm_unary(&radeon_bld->soa.bld_base, TGSI_OPCODE_RCP,
1541 LLVMGetParam(radeon_bld->main_fn,
1542 SI_PARAM_POS_W_FLOAT)),
1543 };
1544 value = lp_build_gather_values(gallivm, pos, 4);
1545 break;
1546 }
1547
1548 case TGSI_SEMANTIC_FACE:
1549 value = LLVMGetParam(radeon_bld->main_fn, SI_PARAM_FRONT_FACE);
1550 break;
1551
1552 case TGSI_SEMANTIC_SAMPLEID:
1553 value = get_sample_id(radeon_bld);
1554 break;
1555
1556 case TGSI_SEMANTIC_SAMPLEPOS: {
1557 LLVMValueRef pos[4] = {
1558 LLVMGetParam(radeon_bld->main_fn, SI_PARAM_POS_X_FLOAT),
1559 LLVMGetParam(radeon_bld->main_fn, SI_PARAM_POS_Y_FLOAT),
1560 lp_build_const_float(gallivm, 0),
1561 lp_build_const_float(gallivm, 0)
1562 };
1563 pos[0] = lp_build_emit_llvm_unary(&radeon_bld->soa.bld_base,
1564 TGSI_OPCODE_FRC, pos[0]);
1565 pos[1] = lp_build_emit_llvm_unary(&radeon_bld->soa.bld_base,
1566 TGSI_OPCODE_FRC, pos[1]);
1567 value = lp_build_gather_values(gallivm, pos, 4);
1568 break;
1569 }
1570
1571 case TGSI_SEMANTIC_SAMPLEMASK:
1572 /* This can only occur with the OpenGL Core profile, which
1573 * doesn't support smoothing.
1574 */
1575 value = LLVMGetParam(radeon_bld->main_fn, SI_PARAM_SAMPLE_COVERAGE);
1576 break;
1577
1578 case TGSI_SEMANTIC_TESSCOORD:
1579 {
1580 LLVMValueRef coord[4] = {
1581 LLVMGetParam(radeon_bld->main_fn, ctx->param_tes_u),
1582 LLVMGetParam(radeon_bld->main_fn, ctx->param_tes_v),
1583 bld->zero,
1584 bld->zero
1585 };
1586
1587 /* For triangles, the vector should be (u, v, 1-u-v). */
1588 if (ctx->shader->selector->info.properties[TGSI_PROPERTY_TES_PRIM_MODE] ==
1589 PIPE_PRIM_TRIANGLES)
1590 coord[2] = lp_build_sub(bld, bld->one,
1591 lp_build_add(bld, coord[0], coord[1]));
1592
1593 value = lp_build_gather_values(gallivm, coord, 4);
1594 break;
1595 }
1596
1597 case TGSI_SEMANTIC_VERTICESIN:
1598 if (ctx->type == PIPE_SHADER_TESS_CTRL)
1599 value = unpack_param(ctx, SI_PARAM_TCS_OUT_LAYOUT, 26, 6);
1600 else if (ctx->type == PIPE_SHADER_TESS_EVAL)
1601 value = unpack_param(ctx, SI_PARAM_TCS_OFFCHIP_LAYOUT, 9, 7);
1602 else
1603 assert(!"invalid shader stage for TGSI_SEMANTIC_VERTICESIN");
1604 break;
1605
1606 case TGSI_SEMANTIC_TESSINNER:
1607 case TGSI_SEMANTIC_TESSOUTER:
1608 {
1609 LLVMValueRef rw_buffers, buffer, base, addr;
1610 int param = si_shader_io_get_unique_index(decl->Semantic.Name, 0);
1611
1612 rw_buffers = LLVMGetParam(ctx->main_fn,
1613 SI_PARAM_RW_BUFFERS);
1614 buffer = build_indexed_load_const(ctx, rw_buffers,
1615 lp_build_const_int32(gallivm, SI_HS_RING_TESS_OFFCHIP));
1616
1617 base = LLVMGetParam(ctx->main_fn, ctx->param_oc_lds);
1618 addr = get_tcs_tes_buffer_address(ctx, NULL,
1619 lp_build_const_int32(gallivm, param));
1620
1621 value = buffer_load(&radeon_bld->soa.bld_base, TGSI_TYPE_FLOAT,
1622 ~0, buffer, base, addr);
1623
1624 break;
1625 }
1626
1627 case TGSI_SEMANTIC_DEFAULT_TESSOUTER_SI:
1628 case TGSI_SEMANTIC_DEFAULT_TESSINNER_SI:
1629 {
1630 LLVMValueRef buf, slot, val[4];
1631 int i, offset;
1632
1633 slot = lp_build_const_int32(gallivm, SI_HS_CONST_DEFAULT_TESS_LEVELS);
1634 buf = LLVMGetParam(ctx->main_fn, SI_PARAM_RW_BUFFERS);
1635 buf = build_indexed_load_const(ctx, buf, slot);
1636 offset = decl->Semantic.Name == TGSI_SEMANTIC_DEFAULT_TESSINNER_SI ? 4 : 0;
1637
1638 for (i = 0; i < 4; i++)
1639 val[i] = buffer_load_const(ctx, buf,
1640 lp_build_const_int32(gallivm, (offset + i) * 4));
1641 value = lp_build_gather_values(gallivm, val, 4);
1642 break;
1643 }
1644
1645 case TGSI_SEMANTIC_PRIMID:
1646 value = get_primitive_id(&radeon_bld->soa.bld_base, 0);
1647 break;
1648
1649 case TGSI_SEMANTIC_GRID_SIZE:
1650 value = LLVMGetParam(radeon_bld->main_fn, SI_PARAM_GRID_SIZE);
1651 break;
1652
1653 case TGSI_SEMANTIC_BLOCK_SIZE:
1654 {
1655 LLVMValueRef values[3];
1656 unsigned i;
1657 unsigned *properties = ctx->shader->selector->info.properties;
1658
1659 if (properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] != 0) {
1660 unsigned sizes[3] = {
1661 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH],
1662 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT],
1663 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH]
1664 };
1665
1666 for (i = 0; i < 3; ++i)
1667 values[i] = lp_build_const_int32(gallivm, sizes[i]);
1668
1669 value = lp_build_gather_values(gallivm, values, 3);
1670 } else {
1671 value = LLVMGetParam(radeon_bld->main_fn, SI_PARAM_BLOCK_SIZE);
1672 }
1673 break;
1674 }
1675
1676 case TGSI_SEMANTIC_BLOCK_ID:
1677 value = LLVMGetParam(radeon_bld->main_fn, SI_PARAM_BLOCK_ID);
1678 break;
1679
1680 case TGSI_SEMANTIC_THREAD_ID:
1681 value = LLVMGetParam(radeon_bld->main_fn, SI_PARAM_THREAD_ID);
1682 break;
1683
1684 #if HAVE_LLVM >= 0x0309
1685 case TGSI_SEMANTIC_HELPER_INVOCATION:
1686 value = lp_build_intrinsic(gallivm->builder,
1687 "llvm.amdgcn.ps.live",
1688 ctx->i1, NULL, 0,
1689 LP_FUNC_ATTR_READNONE);
1690 value = LLVMBuildNot(gallivm->builder, value, "");
1691 value = LLVMBuildSExt(gallivm->builder, value, ctx->i32, "");
1692 break;
1693 #endif
1694
1695 default:
1696 assert(!"unknown system value");
1697 return;
1698 }
1699
1700 radeon_bld->system_values[index] = value;
1701 }
1702
1703 static void declare_compute_memory(struct si_shader_context *radeon_bld,
1704 const struct tgsi_full_declaration *decl)
1705 {
1706 struct si_shader_context *ctx =
1707 si_shader_context(&radeon_bld->soa.bld_base);
1708 struct si_shader_selector *sel = ctx->shader->selector;
1709 struct gallivm_state *gallivm = &radeon_bld->gallivm;
1710
1711 LLVMTypeRef i8p = LLVMPointerType(ctx->i8, LOCAL_ADDR_SPACE);
1712 LLVMValueRef var;
1713
1714 assert(decl->Declaration.MemType == TGSI_MEMORY_TYPE_SHARED);
1715 assert(decl->Range.First == decl->Range.Last);
1716 assert(!ctx->shared_memory);
1717
1718 var = LLVMAddGlobalInAddressSpace(gallivm->module,
1719 LLVMArrayType(ctx->i8, sel->local_size),
1720 "compute_lds",
1721 LOCAL_ADDR_SPACE);
1722 LLVMSetAlignment(var, 4);
1723
1724 ctx->shared_memory = LLVMBuildBitCast(gallivm->builder, var, i8p, "");
1725 }
1726
1727 static LLVMValueRef load_const_buffer_desc(struct si_shader_context *ctx, int i)
1728 {
1729 LLVMValueRef list_ptr = LLVMGetParam(ctx->main_fn,
1730 SI_PARAM_CONST_BUFFERS);
1731
1732 return build_indexed_load_const(ctx, list_ptr,
1733 LLVMConstInt(ctx->i32, i, 0));
1734 }
1735
1736 static LLVMValueRef fetch_constant(
1737 struct lp_build_tgsi_context *bld_base,
1738 const struct tgsi_full_src_register *reg,
1739 enum tgsi_opcode_type type,
1740 unsigned swizzle)
1741 {
1742 struct si_shader_context *ctx = si_shader_context(bld_base);
1743 struct lp_build_context *base = &bld_base->base;
1744 const struct tgsi_ind_register *ireg = &reg->Indirect;
1745 unsigned buf, idx;
1746
1747 LLVMValueRef addr, bufp;
1748 LLVMValueRef result;
1749
1750 if (swizzle == LP_CHAN_ALL) {
1751 unsigned chan;
1752 LLVMValueRef values[4];
1753 for (chan = 0; chan < TGSI_NUM_CHANNELS; ++chan)
1754 values[chan] = fetch_constant(bld_base, reg, type, chan);
1755
1756 return lp_build_gather_values(bld_base->base.gallivm, values, 4);
1757 }
1758
1759 buf = reg->Register.Dimension ? reg->Dimension.Index : 0;
1760 idx = reg->Register.Index * 4 + swizzle;
1761
1762 if (reg->Register.Dimension && reg->Dimension.Indirect) {
1763 LLVMValueRef ptr = LLVMGetParam(ctx->main_fn, SI_PARAM_CONST_BUFFERS);
1764 LLVMValueRef index;
1765 index = get_bounded_indirect_index(ctx, &reg->DimIndirect,
1766 reg->Dimension.Index,
1767 SI_NUM_CONST_BUFFERS);
1768 bufp = build_indexed_load_const(ctx, ptr, index);
1769 } else
1770 bufp = load_const_buffer_desc(ctx, buf);
1771
1772 if (reg->Register.Indirect) {
1773 addr = ctx->soa.addr[ireg->Index][ireg->Swizzle];
1774 addr = LLVMBuildLoad(base->gallivm->builder, addr, "load addr reg");
1775 addr = lp_build_mul_imm(&bld_base->uint_bld, addr, 16);
1776 addr = lp_build_add(&bld_base->uint_bld, addr,
1777 lp_build_const_int32(base->gallivm, idx * 4));
1778 } else {
1779 addr = LLVMConstInt(ctx->i32, idx * 4, 0);
1780 }
1781
1782 result = buffer_load_const(ctx, bufp, addr);
1783
1784 if (!tgsi_type_is_64bit(type))
1785 result = bitcast(bld_base, type, result);
1786 else {
1787 LLVMValueRef addr2, result2;
1788
1789 addr2 = lp_build_add(&bld_base->uint_bld, addr,
1790 LLVMConstInt(ctx->i32, 4, 0));
1791 result2 = buffer_load_const(ctx, bufp, addr2);
1792
1793 result = si_llvm_emit_fetch_64bit(bld_base, type,
1794 result, result2);
1795 }
1796 return result;
1797 }
1798
1799 /* Upper 16 bits must be zero. */
1800 static LLVMValueRef si_llvm_pack_two_int16(struct gallivm_state *gallivm,
1801 LLVMValueRef val[2])
1802 {
1803 return LLVMBuildOr(gallivm->builder, val[0],
1804 LLVMBuildShl(gallivm->builder, val[1],
1805 lp_build_const_int32(gallivm, 16),
1806 ""), "");
1807 }
1808
1809 /* Upper 16 bits are ignored and will be dropped. */
1810 static LLVMValueRef si_llvm_pack_two_int32_as_int16(struct gallivm_state *gallivm,
1811 LLVMValueRef val[2])
1812 {
1813 LLVMValueRef v[2] = {
1814 LLVMBuildAnd(gallivm->builder, val[0],
1815 lp_build_const_int32(gallivm, 0xffff), ""),
1816 val[1],
1817 };
1818 return si_llvm_pack_two_int16(gallivm, v);
1819 }
1820
1821 /* Initialize arguments for the shader export intrinsic */
1822 static void si_llvm_init_export_args(struct lp_build_tgsi_context *bld_base,
1823 LLVMValueRef *values,
1824 unsigned target,
1825 LLVMValueRef *args)
1826 {
1827 struct si_shader_context *ctx = si_shader_context(bld_base);
1828 struct lp_build_context *uint =
1829 &ctx->soa.bld_base.uint_bld;
1830 struct lp_build_context *base = &bld_base->base;
1831 struct gallivm_state *gallivm = base->gallivm;
1832 LLVMBuilderRef builder = base->gallivm->builder;
1833 LLVMValueRef val[4];
1834 unsigned spi_shader_col_format = V_028714_SPI_SHADER_32_ABGR;
1835 unsigned chan;
1836 bool is_int8;
1837
1838 /* Default is 0xf. Adjusted below depending on the format. */
1839 args[0] = lp_build_const_int32(base->gallivm, 0xf); /* writemask */
1840
1841 /* Specify whether the EXEC mask represents the valid mask */
1842 args[1] = uint->zero;
1843
1844 /* Specify whether this is the last export */
1845 args[2] = uint->zero;
1846
1847 /* Specify the target we are exporting */
1848 args[3] = lp_build_const_int32(base->gallivm, target);
1849
1850 if (ctx->type == PIPE_SHADER_FRAGMENT) {
1851 const struct si_shader_key *key = &ctx->shader->key;
1852 unsigned col_formats = key->part.ps.epilog.spi_shader_col_format;
1853 int cbuf = target - V_008DFC_SQ_EXP_MRT;
1854
1855 assert(cbuf >= 0 && cbuf < 8);
1856 spi_shader_col_format = (col_formats >> (cbuf * 4)) & 0xf;
1857 is_int8 = (key->part.ps.epilog.color_is_int8 >> cbuf) & 0x1;
1858 }
1859
1860 args[4] = uint->zero; /* COMPR flag */
1861 args[5] = base->undef;
1862 args[6] = base->undef;
1863 args[7] = base->undef;
1864 args[8] = base->undef;
1865
1866 switch (spi_shader_col_format) {
1867 case V_028714_SPI_SHADER_ZERO:
1868 args[0] = uint->zero; /* writemask */
1869 args[3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_NULL);
1870 break;
1871
1872 case V_028714_SPI_SHADER_32_R:
1873 args[0] = uint->one; /* writemask */
1874 args[5] = values[0];
1875 break;
1876
1877 case V_028714_SPI_SHADER_32_GR:
1878 args[0] = lp_build_const_int32(base->gallivm, 0x3); /* writemask */
1879 args[5] = values[0];
1880 args[6] = values[1];
1881 break;
1882
1883 case V_028714_SPI_SHADER_32_AR:
1884 args[0] = lp_build_const_int32(base->gallivm, 0x9); /* writemask */
1885 args[5] = values[0];
1886 args[8] = values[3];
1887 break;
1888
1889 case V_028714_SPI_SHADER_FP16_ABGR:
1890 args[4] = uint->one; /* COMPR flag */
1891
1892 for (chan = 0; chan < 2; chan++) {
1893 LLVMValueRef pack_args[2] = {
1894 values[2 * chan],
1895 values[2 * chan + 1]
1896 };
1897 LLVMValueRef packed;
1898
1899 packed = lp_build_intrinsic(base->gallivm->builder,
1900 "llvm.SI.packf16",
1901 ctx->i32, pack_args, 2,
1902 LP_FUNC_ATTR_READNONE);
1903 args[chan + 5] =
1904 LLVMBuildBitCast(base->gallivm->builder,
1905 packed, ctx->f32, "");
1906 }
1907 break;
1908
1909 case V_028714_SPI_SHADER_UNORM16_ABGR:
1910 for (chan = 0; chan < 4; chan++) {
1911 val[chan] = si_llvm_saturate(bld_base, values[chan]);
1912 val[chan] = LLVMBuildFMul(builder, val[chan],
1913 lp_build_const_float(gallivm, 65535), "");
1914 val[chan] = LLVMBuildFAdd(builder, val[chan],
1915 lp_build_const_float(gallivm, 0.5), "");
1916 val[chan] = LLVMBuildFPToUI(builder, val[chan],
1917 ctx->i32, "");
1918 }
1919
1920 args[4] = uint->one; /* COMPR flag */
1921 args[5] = bitcast(bld_base, TGSI_TYPE_FLOAT,
1922 si_llvm_pack_two_int16(gallivm, val));
1923 args[6] = bitcast(bld_base, TGSI_TYPE_FLOAT,
1924 si_llvm_pack_two_int16(gallivm, val+2));
1925 break;
1926
1927 case V_028714_SPI_SHADER_SNORM16_ABGR:
1928 for (chan = 0; chan < 4; chan++) {
1929 /* Clamp between [-1, 1]. */
1930 val[chan] = lp_build_emit_llvm_binary(bld_base, TGSI_OPCODE_MIN,
1931 values[chan],
1932 lp_build_const_float(gallivm, 1));
1933 val[chan] = lp_build_emit_llvm_binary(bld_base, TGSI_OPCODE_MAX,
1934 val[chan],
1935 lp_build_const_float(gallivm, -1));
1936 /* Convert to a signed integer in [-32767, 32767]. */
1937 val[chan] = LLVMBuildFMul(builder, val[chan],
1938 lp_build_const_float(gallivm, 32767), "");
1939 /* If positive, add 0.5, else add -0.5. */
1940 val[chan] = LLVMBuildFAdd(builder, val[chan],
1941 LLVMBuildSelect(builder,
1942 LLVMBuildFCmp(builder, LLVMRealOGE,
1943 val[chan], base->zero, ""),
1944 lp_build_const_float(gallivm, 0.5),
1945 lp_build_const_float(gallivm, -0.5), ""), "");
1946 val[chan] = LLVMBuildFPToSI(builder, val[chan], ctx->i32, "");
1947 }
1948
1949 args[4] = uint->one; /* COMPR flag */
1950 args[5] = bitcast(bld_base, TGSI_TYPE_FLOAT,
1951 si_llvm_pack_two_int32_as_int16(gallivm, val));
1952 args[6] = bitcast(bld_base, TGSI_TYPE_FLOAT,
1953 si_llvm_pack_two_int32_as_int16(gallivm, val+2));
1954 break;
1955
1956 case V_028714_SPI_SHADER_UINT16_ABGR: {
1957 LLVMValueRef max = lp_build_const_int32(gallivm, is_int8 ?
1958 255 : 65535);
1959 /* Clamp. */
1960 for (chan = 0; chan < 4; chan++) {
1961 val[chan] = bitcast(bld_base, TGSI_TYPE_UNSIGNED, values[chan]);
1962 val[chan] = lp_build_emit_llvm_binary(bld_base, TGSI_OPCODE_UMIN,
1963 val[chan], max);
1964 }
1965
1966 args[4] = uint->one; /* COMPR flag */
1967 args[5] = bitcast(bld_base, TGSI_TYPE_FLOAT,
1968 si_llvm_pack_two_int16(gallivm, val));
1969 args[6] = bitcast(bld_base, TGSI_TYPE_FLOAT,
1970 si_llvm_pack_two_int16(gallivm, val+2));
1971 break;
1972 }
1973
1974 case V_028714_SPI_SHADER_SINT16_ABGR: {
1975 LLVMValueRef max = lp_build_const_int32(gallivm, is_int8 ?
1976 127 : 32767);
1977 LLVMValueRef min = lp_build_const_int32(gallivm, is_int8 ?
1978 -128 : -32768);
1979 /* Clamp. */
1980 for (chan = 0; chan < 4; chan++) {
1981 val[chan] = bitcast(bld_base, TGSI_TYPE_UNSIGNED, values[chan]);
1982 val[chan] = lp_build_emit_llvm_binary(bld_base,
1983 TGSI_OPCODE_IMIN,
1984 val[chan], max);
1985 val[chan] = lp_build_emit_llvm_binary(bld_base,
1986 TGSI_OPCODE_IMAX,
1987 val[chan], min);
1988 }
1989
1990 args[4] = uint->one; /* COMPR flag */
1991 args[5] = bitcast(bld_base, TGSI_TYPE_FLOAT,
1992 si_llvm_pack_two_int32_as_int16(gallivm, val));
1993 args[6] = bitcast(bld_base, TGSI_TYPE_FLOAT,
1994 si_llvm_pack_two_int32_as_int16(gallivm, val+2));
1995 break;
1996 }
1997
1998 case V_028714_SPI_SHADER_32_ABGR:
1999 memcpy(&args[5], values, sizeof(values[0]) * 4);
2000 break;
2001 }
2002 }
2003
2004 static void si_alpha_test(struct lp_build_tgsi_context *bld_base,
2005 LLVMValueRef alpha)
2006 {
2007 struct si_shader_context *ctx = si_shader_context(bld_base);
2008 struct gallivm_state *gallivm = bld_base->base.gallivm;
2009
2010 if (ctx->shader->key.part.ps.epilog.alpha_func != PIPE_FUNC_NEVER) {
2011 LLVMValueRef alpha_ref = LLVMGetParam(ctx->main_fn,
2012 SI_PARAM_ALPHA_REF);
2013
2014 LLVMValueRef alpha_pass =
2015 lp_build_cmp(&bld_base->base,
2016 ctx->shader->key.part.ps.epilog.alpha_func,
2017 alpha, alpha_ref);
2018 LLVMValueRef arg =
2019 lp_build_select(&bld_base->base,
2020 alpha_pass,
2021 lp_build_const_float(gallivm, 1.0f),
2022 lp_build_const_float(gallivm, -1.0f));
2023
2024 lp_build_intrinsic(gallivm->builder, "llvm.AMDGPU.kill",
2025 ctx->voidt, &arg, 1, 0);
2026 } else {
2027 lp_build_intrinsic(gallivm->builder, "llvm.AMDGPU.kilp",
2028 ctx->voidt, NULL, 0, 0);
2029 }
2030 }
2031
2032 static LLVMValueRef si_scale_alpha_by_sample_mask(struct lp_build_tgsi_context *bld_base,
2033 LLVMValueRef alpha,
2034 unsigned samplemask_param)
2035 {
2036 struct si_shader_context *ctx = si_shader_context(bld_base);
2037 struct gallivm_state *gallivm = bld_base->base.gallivm;
2038 LLVMValueRef coverage;
2039
2040 /* alpha = alpha * popcount(coverage) / SI_NUM_SMOOTH_AA_SAMPLES */
2041 coverage = LLVMGetParam(ctx->main_fn,
2042 samplemask_param);
2043 coverage = bitcast(bld_base, TGSI_TYPE_SIGNED, coverage);
2044
2045 coverage = lp_build_intrinsic(gallivm->builder, "llvm.ctpop.i32",
2046 ctx->i32,
2047 &coverage, 1, LP_FUNC_ATTR_READNONE);
2048
2049 coverage = LLVMBuildUIToFP(gallivm->builder, coverage,
2050 ctx->f32, "");
2051
2052 coverage = LLVMBuildFMul(gallivm->builder, coverage,
2053 lp_build_const_float(gallivm,
2054 1.0 / SI_NUM_SMOOTH_AA_SAMPLES), "");
2055
2056 return LLVMBuildFMul(gallivm->builder, alpha, coverage, "");
2057 }
2058
2059 static void si_llvm_emit_clipvertex(struct lp_build_tgsi_context *bld_base,
2060 LLVMValueRef (*pos)[9], LLVMValueRef *out_elts)
2061 {
2062 struct si_shader_context *ctx = si_shader_context(bld_base);
2063 struct lp_build_context *base = &bld_base->base;
2064 struct lp_build_context *uint = &ctx->soa.bld_base.uint_bld;
2065 unsigned reg_index;
2066 unsigned chan;
2067 unsigned const_chan;
2068 LLVMValueRef base_elt;
2069 LLVMValueRef ptr = LLVMGetParam(ctx->main_fn, SI_PARAM_RW_BUFFERS);
2070 LLVMValueRef constbuf_index = lp_build_const_int32(base->gallivm,
2071 SI_VS_CONST_CLIP_PLANES);
2072 LLVMValueRef const_resource = build_indexed_load_const(ctx, ptr, constbuf_index);
2073
2074 for (reg_index = 0; reg_index < 2; reg_index ++) {
2075 LLVMValueRef *args = pos[2 + reg_index];
2076
2077 args[5] =
2078 args[6] =
2079 args[7] =
2080 args[8] = lp_build_const_float(base->gallivm, 0.0f);
2081
2082 /* Compute dot products of position and user clip plane vectors */
2083 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2084 for (const_chan = 0; const_chan < TGSI_NUM_CHANNELS; const_chan++) {
2085 args[1] = lp_build_const_int32(base->gallivm,
2086 ((reg_index * 4 + chan) * 4 +
2087 const_chan) * 4);
2088 base_elt = buffer_load_const(ctx, const_resource,
2089 args[1]);
2090 args[5 + chan] =
2091 lp_build_add(base, args[5 + chan],
2092 lp_build_mul(base, base_elt,
2093 out_elts[const_chan]));
2094 }
2095 }
2096
2097 args[0] = lp_build_const_int32(base->gallivm, 0xf);
2098 args[1] = uint->zero;
2099 args[2] = uint->zero;
2100 args[3] = lp_build_const_int32(base->gallivm,
2101 V_008DFC_SQ_EXP_POS + 2 + reg_index);
2102 args[4] = uint->zero;
2103 }
2104 }
2105
2106 static void si_dump_streamout(struct pipe_stream_output_info *so)
2107 {
2108 unsigned i;
2109
2110 if (so->num_outputs)
2111 fprintf(stderr, "STREAMOUT\n");
2112
2113 for (i = 0; i < so->num_outputs; i++) {
2114 unsigned mask = ((1 << so->output[i].num_components) - 1) <<
2115 so->output[i].start_component;
2116 fprintf(stderr, " %i: BUF%i[%i..%i] <- OUT[%i].%s%s%s%s\n",
2117 i, so->output[i].output_buffer,
2118 so->output[i].dst_offset, so->output[i].dst_offset + so->output[i].num_components - 1,
2119 so->output[i].register_index,
2120 mask & 1 ? "x" : "",
2121 mask & 2 ? "y" : "",
2122 mask & 4 ? "z" : "",
2123 mask & 8 ? "w" : "");
2124 }
2125 }
2126
2127 /* On SI, the vertex shader is responsible for writing streamout data
2128 * to buffers. */
2129 static void si_llvm_emit_streamout(struct si_shader_context *ctx,
2130 struct si_shader_output_values *outputs,
2131 unsigned noutput)
2132 {
2133 struct pipe_stream_output_info *so = &ctx->shader->selector->so;
2134 struct gallivm_state *gallivm = &ctx->gallivm;
2135 LLVMBuilderRef builder = gallivm->builder;
2136 int i, j;
2137 struct lp_build_if_state if_ctx;
2138 LLVMValueRef so_buffers[4];
2139 LLVMValueRef buf_ptr = LLVMGetParam(ctx->main_fn,
2140 SI_PARAM_RW_BUFFERS);
2141
2142 /* Load the descriptors. */
2143 for (i = 0; i < 4; ++i) {
2144 if (ctx->shader->selector->so.stride[i]) {
2145 LLVMValueRef offset = lp_build_const_int32(gallivm,
2146 SI_VS_STREAMOUT_BUF0 + i);
2147
2148 so_buffers[i] = build_indexed_load_const(ctx, buf_ptr, offset);
2149 }
2150 }
2151
2152 /* Get bits [22:16], i.e. (so_param >> 16) & 127; */
2153 LLVMValueRef so_vtx_count =
2154 unpack_param(ctx, ctx->param_streamout_config, 16, 7);
2155
2156 LLVMValueRef tid = get_thread_id(ctx);
2157
2158 /* can_emit = tid < so_vtx_count; */
2159 LLVMValueRef can_emit =
2160 LLVMBuildICmp(builder, LLVMIntULT, tid, so_vtx_count, "");
2161
2162 LLVMValueRef stream_id =
2163 unpack_param(ctx, ctx->param_streamout_config, 24, 2);
2164
2165 /* Emit the streamout code conditionally. This actually avoids
2166 * out-of-bounds buffer access. The hw tells us via the SGPR
2167 * (so_vtx_count) which threads are allowed to emit streamout data. */
2168 lp_build_if(&if_ctx, gallivm, can_emit);
2169 {
2170 /* The buffer offset is computed as follows:
2171 * ByteOffset = streamout_offset[buffer_id]*4 +
2172 * (streamout_write_index + thread_id)*stride[buffer_id] +
2173 * attrib_offset
2174 */
2175
2176 LLVMValueRef so_write_index =
2177 LLVMGetParam(ctx->main_fn,
2178 ctx->param_streamout_write_index);
2179
2180 /* Compute (streamout_write_index + thread_id). */
2181 so_write_index = LLVMBuildAdd(builder, so_write_index, tid, "");
2182
2183 /* Compute the write offset for each enabled buffer. */
2184 LLVMValueRef so_write_offset[4] = {};
2185 for (i = 0; i < 4; i++) {
2186 if (!so->stride[i])
2187 continue;
2188
2189 LLVMValueRef so_offset = LLVMGetParam(ctx->main_fn,
2190 ctx->param_streamout_offset[i]);
2191 so_offset = LLVMBuildMul(builder, so_offset, LLVMConstInt(ctx->i32, 4, 0), "");
2192
2193 so_write_offset[i] = LLVMBuildMul(builder, so_write_index,
2194 LLVMConstInt(ctx->i32, so->stride[i]*4, 0), "");
2195 so_write_offset[i] = LLVMBuildAdd(builder, so_write_offset[i], so_offset, "");
2196 }
2197
2198 /* Write streamout data. */
2199 for (i = 0; i < so->num_outputs; i++) {
2200 unsigned buf_idx = so->output[i].output_buffer;
2201 unsigned reg = so->output[i].register_index;
2202 unsigned start = so->output[i].start_component;
2203 unsigned num_comps = so->output[i].num_components;
2204 unsigned stream = so->output[i].stream;
2205 LLVMValueRef out[4];
2206 struct lp_build_if_state if_ctx_stream;
2207
2208 assert(num_comps && num_comps <= 4);
2209 if (!num_comps || num_comps > 4)
2210 continue;
2211
2212 if (reg >= noutput)
2213 continue;
2214
2215 /* Load the output as int. */
2216 for (j = 0; j < num_comps; j++) {
2217 out[j] = LLVMBuildBitCast(builder,
2218 outputs[reg].values[start+j],
2219 ctx->i32, "");
2220 }
2221
2222 /* Pack the output. */
2223 LLVMValueRef vdata = NULL;
2224
2225 switch (num_comps) {
2226 case 1: /* as i32 */
2227 vdata = out[0];
2228 break;
2229 case 2: /* as v2i32 */
2230 case 3: /* as v4i32 (aligned to 4) */
2231 case 4: /* as v4i32 */
2232 vdata = LLVMGetUndef(LLVMVectorType(ctx->i32, util_next_power_of_two(num_comps)));
2233 for (j = 0; j < num_comps; j++) {
2234 vdata = LLVMBuildInsertElement(builder, vdata, out[j],
2235 LLVMConstInt(ctx->i32, j, 0), "");
2236 }
2237 break;
2238 }
2239
2240 LLVMValueRef can_emit_stream =
2241 LLVMBuildICmp(builder, LLVMIntEQ,
2242 stream_id,
2243 lp_build_const_int32(gallivm, stream), "");
2244
2245 lp_build_if(&if_ctx_stream, gallivm, can_emit_stream);
2246 build_tbuffer_store_dwords(ctx, so_buffers[buf_idx],
2247 vdata, num_comps,
2248 so_write_offset[buf_idx],
2249 LLVMConstInt(ctx->i32, 0, 0),
2250 so->output[i].dst_offset*4);
2251 lp_build_endif(&if_ctx_stream);
2252 }
2253 }
2254 lp_build_endif(&if_ctx);
2255 }
2256
2257
2258 /* Generate export instructions for hardware VS shader stage */
2259 static void si_llvm_export_vs(struct lp_build_tgsi_context *bld_base,
2260 struct si_shader_output_values *outputs,
2261 unsigned noutput)
2262 {
2263 struct si_shader_context *ctx = si_shader_context(bld_base);
2264 struct si_shader *shader = ctx->shader;
2265 struct lp_build_context *base = &bld_base->base;
2266 struct lp_build_context *uint =
2267 &ctx->soa.bld_base.uint_bld;
2268 LLVMValueRef args[9];
2269 LLVMValueRef pos_args[4][9] = { { 0 } };
2270 LLVMValueRef psize_value = NULL, edgeflag_value = NULL, layer_value = NULL, viewport_index_value = NULL;
2271 unsigned semantic_name, semantic_index;
2272 unsigned target;
2273 unsigned param_count = 0;
2274 unsigned pos_idx;
2275 int i;
2276
2277 if (outputs && ctx->shader->selector->so.num_outputs) {
2278 si_llvm_emit_streamout(ctx, outputs, noutput);
2279 }
2280
2281 for (i = 0; i < noutput; i++) {
2282 semantic_name = outputs[i].name;
2283 semantic_index = outputs[i].sid;
2284 bool export_param = true;
2285
2286 switch (semantic_name) {
2287 case TGSI_SEMANTIC_POSITION: /* ignore these */
2288 case TGSI_SEMANTIC_PSIZE:
2289 case TGSI_SEMANTIC_CLIPVERTEX:
2290 case TGSI_SEMANTIC_EDGEFLAG:
2291 break;
2292 case TGSI_SEMANTIC_GENERIC:
2293 case TGSI_SEMANTIC_CLIPDIST:
2294 if (shader->key.opt.hw_vs.kill_outputs &
2295 (1ull << si_shader_io_get_unique_index(semantic_name, semantic_index)))
2296 export_param = false;
2297 break;
2298 default:
2299 if (shader->key.opt.hw_vs.kill_outputs2 &
2300 (1u << si_shader_io_get_unique_index2(semantic_name, semantic_index)))
2301 export_param = false;
2302 break;
2303 }
2304
2305 handle_semantic:
2306 /* Select the correct target */
2307 switch(semantic_name) {
2308 case TGSI_SEMANTIC_PSIZE:
2309 psize_value = outputs[i].values[0];
2310 continue;
2311 case TGSI_SEMANTIC_EDGEFLAG:
2312 edgeflag_value = outputs[i].values[0];
2313 continue;
2314 case TGSI_SEMANTIC_LAYER:
2315 layer_value = outputs[i].values[0];
2316 semantic_name = TGSI_SEMANTIC_GENERIC;
2317 goto handle_semantic;
2318 case TGSI_SEMANTIC_VIEWPORT_INDEX:
2319 viewport_index_value = outputs[i].values[0];
2320 semantic_name = TGSI_SEMANTIC_GENERIC;
2321 goto handle_semantic;
2322 case TGSI_SEMANTIC_POSITION:
2323 target = V_008DFC_SQ_EXP_POS;
2324 break;
2325 case TGSI_SEMANTIC_COLOR:
2326 case TGSI_SEMANTIC_BCOLOR:
2327 if (!export_param)
2328 continue;
2329 target = V_008DFC_SQ_EXP_PARAM + param_count;
2330 assert(i < ARRAY_SIZE(shader->info.vs_output_param_offset));
2331 shader->info.vs_output_param_offset[i] = param_count;
2332 param_count++;
2333 break;
2334 case TGSI_SEMANTIC_CLIPDIST:
2335 if (shader->key.opt.hw_vs.clip_disable) {
2336 semantic_name = TGSI_SEMANTIC_GENERIC;
2337 goto handle_semantic;
2338 }
2339 target = V_008DFC_SQ_EXP_POS + 2 + semantic_index;
2340 break;
2341 case TGSI_SEMANTIC_CLIPVERTEX:
2342 if (shader->key.opt.hw_vs.clip_disable)
2343 continue;
2344 si_llvm_emit_clipvertex(bld_base, pos_args, outputs[i].values);
2345 continue;
2346 case TGSI_SEMANTIC_PRIMID:
2347 case TGSI_SEMANTIC_FOG:
2348 case TGSI_SEMANTIC_TEXCOORD:
2349 case TGSI_SEMANTIC_GENERIC:
2350 if (!export_param)
2351 continue;
2352 target = V_008DFC_SQ_EXP_PARAM + param_count;
2353 assert(i < ARRAY_SIZE(shader->info.vs_output_param_offset));
2354 shader->info.vs_output_param_offset[i] = param_count;
2355 param_count++;
2356 break;
2357 default:
2358 target = 0;
2359 fprintf(stderr,
2360 "Warning: SI unhandled vs output type:%d\n",
2361 semantic_name);
2362 }
2363
2364 si_llvm_init_export_args(bld_base, outputs[i].values, target, args);
2365
2366 if (target >= V_008DFC_SQ_EXP_POS &&
2367 target <= (V_008DFC_SQ_EXP_POS + 3)) {
2368 memcpy(pos_args[target - V_008DFC_SQ_EXP_POS],
2369 args, sizeof(args));
2370 } else {
2371 lp_build_intrinsic(base->gallivm->builder,
2372 "llvm.SI.export", ctx->voidt,
2373 args, 9, 0);
2374 }
2375
2376 if (semantic_name == TGSI_SEMANTIC_CLIPDIST) {
2377 semantic_name = TGSI_SEMANTIC_GENERIC;
2378 goto handle_semantic;
2379 }
2380 }
2381
2382 shader->info.nr_param_exports = param_count;
2383
2384 /* We need to add the position output manually if it's missing. */
2385 if (!pos_args[0][0]) {
2386 pos_args[0][0] = lp_build_const_int32(base->gallivm, 0xf); /* writemask */
2387 pos_args[0][1] = uint->zero; /* EXEC mask */
2388 pos_args[0][2] = uint->zero; /* last export? */
2389 pos_args[0][3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_POS);
2390 pos_args[0][4] = uint->zero; /* COMPR flag */
2391 pos_args[0][5] = base->zero; /* X */
2392 pos_args[0][6] = base->zero; /* Y */
2393 pos_args[0][7] = base->zero; /* Z */
2394 pos_args[0][8] = base->one; /* W */
2395 }
2396
2397 /* Write the misc vector (point size, edgeflag, layer, viewport). */
2398 if (shader->selector->info.writes_psize ||
2399 shader->selector->info.writes_edgeflag ||
2400 shader->selector->info.writes_viewport_index ||
2401 shader->selector->info.writes_layer) {
2402 pos_args[1][0] = lp_build_const_int32(base->gallivm, /* writemask */
2403 shader->selector->info.writes_psize |
2404 (shader->selector->info.writes_edgeflag << 1) |
2405 (shader->selector->info.writes_layer << 2) |
2406 (shader->selector->info.writes_viewport_index << 3));
2407 pos_args[1][1] = uint->zero; /* EXEC mask */
2408 pos_args[1][2] = uint->zero; /* last export? */
2409 pos_args[1][3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_POS + 1);
2410 pos_args[1][4] = uint->zero; /* COMPR flag */
2411 pos_args[1][5] = base->zero; /* X */
2412 pos_args[1][6] = base->zero; /* Y */
2413 pos_args[1][7] = base->zero; /* Z */
2414 pos_args[1][8] = base->zero; /* W */
2415
2416 if (shader->selector->info.writes_psize)
2417 pos_args[1][5] = psize_value;
2418
2419 if (shader->selector->info.writes_edgeflag) {
2420 /* The output is a float, but the hw expects an integer
2421 * with the first bit containing the edge flag. */
2422 edgeflag_value = LLVMBuildFPToUI(base->gallivm->builder,
2423 edgeflag_value,
2424 ctx->i32, "");
2425 edgeflag_value = lp_build_min(&bld_base->int_bld,
2426 edgeflag_value,
2427 bld_base->int_bld.one);
2428
2429 /* The LLVM intrinsic expects a float. */
2430 pos_args[1][6] = LLVMBuildBitCast(base->gallivm->builder,
2431 edgeflag_value,
2432 ctx->f32, "");
2433 }
2434
2435 if (shader->selector->info.writes_layer)
2436 pos_args[1][7] = layer_value;
2437
2438 if (shader->selector->info.writes_viewport_index)
2439 pos_args[1][8] = viewport_index_value;
2440 }
2441
2442 for (i = 0; i < 4; i++)
2443 if (pos_args[i][0])
2444 shader->info.nr_pos_exports++;
2445
2446 pos_idx = 0;
2447 for (i = 0; i < 4; i++) {
2448 if (!pos_args[i][0])
2449 continue;
2450
2451 /* Specify the target we are exporting */
2452 pos_args[i][3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_POS + pos_idx++);
2453
2454 if (pos_idx == shader->info.nr_pos_exports)
2455 /* Specify that this is the last export */
2456 pos_args[i][2] = uint->one;
2457
2458 lp_build_intrinsic(base->gallivm->builder, "llvm.SI.export",
2459 ctx->voidt, pos_args[i], 9, 0);
2460 }
2461 }
2462
2463 /**
2464 * Forward all outputs from the vertex shader to the TES. This is only used
2465 * for the fixed function TCS.
2466 */
2467 static void si_copy_tcs_inputs(struct lp_build_tgsi_context *bld_base)
2468 {
2469 struct si_shader_context *ctx = si_shader_context(bld_base);
2470 struct gallivm_state *gallivm = bld_base->base.gallivm;
2471 LLVMValueRef invocation_id, rw_buffers, buffer, buffer_offset;
2472 LLVMValueRef lds_vertex_stride, lds_vertex_offset, lds_base;
2473 uint64_t inputs;
2474
2475 invocation_id = unpack_param(ctx, SI_PARAM_REL_IDS, 8, 5);
2476
2477 rw_buffers = LLVMGetParam(ctx->main_fn, SI_PARAM_RW_BUFFERS);
2478 buffer = build_indexed_load_const(ctx, rw_buffers,
2479 lp_build_const_int32(gallivm, SI_HS_RING_TESS_OFFCHIP));
2480
2481 buffer_offset = LLVMGetParam(ctx->main_fn, ctx->param_oc_lds);
2482
2483 lds_vertex_stride = unpack_param(ctx, SI_PARAM_TCS_IN_LAYOUT, 13, 8);
2484 lds_vertex_offset = LLVMBuildMul(gallivm->builder, invocation_id,
2485 lds_vertex_stride, "");
2486 lds_base = get_tcs_in_current_patch_offset(ctx);
2487 lds_base = LLVMBuildAdd(gallivm->builder, lds_base, lds_vertex_offset, "");
2488
2489 inputs = ctx->shader->key.mono.tcs.inputs_to_copy;
2490 while (inputs) {
2491 unsigned i = u_bit_scan64(&inputs);
2492
2493 LLVMValueRef lds_ptr = LLVMBuildAdd(gallivm->builder, lds_base,
2494 lp_build_const_int32(gallivm, 4 * i),
2495 "");
2496
2497 LLVMValueRef buffer_addr = get_tcs_tes_buffer_address(ctx,
2498 invocation_id,
2499 lp_build_const_int32(gallivm, i));
2500
2501 LLVMValueRef value = lds_load(bld_base, TGSI_TYPE_SIGNED, ~0,
2502 lds_ptr);
2503
2504 build_tbuffer_store_dwords(ctx, buffer, value, 4, buffer_addr,
2505 buffer_offset, 0);
2506 }
2507 }
2508
2509 static void si_write_tess_factors(struct lp_build_tgsi_context *bld_base,
2510 LLVMValueRef rel_patch_id,
2511 LLVMValueRef invocation_id,
2512 LLVMValueRef tcs_out_current_patch_data_offset)
2513 {
2514 struct si_shader_context *ctx = si_shader_context(bld_base);
2515 struct gallivm_state *gallivm = bld_base->base.gallivm;
2516 struct si_shader *shader = ctx->shader;
2517 unsigned tess_inner_index, tess_outer_index;
2518 LLVMValueRef lds_base, lds_inner, lds_outer, byteoffset, buffer;
2519 LLVMValueRef out[6], vec0, vec1, rw_buffers, tf_base;
2520 unsigned stride, outer_comps, inner_comps, i;
2521 struct lp_build_if_state if_ctx, inner_if_ctx;
2522
2523 si_llvm_emit_barrier(NULL, bld_base, NULL);
2524
2525 /* Do this only for invocation 0, because the tess levels are per-patch,
2526 * not per-vertex.
2527 *
2528 * This can't jump, because invocation 0 executes this. It should
2529 * at least mask out the loads and stores for other invocations.
2530 */
2531 lp_build_if(&if_ctx, gallivm,
2532 LLVMBuildICmp(gallivm->builder, LLVMIntEQ,
2533 invocation_id, bld_base->uint_bld.zero, ""));
2534
2535 /* Determine the layout of one tess factor element in the buffer. */
2536 switch (shader->key.part.tcs.epilog.prim_mode) {
2537 case PIPE_PRIM_LINES:
2538 stride = 2; /* 2 dwords, 1 vec2 store */
2539 outer_comps = 2;
2540 inner_comps = 0;
2541 break;
2542 case PIPE_PRIM_TRIANGLES:
2543 stride = 4; /* 4 dwords, 1 vec4 store */
2544 outer_comps = 3;
2545 inner_comps = 1;
2546 break;
2547 case PIPE_PRIM_QUADS:
2548 stride = 6; /* 6 dwords, 2 stores (vec4 + vec2) */
2549 outer_comps = 4;
2550 inner_comps = 2;
2551 break;
2552 default:
2553 assert(0);
2554 return;
2555 }
2556
2557 /* Load tess_inner and tess_outer from LDS.
2558 * Any invocation can write them, so we can't get them from a temporary.
2559 */
2560 tess_inner_index = si_shader_io_get_unique_index(TGSI_SEMANTIC_TESSINNER, 0);
2561 tess_outer_index = si_shader_io_get_unique_index(TGSI_SEMANTIC_TESSOUTER, 0);
2562
2563 lds_base = tcs_out_current_patch_data_offset;
2564 lds_inner = LLVMBuildAdd(gallivm->builder, lds_base,
2565 lp_build_const_int32(gallivm,
2566 tess_inner_index * 4), "");
2567 lds_outer = LLVMBuildAdd(gallivm->builder, lds_base,
2568 lp_build_const_int32(gallivm,
2569 tess_outer_index * 4), "");
2570
2571 for (i = 0; i < outer_comps; i++)
2572 out[i] = lds_load(bld_base, TGSI_TYPE_SIGNED, i, lds_outer);
2573 for (i = 0; i < inner_comps; i++)
2574 out[outer_comps+i] = lds_load(bld_base, TGSI_TYPE_SIGNED, i, lds_inner);
2575
2576 /* Convert the outputs to vectors for stores. */
2577 vec0 = lp_build_gather_values(gallivm, out, MIN2(stride, 4));
2578 vec1 = NULL;
2579
2580 if (stride > 4)
2581 vec1 = lp_build_gather_values(gallivm, out+4, stride - 4);
2582
2583 /* Get the buffer. */
2584 rw_buffers = LLVMGetParam(ctx->main_fn,
2585 SI_PARAM_RW_BUFFERS);
2586 buffer = build_indexed_load_const(ctx, rw_buffers,
2587 lp_build_const_int32(gallivm, SI_HS_RING_TESS_FACTOR));
2588
2589 /* Get the offset. */
2590 tf_base = LLVMGetParam(ctx->main_fn,
2591 SI_PARAM_TESS_FACTOR_OFFSET);
2592 byteoffset = LLVMBuildMul(gallivm->builder, rel_patch_id,
2593 lp_build_const_int32(gallivm, 4 * stride), "");
2594
2595 lp_build_if(&inner_if_ctx, gallivm,
2596 LLVMBuildICmp(gallivm->builder, LLVMIntEQ,
2597 rel_patch_id, bld_base->uint_bld.zero, ""));
2598
2599 /* Store the dynamic HS control word. */
2600 build_tbuffer_store_dwords(ctx, buffer,
2601 lp_build_const_int32(gallivm, 0x80000000),
2602 1, lp_build_const_int32(gallivm, 0), tf_base, 0);
2603
2604 lp_build_endif(&inner_if_ctx);
2605
2606 /* Store the tessellation factors. */
2607 build_tbuffer_store_dwords(ctx, buffer, vec0,
2608 MIN2(stride, 4), byteoffset, tf_base, 4);
2609 if (vec1)
2610 build_tbuffer_store_dwords(ctx, buffer, vec1,
2611 stride - 4, byteoffset, tf_base, 20);
2612 lp_build_endif(&if_ctx);
2613 }
2614
2615 /* This only writes the tessellation factor levels. */
2616 static void si_llvm_emit_tcs_epilogue(struct lp_build_tgsi_context *bld_base)
2617 {
2618 struct si_shader_context *ctx = si_shader_context(bld_base);
2619 LLVMValueRef rel_patch_id, invocation_id, tf_lds_offset;
2620
2621 si_copy_tcs_inputs(bld_base);
2622
2623 rel_patch_id = get_rel_patch_id(ctx);
2624 invocation_id = unpack_param(ctx, SI_PARAM_REL_IDS, 8, 5);
2625 tf_lds_offset = get_tcs_out_current_patch_data_offset(ctx);
2626
2627 /* Return epilog parameters from this function. */
2628 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
2629 LLVMValueRef ret = ctx->return_value;
2630 LLVMValueRef rw_buffers, rw0, rw1, tf_soffset;
2631 unsigned vgpr;
2632
2633 /* RW_BUFFERS pointer */
2634 rw_buffers = LLVMGetParam(ctx->main_fn,
2635 SI_PARAM_RW_BUFFERS);
2636 rw_buffers = LLVMBuildPtrToInt(builder, rw_buffers, ctx->i64, "");
2637 rw_buffers = LLVMBuildBitCast(builder, rw_buffers, ctx->v2i32, "");
2638 rw0 = LLVMBuildExtractElement(builder, rw_buffers,
2639 bld_base->uint_bld.zero, "");
2640 rw1 = LLVMBuildExtractElement(builder, rw_buffers,
2641 bld_base->uint_bld.one, "");
2642 ret = LLVMBuildInsertValue(builder, ret, rw0, 0, "");
2643 ret = LLVMBuildInsertValue(builder, ret, rw1, 1, "");
2644
2645 /* Tess factor buffer soffset is after user SGPRs. */
2646 tf_soffset = LLVMGetParam(ctx->main_fn,
2647 SI_PARAM_TESS_FACTOR_OFFSET);
2648 ret = LLVMBuildInsertValue(builder, ret, tf_soffset,
2649 SI_TCS_NUM_USER_SGPR + 1, "");
2650
2651 /* VGPRs */
2652 rel_patch_id = bitcast(bld_base, TGSI_TYPE_FLOAT, rel_patch_id);
2653 invocation_id = bitcast(bld_base, TGSI_TYPE_FLOAT, invocation_id);
2654 tf_lds_offset = bitcast(bld_base, TGSI_TYPE_FLOAT, tf_lds_offset);
2655
2656 vgpr = SI_TCS_NUM_USER_SGPR + 2;
2657 ret = LLVMBuildInsertValue(builder, ret, rel_patch_id, vgpr++, "");
2658 ret = LLVMBuildInsertValue(builder, ret, invocation_id, vgpr++, "");
2659 ret = LLVMBuildInsertValue(builder, ret, tf_lds_offset, vgpr++, "");
2660 ctx->return_value = ret;
2661 }
2662
2663 static void si_llvm_emit_ls_epilogue(struct lp_build_tgsi_context *bld_base)
2664 {
2665 struct si_shader_context *ctx = si_shader_context(bld_base);
2666 struct si_shader *shader = ctx->shader;
2667 struct tgsi_shader_info *info = &shader->selector->info;
2668 struct gallivm_state *gallivm = bld_base->base.gallivm;
2669 unsigned i, chan;
2670 LLVMValueRef vertex_id = LLVMGetParam(ctx->main_fn,
2671 ctx->param_rel_auto_id);
2672 LLVMValueRef vertex_dw_stride =
2673 unpack_param(ctx, SI_PARAM_LS_OUT_LAYOUT, 13, 8);
2674 LLVMValueRef base_dw_addr = LLVMBuildMul(gallivm->builder, vertex_id,
2675 vertex_dw_stride, "");
2676
2677 /* Write outputs to LDS. The next shader (TCS aka HS) will read
2678 * its inputs from it. */
2679 for (i = 0; i < info->num_outputs; i++) {
2680 LLVMValueRef *out_ptr = ctx->soa.outputs[i];
2681 unsigned name = info->output_semantic_name[i];
2682 unsigned index = info->output_semantic_index[i];
2683 int param = si_shader_io_get_unique_index(name, index);
2684 LLVMValueRef dw_addr = LLVMBuildAdd(gallivm->builder, base_dw_addr,
2685 lp_build_const_int32(gallivm, param * 4), "");
2686
2687 for (chan = 0; chan < 4; chan++) {
2688 lds_store(bld_base, chan, dw_addr,
2689 LLVMBuildLoad(gallivm->builder, out_ptr[chan], ""));
2690 }
2691 }
2692 }
2693
2694 static void si_llvm_emit_es_epilogue(struct lp_build_tgsi_context *bld_base)
2695 {
2696 struct si_shader_context *ctx = si_shader_context(bld_base);
2697 struct gallivm_state *gallivm = bld_base->base.gallivm;
2698 struct si_shader *es = ctx->shader;
2699 struct tgsi_shader_info *info = &es->selector->info;
2700 LLVMValueRef soffset = LLVMGetParam(ctx->main_fn,
2701 ctx->param_es2gs_offset);
2702 unsigned chan;
2703 int i;
2704
2705 for (i = 0; i < info->num_outputs; i++) {
2706 LLVMValueRef *out_ptr =
2707 ctx->soa.outputs[i];
2708 int param_index;
2709
2710 if (info->output_semantic_name[i] == TGSI_SEMANTIC_VIEWPORT_INDEX ||
2711 info->output_semantic_name[i] == TGSI_SEMANTIC_LAYER)
2712 continue;
2713
2714 param_index = si_shader_io_get_unique_index(info->output_semantic_name[i],
2715 info->output_semantic_index[i]);
2716
2717 for (chan = 0; chan < 4; chan++) {
2718 LLVMValueRef out_val = LLVMBuildLoad(gallivm->builder, out_ptr[chan], "");
2719 out_val = LLVMBuildBitCast(gallivm->builder, out_val, ctx->i32, "");
2720
2721 build_tbuffer_store(ctx,
2722 ctx->esgs_ring,
2723 out_val, 1,
2724 LLVMGetUndef(ctx->i32), soffset,
2725 (4 * param_index + chan) * 4,
2726 V_008F0C_BUF_DATA_FORMAT_32,
2727 V_008F0C_BUF_NUM_FORMAT_UINT,
2728 0, 0, 1, 1, 0);
2729 }
2730 }
2731 }
2732
2733 static void si_llvm_emit_gs_epilogue(struct lp_build_tgsi_context *bld_base)
2734 {
2735 struct si_shader_context *ctx = si_shader_context(bld_base);
2736 struct gallivm_state *gallivm = bld_base->base.gallivm;
2737 LLVMValueRef args[2];
2738
2739 args[0] = lp_build_const_int32(gallivm, SENDMSG_GS_OP_NOP | SENDMSG_GS_DONE);
2740 args[1] = LLVMGetParam(ctx->main_fn, SI_PARAM_GS_WAVE_ID);
2741 lp_build_intrinsic(gallivm->builder, "llvm.SI.sendmsg",
2742 ctx->voidt, args, 2, 0);
2743 }
2744
2745 static void si_llvm_emit_vs_epilogue(struct lp_build_tgsi_context *bld_base)
2746 {
2747 struct si_shader_context *ctx = si_shader_context(bld_base);
2748 struct gallivm_state *gallivm = bld_base->base.gallivm;
2749 struct tgsi_shader_info *info = &ctx->shader->selector->info;
2750 struct si_shader_output_values *outputs = NULL;
2751 int i,j;
2752
2753 assert(!ctx->shader->is_gs_copy_shader);
2754
2755 outputs = MALLOC((info->num_outputs + 1) * sizeof(outputs[0]));
2756
2757 /* Vertex color clamping.
2758 *
2759 * This uses a state constant loaded in a user data SGPR and
2760 * an IF statement is added that clamps all colors if the constant
2761 * is true.
2762 */
2763 if (ctx->type == PIPE_SHADER_VERTEX) {
2764 struct lp_build_if_state if_ctx;
2765 LLVMValueRef cond = NULL;
2766 LLVMValueRef addr, val;
2767
2768 for (i = 0; i < info->num_outputs; i++) {
2769 if (info->output_semantic_name[i] != TGSI_SEMANTIC_COLOR &&
2770 info->output_semantic_name[i] != TGSI_SEMANTIC_BCOLOR)
2771 continue;
2772
2773 /* We've found a color. */
2774 if (!cond) {
2775 /* The state is in the first bit of the user SGPR. */
2776 cond = LLVMGetParam(ctx->main_fn,
2777 SI_PARAM_VS_STATE_BITS);
2778 cond = LLVMBuildTrunc(gallivm->builder, cond,
2779 ctx->i1, "");
2780 lp_build_if(&if_ctx, gallivm, cond);
2781 }
2782
2783 for (j = 0; j < 4; j++) {
2784 addr = ctx->soa.outputs[i][j];
2785 val = LLVMBuildLoad(gallivm->builder, addr, "");
2786 val = si_llvm_saturate(bld_base, val);
2787 LLVMBuildStore(gallivm->builder, val, addr);
2788 }
2789 }
2790
2791 if (cond)
2792 lp_build_endif(&if_ctx);
2793 }
2794
2795 for (i = 0; i < info->num_outputs; i++) {
2796 outputs[i].name = info->output_semantic_name[i];
2797 outputs[i].sid = info->output_semantic_index[i];
2798
2799 for (j = 0; j < 4; j++)
2800 outputs[i].values[j] =
2801 LLVMBuildLoad(gallivm->builder,
2802 ctx->soa.outputs[i][j],
2803 "");
2804 }
2805
2806 /* Return the primitive ID from the LLVM function. */
2807 ctx->return_value =
2808 LLVMBuildInsertValue(gallivm->builder,
2809 ctx->return_value,
2810 bitcast(bld_base, TGSI_TYPE_FLOAT,
2811 get_primitive_id(bld_base, 0)),
2812 VS_EPILOG_PRIMID_LOC, "");
2813
2814 si_llvm_export_vs(bld_base, outputs, i);
2815 FREE(outputs);
2816 }
2817
2818 struct si_ps_exports {
2819 unsigned num;
2820 LLVMValueRef args[10][9];
2821 };
2822
2823 unsigned si_get_spi_shader_z_format(bool writes_z, bool writes_stencil,
2824 bool writes_samplemask)
2825 {
2826 if (writes_z) {
2827 /* Z needs 32 bits. */
2828 if (writes_samplemask)
2829 return V_028710_SPI_SHADER_32_ABGR;
2830 else if (writes_stencil)
2831 return V_028710_SPI_SHADER_32_GR;
2832 else
2833 return V_028710_SPI_SHADER_32_R;
2834 } else if (writes_stencil || writes_samplemask) {
2835 /* Both stencil and sample mask need only 16 bits. */
2836 return V_028710_SPI_SHADER_UINT16_ABGR;
2837 } else {
2838 return V_028710_SPI_SHADER_ZERO;
2839 }
2840 }
2841
2842 static void si_export_mrt_z(struct lp_build_tgsi_context *bld_base,
2843 LLVMValueRef depth, LLVMValueRef stencil,
2844 LLVMValueRef samplemask, struct si_ps_exports *exp)
2845 {
2846 struct si_shader_context *ctx = si_shader_context(bld_base);
2847 struct lp_build_context *base = &bld_base->base;
2848 struct lp_build_context *uint = &bld_base->uint_bld;
2849 LLVMValueRef args[9];
2850 unsigned mask = 0;
2851 unsigned format = si_get_spi_shader_z_format(depth != NULL,
2852 stencil != NULL,
2853 samplemask != NULL);
2854
2855 assert(depth || stencil || samplemask);
2856
2857 args[1] = uint->one; /* whether the EXEC mask is valid */
2858 args[2] = uint->one; /* DONE bit */
2859
2860 /* Specify the target we are exporting */
2861 args[3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_MRTZ);
2862
2863 args[4] = uint->zero; /* COMP flag */
2864 args[5] = base->undef; /* R, depth */
2865 args[6] = base->undef; /* G, stencil test value[0:7], stencil op value[8:15] */
2866 args[7] = base->undef; /* B, sample mask */
2867 args[8] = base->undef; /* A, alpha to mask */
2868
2869 if (format == V_028710_SPI_SHADER_UINT16_ABGR) {
2870 assert(!depth);
2871 args[4] = uint->one; /* COMPR flag */
2872
2873 if (stencil) {
2874 /* Stencil should be in X[23:16]. */
2875 stencil = bitcast(bld_base, TGSI_TYPE_UNSIGNED, stencil);
2876 stencil = LLVMBuildShl(base->gallivm->builder, stencil,
2877 LLVMConstInt(ctx->i32, 16, 0), "");
2878 args[5] = bitcast(bld_base, TGSI_TYPE_FLOAT, stencil);
2879 mask |= 0x3;
2880 }
2881 if (samplemask) {
2882 /* SampleMask should be in Y[15:0]. */
2883 args[6] = samplemask;
2884 mask |= 0xc;
2885 }
2886 } else {
2887 if (depth) {
2888 args[5] = depth;
2889 mask |= 0x1;
2890 }
2891 if (stencil) {
2892 args[6] = stencil;
2893 mask |= 0x2;
2894 }
2895 if (samplemask) {
2896 args[7] = samplemask;
2897 mask |= 0x4;
2898 }
2899 }
2900
2901 /* SI (except OLAND) has a bug that it only looks
2902 * at the X writemask component. */
2903 if (ctx->screen->b.chip_class == SI &&
2904 ctx->screen->b.family != CHIP_OLAND)
2905 mask |= 0x1;
2906
2907 /* Specify which components to enable */
2908 args[0] = lp_build_const_int32(base->gallivm, mask);
2909
2910 memcpy(exp->args[exp->num++], args, sizeof(args));
2911 }
2912
2913 static void si_export_mrt_color(struct lp_build_tgsi_context *bld_base,
2914 LLVMValueRef *color, unsigned index,
2915 unsigned samplemask_param,
2916 bool is_last, struct si_ps_exports *exp)
2917 {
2918 struct si_shader_context *ctx = si_shader_context(bld_base);
2919 struct lp_build_context *base = &bld_base->base;
2920 int i;
2921
2922 /* Clamp color */
2923 if (ctx->shader->key.part.ps.epilog.clamp_color)
2924 for (i = 0; i < 4; i++)
2925 color[i] = si_llvm_saturate(bld_base, color[i]);
2926
2927 /* Alpha to one */
2928 if (ctx->shader->key.part.ps.epilog.alpha_to_one)
2929 color[3] = base->one;
2930
2931 /* Alpha test */
2932 if (index == 0 &&
2933 ctx->shader->key.part.ps.epilog.alpha_func != PIPE_FUNC_ALWAYS)
2934 si_alpha_test(bld_base, color[3]);
2935
2936 /* Line & polygon smoothing */
2937 if (ctx->shader->key.part.ps.epilog.poly_line_smoothing)
2938 color[3] = si_scale_alpha_by_sample_mask(bld_base, color[3],
2939 samplemask_param);
2940
2941 /* If last_cbuf > 0, FS_COLOR0_WRITES_ALL_CBUFS is true. */
2942 if (ctx->shader->key.part.ps.epilog.last_cbuf > 0) {
2943 LLVMValueRef args[8][9];
2944 int c, last = -1;
2945
2946 /* Get the export arguments, also find out what the last one is. */
2947 for (c = 0; c <= ctx->shader->key.part.ps.epilog.last_cbuf; c++) {
2948 si_llvm_init_export_args(bld_base, color,
2949 V_008DFC_SQ_EXP_MRT + c, args[c]);
2950 if (args[c][0] != bld_base->uint_bld.zero)
2951 last = c;
2952 }
2953
2954 /* Emit all exports. */
2955 for (c = 0; c <= ctx->shader->key.part.ps.epilog.last_cbuf; c++) {
2956 if (is_last && last == c) {
2957 args[c][1] = bld_base->uint_bld.one; /* whether the EXEC mask is valid */
2958 args[c][2] = bld_base->uint_bld.one; /* DONE bit */
2959 } else if (args[c][0] == bld_base->uint_bld.zero)
2960 continue; /* unnecessary NULL export */
2961
2962 memcpy(exp->args[exp->num++], args[c], sizeof(args[c]));
2963 }
2964 } else {
2965 LLVMValueRef args[9];
2966
2967 /* Export */
2968 si_llvm_init_export_args(bld_base, color, V_008DFC_SQ_EXP_MRT + index,
2969 args);
2970 if (is_last) {
2971 args[1] = bld_base->uint_bld.one; /* whether the EXEC mask is valid */
2972 args[2] = bld_base->uint_bld.one; /* DONE bit */
2973 } else if (args[0] == bld_base->uint_bld.zero)
2974 return; /* unnecessary NULL export */
2975
2976 memcpy(exp->args[exp->num++], args, sizeof(args));
2977 }
2978 }
2979
2980 static void si_emit_ps_exports(struct si_shader_context *ctx,
2981 struct si_ps_exports *exp)
2982 {
2983 for (unsigned i = 0; i < exp->num; i++)
2984 lp_build_intrinsic(ctx->gallivm.builder,
2985 "llvm.SI.export", ctx->voidt,
2986 exp->args[i], 9, 0);
2987 }
2988
2989 static void si_export_null(struct lp_build_tgsi_context *bld_base)
2990 {
2991 struct si_shader_context *ctx = si_shader_context(bld_base);
2992 struct lp_build_context *base = &bld_base->base;
2993 struct lp_build_context *uint = &bld_base->uint_bld;
2994 LLVMValueRef args[9];
2995
2996 args[0] = lp_build_const_int32(base->gallivm, 0x0); /* enabled channels */
2997 args[1] = uint->one; /* whether the EXEC mask is valid */
2998 args[2] = uint->one; /* DONE bit */
2999 args[3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_NULL);
3000 args[4] = uint->zero; /* COMPR flag (0 = 32-bit export) */
3001 args[5] = base->undef; /* R */
3002 args[6] = base->undef; /* G */
3003 args[7] = base->undef; /* B */
3004 args[8] = base->undef; /* A */
3005
3006 lp_build_intrinsic(base->gallivm->builder, "llvm.SI.export",
3007 ctx->voidt, args, 9, 0);
3008 }
3009
3010 /**
3011 * Return PS outputs in this order:
3012 *
3013 * v[0:3] = color0.xyzw
3014 * v[4:7] = color1.xyzw
3015 * ...
3016 * vN+0 = Depth
3017 * vN+1 = Stencil
3018 * vN+2 = SampleMask
3019 * vN+3 = SampleMaskIn (used for OpenGL smoothing)
3020 *
3021 * The alpha-ref SGPR is returned via its original location.
3022 */
3023 static void si_llvm_return_fs_outputs(struct lp_build_tgsi_context *bld_base)
3024 {
3025 struct si_shader_context *ctx = si_shader_context(bld_base);
3026 struct si_shader *shader = ctx->shader;
3027 struct lp_build_context *base = &bld_base->base;
3028 struct tgsi_shader_info *info = &shader->selector->info;
3029 LLVMBuilderRef builder = base->gallivm->builder;
3030 unsigned i, j, first_vgpr, vgpr;
3031
3032 LLVMValueRef color[8][4] = {};
3033 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
3034 LLVMValueRef ret;
3035
3036 /* Read the output values. */
3037 for (i = 0; i < info->num_outputs; i++) {
3038 unsigned semantic_name = info->output_semantic_name[i];
3039 unsigned semantic_index = info->output_semantic_index[i];
3040
3041 switch (semantic_name) {
3042 case TGSI_SEMANTIC_COLOR:
3043 assert(semantic_index < 8);
3044 for (j = 0; j < 4; j++) {
3045 LLVMValueRef ptr = ctx->soa.outputs[i][j];
3046 LLVMValueRef result = LLVMBuildLoad(builder, ptr, "");
3047 color[semantic_index][j] = result;
3048 }
3049 break;
3050 case TGSI_SEMANTIC_POSITION:
3051 depth = LLVMBuildLoad(builder,
3052 ctx->soa.outputs[i][2], "");
3053 break;
3054 case TGSI_SEMANTIC_STENCIL:
3055 stencil = LLVMBuildLoad(builder,
3056 ctx->soa.outputs[i][1], "");
3057 break;
3058 case TGSI_SEMANTIC_SAMPLEMASK:
3059 samplemask = LLVMBuildLoad(builder,
3060 ctx->soa.outputs[i][0], "");
3061 break;
3062 default:
3063 fprintf(stderr, "Warning: SI unhandled fs output type:%d\n",
3064 semantic_name);
3065 }
3066 }
3067
3068 /* Fill the return structure. */
3069 ret = ctx->return_value;
3070
3071 /* Set SGPRs. */
3072 ret = LLVMBuildInsertValue(builder, ret,
3073 bitcast(bld_base, TGSI_TYPE_SIGNED,
3074 LLVMGetParam(ctx->main_fn,
3075 SI_PARAM_ALPHA_REF)),
3076 SI_SGPR_ALPHA_REF, "");
3077
3078 /* Set VGPRs */
3079 first_vgpr = vgpr = SI_SGPR_ALPHA_REF + 1;
3080 for (i = 0; i < ARRAY_SIZE(color); i++) {
3081 if (!color[i][0])
3082 continue;
3083
3084 for (j = 0; j < 4; j++)
3085 ret = LLVMBuildInsertValue(builder, ret, color[i][j], vgpr++, "");
3086 }
3087 if (depth)
3088 ret = LLVMBuildInsertValue(builder, ret, depth, vgpr++, "");
3089 if (stencil)
3090 ret = LLVMBuildInsertValue(builder, ret, stencil, vgpr++, "");
3091 if (samplemask)
3092 ret = LLVMBuildInsertValue(builder, ret, samplemask, vgpr++, "");
3093
3094 /* Add the input sample mask for smoothing at the end. */
3095 if (vgpr < first_vgpr + PS_EPILOG_SAMPLEMASK_MIN_LOC)
3096 vgpr = first_vgpr + PS_EPILOG_SAMPLEMASK_MIN_LOC;
3097 ret = LLVMBuildInsertValue(builder, ret,
3098 LLVMGetParam(ctx->main_fn,
3099 SI_PARAM_SAMPLE_COVERAGE), vgpr++, "");
3100
3101 ctx->return_value = ret;
3102 }
3103
3104 /**
3105 * Given a v8i32 resource descriptor for a buffer, extract the size of the
3106 * buffer in number of elements and return it as an i32.
3107 */
3108 static LLVMValueRef get_buffer_size(
3109 struct lp_build_tgsi_context *bld_base,
3110 LLVMValueRef descriptor)
3111 {
3112 struct si_shader_context *ctx = si_shader_context(bld_base);
3113 struct gallivm_state *gallivm = bld_base->base.gallivm;
3114 LLVMBuilderRef builder = gallivm->builder;
3115 LLVMValueRef size =
3116 LLVMBuildExtractElement(builder, descriptor,
3117 lp_build_const_int32(gallivm, 2), "");
3118
3119 if (ctx->screen->b.chip_class >= VI) {
3120 /* On VI, the descriptor contains the size in bytes,
3121 * but TXQ must return the size in elements.
3122 * The stride is always non-zero for resources using TXQ.
3123 */
3124 LLVMValueRef stride =
3125 LLVMBuildExtractElement(builder, descriptor,
3126 lp_build_const_int32(gallivm, 1), "");
3127 stride = LLVMBuildLShr(builder, stride,
3128 lp_build_const_int32(gallivm, 16), "");
3129 stride = LLVMBuildAnd(builder, stride,
3130 lp_build_const_int32(gallivm, 0x3FFF), "");
3131
3132 size = LLVMBuildUDiv(builder, size, stride, "");
3133 }
3134
3135 return size;
3136 }
3137
3138 /**
3139 * Given the i32 or vNi32 \p type, generate the textual name (e.g. for use with
3140 * intrinsic names).
3141 */
3142 static void build_type_name_for_intr(
3143 LLVMTypeRef type,
3144 char *buf, unsigned bufsize)
3145 {
3146 LLVMTypeRef elem_type = type;
3147
3148 assert(bufsize >= 8);
3149
3150 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind) {
3151 int ret = snprintf(buf, bufsize, "v%u",
3152 LLVMGetVectorSize(type));
3153 if (ret < 0) {
3154 char *type_name = LLVMPrintTypeToString(type);
3155 fprintf(stderr, "Error building type name for: %s\n",
3156 type_name);
3157 return;
3158 }
3159 elem_type = LLVMGetElementType(type);
3160 buf += ret;
3161 bufsize -= ret;
3162 }
3163 switch (LLVMGetTypeKind(elem_type)) {
3164 default: break;
3165 case LLVMIntegerTypeKind:
3166 snprintf(buf, bufsize, "i%d", LLVMGetIntTypeWidth(elem_type));
3167 break;
3168 case LLVMFloatTypeKind:
3169 snprintf(buf, bufsize, "f32");
3170 break;
3171 case LLVMDoubleTypeKind:
3172 snprintf(buf, bufsize, "f64");
3173 break;
3174 }
3175 }
3176
3177 static void build_tex_intrinsic(const struct lp_build_tgsi_action *action,
3178 struct lp_build_tgsi_context *bld_base,
3179 struct lp_build_emit_data *emit_data);
3180
3181 /* Prevent optimizations (at least of memory accesses) across the current
3182 * point in the program by emitting empty inline assembly that is marked as
3183 * having side effects.
3184 */
3185 static void emit_optimization_barrier(struct si_shader_context *ctx)
3186 {
3187 LLVMBuilderRef builder = ctx->gallivm.builder;
3188 LLVMTypeRef ftype = LLVMFunctionType(ctx->voidt, NULL, 0, false);
3189 LLVMValueRef inlineasm = LLVMConstInlineAsm(ftype, "", "", true, false);
3190 LLVMBuildCall(builder, inlineasm, NULL, 0, "");
3191 }
3192
3193 static void emit_waitcnt(struct si_shader_context *ctx)
3194 {
3195 struct gallivm_state *gallivm = &ctx->gallivm;
3196 LLVMBuilderRef builder = gallivm->builder;
3197 LLVMValueRef args[1] = {
3198 lp_build_const_int32(gallivm, 0xf70)
3199 };
3200 lp_build_intrinsic(builder, "llvm.amdgcn.s.waitcnt",
3201 ctx->voidt, args, 1, 0);
3202 }
3203
3204 static void membar_emit(
3205 const struct lp_build_tgsi_action *action,
3206 struct lp_build_tgsi_context *bld_base,
3207 struct lp_build_emit_data *emit_data)
3208 {
3209 struct si_shader_context *ctx = si_shader_context(bld_base);
3210
3211 emit_waitcnt(ctx);
3212 }
3213
3214 static LLVMValueRef
3215 shader_buffer_fetch_rsrc(struct si_shader_context *ctx,
3216 const struct tgsi_full_src_register *reg)
3217 {
3218 LLVMValueRef index;
3219 LLVMValueRef rsrc_ptr = LLVMGetParam(ctx->main_fn,
3220 SI_PARAM_SHADER_BUFFERS);
3221
3222 if (!reg->Register.Indirect)
3223 index = LLVMConstInt(ctx->i32, reg->Register.Index, 0);
3224 else
3225 index = get_bounded_indirect_index(ctx, &reg->Indirect,
3226 reg->Register.Index,
3227 SI_NUM_SHADER_BUFFERS);
3228
3229 return build_indexed_load_const(ctx, rsrc_ptr, index);
3230 }
3231
3232 static bool tgsi_is_array_sampler(unsigned target)
3233 {
3234 return target == TGSI_TEXTURE_1D_ARRAY ||
3235 target == TGSI_TEXTURE_SHADOW1D_ARRAY ||
3236 target == TGSI_TEXTURE_2D_ARRAY ||
3237 target == TGSI_TEXTURE_SHADOW2D_ARRAY ||
3238 target == TGSI_TEXTURE_CUBE_ARRAY ||
3239 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY ||
3240 target == TGSI_TEXTURE_2D_ARRAY_MSAA;
3241 }
3242
3243 static bool tgsi_is_array_image(unsigned target)
3244 {
3245 return target == TGSI_TEXTURE_3D ||
3246 target == TGSI_TEXTURE_CUBE ||
3247 target == TGSI_TEXTURE_1D_ARRAY ||
3248 target == TGSI_TEXTURE_2D_ARRAY ||
3249 target == TGSI_TEXTURE_CUBE_ARRAY ||
3250 target == TGSI_TEXTURE_2D_ARRAY_MSAA;
3251 }
3252
3253 /**
3254 * Given a 256-bit resource descriptor, force the DCC enable bit to off.
3255 *
3256 * At least on Tonga, executing image stores on images with DCC enabled and
3257 * non-trivial can eventually lead to lockups. This can occur when an
3258 * application binds an image as read-only but then uses a shader that writes
3259 * to it. The OpenGL spec allows almost arbitrarily bad behavior (including
3260 * program termination) in this case, but it doesn't cost much to be a bit
3261 * nicer: disabling DCC in the shader still leads to undefined results but
3262 * avoids the lockup.
3263 */
3264 static LLVMValueRef force_dcc_off(struct si_shader_context *ctx,
3265 LLVMValueRef rsrc)
3266 {
3267 if (ctx->screen->b.chip_class <= CIK) {
3268 return rsrc;
3269 } else {
3270 LLVMBuilderRef builder = ctx->gallivm.builder;
3271 LLVMValueRef i32_6 = LLVMConstInt(ctx->i32, 6, 0);
3272 LLVMValueRef i32_C = LLVMConstInt(ctx->i32, C_008F28_COMPRESSION_EN, 0);
3273 LLVMValueRef tmp;
3274
3275 tmp = LLVMBuildExtractElement(builder, rsrc, i32_6, "");
3276 tmp = LLVMBuildAnd(builder, tmp, i32_C, "");
3277 return LLVMBuildInsertElement(builder, rsrc, tmp, i32_6, "");
3278 }
3279 }
3280
3281 static LLVMTypeRef const_array(LLVMTypeRef elem_type, int num_elements)
3282 {
3283 return LLVMPointerType(LLVMArrayType(elem_type, num_elements),
3284 CONST_ADDR_SPACE);
3285 }
3286
3287 /**
3288 * Load the resource descriptor for \p image.
3289 */
3290 static void
3291 image_fetch_rsrc(
3292 struct lp_build_tgsi_context *bld_base,
3293 const struct tgsi_full_src_register *image,
3294 bool is_store, unsigned target,
3295 LLVMValueRef *rsrc)
3296 {
3297 struct si_shader_context *ctx = si_shader_context(bld_base);
3298 LLVMValueRef rsrc_ptr = LLVMGetParam(ctx->main_fn,
3299 SI_PARAM_IMAGES);
3300 LLVMValueRef index, tmp;
3301 bool dcc_off = target != TGSI_TEXTURE_BUFFER && is_store;
3302
3303 assert(image->Register.File == TGSI_FILE_IMAGE);
3304
3305 if (!image->Register.Indirect) {
3306 const struct tgsi_shader_info *info = bld_base->info;
3307
3308 index = LLVMConstInt(ctx->i32, image->Register.Index, 0);
3309
3310 if (info->images_writemask & (1 << image->Register.Index) &&
3311 target != TGSI_TEXTURE_BUFFER)
3312 dcc_off = true;
3313 } else {
3314 /* From the GL_ARB_shader_image_load_store extension spec:
3315 *
3316 * If a shader performs an image load, store, or atomic
3317 * operation using an image variable declared as an array,
3318 * and if the index used to select an individual element is
3319 * negative or greater than or equal to the size of the
3320 * array, the results of the operation are undefined but may
3321 * not lead to termination.
3322 */
3323 index = get_bounded_indirect_index(ctx, &image->Indirect,
3324 image->Register.Index,
3325 SI_NUM_IMAGES);
3326 }
3327
3328 if (target == TGSI_TEXTURE_BUFFER) {
3329 LLVMBuilderRef builder = ctx->gallivm.builder;
3330
3331 rsrc_ptr = LLVMBuildPointerCast(builder, rsrc_ptr,
3332 const_array(ctx->v4i32, 0), "");
3333 index = LLVMBuildMul(builder, index,
3334 LLVMConstInt(ctx->i32, 2, 0), "");
3335 index = LLVMBuildAdd(builder, index,
3336 LLVMConstInt(ctx->i32, 1, 0), "");
3337 *rsrc = build_indexed_load_const(ctx, rsrc_ptr, index);
3338 return;
3339 }
3340
3341 tmp = build_indexed_load_const(ctx, rsrc_ptr, index);
3342 if (dcc_off)
3343 tmp = force_dcc_off(ctx, tmp);
3344 *rsrc = tmp;
3345 }
3346
3347 static LLVMValueRef image_fetch_coords(
3348 struct lp_build_tgsi_context *bld_base,
3349 const struct tgsi_full_instruction *inst,
3350 unsigned src)
3351 {
3352 struct gallivm_state *gallivm = bld_base->base.gallivm;
3353 LLVMBuilderRef builder = gallivm->builder;
3354 unsigned target = inst->Memory.Texture;
3355 unsigned num_coords = tgsi_util_get_texture_coord_dim(target);
3356 LLVMValueRef coords[4];
3357 LLVMValueRef tmp;
3358 int chan;
3359
3360 for (chan = 0; chan < num_coords; ++chan) {
3361 tmp = lp_build_emit_fetch(bld_base, inst, src, chan);
3362 tmp = LLVMBuildBitCast(builder, tmp, bld_base->uint_bld.elem_type, "");
3363 coords[chan] = tmp;
3364 }
3365
3366 if (num_coords == 1)
3367 return coords[0];
3368
3369 if (num_coords == 3) {
3370 /* LLVM has difficulties lowering 3-element vectors. */
3371 coords[3] = bld_base->uint_bld.undef;
3372 num_coords = 4;
3373 }
3374
3375 return lp_build_gather_values(gallivm, coords, num_coords);
3376 }
3377
3378 /**
3379 * Append the extra mode bits that are used by image load and store.
3380 */
3381 static void image_append_args(
3382 struct si_shader_context *ctx,
3383 struct lp_build_emit_data * emit_data,
3384 unsigned target,
3385 bool atomic)
3386 {
3387 const struct tgsi_full_instruction *inst = emit_data->inst;
3388 LLVMValueRef i1false = LLVMConstInt(ctx->i1, 0, 0);
3389 LLVMValueRef i1true = LLVMConstInt(ctx->i1, 1, 0);
3390 LLVMValueRef r128 = i1false;
3391 LLVMValueRef da = tgsi_is_array_image(target) ? i1true : i1false;
3392 LLVMValueRef glc =
3393 inst->Memory.Qualifier & (TGSI_MEMORY_COHERENT | TGSI_MEMORY_VOLATILE) ?
3394 i1true : i1false;
3395 LLVMValueRef slc = i1false;
3396 LLVMValueRef lwe = i1false;
3397
3398 if (atomic || (HAVE_LLVM <= 0x0309)) {
3399 emit_data->args[emit_data->arg_count++] = r128;
3400 emit_data->args[emit_data->arg_count++] = da;
3401 if (!atomic) {
3402 emit_data->args[emit_data->arg_count++] = glc;
3403 }
3404 emit_data->args[emit_data->arg_count++] = slc;
3405 return;
3406 }
3407
3408 /* HAVE_LLVM >= 0x0400 */
3409 emit_data->args[emit_data->arg_count++] = glc;
3410 emit_data->args[emit_data->arg_count++] = slc;
3411 emit_data->args[emit_data->arg_count++] = lwe;
3412 emit_data->args[emit_data->arg_count++] = da;
3413 }
3414
3415 /**
3416 * Append the resource and indexing arguments for buffer intrinsics.
3417 *
3418 * \param rsrc the v4i32 buffer resource
3419 * \param index index into the buffer (stride-based)
3420 * \param offset byte offset into the buffer
3421 */
3422 static void buffer_append_args(
3423 struct si_shader_context *ctx,
3424 struct lp_build_emit_data *emit_data,
3425 LLVMValueRef rsrc,
3426 LLVMValueRef index,
3427 LLVMValueRef offset,
3428 bool atomic)
3429 {
3430 const struct tgsi_full_instruction *inst = emit_data->inst;
3431 LLVMValueRef i1false = LLVMConstInt(ctx->i1, 0, 0);
3432 LLVMValueRef i1true = LLVMConstInt(ctx->i1, 1, 0);
3433
3434 emit_data->args[emit_data->arg_count++] = rsrc;
3435 emit_data->args[emit_data->arg_count++] = index; /* vindex */
3436 emit_data->args[emit_data->arg_count++] = offset; /* voffset */
3437 if (!atomic) {
3438 emit_data->args[emit_data->arg_count++] =
3439 inst->Memory.Qualifier & (TGSI_MEMORY_COHERENT | TGSI_MEMORY_VOLATILE) ?
3440 i1true : i1false; /* glc */
3441 }
3442 emit_data->args[emit_data->arg_count++] = i1false; /* slc */
3443 }
3444
3445 static void load_fetch_args(
3446 struct lp_build_tgsi_context * bld_base,
3447 struct lp_build_emit_data * emit_data)
3448 {
3449 struct si_shader_context *ctx = si_shader_context(bld_base);
3450 struct gallivm_state *gallivm = bld_base->base.gallivm;
3451 const struct tgsi_full_instruction * inst = emit_data->inst;
3452 unsigned target = inst->Memory.Texture;
3453 LLVMValueRef rsrc;
3454
3455 emit_data->dst_type = LLVMVectorType(bld_base->base.elem_type, 4);
3456
3457 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER) {
3458 LLVMBuilderRef builder = gallivm->builder;
3459 LLVMValueRef offset;
3460 LLVMValueRef tmp;
3461
3462 rsrc = shader_buffer_fetch_rsrc(ctx, &inst->Src[0]);
3463
3464 tmp = lp_build_emit_fetch(bld_base, inst, 1, 0);
3465 offset = LLVMBuildBitCast(builder, tmp, bld_base->uint_bld.elem_type, "");
3466
3467 buffer_append_args(ctx, emit_data, rsrc, bld_base->uint_bld.zero,
3468 offset, false);
3469 } else if (inst->Src[0].Register.File == TGSI_FILE_IMAGE) {
3470 LLVMValueRef coords;
3471
3472 image_fetch_rsrc(bld_base, &inst->Src[0], false, target, &rsrc);
3473 coords = image_fetch_coords(bld_base, inst, 1);
3474
3475 if (target == TGSI_TEXTURE_BUFFER) {
3476 buffer_append_args(ctx, emit_data, rsrc, coords,
3477 bld_base->uint_bld.zero, false);
3478 } else {
3479 emit_data->args[0] = coords;
3480 emit_data->args[1] = rsrc;
3481 emit_data->args[2] = lp_build_const_int32(gallivm, 15); /* dmask */
3482 emit_data->arg_count = 3;
3483
3484 image_append_args(ctx, emit_data, target, false);
3485 }
3486 }
3487 }
3488
3489 static void load_emit_buffer(struct si_shader_context *ctx,
3490 struct lp_build_emit_data *emit_data)
3491 {
3492 const struct tgsi_full_instruction *inst = emit_data->inst;
3493 struct gallivm_state *gallivm = &ctx->gallivm;
3494 LLVMBuilderRef builder = gallivm->builder;
3495 uint writemask = inst->Dst[0].Register.WriteMask;
3496 uint count = util_last_bit(writemask);
3497 const char *intrinsic_name;
3498 LLVMTypeRef dst_type;
3499
3500 switch (count) {
3501 case 1:
3502 intrinsic_name = "llvm.amdgcn.buffer.load.f32";
3503 dst_type = ctx->f32;
3504 break;
3505 case 2:
3506 intrinsic_name = "llvm.amdgcn.buffer.load.v2f32";
3507 dst_type = LLVMVectorType(ctx->f32, 2);
3508 break;
3509 default: // 3 & 4
3510 intrinsic_name = "llvm.amdgcn.buffer.load.v4f32";
3511 dst_type = ctx->v4f32;
3512 count = 4;
3513 }
3514
3515 emit_data->output[emit_data->chan] = lp_build_intrinsic(
3516 builder, intrinsic_name, dst_type,
3517 emit_data->args, emit_data->arg_count,
3518 LP_FUNC_ATTR_READONLY);
3519 }
3520
3521 static LLVMValueRef get_memory_ptr(struct si_shader_context *ctx,
3522 const struct tgsi_full_instruction *inst,
3523 LLVMTypeRef type, int arg)
3524 {
3525 struct gallivm_state *gallivm = &ctx->gallivm;
3526 LLVMBuilderRef builder = gallivm->builder;
3527 LLVMValueRef offset, ptr;
3528 int addr_space;
3529
3530 offset = lp_build_emit_fetch(&ctx->soa.bld_base, inst, arg, 0);
3531 offset = LLVMBuildBitCast(builder, offset, ctx->i32, "");
3532
3533 ptr = ctx->shared_memory;
3534 ptr = LLVMBuildGEP(builder, ptr, &offset, 1, "");
3535 addr_space = LLVMGetPointerAddressSpace(LLVMTypeOf(ptr));
3536 ptr = LLVMBuildBitCast(builder, ptr, LLVMPointerType(type, addr_space), "");
3537
3538 return ptr;
3539 }
3540
3541 static void load_emit_memory(
3542 struct si_shader_context *ctx,
3543 struct lp_build_emit_data *emit_data)
3544 {
3545 const struct tgsi_full_instruction *inst = emit_data->inst;
3546 struct lp_build_context *base = &ctx->soa.bld_base.base;
3547 struct gallivm_state *gallivm = &ctx->gallivm;
3548 LLVMBuilderRef builder = gallivm->builder;
3549 unsigned writemask = inst->Dst[0].Register.WriteMask;
3550 LLVMValueRef channels[4], ptr, derived_ptr, index;
3551 int chan;
3552
3553 ptr = get_memory_ptr(ctx, inst, base->elem_type, 1);
3554
3555 for (chan = 0; chan < 4; ++chan) {
3556 if (!(writemask & (1 << chan))) {
3557 channels[chan] = LLVMGetUndef(base->elem_type);
3558 continue;
3559 }
3560
3561 index = lp_build_const_int32(gallivm, chan);
3562 derived_ptr = LLVMBuildGEP(builder, ptr, &index, 1, "");
3563 channels[chan] = LLVMBuildLoad(builder, derived_ptr, "");
3564 }
3565 emit_data->output[emit_data->chan] = lp_build_gather_values(gallivm, channels, 4);
3566 }
3567
3568 static void get_image_intr_name(const char *base_name,
3569 LLVMTypeRef data_type,
3570 LLVMTypeRef coords_type,
3571 LLVMTypeRef rsrc_type,
3572 char *out_name, unsigned out_len)
3573 {
3574 char coords_type_name[8];
3575
3576 build_type_name_for_intr(coords_type, coords_type_name,
3577 sizeof(coords_type_name));
3578
3579 if (HAVE_LLVM <= 0x0309) {
3580 snprintf(out_name, out_len, "%s.%s", base_name, coords_type_name);
3581 } else {
3582 char data_type_name[8];
3583 char rsrc_type_name[8];
3584
3585 build_type_name_for_intr(data_type, data_type_name,
3586 sizeof(data_type_name));
3587 build_type_name_for_intr(rsrc_type, rsrc_type_name,
3588 sizeof(rsrc_type_name));
3589 snprintf(out_name, out_len, "%s.%s.%s.%s", base_name,
3590 data_type_name, coords_type_name, rsrc_type_name);
3591 }
3592 }
3593
3594 static void load_emit(
3595 const struct lp_build_tgsi_action *action,
3596 struct lp_build_tgsi_context *bld_base,
3597 struct lp_build_emit_data *emit_data)
3598 {
3599 struct si_shader_context *ctx = si_shader_context(bld_base);
3600 struct gallivm_state *gallivm = bld_base->base.gallivm;
3601 LLVMBuilderRef builder = gallivm->builder;
3602 const struct tgsi_full_instruction * inst = emit_data->inst;
3603 char intrinsic_name[64];
3604
3605 if (inst->Src[0].Register.File == TGSI_FILE_MEMORY) {
3606 load_emit_memory(ctx, emit_data);
3607 return;
3608 }
3609
3610 if (inst->Memory.Qualifier & TGSI_MEMORY_VOLATILE)
3611 emit_waitcnt(ctx);
3612
3613 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER) {
3614 load_emit_buffer(ctx, emit_data);
3615 return;
3616 }
3617
3618 if (inst->Memory.Texture == TGSI_TEXTURE_BUFFER) {
3619 emit_data->output[emit_data->chan] =
3620 lp_build_intrinsic(
3621 builder, "llvm.amdgcn.buffer.load.format.v4f32", emit_data->dst_type,
3622 emit_data->args, emit_data->arg_count,
3623 LP_FUNC_ATTR_READONLY);
3624 } else {
3625 get_image_intr_name("llvm.amdgcn.image.load",
3626 emit_data->dst_type, /* vdata */
3627 LLVMTypeOf(emit_data->args[0]), /* coords */
3628 LLVMTypeOf(emit_data->args[1]), /* rsrc */
3629 intrinsic_name, sizeof(intrinsic_name));
3630
3631 emit_data->output[emit_data->chan] =
3632 lp_build_intrinsic(
3633 builder, intrinsic_name, emit_data->dst_type,
3634 emit_data->args, emit_data->arg_count,
3635 LP_FUNC_ATTR_READONLY);
3636 }
3637 }
3638
3639 static void store_fetch_args(
3640 struct lp_build_tgsi_context * bld_base,
3641 struct lp_build_emit_data * emit_data)
3642 {
3643 struct si_shader_context *ctx = si_shader_context(bld_base);
3644 struct gallivm_state *gallivm = bld_base->base.gallivm;
3645 LLVMBuilderRef builder = gallivm->builder;
3646 const struct tgsi_full_instruction * inst = emit_data->inst;
3647 struct tgsi_full_src_register memory;
3648 LLVMValueRef chans[4];
3649 LLVMValueRef data;
3650 LLVMValueRef rsrc;
3651 unsigned chan;
3652
3653 emit_data->dst_type = LLVMVoidTypeInContext(gallivm->context);
3654
3655 for (chan = 0; chan < 4; ++chan) {
3656 chans[chan] = lp_build_emit_fetch(bld_base, inst, 1, chan);
3657 }
3658 data = lp_build_gather_values(gallivm, chans, 4);
3659
3660 emit_data->args[emit_data->arg_count++] = data;
3661
3662 memory = tgsi_full_src_register_from_dst(&inst->Dst[0]);
3663
3664 if (inst->Dst[0].Register.File == TGSI_FILE_BUFFER) {
3665 LLVMValueRef offset;
3666 LLVMValueRef tmp;
3667
3668 rsrc = shader_buffer_fetch_rsrc(ctx, &memory);
3669
3670 tmp = lp_build_emit_fetch(bld_base, inst, 0, 0);
3671 offset = LLVMBuildBitCast(builder, tmp, bld_base->uint_bld.elem_type, "");
3672
3673 buffer_append_args(ctx, emit_data, rsrc, bld_base->uint_bld.zero,
3674 offset, false);
3675 } else if (inst->Dst[0].Register.File == TGSI_FILE_IMAGE) {
3676 unsigned target = inst->Memory.Texture;
3677 LLVMValueRef coords;
3678
3679 coords = image_fetch_coords(bld_base, inst, 0);
3680
3681 if (target == TGSI_TEXTURE_BUFFER) {
3682 image_fetch_rsrc(bld_base, &memory, true, target, &rsrc);
3683 buffer_append_args(ctx, emit_data, rsrc, coords,
3684 bld_base->uint_bld.zero, false);
3685 } else {
3686 emit_data->args[1] = coords;
3687 image_fetch_rsrc(bld_base, &memory, true, target,
3688 &emit_data->args[2]);
3689 emit_data->args[3] = lp_build_const_int32(gallivm, 15); /* dmask */
3690 emit_data->arg_count = 4;
3691
3692 image_append_args(ctx, emit_data, target, false);
3693 }
3694 }
3695 }
3696
3697 static void store_emit_buffer(
3698 struct si_shader_context *ctx,
3699 struct lp_build_emit_data *emit_data)
3700 {
3701 const struct tgsi_full_instruction *inst = emit_data->inst;
3702 struct gallivm_state *gallivm = &ctx->gallivm;
3703 LLVMBuilderRef builder = gallivm->builder;
3704 struct lp_build_context *uint_bld = &ctx->soa.bld_base.uint_bld;
3705 LLVMValueRef base_data = emit_data->args[0];
3706 LLVMValueRef base_offset = emit_data->args[3];
3707 unsigned writemask = inst->Dst[0].Register.WriteMask;
3708
3709 while (writemask) {
3710 int start, count;
3711 const char *intrinsic_name;
3712 LLVMValueRef data;
3713 LLVMValueRef offset;
3714 LLVMValueRef tmp;
3715
3716 u_bit_scan_consecutive_range(&writemask, &start, &count);
3717
3718 /* Due to an LLVM limitation, split 3-element writes
3719 * into a 2-element and a 1-element write. */
3720 if (count == 3) {
3721 writemask |= 1 << (start + 2);
3722 count = 2;
3723 }
3724
3725 if (count == 4) {
3726 data = base_data;
3727 intrinsic_name = "llvm.amdgcn.buffer.store.v4f32";
3728 } else if (count == 2) {
3729 LLVMTypeRef v2f32 = LLVMVectorType(ctx->f32, 2);
3730
3731 tmp = LLVMBuildExtractElement(
3732 builder, base_data,
3733 lp_build_const_int32(gallivm, start), "");
3734 data = LLVMBuildInsertElement(
3735 builder, LLVMGetUndef(v2f32), tmp,
3736 uint_bld->zero, "");
3737
3738 tmp = LLVMBuildExtractElement(
3739 builder, base_data,
3740 lp_build_const_int32(gallivm, start + 1), "");
3741 data = LLVMBuildInsertElement(
3742 builder, data, tmp, uint_bld->one, "");
3743
3744 intrinsic_name = "llvm.amdgcn.buffer.store.v2f32";
3745 } else {
3746 assert(count == 1);
3747 data = LLVMBuildExtractElement(
3748 builder, base_data,
3749 lp_build_const_int32(gallivm, start), "");
3750 intrinsic_name = "llvm.amdgcn.buffer.store.f32";
3751 }
3752
3753 offset = base_offset;
3754 if (start != 0) {
3755 offset = LLVMBuildAdd(
3756 builder, offset,
3757 lp_build_const_int32(gallivm, start * 4), "");
3758 }
3759
3760 emit_data->args[0] = data;
3761 emit_data->args[3] = offset;
3762
3763 lp_build_intrinsic(
3764 builder, intrinsic_name, emit_data->dst_type,
3765 emit_data->args, emit_data->arg_count, 0);
3766 }
3767 }
3768
3769 static void store_emit_memory(
3770 struct si_shader_context *ctx,
3771 struct lp_build_emit_data *emit_data)
3772 {
3773 const struct tgsi_full_instruction *inst = emit_data->inst;
3774 struct gallivm_state *gallivm = &ctx->gallivm;
3775 struct lp_build_context *base = &ctx->soa.bld_base.base;
3776 LLVMBuilderRef builder = gallivm->builder;
3777 unsigned writemask = inst->Dst[0].Register.WriteMask;
3778 LLVMValueRef ptr, derived_ptr, data, index;
3779 int chan;
3780
3781 ptr = get_memory_ptr(ctx, inst, base->elem_type, 0);
3782
3783 for (chan = 0; chan < 4; ++chan) {
3784 if (!(writemask & (1 << chan))) {
3785 continue;
3786 }
3787 data = lp_build_emit_fetch(&ctx->soa.bld_base, inst, 1, chan);
3788 index = lp_build_const_int32(gallivm, chan);
3789 derived_ptr = LLVMBuildGEP(builder, ptr, &index, 1, "");
3790 LLVMBuildStore(builder, data, derived_ptr);
3791 }
3792 }
3793
3794 static void store_emit(
3795 const struct lp_build_tgsi_action *action,
3796 struct lp_build_tgsi_context *bld_base,
3797 struct lp_build_emit_data *emit_data)
3798 {
3799 struct si_shader_context *ctx = si_shader_context(bld_base);
3800 struct gallivm_state *gallivm = bld_base->base.gallivm;
3801 LLVMBuilderRef builder = gallivm->builder;
3802 const struct tgsi_full_instruction * inst = emit_data->inst;
3803 unsigned target = inst->Memory.Texture;
3804 char intrinsic_name[64];
3805
3806 if (inst->Dst[0].Register.File == TGSI_FILE_MEMORY) {
3807 store_emit_memory(ctx, emit_data);
3808 return;
3809 }
3810
3811 if (inst->Memory.Qualifier & TGSI_MEMORY_VOLATILE)
3812 emit_waitcnt(ctx);
3813
3814 if (inst->Dst[0].Register.File == TGSI_FILE_BUFFER) {
3815 store_emit_buffer(ctx, emit_data);
3816 return;
3817 }
3818
3819 if (target == TGSI_TEXTURE_BUFFER) {
3820 emit_data->output[emit_data->chan] = lp_build_intrinsic(
3821 builder, "llvm.amdgcn.buffer.store.format.v4f32",
3822 emit_data->dst_type, emit_data->args,
3823 emit_data->arg_count, 0);
3824 } else {
3825 get_image_intr_name("llvm.amdgcn.image.store",
3826 LLVMTypeOf(emit_data->args[0]), /* vdata */
3827 LLVMTypeOf(emit_data->args[1]), /* coords */
3828 LLVMTypeOf(emit_data->args[2]), /* rsrc */
3829 intrinsic_name, sizeof(intrinsic_name));
3830
3831 emit_data->output[emit_data->chan] =
3832 lp_build_intrinsic(
3833 builder, intrinsic_name, emit_data->dst_type,
3834 emit_data->args, emit_data->arg_count, 0);
3835 }
3836 }
3837
3838 static void atomic_fetch_args(
3839 struct lp_build_tgsi_context * bld_base,
3840 struct lp_build_emit_data * emit_data)
3841 {
3842 struct si_shader_context *ctx = si_shader_context(bld_base);
3843 struct gallivm_state *gallivm = bld_base->base.gallivm;
3844 LLVMBuilderRef builder = gallivm->builder;
3845 const struct tgsi_full_instruction * inst = emit_data->inst;
3846 LLVMValueRef data1, data2;
3847 LLVMValueRef rsrc;
3848 LLVMValueRef tmp;
3849
3850 emit_data->dst_type = bld_base->base.elem_type;
3851
3852 tmp = lp_build_emit_fetch(bld_base, inst, 2, 0);
3853 data1 = LLVMBuildBitCast(builder, tmp, bld_base->uint_bld.elem_type, "");
3854
3855 if (inst->Instruction.Opcode == TGSI_OPCODE_ATOMCAS) {
3856 tmp = lp_build_emit_fetch(bld_base, inst, 3, 0);
3857 data2 = LLVMBuildBitCast(builder, tmp, bld_base->uint_bld.elem_type, "");
3858 }
3859
3860 /* llvm.amdgcn.image/buffer.atomic.cmpswap reflect the hardware order
3861 * of arguments, which is reversed relative to TGSI (and GLSL)
3862 */
3863 if (inst->Instruction.Opcode == TGSI_OPCODE_ATOMCAS)
3864 emit_data->args[emit_data->arg_count++] = data2;
3865 emit_data->args[emit_data->arg_count++] = data1;
3866
3867 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER) {
3868 LLVMValueRef offset;
3869
3870 rsrc = shader_buffer_fetch_rsrc(ctx, &inst->Src[0]);
3871
3872 tmp = lp_build_emit_fetch(bld_base, inst, 1, 0);
3873 offset = LLVMBuildBitCast(builder, tmp, bld_base->uint_bld.elem_type, "");
3874
3875 buffer_append_args(ctx, emit_data, rsrc, bld_base->uint_bld.zero,
3876 offset, true);
3877 } else if (inst->Src[0].Register.File == TGSI_FILE_IMAGE) {
3878 unsigned target = inst->Memory.Texture;
3879 LLVMValueRef coords;
3880
3881 image_fetch_rsrc(bld_base, &inst->Src[0], true, target, &rsrc);
3882 coords = image_fetch_coords(bld_base, inst, 1);
3883
3884 if (target == TGSI_TEXTURE_BUFFER) {
3885 buffer_append_args(ctx, emit_data, rsrc, coords,
3886 bld_base->uint_bld.zero, true);
3887 } else {
3888 emit_data->args[emit_data->arg_count++] = coords;
3889 emit_data->args[emit_data->arg_count++] = rsrc;
3890
3891 image_append_args(ctx, emit_data, target, true);
3892 }
3893 }
3894 }
3895
3896 static void atomic_emit_memory(struct si_shader_context *ctx,
3897 struct lp_build_emit_data *emit_data) {
3898 struct gallivm_state *gallivm = &ctx->gallivm;
3899 LLVMBuilderRef builder = gallivm->builder;
3900 const struct tgsi_full_instruction * inst = emit_data->inst;
3901 LLVMValueRef ptr, result, arg;
3902
3903 ptr = get_memory_ptr(ctx, inst, ctx->i32, 1);
3904
3905 arg = lp_build_emit_fetch(&ctx->soa.bld_base, inst, 2, 0);
3906 arg = LLVMBuildBitCast(builder, arg, ctx->i32, "");
3907
3908 if (inst->Instruction.Opcode == TGSI_OPCODE_ATOMCAS) {
3909 LLVMValueRef new_data;
3910 new_data = lp_build_emit_fetch(&ctx->soa.bld_base,
3911 inst, 3, 0);
3912
3913 new_data = LLVMBuildBitCast(builder, new_data, ctx->i32, "");
3914
3915 #if HAVE_LLVM >= 0x309
3916 result = LLVMBuildAtomicCmpXchg(builder, ptr, arg, new_data,
3917 LLVMAtomicOrderingSequentiallyConsistent,
3918 LLVMAtomicOrderingSequentiallyConsistent,
3919 false);
3920 #endif
3921
3922 result = LLVMBuildExtractValue(builder, result, 0, "");
3923 } else {
3924 LLVMAtomicRMWBinOp op;
3925
3926 switch(inst->Instruction.Opcode) {
3927 case TGSI_OPCODE_ATOMUADD:
3928 op = LLVMAtomicRMWBinOpAdd;
3929 break;
3930 case TGSI_OPCODE_ATOMXCHG:
3931 op = LLVMAtomicRMWBinOpXchg;
3932 break;
3933 case TGSI_OPCODE_ATOMAND:
3934 op = LLVMAtomicRMWBinOpAnd;
3935 break;
3936 case TGSI_OPCODE_ATOMOR:
3937 op = LLVMAtomicRMWBinOpOr;
3938 break;
3939 case TGSI_OPCODE_ATOMXOR:
3940 op = LLVMAtomicRMWBinOpXor;
3941 break;
3942 case TGSI_OPCODE_ATOMUMIN:
3943 op = LLVMAtomicRMWBinOpUMin;
3944 break;
3945 case TGSI_OPCODE_ATOMUMAX:
3946 op = LLVMAtomicRMWBinOpUMax;
3947 break;
3948 case TGSI_OPCODE_ATOMIMIN:
3949 op = LLVMAtomicRMWBinOpMin;
3950 break;
3951 case TGSI_OPCODE_ATOMIMAX:
3952 op = LLVMAtomicRMWBinOpMax;
3953 break;
3954 default:
3955 unreachable("unknown atomic opcode");
3956 }
3957
3958 result = LLVMBuildAtomicRMW(builder, op, ptr, arg,
3959 LLVMAtomicOrderingSequentiallyConsistent,
3960 false);
3961 }
3962 emit_data->output[emit_data->chan] = LLVMBuildBitCast(builder, result, emit_data->dst_type, "");
3963 }
3964
3965 static void atomic_emit(
3966 const struct lp_build_tgsi_action *action,
3967 struct lp_build_tgsi_context *bld_base,
3968 struct lp_build_emit_data *emit_data)
3969 {
3970 struct si_shader_context *ctx = si_shader_context(bld_base);
3971 struct gallivm_state *gallivm = bld_base->base.gallivm;
3972 LLVMBuilderRef builder = gallivm->builder;
3973 const struct tgsi_full_instruction * inst = emit_data->inst;
3974 char intrinsic_name[40];
3975 LLVMValueRef tmp;
3976
3977 if (inst->Src[0].Register.File == TGSI_FILE_MEMORY) {
3978 atomic_emit_memory(ctx, emit_data);
3979 return;
3980 }
3981
3982 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER ||
3983 inst->Memory.Texture == TGSI_TEXTURE_BUFFER) {
3984 snprintf(intrinsic_name, sizeof(intrinsic_name),
3985 "llvm.amdgcn.buffer.atomic.%s", action->intr_name);
3986 } else {
3987 LLVMValueRef coords;
3988 char coords_type[8];
3989
3990 if (inst->Instruction.Opcode == TGSI_OPCODE_ATOMCAS)
3991 coords = emit_data->args[2];
3992 else
3993 coords = emit_data->args[1];
3994
3995 build_type_name_for_intr(LLVMTypeOf(coords), coords_type, sizeof(coords_type));
3996 snprintf(intrinsic_name, sizeof(intrinsic_name),
3997 "llvm.amdgcn.image.atomic.%s.%s",
3998 action->intr_name, coords_type);
3999 }
4000
4001 tmp = lp_build_intrinsic(
4002 builder, intrinsic_name, bld_base->uint_bld.elem_type,
4003 emit_data->args, emit_data->arg_count, 0);
4004 emit_data->output[emit_data->chan] =
4005 LLVMBuildBitCast(builder, tmp, bld_base->base.elem_type, "");
4006 }
4007
4008 static void resq_fetch_args(
4009 struct lp_build_tgsi_context * bld_base,
4010 struct lp_build_emit_data * emit_data)
4011 {
4012 struct si_shader_context *ctx = si_shader_context(bld_base);
4013 struct gallivm_state *gallivm = bld_base->base.gallivm;
4014 const struct tgsi_full_instruction *inst = emit_data->inst;
4015 const struct tgsi_full_src_register *reg = &inst->Src[0];
4016
4017 emit_data->dst_type = ctx->v4i32;
4018
4019 if (reg->Register.File == TGSI_FILE_BUFFER) {
4020 emit_data->args[0] = shader_buffer_fetch_rsrc(ctx, reg);
4021 emit_data->arg_count = 1;
4022 } else if (inst->Memory.Texture == TGSI_TEXTURE_BUFFER) {
4023 image_fetch_rsrc(bld_base, reg, false, inst->Memory.Texture,
4024 &emit_data->args[0]);
4025 emit_data->arg_count = 1;
4026 } else {
4027 emit_data->args[0] = bld_base->uint_bld.zero; /* mip level */
4028 image_fetch_rsrc(bld_base, reg, false, inst->Memory.Texture,
4029 &emit_data->args[1]);
4030 emit_data->args[2] = lp_build_const_int32(gallivm, 15); /* dmask */
4031 emit_data->args[3] = bld_base->uint_bld.zero; /* unorm */
4032 emit_data->args[4] = bld_base->uint_bld.zero; /* r128 */
4033 emit_data->args[5] = tgsi_is_array_image(inst->Memory.Texture) ?
4034 bld_base->uint_bld.one : bld_base->uint_bld.zero; /* da */
4035 emit_data->args[6] = bld_base->uint_bld.zero; /* glc */
4036 emit_data->args[7] = bld_base->uint_bld.zero; /* slc */
4037 emit_data->args[8] = bld_base->uint_bld.zero; /* tfe */
4038 emit_data->args[9] = bld_base->uint_bld.zero; /* lwe */
4039 emit_data->arg_count = 10;
4040 }
4041 }
4042
4043 static void resq_emit(
4044 const struct lp_build_tgsi_action *action,
4045 struct lp_build_tgsi_context *bld_base,
4046 struct lp_build_emit_data *emit_data)
4047 {
4048 struct gallivm_state *gallivm = bld_base->base.gallivm;
4049 LLVMBuilderRef builder = gallivm->builder;
4050 const struct tgsi_full_instruction *inst = emit_data->inst;
4051 LLVMValueRef out;
4052
4053 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER) {
4054 out = LLVMBuildExtractElement(builder, emit_data->args[0],
4055 lp_build_const_int32(gallivm, 2), "");
4056 } else if (inst->Memory.Texture == TGSI_TEXTURE_BUFFER) {
4057 out = get_buffer_size(bld_base, emit_data->args[0]);
4058 } else {
4059 out = lp_build_intrinsic(
4060 builder, "llvm.SI.getresinfo.i32", emit_data->dst_type,
4061 emit_data->args, emit_data->arg_count,
4062 LP_FUNC_ATTR_READNONE);
4063
4064 /* Divide the number of layers by 6 to get the number of cubes. */
4065 if (inst->Memory.Texture == TGSI_TEXTURE_CUBE_ARRAY) {
4066 LLVMValueRef imm2 = lp_build_const_int32(gallivm, 2);
4067 LLVMValueRef imm6 = lp_build_const_int32(gallivm, 6);
4068
4069 LLVMValueRef z = LLVMBuildExtractElement(builder, out, imm2, "");
4070 z = LLVMBuildSDiv(builder, z, imm6, "");
4071 out = LLVMBuildInsertElement(builder, out, z, imm2, "");
4072 }
4073 }
4074
4075 emit_data->output[emit_data->chan] = out;
4076 }
4077
4078 static void set_tex_fetch_args(struct si_shader_context *ctx,
4079 struct lp_build_emit_data *emit_data,
4080 unsigned opcode, unsigned target,
4081 LLVMValueRef res_ptr, LLVMValueRef samp_ptr,
4082 LLVMValueRef *param, unsigned count,
4083 unsigned dmask)
4084 {
4085 struct gallivm_state *gallivm = &ctx->gallivm;
4086 unsigned num_args;
4087 unsigned is_rect = target == TGSI_TEXTURE_RECT;
4088
4089 /* Pad to power of two vector */
4090 while (count < util_next_power_of_two(count))
4091 param[count++] = LLVMGetUndef(ctx->i32);
4092
4093 /* Texture coordinates. */
4094 if (count > 1)
4095 emit_data->args[0] = lp_build_gather_values(gallivm, param, count);
4096 else
4097 emit_data->args[0] = param[0];
4098
4099 /* Resource. */
4100 emit_data->args[1] = res_ptr;
4101 num_args = 2;
4102
4103 if (opcode == TGSI_OPCODE_TXF || opcode == TGSI_OPCODE_TXQ)
4104 emit_data->dst_type = ctx->v4i32;
4105 else {
4106 emit_data->dst_type = ctx->v4f32;
4107
4108 emit_data->args[num_args++] = samp_ptr;
4109 }
4110
4111 emit_data->args[num_args++] = lp_build_const_int32(gallivm, dmask);
4112 emit_data->args[num_args++] = lp_build_const_int32(gallivm, is_rect); /* unorm */
4113 emit_data->args[num_args++] = lp_build_const_int32(gallivm, 0); /* r128 */
4114 emit_data->args[num_args++] = lp_build_const_int32(gallivm,
4115 tgsi_is_array_sampler(target)); /* da */
4116 emit_data->args[num_args++] = lp_build_const_int32(gallivm, 0); /* glc */
4117 emit_data->args[num_args++] = lp_build_const_int32(gallivm, 0); /* slc */
4118 emit_data->args[num_args++] = lp_build_const_int32(gallivm, 0); /* tfe */
4119 emit_data->args[num_args++] = lp_build_const_int32(gallivm, 0); /* lwe */
4120
4121 emit_data->arg_count = num_args;
4122 }
4123
4124 static const struct lp_build_tgsi_action tex_action;
4125
4126 enum desc_type {
4127 DESC_IMAGE,
4128 DESC_BUFFER,
4129 DESC_FMASK,
4130 DESC_SAMPLER,
4131 };
4132
4133 /**
4134 * Load an image view, fmask view. or sampler state descriptor.
4135 */
4136 static LLVMValueRef load_sampler_desc_custom(struct si_shader_context *ctx,
4137 LLVMValueRef list, LLVMValueRef index,
4138 enum desc_type type)
4139 {
4140 struct gallivm_state *gallivm = &ctx->gallivm;
4141 LLVMBuilderRef builder = gallivm->builder;
4142
4143 switch (type) {
4144 case DESC_IMAGE:
4145 /* The image is at [0:7]. */
4146 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->i32, 2, 0), "");
4147 break;
4148 case DESC_BUFFER:
4149 /* The buffer is in [4:7]. */
4150 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->i32, 4, 0), "");
4151 index = LLVMBuildAdd(builder, index, LLVMConstInt(ctx->i32, 1, 0), "");
4152 list = LLVMBuildPointerCast(builder, list,
4153 const_array(ctx->v4i32, 0), "");
4154 break;
4155 case DESC_FMASK:
4156 /* The FMASK is at [8:15]. */
4157 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->i32, 2, 0), "");
4158 index = LLVMBuildAdd(builder, index, LLVMConstInt(ctx->i32, 1, 0), "");
4159 break;
4160 case DESC_SAMPLER:
4161 /* The sampler state is at [12:15]. */
4162 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->i32, 4, 0), "");
4163 index = LLVMBuildAdd(builder, index, LLVMConstInt(ctx->i32, 3, 0), "");
4164 list = LLVMBuildPointerCast(builder, list,
4165 const_array(ctx->v4i32, 0), "");
4166 break;
4167 }
4168
4169 return build_indexed_load_const(ctx, list, index);
4170 }
4171
4172 static LLVMValueRef load_sampler_desc(struct si_shader_context *ctx,
4173 LLVMValueRef index, enum desc_type type)
4174 {
4175 LLVMValueRef list = LLVMGetParam(ctx->main_fn,
4176 SI_PARAM_SAMPLERS);
4177
4178 return load_sampler_desc_custom(ctx, list, index, type);
4179 }
4180
4181 /* Disable anisotropic filtering if BASE_LEVEL == LAST_LEVEL.
4182 *
4183 * SI-CI:
4184 * If BASE_LEVEL == LAST_LEVEL, the shader must disable anisotropic
4185 * filtering manually. The driver sets img7 to a mask clearing
4186 * MAX_ANISO_RATIO if BASE_LEVEL == LAST_LEVEL. The shader must do:
4187 * s_and_b32 samp0, samp0, img7
4188 *
4189 * VI:
4190 * The ANISO_OVERRIDE sampler field enables this fix in TA.
4191 */
4192 static LLVMValueRef sici_fix_sampler_aniso(struct si_shader_context *ctx,
4193 LLVMValueRef res, LLVMValueRef samp)
4194 {
4195 LLVMBuilderRef builder = ctx->gallivm.builder;
4196 LLVMValueRef img7, samp0;
4197
4198 if (ctx->screen->b.chip_class >= VI)
4199 return samp;
4200
4201 img7 = LLVMBuildExtractElement(builder, res,
4202 LLVMConstInt(ctx->i32, 7, 0), "");
4203 samp0 = LLVMBuildExtractElement(builder, samp,
4204 LLVMConstInt(ctx->i32, 0, 0), "");
4205 samp0 = LLVMBuildAnd(builder, samp0, img7, "");
4206 return LLVMBuildInsertElement(builder, samp, samp0,
4207 LLVMConstInt(ctx->i32, 0, 0), "");
4208 }
4209
4210 static void tex_fetch_ptrs(
4211 struct lp_build_tgsi_context *bld_base,
4212 struct lp_build_emit_data *emit_data,
4213 LLVMValueRef *res_ptr, LLVMValueRef *samp_ptr, LLVMValueRef *fmask_ptr)
4214 {
4215 struct si_shader_context *ctx = si_shader_context(bld_base);
4216 const struct tgsi_full_instruction *inst = emit_data->inst;
4217 unsigned target = inst->Texture.Texture;
4218 unsigned sampler_src;
4219 unsigned sampler_index;
4220 LLVMValueRef index;
4221
4222 sampler_src = emit_data->inst->Instruction.NumSrcRegs - 1;
4223 sampler_index = emit_data->inst->Src[sampler_src].Register.Index;
4224
4225 if (emit_data->inst->Src[sampler_src].Register.Indirect) {
4226 const struct tgsi_full_src_register *reg = &emit_data->inst->Src[sampler_src];
4227
4228 index = get_bounded_indirect_index(ctx,
4229 &reg->Indirect,
4230 reg->Register.Index,
4231 SI_NUM_SAMPLERS);
4232 } else {
4233 index = LLVMConstInt(ctx->i32, sampler_index, 0);
4234 }
4235
4236 if (target == TGSI_TEXTURE_BUFFER)
4237 *res_ptr = load_sampler_desc(ctx, index, DESC_BUFFER);
4238 else
4239 *res_ptr = load_sampler_desc(ctx, index, DESC_IMAGE);
4240
4241 if (samp_ptr)
4242 *samp_ptr = NULL;
4243 if (fmask_ptr)
4244 *fmask_ptr = NULL;
4245
4246 if (target == TGSI_TEXTURE_2D_MSAA ||
4247 target == TGSI_TEXTURE_2D_ARRAY_MSAA) {
4248 if (fmask_ptr)
4249 *fmask_ptr = load_sampler_desc(ctx, index, DESC_FMASK);
4250 } else if (target != TGSI_TEXTURE_BUFFER) {
4251 if (samp_ptr) {
4252 *samp_ptr = load_sampler_desc(ctx, index, DESC_SAMPLER);
4253 *samp_ptr = sici_fix_sampler_aniso(ctx, *res_ptr, *samp_ptr);
4254 }
4255 }
4256 }
4257
4258 static void txq_fetch_args(
4259 struct lp_build_tgsi_context *bld_base,
4260 struct lp_build_emit_data *emit_data)
4261 {
4262 struct si_shader_context *ctx = si_shader_context(bld_base);
4263 const struct tgsi_full_instruction *inst = emit_data->inst;
4264 unsigned target = inst->Texture.Texture;
4265 LLVMValueRef res_ptr;
4266 LLVMValueRef address;
4267
4268 tex_fetch_ptrs(bld_base, emit_data, &res_ptr, NULL, NULL);
4269
4270 if (target == TGSI_TEXTURE_BUFFER) {
4271 /* Read the size from the buffer descriptor directly. */
4272 emit_data->args[0] = get_buffer_size(bld_base, res_ptr);
4273 return;
4274 }
4275
4276 /* Textures - set the mip level. */
4277 address = lp_build_emit_fetch(bld_base, inst, 0, TGSI_CHAN_X);
4278
4279 set_tex_fetch_args(ctx, emit_data, TGSI_OPCODE_TXQ, target, res_ptr,
4280 NULL, &address, 1, 0xf);
4281 }
4282
4283 static void txq_emit(const struct lp_build_tgsi_action *action,
4284 struct lp_build_tgsi_context *bld_base,
4285 struct lp_build_emit_data *emit_data)
4286 {
4287 struct lp_build_context *base = &bld_base->base;
4288 unsigned target = emit_data->inst->Texture.Texture;
4289
4290 if (target == TGSI_TEXTURE_BUFFER) {
4291 /* Just return the buffer size. */
4292 emit_data->output[emit_data->chan] = emit_data->args[0];
4293 return;
4294 }
4295
4296 emit_data->output[emit_data->chan] = lp_build_intrinsic(
4297 base->gallivm->builder, "llvm.SI.getresinfo.i32",
4298 emit_data->dst_type, emit_data->args, emit_data->arg_count,
4299 LP_FUNC_ATTR_READNONE);
4300
4301 /* Divide the number of layers by 6 to get the number of cubes. */
4302 if (target == TGSI_TEXTURE_CUBE_ARRAY ||
4303 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
4304 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
4305 LLVMValueRef two = lp_build_const_int32(bld_base->base.gallivm, 2);
4306 LLVMValueRef six = lp_build_const_int32(bld_base->base.gallivm, 6);
4307
4308 LLVMValueRef v4 = emit_data->output[emit_data->chan];
4309 LLVMValueRef z = LLVMBuildExtractElement(builder, v4, two, "");
4310 z = LLVMBuildSDiv(builder, z, six, "");
4311
4312 emit_data->output[emit_data->chan] =
4313 LLVMBuildInsertElement(builder, v4, z, two, "");
4314 }
4315 }
4316
4317 static void tex_fetch_args(
4318 struct lp_build_tgsi_context *bld_base,
4319 struct lp_build_emit_data *emit_data)
4320 {
4321 struct si_shader_context *ctx = si_shader_context(bld_base);
4322 struct gallivm_state *gallivm = bld_base->base.gallivm;
4323 const struct tgsi_full_instruction *inst = emit_data->inst;
4324 unsigned opcode = inst->Instruction.Opcode;
4325 unsigned target = inst->Texture.Texture;
4326 LLVMValueRef coords[5], derivs[6];
4327 LLVMValueRef address[16];
4328 unsigned num_coords = tgsi_util_get_texture_coord_dim(target);
4329 int ref_pos = tgsi_util_get_shadow_ref_src_index(target);
4330 unsigned count = 0;
4331 unsigned chan;
4332 unsigned num_deriv_channels = 0;
4333 bool has_offset = inst->Texture.NumOffsets > 0;
4334 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL;
4335 unsigned dmask = 0xf;
4336
4337 tex_fetch_ptrs(bld_base, emit_data, &res_ptr, &samp_ptr, &fmask_ptr);
4338
4339 if (target == TGSI_TEXTURE_BUFFER) {
4340 emit_data->dst_type = ctx->v4f32;
4341 emit_data->args[0] = LLVMBuildBitCast(gallivm->builder, res_ptr,
4342 ctx->v16i8, "");
4343 emit_data->args[1] = bld_base->uint_bld.zero;
4344 emit_data->args[2] = lp_build_emit_fetch(bld_base, emit_data->inst, 0, TGSI_CHAN_X);
4345 emit_data->arg_count = 3;
4346 return;
4347 }
4348
4349 /* Fetch and project texture coordinates */
4350 coords[3] = lp_build_emit_fetch(bld_base, emit_data->inst, 0, TGSI_CHAN_W);
4351 for (chan = 0; chan < 3; chan++ ) {
4352 coords[chan] = lp_build_emit_fetch(bld_base,
4353 emit_data->inst, 0,
4354 chan);
4355 if (opcode == TGSI_OPCODE_TXP)
4356 coords[chan] = lp_build_emit_llvm_binary(bld_base,
4357 TGSI_OPCODE_DIV,
4358 coords[chan],
4359 coords[3]);
4360 }
4361
4362 if (opcode == TGSI_OPCODE_TXP)
4363 coords[3] = bld_base->base.one;
4364
4365 /* Pack offsets. */
4366 if (has_offset && opcode != TGSI_OPCODE_TXF) {
4367 /* The offsets are six-bit signed integers packed like this:
4368 * X=[5:0], Y=[13:8], and Z=[21:16].
4369 */
4370 LLVMValueRef offset[3], pack;
4371
4372 assert(inst->Texture.NumOffsets == 1);
4373
4374 for (chan = 0; chan < 3; chan++) {
4375 offset[chan] = lp_build_emit_fetch_texoffset(bld_base,
4376 emit_data->inst, 0, chan);
4377 offset[chan] = LLVMBuildAnd(gallivm->builder, offset[chan],
4378 lp_build_const_int32(gallivm, 0x3f), "");
4379 if (chan)
4380 offset[chan] = LLVMBuildShl(gallivm->builder, offset[chan],
4381 lp_build_const_int32(gallivm, chan*8), "");
4382 }
4383
4384 pack = LLVMBuildOr(gallivm->builder, offset[0], offset[1], "");
4385 pack = LLVMBuildOr(gallivm->builder, pack, offset[2], "");
4386 address[count++] = pack;
4387 }
4388
4389 /* Pack LOD bias value */
4390 if (opcode == TGSI_OPCODE_TXB)
4391 address[count++] = coords[3];
4392 if (opcode == TGSI_OPCODE_TXB2)
4393 address[count++] = lp_build_emit_fetch(bld_base, inst, 1, TGSI_CHAN_X);
4394
4395 /* Pack depth comparison value */
4396 if (tgsi_is_shadow_target(target) && opcode != TGSI_OPCODE_LODQ) {
4397 LLVMValueRef z;
4398
4399 if (target == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
4400 z = lp_build_emit_fetch(bld_base, inst, 1, TGSI_CHAN_X);
4401 } else {
4402 assert(ref_pos >= 0);
4403 z = coords[ref_pos];
4404 }
4405
4406 /* TC-compatible HTILE promotes Z16 and Z24 to Z32_FLOAT,
4407 * so the depth comparison value isn't clamped for Z16 and
4408 * Z24 anymore. Do it manually here.
4409 *
4410 * It's unnecessary if the original texture format was
4411 * Z32_FLOAT, but we don't know that here.
4412 */
4413 if (ctx->screen->b.chip_class == VI)
4414 z = si_llvm_saturate(bld_base, z);
4415
4416 address[count++] = z;
4417 }
4418
4419 /* Pack user derivatives */
4420 if (opcode == TGSI_OPCODE_TXD) {
4421 int param, num_src_deriv_channels;
4422
4423 switch (target) {
4424 case TGSI_TEXTURE_3D:
4425 num_src_deriv_channels = 3;
4426 num_deriv_channels = 3;
4427 break;
4428 case TGSI_TEXTURE_2D:
4429 case TGSI_TEXTURE_SHADOW2D:
4430 case TGSI_TEXTURE_RECT:
4431 case TGSI_TEXTURE_SHADOWRECT:
4432 case TGSI_TEXTURE_2D_ARRAY:
4433 case TGSI_TEXTURE_SHADOW2D_ARRAY:
4434 num_src_deriv_channels = 2;
4435 num_deriv_channels = 2;
4436 break;
4437 case TGSI_TEXTURE_CUBE:
4438 case TGSI_TEXTURE_SHADOWCUBE:
4439 case TGSI_TEXTURE_CUBE_ARRAY:
4440 case TGSI_TEXTURE_SHADOWCUBE_ARRAY:
4441 /* Cube derivatives will be converted to 2D. */
4442 num_src_deriv_channels = 3;
4443 num_deriv_channels = 2;
4444 break;
4445 case TGSI_TEXTURE_1D:
4446 case TGSI_TEXTURE_SHADOW1D:
4447 case TGSI_TEXTURE_1D_ARRAY:
4448 case TGSI_TEXTURE_SHADOW1D_ARRAY:
4449 num_src_deriv_channels = 1;
4450 num_deriv_channels = 1;
4451 break;
4452 default:
4453 unreachable("invalid target");
4454 }
4455
4456 for (param = 0; param < 2; param++)
4457 for (chan = 0; chan < num_src_deriv_channels; chan++)
4458 derivs[param * num_src_deriv_channels + chan] =
4459 lp_build_emit_fetch(bld_base, inst, param+1, chan);
4460 }
4461
4462 if (target == TGSI_TEXTURE_CUBE ||
4463 target == TGSI_TEXTURE_CUBE_ARRAY ||
4464 target == TGSI_TEXTURE_SHADOWCUBE ||
4465 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY)
4466 si_prepare_cube_coords(bld_base, emit_data, coords, derivs);
4467
4468 if (opcode == TGSI_OPCODE_TXD)
4469 for (int i = 0; i < num_deriv_channels * 2; i++)
4470 address[count++] = derivs[i];
4471
4472 /* Pack texture coordinates */
4473 address[count++] = coords[0];
4474 if (num_coords > 1)
4475 address[count++] = coords[1];
4476 if (num_coords > 2)
4477 address[count++] = coords[2];
4478
4479 /* Pack LOD or sample index */
4480 if (opcode == TGSI_OPCODE_TXL || opcode == TGSI_OPCODE_TXF)
4481 address[count++] = coords[3];
4482 else if (opcode == TGSI_OPCODE_TXL2)
4483 address[count++] = lp_build_emit_fetch(bld_base, inst, 1, TGSI_CHAN_X);
4484
4485 if (count > 16) {
4486 assert(!"Cannot handle more than 16 texture address parameters");
4487 count = 16;
4488 }
4489
4490 for (chan = 0; chan < count; chan++ ) {
4491 address[chan] = LLVMBuildBitCast(gallivm->builder,
4492 address[chan], ctx->i32, "");
4493 }
4494
4495 /* Adjust the sample index according to FMASK.
4496 *
4497 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
4498 * which is the identity mapping. Each nibble says which physical sample
4499 * should be fetched to get that sample.
4500 *
4501 * For example, 0x11111100 means there are only 2 samples stored and
4502 * the second sample covers 3/4 of the pixel. When reading samples 0
4503 * and 1, return physical sample 0 (determined by the first two 0s
4504 * in FMASK), otherwise return physical sample 1.
4505 *
4506 * The sample index should be adjusted as follows:
4507 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
4508 */
4509 if (target == TGSI_TEXTURE_2D_MSAA ||
4510 target == TGSI_TEXTURE_2D_ARRAY_MSAA) {
4511 struct lp_build_context *uint_bld = &bld_base->uint_bld;
4512 struct lp_build_emit_data txf_emit_data = *emit_data;
4513 LLVMValueRef txf_address[4];
4514 unsigned txf_count = count;
4515 struct tgsi_full_instruction inst = {};
4516
4517 memcpy(txf_address, address, sizeof(txf_address));
4518
4519 if (target == TGSI_TEXTURE_2D_MSAA) {
4520 txf_address[2] = bld_base->uint_bld.zero;
4521 }
4522 txf_address[3] = bld_base->uint_bld.zero;
4523
4524 /* Read FMASK using TXF. */
4525 inst.Instruction.Opcode = TGSI_OPCODE_TXF;
4526 inst.Texture.Texture = target;
4527 txf_emit_data.inst = &inst;
4528 txf_emit_data.chan = 0;
4529 set_tex_fetch_args(ctx, &txf_emit_data, TGSI_OPCODE_TXF,
4530 target, fmask_ptr, NULL,
4531 txf_address, txf_count, 0xf);
4532 build_tex_intrinsic(&tex_action, bld_base, &txf_emit_data);
4533
4534 /* Initialize some constants. */
4535 LLVMValueRef four = LLVMConstInt(ctx->i32, 4, 0);
4536 LLVMValueRef F = LLVMConstInt(ctx->i32, 0xF, 0);
4537
4538 /* Apply the formula. */
4539 LLVMValueRef fmask =
4540 LLVMBuildExtractElement(gallivm->builder,
4541 txf_emit_data.output[0],
4542 uint_bld->zero, "");
4543
4544 unsigned sample_chan = target == TGSI_TEXTURE_2D_MSAA ? 2 : 3;
4545
4546 LLVMValueRef sample_index4 =
4547 LLVMBuildMul(gallivm->builder, address[sample_chan], four, "");
4548
4549 LLVMValueRef shifted_fmask =
4550 LLVMBuildLShr(gallivm->builder, fmask, sample_index4, "");
4551
4552 LLVMValueRef final_sample =
4553 LLVMBuildAnd(gallivm->builder, shifted_fmask, F, "");
4554
4555 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
4556 * resource descriptor is 0 (invalid),
4557 */
4558 LLVMValueRef fmask_desc =
4559 LLVMBuildBitCast(gallivm->builder, fmask_ptr,
4560 ctx->v8i32, "");
4561
4562 LLVMValueRef fmask_word1 =
4563 LLVMBuildExtractElement(gallivm->builder, fmask_desc,
4564 uint_bld->one, "");
4565
4566 LLVMValueRef word1_is_nonzero =
4567 LLVMBuildICmp(gallivm->builder, LLVMIntNE,
4568 fmask_word1, uint_bld->zero, "");
4569
4570 /* Replace the MSAA sample index. */
4571 address[sample_chan] =
4572 LLVMBuildSelect(gallivm->builder, word1_is_nonzero,
4573 final_sample, address[sample_chan], "");
4574 }
4575
4576 if (opcode == TGSI_OPCODE_TXF) {
4577 /* add tex offsets */
4578 if (inst->Texture.NumOffsets) {
4579 struct lp_build_context *uint_bld = &bld_base->uint_bld;
4580 struct lp_build_tgsi_soa_context *bld = lp_soa_context(bld_base);
4581 const struct tgsi_texture_offset *off = inst->TexOffsets;
4582
4583 assert(inst->Texture.NumOffsets == 1);
4584
4585 switch (target) {
4586 case TGSI_TEXTURE_3D:
4587 address[2] = lp_build_add(uint_bld, address[2],
4588 bld->immediates[off->Index][off->SwizzleZ]);
4589 /* fall through */
4590 case TGSI_TEXTURE_2D:
4591 case TGSI_TEXTURE_SHADOW2D:
4592 case TGSI_TEXTURE_RECT:
4593 case TGSI_TEXTURE_SHADOWRECT:
4594 case TGSI_TEXTURE_2D_ARRAY:
4595 case TGSI_TEXTURE_SHADOW2D_ARRAY:
4596 address[1] =
4597 lp_build_add(uint_bld, address[1],
4598 bld->immediates[off->Index][off->SwizzleY]);
4599 /* fall through */
4600 case TGSI_TEXTURE_1D:
4601 case TGSI_TEXTURE_SHADOW1D:
4602 case TGSI_TEXTURE_1D_ARRAY:
4603 case TGSI_TEXTURE_SHADOW1D_ARRAY:
4604 address[0] =
4605 lp_build_add(uint_bld, address[0],
4606 bld->immediates[off->Index][off->SwizzleX]);
4607 break;
4608 /* texture offsets do not apply to other texture targets */
4609 }
4610 }
4611 }
4612
4613 if (opcode == TGSI_OPCODE_TG4) {
4614 unsigned gather_comp = 0;
4615
4616 /* DMASK was repurposed for GATHER4. 4 components are always
4617 * returned and DMASK works like a swizzle - it selects
4618 * the component to fetch. The only valid DMASK values are
4619 * 1=red, 2=green, 4=blue, 8=alpha. (e.g. 1 returns
4620 * (red,red,red,red) etc.) The ISA document doesn't mention
4621 * this.
4622 */
4623
4624 /* Get the component index from src1.x for Gather4. */
4625 if (!tgsi_is_shadow_target(target)) {
4626 LLVMValueRef (*imms)[4] = lp_soa_context(bld_base)->immediates;
4627 LLVMValueRef comp_imm;
4628 struct tgsi_src_register src1 = inst->Src[1].Register;
4629
4630 assert(src1.File == TGSI_FILE_IMMEDIATE);
4631
4632 comp_imm = imms[src1.Index][src1.SwizzleX];
4633 gather_comp = LLVMConstIntGetZExtValue(comp_imm);
4634 gather_comp = CLAMP(gather_comp, 0, 3);
4635 }
4636
4637 dmask = 1 << gather_comp;
4638 }
4639
4640 set_tex_fetch_args(ctx, emit_data, opcode, target, res_ptr,
4641 samp_ptr, address, count, dmask);
4642 }
4643
4644 /* Gather4 should follow the same rules as bilinear filtering, but the hardware
4645 * incorrectly forces nearest filtering if the texture format is integer.
4646 * The only effect it has on Gather4, which always returns 4 texels for
4647 * bilinear filtering, is that the final coordinates are off by 0.5 of
4648 * the texel size.
4649 *
4650 * The workaround is to subtract 0.5 from the unnormalized coordinates,
4651 * or (0.5 / size) from the normalized coordinates.
4652 */
4653 static void si_lower_gather4_integer(struct si_shader_context *ctx,
4654 struct lp_build_emit_data *emit_data,
4655 const char *intr_name,
4656 unsigned coord_vgpr_index)
4657 {
4658 LLVMBuilderRef builder = ctx->gallivm.builder;
4659 LLVMValueRef coord = emit_data->args[0];
4660 LLVMValueRef half_texel[2];
4661 int c;
4662
4663 if (emit_data->inst->Texture.Texture == TGSI_TEXTURE_RECT ||
4664 emit_data->inst->Texture.Texture == TGSI_TEXTURE_SHADOWRECT) {
4665 half_texel[0] = half_texel[1] = LLVMConstReal(ctx->f32, -0.5);
4666 } else {
4667 struct tgsi_full_instruction txq_inst = {};
4668 struct lp_build_emit_data txq_emit_data = {};
4669
4670 /* Query the texture size. */
4671 txq_inst.Texture.Texture = emit_data->inst->Texture.Texture;
4672 txq_emit_data.inst = &txq_inst;
4673 txq_emit_data.dst_type = ctx->v4i32;
4674 set_tex_fetch_args(ctx, &txq_emit_data, TGSI_OPCODE_TXQ,
4675 txq_inst.Texture.Texture,
4676 emit_data->args[1], NULL,
4677 &ctx->soa.bld_base.uint_bld.zero,
4678 1, 0xf);
4679 txq_emit(NULL, &ctx->soa.bld_base, &txq_emit_data);
4680
4681 /* Compute -0.5 / size. */
4682 for (c = 0; c < 2; c++) {
4683 half_texel[c] =
4684 LLVMBuildExtractElement(builder, txq_emit_data.output[0],
4685 LLVMConstInt(ctx->i32, c, 0), "");
4686 half_texel[c] = LLVMBuildUIToFP(builder, half_texel[c], ctx->f32, "");
4687 half_texel[c] =
4688 lp_build_emit_llvm_unary(&ctx->soa.bld_base,
4689 TGSI_OPCODE_RCP, half_texel[c]);
4690 half_texel[c] = LLVMBuildFMul(builder, half_texel[c],
4691 LLVMConstReal(ctx->f32, -0.5), "");
4692 }
4693 }
4694
4695 for (c = 0; c < 2; c++) {
4696 LLVMValueRef tmp;
4697 LLVMValueRef index = LLVMConstInt(ctx->i32, coord_vgpr_index + c, 0);
4698
4699 tmp = LLVMBuildExtractElement(builder, coord, index, "");
4700 tmp = LLVMBuildBitCast(builder, tmp, ctx->f32, "");
4701 tmp = LLVMBuildFAdd(builder, tmp, half_texel[c], "");
4702 tmp = LLVMBuildBitCast(builder, tmp, ctx->i32, "");
4703 coord = LLVMBuildInsertElement(builder, coord, tmp, index, "");
4704 }
4705
4706 emit_data->args[0] = coord;
4707 emit_data->output[emit_data->chan] =
4708 lp_build_intrinsic(builder, intr_name, emit_data->dst_type,
4709 emit_data->args, emit_data->arg_count,
4710 LP_FUNC_ATTR_READNONE);
4711 }
4712
4713 static void build_tex_intrinsic(const struct lp_build_tgsi_action *action,
4714 struct lp_build_tgsi_context *bld_base,
4715 struct lp_build_emit_data *emit_data)
4716 {
4717 struct si_shader_context *ctx = si_shader_context(bld_base);
4718 struct lp_build_context *base = &bld_base->base;
4719 const struct tgsi_full_instruction *inst = emit_data->inst;
4720 unsigned opcode = inst->Instruction.Opcode;
4721 unsigned target = inst->Texture.Texture;
4722 char intr_name[127];
4723 bool has_offset = inst->Texture.NumOffsets > 0;
4724 bool is_shadow = tgsi_is_shadow_target(target);
4725 char type[64];
4726 const char *name = "llvm.SI.image.sample";
4727 const char *infix = "";
4728
4729 if (target == TGSI_TEXTURE_BUFFER) {
4730 emit_data->output[emit_data->chan] = lp_build_intrinsic(
4731 base->gallivm->builder,
4732 "llvm.SI.vs.load.input", emit_data->dst_type,
4733 emit_data->args, emit_data->arg_count,
4734 LP_FUNC_ATTR_READNONE);
4735 return;
4736 }
4737
4738 switch (opcode) {
4739 case TGSI_OPCODE_TXF:
4740 name = target == TGSI_TEXTURE_2D_MSAA ||
4741 target == TGSI_TEXTURE_2D_ARRAY_MSAA ?
4742 "llvm.SI.image.load" :
4743 "llvm.SI.image.load.mip";
4744 is_shadow = false;
4745 has_offset = false;
4746 break;
4747 case TGSI_OPCODE_LODQ:
4748 name = "llvm.SI.getlod";
4749 is_shadow = false;
4750 has_offset = false;
4751 break;
4752 case TGSI_OPCODE_TEX:
4753 case TGSI_OPCODE_TEX2:
4754 case TGSI_OPCODE_TXP:
4755 if (ctx->type != PIPE_SHADER_FRAGMENT)
4756 infix = ".lz";
4757 break;
4758 case TGSI_OPCODE_TXB:
4759 case TGSI_OPCODE_TXB2:
4760 assert(ctx->type == PIPE_SHADER_FRAGMENT);
4761 infix = ".b";
4762 break;
4763 case TGSI_OPCODE_TXL:
4764 case TGSI_OPCODE_TXL2:
4765 infix = ".l";
4766 break;
4767 case TGSI_OPCODE_TXD:
4768 infix = ".d";
4769 break;
4770 case TGSI_OPCODE_TG4:
4771 name = "llvm.SI.gather4";
4772 infix = ".lz";
4773 break;
4774 default:
4775 assert(0);
4776 return;
4777 }
4778
4779 /* Add the type and suffixes .c, .o if needed. */
4780 build_type_name_for_intr(LLVMTypeOf(emit_data->args[0]), type, sizeof(type));
4781 sprintf(intr_name, "%s%s%s%s.%s",
4782 name, is_shadow ? ".c" : "", infix,
4783 has_offset ? ".o" : "", type);
4784
4785 /* The hardware needs special lowering for Gather4 with integer formats. */
4786 if (opcode == TGSI_OPCODE_TG4) {
4787 struct tgsi_shader_info *info = &ctx->shader->selector->info;
4788 /* This will also work with non-constant indexing because of how
4789 * glsl_to_tgsi works and we intent to preserve that behavior.
4790 */
4791 const unsigned src_idx = 2;
4792 unsigned sampler = inst->Src[src_idx].Register.Index;
4793
4794 assert(inst->Src[src_idx].Register.File == TGSI_FILE_SAMPLER);
4795
4796 if (info->sampler_type[sampler] == TGSI_RETURN_TYPE_SINT ||
4797 info->sampler_type[sampler] == TGSI_RETURN_TYPE_UINT) {
4798 /* Texture coordinates start after:
4799 * {offset, bias, z-compare, derivatives}
4800 * Only the offset and z-compare can occur here.
4801 */
4802 si_lower_gather4_integer(ctx, emit_data, intr_name,
4803 (int)has_offset + (int)is_shadow);
4804 return;
4805 }
4806 }
4807
4808 emit_data->output[emit_data->chan] = lp_build_intrinsic(
4809 base->gallivm->builder, intr_name, emit_data->dst_type,
4810 emit_data->args, emit_data->arg_count,
4811 LP_FUNC_ATTR_READNONE);
4812 }
4813
4814 static void si_llvm_emit_txqs(
4815 const struct lp_build_tgsi_action *action,
4816 struct lp_build_tgsi_context *bld_base,
4817 struct lp_build_emit_data *emit_data)
4818 {
4819 struct si_shader_context *ctx = si_shader_context(bld_base);
4820 struct gallivm_state *gallivm = bld_base->base.gallivm;
4821 LLVMBuilderRef builder = gallivm->builder;
4822 LLVMValueRef res, samples;
4823 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL;
4824
4825 tex_fetch_ptrs(bld_base, emit_data, &res_ptr, &samp_ptr, &fmask_ptr);
4826
4827
4828 /* Read the samples from the descriptor directly. */
4829 res = LLVMBuildBitCast(builder, res_ptr, ctx->v8i32, "");
4830 samples = LLVMBuildExtractElement(
4831 builder, res,
4832 lp_build_const_int32(gallivm, 3), "");
4833 samples = LLVMBuildLShr(builder, samples,
4834 lp_build_const_int32(gallivm, 16), "");
4835 samples = LLVMBuildAnd(builder, samples,
4836 lp_build_const_int32(gallivm, 0xf), "");
4837 samples = LLVMBuildShl(builder, lp_build_const_int32(gallivm, 1),
4838 samples, "");
4839
4840 emit_data->output[emit_data->chan] = samples;
4841 }
4842
4843 /*
4844 * SI implements derivatives using the local data store (LDS)
4845 * All writes to the LDS happen in all executing threads at
4846 * the same time. TID is the Thread ID for the current
4847 * thread and is a value between 0 and 63, representing
4848 * the thread's position in the wavefront.
4849 *
4850 * For the pixel shader threads are grouped into quads of four pixels.
4851 * The TIDs of the pixels of a quad are:
4852 *
4853 * +------+------+
4854 * |4n + 0|4n + 1|
4855 * +------+------+
4856 * |4n + 2|4n + 3|
4857 * +------+------+
4858 *
4859 * So, masking the TID with 0xfffffffc yields the TID of the top left pixel
4860 * of the quad, masking with 0xfffffffd yields the TID of the top pixel of
4861 * the current pixel's column, and masking with 0xfffffffe yields the TID
4862 * of the left pixel of the current pixel's row.
4863 *
4864 * Adding 1 yields the TID of the pixel to the right of the left pixel, and
4865 * adding 2 yields the TID of the pixel below the top pixel.
4866 */
4867 /* masks for thread ID. */
4868 #define TID_MASK_TOP_LEFT 0xfffffffc
4869 #define TID_MASK_TOP 0xfffffffd
4870 #define TID_MASK_LEFT 0xfffffffe
4871
4872 static void si_llvm_emit_ddxy(
4873 const struct lp_build_tgsi_action *action,
4874 struct lp_build_tgsi_context *bld_base,
4875 struct lp_build_emit_data *emit_data)
4876 {
4877 struct si_shader_context *ctx = si_shader_context(bld_base);
4878 struct gallivm_state *gallivm = bld_base->base.gallivm;
4879 unsigned opcode = emit_data->info->opcode;
4880 LLVMValueRef thread_id, tl, trbl, tl_tid, trbl_tid, val, args[2];
4881 int idx;
4882 unsigned mask;
4883
4884 thread_id = get_thread_id(ctx);
4885
4886 if (opcode == TGSI_OPCODE_DDX_FINE)
4887 mask = TID_MASK_LEFT;
4888 else if (opcode == TGSI_OPCODE_DDY_FINE)
4889 mask = TID_MASK_TOP;
4890 else
4891 mask = TID_MASK_TOP_LEFT;
4892
4893 tl_tid = LLVMBuildAnd(gallivm->builder, thread_id,
4894 lp_build_const_int32(gallivm, mask), "");
4895
4896 /* for DDX we want to next X pixel, DDY next Y pixel. */
4897 idx = (opcode == TGSI_OPCODE_DDX || opcode == TGSI_OPCODE_DDX_FINE) ? 1 : 2;
4898 trbl_tid = LLVMBuildAdd(gallivm->builder, tl_tid,
4899 lp_build_const_int32(gallivm, idx), "");
4900
4901 val = LLVMBuildBitCast(gallivm->builder, emit_data->args[0], ctx->i32, "");
4902
4903 if (ctx->screen->has_ds_bpermute) {
4904 args[0] = LLVMBuildMul(gallivm->builder, tl_tid,
4905 lp_build_const_int32(gallivm, 4), "");
4906 args[1] = val;
4907 tl = lp_build_intrinsic(gallivm->builder,
4908 "llvm.amdgcn.ds.bpermute", ctx->i32,
4909 args, 2, LP_FUNC_ATTR_READNONE);
4910
4911 args[0] = LLVMBuildMul(gallivm->builder, trbl_tid,
4912 lp_build_const_int32(gallivm, 4), "");
4913 trbl = lp_build_intrinsic(gallivm->builder,
4914 "llvm.amdgcn.ds.bpermute", ctx->i32,
4915 args, 2, LP_FUNC_ATTR_READNONE);
4916 } else {
4917 LLVMValueRef store_ptr, load_ptr0, load_ptr1;
4918
4919 store_ptr = build_gep0(ctx, ctx->lds, thread_id);
4920 load_ptr0 = build_gep0(ctx, ctx->lds, tl_tid);
4921 load_ptr1 = build_gep0(ctx, ctx->lds, trbl_tid);
4922
4923 LLVMBuildStore(gallivm->builder, val, store_ptr);
4924 tl = LLVMBuildLoad(gallivm->builder, load_ptr0, "");
4925 trbl = LLVMBuildLoad(gallivm->builder, load_ptr1, "");
4926 }
4927
4928 tl = LLVMBuildBitCast(gallivm->builder, tl, ctx->f32, "");
4929 trbl = LLVMBuildBitCast(gallivm->builder, trbl, ctx->f32, "");
4930
4931 emit_data->output[emit_data->chan] =
4932 LLVMBuildFSub(gallivm->builder, trbl, tl, "");
4933 }
4934
4935 /*
4936 * this takes an I,J coordinate pair,
4937 * and works out the X and Y derivatives.
4938 * it returns DDX(I), DDX(J), DDY(I), DDY(J).
4939 */
4940 static LLVMValueRef si_llvm_emit_ddxy_interp(
4941 struct lp_build_tgsi_context *bld_base,
4942 LLVMValueRef interp_ij)
4943 {
4944 struct si_shader_context *ctx = si_shader_context(bld_base);
4945 struct gallivm_state *gallivm = bld_base->base.gallivm;
4946 LLVMValueRef result[4], a;
4947 unsigned i;
4948
4949 for (i = 0; i < 2; i++) {
4950 a = LLVMBuildExtractElement(gallivm->builder, interp_ij,
4951 LLVMConstInt(ctx->i32, i, 0), "");
4952 result[i] = lp_build_emit_llvm_unary(bld_base, TGSI_OPCODE_DDX, a);
4953 result[2+i] = lp_build_emit_llvm_unary(bld_base, TGSI_OPCODE_DDY, a);
4954 }
4955
4956 return lp_build_gather_values(gallivm, result, 4);
4957 }
4958
4959 static void interp_fetch_args(
4960 struct lp_build_tgsi_context *bld_base,
4961 struct lp_build_emit_data *emit_data)
4962 {
4963 struct si_shader_context *ctx = si_shader_context(bld_base);
4964 struct gallivm_state *gallivm = bld_base->base.gallivm;
4965 const struct tgsi_full_instruction *inst = emit_data->inst;
4966
4967 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET) {
4968 /* offset is in second src, first two channels */
4969 emit_data->args[0] = lp_build_emit_fetch(bld_base,
4970 emit_data->inst, 1,
4971 TGSI_CHAN_X);
4972 emit_data->args[1] = lp_build_emit_fetch(bld_base,
4973 emit_data->inst, 1,
4974 TGSI_CHAN_Y);
4975 emit_data->arg_count = 2;
4976 } else if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
4977 LLVMValueRef sample_position;
4978 LLVMValueRef sample_id;
4979 LLVMValueRef halfval = lp_build_const_float(gallivm, 0.5f);
4980
4981 /* fetch sample ID, then fetch its sample position,
4982 * and place into first two channels.
4983 */
4984 sample_id = lp_build_emit_fetch(bld_base,
4985 emit_data->inst, 1, TGSI_CHAN_X);
4986 sample_id = LLVMBuildBitCast(gallivm->builder, sample_id,
4987 ctx->i32, "");
4988 sample_position = load_sample_position(ctx, sample_id);
4989
4990 emit_data->args[0] = LLVMBuildExtractElement(gallivm->builder,
4991 sample_position,
4992 lp_build_const_int32(gallivm, 0), "");
4993
4994 emit_data->args[0] = LLVMBuildFSub(gallivm->builder, emit_data->args[0], halfval, "");
4995 emit_data->args[1] = LLVMBuildExtractElement(gallivm->builder,
4996 sample_position,
4997 lp_build_const_int32(gallivm, 1), "");
4998 emit_data->args[1] = LLVMBuildFSub(gallivm->builder, emit_data->args[1], halfval, "");
4999 emit_data->arg_count = 2;
5000 }
5001 }
5002
5003 static void build_interp_intrinsic(const struct lp_build_tgsi_action *action,
5004 struct lp_build_tgsi_context *bld_base,
5005 struct lp_build_emit_data *emit_data)
5006 {
5007 struct si_shader_context *ctx = si_shader_context(bld_base);
5008 struct si_shader *shader = ctx->shader;
5009 struct gallivm_state *gallivm = bld_base->base.gallivm;
5010 LLVMValueRef interp_param;
5011 const struct tgsi_full_instruction *inst = emit_data->inst;
5012 const char *intr_name;
5013 int input_index = inst->Src[0].Register.Index;
5014 int chan;
5015 int i;
5016 LLVMValueRef attr_number;
5017 LLVMValueRef params = LLVMGetParam(ctx->main_fn, SI_PARAM_PRIM_MASK);
5018 int interp_param_idx;
5019 unsigned interp = shader->selector->info.input_interpolate[input_index];
5020 unsigned location;
5021
5022 assert(inst->Src[0].Register.File == TGSI_FILE_INPUT);
5023
5024 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
5025 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE)
5026 location = TGSI_INTERPOLATE_LOC_CENTER;
5027 else
5028 location = TGSI_INTERPOLATE_LOC_CENTROID;
5029
5030 interp_param_idx = lookup_interp_param_index(interp, location);
5031 if (interp_param_idx == -1)
5032 return;
5033 else if (interp_param_idx)
5034 interp_param = LLVMGetParam(ctx->main_fn, interp_param_idx);
5035 else
5036 interp_param = NULL;
5037
5038 attr_number = lp_build_const_int32(gallivm, input_index);
5039
5040 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
5041 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
5042 LLVMValueRef ij_out[2];
5043 LLVMValueRef ddxy_out = si_llvm_emit_ddxy_interp(bld_base, interp_param);
5044
5045 /*
5046 * take the I then J parameters, and the DDX/Y for it, and
5047 * calculate the IJ inputs for the interpolator.
5048 * temp1 = ddx * offset/sample.x + I;
5049 * interp_param.I = ddy * offset/sample.y + temp1;
5050 * temp1 = ddx * offset/sample.x + J;
5051 * interp_param.J = ddy * offset/sample.y + temp1;
5052 */
5053 for (i = 0; i < 2; i++) {
5054 LLVMValueRef ix_ll = lp_build_const_int32(gallivm, i);
5055 LLVMValueRef iy_ll = lp_build_const_int32(gallivm, i + 2);
5056 LLVMValueRef ddx_el = LLVMBuildExtractElement(gallivm->builder,
5057 ddxy_out, ix_ll, "");
5058 LLVMValueRef ddy_el = LLVMBuildExtractElement(gallivm->builder,
5059 ddxy_out, iy_ll, "");
5060 LLVMValueRef interp_el = LLVMBuildExtractElement(gallivm->builder,
5061 interp_param, ix_ll, "");
5062 LLVMValueRef temp1, temp2;
5063
5064 interp_el = LLVMBuildBitCast(gallivm->builder, interp_el,
5065 ctx->f32, "");
5066
5067 temp1 = LLVMBuildFMul(gallivm->builder, ddx_el, emit_data->args[0], "");
5068
5069 temp1 = LLVMBuildFAdd(gallivm->builder, temp1, interp_el, "");
5070
5071 temp2 = LLVMBuildFMul(gallivm->builder, ddy_el, emit_data->args[1], "");
5072
5073 temp2 = LLVMBuildFAdd(gallivm->builder, temp2, temp1, "");
5074
5075 ij_out[i] = LLVMBuildBitCast(gallivm->builder,
5076 temp2, ctx->i32, "");
5077 }
5078 interp_param = lp_build_gather_values(bld_base->base.gallivm, ij_out, 2);
5079 }
5080
5081 intr_name = interp_param ? "llvm.SI.fs.interp" : "llvm.SI.fs.constant";
5082 for (chan = 0; chan < 4; chan++) {
5083 LLVMValueRef args[4];
5084 LLVMValueRef llvm_chan;
5085 unsigned schan;
5086
5087 schan = tgsi_util_get_full_src_register_swizzle(&inst->Src[0], chan);
5088 llvm_chan = lp_build_const_int32(gallivm, schan);
5089
5090 args[0] = llvm_chan;
5091 args[1] = attr_number;
5092 args[2] = params;
5093 args[3] = interp_param;
5094
5095 emit_data->output[chan] =
5096 lp_build_intrinsic(gallivm->builder, intr_name,
5097 ctx->f32, args, args[3] ? 4 : 3,
5098 LP_FUNC_ATTR_READNONE);
5099 }
5100 }
5101
5102 static unsigned si_llvm_get_stream(struct lp_build_tgsi_context *bld_base,
5103 struct lp_build_emit_data *emit_data)
5104 {
5105 LLVMValueRef (*imms)[4] = lp_soa_context(bld_base)->immediates;
5106 struct tgsi_src_register src0 = emit_data->inst->Src[0].Register;
5107 unsigned stream;
5108
5109 assert(src0.File == TGSI_FILE_IMMEDIATE);
5110
5111 stream = LLVMConstIntGetZExtValue(imms[src0.Index][src0.SwizzleX]) & 0x3;
5112 return stream;
5113 }
5114
5115 /* Emit one vertex from the geometry shader */
5116 static void si_llvm_emit_vertex(
5117 const struct lp_build_tgsi_action *action,
5118 struct lp_build_tgsi_context *bld_base,
5119 struct lp_build_emit_data *emit_data)
5120 {
5121 struct si_shader_context *ctx = si_shader_context(bld_base);
5122 struct lp_build_context *uint = &bld_base->uint_bld;
5123 struct si_shader *shader = ctx->shader;
5124 struct tgsi_shader_info *info = &shader->selector->info;
5125 struct gallivm_state *gallivm = bld_base->base.gallivm;
5126 LLVMValueRef soffset = LLVMGetParam(ctx->main_fn,
5127 SI_PARAM_GS2VS_OFFSET);
5128 LLVMValueRef gs_next_vertex;
5129 LLVMValueRef can_emit, kill;
5130 LLVMValueRef args[2];
5131 unsigned chan;
5132 int i;
5133 unsigned stream;
5134
5135 stream = si_llvm_get_stream(bld_base, emit_data);
5136
5137 /* Write vertex attribute values to GSVS ring */
5138 gs_next_vertex = LLVMBuildLoad(gallivm->builder,
5139 ctx->gs_next_vertex[stream],
5140 "");
5141
5142 /* If this thread has already emitted the declared maximum number of
5143 * vertices, kill it: excessive vertex emissions are not supposed to
5144 * have any effect, and GS threads have no externally observable
5145 * effects other than emitting vertices.
5146 */
5147 can_emit = LLVMBuildICmp(gallivm->builder, LLVMIntULE, gs_next_vertex,
5148 lp_build_const_int32(gallivm,
5149 shader->selector->gs_max_out_vertices), "");
5150 kill = lp_build_select(&bld_base->base, can_emit,
5151 lp_build_const_float(gallivm, 1.0f),
5152 lp_build_const_float(gallivm, -1.0f));
5153
5154 lp_build_intrinsic(gallivm->builder, "llvm.AMDGPU.kill",
5155 ctx->voidt, &kill, 1, 0);
5156
5157 for (i = 0; i < info->num_outputs; i++) {
5158 LLVMValueRef *out_ptr =
5159 ctx->soa.outputs[i];
5160
5161 for (chan = 0; chan < 4; chan++) {
5162 LLVMValueRef out_val = LLVMBuildLoad(gallivm->builder, out_ptr[chan], "");
5163 LLVMValueRef voffset =
5164 lp_build_const_int32(gallivm, (i * 4 + chan) *
5165 shader->selector->gs_max_out_vertices);
5166
5167 voffset = lp_build_add(uint, voffset, gs_next_vertex);
5168 voffset = lp_build_mul_imm(uint, voffset, 4);
5169
5170 out_val = LLVMBuildBitCast(gallivm->builder, out_val, ctx->i32, "");
5171
5172 build_tbuffer_store(ctx,
5173 ctx->gsvs_ring[stream],
5174 out_val, 1,
5175 voffset, soffset, 0,
5176 V_008F0C_BUF_DATA_FORMAT_32,
5177 V_008F0C_BUF_NUM_FORMAT_UINT,
5178 1, 0, 1, 1, 0);
5179 }
5180 }
5181 gs_next_vertex = lp_build_add(uint, gs_next_vertex,
5182 lp_build_const_int32(gallivm, 1));
5183
5184 LLVMBuildStore(gallivm->builder, gs_next_vertex, ctx->gs_next_vertex[stream]);
5185
5186 /* Signal vertex emission */
5187 args[0] = lp_build_const_int32(gallivm, SENDMSG_GS_OP_EMIT | SENDMSG_GS | (stream << 8));
5188 args[1] = LLVMGetParam(ctx->main_fn, SI_PARAM_GS_WAVE_ID);
5189 lp_build_intrinsic(gallivm->builder, "llvm.SI.sendmsg",
5190 ctx->voidt, args, 2, 0);
5191 }
5192
5193 /* Cut one primitive from the geometry shader */
5194 static void si_llvm_emit_primitive(
5195 const struct lp_build_tgsi_action *action,
5196 struct lp_build_tgsi_context *bld_base,
5197 struct lp_build_emit_data *emit_data)
5198 {
5199 struct si_shader_context *ctx = si_shader_context(bld_base);
5200 struct gallivm_state *gallivm = bld_base->base.gallivm;
5201 LLVMValueRef args[2];
5202 unsigned stream;
5203
5204 /* Signal primitive cut */
5205 stream = si_llvm_get_stream(bld_base, emit_data);
5206 args[0] = lp_build_const_int32(gallivm, SENDMSG_GS_OP_CUT | SENDMSG_GS | (stream << 8));
5207 args[1] = LLVMGetParam(ctx->main_fn, SI_PARAM_GS_WAVE_ID);
5208 lp_build_intrinsic(gallivm->builder, "llvm.SI.sendmsg",
5209 ctx->voidt, args, 2, 0);
5210 }
5211
5212 static void si_llvm_emit_barrier(const struct lp_build_tgsi_action *action,
5213 struct lp_build_tgsi_context *bld_base,
5214 struct lp_build_emit_data *emit_data)
5215 {
5216 struct si_shader_context *ctx = si_shader_context(bld_base);
5217 struct gallivm_state *gallivm = bld_base->base.gallivm;
5218
5219 /* The real barrier instruction isn’t needed, because an entire patch
5220 * always fits into a single wave.
5221 */
5222 if (ctx->type == PIPE_SHADER_TESS_CTRL) {
5223 emit_optimization_barrier(ctx);
5224 return;
5225 }
5226
5227 lp_build_intrinsic(gallivm->builder,
5228 HAVE_LLVM >= 0x0309 ? "llvm.amdgcn.s.barrier"
5229 : "llvm.AMDGPU.barrier.local",
5230 ctx->voidt, NULL, 0, 0);
5231 }
5232
5233 static const struct lp_build_tgsi_action tex_action = {
5234 .fetch_args = tex_fetch_args,
5235 .emit = build_tex_intrinsic,
5236 };
5237
5238 static const struct lp_build_tgsi_action interp_action = {
5239 .fetch_args = interp_fetch_args,
5240 .emit = build_interp_intrinsic,
5241 };
5242
5243 static void si_create_function(struct si_shader_context *ctx,
5244 const char *name,
5245 LLVMTypeRef *returns, unsigned num_returns,
5246 LLVMTypeRef *params, unsigned num_params,
5247 int last_sgpr)
5248 {
5249 int i;
5250
5251 si_llvm_create_func(ctx, name, returns, num_returns,
5252 params, num_params);
5253 si_llvm_shader_type(ctx->main_fn, ctx->type);
5254 ctx->return_value = LLVMGetUndef(ctx->return_type);
5255
5256 for (i = 0; i <= last_sgpr; ++i) {
5257 LLVMValueRef P = LLVMGetParam(ctx->main_fn, i);
5258
5259 /* The combination of:
5260 * - ByVal
5261 * - dereferenceable
5262 * - invariant.load
5263 * allows the optimization passes to move loads and reduces
5264 * SGPR spilling significantly.
5265 */
5266 if (LLVMGetTypeKind(LLVMTypeOf(P)) == LLVMPointerTypeKind) {
5267 lp_add_function_attr(ctx->main_fn, i + 1, LP_FUNC_ATTR_BYVAL);
5268 lp_add_attr_dereferenceable(P, UINT64_MAX);
5269 } else
5270 lp_add_function_attr(ctx->main_fn, i + 1, LP_FUNC_ATTR_INREG);
5271 }
5272
5273 if (ctx->screen->b.debug_flags & DBG_UNSAFE_MATH) {
5274 /* These were copied from some LLVM test. */
5275 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
5276 "less-precise-fpmad",
5277 "true");
5278 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
5279 "no-infs-fp-math",
5280 "true");
5281 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
5282 "no-nans-fp-math",
5283 "true");
5284 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
5285 "unsafe-fp-math",
5286 "true");
5287 }
5288 }
5289
5290 static void create_meta_data(struct si_shader_context *ctx)
5291 {
5292 struct gallivm_state *gallivm = ctx->soa.bld_base.base.gallivm;
5293
5294 ctx->invariant_load_md_kind = LLVMGetMDKindIDInContext(gallivm->context,
5295 "invariant.load", 14);
5296 ctx->range_md_kind = LLVMGetMDKindIDInContext(gallivm->context,
5297 "range", 5);
5298 ctx->uniform_md_kind = LLVMGetMDKindIDInContext(gallivm->context,
5299 "amdgpu.uniform", 14);
5300
5301 ctx->empty_md = LLVMMDNodeInContext(gallivm->context, NULL, 0);
5302 }
5303
5304 static void declare_streamout_params(struct si_shader_context *ctx,
5305 struct pipe_stream_output_info *so,
5306 LLVMTypeRef *params, LLVMTypeRef i32,
5307 unsigned *num_params)
5308 {
5309 int i;
5310
5311 /* Streamout SGPRs. */
5312 if (so->num_outputs) {
5313 if (ctx->type != PIPE_SHADER_TESS_EVAL)
5314 params[ctx->param_streamout_config = (*num_params)++] = i32;
5315 else
5316 ctx->param_streamout_config = ctx->param_tess_offchip;
5317
5318 params[ctx->param_streamout_write_index = (*num_params)++] = i32;
5319 }
5320 /* A streamout buffer offset is loaded if the stride is non-zero. */
5321 for (i = 0; i < 4; i++) {
5322 if (!so->stride[i])
5323 continue;
5324
5325 params[ctx->param_streamout_offset[i] = (*num_params)++] = i32;
5326 }
5327 }
5328
5329 static unsigned llvm_get_type_size(LLVMTypeRef type)
5330 {
5331 LLVMTypeKind kind = LLVMGetTypeKind(type);
5332
5333 switch (kind) {
5334 case LLVMIntegerTypeKind:
5335 return LLVMGetIntTypeWidth(type) / 8;
5336 case LLVMFloatTypeKind:
5337 return 4;
5338 case LLVMPointerTypeKind:
5339 return 8;
5340 case LLVMVectorTypeKind:
5341 return LLVMGetVectorSize(type) *
5342 llvm_get_type_size(LLVMGetElementType(type));
5343 case LLVMArrayTypeKind:
5344 return LLVMGetArrayLength(type) *
5345 llvm_get_type_size(LLVMGetElementType(type));
5346 default:
5347 assert(0);
5348 return 0;
5349 }
5350 }
5351
5352 static void declare_tess_lds(struct si_shader_context *ctx)
5353 {
5354 struct gallivm_state *gallivm = &ctx->gallivm;
5355 struct lp_build_tgsi_context *bld_base = &ctx->soa.bld_base;
5356 struct lp_build_context *uint = &bld_base->uint_bld;
5357
5358 unsigned lds_size = ctx->screen->b.chip_class >= CIK ? 65536 : 32768;
5359 ctx->lds = LLVMBuildIntToPtr(gallivm->builder, uint->zero,
5360 LLVMPointerType(LLVMArrayType(ctx->i32, lds_size / 4), LOCAL_ADDR_SPACE),
5361 "tess_lds");
5362 }
5363
5364 static unsigned si_get_max_workgroup_size(struct si_shader *shader)
5365 {
5366 const unsigned *properties = shader->selector->info.properties;
5367 unsigned max_work_group_size =
5368 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] *
5369 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT] *
5370 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH];
5371
5372 if (!max_work_group_size) {
5373 /* This is a variable group size compute shader,
5374 * compile it for the maximum possible group size.
5375 */
5376 max_work_group_size = SI_MAX_VARIABLE_THREADS_PER_BLOCK;
5377 }
5378 return max_work_group_size;
5379 }
5380
5381 static void create_function(struct si_shader_context *ctx)
5382 {
5383 struct lp_build_tgsi_context *bld_base = &ctx->soa.bld_base;
5384 struct gallivm_state *gallivm = bld_base->base.gallivm;
5385 struct si_shader *shader = ctx->shader;
5386 LLVMTypeRef params[SI_NUM_PARAMS + SI_NUM_VERTEX_BUFFERS], v3i32;
5387 LLVMTypeRef returns[16+32*4];
5388 unsigned i, last_sgpr, num_params, num_return_sgprs;
5389 unsigned num_returns = 0;
5390 unsigned num_prolog_vgprs = 0;
5391
5392 v3i32 = LLVMVectorType(ctx->i32, 3);
5393
5394 params[SI_PARAM_RW_BUFFERS] = const_array(ctx->v16i8, SI_NUM_RW_BUFFERS);
5395 params[SI_PARAM_CONST_BUFFERS] = const_array(ctx->v16i8, SI_NUM_CONST_BUFFERS);
5396 params[SI_PARAM_SAMPLERS] = const_array(ctx->v8i32, SI_NUM_SAMPLERS);
5397 params[SI_PARAM_IMAGES] = const_array(ctx->v8i32, SI_NUM_IMAGES);
5398 params[SI_PARAM_SHADER_BUFFERS] = const_array(ctx->v4i32, SI_NUM_SHADER_BUFFERS);
5399
5400 switch (ctx->type) {
5401 case PIPE_SHADER_VERTEX:
5402 params[SI_PARAM_VERTEX_BUFFERS] = const_array(ctx->v16i8, SI_NUM_VERTEX_BUFFERS);
5403 params[SI_PARAM_BASE_VERTEX] = ctx->i32;
5404 params[SI_PARAM_START_INSTANCE] = ctx->i32;
5405 params[SI_PARAM_DRAWID] = ctx->i32;
5406 num_params = SI_PARAM_DRAWID+1;
5407
5408 if (shader->key.as_es) {
5409 params[ctx->param_es2gs_offset = num_params++] = ctx->i32;
5410 } else if (shader->key.as_ls) {
5411 params[SI_PARAM_LS_OUT_LAYOUT] = ctx->i32;
5412 num_params = SI_PARAM_LS_OUT_LAYOUT+1;
5413 } else {
5414 if (shader->is_gs_copy_shader) {
5415 num_params = SI_PARAM_RW_BUFFERS+1;
5416 } else {
5417 params[SI_PARAM_VS_STATE_BITS] = ctx->i32;
5418 num_params = SI_PARAM_VS_STATE_BITS+1;
5419 }
5420
5421 /* The locations of the other parameters are assigned dynamically. */
5422 declare_streamout_params(ctx, &shader->selector->so,
5423 params, ctx->i32, &num_params);
5424 }
5425
5426 last_sgpr = num_params-1;
5427
5428 /* VGPRs */
5429 params[ctx->param_vertex_id = num_params++] = ctx->i32;
5430 params[ctx->param_rel_auto_id = num_params++] = ctx->i32;
5431 params[ctx->param_vs_prim_id = num_params++] = ctx->i32;
5432 params[ctx->param_instance_id = num_params++] = ctx->i32;
5433
5434 if (!shader->is_gs_copy_shader) {
5435 /* Vertex load indices. */
5436 ctx->param_vertex_index0 = num_params;
5437
5438 for (i = 0; i < shader->selector->info.num_inputs; i++)
5439 params[num_params++] = ctx->i32;
5440
5441 num_prolog_vgprs += shader->selector->info.num_inputs;
5442
5443 /* PrimitiveID output. */
5444 if (!shader->key.as_es && !shader->key.as_ls)
5445 for (i = 0; i <= VS_EPILOG_PRIMID_LOC; i++)
5446 returns[num_returns++] = ctx->f32;
5447 }
5448 break;
5449
5450 case PIPE_SHADER_TESS_CTRL:
5451 params[SI_PARAM_TCS_OFFCHIP_LAYOUT] = ctx->i32;
5452 params[SI_PARAM_TCS_OUT_OFFSETS] = ctx->i32;
5453 params[SI_PARAM_TCS_OUT_LAYOUT] = ctx->i32;
5454 params[SI_PARAM_TCS_IN_LAYOUT] = ctx->i32;
5455 params[ctx->param_oc_lds = SI_PARAM_TCS_OC_LDS] = ctx->i32;
5456 params[SI_PARAM_TESS_FACTOR_OFFSET] = ctx->i32;
5457 last_sgpr = SI_PARAM_TESS_FACTOR_OFFSET;
5458
5459 /* VGPRs */
5460 params[SI_PARAM_PATCH_ID] = ctx->i32;
5461 params[SI_PARAM_REL_IDS] = ctx->i32;
5462 num_params = SI_PARAM_REL_IDS+1;
5463
5464 /* SI_PARAM_TCS_OC_LDS and PARAM_TESS_FACTOR_OFFSET are
5465 * placed after the user SGPRs.
5466 */
5467 for (i = 0; i < SI_TCS_NUM_USER_SGPR + 2; i++)
5468 returns[num_returns++] = ctx->i32; /* SGPRs */
5469
5470 for (i = 0; i < 3; i++)
5471 returns[num_returns++] = ctx->f32; /* VGPRs */
5472 break;
5473
5474 case PIPE_SHADER_TESS_EVAL:
5475 params[SI_PARAM_TCS_OFFCHIP_LAYOUT] = ctx->i32;
5476 num_params = SI_PARAM_TCS_OFFCHIP_LAYOUT+1;
5477
5478 if (shader->key.as_es) {
5479 params[ctx->param_oc_lds = num_params++] = ctx->i32;
5480 params[ctx->param_tess_offchip = num_params++] = ctx->i32;
5481 params[ctx->param_es2gs_offset = num_params++] = ctx->i32;
5482 } else {
5483 params[ctx->param_tess_offchip = num_params++] = ctx->i32;
5484 declare_streamout_params(ctx, &shader->selector->so,
5485 params, ctx->i32, &num_params);
5486 params[ctx->param_oc_lds = num_params++] = ctx->i32;
5487 }
5488 last_sgpr = num_params - 1;
5489
5490 /* VGPRs */
5491 params[ctx->param_tes_u = num_params++] = ctx->f32;
5492 params[ctx->param_tes_v = num_params++] = ctx->f32;
5493 params[ctx->param_tes_rel_patch_id = num_params++] = ctx->i32;
5494 params[ctx->param_tes_patch_id = num_params++] = ctx->i32;
5495
5496 /* PrimitiveID output. */
5497 if (!shader->key.as_es)
5498 for (i = 0; i <= VS_EPILOG_PRIMID_LOC; i++)
5499 returns[num_returns++] = ctx->f32;
5500 break;
5501
5502 case PIPE_SHADER_GEOMETRY:
5503 params[SI_PARAM_GS2VS_OFFSET] = ctx->i32;
5504 params[SI_PARAM_GS_WAVE_ID] = ctx->i32;
5505 last_sgpr = SI_PARAM_GS_WAVE_ID;
5506
5507 /* VGPRs */
5508 params[SI_PARAM_VTX0_OFFSET] = ctx->i32;
5509 params[SI_PARAM_VTX1_OFFSET] = ctx->i32;
5510 params[SI_PARAM_PRIMITIVE_ID] = ctx->i32;
5511 params[SI_PARAM_VTX2_OFFSET] = ctx->i32;
5512 params[SI_PARAM_VTX3_OFFSET] = ctx->i32;
5513 params[SI_PARAM_VTX4_OFFSET] = ctx->i32;
5514 params[SI_PARAM_VTX5_OFFSET] = ctx->i32;
5515 params[SI_PARAM_GS_INSTANCE_ID] = ctx->i32;
5516 num_params = SI_PARAM_GS_INSTANCE_ID+1;
5517 break;
5518
5519 case PIPE_SHADER_FRAGMENT:
5520 params[SI_PARAM_ALPHA_REF] = ctx->f32;
5521 params[SI_PARAM_PRIM_MASK] = ctx->i32;
5522 last_sgpr = SI_PARAM_PRIM_MASK;
5523 params[SI_PARAM_PERSP_SAMPLE] = ctx->v2i32;
5524 params[SI_PARAM_PERSP_CENTER] = ctx->v2i32;
5525 params[SI_PARAM_PERSP_CENTROID] = ctx->v2i32;
5526 params[SI_PARAM_PERSP_PULL_MODEL] = v3i32;
5527 params[SI_PARAM_LINEAR_SAMPLE] = ctx->v2i32;
5528 params[SI_PARAM_LINEAR_CENTER] = ctx->v2i32;
5529 params[SI_PARAM_LINEAR_CENTROID] = ctx->v2i32;
5530 params[SI_PARAM_LINE_STIPPLE_TEX] = ctx->f32;
5531 params[SI_PARAM_POS_X_FLOAT] = ctx->f32;
5532 params[SI_PARAM_POS_Y_FLOAT] = ctx->f32;
5533 params[SI_PARAM_POS_Z_FLOAT] = ctx->f32;
5534 params[SI_PARAM_POS_W_FLOAT] = ctx->f32;
5535 params[SI_PARAM_FRONT_FACE] = ctx->i32;
5536 shader->info.face_vgpr_index = 20;
5537 params[SI_PARAM_ANCILLARY] = ctx->i32;
5538 params[SI_PARAM_SAMPLE_COVERAGE] = ctx->f32;
5539 params[SI_PARAM_POS_FIXED_PT] = ctx->i32;
5540 num_params = SI_PARAM_POS_FIXED_PT+1;
5541
5542 /* Color inputs from the prolog. */
5543 if (shader->selector->info.colors_read) {
5544 unsigned num_color_elements =
5545 util_bitcount(shader->selector->info.colors_read);
5546
5547 assert(num_params + num_color_elements <= ARRAY_SIZE(params));
5548 for (i = 0; i < num_color_elements; i++)
5549 params[num_params++] = ctx->f32;
5550
5551 num_prolog_vgprs += num_color_elements;
5552 }
5553
5554 /* Outputs for the epilog. */
5555 num_return_sgprs = SI_SGPR_ALPHA_REF + 1;
5556 num_returns =
5557 num_return_sgprs +
5558 util_bitcount(shader->selector->info.colors_written) * 4 +
5559 shader->selector->info.writes_z +
5560 shader->selector->info.writes_stencil +
5561 shader->selector->info.writes_samplemask +
5562 1 /* SampleMaskIn */;
5563
5564 num_returns = MAX2(num_returns,
5565 num_return_sgprs +
5566 PS_EPILOG_SAMPLEMASK_MIN_LOC + 1);
5567
5568 for (i = 0; i < num_return_sgprs; i++)
5569 returns[i] = ctx->i32;
5570 for (; i < num_returns; i++)
5571 returns[i] = ctx->f32;
5572 break;
5573
5574 case PIPE_SHADER_COMPUTE:
5575 params[SI_PARAM_GRID_SIZE] = v3i32;
5576 params[SI_PARAM_BLOCK_SIZE] = v3i32;
5577 params[SI_PARAM_BLOCK_ID] = v3i32;
5578 last_sgpr = SI_PARAM_BLOCK_ID;
5579
5580 params[SI_PARAM_THREAD_ID] = v3i32;
5581 num_params = SI_PARAM_THREAD_ID + 1;
5582 break;
5583 default:
5584 assert(0 && "unimplemented shader");
5585 return;
5586 }
5587
5588 assert(num_params <= ARRAY_SIZE(params));
5589
5590 si_create_function(ctx, "main", returns, num_returns, params,
5591 num_params, last_sgpr);
5592
5593 /* Reserve register locations for VGPR inputs the PS prolog may need. */
5594 if (ctx->type == PIPE_SHADER_FRAGMENT &&
5595 ctx->separate_prolog) {
5596 si_llvm_add_attribute(ctx->main_fn,
5597 "InitialPSInputAddr",
5598 S_0286D0_PERSP_SAMPLE_ENA(1) |
5599 S_0286D0_PERSP_CENTER_ENA(1) |
5600 S_0286D0_PERSP_CENTROID_ENA(1) |
5601 S_0286D0_LINEAR_SAMPLE_ENA(1) |
5602 S_0286D0_LINEAR_CENTER_ENA(1) |
5603 S_0286D0_LINEAR_CENTROID_ENA(1) |
5604 S_0286D0_FRONT_FACE_ENA(1) |
5605 S_0286D0_POS_FIXED_PT_ENA(1));
5606 } else if (ctx->type == PIPE_SHADER_COMPUTE) {
5607 si_llvm_add_attribute(ctx->main_fn,
5608 "amdgpu-max-work-group-size",
5609 si_get_max_workgroup_size(shader));
5610 }
5611
5612 shader->info.num_input_sgprs = 0;
5613 shader->info.num_input_vgprs = 0;
5614
5615 for (i = 0; i <= last_sgpr; ++i)
5616 shader->info.num_input_sgprs += llvm_get_type_size(params[i]) / 4;
5617
5618 for (; i < num_params; ++i)
5619 shader->info.num_input_vgprs += llvm_get_type_size(params[i]) / 4;
5620
5621 assert(shader->info.num_input_vgprs >= num_prolog_vgprs);
5622 shader->info.num_input_vgprs -= num_prolog_vgprs;
5623
5624 if (!ctx->screen->has_ds_bpermute &&
5625 bld_base->info &&
5626 (bld_base->info->opcode_count[TGSI_OPCODE_DDX] > 0 ||
5627 bld_base->info->opcode_count[TGSI_OPCODE_DDY] > 0 ||
5628 bld_base->info->opcode_count[TGSI_OPCODE_DDX_FINE] > 0 ||
5629 bld_base->info->opcode_count[TGSI_OPCODE_DDY_FINE] > 0 ||
5630 bld_base->info->opcode_count[TGSI_OPCODE_INTERP_OFFSET] > 0 ||
5631 bld_base->info->opcode_count[TGSI_OPCODE_INTERP_SAMPLE] > 0))
5632 ctx->lds =
5633 LLVMAddGlobalInAddressSpace(gallivm->module,
5634 LLVMArrayType(ctx->i32, 64),
5635 "ddxy_lds",
5636 LOCAL_ADDR_SPACE);
5637
5638 if ((ctx->type == PIPE_SHADER_VERTEX && shader->key.as_ls) ||
5639 ctx->type == PIPE_SHADER_TESS_CTRL ||
5640 ctx->type == PIPE_SHADER_TESS_EVAL)
5641 declare_tess_lds(ctx);
5642 }
5643
5644 /**
5645 * Load ESGS and GSVS ring buffer resource descriptors and save the variables
5646 * for later use.
5647 */
5648 static void preload_ring_buffers(struct si_shader_context *ctx)
5649 {
5650 struct gallivm_state *gallivm =
5651 ctx->soa.bld_base.base.gallivm;
5652
5653 LLVMValueRef buf_ptr = LLVMGetParam(ctx->main_fn,
5654 SI_PARAM_RW_BUFFERS);
5655
5656 if ((ctx->type == PIPE_SHADER_VERTEX &&
5657 ctx->shader->key.as_es) ||
5658 (ctx->type == PIPE_SHADER_TESS_EVAL &&
5659 ctx->shader->key.as_es) ||
5660 ctx->type == PIPE_SHADER_GEOMETRY) {
5661 unsigned ring =
5662 ctx->type == PIPE_SHADER_GEOMETRY ? SI_GS_RING_ESGS
5663 : SI_ES_RING_ESGS;
5664 LLVMValueRef offset = lp_build_const_int32(gallivm, ring);
5665
5666 ctx->esgs_ring =
5667 build_indexed_load_const(ctx, buf_ptr, offset);
5668 }
5669
5670 if (ctx->shader->is_gs_copy_shader) {
5671 LLVMValueRef offset = lp_build_const_int32(gallivm, SI_VS_RING_GSVS);
5672
5673 ctx->gsvs_ring[0] =
5674 build_indexed_load_const(ctx, buf_ptr, offset);
5675 }
5676 if (ctx->type == PIPE_SHADER_GEOMETRY) {
5677 int i;
5678 for (i = 0; i < 4; i++) {
5679 LLVMValueRef offset = lp_build_const_int32(gallivm, SI_GS_RING_GSVS0 + i);
5680
5681 ctx->gsvs_ring[i] =
5682 build_indexed_load_const(ctx, buf_ptr, offset);
5683 }
5684 }
5685 }
5686
5687 static void si_llvm_emit_polygon_stipple(struct si_shader_context *ctx,
5688 LLVMValueRef param_rw_buffers,
5689 unsigned param_pos_fixed_pt)
5690 {
5691 struct lp_build_tgsi_context *bld_base =
5692 &ctx->soa.bld_base;
5693 struct gallivm_state *gallivm = bld_base->base.gallivm;
5694 LLVMBuilderRef builder = gallivm->builder;
5695 LLVMValueRef slot, desc, offset, row, bit, address[2];
5696
5697 /* Use the fixed-point gl_FragCoord input.
5698 * Since the stipple pattern is 32x32 and it repeats, just get 5 bits
5699 * per coordinate to get the repeating effect.
5700 */
5701 address[0] = unpack_param(ctx, param_pos_fixed_pt, 0, 5);
5702 address[1] = unpack_param(ctx, param_pos_fixed_pt, 16, 5);
5703
5704 /* Load the buffer descriptor. */
5705 slot = lp_build_const_int32(gallivm, SI_PS_CONST_POLY_STIPPLE);
5706 desc = build_indexed_load_const(ctx, param_rw_buffers, slot);
5707
5708 /* The stipple pattern is 32x32, each row has 32 bits. */
5709 offset = LLVMBuildMul(builder, address[1],
5710 LLVMConstInt(ctx->i32, 4, 0), "");
5711 row = buffer_load_const(ctx, desc, offset);
5712 row = LLVMBuildBitCast(builder, row, ctx->i32, "");
5713 bit = LLVMBuildLShr(builder, row, address[0], "");
5714 bit = LLVMBuildTrunc(builder, bit, ctx->i1, "");
5715
5716 /* The intrinsic kills the thread if arg < 0. */
5717 bit = LLVMBuildSelect(builder, bit, LLVMConstReal(ctx->f32, 0),
5718 LLVMConstReal(ctx->f32, -1), "");
5719 lp_build_intrinsic(builder, "llvm.AMDGPU.kill", ctx->voidt, &bit, 1, 0);
5720 }
5721
5722 void si_shader_binary_read_config(struct radeon_shader_binary *binary,
5723 struct si_shader_config *conf,
5724 unsigned symbol_offset)
5725 {
5726 unsigned i;
5727 const unsigned char *config =
5728 radeon_shader_binary_config_start(binary, symbol_offset);
5729 bool really_needs_scratch = false;
5730
5731 /* LLVM adds SGPR spills to the scratch size.
5732 * Find out if we really need the scratch buffer.
5733 */
5734 for (i = 0; i < binary->reloc_count; i++) {
5735 const struct radeon_shader_reloc *reloc = &binary->relocs[i];
5736
5737 if (!strcmp(scratch_rsrc_dword0_symbol, reloc->name) ||
5738 !strcmp(scratch_rsrc_dword1_symbol, reloc->name)) {
5739 really_needs_scratch = true;
5740 break;
5741 }
5742 }
5743
5744 /* XXX: We may be able to emit some of these values directly rather than
5745 * extracting fields to be emitted later.
5746 */
5747
5748 for (i = 0; i < binary->config_size_per_symbol; i+= 8) {
5749 unsigned reg = util_le32_to_cpu(*(uint32_t*)(config + i));
5750 unsigned value = util_le32_to_cpu(*(uint32_t*)(config + i + 4));
5751 switch (reg) {
5752 case R_00B028_SPI_SHADER_PGM_RSRC1_PS:
5753 case R_00B128_SPI_SHADER_PGM_RSRC1_VS:
5754 case R_00B228_SPI_SHADER_PGM_RSRC1_GS:
5755 case R_00B848_COMPUTE_PGM_RSRC1:
5756 conf->num_sgprs = MAX2(conf->num_sgprs, (G_00B028_SGPRS(value) + 1) * 8);
5757 conf->num_vgprs = MAX2(conf->num_vgprs, (G_00B028_VGPRS(value) + 1) * 4);
5758 conf->float_mode = G_00B028_FLOAT_MODE(value);
5759 conf->rsrc1 = value;
5760 break;
5761 case R_00B02C_SPI_SHADER_PGM_RSRC2_PS:
5762 conf->lds_size = MAX2(conf->lds_size, G_00B02C_EXTRA_LDS_SIZE(value));
5763 break;
5764 case R_00B84C_COMPUTE_PGM_RSRC2:
5765 conf->lds_size = MAX2(conf->lds_size, G_00B84C_LDS_SIZE(value));
5766 conf->rsrc2 = value;
5767 break;
5768 case R_0286CC_SPI_PS_INPUT_ENA:
5769 conf->spi_ps_input_ena = value;
5770 break;
5771 case R_0286D0_SPI_PS_INPUT_ADDR:
5772 conf->spi_ps_input_addr = value;
5773 break;
5774 case R_0286E8_SPI_TMPRING_SIZE:
5775 case R_00B860_COMPUTE_TMPRING_SIZE:
5776 /* WAVESIZE is in units of 256 dwords. */
5777 if (really_needs_scratch)
5778 conf->scratch_bytes_per_wave =
5779 G_00B860_WAVESIZE(value) * 256 * 4;
5780 break;
5781 case 0x4: /* SPILLED_SGPRS */
5782 conf->spilled_sgprs = value;
5783 break;
5784 case 0x8: /* SPILLED_VGPRS */
5785 conf->spilled_vgprs = value;
5786 break;
5787 default:
5788 {
5789 static bool printed;
5790
5791 if (!printed) {
5792 fprintf(stderr, "Warning: LLVM emitted unknown "
5793 "config register: 0x%x\n", reg);
5794 printed = true;
5795 }
5796 }
5797 break;
5798 }
5799 }
5800
5801 if (!conf->spi_ps_input_addr)
5802 conf->spi_ps_input_addr = conf->spi_ps_input_ena;
5803 }
5804
5805 void si_shader_apply_scratch_relocs(struct si_context *sctx,
5806 struct si_shader *shader,
5807 struct si_shader_config *config,
5808 uint64_t scratch_va)
5809 {
5810 unsigned i;
5811 uint32_t scratch_rsrc_dword0 = scratch_va;
5812 uint32_t scratch_rsrc_dword1 =
5813 S_008F04_BASE_ADDRESS_HI(scratch_va >> 32);
5814
5815 /* Enable scratch coalescing if LLVM sets ELEMENT_SIZE & INDEX_STRIDE
5816 * correctly.
5817 */
5818 if (HAVE_LLVM >= 0x0309)
5819 scratch_rsrc_dword1 |= S_008F04_SWIZZLE_ENABLE(1);
5820 else
5821 scratch_rsrc_dword1 |=
5822 S_008F04_STRIDE(config->scratch_bytes_per_wave / 64);
5823
5824 for (i = 0 ; i < shader->binary.reloc_count; i++) {
5825 const struct radeon_shader_reloc *reloc =
5826 &shader->binary.relocs[i];
5827 if (!strcmp(scratch_rsrc_dword0_symbol, reloc->name)) {
5828 util_memcpy_cpu_to_le32(shader->binary.code + reloc->offset,
5829 &scratch_rsrc_dword0, 4);
5830 } else if (!strcmp(scratch_rsrc_dword1_symbol, reloc->name)) {
5831 util_memcpy_cpu_to_le32(shader->binary.code + reloc->offset,
5832 &scratch_rsrc_dword1, 4);
5833 }
5834 }
5835 }
5836
5837 static unsigned si_get_shader_binary_size(struct si_shader *shader)
5838 {
5839 unsigned size = shader->binary.code_size;
5840
5841 if (shader->prolog)
5842 size += shader->prolog->binary.code_size;
5843 if (shader->epilog)
5844 size += shader->epilog->binary.code_size;
5845 return size;
5846 }
5847
5848 int si_shader_binary_upload(struct si_screen *sscreen, struct si_shader *shader)
5849 {
5850 const struct radeon_shader_binary *prolog =
5851 shader->prolog ? &shader->prolog->binary : NULL;
5852 const struct radeon_shader_binary *epilog =
5853 shader->epilog ? &shader->epilog->binary : NULL;
5854 const struct radeon_shader_binary *mainb = &shader->binary;
5855 unsigned bo_size = si_get_shader_binary_size(shader) +
5856 (!epilog ? mainb->rodata_size : 0);
5857 unsigned char *ptr;
5858
5859 assert(!prolog || !prolog->rodata_size);
5860 assert((!prolog && !epilog) || !mainb->rodata_size);
5861 assert(!epilog || !epilog->rodata_size);
5862
5863 r600_resource_reference(&shader->bo, NULL);
5864 shader->bo = (struct r600_resource*)
5865 pipe_buffer_create(&sscreen->b.b, 0,
5866 PIPE_USAGE_IMMUTABLE, bo_size);
5867 if (!shader->bo)
5868 return -ENOMEM;
5869
5870 /* Upload. */
5871 ptr = sscreen->b.ws->buffer_map(shader->bo->buf, NULL,
5872 PIPE_TRANSFER_READ_WRITE);
5873
5874 if (prolog) {
5875 util_memcpy_cpu_to_le32(ptr, prolog->code, prolog->code_size);
5876 ptr += prolog->code_size;
5877 }
5878
5879 util_memcpy_cpu_to_le32(ptr, mainb->code, mainb->code_size);
5880 ptr += mainb->code_size;
5881
5882 if (epilog)
5883 util_memcpy_cpu_to_le32(ptr, epilog->code, epilog->code_size);
5884 else if (mainb->rodata_size > 0)
5885 util_memcpy_cpu_to_le32(ptr, mainb->rodata, mainb->rodata_size);
5886
5887 sscreen->b.ws->buffer_unmap(shader->bo->buf);
5888 return 0;
5889 }
5890
5891 static void si_shader_dump_disassembly(const struct radeon_shader_binary *binary,
5892 struct pipe_debug_callback *debug,
5893 const char *name, FILE *file)
5894 {
5895 char *line, *p;
5896 unsigned i, count;
5897
5898 if (binary->disasm_string) {
5899 fprintf(file, "Shader %s disassembly:\n", name);
5900 fprintf(file, "%s", binary->disasm_string);
5901
5902 if (debug && debug->debug_message) {
5903 /* Very long debug messages are cut off, so send the
5904 * disassembly one line at a time. This causes more
5905 * overhead, but on the plus side it simplifies
5906 * parsing of resulting logs.
5907 */
5908 pipe_debug_message(debug, SHADER_INFO,
5909 "Shader Disassembly Begin");
5910
5911 line = binary->disasm_string;
5912 while (*line) {
5913 p = util_strchrnul(line, '\n');
5914 count = p - line;
5915
5916 if (count) {
5917 pipe_debug_message(debug, SHADER_INFO,
5918 "%.*s", count, line);
5919 }
5920
5921 if (!*p)
5922 break;
5923 line = p + 1;
5924 }
5925
5926 pipe_debug_message(debug, SHADER_INFO,
5927 "Shader Disassembly End");
5928 }
5929 } else {
5930 fprintf(file, "Shader %s binary:\n", name);
5931 for (i = 0; i < binary->code_size; i += 4) {
5932 fprintf(file, "@0x%x: %02x%02x%02x%02x\n", i,
5933 binary->code[i + 3], binary->code[i + 2],
5934 binary->code[i + 1], binary->code[i]);
5935 }
5936 }
5937 }
5938
5939 static void si_shader_dump_stats(struct si_screen *sscreen,
5940 struct si_shader_config *conf,
5941 unsigned num_inputs,
5942 unsigned code_size,
5943 struct pipe_debug_callback *debug,
5944 unsigned processor,
5945 FILE *file)
5946 {
5947 unsigned lds_increment = sscreen->b.chip_class >= CIK ? 512 : 256;
5948 unsigned lds_per_wave = 0;
5949 unsigned max_simd_waves = 10;
5950
5951 /* Compute LDS usage for PS. */
5952 if (processor == PIPE_SHADER_FRAGMENT) {
5953 /* The minimum usage per wave is (num_inputs * 48). The maximum
5954 * usage is (num_inputs * 48 * 16).
5955 * We can get anything in between and it varies between waves.
5956 *
5957 * The 48 bytes per input for a single primitive is equal to
5958 * 4 bytes/component * 4 components/input * 3 points.
5959 *
5960 * Other stages don't know the size at compile time or don't
5961 * allocate LDS per wave, but instead they do it per thread group.
5962 */
5963 lds_per_wave = conf->lds_size * lds_increment +
5964 align(num_inputs * 48, lds_increment);
5965 }
5966
5967 /* Compute the per-SIMD wave counts. */
5968 if (conf->num_sgprs) {
5969 if (sscreen->b.chip_class >= VI)
5970 max_simd_waves = MIN2(max_simd_waves, 800 / conf->num_sgprs);
5971 else
5972 max_simd_waves = MIN2(max_simd_waves, 512 / conf->num_sgprs);
5973 }
5974
5975 if (conf->num_vgprs)
5976 max_simd_waves = MIN2(max_simd_waves, 256 / conf->num_vgprs);
5977
5978 /* LDS is 64KB per CU (4 SIMDs), divided into 16KB blocks per SIMD
5979 * that PS can use.
5980 */
5981 if (lds_per_wave)
5982 max_simd_waves = MIN2(max_simd_waves, 16384 / lds_per_wave);
5983
5984 if (file != stderr ||
5985 r600_can_dump_shader(&sscreen->b, processor)) {
5986 if (processor == PIPE_SHADER_FRAGMENT) {
5987 fprintf(file, "*** SHADER CONFIG ***\n"
5988 "SPI_PS_INPUT_ADDR = 0x%04x\n"
5989 "SPI_PS_INPUT_ENA = 0x%04x\n",
5990 conf->spi_ps_input_addr, conf->spi_ps_input_ena);
5991 }
5992
5993 fprintf(file, "*** SHADER STATS ***\n"
5994 "SGPRS: %d\n"
5995 "VGPRS: %d\n"
5996 "Spilled SGPRs: %d\n"
5997 "Spilled VGPRs: %d\n"
5998 "Private memory VGPRs: %d\n"
5999 "Code Size: %d bytes\n"
6000 "LDS: %d blocks\n"
6001 "Scratch: %d bytes per wave\n"
6002 "Max Waves: %d\n"
6003 "********************\n\n\n",
6004 conf->num_sgprs, conf->num_vgprs,
6005 conf->spilled_sgprs, conf->spilled_vgprs,
6006 conf->private_mem_vgprs, code_size,
6007 conf->lds_size, conf->scratch_bytes_per_wave,
6008 max_simd_waves);
6009 }
6010
6011 pipe_debug_message(debug, SHADER_INFO,
6012 "Shader Stats: SGPRS: %d VGPRS: %d Code Size: %d "
6013 "LDS: %d Scratch: %d Max Waves: %d Spilled SGPRs: %d "
6014 "Spilled VGPRs: %d PrivMem VGPRs: %d",
6015 conf->num_sgprs, conf->num_vgprs, code_size,
6016 conf->lds_size, conf->scratch_bytes_per_wave,
6017 max_simd_waves, conf->spilled_sgprs,
6018 conf->spilled_vgprs, conf->private_mem_vgprs);
6019 }
6020
6021 static const char *si_get_shader_name(struct si_shader *shader,
6022 unsigned processor)
6023 {
6024 switch (processor) {
6025 case PIPE_SHADER_VERTEX:
6026 if (shader->key.as_es)
6027 return "Vertex Shader as ES";
6028 else if (shader->key.as_ls)
6029 return "Vertex Shader as LS";
6030 else
6031 return "Vertex Shader as VS";
6032 case PIPE_SHADER_TESS_CTRL:
6033 return "Tessellation Control Shader";
6034 case PIPE_SHADER_TESS_EVAL:
6035 if (shader->key.as_es)
6036 return "Tessellation Evaluation Shader as ES";
6037 else
6038 return "Tessellation Evaluation Shader as VS";
6039 case PIPE_SHADER_GEOMETRY:
6040 if (shader->is_gs_copy_shader)
6041 return "GS Copy Shader as VS";
6042 else
6043 return "Geometry Shader";
6044 case PIPE_SHADER_FRAGMENT:
6045 return "Pixel Shader";
6046 case PIPE_SHADER_COMPUTE:
6047 return "Compute Shader";
6048 default:
6049 return "Unknown Shader";
6050 }
6051 }
6052
6053 void si_shader_dump(struct si_screen *sscreen, struct si_shader *shader,
6054 struct pipe_debug_callback *debug, unsigned processor,
6055 FILE *file)
6056 {
6057 if (file != stderr ||
6058 r600_can_dump_shader(&sscreen->b, processor))
6059 si_dump_shader_key(processor, &shader->key, file);
6060
6061 if (file != stderr && shader->binary.llvm_ir_string) {
6062 fprintf(file, "\n%s - main shader part - LLVM IR:\n\n",
6063 si_get_shader_name(shader, processor));
6064 fprintf(file, "%s\n", shader->binary.llvm_ir_string);
6065 }
6066
6067 if (file != stderr ||
6068 (r600_can_dump_shader(&sscreen->b, processor) &&
6069 !(sscreen->b.debug_flags & DBG_NO_ASM))) {
6070 fprintf(file, "\n%s:\n", si_get_shader_name(shader, processor));
6071
6072 if (shader->prolog)
6073 si_shader_dump_disassembly(&shader->prolog->binary,
6074 debug, "prolog", file);
6075
6076 si_shader_dump_disassembly(&shader->binary, debug, "main", file);
6077
6078 if (shader->epilog)
6079 si_shader_dump_disassembly(&shader->epilog->binary,
6080 debug, "epilog", file);
6081 fprintf(file, "\n");
6082 }
6083
6084 si_shader_dump_stats(sscreen, &shader->config,
6085 shader->selector ? shader->selector->info.num_inputs : 0,
6086 si_get_shader_binary_size(shader), debug, processor,
6087 file);
6088 }
6089
6090 int si_compile_llvm(struct si_screen *sscreen,
6091 struct radeon_shader_binary *binary,
6092 struct si_shader_config *conf,
6093 LLVMTargetMachineRef tm,
6094 LLVMModuleRef mod,
6095 struct pipe_debug_callback *debug,
6096 unsigned processor,
6097 const char *name)
6098 {
6099 int r = 0;
6100 unsigned count = p_atomic_inc_return(&sscreen->b.num_compilations);
6101
6102 if (r600_can_dump_shader(&sscreen->b, processor)) {
6103 fprintf(stderr, "radeonsi: Compiling shader %d\n", count);
6104
6105 if (!(sscreen->b.debug_flags & (DBG_NO_IR | DBG_PREOPT_IR))) {
6106 fprintf(stderr, "%s LLVM IR:\n\n", name);
6107 LLVMDumpModule(mod);
6108 fprintf(stderr, "\n");
6109 }
6110 }
6111
6112 if (sscreen->record_llvm_ir) {
6113 char *ir = LLVMPrintModuleToString(mod);
6114 binary->llvm_ir_string = strdup(ir);
6115 LLVMDisposeMessage(ir);
6116 }
6117
6118 if (!si_replace_shader(count, binary)) {
6119 r = si_llvm_compile(mod, binary, tm, debug);
6120 if (r)
6121 return r;
6122 }
6123
6124 si_shader_binary_read_config(binary, conf, 0);
6125
6126 /* Enable 64-bit and 16-bit denormals, because there is no performance
6127 * cost.
6128 *
6129 * If denormals are enabled, all floating-point output modifiers are
6130 * ignored.
6131 *
6132 * Don't enable denormals for 32-bit floats, because:
6133 * - Floating-point output modifiers would be ignored by the hw.
6134 * - Some opcodes don't support denormals, such as v_mad_f32. We would
6135 * have to stop using those.
6136 * - SI & CI would be very slow.
6137 */
6138 conf->float_mode |= V_00B028_FP_64_DENORMS;
6139
6140 FREE(binary->config);
6141 FREE(binary->global_symbol_offsets);
6142 binary->config = NULL;
6143 binary->global_symbol_offsets = NULL;
6144
6145 /* Some shaders can't have rodata because their binaries can be
6146 * concatenated.
6147 */
6148 if (binary->rodata_size &&
6149 (processor == PIPE_SHADER_VERTEX ||
6150 processor == PIPE_SHADER_TESS_CTRL ||
6151 processor == PIPE_SHADER_TESS_EVAL ||
6152 processor == PIPE_SHADER_FRAGMENT)) {
6153 fprintf(stderr, "radeonsi: The shader can't have rodata.");
6154 return -EINVAL;
6155 }
6156
6157 return r;
6158 }
6159
6160 static void si_llvm_build_ret(struct si_shader_context *ctx, LLVMValueRef ret)
6161 {
6162 if (LLVMGetTypeKind(LLVMTypeOf(ret)) == LLVMVoidTypeKind)
6163 LLVMBuildRetVoid(ctx->gallivm.builder);
6164 else
6165 LLVMBuildRet(ctx->gallivm.builder, ret);
6166 }
6167
6168 /* Generate code for the hardware VS shader stage to go with a geometry shader */
6169 struct si_shader *
6170 si_generate_gs_copy_shader(struct si_screen *sscreen,
6171 LLVMTargetMachineRef tm,
6172 struct si_shader_selector *gs_selector,
6173 struct pipe_debug_callback *debug)
6174 {
6175 struct si_shader_context ctx;
6176 struct si_shader *shader;
6177 struct gallivm_state *gallivm = &ctx.gallivm;
6178 struct lp_build_tgsi_context *bld_base = &ctx.soa.bld_base;
6179 struct lp_build_context *uint = &bld_base->uint_bld;
6180 struct si_shader_output_values *outputs;
6181 struct tgsi_shader_info *gsinfo = &gs_selector->info;
6182 LLVMValueRef args[9];
6183 int i, r;
6184
6185 outputs = MALLOC(gsinfo->num_outputs * sizeof(outputs[0]));
6186
6187 if (!outputs)
6188 return NULL;
6189
6190 shader = CALLOC_STRUCT(si_shader);
6191 if (!shader) {
6192 FREE(outputs);
6193 return NULL;
6194 }
6195
6196
6197 shader->selector = gs_selector;
6198 shader->is_gs_copy_shader = true;
6199
6200 si_init_shader_ctx(&ctx, sscreen, shader, tm);
6201 ctx.type = PIPE_SHADER_VERTEX;
6202
6203 create_meta_data(&ctx);
6204 create_function(&ctx);
6205 preload_ring_buffers(&ctx);
6206
6207 args[0] = ctx.gsvs_ring[0];
6208 args[1] = lp_build_mul_imm(uint,
6209 LLVMGetParam(ctx.main_fn,
6210 ctx.param_vertex_id),
6211 4);
6212 args[3] = uint->zero;
6213 args[4] = uint->one; /* OFFEN */
6214 args[5] = uint->zero; /* IDXEN */
6215 args[6] = uint->one; /* GLC */
6216 args[7] = uint->one; /* SLC */
6217 args[8] = uint->zero; /* TFE */
6218
6219 /* Fetch vertex data from GSVS ring */
6220 for (i = 0; i < gsinfo->num_outputs; ++i) {
6221 unsigned chan;
6222
6223 outputs[i].name = gsinfo->output_semantic_name[i];
6224 outputs[i].sid = gsinfo->output_semantic_index[i];
6225
6226 for (chan = 0; chan < 4; chan++) {
6227 args[2] = lp_build_const_int32(gallivm,
6228 (i * 4 + chan) *
6229 gs_selector->gs_max_out_vertices * 16 * 4);
6230
6231 outputs[i].values[chan] =
6232 LLVMBuildBitCast(gallivm->builder,
6233 lp_build_intrinsic(gallivm->builder,
6234 "llvm.SI.buffer.load.dword.i32.i32",
6235 ctx.i32, args, 9,
6236 LP_FUNC_ATTR_READONLY),
6237 ctx.f32, "");
6238 }
6239 }
6240
6241 si_llvm_export_vs(bld_base, outputs, gsinfo->num_outputs);
6242
6243 LLVMBuildRetVoid(gallivm->builder);
6244
6245 /* Dump LLVM IR before any optimization passes */
6246 if (sscreen->b.debug_flags & DBG_PREOPT_IR &&
6247 r600_can_dump_shader(&sscreen->b, PIPE_SHADER_GEOMETRY))
6248 LLVMDumpModule(bld_base->base.gallivm->module);
6249
6250 si_llvm_finalize_module(&ctx,
6251 r600_extra_shader_checks(&sscreen->b, PIPE_SHADER_GEOMETRY));
6252
6253 r = si_compile_llvm(sscreen, &ctx.shader->binary,
6254 &ctx.shader->config, ctx.tm,
6255 bld_base->base.gallivm->module,
6256 debug, PIPE_SHADER_GEOMETRY,
6257 "GS Copy Shader");
6258 if (!r) {
6259 if (r600_can_dump_shader(&sscreen->b, PIPE_SHADER_GEOMETRY))
6260 fprintf(stderr, "GS Copy Shader:\n");
6261 si_shader_dump(sscreen, ctx.shader, debug,
6262 PIPE_SHADER_GEOMETRY, stderr);
6263 r = si_shader_binary_upload(sscreen, ctx.shader);
6264 }
6265
6266 si_llvm_dispose(&ctx);
6267
6268 FREE(outputs);
6269
6270 if (r != 0) {
6271 FREE(shader);
6272 shader = NULL;
6273 }
6274 return shader;
6275 }
6276
6277 static void si_dump_shader_key(unsigned shader, struct si_shader_key *key,
6278 FILE *f)
6279 {
6280 int i;
6281
6282 fprintf(f, "SHADER KEY\n");
6283
6284 switch (shader) {
6285 case PIPE_SHADER_VERTEX:
6286 fprintf(f, " part.vs.prolog.instance_divisors = {");
6287 for (i = 0; i < ARRAY_SIZE(key->part.vs.prolog.instance_divisors); i++)
6288 fprintf(f, !i ? "%u" : ", %u",
6289 key->part.vs.prolog.instance_divisors[i]);
6290 fprintf(f, "}\n");
6291 fprintf(f, " part.vs.epilog.export_prim_id = %u\n", key->part.vs.epilog.export_prim_id);
6292 fprintf(f, " as_es = %u\n", key->as_es);
6293 fprintf(f, " as_ls = %u\n", key->as_ls);
6294 fprintf(f, " mono.vs.fix_fetch = 0x%x\n", key->mono.vs.fix_fetch);
6295 break;
6296
6297 case PIPE_SHADER_TESS_CTRL:
6298 fprintf(f, " part.tcs.epilog.prim_mode = %u\n", key->part.tcs.epilog.prim_mode);
6299 fprintf(f, " mono.tcs.inputs_to_copy = 0x%"PRIx64"\n", key->mono.tcs.inputs_to_copy);
6300 break;
6301
6302 case PIPE_SHADER_TESS_EVAL:
6303 fprintf(f, " part.tes.epilog.export_prim_id = %u\n", key->part.tes.epilog.export_prim_id);
6304 fprintf(f, " as_es = %u\n", key->as_es);
6305 break;
6306
6307 case PIPE_SHADER_GEOMETRY:
6308 fprintf(f, " part.gs.prolog.tri_strip_adj_fix = %u\n", key->part.gs.prolog.tri_strip_adj_fix);
6309 break;
6310
6311 case PIPE_SHADER_COMPUTE:
6312 break;
6313
6314 case PIPE_SHADER_FRAGMENT:
6315 fprintf(f, " part.ps.prolog.color_two_side = %u\n", key->part.ps.prolog.color_two_side);
6316 fprintf(f, " part.ps.prolog.flatshade_colors = %u\n", key->part.ps.prolog.flatshade_colors);
6317 fprintf(f, " part.ps.prolog.poly_stipple = %u\n", key->part.ps.prolog.poly_stipple);
6318 fprintf(f, " part.ps.prolog.force_persp_sample_interp = %u\n", key->part.ps.prolog.force_persp_sample_interp);
6319 fprintf(f, " part.ps.prolog.force_linear_sample_interp = %u\n", key->part.ps.prolog.force_linear_sample_interp);
6320 fprintf(f, " part.ps.prolog.force_persp_center_interp = %u\n", key->part.ps.prolog.force_persp_center_interp);
6321 fprintf(f, " part.ps.prolog.force_linear_center_interp = %u\n", key->part.ps.prolog.force_linear_center_interp);
6322 fprintf(f, " part.ps.prolog.bc_optimize_for_persp = %u\n", key->part.ps.prolog.bc_optimize_for_persp);
6323 fprintf(f, " part.ps.prolog.bc_optimize_for_linear = %u\n", key->part.ps.prolog.bc_optimize_for_linear);
6324 fprintf(f, " part.ps.epilog.spi_shader_col_format = 0x%x\n", key->part.ps.epilog.spi_shader_col_format);
6325 fprintf(f, " part.ps.epilog.color_is_int8 = 0x%X\n", key->part.ps.epilog.color_is_int8);
6326 fprintf(f, " part.ps.epilog.last_cbuf = %u\n", key->part.ps.epilog.last_cbuf);
6327 fprintf(f, " part.ps.epilog.alpha_func = %u\n", key->part.ps.epilog.alpha_func);
6328 fprintf(f, " part.ps.epilog.alpha_to_one = %u\n", key->part.ps.epilog.alpha_to_one);
6329 fprintf(f, " part.ps.epilog.poly_line_smoothing = %u\n", key->part.ps.epilog.poly_line_smoothing);
6330 fprintf(f, " part.ps.epilog.clamp_color = %u\n", key->part.ps.epilog.clamp_color);
6331 break;
6332
6333 default:
6334 assert(0);
6335 }
6336
6337 if ((shader == PIPE_SHADER_GEOMETRY ||
6338 shader == PIPE_SHADER_TESS_EVAL ||
6339 shader == PIPE_SHADER_VERTEX) &&
6340 !key->as_es && !key->as_ls) {
6341 fprintf(f, " opt.hw_vs.kill_outputs = 0x%"PRIx64"\n", key->opt.hw_vs.kill_outputs);
6342 fprintf(f, " opt.hw_vs.kill_outputs2 = 0x%x\n", key->opt.hw_vs.kill_outputs2);
6343 fprintf(f, " opt.hw_vs.clip_disable = %u\n", key->opt.hw_vs.clip_disable);
6344 }
6345 }
6346
6347 static void si_init_shader_ctx(struct si_shader_context *ctx,
6348 struct si_screen *sscreen,
6349 struct si_shader *shader,
6350 LLVMTargetMachineRef tm)
6351 {
6352 struct lp_build_tgsi_context *bld_base;
6353 struct lp_build_tgsi_action tmpl = {};
6354
6355 si_llvm_context_init(ctx, sscreen, shader, tm,
6356 (shader && shader->selector) ? &shader->selector->info : NULL,
6357 (shader && shader->selector) ? shader->selector->tokens : NULL);
6358
6359 bld_base = &ctx->soa.bld_base;
6360 bld_base->emit_fetch_funcs[TGSI_FILE_CONSTANT] = fetch_constant;
6361
6362 bld_base->op_actions[TGSI_OPCODE_INTERP_CENTROID] = interp_action;
6363 bld_base->op_actions[TGSI_OPCODE_INTERP_SAMPLE] = interp_action;
6364 bld_base->op_actions[TGSI_OPCODE_INTERP_OFFSET] = interp_action;
6365
6366 bld_base->op_actions[TGSI_OPCODE_TEX] = tex_action;
6367 bld_base->op_actions[TGSI_OPCODE_TEX2] = tex_action;
6368 bld_base->op_actions[TGSI_OPCODE_TXB] = tex_action;
6369 bld_base->op_actions[TGSI_OPCODE_TXB2] = tex_action;
6370 bld_base->op_actions[TGSI_OPCODE_TXD] = tex_action;
6371 bld_base->op_actions[TGSI_OPCODE_TXF] = tex_action;
6372 bld_base->op_actions[TGSI_OPCODE_TXL] = tex_action;
6373 bld_base->op_actions[TGSI_OPCODE_TXL2] = tex_action;
6374 bld_base->op_actions[TGSI_OPCODE_TXP] = tex_action;
6375 bld_base->op_actions[TGSI_OPCODE_TXQ].fetch_args = txq_fetch_args;
6376 bld_base->op_actions[TGSI_OPCODE_TXQ].emit = txq_emit;
6377 bld_base->op_actions[TGSI_OPCODE_TG4] = tex_action;
6378 bld_base->op_actions[TGSI_OPCODE_LODQ] = tex_action;
6379 bld_base->op_actions[TGSI_OPCODE_TXQS].emit = si_llvm_emit_txqs;
6380
6381 bld_base->op_actions[TGSI_OPCODE_LOAD].fetch_args = load_fetch_args;
6382 bld_base->op_actions[TGSI_OPCODE_LOAD].emit = load_emit;
6383 bld_base->op_actions[TGSI_OPCODE_STORE].fetch_args = store_fetch_args;
6384 bld_base->op_actions[TGSI_OPCODE_STORE].emit = store_emit;
6385 bld_base->op_actions[TGSI_OPCODE_RESQ].fetch_args = resq_fetch_args;
6386 bld_base->op_actions[TGSI_OPCODE_RESQ].emit = resq_emit;
6387
6388 tmpl.fetch_args = atomic_fetch_args;
6389 tmpl.emit = atomic_emit;
6390 bld_base->op_actions[TGSI_OPCODE_ATOMUADD] = tmpl;
6391 bld_base->op_actions[TGSI_OPCODE_ATOMUADD].intr_name = "add";
6392 bld_base->op_actions[TGSI_OPCODE_ATOMXCHG] = tmpl;
6393 bld_base->op_actions[TGSI_OPCODE_ATOMXCHG].intr_name = "swap";
6394 bld_base->op_actions[TGSI_OPCODE_ATOMCAS] = tmpl;
6395 bld_base->op_actions[TGSI_OPCODE_ATOMCAS].intr_name = "cmpswap";
6396 bld_base->op_actions[TGSI_OPCODE_ATOMAND] = tmpl;
6397 bld_base->op_actions[TGSI_OPCODE_ATOMAND].intr_name = "and";
6398 bld_base->op_actions[TGSI_OPCODE_ATOMOR] = tmpl;
6399 bld_base->op_actions[TGSI_OPCODE_ATOMOR].intr_name = "or";
6400 bld_base->op_actions[TGSI_OPCODE_ATOMXOR] = tmpl;
6401 bld_base->op_actions[TGSI_OPCODE_ATOMXOR].intr_name = "xor";
6402 bld_base->op_actions[TGSI_OPCODE_ATOMUMIN] = tmpl;
6403 bld_base->op_actions[TGSI_OPCODE_ATOMUMIN].intr_name = "umin";
6404 bld_base->op_actions[TGSI_OPCODE_ATOMUMAX] = tmpl;
6405 bld_base->op_actions[TGSI_OPCODE_ATOMUMAX].intr_name = "umax";
6406 bld_base->op_actions[TGSI_OPCODE_ATOMIMIN] = tmpl;
6407 bld_base->op_actions[TGSI_OPCODE_ATOMIMIN].intr_name = "smin";
6408 bld_base->op_actions[TGSI_OPCODE_ATOMIMAX] = tmpl;
6409 bld_base->op_actions[TGSI_OPCODE_ATOMIMAX].intr_name = "smax";
6410
6411 bld_base->op_actions[TGSI_OPCODE_MEMBAR].emit = membar_emit;
6412
6413 bld_base->op_actions[TGSI_OPCODE_DDX].emit = si_llvm_emit_ddxy;
6414 bld_base->op_actions[TGSI_OPCODE_DDY].emit = si_llvm_emit_ddxy;
6415 bld_base->op_actions[TGSI_OPCODE_DDX_FINE].emit = si_llvm_emit_ddxy;
6416 bld_base->op_actions[TGSI_OPCODE_DDY_FINE].emit = si_llvm_emit_ddxy;
6417
6418 bld_base->op_actions[TGSI_OPCODE_EMIT].emit = si_llvm_emit_vertex;
6419 bld_base->op_actions[TGSI_OPCODE_ENDPRIM].emit = si_llvm_emit_primitive;
6420 bld_base->op_actions[TGSI_OPCODE_BARRIER].emit = si_llvm_emit_barrier;
6421 }
6422
6423 /* Return true if the PARAM export has been eliminated. */
6424 static bool si_eliminate_const_output(struct si_shader_context *ctx,
6425 LLVMValueRef inst, unsigned offset)
6426 {
6427 struct si_shader *shader = ctx->shader;
6428 unsigned num_outputs = shader->selector->info.num_outputs;
6429 unsigned i, default_val; /* SPI_PS_INPUT_CNTL_i.DEFAULT_VAL */
6430 bool is_zero[4] = {}, is_one[4] = {};
6431
6432 for (i = 0; i < 4; i++) {
6433 LLVMBool loses_info;
6434 LLVMValueRef p = LLVMGetOperand(inst, 5 + i);
6435
6436 /* It's a constant expression. Undef outputs are eliminated too. */
6437 if (LLVMIsUndef(p)) {
6438 is_zero[i] = true;
6439 is_one[i] = true;
6440 } else if (LLVMIsAConstantFP(p)) {
6441 double a = LLVMConstRealGetDouble(p, &loses_info);
6442
6443 if (a == 0)
6444 is_zero[i] = true;
6445 else if (a == 1)
6446 is_one[i] = true;
6447 else
6448 return false; /* other constant */
6449 } else
6450 return false;
6451 }
6452
6453 /* Only certain combinations of 0 and 1 can be eliminated. */
6454 if (is_zero[0] && is_zero[1] && is_zero[2])
6455 default_val = is_zero[3] ? 0 : 1;
6456 else if (is_one[0] && is_one[1] && is_one[2])
6457 default_val = is_zero[3] ? 2 : 3;
6458 else
6459 return false;
6460
6461 /* The PARAM export can be represented as DEFAULT_VAL. Kill it. */
6462 LLVMInstructionEraseFromParent(inst);
6463
6464 /* Change OFFSET to DEFAULT_VAL. */
6465 for (i = 0; i < num_outputs; i++) {
6466 if (shader->info.vs_output_param_offset[i] == offset) {
6467 shader->info.vs_output_param_offset[i] =
6468 EXP_PARAM_DEFAULT_VAL_0000 + default_val;
6469 break;
6470 }
6471 }
6472 return true;
6473 }
6474
6475 struct si_vs_exports {
6476 unsigned num;
6477 unsigned offset[SI_MAX_VS_OUTPUTS];
6478 LLVMValueRef inst[SI_MAX_VS_OUTPUTS];
6479 };
6480
6481 static void si_eliminate_const_vs_outputs(struct si_shader_context *ctx)
6482 {
6483 struct si_shader *shader = ctx->shader;
6484 struct tgsi_shader_info *info = &shader->selector->info;
6485 LLVMBasicBlockRef bb;
6486 struct si_vs_exports exports;
6487 bool removed_any = false;
6488
6489 exports.num = 0;
6490
6491 if (ctx->type == PIPE_SHADER_FRAGMENT ||
6492 ctx->type == PIPE_SHADER_COMPUTE ||
6493 shader->key.as_es ||
6494 shader->key.as_ls)
6495 return;
6496
6497 /* Process all LLVM instructions. */
6498 bb = LLVMGetFirstBasicBlock(ctx->main_fn);
6499 while (bb) {
6500 LLVMValueRef inst = LLVMGetFirstInstruction(bb);
6501
6502 while (inst) {
6503 LLVMValueRef cur = inst;
6504 inst = LLVMGetNextInstruction(inst);
6505
6506 if (LLVMGetInstructionOpcode(cur) != LLVMCall)
6507 continue;
6508
6509 LLVMValueRef callee = lp_get_called_value(cur);
6510
6511 if (!lp_is_function(callee))
6512 continue;
6513
6514 const char *name = LLVMGetValueName(callee);
6515 unsigned num_args = LLVMCountParams(callee);
6516
6517 /* Check if this is an export instruction. */
6518 if (num_args != 9 || strcmp(name, "llvm.SI.export"))
6519 continue;
6520
6521 LLVMValueRef arg = LLVMGetOperand(cur, 3);
6522 unsigned target = LLVMConstIntGetZExtValue(arg);
6523
6524 if (target < V_008DFC_SQ_EXP_PARAM)
6525 continue;
6526
6527 target -= V_008DFC_SQ_EXP_PARAM;
6528
6529 /* Eliminate constant value PARAM exports. */
6530 if (si_eliminate_const_output(ctx, cur, target)) {
6531 removed_any = true;
6532 } else {
6533 exports.offset[exports.num] = target;
6534 exports.inst[exports.num] = cur;
6535 exports.num++;
6536 }
6537 }
6538 bb = LLVMGetNextBasicBlock(bb);
6539 }
6540
6541 /* Remove holes in export memory due to removed PARAM exports.
6542 * This is done by renumbering all PARAM exports.
6543 */
6544 if (removed_any) {
6545 ubyte current_offset[SI_MAX_VS_OUTPUTS];
6546 unsigned new_count = 0;
6547 unsigned out, i;
6548
6549 /* Make a copy of the offsets. We need the old version while
6550 * we are modifying some of them. */
6551 assert(sizeof(current_offset) ==
6552 sizeof(shader->info.vs_output_param_offset));
6553 memcpy(current_offset, shader->info.vs_output_param_offset,
6554 sizeof(current_offset));
6555
6556 for (i = 0; i < exports.num; i++) {
6557 unsigned offset = exports.offset[i];
6558
6559 for (out = 0; out < info->num_outputs; out++) {
6560 if (current_offset[out] != offset)
6561 continue;
6562
6563 LLVMSetOperand(exports.inst[i], 3,
6564 LLVMConstInt(ctx->i32,
6565 V_008DFC_SQ_EXP_PARAM + new_count, 0));
6566 shader->info.vs_output_param_offset[out] = new_count;
6567 new_count++;
6568 break;
6569 }
6570 }
6571 shader->info.nr_param_exports = new_count;
6572 }
6573 }
6574
6575 static void si_count_scratch_private_memory(struct si_shader_context *ctx)
6576 {
6577 ctx->shader->config.private_mem_vgprs = 0;
6578
6579 /* Process all LLVM instructions. */
6580 LLVMBasicBlockRef bb = LLVMGetFirstBasicBlock(ctx->main_fn);
6581 while (bb) {
6582 LLVMValueRef next = LLVMGetFirstInstruction(bb);
6583
6584 while (next) {
6585 LLVMValueRef inst = next;
6586 next = LLVMGetNextInstruction(next);
6587
6588 if (LLVMGetInstructionOpcode(inst) != LLVMAlloca)
6589 continue;
6590
6591 LLVMTypeRef type = LLVMGetElementType(LLVMTypeOf(inst));
6592 /* No idea why LLVM aligns allocas to 4 elements. */
6593 unsigned alignment = LLVMGetAlignment(inst);
6594 unsigned dw_size = align(llvm_get_type_size(type) / 4, alignment);
6595 ctx->shader->config.private_mem_vgprs += dw_size;
6596 }
6597 bb = LLVMGetNextBasicBlock(bb);
6598 }
6599 }
6600
6601 static bool si_compile_tgsi_main(struct si_shader_context *ctx,
6602 struct si_shader *shader)
6603 {
6604 struct si_shader_selector *sel = shader->selector;
6605 struct lp_build_tgsi_context *bld_base = &ctx->soa.bld_base;
6606
6607 switch (ctx->type) {
6608 case PIPE_SHADER_VERTEX:
6609 ctx->load_input = declare_input_vs;
6610 if (shader->key.as_ls)
6611 bld_base->emit_epilogue = si_llvm_emit_ls_epilogue;
6612 else if (shader->key.as_es)
6613 bld_base->emit_epilogue = si_llvm_emit_es_epilogue;
6614 else
6615 bld_base->emit_epilogue = si_llvm_emit_vs_epilogue;
6616 break;
6617 case PIPE_SHADER_TESS_CTRL:
6618 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_tcs;
6619 bld_base->emit_fetch_funcs[TGSI_FILE_OUTPUT] = fetch_output_tcs;
6620 bld_base->emit_store = store_output_tcs;
6621 bld_base->emit_epilogue = si_llvm_emit_tcs_epilogue;
6622 break;
6623 case PIPE_SHADER_TESS_EVAL:
6624 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_tes;
6625 if (shader->key.as_es)
6626 bld_base->emit_epilogue = si_llvm_emit_es_epilogue;
6627 else
6628 bld_base->emit_epilogue = si_llvm_emit_vs_epilogue;
6629 break;
6630 case PIPE_SHADER_GEOMETRY:
6631 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_gs;
6632 bld_base->emit_epilogue = si_llvm_emit_gs_epilogue;
6633 break;
6634 case PIPE_SHADER_FRAGMENT:
6635 ctx->load_input = declare_input_fs;
6636 bld_base->emit_epilogue = si_llvm_return_fs_outputs;
6637 break;
6638 case PIPE_SHADER_COMPUTE:
6639 ctx->declare_memory_region = declare_compute_memory;
6640 break;
6641 default:
6642 assert(!"Unsupported shader type");
6643 return false;
6644 }
6645
6646 create_meta_data(ctx);
6647 create_function(ctx);
6648 preload_ring_buffers(ctx);
6649
6650 if (ctx->type == PIPE_SHADER_GEOMETRY) {
6651 int i;
6652 for (i = 0; i < 4; i++) {
6653 ctx->gs_next_vertex[i] =
6654 lp_build_alloca(bld_base->base.gallivm,
6655 ctx->i32, "");
6656 }
6657 }
6658
6659 if (!lp_build_tgsi_llvm(bld_base, sel->tokens)) {
6660 fprintf(stderr, "Failed to translate shader from TGSI to LLVM\n");
6661 return false;
6662 }
6663
6664 si_llvm_build_ret(ctx, ctx->return_value);
6665 return true;
6666 }
6667
6668 /**
6669 * Compute the VS prolog key, which contains all the information needed to
6670 * build the VS prolog function, and set shader->info bits where needed.
6671 */
6672 static void si_get_vs_prolog_key(struct si_shader *shader,
6673 union si_shader_part_key *key)
6674 {
6675 struct tgsi_shader_info *info = &shader->selector->info;
6676
6677 memset(key, 0, sizeof(*key));
6678 key->vs_prolog.states = shader->key.part.vs.prolog;
6679 key->vs_prolog.num_input_sgprs = shader->info.num_input_sgprs;
6680 key->vs_prolog.last_input = MAX2(1, info->num_inputs) - 1;
6681
6682 /* Set the instanceID flag. */
6683 for (unsigned i = 0; i < info->num_inputs; i++)
6684 if (key->vs_prolog.states.instance_divisors[i])
6685 shader->info.uses_instanceid = true;
6686 }
6687
6688 /**
6689 * Compute the VS epilog key, which contains all the information needed to
6690 * build the VS epilog function, and set the PrimitiveID output offset.
6691 */
6692 static void si_get_vs_epilog_key(struct si_shader *shader,
6693 struct si_vs_epilog_bits *states,
6694 union si_shader_part_key *key)
6695 {
6696 memset(key, 0, sizeof(*key));
6697 key->vs_epilog.states = *states;
6698
6699 /* Set up the PrimitiveID output. */
6700 if (shader->key.part.vs.epilog.export_prim_id) {
6701 unsigned index = shader->selector->info.num_outputs;
6702 unsigned offset = shader->info.nr_param_exports++;
6703
6704 key->vs_epilog.prim_id_param_offset = offset;
6705 assert(index < ARRAY_SIZE(shader->info.vs_output_param_offset));
6706 shader->info.vs_output_param_offset[index] = offset;
6707 }
6708 }
6709
6710 /**
6711 * Compute the PS prolog key, which contains all the information needed to
6712 * build the PS prolog function, and set related bits in shader->config.
6713 */
6714 static void si_get_ps_prolog_key(struct si_shader *shader,
6715 union si_shader_part_key *key,
6716 bool separate_prolog)
6717 {
6718 struct tgsi_shader_info *info = &shader->selector->info;
6719
6720 memset(key, 0, sizeof(*key));
6721 key->ps_prolog.states = shader->key.part.ps.prolog;
6722 key->ps_prolog.colors_read = info->colors_read;
6723 key->ps_prolog.num_input_sgprs = shader->info.num_input_sgprs;
6724 key->ps_prolog.num_input_vgprs = shader->info.num_input_vgprs;
6725 key->ps_prolog.wqm = info->uses_derivatives &&
6726 (key->ps_prolog.colors_read ||
6727 key->ps_prolog.states.force_persp_sample_interp ||
6728 key->ps_prolog.states.force_linear_sample_interp ||
6729 key->ps_prolog.states.force_persp_center_interp ||
6730 key->ps_prolog.states.force_linear_center_interp ||
6731 key->ps_prolog.states.bc_optimize_for_persp ||
6732 key->ps_prolog.states.bc_optimize_for_linear);
6733
6734 if (info->colors_read) {
6735 unsigned *color = shader->selector->color_attr_index;
6736
6737 if (shader->key.part.ps.prolog.color_two_side) {
6738 /* BCOLORs are stored after the last input. */
6739 key->ps_prolog.num_interp_inputs = info->num_inputs;
6740 key->ps_prolog.face_vgpr_index = shader->info.face_vgpr_index;
6741 shader->config.spi_ps_input_ena |= S_0286CC_FRONT_FACE_ENA(1);
6742 }
6743
6744 for (unsigned i = 0; i < 2; i++) {
6745 unsigned interp = info->input_interpolate[color[i]];
6746 unsigned location = info->input_interpolate_loc[color[i]];
6747
6748 if (!(info->colors_read & (0xf << i*4)))
6749 continue;
6750
6751 key->ps_prolog.color_attr_index[i] = color[i];
6752
6753 if (shader->key.part.ps.prolog.flatshade_colors &&
6754 interp == TGSI_INTERPOLATE_COLOR)
6755 interp = TGSI_INTERPOLATE_CONSTANT;
6756
6757 switch (interp) {
6758 case TGSI_INTERPOLATE_CONSTANT:
6759 key->ps_prolog.color_interp_vgpr_index[i] = -1;
6760 break;
6761 case TGSI_INTERPOLATE_PERSPECTIVE:
6762 case TGSI_INTERPOLATE_COLOR:
6763 /* Force the interpolation location for colors here. */
6764 if (shader->key.part.ps.prolog.force_persp_sample_interp)
6765 location = TGSI_INTERPOLATE_LOC_SAMPLE;
6766 if (shader->key.part.ps.prolog.force_persp_center_interp)
6767 location = TGSI_INTERPOLATE_LOC_CENTER;
6768
6769 switch (location) {
6770 case TGSI_INTERPOLATE_LOC_SAMPLE:
6771 key->ps_prolog.color_interp_vgpr_index[i] = 0;
6772 shader->config.spi_ps_input_ena |=
6773 S_0286CC_PERSP_SAMPLE_ENA(1);
6774 break;
6775 case TGSI_INTERPOLATE_LOC_CENTER:
6776 key->ps_prolog.color_interp_vgpr_index[i] = 2;
6777 shader->config.spi_ps_input_ena |=
6778 S_0286CC_PERSP_CENTER_ENA(1);
6779 break;
6780 case TGSI_INTERPOLATE_LOC_CENTROID:
6781 key->ps_prolog.color_interp_vgpr_index[i] = 4;
6782 shader->config.spi_ps_input_ena |=
6783 S_0286CC_PERSP_CENTROID_ENA(1);
6784 break;
6785 default:
6786 assert(0);
6787 }
6788 break;
6789 case TGSI_INTERPOLATE_LINEAR:
6790 /* Force the interpolation location for colors here. */
6791 if (shader->key.part.ps.prolog.force_linear_sample_interp)
6792 location = TGSI_INTERPOLATE_LOC_SAMPLE;
6793 if (shader->key.part.ps.prolog.force_linear_center_interp)
6794 location = TGSI_INTERPOLATE_LOC_CENTER;
6795
6796 /* The VGPR assignment for non-monolithic shaders
6797 * works because InitialPSInputAddr is set on the
6798 * main shader and PERSP_PULL_MODEL is never used.
6799 */
6800 switch (location) {
6801 case TGSI_INTERPOLATE_LOC_SAMPLE:
6802 key->ps_prolog.color_interp_vgpr_index[i] =
6803 separate_prolog ? 6 : 9;
6804 shader->config.spi_ps_input_ena |=
6805 S_0286CC_LINEAR_SAMPLE_ENA(1);
6806 break;
6807 case TGSI_INTERPOLATE_LOC_CENTER:
6808 key->ps_prolog.color_interp_vgpr_index[i] =
6809 separate_prolog ? 8 : 11;
6810 shader->config.spi_ps_input_ena |=
6811 S_0286CC_LINEAR_CENTER_ENA(1);
6812 break;
6813 case TGSI_INTERPOLATE_LOC_CENTROID:
6814 key->ps_prolog.color_interp_vgpr_index[i] =
6815 separate_prolog ? 10 : 13;
6816 shader->config.spi_ps_input_ena |=
6817 S_0286CC_LINEAR_CENTROID_ENA(1);
6818 break;
6819 default:
6820 assert(0);
6821 }
6822 break;
6823 default:
6824 assert(0);
6825 }
6826 }
6827 }
6828 }
6829
6830 /**
6831 * Check whether a PS prolog is required based on the key.
6832 */
6833 static bool si_need_ps_prolog(const union si_shader_part_key *key)
6834 {
6835 return key->ps_prolog.colors_read ||
6836 key->ps_prolog.states.force_persp_sample_interp ||
6837 key->ps_prolog.states.force_linear_sample_interp ||
6838 key->ps_prolog.states.force_persp_center_interp ||
6839 key->ps_prolog.states.force_linear_center_interp ||
6840 key->ps_prolog.states.bc_optimize_for_persp ||
6841 key->ps_prolog.states.bc_optimize_for_linear ||
6842 key->ps_prolog.states.poly_stipple;
6843 }
6844
6845 /**
6846 * Compute the PS epilog key, which contains all the information needed to
6847 * build the PS epilog function.
6848 */
6849 static void si_get_ps_epilog_key(struct si_shader *shader,
6850 union si_shader_part_key *key)
6851 {
6852 struct tgsi_shader_info *info = &shader->selector->info;
6853 memset(key, 0, sizeof(*key));
6854 key->ps_epilog.colors_written = info->colors_written;
6855 key->ps_epilog.writes_z = info->writes_z;
6856 key->ps_epilog.writes_stencil = info->writes_stencil;
6857 key->ps_epilog.writes_samplemask = info->writes_samplemask;
6858 key->ps_epilog.states = shader->key.part.ps.epilog;
6859 }
6860
6861 /**
6862 * Build the GS prolog function. Rotate the input vertices for triangle strips
6863 * with adjacency.
6864 */
6865 static void si_build_gs_prolog_function(struct si_shader_context *ctx,
6866 union si_shader_part_key *key)
6867 {
6868 const unsigned num_sgprs = SI_GS_NUM_USER_SGPR + 2;
6869 const unsigned num_vgprs = 8;
6870 struct gallivm_state *gallivm = &ctx->gallivm;
6871 LLVMBuilderRef builder = gallivm->builder;
6872 LLVMTypeRef params[32];
6873 LLVMTypeRef returns[32];
6874 LLVMValueRef func, ret;
6875
6876 for (unsigned i = 0; i < num_sgprs; ++i) {
6877 params[i] = ctx->i32;
6878 returns[i] = ctx->i32;
6879 }
6880
6881 for (unsigned i = 0; i < num_vgprs; ++i) {
6882 params[num_sgprs + i] = ctx->i32;
6883 returns[num_sgprs + i] = ctx->f32;
6884 }
6885
6886 /* Create the function. */
6887 si_create_function(ctx, "gs_prolog", returns, num_sgprs + num_vgprs,
6888 params, num_sgprs + num_vgprs, num_sgprs - 1);
6889 func = ctx->main_fn;
6890
6891 /* Copy inputs to outputs. This should be no-op, as the registers match,
6892 * but it will prevent the compiler from overwriting them unintentionally.
6893 */
6894 ret = ctx->return_value;
6895 for (unsigned i = 0; i < num_sgprs; i++) {
6896 LLVMValueRef p = LLVMGetParam(func, i);
6897 ret = LLVMBuildInsertValue(builder, ret, p, i, "");
6898 }
6899 for (unsigned i = 0; i < num_vgprs; i++) {
6900 LLVMValueRef p = LLVMGetParam(func, num_sgprs + i);
6901 p = LLVMBuildBitCast(builder, p, ctx->f32, "");
6902 ret = LLVMBuildInsertValue(builder, ret, p, num_sgprs + i, "");
6903 }
6904
6905 if (key->gs_prolog.states.tri_strip_adj_fix) {
6906 /* Remap the input vertices for every other primitive. */
6907 const unsigned vtx_params[6] = {
6908 num_sgprs,
6909 num_sgprs + 1,
6910 num_sgprs + 3,
6911 num_sgprs + 4,
6912 num_sgprs + 5,
6913 num_sgprs + 6
6914 };
6915 LLVMValueRef prim_id, rotate;
6916
6917 prim_id = LLVMGetParam(func, num_sgprs + 2);
6918 rotate = LLVMBuildTrunc(builder, prim_id, ctx->i1, "");
6919
6920 for (unsigned i = 0; i < 6; ++i) {
6921 LLVMValueRef base, rotated, actual;
6922 base = LLVMGetParam(func, vtx_params[i]);
6923 rotated = LLVMGetParam(func, vtx_params[(i + 4) % 6]);
6924 actual = LLVMBuildSelect(builder, rotate, rotated, base, "");
6925 actual = LLVMBuildBitCast(builder, actual, ctx->f32, "");
6926 ret = LLVMBuildInsertValue(builder, ret, actual, vtx_params[i], "");
6927 }
6928 }
6929
6930 LLVMBuildRet(builder, ret);
6931 }
6932
6933 /**
6934 * Given a list of shader part functions, build a wrapper function that
6935 * runs them in sequence to form a monolithic shader.
6936 */
6937 static void si_build_wrapper_function(struct si_shader_context *ctx,
6938 LLVMValueRef *parts,
6939 unsigned num_parts,
6940 unsigned main_part)
6941 {
6942 struct gallivm_state *gallivm = &ctx->gallivm;
6943 LLVMBuilderRef builder = ctx->gallivm.builder;
6944 /* PS epilog has one arg per color component */
6945 LLVMTypeRef param_types[48];
6946 LLVMValueRef out[48];
6947 LLVMTypeRef function_type;
6948 unsigned num_params;
6949 unsigned num_out;
6950 MAYBE_UNUSED unsigned num_out_sgpr; /* used in debug checks */
6951 unsigned num_sgprs, num_vgprs;
6952 unsigned last_sgpr_param;
6953 unsigned gprs;
6954
6955 for (unsigned i = 0; i < num_parts; ++i) {
6956 lp_add_function_attr(parts[i], -1, LP_FUNC_ATTR_ALWAYSINLINE);
6957 LLVMSetLinkage(parts[i], LLVMPrivateLinkage);
6958 }
6959
6960 /* The parameters of the wrapper function correspond to those of the
6961 * first part in terms of SGPRs and VGPRs, but we use the types of the
6962 * main part to get the right types. This is relevant for the
6963 * dereferenceable attribute on descriptor table pointers.
6964 */
6965 num_sgprs = 0;
6966 num_vgprs = 0;
6967
6968 function_type = LLVMGetElementType(LLVMTypeOf(parts[0]));
6969 num_params = LLVMCountParamTypes(function_type);
6970
6971 for (unsigned i = 0; i < num_params; ++i) {
6972 LLVMValueRef param = LLVMGetParam(parts[0], i);
6973
6974 if (ac_is_sgpr_param(param)) {
6975 assert(num_vgprs == 0);
6976 num_sgprs += llvm_get_type_size(LLVMTypeOf(param)) / 4;
6977 } else {
6978 num_vgprs += llvm_get_type_size(LLVMTypeOf(param)) / 4;
6979 }
6980 }
6981 assert(num_vgprs + num_sgprs <= ARRAY_SIZE(param_types));
6982
6983 num_params = 0;
6984 last_sgpr_param = 0;
6985 gprs = 0;
6986 while (gprs < num_sgprs + num_vgprs) {
6987 LLVMValueRef param = LLVMGetParam(parts[main_part], num_params);
6988 unsigned size;
6989
6990 param_types[num_params] = LLVMTypeOf(param);
6991 if (gprs < num_sgprs)
6992 last_sgpr_param = num_params;
6993 size = llvm_get_type_size(param_types[num_params]) / 4;
6994 num_params++;
6995
6996 assert(ac_is_sgpr_param(param) == (gprs < num_sgprs));
6997 assert(gprs + size <= num_sgprs + num_vgprs &&
6998 (gprs >= num_sgprs || gprs + size <= num_sgprs));
6999
7000 gprs += size;
7001 }
7002
7003 si_create_function(ctx, "wrapper", NULL, 0, param_types, num_params, last_sgpr_param);
7004
7005 /* Record the arguments of the function as if they were an output of
7006 * a previous part.
7007 */
7008 num_out = 0;
7009 num_out_sgpr = 0;
7010
7011 for (unsigned i = 0; i < num_params; ++i) {
7012 LLVMValueRef param = LLVMGetParam(ctx->main_fn, i);
7013 LLVMTypeRef param_type = LLVMTypeOf(param);
7014 LLVMTypeRef out_type = i <= last_sgpr_param ? ctx->i32 : ctx->f32;
7015 unsigned size = llvm_get_type_size(param_type) / 4;
7016
7017 if (size == 1) {
7018 if (param_type != out_type)
7019 param = LLVMBuildBitCast(builder, param, out_type, "");
7020 out[num_out++] = param;
7021 } else {
7022 LLVMTypeRef vector_type = LLVMVectorType(out_type, size);
7023
7024 if (LLVMGetTypeKind(param_type) == LLVMPointerTypeKind) {
7025 param = LLVMBuildPtrToInt(builder, param, ctx->i64, "");
7026 param_type = ctx->i64;
7027 }
7028
7029 if (param_type != vector_type)
7030 param = LLVMBuildBitCast(builder, param, vector_type, "");
7031
7032 for (unsigned j = 0; j < size; ++j)
7033 out[num_out++] = LLVMBuildExtractElement(
7034 builder, param, LLVMConstInt(ctx->i32, j, 0), "");
7035 }
7036
7037 if (i <= last_sgpr_param)
7038 num_out_sgpr = num_out;
7039 }
7040
7041 /* Now chain the parts. */
7042 for (unsigned part = 0; part < num_parts; ++part) {
7043 LLVMValueRef in[48];
7044 LLVMValueRef ret;
7045 LLVMTypeRef ret_type;
7046 unsigned out_idx = 0;
7047
7048 num_params = LLVMCountParams(parts[part]);
7049 assert(num_params <= ARRAY_SIZE(param_types));
7050
7051 /* Derive arguments for the next part from outputs of the
7052 * previous one.
7053 */
7054 for (unsigned param_idx = 0; param_idx < num_params; ++param_idx) {
7055 LLVMValueRef param;
7056 LLVMTypeRef param_type;
7057 bool is_sgpr;
7058 unsigned param_size;
7059 LLVMValueRef arg = NULL;
7060
7061 param = LLVMGetParam(parts[part], param_idx);
7062 param_type = LLVMTypeOf(param);
7063 param_size = llvm_get_type_size(param_type) / 4;
7064 is_sgpr = ac_is_sgpr_param(param);
7065
7066 if (is_sgpr) {
7067 #if HAVE_LLVM < 0x0400
7068 LLVMRemoveAttribute(param, LLVMByValAttribute);
7069 #else
7070 unsigned kind_id = LLVMGetEnumAttributeKindForName("byval", 5);
7071 LLVMRemoveEnumAttributeAtIndex(parts[part], param_idx + 1, kind_id);
7072 #endif
7073 lp_add_function_attr(parts[part], param_idx + 1, LP_FUNC_ATTR_INREG);
7074 }
7075
7076 assert(out_idx + param_size <= (is_sgpr ? num_out_sgpr : num_out));
7077 assert(is_sgpr || out_idx >= num_out_sgpr);
7078
7079 if (param_size == 1)
7080 arg = out[out_idx];
7081 else
7082 arg = lp_build_gather_values(gallivm, &out[out_idx], param_size);
7083
7084 if (LLVMTypeOf(arg) != param_type) {
7085 if (LLVMGetTypeKind(param_type) == LLVMPointerTypeKind) {
7086 arg = LLVMBuildBitCast(builder, arg, ctx->i64, "");
7087 arg = LLVMBuildIntToPtr(builder, arg, param_type, "");
7088 } else {
7089 arg = LLVMBuildBitCast(builder, arg, param_type, "");
7090 }
7091 }
7092
7093 in[param_idx] = arg;
7094 out_idx += param_size;
7095 }
7096
7097 ret = LLVMBuildCall(builder, parts[part], in, num_params, "");
7098 ret_type = LLVMTypeOf(ret);
7099
7100 /* Extract the returned GPRs. */
7101 num_out = 0;
7102 num_out_sgpr = 0;
7103
7104 if (LLVMGetTypeKind(ret_type) != LLVMVoidTypeKind) {
7105 assert(LLVMGetTypeKind(ret_type) == LLVMStructTypeKind);
7106
7107 unsigned ret_size = LLVMCountStructElementTypes(ret_type);
7108
7109 for (unsigned i = 0; i < ret_size; ++i) {
7110 LLVMValueRef val =
7111 LLVMBuildExtractValue(builder, ret, i, "");
7112
7113 out[num_out++] = val;
7114
7115 if (LLVMTypeOf(val) == ctx->i32) {
7116 assert(num_out_sgpr + 1 == num_out);
7117 num_out_sgpr = num_out;
7118 }
7119 }
7120 }
7121 }
7122
7123 LLVMBuildRetVoid(builder);
7124 }
7125
7126 int si_compile_tgsi_shader(struct si_screen *sscreen,
7127 LLVMTargetMachineRef tm,
7128 struct si_shader *shader,
7129 bool is_monolithic,
7130 struct pipe_debug_callback *debug)
7131 {
7132 struct si_shader_selector *sel = shader->selector;
7133 struct si_shader_context ctx;
7134 struct lp_build_tgsi_context *bld_base;
7135 LLVMModuleRef mod;
7136 int r = -1;
7137
7138 /* Dump TGSI code before doing TGSI->LLVM conversion in case the
7139 * conversion fails. */
7140 if (r600_can_dump_shader(&sscreen->b, sel->info.processor) &&
7141 !(sscreen->b.debug_flags & DBG_NO_TGSI)) {
7142 tgsi_dump(sel->tokens, 0);
7143 si_dump_streamout(&sel->so);
7144 }
7145
7146 si_init_shader_ctx(&ctx, sscreen, shader, tm);
7147 ctx.separate_prolog = !is_monolithic;
7148
7149 memset(shader->info.vs_output_param_offset, EXP_PARAM_UNDEFINED,
7150 sizeof(shader->info.vs_output_param_offset));
7151
7152 shader->info.uses_instanceid = sel->info.uses_instanceid;
7153
7154 bld_base = &ctx.soa.bld_base;
7155 ctx.load_system_value = declare_system_value;
7156
7157 if (!si_compile_tgsi_main(&ctx, shader)) {
7158 si_llvm_dispose(&ctx);
7159 return -1;
7160 }
7161
7162 if (is_monolithic && ctx.type == PIPE_SHADER_VERTEX) {
7163 LLVMValueRef parts[3];
7164 bool need_prolog;
7165 bool need_epilog;
7166
7167 need_prolog = sel->info.num_inputs;
7168 need_epilog = !shader->key.as_es && !shader->key.as_ls;
7169
7170 parts[need_prolog ? 1 : 0] = ctx.main_fn;
7171
7172 if (need_prolog) {
7173 union si_shader_part_key prolog_key;
7174 si_get_vs_prolog_key(shader, &prolog_key);
7175 si_build_vs_prolog_function(&ctx, &prolog_key);
7176 parts[0] = ctx.main_fn;
7177 }
7178
7179 if (need_epilog) {
7180 union si_shader_part_key epilog_key;
7181 si_get_vs_epilog_key(shader, &shader->key.part.vs.epilog, &epilog_key);
7182 si_build_vs_epilog_function(&ctx, &epilog_key);
7183 parts[need_prolog ? 2 : 1] = ctx.main_fn;
7184 }
7185
7186 si_build_wrapper_function(&ctx, parts, 1 + need_prolog + need_epilog,
7187 need_prolog ? 1 : 0);
7188 } else if (is_monolithic && ctx.type == PIPE_SHADER_TESS_CTRL) {
7189 LLVMValueRef parts[2];
7190 union si_shader_part_key epilog_key;
7191
7192 parts[0] = ctx.main_fn;
7193
7194 memset(&epilog_key, 0, sizeof(epilog_key));
7195 epilog_key.tcs_epilog.states = shader->key.part.tcs.epilog;
7196 si_build_tcs_epilog_function(&ctx, &epilog_key);
7197 parts[1] = ctx.main_fn;
7198
7199 si_build_wrapper_function(&ctx, parts, 2, 0);
7200 } else if (is_monolithic && ctx.type == PIPE_SHADER_TESS_EVAL &&
7201 !shader->key.as_es) {
7202 LLVMValueRef parts[2];
7203 union si_shader_part_key epilog_key;
7204
7205 parts[0] = ctx.main_fn;
7206
7207 si_get_vs_epilog_key(shader, &shader->key.part.tes.epilog, &epilog_key);
7208 si_build_vs_epilog_function(&ctx, &epilog_key);
7209 parts[1] = ctx.main_fn;
7210
7211 si_build_wrapper_function(&ctx, parts, 2, 0);
7212 } else if (is_monolithic && ctx.type == PIPE_SHADER_GEOMETRY) {
7213 LLVMValueRef parts[2];
7214 union si_shader_part_key prolog_key;
7215
7216 parts[1] = ctx.main_fn;
7217
7218 memset(&prolog_key, 0, sizeof(prolog_key));
7219 prolog_key.gs_prolog.states = shader->key.part.gs.prolog;
7220 si_build_gs_prolog_function(&ctx, &prolog_key);
7221 parts[0] = ctx.main_fn;
7222
7223 si_build_wrapper_function(&ctx, parts, 2, 1);
7224 } else if (is_monolithic && ctx.type == PIPE_SHADER_FRAGMENT) {
7225 LLVMValueRef parts[3];
7226 union si_shader_part_key prolog_key;
7227 union si_shader_part_key epilog_key;
7228 bool need_prolog;
7229
7230 si_get_ps_prolog_key(shader, &prolog_key, false);
7231 need_prolog = si_need_ps_prolog(&prolog_key);
7232
7233 parts[need_prolog ? 1 : 0] = ctx.main_fn;
7234
7235 if (need_prolog) {
7236 si_build_ps_prolog_function(&ctx, &prolog_key);
7237 parts[0] = ctx.main_fn;
7238 }
7239
7240 si_get_ps_epilog_key(shader, &epilog_key);
7241 si_build_ps_epilog_function(&ctx, &epilog_key);
7242 parts[need_prolog ? 2 : 1] = ctx.main_fn;
7243
7244 si_build_wrapper_function(&ctx, parts, need_prolog ? 3 : 2, need_prolog ? 1 : 0);
7245 }
7246
7247 mod = bld_base->base.gallivm->module;
7248
7249 /* Dump LLVM IR before any optimization passes */
7250 if (sscreen->b.debug_flags & DBG_PREOPT_IR &&
7251 r600_can_dump_shader(&sscreen->b, ctx.type))
7252 LLVMDumpModule(mod);
7253
7254 si_llvm_finalize_module(&ctx,
7255 r600_extra_shader_checks(&sscreen->b, ctx.type));
7256
7257 /* Post-optimization transformations and analysis. */
7258 si_eliminate_const_vs_outputs(&ctx);
7259
7260 if ((debug && debug->debug_message) ||
7261 r600_can_dump_shader(&sscreen->b, ctx.type))
7262 si_count_scratch_private_memory(&ctx);
7263
7264 /* Compile to bytecode. */
7265 r = si_compile_llvm(sscreen, &shader->binary, &shader->config, tm,
7266 mod, debug, ctx.type, "TGSI shader");
7267 si_llvm_dispose(&ctx);
7268 if (r) {
7269 fprintf(stderr, "LLVM failed to compile shader\n");
7270 return r;
7271 }
7272
7273 /* Validate SGPR and VGPR usage for compute to detect compiler bugs.
7274 * LLVM 3.9svn has this bug.
7275 */
7276 if (sel->type == PIPE_SHADER_COMPUTE) {
7277 unsigned wave_size = 64;
7278 unsigned max_vgprs = 256;
7279 unsigned max_sgprs = sscreen->b.chip_class >= VI ? 800 : 512;
7280 unsigned max_sgprs_per_wave = 128;
7281 unsigned max_block_threads = si_get_max_workgroup_size(shader);
7282 unsigned min_waves_per_cu = DIV_ROUND_UP(max_block_threads, wave_size);
7283 unsigned min_waves_per_simd = DIV_ROUND_UP(min_waves_per_cu, 4);
7284
7285 max_vgprs = max_vgprs / min_waves_per_simd;
7286 max_sgprs = MIN2(max_sgprs / min_waves_per_simd, max_sgprs_per_wave);
7287
7288 if (shader->config.num_sgprs > max_sgprs ||
7289 shader->config.num_vgprs > max_vgprs) {
7290 fprintf(stderr, "LLVM failed to compile a shader correctly: "
7291 "SGPR:VGPR usage is %u:%u, but the hw limit is %u:%u\n",
7292 shader->config.num_sgprs, shader->config.num_vgprs,
7293 max_sgprs, max_vgprs);
7294
7295 /* Just terminate the process, because dependent
7296 * shaders can hang due to bad input data, but use
7297 * the env var to allow shader-db to work.
7298 */
7299 if (!debug_get_bool_option("SI_PASS_BAD_SHADERS", false))
7300 abort();
7301 }
7302 }
7303
7304 /* Add the scratch offset to input SGPRs. */
7305 if (shader->config.scratch_bytes_per_wave)
7306 shader->info.num_input_sgprs += 1; /* scratch byte offset */
7307
7308 /* Calculate the number of fragment input VGPRs. */
7309 if (ctx.type == PIPE_SHADER_FRAGMENT) {
7310 shader->info.num_input_vgprs = 0;
7311 shader->info.face_vgpr_index = -1;
7312
7313 if (G_0286CC_PERSP_SAMPLE_ENA(shader->config.spi_ps_input_addr))
7314 shader->info.num_input_vgprs += 2;
7315 if (G_0286CC_PERSP_CENTER_ENA(shader->config.spi_ps_input_addr))
7316 shader->info.num_input_vgprs += 2;
7317 if (G_0286CC_PERSP_CENTROID_ENA(shader->config.spi_ps_input_addr))
7318 shader->info.num_input_vgprs += 2;
7319 if (G_0286CC_PERSP_PULL_MODEL_ENA(shader->config.spi_ps_input_addr))
7320 shader->info.num_input_vgprs += 3;
7321 if (G_0286CC_LINEAR_SAMPLE_ENA(shader->config.spi_ps_input_addr))
7322 shader->info.num_input_vgprs += 2;
7323 if (G_0286CC_LINEAR_CENTER_ENA(shader->config.spi_ps_input_addr))
7324 shader->info.num_input_vgprs += 2;
7325 if (G_0286CC_LINEAR_CENTROID_ENA(shader->config.spi_ps_input_addr))
7326 shader->info.num_input_vgprs += 2;
7327 if (G_0286CC_LINE_STIPPLE_TEX_ENA(shader->config.spi_ps_input_addr))
7328 shader->info.num_input_vgprs += 1;
7329 if (G_0286CC_POS_X_FLOAT_ENA(shader->config.spi_ps_input_addr))
7330 shader->info.num_input_vgprs += 1;
7331 if (G_0286CC_POS_Y_FLOAT_ENA(shader->config.spi_ps_input_addr))
7332 shader->info.num_input_vgprs += 1;
7333 if (G_0286CC_POS_Z_FLOAT_ENA(shader->config.spi_ps_input_addr))
7334 shader->info.num_input_vgprs += 1;
7335 if (G_0286CC_POS_W_FLOAT_ENA(shader->config.spi_ps_input_addr))
7336 shader->info.num_input_vgprs += 1;
7337 if (G_0286CC_FRONT_FACE_ENA(shader->config.spi_ps_input_addr)) {
7338 shader->info.face_vgpr_index = shader->info.num_input_vgprs;
7339 shader->info.num_input_vgprs += 1;
7340 }
7341 if (G_0286CC_ANCILLARY_ENA(shader->config.spi_ps_input_addr))
7342 shader->info.num_input_vgprs += 1;
7343 if (G_0286CC_SAMPLE_COVERAGE_ENA(shader->config.spi_ps_input_addr))
7344 shader->info.num_input_vgprs += 1;
7345 if (G_0286CC_POS_FIXED_PT_ENA(shader->config.spi_ps_input_addr))
7346 shader->info.num_input_vgprs += 1;
7347 }
7348
7349 return 0;
7350 }
7351
7352 /**
7353 * Create, compile and return a shader part (prolog or epilog).
7354 *
7355 * \param sscreen screen
7356 * \param list list of shader parts of the same category
7357 * \param type shader type
7358 * \param key shader part key
7359 * \param prolog whether the part being requested is a prolog
7360 * \param tm LLVM target machine
7361 * \param debug debug callback
7362 * \param build the callback responsible for building the main function
7363 * \return non-NULL on success
7364 */
7365 static struct si_shader_part *
7366 si_get_shader_part(struct si_screen *sscreen,
7367 struct si_shader_part **list,
7368 enum pipe_shader_type type,
7369 bool prolog,
7370 union si_shader_part_key *key,
7371 LLVMTargetMachineRef tm,
7372 struct pipe_debug_callback *debug,
7373 void (*build)(struct si_shader_context *,
7374 union si_shader_part_key *),
7375 const char *name)
7376 {
7377 struct si_shader_part *result;
7378
7379 pipe_mutex_lock(sscreen->shader_parts_mutex);
7380
7381 /* Find existing. */
7382 for (result = *list; result; result = result->next) {
7383 if (memcmp(&result->key, key, sizeof(*key)) == 0) {
7384 pipe_mutex_unlock(sscreen->shader_parts_mutex);
7385 return result;
7386 }
7387 }
7388
7389 /* Compile a new one. */
7390 result = CALLOC_STRUCT(si_shader_part);
7391 result->key = *key;
7392
7393 struct si_shader shader = {};
7394 struct si_shader_context ctx;
7395 struct gallivm_state *gallivm = &ctx.gallivm;
7396
7397 si_init_shader_ctx(&ctx, sscreen, &shader, tm);
7398 ctx.type = type;
7399
7400 switch (type) {
7401 case PIPE_SHADER_VERTEX:
7402 break;
7403 case PIPE_SHADER_TESS_CTRL:
7404 assert(!prolog);
7405 shader.key.part.tcs.epilog = key->tcs_epilog.states;
7406 break;
7407 case PIPE_SHADER_GEOMETRY:
7408 assert(prolog);
7409 break;
7410 case PIPE_SHADER_FRAGMENT:
7411 if (prolog)
7412 shader.key.part.ps.prolog = key->ps_prolog.states;
7413 else
7414 shader.key.part.ps.epilog = key->ps_epilog.states;
7415 break;
7416 default:
7417 unreachable("bad shader part");
7418 }
7419
7420 build(&ctx, key);
7421
7422 /* Compile. */
7423 si_llvm_finalize_module(&ctx,
7424 r600_extra_shader_checks(&sscreen->b, PIPE_SHADER_FRAGMENT));
7425
7426 if (si_compile_llvm(sscreen, &result->binary, &result->config, tm,
7427 gallivm->module, debug, ctx.type, name)) {
7428 FREE(result);
7429 result = NULL;
7430 goto out;
7431 }
7432
7433 result->next = *list;
7434 *list = result;
7435
7436 out:
7437 si_llvm_dispose(&ctx);
7438 pipe_mutex_unlock(sscreen->shader_parts_mutex);
7439 return result;
7440 }
7441
7442 /**
7443 * Build the vertex shader prolog function.
7444 *
7445 * The inputs are the same as VS (a lot of SGPRs and 4 VGPR system values).
7446 * All inputs are returned unmodified. The vertex load indices are
7447 * stored after them, which will be used by the API VS for fetching inputs.
7448 *
7449 * For example, the expected outputs for instance_divisors[] = {0, 1, 2} are:
7450 * input_v0,
7451 * input_v1,
7452 * input_v2,
7453 * input_v3,
7454 * (VertexID + BaseVertex),
7455 * (InstanceID + StartInstance),
7456 * (InstanceID / 2 + StartInstance)
7457 */
7458 static void si_build_vs_prolog_function(struct si_shader_context *ctx,
7459 union si_shader_part_key *key)
7460 {
7461 struct gallivm_state *gallivm = &ctx->gallivm;
7462 LLVMTypeRef *params, *returns;
7463 LLVMValueRef ret, func;
7464 int last_sgpr, num_params, num_returns, i;
7465
7466 ctx->param_vertex_id = key->vs_prolog.num_input_sgprs;
7467 ctx->param_instance_id = key->vs_prolog.num_input_sgprs + 3;
7468
7469 /* 4 preloaded VGPRs + vertex load indices as prolog outputs */
7470 params = alloca((key->vs_prolog.num_input_sgprs + 4) *
7471 sizeof(LLVMTypeRef));
7472 returns = alloca((key->vs_prolog.num_input_sgprs + 4 +
7473 key->vs_prolog.last_input + 1) *
7474 sizeof(LLVMTypeRef));
7475 num_params = 0;
7476 num_returns = 0;
7477
7478 /* Declare input and output SGPRs. */
7479 num_params = 0;
7480 for (i = 0; i < key->vs_prolog.num_input_sgprs; i++) {
7481 params[num_params++] = ctx->i32;
7482 returns[num_returns++] = ctx->i32;
7483 }
7484 last_sgpr = num_params - 1;
7485
7486 /* 4 preloaded VGPRs (outputs must be floats) */
7487 for (i = 0; i < 4; i++) {
7488 params[num_params++] = ctx->i32;
7489 returns[num_returns++] = ctx->f32;
7490 }
7491
7492 /* Vertex load indices. */
7493 for (i = 0; i <= key->vs_prolog.last_input; i++)
7494 returns[num_returns++] = ctx->f32;
7495
7496 /* Create the function. */
7497 si_create_function(ctx, "vs_prolog", returns, num_returns, params,
7498 num_params, last_sgpr);
7499 func = ctx->main_fn;
7500
7501 /* Copy inputs to outputs. This should be no-op, as the registers match,
7502 * but it will prevent the compiler from overwriting them unintentionally.
7503 */
7504 ret = ctx->return_value;
7505 for (i = 0; i < key->vs_prolog.num_input_sgprs; i++) {
7506 LLVMValueRef p = LLVMGetParam(func, i);
7507 ret = LLVMBuildInsertValue(gallivm->builder, ret, p, i, "");
7508 }
7509 for (i = num_params - 4; i < num_params; i++) {
7510 LLVMValueRef p = LLVMGetParam(func, i);
7511 p = LLVMBuildBitCast(gallivm->builder, p, ctx->f32, "");
7512 ret = LLVMBuildInsertValue(gallivm->builder, ret, p, i, "");
7513 }
7514
7515 /* Compute vertex load indices from instance divisors. */
7516 for (i = 0; i <= key->vs_prolog.last_input; i++) {
7517 unsigned divisor = key->vs_prolog.states.instance_divisors[i];
7518 LLVMValueRef index;
7519
7520 if (divisor) {
7521 /* InstanceID / Divisor + StartInstance */
7522 index = get_instance_index_for_fetch(ctx,
7523 SI_SGPR_START_INSTANCE,
7524 divisor);
7525 } else {
7526 /* VertexID + BaseVertex */
7527 index = LLVMBuildAdd(gallivm->builder,
7528 LLVMGetParam(func, ctx->param_vertex_id),
7529 LLVMGetParam(func, SI_SGPR_BASE_VERTEX), "");
7530 }
7531
7532 index = LLVMBuildBitCast(gallivm->builder, index, ctx->f32, "");
7533 ret = LLVMBuildInsertValue(gallivm->builder, ret, index,
7534 num_params++, "");
7535 }
7536
7537 si_llvm_build_ret(ctx, ret);
7538 }
7539
7540 /**
7541 * Build the vertex shader epilog function. This is also used by the tessellation
7542 * evaluation shader compiled as VS.
7543 *
7544 * The input is PrimitiveID.
7545 *
7546 * If PrimitiveID is required by the pixel shader, export it.
7547 * Otherwise, do nothing.
7548 */
7549 static void si_build_vs_epilog_function(struct si_shader_context *ctx,
7550 union si_shader_part_key *key)
7551 {
7552 struct gallivm_state *gallivm = &ctx->gallivm;
7553 struct lp_build_tgsi_context *bld_base = &ctx->soa.bld_base;
7554 LLVMTypeRef params[5];
7555 int num_params, i;
7556
7557 /* Declare input VGPRs. */
7558 num_params = key->vs_epilog.states.export_prim_id ?
7559 (VS_EPILOG_PRIMID_LOC + 1) : 0;
7560 assert(num_params <= ARRAY_SIZE(params));
7561
7562 for (i = 0; i < num_params; i++)
7563 params[i] = ctx->f32;
7564
7565 /* Create the function. */
7566 si_create_function(ctx, "vs_epilog", NULL, 0, params, num_params, -1);
7567
7568 /* Emit exports. */
7569 if (key->vs_epilog.states.export_prim_id) {
7570 struct lp_build_context *base = &bld_base->base;
7571 struct lp_build_context *uint = &bld_base->uint_bld;
7572 LLVMValueRef args[9];
7573
7574 args[0] = lp_build_const_int32(base->gallivm, 0x0); /* enabled channels */
7575 args[1] = uint->zero; /* whether the EXEC mask is valid */
7576 args[2] = uint->zero; /* DONE bit */
7577 args[3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_PARAM +
7578 key->vs_epilog.prim_id_param_offset);
7579 args[4] = uint->zero; /* COMPR flag (0 = 32-bit export) */
7580 args[5] = LLVMGetParam(ctx->main_fn,
7581 VS_EPILOG_PRIMID_LOC); /* X */
7582 args[6] = base->undef; /* Y */
7583 args[7] = base->undef; /* Z */
7584 args[8] = base->undef; /* W */
7585
7586 lp_build_intrinsic(base->gallivm->builder, "llvm.SI.export",
7587 LLVMVoidTypeInContext(base->gallivm->context),
7588 args, 9, 0);
7589 }
7590
7591 LLVMBuildRetVoid(gallivm->builder);
7592 }
7593
7594 /**
7595 * Create & compile a vertex shader epilog. This a helper used by VS and TES.
7596 */
7597 static bool si_get_vs_epilog(struct si_screen *sscreen,
7598 LLVMTargetMachineRef tm,
7599 struct si_shader *shader,
7600 struct pipe_debug_callback *debug,
7601 struct si_vs_epilog_bits *states)
7602 {
7603 union si_shader_part_key epilog_key;
7604
7605 si_get_vs_epilog_key(shader, states, &epilog_key);
7606
7607 shader->epilog = si_get_shader_part(sscreen, &sscreen->vs_epilogs,
7608 PIPE_SHADER_VERTEX, true,
7609 &epilog_key, tm, debug,
7610 si_build_vs_epilog_function,
7611 "Vertex Shader Epilog");
7612 return shader->epilog != NULL;
7613 }
7614
7615 /**
7616 * Select and compile (or reuse) vertex shader parts (prolog & epilog).
7617 */
7618 static bool si_shader_select_vs_parts(struct si_screen *sscreen,
7619 LLVMTargetMachineRef tm,
7620 struct si_shader *shader,
7621 struct pipe_debug_callback *debug)
7622 {
7623 struct tgsi_shader_info *info = &shader->selector->info;
7624 union si_shader_part_key prolog_key;
7625
7626 /* Get the prolog. */
7627 si_get_vs_prolog_key(shader, &prolog_key);
7628
7629 /* The prolog is a no-op if there are no inputs. */
7630 if (info->num_inputs) {
7631 shader->prolog =
7632 si_get_shader_part(sscreen, &sscreen->vs_prologs,
7633 PIPE_SHADER_VERTEX, true,
7634 &prolog_key, tm, debug,
7635 si_build_vs_prolog_function,
7636 "Vertex Shader Prolog");
7637 if (!shader->prolog)
7638 return false;
7639 }
7640
7641 /* Get the epilog. */
7642 if (!shader->key.as_es && !shader->key.as_ls &&
7643 !si_get_vs_epilog(sscreen, tm, shader, debug,
7644 &shader->key.part.vs.epilog))
7645 return false;
7646
7647 return true;
7648 }
7649
7650 /**
7651 * Select and compile (or reuse) TES parts (epilog).
7652 */
7653 static bool si_shader_select_tes_parts(struct si_screen *sscreen,
7654 LLVMTargetMachineRef tm,
7655 struct si_shader *shader,
7656 struct pipe_debug_callback *debug)
7657 {
7658 if (shader->key.as_es)
7659 return true;
7660
7661 /* TES compiled as VS. */
7662 return si_get_vs_epilog(sscreen, tm, shader, debug,
7663 &shader->key.part.tes.epilog);
7664 }
7665
7666 /**
7667 * Compile the TCS epilog function. This writes tesselation factors to memory
7668 * based on the output primitive type of the tesselator (determined by TES).
7669 */
7670 static void si_build_tcs_epilog_function(struct si_shader_context *ctx,
7671 union si_shader_part_key *key)
7672 {
7673 struct gallivm_state *gallivm = &ctx->gallivm;
7674 struct lp_build_tgsi_context *bld_base = &ctx->soa.bld_base;
7675 LLVMTypeRef params[16];
7676 LLVMValueRef func;
7677 int last_sgpr, num_params;
7678
7679 /* Declare inputs. Only RW_BUFFERS and TESS_FACTOR_OFFSET are used. */
7680 params[SI_PARAM_RW_BUFFERS] = const_array(ctx->v16i8, SI_NUM_RW_BUFFERS);
7681 params[SI_PARAM_CONST_BUFFERS] = ctx->i64;
7682 params[SI_PARAM_SAMPLERS] = ctx->i64;
7683 params[SI_PARAM_IMAGES] = ctx->i64;
7684 params[SI_PARAM_SHADER_BUFFERS] = ctx->i64;
7685 params[SI_PARAM_TCS_OFFCHIP_LAYOUT] = ctx->i32;
7686 params[SI_PARAM_TCS_OUT_OFFSETS] = ctx->i32;
7687 params[SI_PARAM_TCS_OUT_LAYOUT] = ctx->i32;
7688 params[SI_PARAM_TCS_IN_LAYOUT] = ctx->i32;
7689 params[ctx->param_oc_lds = SI_PARAM_TCS_OC_LDS] = ctx->i32;
7690 params[SI_PARAM_TESS_FACTOR_OFFSET] = ctx->i32;
7691 last_sgpr = SI_PARAM_TESS_FACTOR_OFFSET;
7692 num_params = last_sgpr + 1;
7693
7694 params[num_params++] = ctx->i32; /* patch index within the wave (REL_PATCH_ID) */
7695 params[num_params++] = ctx->i32; /* invocation ID within the patch */
7696 params[num_params++] = ctx->i32; /* LDS offset where tess factors should be loaded from */
7697
7698 /* Create the function. */
7699 si_create_function(ctx, "tcs_epilog", NULL, 0, params, num_params, last_sgpr);
7700 declare_tess_lds(ctx);
7701 func = ctx->main_fn;
7702
7703 si_write_tess_factors(bld_base,
7704 LLVMGetParam(func, last_sgpr + 1),
7705 LLVMGetParam(func, last_sgpr + 2),
7706 LLVMGetParam(func, last_sgpr + 3));
7707
7708 LLVMBuildRetVoid(gallivm->builder);
7709 }
7710
7711 /**
7712 * Select and compile (or reuse) TCS parts (epilog).
7713 */
7714 static bool si_shader_select_tcs_parts(struct si_screen *sscreen,
7715 LLVMTargetMachineRef tm,
7716 struct si_shader *shader,
7717 struct pipe_debug_callback *debug)
7718 {
7719 union si_shader_part_key epilog_key;
7720
7721 /* Get the epilog. */
7722 memset(&epilog_key, 0, sizeof(epilog_key));
7723 epilog_key.tcs_epilog.states = shader->key.part.tcs.epilog;
7724
7725 shader->epilog = si_get_shader_part(sscreen, &sscreen->tcs_epilogs,
7726 PIPE_SHADER_TESS_CTRL, false,
7727 &epilog_key, tm, debug,
7728 si_build_tcs_epilog_function,
7729 "Tessellation Control Shader Epilog");
7730 return shader->epilog != NULL;
7731 }
7732
7733 /**
7734 * Select and compile (or reuse) GS parts (prolog).
7735 */
7736 static bool si_shader_select_gs_parts(struct si_screen *sscreen,
7737 LLVMTargetMachineRef tm,
7738 struct si_shader *shader,
7739 struct pipe_debug_callback *debug)
7740 {
7741 union si_shader_part_key prolog_key;
7742
7743 if (!shader->key.part.gs.prolog.tri_strip_adj_fix)
7744 return true;
7745
7746 memset(&prolog_key, 0, sizeof(prolog_key));
7747 prolog_key.gs_prolog.states = shader->key.part.gs.prolog;
7748
7749 shader->prolog = si_get_shader_part(sscreen, &sscreen->gs_prologs,
7750 PIPE_SHADER_GEOMETRY, true,
7751 &prolog_key, tm, debug,
7752 si_build_gs_prolog_function,
7753 "Geometry Shader Prolog");
7754 return shader->prolog != NULL;
7755 }
7756
7757 /**
7758 * Build the pixel shader prolog function. This handles:
7759 * - two-side color selection and interpolation
7760 * - overriding interpolation parameters for the API PS
7761 * - polygon stippling
7762 *
7763 * All preloaded SGPRs and VGPRs are passed through unmodified unless they are
7764 * overriden by other states. (e.g. per-sample interpolation)
7765 * Interpolated colors are stored after the preloaded VGPRs.
7766 */
7767 static void si_build_ps_prolog_function(struct si_shader_context *ctx,
7768 union si_shader_part_key *key)
7769 {
7770 struct gallivm_state *gallivm = &ctx->gallivm;
7771 LLVMTypeRef *params;
7772 LLVMValueRef ret, func;
7773 int last_sgpr, num_params, num_returns, i, num_color_channels;
7774
7775 assert(si_need_ps_prolog(key));
7776
7777 /* Number of inputs + 8 color elements. */
7778 params = alloca((key->ps_prolog.num_input_sgprs +
7779 key->ps_prolog.num_input_vgprs + 8) *
7780 sizeof(LLVMTypeRef));
7781
7782 /* Declare inputs. */
7783 num_params = 0;
7784 for (i = 0; i < key->ps_prolog.num_input_sgprs; i++)
7785 params[num_params++] = ctx->i32;
7786 last_sgpr = num_params - 1;
7787
7788 for (i = 0; i < key->ps_prolog.num_input_vgprs; i++)
7789 params[num_params++] = ctx->f32;
7790
7791 /* Declare outputs (same as inputs + add colors if needed) */
7792 num_returns = num_params;
7793 num_color_channels = util_bitcount(key->ps_prolog.colors_read);
7794 for (i = 0; i < num_color_channels; i++)
7795 params[num_returns++] = ctx->f32;
7796
7797 /* Create the function. */
7798 si_create_function(ctx, "ps_prolog", params, num_returns, params,
7799 num_params, last_sgpr);
7800 func = ctx->main_fn;
7801
7802 /* Copy inputs to outputs. This should be no-op, as the registers match,
7803 * but it will prevent the compiler from overwriting them unintentionally.
7804 */
7805 ret = ctx->return_value;
7806 for (i = 0; i < num_params; i++) {
7807 LLVMValueRef p = LLVMGetParam(func, i);
7808 ret = LLVMBuildInsertValue(gallivm->builder, ret, p, i, "");
7809 }
7810
7811 /* Polygon stippling. */
7812 if (key->ps_prolog.states.poly_stipple) {
7813 /* POS_FIXED_PT is always last. */
7814 unsigned pos = key->ps_prolog.num_input_sgprs +
7815 key->ps_prolog.num_input_vgprs - 1;
7816 LLVMValueRef ptr[2], list;
7817
7818 /* Get the pointer to rw buffers. */
7819 ptr[0] = LLVMGetParam(func, SI_SGPR_RW_BUFFERS);
7820 ptr[1] = LLVMGetParam(func, SI_SGPR_RW_BUFFERS_HI);
7821 list = lp_build_gather_values(gallivm, ptr, 2);
7822 list = LLVMBuildBitCast(gallivm->builder, list, ctx->i64, "");
7823 list = LLVMBuildIntToPtr(gallivm->builder, list,
7824 const_array(ctx->v16i8, SI_NUM_RW_BUFFERS), "");
7825
7826 si_llvm_emit_polygon_stipple(ctx, list, pos);
7827 }
7828
7829 if (key->ps_prolog.states.bc_optimize_for_persp ||
7830 key->ps_prolog.states.bc_optimize_for_linear) {
7831 unsigned i, base = key->ps_prolog.num_input_sgprs;
7832 LLVMValueRef center[2], centroid[2], tmp, bc_optimize;
7833
7834 /* The shader should do: if (PRIM_MASK[31]) CENTROID = CENTER;
7835 * The hw doesn't compute CENTROID if the whole wave only
7836 * contains fully-covered quads.
7837 *
7838 * PRIM_MASK is after user SGPRs.
7839 */
7840 bc_optimize = LLVMGetParam(func, SI_PS_NUM_USER_SGPR);
7841 bc_optimize = LLVMBuildLShr(gallivm->builder, bc_optimize,
7842 LLVMConstInt(ctx->i32, 31, 0), "");
7843 bc_optimize = LLVMBuildTrunc(gallivm->builder, bc_optimize,
7844 ctx->i1, "");
7845
7846 if (key->ps_prolog.states.bc_optimize_for_persp) {
7847 /* Read PERSP_CENTER. */
7848 for (i = 0; i < 2; i++)
7849 center[i] = LLVMGetParam(func, base + 2 + i);
7850 /* Read PERSP_CENTROID. */
7851 for (i = 0; i < 2; i++)
7852 centroid[i] = LLVMGetParam(func, base + 4 + i);
7853 /* Select PERSP_CENTROID. */
7854 for (i = 0; i < 2; i++) {
7855 tmp = LLVMBuildSelect(gallivm->builder, bc_optimize,
7856 center[i], centroid[i], "");
7857 ret = LLVMBuildInsertValue(gallivm->builder, ret,
7858 tmp, base + 4 + i, "");
7859 }
7860 }
7861 if (key->ps_prolog.states.bc_optimize_for_linear) {
7862 /* Read LINEAR_CENTER. */
7863 for (i = 0; i < 2; i++)
7864 center[i] = LLVMGetParam(func, base + 8 + i);
7865 /* Read LINEAR_CENTROID. */
7866 for (i = 0; i < 2; i++)
7867 centroid[i] = LLVMGetParam(func, base + 10 + i);
7868 /* Select LINEAR_CENTROID. */
7869 for (i = 0; i < 2; i++) {
7870 tmp = LLVMBuildSelect(gallivm->builder, bc_optimize,
7871 center[i], centroid[i], "");
7872 ret = LLVMBuildInsertValue(gallivm->builder, ret,
7873 tmp, base + 10 + i, "");
7874 }
7875 }
7876 }
7877
7878 /* Force per-sample interpolation. */
7879 if (key->ps_prolog.states.force_persp_sample_interp) {
7880 unsigned i, base = key->ps_prolog.num_input_sgprs;
7881 LLVMValueRef persp_sample[2];
7882
7883 /* Read PERSP_SAMPLE. */
7884 for (i = 0; i < 2; i++)
7885 persp_sample[i] = LLVMGetParam(func, base + i);
7886 /* Overwrite PERSP_CENTER. */
7887 for (i = 0; i < 2; i++)
7888 ret = LLVMBuildInsertValue(gallivm->builder, ret,
7889 persp_sample[i], base + 2 + i, "");
7890 /* Overwrite PERSP_CENTROID. */
7891 for (i = 0; i < 2; i++)
7892 ret = LLVMBuildInsertValue(gallivm->builder, ret,
7893 persp_sample[i], base + 4 + i, "");
7894 }
7895 if (key->ps_prolog.states.force_linear_sample_interp) {
7896 unsigned i, base = key->ps_prolog.num_input_sgprs;
7897 LLVMValueRef linear_sample[2];
7898
7899 /* Read LINEAR_SAMPLE. */
7900 for (i = 0; i < 2; i++)
7901 linear_sample[i] = LLVMGetParam(func, base + 6 + i);
7902 /* Overwrite LINEAR_CENTER. */
7903 for (i = 0; i < 2; i++)
7904 ret = LLVMBuildInsertValue(gallivm->builder, ret,
7905 linear_sample[i], base + 8 + i, "");
7906 /* Overwrite LINEAR_CENTROID. */
7907 for (i = 0; i < 2; i++)
7908 ret = LLVMBuildInsertValue(gallivm->builder, ret,
7909 linear_sample[i], base + 10 + i, "");
7910 }
7911
7912 /* Force center interpolation. */
7913 if (key->ps_prolog.states.force_persp_center_interp) {
7914 unsigned i, base = key->ps_prolog.num_input_sgprs;
7915 LLVMValueRef persp_center[2];
7916
7917 /* Read PERSP_CENTER. */
7918 for (i = 0; i < 2; i++)
7919 persp_center[i] = LLVMGetParam(func, base + 2 + i);
7920 /* Overwrite PERSP_SAMPLE. */
7921 for (i = 0; i < 2; i++)
7922 ret = LLVMBuildInsertValue(gallivm->builder, ret,
7923 persp_center[i], base + i, "");
7924 /* Overwrite PERSP_CENTROID. */
7925 for (i = 0; i < 2; i++)
7926 ret = LLVMBuildInsertValue(gallivm->builder, ret,
7927 persp_center[i], base + 4 + i, "");
7928 }
7929 if (key->ps_prolog.states.force_linear_center_interp) {
7930 unsigned i, base = key->ps_prolog.num_input_sgprs;
7931 LLVMValueRef linear_center[2];
7932
7933 /* Read LINEAR_CENTER. */
7934 for (i = 0; i < 2; i++)
7935 linear_center[i] = LLVMGetParam(func, base + 8 + i);
7936 /* Overwrite LINEAR_SAMPLE. */
7937 for (i = 0; i < 2; i++)
7938 ret = LLVMBuildInsertValue(gallivm->builder, ret,
7939 linear_center[i], base + 6 + i, "");
7940 /* Overwrite LINEAR_CENTROID. */
7941 for (i = 0; i < 2; i++)
7942 ret = LLVMBuildInsertValue(gallivm->builder, ret,
7943 linear_center[i], base + 10 + i, "");
7944 }
7945
7946 /* Interpolate colors. */
7947 for (i = 0; i < 2; i++) {
7948 unsigned writemask = (key->ps_prolog.colors_read >> (i * 4)) & 0xf;
7949 unsigned face_vgpr = key->ps_prolog.num_input_sgprs +
7950 key->ps_prolog.face_vgpr_index;
7951 LLVMValueRef interp[2], color[4];
7952 LLVMValueRef interp_ij = NULL, prim_mask = NULL, face = NULL;
7953
7954 if (!writemask)
7955 continue;
7956
7957 /* If the interpolation qualifier is not CONSTANT (-1). */
7958 if (key->ps_prolog.color_interp_vgpr_index[i] != -1) {
7959 unsigned interp_vgpr = key->ps_prolog.num_input_sgprs +
7960 key->ps_prolog.color_interp_vgpr_index[i];
7961
7962 /* Get the (i,j) updated by bc_optimize handling. */
7963 interp[0] = LLVMBuildExtractValue(gallivm->builder, ret,
7964 interp_vgpr, "");
7965 interp[1] = LLVMBuildExtractValue(gallivm->builder, ret,
7966 interp_vgpr + 1, "");
7967 interp_ij = lp_build_gather_values(gallivm, interp, 2);
7968 interp_ij = LLVMBuildBitCast(gallivm->builder, interp_ij,
7969 ctx->v2i32, "");
7970 }
7971
7972 /* Use the absolute location of the input. */
7973 prim_mask = LLVMGetParam(func, SI_PS_NUM_USER_SGPR);
7974
7975 if (key->ps_prolog.states.color_two_side) {
7976 face = LLVMGetParam(func, face_vgpr);
7977 face = LLVMBuildBitCast(gallivm->builder, face, ctx->i32, "");
7978 }
7979
7980 interp_fs_input(ctx,
7981 key->ps_prolog.color_attr_index[i],
7982 TGSI_SEMANTIC_COLOR, i,
7983 key->ps_prolog.num_interp_inputs,
7984 key->ps_prolog.colors_read, interp_ij,
7985 prim_mask, face, color);
7986
7987 while (writemask) {
7988 unsigned chan = u_bit_scan(&writemask);
7989 ret = LLVMBuildInsertValue(gallivm->builder, ret, color[chan],
7990 num_params++, "");
7991 }
7992 }
7993
7994 /* Tell LLVM to insert WQM instruction sequence when needed. */
7995 if (key->ps_prolog.wqm) {
7996 LLVMAddTargetDependentFunctionAttr(func,
7997 "amdgpu-ps-wqm-outputs", "");
7998 }
7999
8000 si_llvm_build_ret(ctx, ret);
8001 }
8002
8003 /**
8004 * Build the pixel shader epilog function. This handles everything that must be
8005 * emulated for pixel shader exports. (alpha-test, format conversions, etc)
8006 */
8007 static void si_build_ps_epilog_function(struct si_shader_context *ctx,
8008 union si_shader_part_key *key)
8009 {
8010 struct gallivm_state *gallivm = &ctx->gallivm;
8011 struct lp_build_tgsi_context *bld_base = &ctx->soa.bld_base;
8012 LLVMTypeRef params[16+8*4+3];
8013 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
8014 int last_sgpr, num_params, i;
8015 struct si_ps_exports exp = {};
8016
8017 /* Declare input SGPRs. */
8018 params[SI_PARAM_RW_BUFFERS] = ctx->i64;
8019 params[SI_PARAM_CONST_BUFFERS] = ctx->i64;
8020 params[SI_PARAM_SAMPLERS] = ctx->i64;
8021 params[SI_PARAM_IMAGES] = ctx->i64;
8022 params[SI_PARAM_SHADER_BUFFERS] = ctx->i64;
8023 params[SI_PARAM_ALPHA_REF] = ctx->f32;
8024 last_sgpr = SI_PARAM_ALPHA_REF;
8025
8026 /* Declare input VGPRs. */
8027 num_params = (last_sgpr + 1) +
8028 util_bitcount(key->ps_epilog.colors_written) * 4 +
8029 key->ps_epilog.writes_z +
8030 key->ps_epilog.writes_stencil +
8031 key->ps_epilog.writes_samplemask;
8032
8033 num_params = MAX2(num_params,
8034 last_sgpr + 1 + PS_EPILOG_SAMPLEMASK_MIN_LOC + 1);
8035
8036 assert(num_params <= ARRAY_SIZE(params));
8037
8038 for (i = last_sgpr + 1; i < num_params; i++)
8039 params[i] = ctx->f32;
8040
8041 /* Create the function. */
8042 si_create_function(ctx, "ps_epilog", NULL, 0, params, num_params, last_sgpr);
8043 /* Disable elimination of unused inputs. */
8044 si_llvm_add_attribute(ctx->main_fn,
8045 "InitialPSInputAddr", 0xffffff);
8046
8047 /* Process colors. */
8048 unsigned vgpr = last_sgpr + 1;
8049 unsigned colors_written = key->ps_epilog.colors_written;
8050 int last_color_export = -1;
8051
8052 /* Find the last color export. */
8053 if (!key->ps_epilog.writes_z &&
8054 !key->ps_epilog.writes_stencil &&
8055 !key->ps_epilog.writes_samplemask) {
8056 unsigned spi_format = key->ps_epilog.states.spi_shader_col_format;
8057
8058 /* If last_cbuf > 0, FS_COLOR0_WRITES_ALL_CBUFS is true. */
8059 if (colors_written == 0x1 && key->ps_epilog.states.last_cbuf > 0) {
8060 /* Just set this if any of the colorbuffers are enabled. */
8061 if (spi_format &
8062 ((1llu << (4 * (key->ps_epilog.states.last_cbuf + 1))) - 1))
8063 last_color_export = 0;
8064 } else {
8065 for (i = 0; i < 8; i++)
8066 if (colors_written & (1 << i) &&
8067 (spi_format >> (i * 4)) & 0xf)
8068 last_color_export = i;
8069 }
8070 }
8071
8072 while (colors_written) {
8073 LLVMValueRef color[4];
8074 int mrt = u_bit_scan(&colors_written);
8075
8076 for (i = 0; i < 4; i++)
8077 color[i] = LLVMGetParam(ctx->main_fn, vgpr++);
8078
8079 si_export_mrt_color(bld_base, color, mrt,
8080 num_params - 1,
8081 mrt == last_color_export, &exp);
8082 }
8083
8084 /* Process depth, stencil, samplemask. */
8085 if (key->ps_epilog.writes_z)
8086 depth = LLVMGetParam(ctx->main_fn, vgpr++);
8087 if (key->ps_epilog.writes_stencil)
8088 stencil = LLVMGetParam(ctx->main_fn, vgpr++);
8089 if (key->ps_epilog.writes_samplemask)
8090 samplemask = LLVMGetParam(ctx->main_fn, vgpr++);
8091
8092 if (depth || stencil || samplemask)
8093 si_export_mrt_z(bld_base, depth, stencil, samplemask, &exp);
8094 else if (last_color_export == -1)
8095 si_export_null(bld_base);
8096
8097 if (exp.num)
8098 si_emit_ps_exports(ctx, &exp);
8099
8100 /* Compile. */
8101 LLVMBuildRetVoid(gallivm->builder);
8102 }
8103
8104 /**
8105 * Select and compile (or reuse) pixel shader parts (prolog & epilog).
8106 */
8107 static bool si_shader_select_ps_parts(struct si_screen *sscreen,
8108 LLVMTargetMachineRef tm,
8109 struct si_shader *shader,
8110 struct pipe_debug_callback *debug)
8111 {
8112 union si_shader_part_key prolog_key;
8113 union si_shader_part_key epilog_key;
8114
8115 /* Get the prolog. */
8116 si_get_ps_prolog_key(shader, &prolog_key, true);
8117
8118 /* The prolog is a no-op if these aren't set. */
8119 if (si_need_ps_prolog(&prolog_key)) {
8120 shader->prolog =
8121 si_get_shader_part(sscreen, &sscreen->ps_prologs,
8122 PIPE_SHADER_FRAGMENT, true,
8123 &prolog_key, tm, debug,
8124 si_build_ps_prolog_function,
8125 "Fragment Shader Prolog");
8126 if (!shader->prolog)
8127 return false;
8128 }
8129
8130 /* Get the epilog. */
8131 si_get_ps_epilog_key(shader, &epilog_key);
8132
8133 shader->epilog =
8134 si_get_shader_part(sscreen, &sscreen->ps_epilogs,
8135 PIPE_SHADER_FRAGMENT, false,
8136 &epilog_key, tm, debug,
8137 si_build_ps_epilog_function,
8138 "Fragment Shader Epilog");
8139 if (!shader->epilog)
8140 return false;
8141
8142 /* Enable POS_FIXED_PT if polygon stippling is enabled. */
8143 if (shader->key.part.ps.prolog.poly_stipple) {
8144 shader->config.spi_ps_input_ena |= S_0286CC_POS_FIXED_PT_ENA(1);
8145 assert(G_0286CC_POS_FIXED_PT_ENA(shader->config.spi_ps_input_addr));
8146 }
8147
8148 /* Set up the enable bits for per-sample shading if needed. */
8149 if (shader->key.part.ps.prolog.force_persp_sample_interp &&
8150 (G_0286CC_PERSP_CENTER_ENA(shader->config.spi_ps_input_ena) ||
8151 G_0286CC_PERSP_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
8152 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_CENTER_ENA;
8153 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_CENTROID_ENA;
8154 shader->config.spi_ps_input_ena |= S_0286CC_PERSP_SAMPLE_ENA(1);
8155 }
8156 if (shader->key.part.ps.prolog.force_linear_sample_interp &&
8157 (G_0286CC_LINEAR_CENTER_ENA(shader->config.spi_ps_input_ena) ||
8158 G_0286CC_LINEAR_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
8159 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_CENTER_ENA;
8160 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_CENTROID_ENA;
8161 shader->config.spi_ps_input_ena |= S_0286CC_LINEAR_SAMPLE_ENA(1);
8162 }
8163 if (shader->key.part.ps.prolog.force_persp_center_interp &&
8164 (G_0286CC_PERSP_SAMPLE_ENA(shader->config.spi_ps_input_ena) ||
8165 G_0286CC_PERSP_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
8166 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_SAMPLE_ENA;
8167 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_CENTROID_ENA;
8168 shader->config.spi_ps_input_ena |= S_0286CC_PERSP_CENTER_ENA(1);
8169 }
8170 if (shader->key.part.ps.prolog.force_linear_center_interp &&
8171 (G_0286CC_LINEAR_SAMPLE_ENA(shader->config.spi_ps_input_ena) ||
8172 G_0286CC_LINEAR_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
8173 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_SAMPLE_ENA;
8174 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_CENTROID_ENA;
8175 shader->config.spi_ps_input_ena |= S_0286CC_LINEAR_CENTER_ENA(1);
8176 }
8177
8178 /* POW_W_FLOAT requires that one of the perspective weights is enabled. */
8179 if (G_0286CC_POS_W_FLOAT_ENA(shader->config.spi_ps_input_ena) &&
8180 !(shader->config.spi_ps_input_ena & 0xf)) {
8181 shader->config.spi_ps_input_ena |= S_0286CC_PERSP_CENTER_ENA(1);
8182 assert(G_0286CC_PERSP_CENTER_ENA(shader->config.spi_ps_input_addr));
8183 }
8184
8185 /* At least one pair of interpolation weights must be enabled. */
8186 if (!(shader->config.spi_ps_input_ena & 0x7f)) {
8187 shader->config.spi_ps_input_ena |= S_0286CC_LINEAR_CENTER_ENA(1);
8188 assert(G_0286CC_LINEAR_CENTER_ENA(shader->config.spi_ps_input_addr));
8189 }
8190
8191 /* The sample mask input is always enabled, because the API shader always
8192 * passes it through to the epilog. Disable it here if it's unused.
8193 */
8194 if (!shader->key.part.ps.epilog.poly_line_smoothing &&
8195 !shader->selector->info.reads_samplemask)
8196 shader->config.spi_ps_input_ena &= C_0286CC_SAMPLE_COVERAGE_ENA;
8197
8198 return true;
8199 }
8200
8201 static void si_fix_num_sgprs(struct si_shader *shader)
8202 {
8203 unsigned min_sgprs = shader->info.num_input_sgprs + 2; /* VCC */
8204
8205 shader->config.num_sgprs = MAX2(shader->config.num_sgprs, min_sgprs);
8206 }
8207
8208 int si_shader_create(struct si_screen *sscreen, LLVMTargetMachineRef tm,
8209 struct si_shader *shader,
8210 struct pipe_debug_callback *debug)
8211 {
8212 struct si_shader_selector *sel = shader->selector;
8213 struct si_shader *mainp = sel->main_shader_part;
8214 int r;
8215
8216 /* LS, ES, VS are compiled on demand if the main part hasn't been
8217 * compiled for that stage.
8218 *
8219 * Vertex shaders are compiled on demand when a vertex fetch
8220 * workaround must be applied.
8221 */
8222 if (shader->is_monolithic) {
8223 /* Monolithic shader (compiled as a whole, has many variants,
8224 * may take a long time to compile).
8225 */
8226 r = si_compile_tgsi_shader(sscreen, tm, shader, true, debug);
8227 if (r)
8228 return r;
8229 } else {
8230 /* The shader consists of 2-3 parts:
8231 *
8232 * - the middle part is the user shader, it has 1 variant only
8233 * and it was compiled during the creation of the shader
8234 * selector
8235 * - the prolog part is inserted at the beginning
8236 * - the epilog part is inserted at the end
8237 *
8238 * The prolog and epilog have many (but simple) variants.
8239 */
8240
8241 /* Copy the compiled TGSI shader data over. */
8242 shader->is_binary_shared = true;
8243 shader->binary = mainp->binary;
8244 shader->config = mainp->config;
8245 shader->info.num_input_sgprs = mainp->info.num_input_sgprs;
8246 shader->info.num_input_vgprs = mainp->info.num_input_vgprs;
8247 shader->info.face_vgpr_index = mainp->info.face_vgpr_index;
8248 memcpy(shader->info.vs_output_param_offset,
8249 mainp->info.vs_output_param_offset,
8250 sizeof(mainp->info.vs_output_param_offset));
8251 shader->info.uses_instanceid = mainp->info.uses_instanceid;
8252 shader->info.nr_pos_exports = mainp->info.nr_pos_exports;
8253 shader->info.nr_param_exports = mainp->info.nr_param_exports;
8254
8255 /* Select prologs and/or epilogs. */
8256 switch (sel->type) {
8257 case PIPE_SHADER_VERTEX:
8258 if (!si_shader_select_vs_parts(sscreen, tm, shader, debug))
8259 return -1;
8260 break;
8261 case PIPE_SHADER_TESS_CTRL:
8262 if (!si_shader_select_tcs_parts(sscreen, tm, shader, debug))
8263 return -1;
8264 break;
8265 case PIPE_SHADER_TESS_EVAL:
8266 if (!si_shader_select_tes_parts(sscreen, tm, shader, debug))
8267 return -1;
8268 break;
8269 case PIPE_SHADER_GEOMETRY:
8270 if (!si_shader_select_gs_parts(sscreen, tm, shader, debug))
8271 return -1;
8272 break;
8273 case PIPE_SHADER_FRAGMENT:
8274 if (!si_shader_select_ps_parts(sscreen, tm, shader, debug))
8275 return -1;
8276
8277 /* Make sure we have at least as many VGPRs as there
8278 * are allocated inputs.
8279 */
8280 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
8281 shader->info.num_input_vgprs);
8282 break;
8283 }
8284
8285 /* Update SGPR and VGPR counts. */
8286 if (shader->prolog) {
8287 shader->config.num_sgprs = MAX2(shader->config.num_sgprs,
8288 shader->prolog->config.num_sgprs);
8289 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
8290 shader->prolog->config.num_vgprs);
8291 }
8292 if (shader->epilog) {
8293 shader->config.num_sgprs = MAX2(shader->config.num_sgprs,
8294 shader->epilog->config.num_sgprs);
8295 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
8296 shader->epilog->config.num_vgprs);
8297 }
8298 }
8299
8300 si_fix_num_sgprs(shader);
8301 si_shader_dump(sscreen, shader, debug, sel->info.processor,
8302 stderr);
8303
8304 /* Upload. */
8305 r = si_shader_binary_upload(sscreen, shader);
8306 if (r) {
8307 fprintf(stderr, "LLVM failed to upload shader\n");
8308 return r;
8309 }
8310
8311 return 0;
8312 }
8313
8314 void si_shader_destroy(struct si_shader *shader)
8315 {
8316 if (shader->scratch_bo)
8317 r600_resource_reference(&shader->scratch_bo, NULL);
8318
8319 r600_resource_reference(&shader->bo, NULL);
8320
8321 if (!shader->is_binary_shared)
8322 radeon_shader_binary_clean(&shader->binary);
8323
8324 free(shader->shader_log);
8325 }