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radeonsi: Lower TGSI_OPCODE_ATOM* down to LLVM op
[mesa.git] / src / gallium / drivers / radeonsi / si_shader.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Tom Stellard <thomas.stellard@amd.com>
25 * Michel Dänzer <michel.daenzer@amd.com>
26 * Christian König <christian.koenig@amd.com>
27 */
28
29 #include "gallivm/lp_bld_const.h"
30 #include "gallivm/lp_bld_gather.h"
31 #include "gallivm/lp_bld_intr.h"
32 #include "gallivm/lp_bld_logic.h"
33 #include "gallivm/lp_bld_arit.h"
34 #include "gallivm/lp_bld_bitarit.h"
35 #include "gallivm/lp_bld_flow.h"
36 #include "radeon/r600_cs.h"
37 #include "radeon/radeon_llvm.h"
38 #include "radeon/radeon_elf_util.h"
39 #include "radeon/radeon_llvm_emit.h"
40 #include "util/u_memory.h"
41 #include "util/u_pstipple.h"
42 #include "tgsi/tgsi_parse.h"
43 #include "tgsi/tgsi_build.h"
44 #include "tgsi/tgsi_util.h"
45 #include "tgsi/tgsi_dump.h"
46
47 #include "si_pipe.h"
48 #include "si_shader.h"
49 #include "sid.h"
50
51 #include <errno.h>
52
53 static const char *scratch_rsrc_dword0_symbol =
54 "SCRATCH_RSRC_DWORD0";
55
56 static const char *scratch_rsrc_dword1_symbol =
57 "SCRATCH_RSRC_DWORD1";
58
59 struct si_shader_output_values
60 {
61 LLVMValueRef values[4];
62 unsigned name;
63 unsigned sid;
64 };
65
66 struct si_shader_context
67 {
68 struct radeon_llvm_context radeon_bld;
69 struct si_shader *shader;
70 struct si_screen *screen;
71
72 unsigned type; /* TGSI_PROCESSOR_* specifies the type of shader. */
73 bool is_gs_copy_shader;
74
75 /* Whether to generate the optimized shader variant compiled as a whole
76 * (without a prolog and epilog)
77 */
78 bool is_monolithic;
79
80 int param_streamout_config;
81 int param_streamout_write_index;
82 int param_streamout_offset[4];
83 int param_vertex_id;
84 int param_rel_auto_id;
85 int param_vs_prim_id;
86 int param_instance_id;
87 int param_vertex_index0;
88 int param_tes_u;
89 int param_tes_v;
90 int param_tes_rel_patch_id;
91 int param_tes_patch_id;
92 int param_es2gs_offset;
93
94 LLVMTargetMachineRef tm;
95
96 LLVMValueRef const_md;
97 LLVMValueRef const_buffers[SI_NUM_CONST_BUFFERS];
98 LLVMValueRef lds;
99 LLVMValueRef *constants[SI_NUM_CONST_BUFFERS];
100 LLVMValueRef sampler_views[SI_NUM_SAMPLERS];
101 LLVMValueRef sampler_states[SI_NUM_SAMPLERS];
102 LLVMValueRef fmasks[SI_NUM_USER_SAMPLERS];
103 LLVMValueRef images[SI_NUM_IMAGES];
104 LLVMValueRef so_buffers[4];
105 LLVMValueRef esgs_ring;
106 LLVMValueRef gsvs_ring[4];
107 LLVMValueRef gs_next_vertex[4];
108 LLVMValueRef return_value;
109
110 LLVMTypeRef voidt;
111 LLVMTypeRef i1;
112 LLVMTypeRef i8;
113 LLVMTypeRef i32;
114 LLVMTypeRef i64;
115 LLVMTypeRef i128;
116 LLVMTypeRef f32;
117 LLVMTypeRef v16i8;
118 LLVMTypeRef v2i32;
119 LLVMTypeRef v4i32;
120 LLVMTypeRef v4f32;
121 LLVMTypeRef v8i32;
122 };
123
124 static struct si_shader_context *si_shader_context(
125 struct lp_build_tgsi_context *bld_base)
126 {
127 return (struct si_shader_context *)bld_base;
128 }
129
130 static void si_init_shader_ctx(struct si_shader_context *ctx,
131 struct si_screen *sscreen,
132 struct si_shader *shader,
133 LLVMTargetMachineRef tm);
134
135 /* Ideally pass the sample mask input to the PS epilog as v13, which
136 * is its usual location, so that the shader doesn't have to add v_mov.
137 */
138 #define PS_EPILOG_SAMPLEMASK_MIN_LOC 13
139
140 /* The VS location of the PrimitiveID input is the same in the epilog,
141 * so that the main shader part doesn't have to move it.
142 */
143 #define VS_EPILOG_PRIMID_LOC 2
144
145 #define PERSPECTIVE_BASE 0
146 #define LINEAR_BASE 9
147
148 #define SAMPLE_OFFSET 0
149 #define CENTER_OFFSET 2
150 #define CENTROID_OFSET 4
151
152 #define USE_SGPR_MAX_SUFFIX_LEN 5
153 #define CONST_ADDR_SPACE 2
154 #define LOCAL_ADDR_SPACE 3
155 #define USER_SGPR_ADDR_SPACE 8
156
157
158 #define SENDMSG_GS 2
159 #define SENDMSG_GS_DONE 3
160
161 #define SENDMSG_GS_OP_NOP (0 << 4)
162 #define SENDMSG_GS_OP_CUT (1 << 4)
163 #define SENDMSG_GS_OP_EMIT (2 << 4)
164 #define SENDMSG_GS_OP_EMIT_CUT (3 << 4)
165
166 /**
167 * Returns a unique index for a semantic name and index. The index must be
168 * less than 64, so that a 64-bit bitmask of used inputs or outputs can be
169 * calculated.
170 */
171 unsigned si_shader_io_get_unique_index(unsigned semantic_name, unsigned index)
172 {
173 switch (semantic_name) {
174 case TGSI_SEMANTIC_POSITION:
175 return 0;
176 case TGSI_SEMANTIC_PSIZE:
177 return 1;
178 case TGSI_SEMANTIC_CLIPDIST:
179 assert(index <= 1);
180 return 2 + index;
181 case TGSI_SEMANTIC_GENERIC:
182 if (index <= 63-4)
183 return 4 + index;
184 else
185 /* same explanation as in the default statement,
186 * the only user hitting this is st/nine.
187 */
188 return 0;
189
190 /* patch indices are completely separate and thus start from 0 */
191 case TGSI_SEMANTIC_TESSOUTER:
192 return 0;
193 case TGSI_SEMANTIC_TESSINNER:
194 return 1;
195 case TGSI_SEMANTIC_PATCH:
196 return 2 + index;
197
198 default:
199 /* Don't fail here. The result of this function is only used
200 * for LS, TCS, TES, and GS, where legacy GL semantics can't
201 * occur, but this function is called for all vertex shaders
202 * before it's known whether LS will be compiled or not.
203 */
204 return 0;
205 }
206 }
207
208 /**
209 * Get the value of a shader input parameter and extract a bitfield.
210 */
211 static LLVMValueRef unpack_param(struct si_shader_context *ctx,
212 unsigned param, unsigned rshift,
213 unsigned bitwidth)
214 {
215 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
216 LLVMValueRef value = LLVMGetParam(ctx->radeon_bld.main_fn,
217 param);
218
219 if (LLVMGetTypeKind(LLVMTypeOf(value)) == LLVMFloatTypeKind)
220 value = bitcast(&ctx->radeon_bld.soa.bld_base,
221 TGSI_TYPE_UNSIGNED, value);
222
223 if (rshift)
224 value = LLVMBuildLShr(gallivm->builder, value,
225 lp_build_const_int32(gallivm, rshift), "");
226
227 if (rshift + bitwidth < 32) {
228 unsigned mask = (1 << bitwidth) - 1;
229 value = LLVMBuildAnd(gallivm->builder, value,
230 lp_build_const_int32(gallivm, mask), "");
231 }
232
233 return value;
234 }
235
236 static LLVMValueRef get_rel_patch_id(struct si_shader_context *ctx)
237 {
238 switch (ctx->type) {
239 case TGSI_PROCESSOR_TESS_CTRL:
240 return unpack_param(ctx, SI_PARAM_REL_IDS, 0, 8);
241
242 case TGSI_PROCESSOR_TESS_EVAL:
243 return LLVMGetParam(ctx->radeon_bld.main_fn,
244 ctx->param_tes_rel_patch_id);
245
246 default:
247 assert(0);
248 return NULL;
249 }
250 }
251
252 /* Tessellation shaders pass outputs to the next shader using LDS.
253 *
254 * LS outputs = TCS inputs
255 * TCS outputs = TES inputs
256 *
257 * The LDS layout is:
258 * - TCS inputs for patch 0
259 * - TCS inputs for patch 1
260 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
261 * - ...
262 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
263 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
264 * - TCS outputs for patch 1
265 * - Per-patch TCS outputs for patch 1
266 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
267 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
268 * - ...
269 *
270 * All three shaders VS(LS), TCS, TES share the same LDS space.
271 */
272
273 static LLVMValueRef
274 get_tcs_in_patch_stride(struct si_shader_context *ctx)
275 {
276 if (ctx->type == TGSI_PROCESSOR_VERTEX)
277 return unpack_param(ctx, SI_PARAM_LS_OUT_LAYOUT, 0, 13);
278 else if (ctx->type == TGSI_PROCESSOR_TESS_CTRL)
279 return unpack_param(ctx, SI_PARAM_TCS_IN_LAYOUT, 0, 13);
280 else {
281 assert(0);
282 return NULL;
283 }
284 }
285
286 static LLVMValueRef
287 get_tcs_out_patch_stride(struct si_shader_context *ctx)
288 {
289 return unpack_param(ctx, SI_PARAM_TCS_OUT_LAYOUT, 0, 13);
290 }
291
292 static LLVMValueRef
293 get_tcs_out_patch0_offset(struct si_shader_context *ctx)
294 {
295 return lp_build_mul_imm(&ctx->radeon_bld.soa.bld_base.uint_bld,
296 unpack_param(ctx,
297 SI_PARAM_TCS_OUT_OFFSETS,
298 0, 16),
299 4);
300 }
301
302 static LLVMValueRef
303 get_tcs_out_patch0_patch_data_offset(struct si_shader_context *ctx)
304 {
305 return lp_build_mul_imm(&ctx->radeon_bld.soa.bld_base.uint_bld,
306 unpack_param(ctx,
307 SI_PARAM_TCS_OUT_OFFSETS,
308 16, 16),
309 4);
310 }
311
312 static LLVMValueRef
313 get_tcs_in_current_patch_offset(struct si_shader_context *ctx)
314 {
315 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
316 LLVMValueRef patch_stride = get_tcs_in_patch_stride(ctx);
317 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
318
319 return LLVMBuildMul(gallivm->builder, patch_stride, rel_patch_id, "");
320 }
321
322 static LLVMValueRef
323 get_tcs_out_current_patch_offset(struct si_shader_context *ctx)
324 {
325 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
326 LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(ctx);
327 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
328 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
329
330 return LLVMBuildAdd(gallivm->builder, patch0_offset,
331 LLVMBuildMul(gallivm->builder, patch_stride,
332 rel_patch_id, ""),
333 "");
334 }
335
336 static LLVMValueRef
337 get_tcs_out_current_patch_data_offset(struct si_shader_context *ctx)
338 {
339 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
340 LLVMValueRef patch0_patch_data_offset =
341 get_tcs_out_patch0_patch_data_offset(ctx);
342 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
343 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
344
345 return LLVMBuildAdd(gallivm->builder, patch0_patch_data_offset,
346 LLVMBuildMul(gallivm->builder, patch_stride,
347 rel_patch_id, ""),
348 "");
349 }
350
351 static void build_indexed_store(struct si_shader_context *ctx,
352 LLVMValueRef base_ptr, LLVMValueRef index,
353 LLVMValueRef value)
354 {
355 struct lp_build_tgsi_context *bld_base = &ctx->radeon_bld.soa.bld_base;
356 struct gallivm_state *gallivm = bld_base->base.gallivm;
357 LLVMValueRef indices[2], pointer;
358
359 indices[0] = bld_base->uint_bld.zero;
360 indices[1] = index;
361
362 pointer = LLVMBuildGEP(gallivm->builder, base_ptr, indices, 2, "");
363 LLVMBuildStore(gallivm->builder, value, pointer);
364 }
365
366 /**
367 * Build an LLVM bytecode indexed load using LLVMBuildGEP + LLVMBuildLoad.
368 * It's equivalent to doing a load from &base_ptr[index].
369 *
370 * \param base_ptr Where the array starts.
371 * \param index The element index into the array.
372 */
373 static LLVMValueRef build_indexed_load(struct si_shader_context *ctx,
374 LLVMValueRef base_ptr, LLVMValueRef index)
375 {
376 struct lp_build_tgsi_context *bld_base = &ctx->radeon_bld.soa.bld_base;
377 struct gallivm_state *gallivm = bld_base->base.gallivm;
378 LLVMValueRef indices[2], pointer;
379
380 indices[0] = bld_base->uint_bld.zero;
381 indices[1] = index;
382
383 pointer = LLVMBuildGEP(gallivm->builder, base_ptr, indices, 2, "");
384 return LLVMBuildLoad(gallivm->builder, pointer, "");
385 }
386
387 /**
388 * Do a load from &base_ptr[index], but also add a flag that it's loading
389 * a constant.
390 */
391 static LLVMValueRef build_indexed_load_const(
392 struct si_shader_context *ctx,
393 LLVMValueRef base_ptr, LLVMValueRef index)
394 {
395 LLVMValueRef result = build_indexed_load(ctx, base_ptr, index);
396 LLVMSetMetadata(result, 1, ctx->const_md);
397 return result;
398 }
399
400 static LLVMValueRef get_instance_index_for_fetch(
401 struct radeon_llvm_context *radeon_bld,
402 unsigned param_start_instance, unsigned divisor)
403 {
404 struct si_shader_context *ctx =
405 si_shader_context(&radeon_bld->soa.bld_base);
406 struct gallivm_state *gallivm = radeon_bld->soa.bld_base.base.gallivm;
407
408 LLVMValueRef result = LLVMGetParam(radeon_bld->main_fn,
409 ctx->param_instance_id);
410
411 /* The division must be done before START_INSTANCE is added. */
412 if (divisor > 1)
413 result = LLVMBuildUDiv(gallivm->builder, result,
414 lp_build_const_int32(gallivm, divisor), "");
415
416 return LLVMBuildAdd(gallivm->builder, result,
417 LLVMGetParam(radeon_bld->main_fn, param_start_instance), "");
418 }
419
420 static void declare_input_vs(
421 struct radeon_llvm_context *radeon_bld,
422 unsigned input_index,
423 const struct tgsi_full_declaration *decl)
424 {
425 struct lp_build_context *base = &radeon_bld->soa.bld_base.base;
426 struct gallivm_state *gallivm = base->gallivm;
427 struct si_shader_context *ctx =
428 si_shader_context(&radeon_bld->soa.bld_base);
429 unsigned divisor =
430 ctx->shader->key.vs.prolog.instance_divisors[input_index];
431
432 unsigned chan;
433
434 LLVMValueRef t_list_ptr;
435 LLVMValueRef t_offset;
436 LLVMValueRef t_list;
437 LLVMValueRef attribute_offset;
438 LLVMValueRef buffer_index;
439 LLVMValueRef args[3];
440 LLVMValueRef input;
441
442 /* Load the T list */
443 t_list_ptr = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_VERTEX_BUFFERS);
444
445 t_offset = lp_build_const_int32(gallivm, input_index);
446
447 t_list = build_indexed_load_const(ctx, t_list_ptr, t_offset);
448
449 /* Build the attribute offset */
450 attribute_offset = lp_build_const_int32(gallivm, 0);
451
452 if (!ctx->is_monolithic) {
453 buffer_index = LLVMGetParam(radeon_bld->main_fn,
454 ctx->param_vertex_index0 +
455 input_index);
456 } else if (divisor) {
457 /* Build index from instance ID, start instance and divisor */
458 ctx->shader->info.uses_instanceid = true;
459 buffer_index = get_instance_index_for_fetch(&ctx->radeon_bld,
460 SI_PARAM_START_INSTANCE,
461 divisor);
462 } else {
463 /* Load the buffer index for vertices. */
464 LLVMValueRef vertex_id = LLVMGetParam(ctx->radeon_bld.main_fn,
465 ctx->param_vertex_id);
466 LLVMValueRef base_vertex = LLVMGetParam(radeon_bld->main_fn,
467 SI_PARAM_BASE_VERTEX);
468 buffer_index = LLVMBuildAdd(gallivm->builder, base_vertex, vertex_id, "");
469 }
470
471 args[0] = t_list;
472 args[1] = attribute_offset;
473 args[2] = buffer_index;
474 input = lp_build_intrinsic(gallivm->builder,
475 "llvm.SI.vs.load.input", ctx->v4f32, args, 3,
476 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
477
478 /* Break up the vec4 into individual components */
479 for (chan = 0; chan < 4; chan++) {
480 LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan);
481 /* XXX: Use a helper function for this. There is one in
482 * tgsi_llvm.c. */
483 ctx->radeon_bld.inputs[radeon_llvm_reg_index_soa(input_index, chan)] =
484 LLVMBuildExtractElement(gallivm->builder,
485 input, llvm_chan, "");
486 }
487 }
488
489 static LLVMValueRef get_primitive_id(struct lp_build_tgsi_context *bld_base,
490 unsigned swizzle)
491 {
492 struct si_shader_context *ctx = si_shader_context(bld_base);
493
494 if (swizzle > 0)
495 return bld_base->uint_bld.zero;
496
497 switch (ctx->type) {
498 case TGSI_PROCESSOR_VERTEX:
499 return LLVMGetParam(ctx->radeon_bld.main_fn,
500 ctx->param_vs_prim_id);
501 case TGSI_PROCESSOR_TESS_CTRL:
502 return LLVMGetParam(ctx->radeon_bld.main_fn,
503 SI_PARAM_PATCH_ID);
504 case TGSI_PROCESSOR_TESS_EVAL:
505 return LLVMGetParam(ctx->radeon_bld.main_fn,
506 ctx->param_tes_patch_id);
507 case TGSI_PROCESSOR_GEOMETRY:
508 return LLVMGetParam(ctx->radeon_bld.main_fn,
509 SI_PARAM_PRIMITIVE_ID);
510 default:
511 assert(0);
512 return bld_base->uint_bld.zero;
513 }
514 }
515
516 /**
517 * Return the value of tgsi_ind_register for indexing.
518 * This is the indirect index with the constant offset added to it.
519 */
520 static LLVMValueRef get_indirect_index(struct si_shader_context *ctx,
521 const struct tgsi_ind_register *ind,
522 int rel_index)
523 {
524 struct gallivm_state *gallivm = ctx->radeon_bld.soa.bld_base.base.gallivm;
525 LLVMValueRef result;
526
527 result = ctx->radeon_bld.soa.addr[ind->Index][ind->Swizzle];
528 result = LLVMBuildLoad(gallivm->builder, result, "");
529 result = LLVMBuildAdd(gallivm->builder, result,
530 lp_build_const_int32(gallivm, rel_index), "");
531 return result;
532 }
533
534 /**
535 * Calculate a dword address given an input or output register and a stride.
536 */
537 static LLVMValueRef get_dw_address(struct si_shader_context *ctx,
538 const struct tgsi_full_dst_register *dst,
539 const struct tgsi_full_src_register *src,
540 LLVMValueRef vertex_dw_stride,
541 LLVMValueRef base_addr)
542 {
543 struct gallivm_state *gallivm = ctx->radeon_bld.soa.bld_base.base.gallivm;
544 struct tgsi_shader_info *info = &ctx->shader->selector->info;
545 ubyte *name, *index, *array_first;
546 int first, param;
547 struct tgsi_full_dst_register reg;
548
549 /* Set the register description. The address computation is the same
550 * for sources and destinations. */
551 if (src) {
552 reg.Register.File = src->Register.File;
553 reg.Register.Index = src->Register.Index;
554 reg.Register.Indirect = src->Register.Indirect;
555 reg.Register.Dimension = src->Register.Dimension;
556 reg.Indirect = src->Indirect;
557 reg.Dimension = src->Dimension;
558 reg.DimIndirect = src->DimIndirect;
559 } else
560 reg = *dst;
561
562 /* If the register is 2-dimensional (e.g. an array of vertices
563 * in a primitive), calculate the base address of the vertex. */
564 if (reg.Register.Dimension) {
565 LLVMValueRef index;
566
567 if (reg.Dimension.Indirect)
568 index = get_indirect_index(ctx, &reg.DimIndirect,
569 reg.Dimension.Index);
570 else
571 index = lp_build_const_int32(gallivm, reg.Dimension.Index);
572
573 base_addr = LLVMBuildAdd(gallivm->builder, base_addr,
574 LLVMBuildMul(gallivm->builder, index,
575 vertex_dw_stride, ""), "");
576 }
577
578 /* Get information about the register. */
579 if (reg.Register.File == TGSI_FILE_INPUT) {
580 name = info->input_semantic_name;
581 index = info->input_semantic_index;
582 array_first = info->input_array_first;
583 } else if (reg.Register.File == TGSI_FILE_OUTPUT) {
584 name = info->output_semantic_name;
585 index = info->output_semantic_index;
586 array_first = info->output_array_first;
587 } else {
588 assert(0);
589 return NULL;
590 }
591
592 if (reg.Register.Indirect) {
593 /* Add the relative address of the element. */
594 LLVMValueRef ind_index;
595
596 if (reg.Indirect.ArrayID)
597 first = array_first[reg.Indirect.ArrayID];
598 else
599 first = reg.Register.Index;
600
601 ind_index = get_indirect_index(ctx, &reg.Indirect,
602 reg.Register.Index - first);
603
604 base_addr = LLVMBuildAdd(gallivm->builder, base_addr,
605 LLVMBuildMul(gallivm->builder, ind_index,
606 lp_build_const_int32(gallivm, 4), ""), "");
607
608 param = si_shader_io_get_unique_index(name[first], index[first]);
609 } else {
610 param = si_shader_io_get_unique_index(name[reg.Register.Index],
611 index[reg.Register.Index]);
612 }
613
614 /* Add the base address of the element. */
615 return LLVMBuildAdd(gallivm->builder, base_addr,
616 lp_build_const_int32(gallivm, param * 4), "");
617 }
618
619 /**
620 * Load from LDS.
621 *
622 * \param type output value type
623 * \param swizzle offset (typically 0..3); it can be ~0, which loads a vec4
624 * \param dw_addr address in dwords
625 */
626 static LLVMValueRef lds_load(struct lp_build_tgsi_context *bld_base,
627 enum tgsi_opcode_type type, unsigned swizzle,
628 LLVMValueRef dw_addr)
629 {
630 struct si_shader_context *ctx = si_shader_context(bld_base);
631 struct gallivm_state *gallivm = bld_base->base.gallivm;
632 LLVMValueRef value;
633
634 if (swizzle == ~0) {
635 LLVMValueRef values[TGSI_NUM_CHANNELS];
636
637 for (unsigned chan = 0; chan < TGSI_NUM_CHANNELS; chan++)
638 values[chan] = lds_load(bld_base, type, chan, dw_addr);
639
640 return lp_build_gather_values(bld_base->base.gallivm, values,
641 TGSI_NUM_CHANNELS);
642 }
643
644 dw_addr = lp_build_add(&bld_base->uint_bld, dw_addr,
645 lp_build_const_int32(gallivm, swizzle));
646
647 value = build_indexed_load(ctx, ctx->lds, dw_addr);
648 if (type == TGSI_TYPE_DOUBLE) {
649 LLVMValueRef value2;
650 dw_addr = lp_build_add(&bld_base->uint_bld, dw_addr,
651 lp_build_const_int32(gallivm, swizzle + 1));
652 value2 = build_indexed_load(ctx, ctx->lds, dw_addr);
653 return radeon_llvm_emit_fetch_double(bld_base, value, value2);
654 }
655
656 return LLVMBuildBitCast(gallivm->builder, value,
657 tgsi2llvmtype(bld_base, type), "");
658 }
659
660 /**
661 * Store to LDS.
662 *
663 * \param swizzle offset (typically 0..3)
664 * \param dw_addr address in dwords
665 * \param value value to store
666 */
667 static void lds_store(struct lp_build_tgsi_context *bld_base,
668 unsigned swizzle, LLVMValueRef dw_addr,
669 LLVMValueRef value)
670 {
671 struct si_shader_context *ctx = si_shader_context(bld_base);
672 struct gallivm_state *gallivm = bld_base->base.gallivm;
673
674 dw_addr = lp_build_add(&bld_base->uint_bld, dw_addr,
675 lp_build_const_int32(gallivm, swizzle));
676
677 value = LLVMBuildBitCast(gallivm->builder, value, ctx->i32, "");
678 build_indexed_store(ctx, ctx->lds,
679 dw_addr, value);
680 }
681
682 static LLVMValueRef fetch_input_tcs(
683 struct lp_build_tgsi_context *bld_base,
684 const struct tgsi_full_src_register *reg,
685 enum tgsi_opcode_type type, unsigned swizzle)
686 {
687 struct si_shader_context *ctx = si_shader_context(bld_base);
688 LLVMValueRef dw_addr, stride;
689
690 stride = unpack_param(ctx, SI_PARAM_TCS_IN_LAYOUT, 13, 8);
691 dw_addr = get_tcs_in_current_patch_offset(ctx);
692 dw_addr = get_dw_address(ctx, NULL, reg, stride, dw_addr);
693
694 return lds_load(bld_base, type, swizzle, dw_addr);
695 }
696
697 static LLVMValueRef fetch_output_tcs(
698 struct lp_build_tgsi_context *bld_base,
699 const struct tgsi_full_src_register *reg,
700 enum tgsi_opcode_type type, unsigned swizzle)
701 {
702 struct si_shader_context *ctx = si_shader_context(bld_base);
703 LLVMValueRef dw_addr, stride;
704
705 if (reg->Register.Dimension) {
706 stride = unpack_param(ctx, SI_PARAM_TCS_OUT_LAYOUT, 13, 8);
707 dw_addr = get_tcs_out_current_patch_offset(ctx);
708 dw_addr = get_dw_address(ctx, NULL, reg, stride, dw_addr);
709 } else {
710 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
711 dw_addr = get_dw_address(ctx, NULL, reg, NULL, dw_addr);
712 }
713
714 return lds_load(bld_base, type, swizzle, dw_addr);
715 }
716
717 static LLVMValueRef fetch_input_tes(
718 struct lp_build_tgsi_context *bld_base,
719 const struct tgsi_full_src_register *reg,
720 enum tgsi_opcode_type type, unsigned swizzle)
721 {
722 struct si_shader_context *ctx = si_shader_context(bld_base);
723 LLVMValueRef dw_addr, stride;
724
725 if (reg->Register.Dimension) {
726 stride = unpack_param(ctx, SI_PARAM_TCS_OUT_LAYOUT, 13, 8);
727 dw_addr = get_tcs_out_current_patch_offset(ctx);
728 dw_addr = get_dw_address(ctx, NULL, reg, stride, dw_addr);
729 } else {
730 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
731 dw_addr = get_dw_address(ctx, NULL, reg, NULL, dw_addr);
732 }
733
734 return lds_load(bld_base, type, swizzle, dw_addr);
735 }
736
737 static void store_output_tcs(struct lp_build_tgsi_context *bld_base,
738 const struct tgsi_full_instruction *inst,
739 const struct tgsi_opcode_info *info,
740 LLVMValueRef dst[4])
741 {
742 struct si_shader_context *ctx = si_shader_context(bld_base);
743 const struct tgsi_full_dst_register *reg = &inst->Dst[0];
744 unsigned chan_index;
745 LLVMValueRef dw_addr, stride;
746
747 /* Only handle per-patch and per-vertex outputs here.
748 * Vectors will be lowered to scalars and this function will be called again.
749 */
750 if (reg->Register.File != TGSI_FILE_OUTPUT ||
751 (dst[0] && LLVMGetTypeKind(LLVMTypeOf(dst[0])) == LLVMVectorTypeKind)) {
752 radeon_llvm_emit_store(bld_base, inst, info, dst);
753 return;
754 }
755
756 if (reg->Register.Dimension) {
757 stride = unpack_param(ctx, SI_PARAM_TCS_OUT_LAYOUT, 13, 8);
758 dw_addr = get_tcs_out_current_patch_offset(ctx);
759 dw_addr = get_dw_address(ctx, reg, NULL, stride, dw_addr);
760 } else {
761 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
762 dw_addr = get_dw_address(ctx, reg, NULL, NULL, dw_addr);
763 }
764
765 TGSI_FOR_EACH_DST0_ENABLED_CHANNEL(inst, chan_index) {
766 LLVMValueRef value = dst[chan_index];
767
768 if (inst->Instruction.Saturate)
769 value = radeon_llvm_saturate(bld_base, value);
770
771 lds_store(bld_base, chan_index, dw_addr, value);
772 }
773 }
774
775 static LLVMValueRef fetch_input_gs(
776 struct lp_build_tgsi_context *bld_base,
777 const struct tgsi_full_src_register *reg,
778 enum tgsi_opcode_type type,
779 unsigned swizzle)
780 {
781 struct lp_build_context *base = &bld_base->base;
782 struct si_shader_context *ctx = si_shader_context(bld_base);
783 struct si_shader *shader = ctx->shader;
784 struct lp_build_context *uint = &ctx->radeon_bld.soa.bld_base.uint_bld;
785 struct gallivm_state *gallivm = base->gallivm;
786 LLVMValueRef vtx_offset;
787 LLVMValueRef args[9];
788 unsigned vtx_offset_param;
789 struct tgsi_shader_info *info = &shader->selector->info;
790 unsigned semantic_name = info->input_semantic_name[reg->Register.Index];
791 unsigned semantic_index = info->input_semantic_index[reg->Register.Index];
792 unsigned param;
793 LLVMValueRef value;
794
795 if (swizzle != ~0 && semantic_name == TGSI_SEMANTIC_PRIMID)
796 return get_primitive_id(bld_base, swizzle);
797
798 if (!reg->Register.Dimension)
799 return NULL;
800
801 if (swizzle == ~0) {
802 LLVMValueRef values[TGSI_NUM_CHANNELS];
803 unsigned chan;
804 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
805 values[chan] = fetch_input_gs(bld_base, reg, type, chan);
806 }
807 return lp_build_gather_values(bld_base->base.gallivm, values,
808 TGSI_NUM_CHANNELS);
809 }
810
811 /* Get the vertex offset parameter */
812 vtx_offset_param = reg->Dimension.Index;
813 if (vtx_offset_param < 2) {
814 vtx_offset_param += SI_PARAM_VTX0_OFFSET;
815 } else {
816 assert(vtx_offset_param < 6);
817 vtx_offset_param += SI_PARAM_VTX2_OFFSET - 2;
818 }
819 vtx_offset = lp_build_mul_imm(uint,
820 LLVMGetParam(ctx->radeon_bld.main_fn,
821 vtx_offset_param),
822 4);
823
824 param = si_shader_io_get_unique_index(semantic_name, semantic_index);
825 args[0] = ctx->esgs_ring;
826 args[1] = vtx_offset;
827 args[2] = lp_build_const_int32(gallivm, (param * 4 + swizzle) * 256);
828 args[3] = uint->zero;
829 args[4] = uint->one; /* OFFEN */
830 args[5] = uint->zero; /* IDXEN */
831 args[6] = uint->one; /* GLC */
832 args[7] = uint->zero; /* SLC */
833 args[8] = uint->zero; /* TFE */
834
835 value = lp_build_intrinsic(gallivm->builder,
836 "llvm.SI.buffer.load.dword.i32.i32",
837 ctx->i32, args, 9,
838 LLVMReadOnlyAttribute | LLVMNoUnwindAttribute);
839 if (type == TGSI_TYPE_DOUBLE) {
840 LLVMValueRef value2;
841 args[2] = lp_build_const_int32(gallivm, (param * 4 + swizzle + 1) * 256);
842 value2 = lp_build_intrinsic(gallivm->builder,
843 "llvm.SI.buffer.load.dword.i32.i32",
844 ctx->i32, args, 9,
845 LLVMReadOnlyAttribute | LLVMNoUnwindAttribute);
846 return radeon_llvm_emit_fetch_double(bld_base,
847 value, value2);
848 }
849 return LLVMBuildBitCast(gallivm->builder,
850 value,
851 tgsi2llvmtype(bld_base, type), "");
852 }
853
854 static int lookup_interp_param_index(unsigned interpolate, unsigned location)
855 {
856 switch (interpolate) {
857 case TGSI_INTERPOLATE_CONSTANT:
858 return 0;
859
860 case TGSI_INTERPOLATE_LINEAR:
861 if (location == TGSI_INTERPOLATE_LOC_SAMPLE)
862 return SI_PARAM_LINEAR_SAMPLE;
863 else if (location == TGSI_INTERPOLATE_LOC_CENTROID)
864 return SI_PARAM_LINEAR_CENTROID;
865 else
866 return SI_PARAM_LINEAR_CENTER;
867 break;
868 case TGSI_INTERPOLATE_COLOR:
869 case TGSI_INTERPOLATE_PERSPECTIVE:
870 if (location == TGSI_INTERPOLATE_LOC_SAMPLE)
871 return SI_PARAM_PERSP_SAMPLE;
872 else if (location == TGSI_INTERPOLATE_LOC_CENTROID)
873 return SI_PARAM_PERSP_CENTROID;
874 else
875 return SI_PARAM_PERSP_CENTER;
876 break;
877 default:
878 fprintf(stderr, "Warning: Unhandled interpolation mode.\n");
879 return -1;
880 }
881 }
882
883 /* This shouldn't be used by explicit INTERP opcodes. */
884 static unsigned select_interp_param(struct si_shader_context *ctx,
885 unsigned param)
886 {
887 if (!ctx->shader->key.ps.prolog.force_persample_interp ||
888 !ctx->is_monolithic)
889 return param;
890
891 /* If the shader doesn't use center/centroid, just return the parameter.
892 *
893 * If the shader only uses one set of (i,j), "si_emit_spi_ps_input" can
894 * switch between center/centroid and sample without shader changes.
895 */
896 switch (param) {
897 case SI_PARAM_PERSP_CENTROID:
898 case SI_PARAM_PERSP_CENTER:
899 return SI_PARAM_PERSP_SAMPLE;
900
901 case SI_PARAM_LINEAR_CENTROID:
902 case SI_PARAM_LINEAR_CENTER:
903 return SI_PARAM_LINEAR_SAMPLE;
904
905 default:
906 return param;
907 }
908 }
909
910 /**
911 * Interpolate a fragment shader input.
912 *
913 * @param ctx context
914 * @param input_index index of the input in hardware
915 * @param semantic_name TGSI_SEMANTIC_*
916 * @param semantic_index semantic index
917 * @param num_interp_inputs number of all interpolated inputs (= BCOLOR offset)
918 * @param colors_read_mask color components read (4 bits for each color, 8 bits in total)
919 * @param interp_param interpolation weights (i,j)
920 * @param prim_mask SI_PARAM_PRIM_MASK
921 * @param face SI_PARAM_FRONT_FACE
922 * @param result the return value (4 components)
923 */
924 static void interp_fs_input(struct si_shader_context *ctx,
925 unsigned input_index,
926 unsigned semantic_name,
927 unsigned semantic_index,
928 unsigned num_interp_inputs,
929 unsigned colors_read_mask,
930 LLVMValueRef interp_param,
931 LLVMValueRef prim_mask,
932 LLVMValueRef face,
933 LLVMValueRef result[4])
934 {
935 struct lp_build_context *base = &ctx->radeon_bld.soa.bld_base.base;
936 struct lp_build_context *uint = &ctx->radeon_bld.soa.bld_base.uint_bld;
937 struct gallivm_state *gallivm = base->gallivm;
938 const char *intr_name;
939 LLVMValueRef attr_number;
940
941 unsigned chan;
942
943 attr_number = lp_build_const_int32(gallivm, input_index);
944
945 /* fs.constant returns the param from the middle vertex, so it's not
946 * really useful for flat shading. It's meant to be used for custom
947 * interpolation (but the intrinsic can't fetch from the other two
948 * vertices).
949 *
950 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
951 * to do the right thing. The only reason we use fs.constant is that
952 * fs.interp cannot be used on integers, because they can be equal
953 * to NaN.
954 */
955 intr_name = interp_param ? "llvm.SI.fs.interp" : "llvm.SI.fs.constant";
956
957 if (semantic_name == TGSI_SEMANTIC_COLOR &&
958 ctx->shader->key.ps.prolog.color_two_side) {
959 LLVMValueRef args[4];
960 LLVMValueRef is_face_positive;
961 LLVMValueRef back_attr_number;
962
963 /* If BCOLOR0 is used, BCOLOR1 is at offset "num_inputs + 1",
964 * otherwise it's at offset "num_inputs".
965 */
966 unsigned back_attr_offset = num_interp_inputs;
967 if (semantic_index == 1 && colors_read_mask & 0xf)
968 back_attr_offset += 1;
969
970 back_attr_number = lp_build_const_int32(gallivm, back_attr_offset);
971
972 is_face_positive = LLVMBuildICmp(gallivm->builder, LLVMIntNE,
973 face, uint->zero, "");
974
975 args[2] = prim_mask;
976 args[3] = interp_param;
977 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
978 LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan);
979 LLVMValueRef front, back;
980
981 args[0] = llvm_chan;
982 args[1] = attr_number;
983 front = lp_build_intrinsic(gallivm->builder, intr_name,
984 ctx->f32, args, args[3] ? 4 : 3,
985 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
986
987 args[1] = back_attr_number;
988 back = lp_build_intrinsic(gallivm->builder, intr_name,
989 ctx->f32, args, args[3] ? 4 : 3,
990 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
991
992 result[chan] = LLVMBuildSelect(gallivm->builder,
993 is_face_positive,
994 front,
995 back,
996 "");
997 }
998 } else if (semantic_name == TGSI_SEMANTIC_FOG) {
999 LLVMValueRef args[4];
1000
1001 args[0] = uint->zero;
1002 args[1] = attr_number;
1003 args[2] = prim_mask;
1004 args[3] = interp_param;
1005 result[0] = lp_build_intrinsic(gallivm->builder, intr_name,
1006 ctx->f32, args, args[3] ? 4 : 3,
1007 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
1008 result[1] =
1009 result[2] = lp_build_const_float(gallivm, 0.0f);
1010 result[3] = lp_build_const_float(gallivm, 1.0f);
1011 } else {
1012 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1013 LLVMValueRef args[4];
1014 LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan);
1015
1016 args[0] = llvm_chan;
1017 args[1] = attr_number;
1018 args[2] = prim_mask;
1019 args[3] = interp_param;
1020 result[chan] = lp_build_intrinsic(gallivm->builder, intr_name,
1021 ctx->f32, args, args[3] ? 4 : 3,
1022 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
1023 }
1024 }
1025 }
1026
1027 static void declare_input_fs(
1028 struct radeon_llvm_context *radeon_bld,
1029 unsigned input_index,
1030 const struct tgsi_full_declaration *decl)
1031 {
1032 struct lp_build_context *base = &radeon_bld->soa.bld_base.base;
1033 struct si_shader_context *ctx =
1034 si_shader_context(&radeon_bld->soa.bld_base);
1035 struct si_shader *shader = ctx->shader;
1036 LLVMValueRef main_fn = radeon_bld->main_fn;
1037 LLVMValueRef interp_param = NULL;
1038 int interp_param_idx;
1039
1040 /* Get colors from input VGPRs (set by the prolog). */
1041 if (!ctx->is_monolithic &&
1042 decl->Semantic.Name == TGSI_SEMANTIC_COLOR) {
1043 unsigned i = decl->Semantic.Index;
1044 unsigned colors_read = shader->selector->info.colors_read;
1045 unsigned mask = colors_read >> (i * 4);
1046 unsigned offset = SI_PARAM_POS_FIXED_PT + 1 +
1047 (i ? util_bitcount(colors_read & 0xf) : 0);
1048
1049 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 0)] =
1050 mask & 0x1 ? LLVMGetParam(main_fn, offset++) : base->undef;
1051 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 1)] =
1052 mask & 0x2 ? LLVMGetParam(main_fn, offset++) : base->undef;
1053 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 2)] =
1054 mask & 0x4 ? LLVMGetParam(main_fn, offset++) : base->undef;
1055 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 3)] =
1056 mask & 0x8 ? LLVMGetParam(main_fn, offset++) : base->undef;
1057 return;
1058 }
1059
1060 interp_param_idx = lookup_interp_param_index(decl->Interp.Interpolate,
1061 decl->Interp.Location);
1062 if (interp_param_idx == -1)
1063 return;
1064 else if (interp_param_idx) {
1065 interp_param_idx = select_interp_param(ctx,
1066 interp_param_idx);
1067 interp_param = LLVMGetParam(main_fn, interp_param_idx);
1068 }
1069
1070 interp_fs_input(ctx, input_index, decl->Semantic.Name,
1071 decl->Semantic.Index, shader->selector->info.num_inputs,
1072 shader->selector->info.colors_read, interp_param,
1073 LLVMGetParam(main_fn, SI_PARAM_PRIM_MASK),
1074 LLVMGetParam(main_fn, SI_PARAM_FRONT_FACE),
1075 &radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 0)]);
1076 }
1077
1078 static LLVMValueRef get_sample_id(struct radeon_llvm_context *radeon_bld)
1079 {
1080 return unpack_param(si_shader_context(&radeon_bld->soa.bld_base),
1081 SI_PARAM_ANCILLARY, 8, 4);
1082 }
1083
1084 /**
1085 * Load a dword from a constant buffer.
1086 */
1087 static LLVMValueRef buffer_load_const(LLVMBuilderRef builder, LLVMValueRef resource,
1088 LLVMValueRef offset, LLVMTypeRef return_type)
1089 {
1090 LLVMValueRef args[2] = {resource, offset};
1091
1092 return lp_build_intrinsic(builder, "llvm.SI.load.const", return_type, args, 2,
1093 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
1094 }
1095
1096 static LLVMValueRef load_sample_position(struct radeon_llvm_context *radeon_bld, LLVMValueRef sample_id)
1097 {
1098 struct si_shader_context *ctx =
1099 si_shader_context(&radeon_bld->soa.bld_base);
1100 struct lp_build_context *uint_bld = &radeon_bld->soa.bld_base.uint_bld;
1101 struct gallivm_state *gallivm = &radeon_bld->gallivm;
1102 LLVMBuilderRef builder = gallivm->builder;
1103 LLVMValueRef desc = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_CONST_BUFFERS);
1104 LLVMValueRef buf_index = lp_build_const_int32(gallivm, SI_DRIVER_STATE_CONST_BUF);
1105 LLVMValueRef resource = build_indexed_load_const(ctx, desc, buf_index);
1106
1107 /* offset = sample_id * 8 (8 = 2 floats containing samplepos.xy) */
1108 LLVMValueRef offset0 = lp_build_mul_imm(uint_bld, sample_id, 8);
1109 LLVMValueRef offset1 = LLVMBuildAdd(builder, offset0, lp_build_const_int32(gallivm, 4), "");
1110
1111 LLVMValueRef pos[4] = {
1112 buffer_load_const(builder, resource, offset0, ctx->f32),
1113 buffer_load_const(builder, resource, offset1, ctx->f32),
1114 lp_build_const_float(gallivm, 0),
1115 lp_build_const_float(gallivm, 0)
1116 };
1117
1118 return lp_build_gather_values(gallivm, pos, 4);
1119 }
1120
1121 static void declare_system_value(
1122 struct radeon_llvm_context *radeon_bld,
1123 unsigned index,
1124 const struct tgsi_full_declaration *decl)
1125 {
1126 struct si_shader_context *ctx =
1127 si_shader_context(&radeon_bld->soa.bld_base);
1128 struct lp_build_context *bld = &radeon_bld->soa.bld_base.base;
1129 struct gallivm_state *gallivm = &radeon_bld->gallivm;
1130 LLVMValueRef value = 0;
1131
1132 switch (decl->Semantic.Name) {
1133 case TGSI_SEMANTIC_INSTANCEID:
1134 value = LLVMGetParam(radeon_bld->main_fn,
1135 ctx->param_instance_id);
1136 break;
1137
1138 case TGSI_SEMANTIC_VERTEXID:
1139 value = LLVMBuildAdd(gallivm->builder,
1140 LLVMGetParam(radeon_bld->main_fn,
1141 ctx->param_vertex_id),
1142 LLVMGetParam(radeon_bld->main_fn,
1143 SI_PARAM_BASE_VERTEX), "");
1144 break;
1145
1146 case TGSI_SEMANTIC_VERTEXID_NOBASE:
1147 value = LLVMGetParam(radeon_bld->main_fn,
1148 ctx->param_vertex_id);
1149 break;
1150
1151 case TGSI_SEMANTIC_BASEVERTEX:
1152 value = LLVMGetParam(radeon_bld->main_fn,
1153 SI_PARAM_BASE_VERTEX);
1154 break;
1155
1156 case TGSI_SEMANTIC_INVOCATIONID:
1157 if (ctx->type == TGSI_PROCESSOR_TESS_CTRL)
1158 value = unpack_param(ctx, SI_PARAM_REL_IDS, 8, 5);
1159 else if (ctx->type == TGSI_PROCESSOR_GEOMETRY)
1160 value = LLVMGetParam(radeon_bld->main_fn,
1161 SI_PARAM_GS_INSTANCE_ID);
1162 else
1163 assert(!"INVOCATIONID not implemented");
1164 break;
1165
1166 case TGSI_SEMANTIC_POSITION:
1167 {
1168 LLVMValueRef pos[4] = {
1169 LLVMGetParam(radeon_bld->main_fn, SI_PARAM_POS_X_FLOAT),
1170 LLVMGetParam(radeon_bld->main_fn, SI_PARAM_POS_Y_FLOAT),
1171 LLVMGetParam(radeon_bld->main_fn, SI_PARAM_POS_Z_FLOAT),
1172 lp_build_emit_llvm_unary(&radeon_bld->soa.bld_base, TGSI_OPCODE_RCP,
1173 LLVMGetParam(radeon_bld->main_fn,
1174 SI_PARAM_POS_W_FLOAT)),
1175 };
1176 value = lp_build_gather_values(gallivm, pos, 4);
1177 break;
1178 }
1179
1180 case TGSI_SEMANTIC_FACE:
1181 value = LLVMGetParam(radeon_bld->main_fn, SI_PARAM_FRONT_FACE);
1182 break;
1183
1184 case TGSI_SEMANTIC_SAMPLEID:
1185 value = get_sample_id(radeon_bld);
1186 break;
1187
1188 case TGSI_SEMANTIC_SAMPLEPOS: {
1189 LLVMValueRef pos[4] = {
1190 LLVMGetParam(radeon_bld->main_fn, SI_PARAM_POS_X_FLOAT),
1191 LLVMGetParam(radeon_bld->main_fn, SI_PARAM_POS_Y_FLOAT),
1192 lp_build_const_float(gallivm, 0),
1193 lp_build_const_float(gallivm, 0)
1194 };
1195 pos[0] = lp_build_emit_llvm_unary(&radeon_bld->soa.bld_base,
1196 TGSI_OPCODE_FRC, pos[0]);
1197 pos[1] = lp_build_emit_llvm_unary(&radeon_bld->soa.bld_base,
1198 TGSI_OPCODE_FRC, pos[1]);
1199 value = lp_build_gather_values(gallivm, pos, 4);
1200 break;
1201 }
1202
1203 case TGSI_SEMANTIC_SAMPLEMASK:
1204 /* This can only occur with the OpenGL Core profile, which
1205 * doesn't support smoothing.
1206 */
1207 value = LLVMGetParam(radeon_bld->main_fn, SI_PARAM_SAMPLE_COVERAGE);
1208 break;
1209
1210 case TGSI_SEMANTIC_TESSCOORD:
1211 {
1212 LLVMValueRef coord[4] = {
1213 LLVMGetParam(radeon_bld->main_fn, ctx->param_tes_u),
1214 LLVMGetParam(radeon_bld->main_fn, ctx->param_tes_v),
1215 bld->zero,
1216 bld->zero
1217 };
1218
1219 /* For triangles, the vector should be (u, v, 1-u-v). */
1220 if (ctx->shader->selector->info.properties[TGSI_PROPERTY_TES_PRIM_MODE] ==
1221 PIPE_PRIM_TRIANGLES)
1222 coord[2] = lp_build_sub(bld, bld->one,
1223 lp_build_add(bld, coord[0], coord[1]));
1224
1225 value = lp_build_gather_values(gallivm, coord, 4);
1226 break;
1227 }
1228
1229 case TGSI_SEMANTIC_VERTICESIN:
1230 value = unpack_param(ctx, SI_PARAM_TCS_OUT_LAYOUT, 26, 6);
1231 break;
1232
1233 case TGSI_SEMANTIC_TESSINNER:
1234 case TGSI_SEMANTIC_TESSOUTER:
1235 {
1236 LLVMValueRef dw_addr;
1237 int param = si_shader_io_get_unique_index(decl->Semantic.Name, 0);
1238
1239 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1240 dw_addr = LLVMBuildAdd(gallivm->builder, dw_addr,
1241 lp_build_const_int32(gallivm, param * 4), "");
1242
1243 value = lds_load(&radeon_bld->soa.bld_base, TGSI_TYPE_FLOAT,
1244 ~0, dw_addr);
1245 break;
1246 }
1247
1248 case TGSI_SEMANTIC_PRIMID:
1249 value = get_primitive_id(&radeon_bld->soa.bld_base, 0);
1250 break;
1251
1252 default:
1253 assert(!"unknown system value");
1254 return;
1255 }
1256
1257 radeon_bld->system_values[index] = value;
1258 }
1259
1260 static LLVMValueRef fetch_constant(
1261 struct lp_build_tgsi_context *bld_base,
1262 const struct tgsi_full_src_register *reg,
1263 enum tgsi_opcode_type type,
1264 unsigned swizzle)
1265 {
1266 struct si_shader_context *ctx = si_shader_context(bld_base);
1267 struct lp_build_context *base = &bld_base->base;
1268 const struct tgsi_ind_register *ireg = &reg->Indirect;
1269 unsigned buf, idx;
1270
1271 LLVMValueRef addr, bufp;
1272 LLVMValueRef result;
1273
1274 if (swizzle == LP_CHAN_ALL) {
1275 unsigned chan;
1276 LLVMValueRef values[4];
1277 for (chan = 0; chan < TGSI_NUM_CHANNELS; ++chan)
1278 values[chan] = fetch_constant(bld_base, reg, type, chan);
1279
1280 return lp_build_gather_values(bld_base->base.gallivm, values, 4);
1281 }
1282
1283 buf = reg->Register.Dimension ? reg->Dimension.Index : 0;
1284 idx = reg->Register.Index * 4 + swizzle;
1285
1286 if (!reg->Register.Indirect && !reg->Dimension.Indirect) {
1287 if (type != TGSI_TYPE_DOUBLE)
1288 return bitcast(bld_base, type, ctx->constants[buf][idx]);
1289 else {
1290 return radeon_llvm_emit_fetch_double(bld_base,
1291 ctx->constants[buf][idx],
1292 ctx->constants[buf][idx + 1]);
1293 }
1294 }
1295
1296 if (reg->Register.Dimension && reg->Dimension.Indirect) {
1297 LLVMValueRef ptr = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_CONST_BUFFERS);
1298 LLVMValueRef index;
1299 index = get_indirect_index(ctx, &reg->DimIndirect,
1300 reg->Dimension.Index);
1301 bufp = build_indexed_load_const(ctx, ptr, index);
1302 } else
1303 bufp = ctx->const_buffers[buf];
1304
1305 addr = ctx->radeon_bld.soa.addr[ireg->Index][ireg->Swizzle];
1306 addr = LLVMBuildLoad(base->gallivm->builder, addr, "load addr reg");
1307 addr = lp_build_mul_imm(&bld_base->uint_bld, addr, 16);
1308 addr = lp_build_add(&bld_base->uint_bld, addr,
1309 lp_build_const_int32(base->gallivm, idx * 4));
1310
1311 result = buffer_load_const(base->gallivm->builder, bufp,
1312 addr, ctx->f32);
1313
1314 if (type != TGSI_TYPE_DOUBLE)
1315 result = bitcast(bld_base, type, result);
1316 else {
1317 LLVMValueRef addr2, result2;
1318 addr2 = ctx->radeon_bld.soa.addr[ireg->Index][ireg->Swizzle + 1];
1319 addr2 = LLVMBuildLoad(base->gallivm->builder, addr2, "load addr reg2");
1320 addr2 = lp_build_mul_imm(&bld_base->uint_bld, addr2, 16);
1321 addr2 = lp_build_add(&bld_base->uint_bld, addr2,
1322 lp_build_const_int32(base->gallivm, idx * 4));
1323
1324 result2 = buffer_load_const(base->gallivm->builder, ctx->const_buffers[buf],
1325 addr2, ctx->f32);
1326
1327 result = radeon_llvm_emit_fetch_double(bld_base,
1328 result, result2);
1329 }
1330 return result;
1331 }
1332
1333 /* Upper 16 bits must be zero. */
1334 static LLVMValueRef si_llvm_pack_two_int16(struct gallivm_state *gallivm,
1335 LLVMValueRef val[2])
1336 {
1337 return LLVMBuildOr(gallivm->builder, val[0],
1338 LLVMBuildShl(gallivm->builder, val[1],
1339 lp_build_const_int32(gallivm, 16),
1340 ""), "");
1341 }
1342
1343 /* Upper 16 bits are ignored and will be dropped. */
1344 static LLVMValueRef si_llvm_pack_two_int32_as_int16(struct gallivm_state *gallivm,
1345 LLVMValueRef val[2])
1346 {
1347 LLVMValueRef v[2] = {
1348 LLVMBuildAnd(gallivm->builder, val[0],
1349 lp_build_const_int32(gallivm, 0xffff), ""),
1350 val[1],
1351 };
1352 return si_llvm_pack_two_int16(gallivm, v);
1353 }
1354
1355 /* Initialize arguments for the shader export intrinsic */
1356 static void si_llvm_init_export_args(struct lp_build_tgsi_context *bld_base,
1357 LLVMValueRef *values,
1358 unsigned target,
1359 LLVMValueRef *args)
1360 {
1361 struct si_shader_context *ctx = si_shader_context(bld_base);
1362 struct lp_build_context *uint =
1363 &ctx->radeon_bld.soa.bld_base.uint_bld;
1364 struct lp_build_context *base = &bld_base->base;
1365 struct gallivm_state *gallivm = base->gallivm;
1366 LLVMBuilderRef builder = base->gallivm->builder;
1367 LLVMValueRef val[4];
1368 unsigned spi_shader_col_format = V_028714_SPI_SHADER_32_ABGR;
1369 unsigned chan;
1370 bool is_int8;
1371
1372 /* Default is 0xf. Adjusted below depending on the format. */
1373 args[0] = lp_build_const_int32(base->gallivm, 0xf); /* writemask */
1374
1375 /* Specify whether the EXEC mask represents the valid mask */
1376 args[1] = uint->zero;
1377
1378 /* Specify whether this is the last export */
1379 args[2] = uint->zero;
1380
1381 /* Specify the target we are exporting */
1382 args[3] = lp_build_const_int32(base->gallivm, target);
1383
1384 if (ctx->type == TGSI_PROCESSOR_FRAGMENT) {
1385 const union si_shader_key *key = &ctx->shader->key;
1386 unsigned col_formats = key->ps.epilog.spi_shader_col_format;
1387 int cbuf = target - V_008DFC_SQ_EXP_MRT;
1388
1389 assert(cbuf >= 0 && cbuf < 8);
1390 spi_shader_col_format = (col_formats >> (cbuf * 4)) & 0xf;
1391 is_int8 = (key->ps.epilog.color_is_int8 >> cbuf) & 0x1;
1392 }
1393
1394 args[4] = uint->zero; /* COMPR flag */
1395 args[5] = base->undef;
1396 args[6] = base->undef;
1397 args[7] = base->undef;
1398 args[8] = base->undef;
1399
1400 switch (spi_shader_col_format) {
1401 case V_028714_SPI_SHADER_ZERO:
1402 args[0] = uint->zero; /* writemask */
1403 args[3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_NULL);
1404 break;
1405
1406 case V_028714_SPI_SHADER_32_R:
1407 args[0] = uint->one; /* writemask */
1408 args[5] = values[0];
1409 break;
1410
1411 case V_028714_SPI_SHADER_32_GR:
1412 args[0] = lp_build_const_int32(base->gallivm, 0x3); /* writemask */
1413 args[5] = values[0];
1414 args[6] = values[1];
1415 break;
1416
1417 case V_028714_SPI_SHADER_32_AR:
1418 args[0] = lp_build_const_int32(base->gallivm, 0x9); /* writemask */
1419 args[5] = values[0];
1420 args[8] = values[3];
1421 break;
1422
1423 case V_028714_SPI_SHADER_FP16_ABGR:
1424 args[4] = uint->one; /* COMPR flag */
1425
1426 for (chan = 0; chan < 2; chan++) {
1427 LLVMValueRef pack_args[2] = {
1428 values[2 * chan],
1429 values[2 * chan + 1]
1430 };
1431 LLVMValueRef packed;
1432
1433 packed = lp_build_intrinsic(base->gallivm->builder,
1434 "llvm.SI.packf16",
1435 ctx->i32, pack_args, 2,
1436 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
1437 args[chan + 5] =
1438 LLVMBuildBitCast(base->gallivm->builder,
1439 packed, ctx->f32, "");
1440 }
1441 break;
1442
1443 case V_028714_SPI_SHADER_UNORM16_ABGR:
1444 for (chan = 0; chan < 4; chan++) {
1445 val[chan] = radeon_llvm_saturate(bld_base, values[chan]);
1446 val[chan] = LLVMBuildFMul(builder, val[chan],
1447 lp_build_const_float(gallivm, 65535), "");
1448 val[chan] = LLVMBuildFAdd(builder, val[chan],
1449 lp_build_const_float(gallivm, 0.5), "");
1450 val[chan] = LLVMBuildFPToUI(builder, val[chan],
1451 ctx->i32, "");
1452 }
1453
1454 args[4] = uint->one; /* COMPR flag */
1455 args[5] = bitcast(bld_base, TGSI_TYPE_FLOAT,
1456 si_llvm_pack_two_int16(gallivm, val));
1457 args[6] = bitcast(bld_base, TGSI_TYPE_FLOAT,
1458 si_llvm_pack_two_int16(gallivm, val+2));
1459 break;
1460
1461 case V_028714_SPI_SHADER_SNORM16_ABGR:
1462 for (chan = 0; chan < 4; chan++) {
1463 /* Clamp between [-1, 1]. */
1464 val[chan] = lp_build_emit_llvm_binary(bld_base, TGSI_OPCODE_MIN,
1465 values[chan],
1466 lp_build_const_float(gallivm, 1));
1467 val[chan] = lp_build_emit_llvm_binary(bld_base, TGSI_OPCODE_MAX,
1468 val[chan],
1469 lp_build_const_float(gallivm, -1));
1470 /* Convert to a signed integer in [-32767, 32767]. */
1471 val[chan] = LLVMBuildFMul(builder, val[chan],
1472 lp_build_const_float(gallivm, 32767), "");
1473 /* If positive, add 0.5, else add -0.5. */
1474 val[chan] = LLVMBuildFAdd(builder, val[chan],
1475 LLVMBuildSelect(builder,
1476 LLVMBuildFCmp(builder, LLVMRealOGE,
1477 val[chan], base->zero, ""),
1478 lp_build_const_float(gallivm, 0.5),
1479 lp_build_const_float(gallivm, -0.5), ""), "");
1480 val[chan] = LLVMBuildFPToSI(builder, val[chan], ctx->i32, "");
1481 }
1482
1483 args[4] = uint->one; /* COMPR flag */
1484 args[5] = bitcast(bld_base, TGSI_TYPE_FLOAT,
1485 si_llvm_pack_two_int32_as_int16(gallivm, val));
1486 args[6] = bitcast(bld_base, TGSI_TYPE_FLOAT,
1487 si_llvm_pack_two_int32_as_int16(gallivm, val+2));
1488 break;
1489
1490 case V_028714_SPI_SHADER_UINT16_ABGR: {
1491 LLVMValueRef max = lp_build_const_int32(gallivm, is_int8 ?
1492 255 : 65535);
1493 /* Clamp. */
1494 for (chan = 0; chan < 4; chan++) {
1495 val[chan] = bitcast(bld_base, TGSI_TYPE_UNSIGNED, values[chan]);
1496 val[chan] = lp_build_emit_llvm_binary(bld_base, TGSI_OPCODE_UMIN,
1497 val[chan], max);
1498 }
1499
1500 args[4] = uint->one; /* COMPR flag */
1501 args[5] = bitcast(bld_base, TGSI_TYPE_FLOAT,
1502 si_llvm_pack_two_int16(gallivm, val));
1503 args[6] = bitcast(bld_base, TGSI_TYPE_FLOAT,
1504 si_llvm_pack_two_int16(gallivm, val+2));
1505 break;
1506 }
1507
1508 case V_028714_SPI_SHADER_SINT16_ABGR: {
1509 LLVMValueRef max = lp_build_const_int32(gallivm, is_int8 ?
1510 127 : 32767);
1511 LLVMValueRef min = lp_build_const_int32(gallivm, is_int8 ?
1512 -128 : -32768);
1513 /* Clamp. */
1514 for (chan = 0; chan < 4; chan++) {
1515 val[chan] = bitcast(bld_base, TGSI_TYPE_UNSIGNED, values[chan]);
1516 val[chan] = lp_build_emit_llvm_binary(bld_base,
1517 TGSI_OPCODE_IMIN,
1518 val[chan], max);
1519 val[chan] = lp_build_emit_llvm_binary(bld_base,
1520 TGSI_OPCODE_IMAX,
1521 val[chan], min);
1522 }
1523
1524 args[4] = uint->one; /* COMPR flag */
1525 args[5] = bitcast(bld_base, TGSI_TYPE_FLOAT,
1526 si_llvm_pack_two_int32_as_int16(gallivm, val));
1527 args[6] = bitcast(bld_base, TGSI_TYPE_FLOAT,
1528 si_llvm_pack_two_int32_as_int16(gallivm, val+2));
1529 break;
1530 }
1531
1532 case V_028714_SPI_SHADER_32_ABGR:
1533 memcpy(&args[5], values, sizeof(values[0]) * 4);
1534 break;
1535 }
1536 }
1537
1538 static void si_alpha_test(struct lp_build_tgsi_context *bld_base,
1539 LLVMValueRef alpha)
1540 {
1541 struct si_shader_context *ctx = si_shader_context(bld_base);
1542 struct gallivm_state *gallivm = bld_base->base.gallivm;
1543
1544 if (ctx->shader->key.ps.epilog.alpha_func != PIPE_FUNC_NEVER) {
1545 LLVMValueRef alpha_ref = LLVMGetParam(ctx->radeon_bld.main_fn,
1546 SI_PARAM_ALPHA_REF);
1547
1548 LLVMValueRef alpha_pass =
1549 lp_build_cmp(&bld_base->base,
1550 ctx->shader->key.ps.epilog.alpha_func,
1551 alpha, alpha_ref);
1552 LLVMValueRef arg =
1553 lp_build_select(&bld_base->base,
1554 alpha_pass,
1555 lp_build_const_float(gallivm, 1.0f),
1556 lp_build_const_float(gallivm, -1.0f));
1557
1558 lp_build_intrinsic(gallivm->builder, "llvm.AMDGPU.kill",
1559 ctx->voidt, &arg, 1, 0);
1560 } else {
1561 lp_build_intrinsic(gallivm->builder, "llvm.AMDGPU.kilp",
1562 ctx->voidt, NULL, 0, 0);
1563 }
1564 }
1565
1566 static LLVMValueRef si_scale_alpha_by_sample_mask(struct lp_build_tgsi_context *bld_base,
1567 LLVMValueRef alpha,
1568 unsigned samplemask_param)
1569 {
1570 struct si_shader_context *ctx = si_shader_context(bld_base);
1571 struct gallivm_state *gallivm = bld_base->base.gallivm;
1572 LLVMValueRef coverage;
1573
1574 /* alpha = alpha * popcount(coverage) / SI_NUM_SMOOTH_AA_SAMPLES */
1575 coverage = LLVMGetParam(ctx->radeon_bld.main_fn,
1576 samplemask_param);
1577 coverage = bitcast(bld_base, TGSI_TYPE_SIGNED, coverage);
1578
1579 coverage = lp_build_intrinsic(gallivm->builder, "llvm.ctpop.i32",
1580 ctx->i32,
1581 &coverage, 1, LLVMReadNoneAttribute);
1582
1583 coverage = LLVMBuildUIToFP(gallivm->builder, coverage,
1584 ctx->f32, "");
1585
1586 coverage = LLVMBuildFMul(gallivm->builder, coverage,
1587 lp_build_const_float(gallivm,
1588 1.0 / SI_NUM_SMOOTH_AA_SAMPLES), "");
1589
1590 return LLVMBuildFMul(gallivm->builder, alpha, coverage, "");
1591 }
1592
1593 static void si_llvm_emit_clipvertex(struct lp_build_tgsi_context *bld_base,
1594 LLVMValueRef (*pos)[9], LLVMValueRef *out_elts)
1595 {
1596 struct si_shader_context *ctx = si_shader_context(bld_base);
1597 struct lp_build_context *base = &bld_base->base;
1598 struct lp_build_context *uint = &ctx->radeon_bld.soa.bld_base.uint_bld;
1599 unsigned reg_index;
1600 unsigned chan;
1601 unsigned const_chan;
1602 LLVMValueRef base_elt;
1603 LLVMValueRef ptr = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_CONST_BUFFERS);
1604 LLVMValueRef constbuf_index = lp_build_const_int32(base->gallivm, SI_DRIVER_STATE_CONST_BUF);
1605 LLVMValueRef const_resource = build_indexed_load_const(ctx, ptr, constbuf_index);
1606
1607 for (reg_index = 0; reg_index < 2; reg_index ++) {
1608 LLVMValueRef *args = pos[2 + reg_index];
1609
1610 args[5] =
1611 args[6] =
1612 args[7] =
1613 args[8] = lp_build_const_float(base->gallivm, 0.0f);
1614
1615 /* Compute dot products of position and user clip plane vectors */
1616 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1617 for (const_chan = 0; const_chan < TGSI_NUM_CHANNELS; const_chan++) {
1618 args[1] = lp_build_const_int32(base->gallivm,
1619 ((reg_index * 4 + chan) * 4 +
1620 const_chan) * 4);
1621 base_elt = buffer_load_const(base->gallivm->builder, const_resource,
1622 args[1], ctx->f32);
1623 args[5 + chan] =
1624 lp_build_add(base, args[5 + chan],
1625 lp_build_mul(base, base_elt,
1626 out_elts[const_chan]));
1627 }
1628 }
1629
1630 args[0] = lp_build_const_int32(base->gallivm, 0xf);
1631 args[1] = uint->zero;
1632 args[2] = uint->zero;
1633 args[3] = lp_build_const_int32(base->gallivm,
1634 V_008DFC_SQ_EXP_POS + 2 + reg_index);
1635 args[4] = uint->zero;
1636 }
1637 }
1638
1639 static void si_dump_streamout(struct pipe_stream_output_info *so)
1640 {
1641 unsigned i;
1642
1643 if (so->num_outputs)
1644 fprintf(stderr, "STREAMOUT\n");
1645
1646 for (i = 0; i < so->num_outputs; i++) {
1647 unsigned mask = ((1 << so->output[i].num_components) - 1) <<
1648 so->output[i].start_component;
1649 fprintf(stderr, " %i: BUF%i[%i..%i] <- OUT[%i].%s%s%s%s\n",
1650 i, so->output[i].output_buffer,
1651 so->output[i].dst_offset, so->output[i].dst_offset + so->output[i].num_components - 1,
1652 so->output[i].register_index,
1653 mask & 1 ? "x" : "",
1654 mask & 2 ? "y" : "",
1655 mask & 4 ? "z" : "",
1656 mask & 8 ? "w" : "");
1657 }
1658 }
1659
1660 /* TBUFFER_STORE_FORMAT_{X,XY,XYZ,XYZW} <- the suffix is selected by num_channels=1..4.
1661 * The type of vdata must be one of i32 (num_channels=1), v2i32 (num_channels=2),
1662 * or v4i32 (num_channels=3,4). */
1663 static void build_tbuffer_store(struct si_shader_context *ctx,
1664 LLVMValueRef rsrc,
1665 LLVMValueRef vdata,
1666 unsigned num_channels,
1667 LLVMValueRef vaddr,
1668 LLVMValueRef soffset,
1669 unsigned inst_offset,
1670 unsigned dfmt,
1671 unsigned nfmt,
1672 unsigned offen,
1673 unsigned idxen,
1674 unsigned glc,
1675 unsigned slc,
1676 unsigned tfe)
1677 {
1678 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
1679 LLVMValueRef args[] = {
1680 rsrc,
1681 vdata,
1682 LLVMConstInt(ctx->i32, num_channels, 0),
1683 vaddr,
1684 soffset,
1685 LLVMConstInt(ctx->i32, inst_offset, 0),
1686 LLVMConstInt(ctx->i32, dfmt, 0),
1687 LLVMConstInt(ctx->i32, nfmt, 0),
1688 LLVMConstInt(ctx->i32, offen, 0),
1689 LLVMConstInt(ctx->i32, idxen, 0),
1690 LLVMConstInt(ctx->i32, glc, 0),
1691 LLVMConstInt(ctx->i32, slc, 0),
1692 LLVMConstInt(ctx->i32, tfe, 0)
1693 };
1694
1695 /* The instruction offset field has 12 bits */
1696 assert(offen || inst_offset < (1 << 12));
1697
1698 /* The intrinsic is overloaded, we need to add a type suffix for overloading to work. */
1699 unsigned func = CLAMP(num_channels, 1, 3) - 1;
1700 const char *types[] = {"i32", "v2i32", "v4i32"};
1701 char name[256];
1702 snprintf(name, sizeof(name), "llvm.SI.tbuffer.store.%s", types[func]);
1703
1704 lp_build_intrinsic(gallivm->builder, name, ctx->voidt,
1705 args, Elements(args), 0);
1706 }
1707
1708 static void build_tbuffer_store_dwords(struct si_shader_context *ctx,
1709 LLVMValueRef rsrc,
1710 LLVMValueRef vdata,
1711 unsigned num_channels,
1712 LLVMValueRef vaddr,
1713 LLVMValueRef soffset,
1714 unsigned inst_offset)
1715 {
1716 static unsigned dfmt[] = {
1717 V_008F0C_BUF_DATA_FORMAT_32,
1718 V_008F0C_BUF_DATA_FORMAT_32_32,
1719 V_008F0C_BUF_DATA_FORMAT_32_32_32,
1720 V_008F0C_BUF_DATA_FORMAT_32_32_32_32
1721 };
1722 assert(num_channels >= 1 && num_channels <= 4);
1723
1724 build_tbuffer_store(ctx, rsrc, vdata, num_channels, vaddr, soffset,
1725 inst_offset, dfmt[num_channels-1],
1726 V_008F0C_BUF_NUM_FORMAT_UINT, 1, 0, 1, 1, 0);
1727 }
1728
1729 /* On SI, the vertex shader is responsible for writing streamout data
1730 * to buffers. */
1731 static void si_llvm_emit_streamout(struct si_shader_context *ctx,
1732 struct si_shader_output_values *outputs,
1733 unsigned noutput)
1734 {
1735 struct pipe_stream_output_info *so = &ctx->shader->selector->so;
1736 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
1737 LLVMBuilderRef builder = gallivm->builder;
1738 int i, j;
1739 struct lp_build_if_state if_ctx;
1740
1741 /* Get bits [22:16], i.e. (so_param >> 16) & 127; */
1742 LLVMValueRef so_vtx_count =
1743 unpack_param(ctx, ctx->param_streamout_config, 16, 7);
1744
1745 LLVMValueRef tid = lp_build_intrinsic(builder, "llvm.SI.tid", ctx->i32,
1746 NULL, 0, LLVMReadNoneAttribute);
1747
1748 /* can_emit = tid < so_vtx_count; */
1749 LLVMValueRef can_emit =
1750 LLVMBuildICmp(builder, LLVMIntULT, tid, so_vtx_count, "");
1751
1752 LLVMValueRef stream_id =
1753 unpack_param(ctx, ctx->param_streamout_config, 24, 2);
1754
1755 /* Emit the streamout code conditionally. This actually avoids
1756 * out-of-bounds buffer access. The hw tells us via the SGPR
1757 * (so_vtx_count) which threads are allowed to emit streamout data. */
1758 lp_build_if(&if_ctx, gallivm, can_emit);
1759 {
1760 /* The buffer offset is computed as follows:
1761 * ByteOffset = streamout_offset[buffer_id]*4 +
1762 * (streamout_write_index + thread_id)*stride[buffer_id] +
1763 * attrib_offset
1764 */
1765
1766 LLVMValueRef so_write_index =
1767 LLVMGetParam(ctx->radeon_bld.main_fn,
1768 ctx->param_streamout_write_index);
1769
1770 /* Compute (streamout_write_index + thread_id). */
1771 so_write_index = LLVMBuildAdd(builder, so_write_index, tid, "");
1772
1773 /* Compute the write offset for each enabled buffer. */
1774 LLVMValueRef so_write_offset[4] = {};
1775 for (i = 0; i < 4; i++) {
1776 if (!so->stride[i])
1777 continue;
1778
1779 LLVMValueRef so_offset = LLVMGetParam(ctx->radeon_bld.main_fn,
1780 ctx->param_streamout_offset[i]);
1781 so_offset = LLVMBuildMul(builder, so_offset, LLVMConstInt(ctx->i32, 4, 0), "");
1782
1783 so_write_offset[i] = LLVMBuildMul(builder, so_write_index,
1784 LLVMConstInt(ctx->i32, so->stride[i]*4, 0), "");
1785 so_write_offset[i] = LLVMBuildAdd(builder, so_write_offset[i], so_offset, "");
1786 }
1787
1788 /* Write streamout data. */
1789 for (i = 0; i < so->num_outputs; i++) {
1790 unsigned buf_idx = so->output[i].output_buffer;
1791 unsigned reg = so->output[i].register_index;
1792 unsigned start = so->output[i].start_component;
1793 unsigned num_comps = so->output[i].num_components;
1794 unsigned stream = so->output[i].stream;
1795 LLVMValueRef out[4];
1796 struct lp_build_if_state if_ctx_stream;
1797
1798 assert(num_comps && num_comps <= 4);
1799 if (!num_comps || num_comps > 4)
1800 continue;
1801
1802 if (reg >= noutput)
1803 continue;
1804
1805 /* Load the output as int. */
1806 for (j = 0; j < num_comps; j++) {
1807 out[j] = LLVMBuildBitCast(builder,
1808 outputs[reg].values[start+j],
1809 ctx->i32, "");
1810 }
1811
1812 /* Pack the output. */
1813 LLVMValueRef vdata = NULL;
1814
1815 switch (num_comps) {
1816 case 1: /* as i32 */
1817 vdata = out[0];
1818 break;
1819 case 2: /* as v2i32 */
1820 case 3: /* as v4i32 (aligned to 4) */
1821 case 4: /* as v4i32 */
1822 vdata = LLVMGetUndef(LLVMVectorType(ctx->i32, util_next_power_of_two(num_comps)));
1823 for (j = 0; j < num_comps; j++) {
1824 vdata = LLVMBuildInsertElement(builder, vdata, out[j],
1825 LLVMConstInt(ctx->i32, j, 0), "");
1826 }
1827 break;
1828 }
1829
1830 LLVMValueRef can_emit_stream =
1831 LLVMBuildICmp(builder, LLVMIntEQ,
1832 stream_id,
1833 lp_build_const_int32(gallivm, stream), "");
1834
1835 lp_build_if(&if_ctx_stream, gallivm, can_emit_stream);
1836 build_tbuffer_store_dwords(ctx, ctx->so_buffers[buf_idx],
1837 vdata, num_comps,
1838 so_write_offset[buf_idx],
1839 LLVMConstInt(ctx->i32, 0, 0),
1840 so->output[i].dst_offset*4);
1841 lp_build_endif(&if_ctx_stream);
1842 }
1843 }
1844 lp_build_endif(&if_ctx);
1845 }
1846
1847
1848 /* Generate export instructions for hardware VS shader stage */
1849 static void si_llvm_export_vs(struct lp_build_tgsi_context *bld_base,
1850 struct si_shader_output_values *outputs,
1851 unsigned noutput)
1852 {
1853 struct si_shader_context *ctx = si_shader_context(bld_base);
1854 struct si_shader *shader = ctx->shader;
1855 struct lp_build_context *base = &bld_base->base;
1856 struct lp_build_context *uint =
1857 &ctx->radeon_bld.soa.bld_base.uint_bld;
1858 LLVMValueRef args[9];
1859 LLVMValueRef pos_args[4][9] = { { 0 } };
1860 LLVMValueRef psize_value = NULL, edgeflag_value = NULL, layer_value = NULL, viewport_index_value = NULL;
1861 unsigned semantic_name, semantic_index;
1862 unsigned target;
1863 unsigned param_count = 0;
1864 unsigned pos_idx;
1865 int i;
1866
1867 if (outputs && ctx->shader->selector->so.num_outputs) {
1868 si_llvm_emit_streamout(ctx, outputs, noutput);
1869 }
1870
1871 for (i = 0; i < noutput; i++) {
1872 semantic_name = outputs[i].name;
1873 semantic_index = outputs[i].sid;
1874
1875 handle_semantic:
1876 /* Select the correct target */
1877 switch(semantic_name) {
1878 case TGSI_SEMANTIC_PSIZE:
1879 psize_value = outputs[i].values[0];
1880 continue;
1881 case TGSI_SEMANTIC_EDGEFLAG:
1882 edgeflag_value = outputs[i].values[0];
1883 continue;
1884 case TGSI_SEMANTIC_LAYER:
1885 layer_value = outputs[i].values[0];
1886 semantic_name = TGSI_SEMANTIC_GENERIC;
1887 goto handle_semantic;
1888 case TGSI_SEMANTIC_VIEWPORT_INDEX:
1889 viewport_index_value = outputs[i].values[0];
1890 semantic_name = TGSI_SEMANTIC_GENERIC;
1891 goto handle_semantic;
1892 case TGSI_SEMANTIC_POSITION:
1893 target = V_008DFC_SQ_EXP_POS;
1894 break;
1895 case TGSI_SEMANTIC_COLOR:
1896 case TGSI_SEMANTIC_BCOLOR:
1897 target = V_008DFC_SQ_EXP_PARAM + param_count;
1898 assert(i < ARRAY_SIZE(shader->info.vs_output_param_offset));
1899 shader->info.vs_output_param_offset[i] = param_count;
1900 param_count++;
1901 break;
1902 case TGSI_SEMANTIC_CLIPDIST:
1903 target = V_008DFC_SQ_EXP_POS + 2 + semantic_index;
1904 break;
1905 case TGSI_SEMANTIC_CLIPVERTEX:
1906 si_llvm_emit_clipvertex(bld_base, pos_args, outputs[i].values);
1907 continue;
1908 case TGSI_SEMANTIC_PRIMID:
1909 case TGSI_SEMANTIC_FOG:
1910 case TGSI_SEMANTIC_TEXCOORD:
1911 case TGSI_SEMANTIC_GENERIC:
1912 target = V_008DFC_SQ_EXP_PARAM + param_count;
1913 assert(i < ARRAY_SIZE(shader->info.vs_output_param_offset));
1914 shader->info.vs_output_param_offset[i] = param_count;
1915 param_count++;
1916 break;
1917 default:
1918 target = 0;
1919 fprintf(stderr,
1920 "Warning: SI unhandled vs output type:%d\n",
1921 semantic_name);
1922 }
1923
1924 si_llvm_init_export_args(bld_base, outputs[i].values, target, args);
1925
1926 if (target >= V_008DFC_SQ_EXP_POS &&
1927 target <= (V_008DFC_SQ_EXP_POS + 3)) {
1928 memcpy(pos_args[target - V_008DFC_SQ_EXP_POS],
1929 args, sizeof(args));
1930 } else {
1931 lp_build_intrinsic(base->gallivm->builder,
1932 "llvm.SI.export", ctx->voidt,
1933 args, 9, 0);
1934 }
1935
1936 if (semantic_name == TGSI_SEMANTIC_CLIPDIST) {
1937 semantic_name = TGSI_SEMANTIC_GENERIC;
1938 goto handle_semantic;
1939 }
1940 }
1941
1942 shader->info.nr_param_exports = param_count;
1943
1944 /* We need to add the position output manually if it's missing. */
1945 if (!pos_args[0][0]) {
1946 pos_args[0][0] = lp_build_const_int32(base->gallivm, 0xf); /* writemask */
1947 pos_args[0][1] = uint->zero; /* EXEC mask */
1948 pos_args[0][2] = uint->zero; /* last export? */
1949 pos_args[0][3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_POS);
1950 pos_args[0][4] = uint->zero; /* COMPR flag */
1951 pos_args[0][5] = base->zero; /* X */
1952 pos_args[0][6] = base->zero; /* Y */
1953 pos_args[0][7] = base->zero; /* Z */
1954 pos_args[0][8] = base->one; /* W */
1955 }
1956
1957 /* Write the misc vector (point size, edgeflag, layer, viewport). */
1958 if (shader->selector->info.writes_psize ||
1959 shader->selector->info.writes_edgeflag ||
1960 shader->selector->info.writes_viewport_index ||
1961 shader->selector->info.writes_layer) {
1962 pos_args[1][0] = lp_build_const_int32(base->gallivm, /* writemask */
1963 shader->selector->info.writes_psize |
1964 (shader->selector->info.writes_edgeflag << 1) |
1965 (shader->selector->info.writes_layer << 2) |
1966 (shader->selector->info.writes_viewport_index << 3));
1967 pos_args[1][1] = uint->zero; /* EXEC mask */
1968 pos_args[1][2] = uint->zero; /* last export? */
1969 pos_args[1][3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_POS + 1);
1970 pos_args[1][4] = uint->zero; /* COMPR flag */
1971 pos_args[1][5] = base->zero; /* X */
1972 pos_args[1][6] = base->zero; /* Y */
1973 pos_args[1][7] = base->zero; /* Z */
1974 pos_args[1][8] = base->zero; /* W */
1975
1976 if (shader->selector->info.writes_psize)
1977 pos_args[1][5] = psize_value;
1978
1979 if (shader->selector->info.writes_edgeflag) {
1980 /* The output is a float, but the hw expects an integer
1981 * with the first bit containing the edge flag. */
1982 edgeflag_value = LLVMBuildFPToUI(base->gallivm->builder,
1983 edgeflag_value,
1984 ctx->i32, "");
1985 edgeflag_value = lp_build_min(&bld_base->int_bld,
1986 edgeflag_value,
1987 bld_base->int_bld.one);
1988
1989 /* The LLVM intrinsic expects a float. */
1990 pos_args[1][6] = LLVMBuildBitCast(base->gallivm->builder,
1991 edgeflag_value,
1992 ctx->f32, "");
1993 }
1994
1995 if (shader->selector->info.writes_layer)
1996 pos_args[1][7] = layer_value;
1997
1998 if (shader->selector->info.writes_viewport_index)
1999 pos_args[1][8] = viewport_index_value;
2000 }
2001
2002 for (i = 0; i < 4; i++)
2003 if (pos_args[i][0])
2004 shader->info.nr_pos_exports++;
2005
2006 pos_idx = 0;
2007 for (i = 0; i < 4; i++) {
2008 if (!pos_args[i][0])
2009 continue;
2010
2011 /* Specify the target we are exporting */
2012 pos_args[i][3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_POS + pos_idx++);
2013
2014 if (pos_idx == shader->info.nr_pos_exports)
2015 /* Specify that this is the last export */
2016 pos_args[i][2] = uint->one;
2017
2018 lp_build_intrinsic(base->gallivm->builder, "llvm.SI.export",
2019 ctx->voidt, pos_args[i], 9, 0);
2020 }
2021 }
2022
2023 static void si_write_tess_factors(struct lp_build_tgsi_context *bld_base,
2024 LLVMValueRef rel_patch_id,
2025 LLVMValueRef invocation_id,
2026 LLVMValueRef tcs_out_current_patch_data_offset)
2027 {
2028 struct si_shader_context *ctx = si_shader_context(bld_base);
2029 struct gallivm_state *gallivm = bld_base->base.gallivm;
2030 struct si_shader *shader = ctx->shader;
2031 unsigned tess_inner_index, tess_outer_index;
2032 LLVMValueRef lds_base, lds_inner, lds_outer, byteoffset, buffer;
2033 LLVMValueRef out[6], vec0, vec1, rw_buffers, tf_base;
2034 unsigned stride, outer_comps, inner_comps, i;
2035 struct lp_build_if_state if_ctx;
2036
2037 /* Do this only for invocation 0, because the tess levels are per-patch,
2038 * not per-vertex.
2039 *
2040 * This can't jump, because invocation 0 executes this. It should
2041 * at least mask out the loads and stores for other invocations.
2042 */
2043 lp_build_if(&if_ctx, gallivm,
2044 LLVMBuildICmp(gallivm->builder, LLVMIntEQ,
2045 invocation_id, bld_base->uint_bld.zero, ""));
2046
2047 /* Determine the layout of one tess factor element in the buffer. */
2048 switch (shader->key.tcs.epilog.prim_mode) {
2049 case PIPE_PRIM_LINES:
2050 stride = 2; /* 2 dwords, 1 vec2 store */
2051 outer_comps = 2;
2052 inner_comps = 0;
2053 break;
2054 case PIPE_PRIM_TRIANGLES:
2055 stride = 4; /* 4 dwords, 1 vec4 store */
2056 outer_comps = 3;
2057 inner_comps = 1;
2058 break;
2059 case PIPE_PRIM_QUADS:
2060 stride = 6; /* 6 dwords, 2 stores (vec4 + vec2) */
2061 outer_comps = 4;
2062 inner_comps = 2;
2063 break;
2064 default:
2065 assert(0);
2066 return;
2067 }
2068
2069 /* Load tess_inner and tess_outer from LDS.
2070 * Any invocation can write them, so we can't get them from a temporary.
2071 */
2072 tess_inner_index = si_shader_io_get_unique_index(TGSI_SEMANTIC_TESSINNER, 0);
2073 tess_outer_index = si_shader_io_get_unique_index(TGSI_SEMANTIC_TESSOUTER, 0);
2074
2075 lds_base = tcs_out_current_patch_data_offset;
2076 lds_inner = LLVMBuildAdd(gallivm->builder, lds_base,
2077 lp_build_const_int32(gallivm,
2078 tess_inner_index * 4), "");
2079 lds_outer = LLVMBuildAdd(gallivm->builder, lds_base,
2080 lp_build_const_int32(gallivm,
2081 tess_outer_index * 4), "");
2082
2083 for (i = 0; i < outer_comps; i++)
2084 out[i] = lds_load(bld_base, TGSI_TYPE_SIGNED, i, lds_outer);
2085 for (i = 0; i < inner_comps; i++)
2086 out[outer_comps+i] = lds_load(bld_base, TGSI_TYPE_SIGNED, i, lds_inner);
2087
2088 /* Convert the outputs to vectors for stores. */
2089 vec0 = lp_build_gather_values(gallivm, out, MIN2(stride, 4));
2090 vec1 = NULL;
2091
2092 if (stride > 4)
2093 vec1 = lp_build_gather_values(gallivm, out+4, stride - 4);
2094
2095 /* Get the buffer. */
2096 rw_buffers = LLVMGetParam(ctx->radeon_bld.main_fn,
2097 SI_PARAM_RW_BUFFERS);
2098 buffer = build_indexed_load_const(ctx, rw_buffers,
2099 lp_build_const_int32(gallivm, SI_RING_TESS_FACTOR));
2100
2101 /* Get the offset. */
2102 tf_base = LLVMGetParam(ctx->radeon_bld.main_fn,
2103 SI_PARAM_TESS_FACTOR_OFFSET);
2104 byteoffset = LLVMBuildMul(gallivm->builder, rel_patch_id,
2105 lp_build_const_int32(gallivm, 4 * stride), "");
2106
2107 /* Store the outputs. */
2108 build_tbuffer_store_dwords(ctx, buffer, vec0,
2109 MIN2(stride, 4), byteoffset, tf_base, 0);
2110 if (vec1)
2111 build_tbuffer_store_dwords(ctx, buffer, vec1,
2112 stride - 4, byteoffset, tf_base, 16);
2113 lp_build_endif(&if_ctx);
2114 }
2115
2116 /* This only writes the tessellation factor levels. */
2117 static void si_llvm_emit_tcs_epilogue(struct lp_build_tgsi_context *bld_base)
2118 {
2119 struct si_shader_context *ctx = si_shader_context(bld_base);
2120 LLVMValueRef rel_patch_id, invocation_id, tf_lds_offset;
2121
2122 rel_patch_id = get_rel_patch_id(ctx);
2123 invocation_id = unpack_param(ctx, SI_PARAM_REL_IDS, 8, 5);
2124 tf_lds_offset = get_tcs_out_current_patch_data_offset(ctx);
2125
2126 if (!ctx->is_monolithic) {
2127 /* Return epilog parameters from this function. */
2128 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
2129 LLVMValueRef ret = ctx->return_value;
2130 LLVMValueRef rw_buffers, rw0, rw1, tf_soffset;
2131 unsigned vgpr;
2132
2133 /* RW_BUFFERS pointer */
2134 rw_buffers = LLVMGetParam(ctx->radeon_bld.main_fn,
2135 SI_PARAM_RW_BUFFERS);
2136 rw_buffers = LLVMBuildPtrToInt(builder, rw_buffers, ctx->i64, "");
2137 rw_buffers = LLVMBuildBitCast(builder, rw_buffers, ctx->v2i32, "");
2138 rw0 = LLVMBuildExtractElement(builder, rw_buffers,
2139 bld_base->uint_bld.zero, "");
2140 rw1 = LLVMBuildExtractElement(builder, rw_buffers,
2141 bld_base->uint_bld.one, "");
2142 ret = LLVMBuildInsertValue(builder, ret, rw0, 0, "");
2143 ret = LLVMBuildInsertValue(builder, ret, rw1, 1, "");
2144
2145 /* Tess factor buffer soffset is after user SGPRs. */
2146 tf_soffset = LLVMGetParam(ctx->radeon_bld.main_fn,
2147 SI_PARAM_TESS_FACTOR_OFFSET);
2148 ret = LLVMBuildInsertValue(builder, ret, tf_soffset,
2149 SI_TCS_NUM_USER_SGPR, "");
2150
2151 /* VGPRs */
2152 rel_patch_id = bitcast(bld_base, TGSI_TYPE_FLOAT, rel_patch_id);
2153 invocation_id = bitcast(bld_base, TGSI_TYPE_FLOAT, invocation_id);
2154 tf_lds_offset = bitcast(bld_base, TGSI_TYPE_FLOAT, tf_lds_offset);
2155
2156 vgpr = SI_TCS_NUM_USER_SGPR + 1;
2157 ret = LLVMBuildInsertValue(builder, ret, rel_patch_id, vgpr++, "");
2158 ret = LLVMBuildInsertValue(builder, ret, invocation_id, vgpr++, "");
2159 ret = LLVMBuildInsertValue(builder, ret, tf_lds_offset, vgpr++, "");
2160 ctx->return_value = ret;
2161 return;
2162 }
2163
2164 si_write_tess_factors(bld_base, rel_patch_id, invocation_id, tf_lds_offset);
2165 }
2166
2167 static void si_llvm_emit_ls_epilogue(struct lp_build_tgsi_context *bld_base)
2168 {
2169 struct si_shader_context *ctx = si_shader_context(bld_base);
2170 struct si_shader *shader = ctx->shader;
2171 struct tgsi_shader_info *info = &shader->selector->info;
2172 struct gallivm_state *gallivm = bld_base->base.gallivm;
2173 unsigned i, chan;
2174 LLVMValueRef vertex_id = LLVMGetParam(ctx->radeon_bld.main_fn,
2175 ctx->param_rel_auto_id);
2176 LLVMValueRef vertex_dw_stride =
2177 unpack_param(ctx, SI_PARAM_LS_OUT_LAYOUT, 13, 8);
2178 LLVMValueRef base_dw_addr = LLVMBuildMul(gallivm->builder, vertex_id,
2179 vertex_dw_stride, "");
2180
2181 /* Write outputs to LDS. The next shader (TCS aka HS) will read
2182 * its inputs from it. */
2183 for (i = 0; i < info->num_outputs; i++) {
2184 LLVMValueRef *out_ptr = ctx->radeon_bld.soa.outputs[i];
2185 unsigned name = info->output_semantic_name[i];
2186 unsigned index = info->output_semantic_index[i];
2187 int param = si_shader_io_get_unique_index(name, index);
2188 LLVMValueRef dw_addr = LLVMBuildAdd(gallivm->builder, base_dw_addr,
2189 lp_build_const_int32(gallivm, param * 4), "");
2190
2191 for (chan = 0; chan < 4; chan++) {
2192 lds_store(bld_base, chan, dw_addr,
2193 LLVMBuildLoad(gallivm->builder, out_ptr[chan], ""));
2194 }
2195 }
2196 }
2197
2198 static void si_llvm_emit_es_epilogue(struct lp_build_tgsi_context *bld_base)
2199 {
2200 struct si_shader_context *ctx = si_shader_context(bld_base);
2201 struct gallivm_state *gallivm = bld_base->base.gallivm;
2202 struct si_shader *es = ctx->shader;
2203 struct tgsi_shader_info *info = &es->selector->info;
2204 LLVMValueRef soffset = LLVMGetParam(ctx->radeon_bld.main_fn,
2205 ctx->param_es2gs_offset);
2206 unsigned chan;
2207 int i;
2208
2209 for (i = 0; i < info->num_outputs; i++) {
2210 LLVMValueRef *out_ptr =
2211 ctx->radeon_bld.soa.outputs[i];
2212 int param_index;
2213
2214 if (info->output_semantic_name[i] == TGSI_SEMANTIC_VIEWPORT_INDEX ||
2215 info->output_semantic_name[i] == TGSI_SEMANTIC_LAYER)
2216 continue;
2217
2218 param_index = si_shader_io_get_unique_index(info->output_semantic_name[i],
2219 info->output_semantic_index[i]);
2220
2221 for (chan = 0; chan < 4; chan++) {
2222 LLVMValueRef out_val = LLVMBuildLoad(gallivm->builder, out_ptr[chan], "");
2223 out_val = LLVMBuildBitCast(gallivm->builder, out_val, ctx->i32, "");
2224
2225 build_tbuffer_store(ctx,
2226 ctx->esgs_ring,
2227 out_val, 1,
2228 LLVMGetUndef(ctx->i32), soffset,
2229 (4 * param_index + chan) * 4,
2230 V_008F0C_BUF_DATA_FORMAT_32,
2231 V_008F0C_BUF_NUM_FORMAT_UINT,
2232 0, 0, 1, 1, 0);
2233 }
2234 }
2235 }
2236
2237 static void si_llvm_emit_gs_epilogue(struct lp_build_tgsi_context *bld_base)
2238 {
2239 struct si_shader_context *ctx = si_shader_context(bld_base);
2240 struct gallivm_state *gallivm = bld_base->base.gallivm;
2241 LLVMValueRef args[2];
2242
2243 args[0] = lp_build_const_int32(gallivm, SENDMSG_GS_OP_NOP | SENDMSG_GS_DONE);
2244 args[1] = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_GS_WAVE_ID);
2245 lp_build_intrinsic(gallivm->builder, "llvm.SI.sendmsg",
2246 ctx->voidt, args, 2, LLVMNoUnwindAttribute);
2247 }
2248
2249 static void si_llvm_emit_vs_epilogue(struct lp_build_tgsi_context *bld_base)
2250 {
2251 struct si_shader_context *ctx = si_shader_context(bld_base);
2252 struct gallivm_state *gallivm = bld_base->base.gallivm;
2253 struct tgsi_shader_info *info = &ctx->shader->selector->info;
2254 struct si_shader_output_values *outputs = NULL;
2255 int i,j;
2256
2257 assert(!ctx->is_gs_copy_shader);
2258
2259 outputs = MALLOC((info->num_outputs + 1) * sizeof(outputs[0]));
2260
2261 /* Vertex color clamping.
2262 *
2263 * This uses a state constant loaded in a user data SGPR and
2264 * an IF statement is added that clamps all colors if the constant
2265 * is true.
2266 */
2267 if (ctx->type == TGSI_PROCESSOR_VERTEX) {
2268 struct lp_build_if_state if_ctx;
2269 LLVMValueRef cond = NULL;
2270 LLVMValueRef addr, val;
2271
2272 for (i = 0; i < info->num_outputs; i++) {
2273 if (info->output_semantic_name[i] != TGSI_SEMANTIC_COLOR &&
2274 info->output_semantic_name[i] != TGSI_SEMANTIC_BCOLOR)
2275 continue;
2276
2277 /* We've found a color. */
2278 if (!cond) {
2279 /* The state is in the first bit of the user SGPR. */
2280 cond = LLVMGetParam(ctx->radeon_bld.main_fn,
2281 SI_PARAM_VS_STATE_BITS);
2282 cond = LLVMBuildTrunc(gallivm->builder, cond,
2283 ctx->i1, "");
2284 lp_build_if(&if_ctx, gallivm, cond);
2285 }
2286
2287 for (j = 0; j < 4; j++) {
2288 addr = ctx->radeon_bld.soa.outputs[i][j];
2289 val = LLVMBuildLoad(gallivm->builder, addr, "");
2290 val = radeon_llvm_saturate(bld_base, val);
2291 LLVMBuildStore(gallivm->builder, val, addr);
2292 }
2293 }
2294
2295 if (cond)
2296 lp_build_endif(&if_ctx);
2297 }
2298
2299 for (i = 0; i < info->num_outputs; i++) {
2300 outputs[i].name = info->output_semantic_name[i];
2301 outputs[i].sid = info->output_semantic_index[i];
2302
2303 for (j = 0; j < 4; j++)
2304 outputs[i].values[j] =
2305 LLVMBuildLoad(gallivm->builder,
2306 ctx->radeon_bld.soa.outputs[i][j],
2307 "");
2308 }
2309
2310 if (ctx->is_monolithic) {
2311 /* Export PrimitiveID when PS needs it. */
2312 if (si_vs_exports_prim_id(ctx->shader)) {
2313 outputs[i].name = TGSI_SEMANTIC_PRIMID;
2314 outputs[i].sid = 0;
2315 outputs[i].values[0] = bitcast(bld_base, TGSI_TYPE_FLOAT,
2316 get_primitive_id(bld_base, 0));
2317 outputs[i].values[1] = bld_base->base.undef;
2318 outputs[i].values[2] = bld_base->base.undef;
2319 outputs[i].values[3] = bld_base->base.undef;
2320 i++;
2321 }
2322 } else {
2323 /* Return the primitive ID from the LLVM function. */
2324 ctx->return_value =
2325 LLVMBuildInsertValue(gallivm->builder,
2326 ctx->return_value,
2327 bitcast(bld_base, TGSI_TYPE_FLOAT,
2328 get_primitive_id(bld_base, 0)),
2329 VS_EPILOG_PRIMID_LOC, "");
2330 }
2331
2332 si_llvm_export_vs(bld_base, outputs, i);
2333 FREE(outputs);
2334 }
2335
2336 static void si_export_mrt_z(struct lp_build_tgsi_context *bld_base,
2337 LLVMValueRef depth, LLVMValueRef stencil,
2338 LLVMValueRef samplemask)
2339 {
2340 struct si_shader_context *ctx = si_shader_context(bld_base);
2341 struct lp_build_context *base = &bld_base->base;
2342 struct lp_build_context *uint = &bld_base->uint_bld;
2343 LLVMValueRef args[9];
2344 unsigned mask = 0;
2345
2346 assert(depth || stencil || samplemask);
2347
2348 args[1] = uint->one; /* whether the EXEC mask is valid */
2349 args[2] = uint->one; /* DONE bit */
2350
2351 /* Specify the target we are exporting */
2352 args[3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_MRTZ);
2353
2354 args[4] = uint->zero; /* COMP flag */
2355 args[5] = base->undef; /* R, depth */
2356 args[6] = base->undef; /* G, stencil test value[0:7], stencil op value[8:15] */
2357 args[7] = base->undef; /* B, sample mask */
2358 args[8] = base->undef; /* A, alpha to mask */
2359
2360 if (depth) {
2361 args[5] = depth;
2362 mask |= 0x1;
2363 }
2364
2365 if (stencil) {
2366 args[6] = stencil;
2367 mask |= 0x2;
2368 }
2369
2370 if (samplemask) {
2371 args[7] = samplemask;
2372 mask |= 0x4;
2373 }
2374
2375 /* SI (except OLAND) has a bug that it only looks
2376 * at the X writemask component. */
2377 if (ctx->screen->b.chip_class == SI &&
2378 ctx->screen->b.family != CHIP_OLAND)
2379 mask |= 0x1;
2380
2381 /* Specify which components to enable */
2382 args[0] = lp_build_const_int32(base->gallivm, mask);
2383
2384 lp_build_intrinsic(base->gallivm->builder, "llvm.SI.export",
2385 ctx->voidt, args, 9, 0);
2386 }
2387
2388 static void si_export_mrt_color(struct lp_build_tgsi_context *bld_base,
2389 LLVMValueRef *color, unsigned index,
2390 unsigned samplemask_param,
2391 bool is_last)
2392 {
2393 struct si_shader_context *ctx = si_shader_context(bld_base);
2394 struct lp_build_context *base = &bld_base->base;
2395 int i;
2396
2397 /* Clamp color */
2398 if (ctx->shader->key.ps.epilog.clamp_color)
2399 for (i = 0; i < 4; i++)
2400 color[i] = radeon_llvm_saturate(bld_base, color[i]);
2401
2402 /* Alpha to one */
2403 if (ctx->shader->key.ps.epilog.alpha_to_one)
2404 color[3] = base->one;
2405
2406 /* Alpha test */
2407 if (index == 0 &&
2408 ctx->shader->key.ps.epilog.alpha_func != PIPE_FUNC_ALWAYS)
2409 si_alpha_test(bld_base, color[3]);
2410
2411 /* Line & polygon smoothing */
2412 if (ctx->shader->key.ps.epilog.poly_line_smoothing)
2413 color[3] = si_scale_alpha_by_sample_mask(bld_base, color[3],
2414 samplemask_param);
2415
2416 /* If last_cbuf > 0, FS_COLOR0_WRITES_ALL_CBUFS is true. */
2417 if (ctx->shader->key.ps.epilog.last_cbuf > 0) {
2418 LLVMValueRef args[8][9];
2419 int c, last = -1;
2420
2421 /* Get the export arguments, also find out what the last one is. */
2422 for (c = 0; c <= ctx->shader->key.ps.epilog.last_cbuf; c++) {
2423 si_llvm_init_export_args(bld_base, color,
2424 V_008DFC_SQ_EXP_MRT + c, args[c]);
2425 if (args[c][0] != bld_base->uint_bld.zero)
2426 last = c;
2427 }
2428
2429 /* Emit all exports. */
2430 for (c = 0; c <= ctx->shader->key.ps.epilog.last_cbuf; c++) {
2431 if (is_last && last == c) {
2432 args[c][1] = bld_base->uint_bld.one; /* whether the EXEC mask is valid */
2433 args[c][2] = bld_base->uint_bld.one; /* DONE bit */
2434 } else if (args[c][0] == bld_base->uint_bld.zero)
2435 continue; /* unnecessary NULL export */
2436
2437 lp_build_intrinsic(base->gallivm->builder, "llvm.SI.export",
2438 ctx->voidt, args[c], 9, 0);
2439 }
2440 } else {
2441 LLVMValueRef args[9];
2442
2443 /* Export */
2444 si_llvm_init_export_args(bld_base, color, V_008DFC_SQ_EXP_MRT + index,
2445 args);
2446 if (is_last) {
2447 args[1] = bld_base->uint_bld.one; /* whether the EXEC mask is valid */
2448 args[2] = bld_base->uint_bld.one; /* DONE bit */
2449 } else if (args[0] == bld_base->uint_bld.zero)
2450 return; /* unnecessary NULL export */
2451
2452 lp_build_intrinsic(base->gallivm->builder, "llvm.SI.export",
2453 ctx->voidt, args, 9, 0);
2454 }
2455 }
2456
2457 static void si_export_null(struct lp_build_tgsi_context *bld_base)
2458 {
2459 struct si_shader_context *ctx = si_shader_context(bld_base);
2460 struct lp_build_context *base = &bld_base->base;
2461 struct lp_build_context *uint = &bld_base->uint_bld;
2462 LLVMValueRef args[9];
2463
2464 args[0] = lp_build_const_int32(base->gallivm, 0x0); /* enabled channels */
2465 args[1] = uint->one; /* whether the EXEC mask is valid */
2466 args[2] = uint->one; /* DONE bit */
2467 args[3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_NULL);
2468 args[4] = uint->zero; /* COMPR flag (0 = 32-bit export) */
2469 args[5] = uint->undef; /* R */
2470 args[6] = uint->undef; /* G */
2471 args[7] = uint->undef; /* B */
2472 args[8] = uint->undef; /* A */
2473
2474 lp_build_intrinsic(base->gallivm->builder, "llvm.SI.export",
2475 ctx->voidt, args, 9, 0);
2476 }
2477
2478 static void si_llvm_emit_fs_epilogue(struct lp_build_tgsi_context *bld_base)
2479 {
2480 struct si_shader_context *ctx = si_shader_context(bld_base);
2481 struct si_shader *shader = ctx->shader;
2482 struct lp_build_context *base = &bld_base->base;
2483 struct tgsi_shader_info *info = &shader->selector->info;
2484 LLVMBuilderRef builder = base->gallivm->builder;
2485 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
2486 int last_color_export = -1;
2487 int i;
2488
2489 /* Determine the last export. If MRTZ is present, it's always last.
2490 * Otherwise, find the last color export.
2491 */
2492 if (!info->writes_z && !info->writes_stencil && !info->writes_samplemask) {
2493 unsigned spi_format = shader->key.ps.epilog.spi_shader_col_format;
2494
2495 /* Don't export NULL and return if alpha-test is enabled. */
2496 if (shader->key.ps.epilog.alpha_func != PIPE_FUNC_ALWAYS &&
2497 shader->key.ps.epilog.alpha_func != PIPE_FUNC_NEVER &&
2498 (spi_format & 0xf) == 0)
2499 spi_format |= V_028714_SPI_SHADER_32_AR;
2500
2501 for (i = 0; i < info->num_outputs; i++) {
2502 unsigned index = info->output_semantic_index[i];
2503
2504 if (info->output_semantic_name[i] != TGSI_SEMANTIC_COLOR)
2505 continue;
2506
2507 /* If last_cbuf > 0, FS_COLOR0_WRITES_ALL_CBUFS is true. */
2508 if (shader->key.ps.epilog.last_cbuf > 0) {
2509 /* Just set this if any of the colorbuffers are enabled. */
2510 if (spi_format &
2511 ((1llu << (4 * (shader->key.ps.epilog.last_cbuf + 1))) - 1))
2512 last_color_export = i;
2513 continue;
2514 }
2515
2516 if ((spi_format >> (index * 4)) & 0xf)
2517 last_color_export = i;
2518 }
2519
2520 /* If there are no outputs, export NULL. */
2521 if (last_color_export == -1) {
2522 si_export_null(bld_base);
2523 return;
2524 }
2525 }
2526
2527 for (i = 0; i < info->num_outputs; i++) {
2528 unsigned semantic_name = info->output_semantic_name[i];
2529 unsigned semantic_index = info->output_semantic_index[i];
2530 unsigned j;
2531 LLVMValueRef color[4] = {};
2532
2533 /* Select the correct target */
2534 switch (semantic_name) {
2535 case TGSI_SEMANTIC_POSITION:
2536 depth = LLVMBuildLoad(builder,
2537 ctx->radeon_bld.soa.outputs[i][2], "");
2538 break;
2539 case TGSI_SEMANTIC_STENCIL:
2540 stencil = LLVMBuildLoad(builder,
2541 ctx->radeon_bld.soa.outputs[i][1], "");
2542 break;
2543 case TGSI_SEMANTIC_SAMPLEMASK:
2544 samplemask = LLVMBuildLoad(builder,
2545 ctx->radeon_bld.soa.outputs[i][0], "");
2546 break;
2547 case TGSI_SEMANTIC_COLOR:
2548 for (j = 0; j < 4; j++)
2549 color[j] = LLVMBuildLoad(builder,
2550 ctx->radeon_bld.soa.outputs[i][j], "");
2551
2552 si_export_mrt_color(bld_base, color, semantic_index,
2553 SI_PARAM_SAMPLE_COVERAGE,
2554 last_color_export == i);
2555 break;
2556 default:
2557 fprintf(stderr,
2558 "Warning: SI unhandled fs output type:%d\n",
2559 semantic_name);
2560 }
2561 }
2562
2563 if (depth || stencil || samplemask)
2564 si_export_mrt_z(bld_base, depth, stencil, samplemask);
2565 }
2566
2567 /**
2568 * Return PS outputs in this order:
2569 *
2570 * v[0:3] = color0.xyzw
2571 * v[4:7] = color1.xyzw
2572 * ...
2573 * vN+0 = Depth
2574 * vN+1 = Stencil
2575 * vN+2 = SampleMask
2576 * vN+3 = SampleMaskIn (used for OpenGL smoothing)
2577 *
2578 * The alpha-ref SGPR is returned via its original location.
2579 */
2580 static void si_llvm_return_fs_outputs(struct lp_build_tgsi_context *bld_base)
2581 {
2582 struct si_shader_context *ctx = si_shader_context(bld_base);
2583 struct si_shader *shader = ctx->shader;
2584 struct lp_build_context *base = &bld_base->base;
2585 struct tgsi_shader_info *info = &shader->selector->info;
2586 LLVMBuilderRef builder = base->gallivm->builder;
2587 unsigned i, j, first_vgpr, vgpr;
2588
2589 LLVMValueRef color[8][4] = {};
2590 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
2591 LLVMValueRef ret;
2592
2593 /* Read the output values. */
2594 for (i = 0; i < info->num_outputs; i++) {
2595 unsigned semantic_name = info->output_semantic_name[i];
2596 unsigned semantic_index = info->output_semantic_index[i];
2597
2598 switch (semantic_name) {
2599 case TGSI_SEMANTIC_COLOR:
2600 assert(semantic_index < 8);
2601 for (j = 0; j < 4; j++) {
2602 LLVMValueRef ptr = ctx->radeon_bld.soa.outputs[i][j];
2603 LLVMValueRef result = LLVMBuildLoad(builder, ptr, "");
2604 color[semantic_index][j] = result;
2605 }
2606 break;
2607 case TGSI_SEMANTIC_POSITION:
2608 depth = LLVMBuildLoad(builder,
2609 ctx->radeon_bld.soa.outputs[i][2], "");
2610 break;
2611 case TGSI_SEMANTIC_STENCIL:
2612 stencil = LLVMBuildLoad(builder,
2613 ctx->radeon_bld.soa.outputs[i][1], "");
2614 break;
2615 case TGSI_SEMANTIC_SAMPLEMASK:
2616 samplemask = LLVMBuildLoad(builder,
2617 ctx->radeon_bld.soa.outputs[i][0], "");
2618 break;
2619 default:
2620 fprintf(stderr, "Warning: SI unhandled fs output type:%d\n",
2621 semantic_name);
2622 }
2623 }
2624
2625 /* Fill the return structure. */
2626 ret = ctx->return_value;
2627
2628 /* Set SGPRs. */
2629 ret = LLVMBuildInsertValue(builder, ret,
2630 bitcast(bld_base, TGSI_TYPE_SIGNED,
2631 LLVMGetParam(ctx->radeon_bld.main_fn,
2632 SI_PARAM_ALPHA_REF)),
2633 SI_SGPR_ALPHA_REF, "");
2634
2635 /* Set VGPRs */
2636 first_vgpr = vgpr = SI_SGPR_ALPHA_REF + 1;
2637 for (i = 0; i < ARRAY_SIZE(color); i++) {
2638 if (!color[i][0])
2639 continue;
2640
2641 for (j = 0; j < 4; j++)
2642 ret = LLVMBuildInsertValue(builder, ret, color[i][j], vgpr++, "");
2643 }
2644 if (depth)
2645 ret = LLVMBuildInsertValue(builder, ret, depth, vgpr++, "");
2646 if (stencil)
2647 ret = LLVMBuildInsertValue(builder, ret, stencil, vgpr++, "");
2648 if (samplemask)
2649 ret = LLVMBuildInsertValue(builder, ret, samplemask, vgpr++, "");
2650
2651 /* Add the input sample mask for smoothing at the end. */
2652 if (vgpr < first_vgpr + PS_EPILOG_SAMPLEMASK_MIN_LOC)
2653 vgpr = first_vgpr + PS_EPILOG_SAMPLEMASK_MIN_LOC;
2654 ret = LLVMBuildInsertValue(builder, ret,
2655 LLVMGetParam(ctx->radeon_bld.main_fn,
2656 SI_PARAM_SAMPLE_COVERAGE), vgpr++, "");
2657
2658 ctx->return_value = ret;
2659 }
2660
2661 /**
2662 * Given a v8i32 resource descriptor for a buffer, extract the size of the
2663 * buffer in number of elements and return it as an i32.
2664 */
2665 static LLVMValueRef get_buffer_size(
2666 struct lp_build_tgsi_context *bld_base,
2667 LLVMValueRef descriptor)
2668 {
2669 struct si_shader_context *ctx = si_shader_context(bld_base);
2670 struct gallivm_state *gallivm = bld_base->base.gallivm;
2671 LLVMBuilderRef builder = gallivm->builder;
2672 LLVMValueRef size =
2673 LLVMBuildExtractElement(builder, descriptor,
2674 lp_build_const_int32(gallivm, 6), "");
2675
2676 if (ctx->screen->b.chip_class >= VI) {
2677 /* On VI, the descriptor contains the size in bytes,
2678 * but TXQ must return the size in elements.
2679 * The stride is always non-zero for resources using TXQ.
2680 */
2681 LLVMValueRef stride =
2682 LLVMBuildExtractElement(builder, descriptor,
2683 lp_build_const_int32(gallivm, 5), "");
2684 stride = LLVMBuildLShr(builder, stride,
2685 lp_build_const_int32(gallivm, 16), "");
2686 stride = LLVMBuildAnd(builder, stride,
2687 lp_build_const_int32(gallivm, 0x3FFF), "");
2688
2689 size = LLVMBuildUDiv(builder, size, stride, "");
2690 }
2691
2692 return size;
2693 }
2694
2695 /**
2696 * Given the i32 or vNi32 \p type, generate the textual name (e.g. for use with
2697 * intrinsic names).
2698 */
2699 static void build_int_type_name(
2700 LLVMTypeRef type,
2701 char *buf, unsigned bufsize)
2702 {
2703 assert(bufsize >= 6);
2704
2705 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
2706 snprintf(buf, bufsize, "v%ui32",
2707 LLVMGetVectorSize(type));
2708 else
2709 strcpy(buf, "i32");
2710 }
2711
2712 static void build_tex_intrinsic(const struct lp_build_tgsi_action *action,
2713 struct lp_build_tgsi_context *bld_base,
2714 struct lp_build_emit_data *emit_data);
2715
2716 static bool tgsi_is_array_sampler(unsigned target)
2717 {
2718 return target == TGSI_TEXTURE_1D_ARRAY ||
2719 target == TGSI_TEXTURE_SHADOW1D_ARRAY ||
2720 target == TGSI_TEXTURE_2D_ARRAY ||
2721 target == TGSI_TEXTURE_SHADOW2D_ARRAY ||
2722 target == TGSI_TEXTURE_CUBE_ARRAY ||
2723 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY ||
2724 target == TGSI_TEXTURE_2D_ARRAY_MSAA;
2725 }
2726
2727 static bool tgsi_is_array_image(unsigned target)
2728 {
2729 return target == TGSI_TEXTURE_3D ||
2730 target == TGSI_TEXTURE_CUBE ||
2731 target == TGSI_TEXTURE_1D_ARRAY ||
2732 target == TGSI_TEXTURE_2D_ARRAY ||
2733 target == TGSI_TEXTURE_CUBE_ARRAY ||
2734 target == TGSI_TEXTURE_2D_ARRAY_MSAA;
2735 }
2736
2737 /**
2738 * Load the resource descriptor for \p image.
2739 */
2740 static void
2741 image_fetch_rsrc(
2742 struct lp_build_tgsi_context *bld_base,
2743 const struct tgsi_full_src_register *image,
2744 LLVMValueRef *rsrc)
2745 {
2746 struct si_shader_context *ctx = si_shader_context(bld_base);
2747
2748 assert(image->Register.File == TGSI_FILE_IMAGE);
2749
2750 if (!image->Register.Indirect) {
2751 /* Fast path: use preloaded resources */
2752 *rsrc = ctx->images[image->Register.Index];
2753 } else {
2754 /* Indexing and manual load */
2755 LLVMValueRef ind_index;
2756 LLVMValueRef rsrc_ptr;
2757
2758 ind_index = get_indirect_index(ctx, &image->Indirect, image->Register.Index);
2759
2760 rsrc_ptr = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_IMAGES);
2761 *rsrc = build_indexed_load_const(ctx, rsrc_ptr, ind_index);
2762 }
2763 }
2764
2765 static LLVMValueRef image_fetch_coords(
2766 struct lp_build_tgsi_context *bld_base,
2767 const struct tgsi_full_instruction *inst,
2768 unsigned src)
2769 {
2770 struct gallivm_state *gallivm = bld_base->base.gallivm;
2771 LLVMBuilderRef builder = gallivm->builder;
2772 unsigned target = inst->Memory.Texture;
2773 int sample;
2774 unsigned num_coords = tgsi_util_get_texture_coord_dim(target, &sample);
2775 LLVMValueRef coords[4];
2776 LLVMValueRef tmp;
2777 int chan;
2778
2779 for (chan = 0; chan < num_coords; ++chan) {
2780 tmp = lp_build_emit_fetch(bld_base, inst, src, chan);
2781 tmp = LLVMBuildBitCast(builder, tmp, bld_base->uint_bld.elem_type, "");
2782 coords[chan] = tmp;
2783 }
2784
2785 if (num_coords == 1)
2786 return coords[0];
2787
2788 if (num_coords == 3) {
2789 /* LLVM has difficulties lowering 3-element vectors. */
2790 coords[3] = bld_base->uint_bld.undef;
2791 num_coords = 4;
2792 }
2793
2794 return lp_build_gather_values(gallivm, coords, num_coords);
2795 }
2796
2797 /**
2798 * Append the extra mode bits that are used by image load and store.
2799 */
2800 static void image_append_args(
2801 struct si_shader_context *ctx,
2802 struct lp_build_emit_data * emit_data,
2803 unsigned target,
2804 bool atomic)
2805 {
2806 LLVMValueRef i1false = LLVMConstInt(ctx->i1, 0, 0);
2807 LLVMValueRef i1true = LLVMConstInt(ctx->i1, 1, 0);
2808
2809 emit_data->args[emit_data->arg_count++] = i1false; /* r128 */
2810 emit_data->args[emit_data->arg_count++] =
2811 tgsi_is_array_image(target) ? i1true : i1false; /* da */
2812 if (!atomic)
2813 emit_data->args[emit_data->arg_count++] = i1false; /* glc */
2814 emit_data->args[emit_data->arg_count++] = i1false; /* slc */
2815 }
2816
2817 /**
2818 * Append the resource and indexing arguments for buffer intrinsics.
2819 *
2820 * \param rsrc the 256 bit resource
2821 * \param index index into the buffer
2822 */
2823 static void buffer_append_args(
2824 struct si_shader_context *ctx,
2825 struct lp_build_emit_data *emit_data,
2826 LLVMValueRef rsrc,
2827 LLVMValueRef index,
2828 bool atomic)
2829 {
2830 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
2831 struct lp_build_tgsi_context *bld_base = &ctx->radeon_bld.soa.bld_base;
2832 LLVMTypeRef v2i128 = LLVMVectorType(ctx->i128, 2);
2833 LLVMValueRef i1false = LLVMConstInt(ctx->i1, 0, 0);
2834
2835 rsrc = LLVMBuildBitCast(gallivm->builder, rsrc, v2i128, "");
2836 rsrc = LLVMBuildExtractElement(gallivm->builder, rsrc, bld_base->uint_bld.one, "");
2837 rsrc = LLVMBuildBitCast(gallivm->builder, rsrc, ctx->v4i32, "");
2838
2839 emit_data->args[emit_data->arg_count++] = rsrc;
2840 emit_data->args[emit_data->arg_count++] = index; /* vindex */
2841 emit_data->args[emit_data->arg_count++] = bld_base->uint_bld.zero; /* voffset */
2842 if (!atomic)
2843 emit_data->args[emit_data->arg_count++] = i1false; /* glc */
2844 emit_data->args[emit_data->arg_count++] = i1false; /* slc */
2845 }
2846
2847 static void load_fetch_args(
2848 struct lp_build_tgsi_context * bld_base,
2849 struct lp_build_emit_data * emit_data)
2850 {
2851 struct si_shader_context *ctx = si_shader_context(bld_base);
2852 struct gallivm_state *gallivm = bld_base->base.gallivm;
2853 const struct tgsi_full_instruction * inst = emit_data->inst;
2854 unsigned target = inst->Memory.Texture;
2855 LLVMValueRef coords;
2856 LLVMValueRef rsrc;
2857
2858 emit_data->dst_type = LLVMVectorType(bld_base->base.elem_type, 4);
2859
2860 image_fetch_rsrc(bld_base, &inst->Src[0], &rsrc);
2861 coords = image_fetch_coords(bld_base, inst, 1);
2862
2863 if (target == TGSI_TEXTURE_BUFFER) {
2864 buffer_append_args(ctx, emit_data, rsrc, coords, false);
2865 } else {
2866 emit_data->args[0] = coords;
2867 emit_data->args[1] = rsrc;
2868 emit_data->args[2] = lp_build_const_int32(gallivm, 15); /* dmask */
2869 emit_data->arg_count = 3;
2870
2871 image_append_args(ctx, emit_data, target, false);
2872 }
2873 }
2874
2875 static void load_emit(
2876 const struct lp_build_tgsi_action *action,
2877 struct lp_build_tgsi_context *bld_base,
2878 struct lp_build_emit_data *emit_data)
2879 {
2880 struct gallivm_state *gallivm = bld_base->base.gallivm;
2881 LLVMBuilderRef builder = gallivm->builder;
2882 const struct tgsi_full_instruction * inst = emit_data->inst;
2883 unsigned target = inst->Memory.Texture;
2884 char intrinsic_name[32];
2885 char coords_type[8];
2886
2887 if (target == TGSI_TEXTURE_BUFFER) {
2888 emit_data->output[emit_data->chan] = lp_build_intrinsic(
2889 builder, "llvm.amdgcn.buffer.load.format.v4f32", emit_data->dst_type,
2890 emit_data->args, emit_data->arg_count,
2891 LLVMReadOnlyAttribute | LLVMNoUnwindAttribute);
2892 } else {
2893 build_int_type_name(LLVMTypeOf(emit_data->args[0]),
2894 coords_type, sizeof(coords_type));
2895
2896 snprintf(intrinsic_name, sizeof(intrinsic_name),
2897 "llvm.amdgcn.image.load.%s", coords_type);
2898
2899 emit_data->output[emit_data->chan] =
2900 lp_build_intrinsic(
2901 builder, intrinsic_name, emit_data->dst_type,
2902 emit_data->args, emit_data->arg_count,
2903 LLVMReadOnlyAttribute | LLVMNoUnwindAttribute);
2904 }
2905 }
2906
2907 static void store_fetch_args(
2908 struct lp_build_tgsi_context * bld_base,
2909 struct lp_build_emit_data * emit_data)
2910 {
2911 struct si_shader_context *ctx = si_shader_context(bld_base);
2912 struct gallivm_state *gallivm = bld_base->base.gallivm;
2913 const struct tgsi_full_instruction * inst = emit_data->inst;
2914 struct tgsi_full_src_register image;
2915 unsigned target = inst->Memory.Texture;
2916 LLVMValueRef chans[4];
2917 LLVMValueRef data;
2918 LLVMValueRef coords;
2919 LLVMValueRef rsrc;
2920 unsigned chan;
2921
2922 emit_data->dst_type = LLVMVoidTypeInContext(gallivm->context);
2923
2924 image = tgsi_full_src_register_from_dst(&inst->Dst[0]);
2925 image_fetch_rsrc(bld_base, &image, &rsrc);
2926 coords = image_fetch_coords(bld_base, inst, 0);
2927
2928 for (chan = 0; chan < 4; ++chan) {
2929 chans[chan] = lp_build_emit_fetch(bld_base, inst, 1, chan);
2930 }
2931 data = lp_build_gather_values(gallivm, chans, 4);
2932
2933 if (target == TGSI_TEXTURE_BUFFER) {
2934 emit_data->args[0] = data;
2935 emit_data->arg_count = 1;
2936
2937 buffer_append_args(ctx, emit_data, rsrc, coords, false);
2938 } else {
2939 emit_data->args[0] = data;
2940 emit_data->args[1] = coords;
2941 emit_data->args[2] = rsrc;
2942 emit_data->args[3] = lp_build_const_int32(gallivm, 15); /* dmask */
2943 emit_data->arg_count = 4;
2944
2945 image_append_args(ctx, emit_data, target, false);
2946 }
2947 }
2948
2949 static void store_emit(
2950 const struct lp_build_tgsi_action *action,
2951 struct lp_build_tgsi_context *bld_base,
2952 struct lp_build_emit_data *emit_data)
2953 {
2954 struct gallivm_state *gallivm = bld_base->base.gallivm;
2955 LLVMBuilderRef builder = gallivm->builder;
2956 const struct tgsi_full_instruction * inst = emit_data->inst;
2957 unsigned target = inst->Memory.Texture;
2958 char intrinsic_name[32];
2959 char coords_type[8];
2960
2961 if (target == TGSI_TEXTURE_BUFFER) {
2962 emit_data->output[emit_data->chan] = lp_build_intrinsic(
2963 builder, "llvm.amdgcn.buffer.store.format.v4f32",
2964 emit_data->dst_type, emit_data->args, emit_data->arg_count,
2965 LLVMNoUnwindAttribute);
2966 } else {
2967 build_int_type_name(LLVMTypeOf(emit_data->args[1]),
2968 coords_type, sizeof(coords_type));
2969 snprintf(intrinsic_name, sizeof(intrinsic_name),
2970 "llvm.amdgcn.image.store.%s", coords_type);
2971
2972 emit_data->output[emit_data->chan] =
2973 lp_build_intrinsic(
2974 builder, intrinsic_name, emit_data->dst_type,
2975 emit_data->args, emit_data->arg_count,
2976 LLVMNoUnwindAttribute);
2977 }
2978 }
2979
2980 static void atomic_fetch_args(
2981 struct lp_build_tgsi_context * bld_base,
2982 struct lp_build_emit_data * emit_data)
2983 {
2984 struct si_shader_context *ctx = si_shader_context(bld_base);
2985 struct gallivm_state *gallivm = bld_base->base.gallivm;
2986 LLVMBuilderRef builder = gallivm->builder;
2987 const struct tgsi_full_instruction * inst = emit_data->inst;
2988 unsigned target = inst->Memory.Texture;
2989 LLVMValueRef data1, data2;
2990 LLVMValueRef coords;
2991 LLVMValueRef rsrc;
2992 LLVMValueRef tmp;
2993
2994 emit_data->dst_type = bld_base->base.elem_type;
2995
2996 image_fetch_rsrc(bld_base, &inst->Src[0], &rsrc);
2997 coords = image_fetch_coords(bld_base, inst, 1);
2998
2999 tmp = lp_build_emit_fetch(bld_base, inst, 2, 0);
3000 data1 = LLVMBuildBitCast(builder, tmp, bld_base->uint_bld.elem_type, "");
3001
3002 if (inst->Instruction.Opcode == TGSI_OPCODE_ATOMCAS) {
3003 tmp = lp_build_emit_fetch(bld_base, inst, 3, 0);
3004 data2 = LLVMBuildBitCast(builder, tmp, bld_base->uint_bld.elem_type, "");
3005 }
3006
3007 /* llvm.amdgcn.image/buffer.atomic.cmpswap reflect the hardware order
3008 * of arguments, which is reversed relative to TGSI (and GLSL)
3009 */
3010 if (inst->Instruction.Opcode == TGSI_OPCODE_ATOMCAS)
3011 emit_data->args[emit_data->arg_count++] = data2;
3012 emit_data->args[emit_data->arg_count++] = data1;
3013
3014 if (target == TGSI_TEXTURE_BUFFER) {
3015 buffer_append_args(ctx, emit_data, rsrc, coords, true);
3016 } else {
3017 emit_data->args[emit_data->arg_count++] = coords;
3018 emit_data->args[emit_data->arg_count++] = rsrc;
3019
3020 image_append_args(ctx, emit_data, target, true);
3021 }
3022 }
3023
3024 static void atomic_emit(
3025 const struct lp_build_tgsi_action *action,
3026 struct lp_build_tgsi_context *bld_base,
3027 struct lp_build_emit_data *emit_data)
3028 {
3029 struct gallivm_state *gallivm = bld_base->base.gallivm;
3030 LLVMBuilderRef builder = gallivm->builder;
3031 const struct tgsi_full_instruction * inst = emit_data->inst;
3032 unsigned target = inst->Memory.Texture;
3033 char intrinsic_name[40];
3034 LLVMValueRef tmp;
3035
3036 if (target == TGSI_TEXTURE_BUFFER) {
3037 snprintf(intrinsic_name, sizeof(intrinsic_name),
3038 "llvm.amdgcn.buffer.atomic.%s", action->intr_name);
3039 } else {
3040 char coords_type[8];
3041
3042 build_int_type_name(LLVMTypeOf(emit_data->args[1]),
3043 coords_type, sizeof(coords_type));
3044 snprintf(intrinsic_name, sizeof(intrinsic_name),
3045 "llvm.amdgcn.image.atomic.%s.%s",
3046 action->intr_name, coords_type);
3047 }
3048
3049 tmp = lp_build_intrinsic(
3050 builder, intrinsic_name, bld_base->uint_bld.elem_type,
3051 emit_data->args, emit_data->arg_count,
3052 LLVMNoUnwindAttribute);
3053 emit_data->output[emit_data->chan] =
3054 LLVMBuildBitCast(builder, tmp, bld_base->base.elem_type, "");
3055 }
3056
3057 static void resq_fetch_args(
3058 struct lp_build_tgsi_context * bld_base,
3059 struct lp_build_emit_data * emit_data)
3060 {
3061 struct gallivm_state *gallivm = bld_base->base.gallivm;
3062 const struct tgsi_full_instruction *inst = emit_data->inst;
3063 const struct tgsi_full_src_register *reg = &inst->Src[0];
3064 unsigned tex_target = inst->Memory.Texture;
3065
3066 emit_data->dst_type = LLVMVectorType(bld_base->base.elem_type, 4);
3067
3068 if (tex_target == TGSI_TEXTURE_BUFFER) {
3069 image_fetch_rsrc(bld_base, reg, &emit_data->args[0]);
3070 emit_data->arg_count = 1;
3071 } else {
3072 emit_data->args[0] = bld_base->uint_bld.zero; /* mip level */
3073 image_fetch_rsrc(bld_base, reg, &emit_data->args[1]);
3074 emit_data->args[2] = lp_build_const_int32(gallivm, 15); /* dmask */
3075 emit_data->args[3] = bld_base->uint_bld.zero; /* unorm */
3076 emit_data->args[4] = bld_base->uint_bld.zero; /* r128 */
3077 emit_data->args[5] = tgsi_is_array_image(tex_target) ?
3078 bld_base->uint_bld.one : bld_base->uint_bld.zero; /* da */
3079 emit_data->args[6] = bld_base->uint_bld.zero; /* glc */
3080 emit_data->args[7] = bld_base->uint_bld.zero; /* slc */
3081 emit_data->args[8] = bld_base->uint_bld.zero; /* tfe */
3082 emit_data->args[9] = bld_base->uint_bld.zero; /* lwe */
3083 emit_data->arg_count = 10;
3084 }
3085 }
3086
3087 static void resq_emit(
3088 const struct lp_build_tgsi_action *action,
3089 struct lp_build_tgsi_context *bld_base,
3090 struct lp_build_emit_data *emit_data)
3091 {
3092 struct gallivm_state *gallivm = bld_base->base.gallivm;
3093 LLVMBuilderRef builder = gallivm->builder;
3094 const struct tgsi_full_instruction *inst = emit_data->inst;
3095 unsigned target = inst->Memory.Texture;
3096 LLVMValueRef out;
3097
3098 if (target == TGSI_TEXTURE_BUFFER) {
3099 out = get_buffer_size(bld_base, emit_data->args[0]);
3100 } else {
3101 out = lp_build_intrinsic(
3102 builder, "llvm.SI.getresinfo.i32", emit_data->dst_type,
3103 emit_data->args, emit_data->arg_count,
3104 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
3105
3106 /* Divide the number of layers by 6 to get the number of cubes. */
3107 if (target == TGSI_TEXTURE_CUBE_ARRAY) {
3108 LLVMValueRef imm2 = lp_build_const_int32(gallivm, 2);
3109 LLVMValueRef imm6 = lp_build_const_int32(gallivm, 6);
3110
3111 LLVMValueRef z = LLVMBuildExtractElement(builder, out, imm2, "");
3112 z = LLVMBuildBitCast(builder, z, bld_base->uint_bld.elem_type, "");
3113 z = LLVMBuildSDiv(builder, z, imm6, "");
3114 z = LLVMBuildBitCast(builder, z, bld_base->base.elem_type, "");
3115 out = LLVMBuildInsertElement(builder, out, z, imm2, "");
3116 }
3117 }
3118
3119 emit_data->output[emit_data->chan] = out;
3120 }
3121
3122 static void set_tex_fetch_args(struct si_shader_context *ctx,
3123 struct lp_build_emit_data *emit_data,
3124 unsigned opcode, unsigned target,
3125 LLVMValueRef res_ptr, LLVMValueRef samp_ptr,
3126 LLVMValueRef *param, unsigned count,
3127 unsigned dmask)
3128 {
3129 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
3130 unsigned num_args;
3131 unsigned is_rect = target == TGSI_TEXTURE_RECT;
3132
3133 /* Pad to power of two vector */
3134 while (count < util_next_power_of_two(count))
3135 param[count++] = LLVMGetUndef(ctx->i32);
3136
3137 /* Texture coordinates. */
3138 if (count > 1)
3139 emit_data->args[0] = lp_build_gather_values(gallivm, param, count);
3140 else
3141 emit_data->args[0] = param[0];
3142
3143 /* Resource. */
3144 emit_data->args[1] = res_ptr;
3145 num_args = 2;
3146
3147 if (opcode == TGSI_OPCODE_TXF || opcode == TGSI_OPCODE_TXQ)
3148 emit_data->dst_type = ctx->v4i32;
3149 else {
3150 emit_data->dst_type = ctx->v4f32;
3151
3152 emit_data->args[num_args++] = samp_ptr;
3153 }
3154
3155 emit_data->args[num_args++] = lp_build_const_int32(gallivm, dmask);
3156 emit_data->args[num_args++] = lp_build_const_int32(gallivm, is_rect); /* unorm */
3157 emit_data->args[num_args++] = lp_build_const_int32(gallivm, 0); /* r128 */
3158 emit_data->args[num_args++] = lp_build_const_int32(gallivm,
3159 tgsi_is_array_sampler(target)); /* da */
3160 emit_data->args[num_args++] = lp_build_const_int32(gallivm, 0); /* glc */
3161 emit_data->args[num_args++] = lp_build_const_int32(gallivm, 0); /* slc */
3162 emit_data->args[num_args++] = lp_build_const_int32(gallivm, 0); /* tfe */
3163 emit_data->args[num_args++] = lp_build_const_int32(gallivm, 0); /* lwe */
3164
3165 emit_data->arg_count = num_args;
3166 }
3167
3168 static const struct lp_build_tgsi_action tex_action;
3169
3170 enum desc_type {
3171 DESC_IMAGE,
3172 DESC_FMASK,
3173 DESC_SAMPLER
3174 };
3175
3176 static LLVMTypeRef const_array(LLVMTypeRef elem_type, int num_elements)
3177 {
3178 return LLVMPointerType(LLVMArrayType(elem_type, num_elements),
3179 CONST_ADDR_SPACE);
3180 }
3181
3182 /**
3183 * Load an image view, fmask view. or sampler state descriptor.
3184 */
3185 static LLVMValueRef get_sampler_desc_custom(struct si_shader_context *ctx,
3186 LLVMValueRef list, LLVMValueRef index,
3187 enum desc_type type)
3188 {
3189 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
3190 LLVMBuilderRef builder = gallivm->builder;
3191
3192 switch (type) {
3193 case DESC_IMAGE:
3194 /* The image is at [0:7]. */
3195 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->i32, 2, 0), "");
3196 break;
3197 case DESC_FMASK:
3198 /* The FMASK is at [8:15]. */
3199 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->i32, 2, 0), "");
3200 index = LLVMBuildAdd(builder, index, LLVMConstInt(ctx->i32, 1, 0), "");
3201 break;
3202 case DESC_SAMPLER:
3203 /* The sampler state is at [12:15]. */
3204 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->i32, 4, 0), "");
3205 index = LLVMBuildAdd(builder, index, LLVMConstInt(ctx->i32, 3, 0), "");
3206 list = LLVMBuildPointerCast(builder, list,
3207 const_array(ctx->v4i32, 0), "");
3208 break;
3209 }
3210
3211 return build_indexed_load_const(ctx, list, index);
3212 }
3213
3214 static LLVMValueRef get_sampler_desc(struct si_shader_context *ctx,
3215 LLVMValueRef index, enum desc_type type)
3216 {
3217 LLVMValueRef list = LLVMGetParam(ctx->radeon_bld.main_fn,
3218 SI_PARAM_SAMPLERS);
3219
3220 return get_sampler_desc_custom(ctx, list, index, type);
3221 }
3222
3223 static void tex_fetch_ptrs(
3224 struct lp_build_tgsi_context *bld_base,
3225 struct lp_build_emit_data *emit_data,
3226 LLVMValueRef *res_ptr, LLVMValueRef *samp_ptr, LLVMValueRef *fmask_ptr)
3227 {
3228 struct si_shader_context *ctx = si_shader_context(bld_base);
3229 const struct tgsi_full_instruction *inst = emit_data->inst;
3230 unsigned target = inst->Texture.Texture;
3231 unsigned sampler_src;
3232 unsigned sampler_index;
3233
3234 sampler_src = emit_data->inst->Instruction.NumSrcRegs - 1;
3235 sampler_index = emit_data->inst->Src[sampler_src].Register.Index;
3236
3237 if (emit_data->inst->Src[sampler_src].Register.Indirect) {
3238 const struct tgsi_full_src_register *reg = &emit_data->inst->Src[sampler_src];
3239 LLVMValueRef ind_index;
3240
3241 ind_index = get_indirect_index(ctx, &reg->Indirect, reg->Register.Index);
3242
3243 *res_ptr = get_sampler_desc(ctx, ind_index, DESC_IMAGE);
3244
3245 if (target == TGSI_TEXTURE_2D_MSAA ||
3246 target == TGSI_TEXTURE_2D_ARRAY_MSAA) {
3247 *samp_ptr = NULL;
3248 *fmask_ptr = get_sampler_desc(ctx, ind_index, DESC_FMASK);
3249 } else {
3250 *samp_ptr = get_sampler_desc(ctx, ind_index, DESC_SAMPLER);
3251 *fmask_ptr = NULL;
3252 }
3253 } else {
3254 *res_ptr = ctx->sampler_views[sampler_index];
3255 *samp_ptr = ctx->sampler_states[sampler_index];
3256 *fmask_ptr = ctx->fmasks[sampler_index];
3257 }
3258 }
3259
3260 static void tex_fetch_args(
3261 struct lp_build_tgsi_context *bld_base,
3262 struct lp_build_emit_data *emit_data)
3263 {
3264 struct si_shader_context *ctx = si_shader_context(bld_base);
3265 struct gallivm_state *gallivm = bld_base->base.gallivm;
3266 LLVMBuilderRef builder = gallivm->builder;
3267 const struct tgsi_full_instruction *inst = emit_data->inst;
3268 unsigned opcode = inst->Instruction.Opcode;
3269 unsigned target = inst->Texture.Texture;
3270 LLVMValueRef coords[5], derivs[6];
3271 LLVMValueRef address[16];
3272 int ref_pos;
3273 unsigned num_coords = tgsi_util_get_texture_coord_dim(target, &ref_pos);
3274 unsigned count = 0;
3275 unsigned chan;
3276 unsigned num_deriv_channels = 0;
3277 bool has_offset = inst->Texture.NumOffsets > 0;
3278 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL;
3279 unsigned dmask = 0xf;
3280
3281 tex_fetch_ptrs(bld_base, emit_data, &res_ptr, &samp_ptr, &fmask_ptr);
3282
3283 if (opcode == TGSI_OPCODE_TXQ) {
3284 if (target == TGSI_TEXTURE_BUFFER) {
3285 /* Read the size from the buffer descriptor directly. */
3286 LLVMValueRef res = LLVMBuildBitCast(builder, res_ptr, ctx->v8i32, "");
3287 emit_data->args[0] = get_buffer_size(bld_base, res);
3288 return;
3289 }
3290
3291 /* Textures - set the mip level. */
3292 address[count++] = lp_build_emit_fetch(bld_base, inst, 0, TGSI_CHAN_X);
3293
3294 set_tex_fetch_args(ctx, emit_data, opcode, target, res_ptr,
3295 NULL, address, count, 0xf);
3296 return;
3297 }
3298
3299 if (target == TGSI_TEXTURE_BUFFER) {
3300 LLVMTypeRef v2i128 = LLVMVectorType(ctx->i128, 2);
3301
3302 /* Bitcast and truncate v8i32 to v16i8. */
3303 LLVMValueRef res = res_ptr;
3304 res = LLVMBuildBitCast(gallivm->builder, res, v2i128, "");
3305 res = LLVMBuildExtractElement(gallivm->builder, res, bld_base->uint_bld.one, "");
3306 res = LLVMBuildBitCast(gallivm->builder, res, ctx->v16i8, "");
3307
3308 emit_data->dst_type = ctx->v4f32;
3309 emit_data->args[0] = res;
3310 emit_data->args[1] = bld_base->uint_bld.zero;
3311 emit_data->args[2] = lp_build_emit_fetch(bld_base, emit_data->inst, 0, TGSI_CHAN_X);
3312 emit_data->arg_count = 3;
3313 return;
3314 }
3315
3316 /* Fetch and project texture coordinates */
3317 coords[3] = lp_build_emit_fetch(bld_base, emit_data->inst, 0, TGSI_CHAN_W);
3318 for (chan = 0; chan < 3; chan++ ) {
3319 coords[chan] = lp_build_emit_fetch(bld_base,
3320 emit_data->inst, 0,
3321 chan);
3322 if (opcode == TGSI_OPCODE_TXP)
3323 coords[chan] = lp_build_emit_llvm_binary(bld_base,
3324 TGSI_OPCODE_DIV,
3325 coords[chan],
3326 coords[3]);
3327 }
3328
3329 if (opcode == TGSI_OPCODE_TXP)
3330 coords[3] = bld_base->base.one;
3331
3332 /* Pack offsets. */
3333 if (has_offset && opcode != TGSI_OPCODE_TXF) {
3334 /* The offsets are six-bit signed integers packed like this:
3335 * X=[5:0], Y=[13:8], and Z=[21:16].
3336 */
3337 LLVMValueRef offset[3], pack;
3338
3339 assert(inst->Texture.NumOffsets == 1);
3340
3341 for (chan = 0; chan < 3; chan++) {
3342 offset[chan] = lp_build_emit_fetch_texoffset(bld_base,
3343 emit_data->inst, 0, chan);
3344 offset[chan] = LLVMBuildAnd(gallivm->builder, offset[chan],
3345 lp_build_const_int32(gallivm, 0x3f), "");
3346 if (chan)
3347 offset[chan] = LLVMBuildShl(gallivm->builder, offset[chan],
3348 lp_build_const_int32(gallivm, chan*8), "");
3349 }
3350
3351 pack = LLVMBuildOr(gallivm->builder, offset[0], offset[1], "");
3352 pack = LLVMBuildOr(gallivm->builder, pack, offset[2], "");
3353 address[count++] = pack;
3354 }
3355
3356 /* Pack LOD bias value */
3357 if (opcode == TGSI_OPCODE_TXB)
3358 address[count++] = coords[3];
3359 if (opcode == TGSI_OPCODE_TXB2)
3360 address[count++] = lp_build_emit_fetch(bld_base, inst, 1, TGSI_CHAN_X);
3361
3362 /* Pack depth comparison value */
3363 if (tgsi_is_shadow_target(target) && opcode != TGSI_OPCODE_LODQ) {
3364 if (target == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
3365 address[count++] = lp_build_emit_fetch(bld_base, inst, 1, TGSI_CHAN_X);
3366 } else {
3367 assert(ref_pos >= 0);
3368 address[count++] = coords[ref_pos];
3369 }
3370 }
3371
3372 /* Pack user derivatives */
3373 if (opcode == TGSI_OPCODE_TXD) {
3374 int param, num_src_deriv_channels;
3375
3376 switch (target) {
3377 case TGSI_TEXTURE_3D:
3378 num_src_deriv_channels = 3;
3379 num_deriv_channels = 3;
3380 break;
3381 case TGSI_TEXTURE_2D:
3382 case TGSI_TEXTURE_SHADOW2D:
3383 case TGSI_TEXTURE_RECT:
3384 case TGSI_TEXTURE_SHADOWRECT:
3385 case TGSI_TEXTURE_2D_ARRAY:
3386 case TGSI_TEXTURE_SHADOW2D_ARRAY:
3387 num_src_deriv_channels = 2;
3388 num_deriv_channels = 2;
3389 break;
3390 case TGSI_TEXTURE_CUBE:
3391 case TGSI_TEXTURE_SHADOWCUBE:
3392 case TGSI_TEXTURE_CUBE_ARRAY:
3393 case TGSI_TEXTURE_SHADOWCUBE_ARRAY:
3394 /* Cube derivatives will be converted to 2D. */
3395 num_src_deriv_channels = 3;
3396 num_deriv_channels = 2;
3397 break;
3398 case TGSI_TEXTURE_1D:
3399 case TGSI_TEXTURE_SHADOW1D:
3400 case TGSI_TEXTURE_1D_ARRAY:
3401 case TGSI_TEXTURE_SHADOW1D_ARRAY:
3402 num_src_deriv_channels = 1;
3403 num_deriv_channels = 1;
3404 break;
3405 default:
3406 unreachable("invalid target");
3407 }
3408
3409 for (param = 0; param < 2; param++)
3410 for (chan = 0; chan < num_src_deriv_channels; chan++)
3411 derivs[param * num_src_deriv_channels + chan] =
3412 lp_build_emit_fetch(bld_base, inst, param+1, chan);
3413 }
3414
3415 if (target == TGSI_TEXTURE_CUBE ||
3416 target == TGSI_TEXTURE_CUBE_ARRAY ||
3417 target == TGSI_TEXTURE_SHADOWCUBE ||
3418 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY)
3419 radeon_llvm_emit_prepare_cube_coords(bld_base, emit_data, coords, derivs);
3420
3421 if (opcode == TGSI_OPCODE_TXD)
3422 for (int i = 0; i < num_deriv_channels * 2; i++)
3423 address[count++] = derivs[i];
3424
3425 /* Pack texture coordinates */
3426 address[count++] = coords[0];
3427 if (num_coords > 1)
3428 address[count++] = coords[1];
3429 if (num_coords > 2)
3430 address[count++] = coords[2];
3431
3432 /* Pack LOD or sample index */
3433 if (opcode == TGSI_OPCODE_TXL || opcode == TGSI_OPCODE_TXF)
3434 address[count++] = coords[3];
3435 else if (opcode == TGSI_OPCODE_TXL2)
3436 address[count++] = lp_build_emit_fetch(bld_base, inst, 1, TGSI_CHAN_X);
3437
3438 if (count > 16) {
3439 assert(!"Cannot handle more than 16 texture address parameters");
3440 count = 16;
3441 }
3442
3443 for (chan = 0; chan < count; chan++ ) {
3444 address[chan] = LLVMBuildBitCast(gallivm->builder,
3445 address[chan], ctx->i32, "");
3446 }
3447
3448 /* Adjust the sample index according to FMASK.
3449 *
3450 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
3451 * which is the identity mapping. Each nibble says which physical sample
3452 * should be fetched to get that sample.
3453 *
3454 * For example, 0x11111100 means there are only 2 samples stored and
3455 * the second sample covers 3/4 of the pixel. When reading samples 0
3456 * and 1, return physical sample 0 (determined by the first two 0s
3457 * in FMASK), otherwise return physical sample 1.
3458 *
3459 * The sample index should be adjusted as follows:
3460 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
3461 */
3462 if (target == TGSI_TEXTURE_2D_MSAA ||
3463 target == TGSI_TEXTURE_2D_ARRAY_MSAA) {
3464 struct lp_build_context *uint_bld = &bld_base->uint_bld;
3465 struct lp_build_emit_data txf_emit_data = *emit_data;
3466 LLVMValueRef txf_address[4];
3467 unsigned txf_count = count;
3468 struct tgsi_full_instruction inst = {};
3469
3470 memcpy(txf_address, address, sizeof(txf_address));
3471
3472 if (target == TGSI_TEXTURE_2D_MSAA) {
3473 txf_address[2] = bld_base->uint_bld.zero;
3474 }
3475 txf_address[3] = bld_base->uint_bld.zero;
3476
3477 /* Read FMASK using TXF. */
3478 inst.Instruction.Opcode = TGSI_OPCODE_TXF;
3479 inst.Texture.Texture = target;
3480 txf_emit_data.inst = &inst;
3481 txf_emit_data.chan = 0;
3482 set_tex_fetch_args(ctx, &txf_emit_data, TGSI_OPCODE_TXF,
3483 target, fmask_ptr, NULL,
3484 txf_address, txf_count, 0xf);
3485 build_tex_intrinsic(&tex_action, bld_base, &txf_emit_data);
3486
3487 /* Initialize some constants. */
3488 LLVMValueRef four = LLVMConstInt(ctx->i32, 4, 0);
3489 LLVMValueRef F = LLVMConstInt(ctx->i32, 0xF, 0);
3490
3491 /* Apply the formula. */
3492 LLVMValueRef fmask =
3493 LLVMBuildExtractElement(gallivm->builder,
3494 txf_emit_data.output[0],
3495 uint_bld->zero, "");
3496
3497 unsigned sample_chan = target == TGSI_TEXTURE_2D_MSAA ? 2 : 3;
3498
3499 LLVMValueRef sample_index4 =
3500 LLVMBuildMul(gallivm->builder, address[sample_chan], four, "");
3501
3502 LLVMValueRef shifted_fmask =
3503 LLVMBuildLShr(gallivm->builder, fmask, sample_index4, "");
3504
3505 LLVMValueRef final_sample =
3506 LLVMBuildAnd(gallivm->builder, shifted_fmask, F, "");
3507
3508 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
3509 * resource descriptor is 0 (invalid),
3510 */
3511 LLVMValueRef fmask_desc =
3512 LLVMBuildBitCast(gallivm->builder, fmask_ptr,
3513 ctx->v8i32, "");
3514
3515 LLVMValueRef fmask_word1 =
3516 LLVMBuildExtractElement(gallivm->builder, fmask_desc,
3517 uint_bld->one, "");
3518
3519 LLVMValueRef word1_is_nonzero =
3520 LLVMBuildICmp(gallivm->builder, LLVMIntNE,
3521 fmask_word1, uint_bld->zero, "");
3522
3523 /* Replace the MSAA sample index. */
3524 address[sample_chan] =
3525 LLVMBuildSelect(gallivm->builder, word1_is_nonzero,
3526 final_sample, address[sample_chan], "");
3527 }
3528
3529 if (opcode == TGSI_OPCODE_TXF) {
3530 /* add tex offsets */
3531 if (inst->Texture.NumOffsets) {
3532 struct lp_build_context *uint_bld = &bld_base->uint_bld;
3533 struct lp_build_tgsi_soa_context *bld = lp_soa_context(bld_base);
3534 const struct tgsi_texture_offset *off = inst->TexOffsets;
3535
3536 assert(inst->Texture.NumOffsets == 1);
3537
3538 switch (target) {
3539 case TGSI_TEXTURE_3D:
3540 address[2] = lp_build_add(uint_bld, address[2],
3541 bld->immediates[off->Index][off->SwizzleZ]);
3542 /* fall through */
3543 case TGSI_TEXTURE_2D:
3544 case TGSI_TEXTURE_SHADOW2D:
3545 case TGSI_TEXTURE_RECT:
3546 case TGSI_TEXTURE_SHADOWRECT:
3547 case TGSI_TEXTURE_2D_ARRAY:
3548 case TGSI_TEXTURE_SHADOW2D_ARRAY:
3549 address[1] =
3550 lp_build_add(uint_bld, address[1],
3551 bld->immediates[off->Index][off->SwizzleY]);
3552 /* fall through */
3553 case TGSI_TEXTURE_1D:
3554 case TGSI_TEXTURE_SHADOW1D:
3555 case TGSI_TEXTURE_1D_ARRAY:
3556 case TGSI_TEXTURE_SHADOW1D_ARRAY:
3557 address[0] =
3558 lp_build_add(uint_bld, address[0],
3559 bld->immediates[off->Index][off->SwizzleX]);
3560 break;
3561 /* texture offsets do not apply to other texture targets */
3562 }
3563 }
3564 }
3565
3566 if (opcode == TGSI_OPCODE_TG4) {
3567 unsigned gather_comp = 0;
3568
3569 /* DMASK was repurposed for GATHER4. 4 components are always
3570 * returned and DMASK works like a swizzle - it selects
3571 * the component to fetch. The only valid DMASK values are
3572 * 1=red, 2=green, 4=blue, 8=alpha. (e.g. 1 returns
3573 * (red,red,red,red) etc.) The ISA document doesn't mention
3574 * this.
3575 */
3576
3577 /* Get the component index from src1.x for Gather4. */
3578 if (!tgsi_is_shadow_target(target)) {
3579 LLVMValueRef (*imms)[4] = lp_soa_context(bld_base)->immediates;
3580 LLVMValueRef comp_imm;
3581 struct tgsi_src_register src1 = inst->Src[1].Register;
3582
3583 assert(src1.File == TGSI_FILE_IMMEDIATE);
3584
3585 comp_imm = imms[src1.Index][src1.SwizzleX];
3586 gather_comp = LLVMConstIntGetZExtValue(comp_imm);
3587 gather_comp = CLAMP(gather_comp, 0, 3);
3588 }
3589
3590 dmask = 1 << gather_comp;
3591 }
3592
3593 set_tex_fetch_args(ctx, emit_data, opcode, target, res_ptr,
3594 samp_ptr, address, count, dmask);
3595 }
3596
3597 static void build_tex_intrinsic(const struct lp_build_tgsi_action *action,
3598 struct lp_build_tgsi_context *bld_base,
3599 struct lp_build_emit_data *emit_data)
3600 {
3601 struct lp_build_context *base = &bld_base->base;
3602 unsigned opcode = emit_data->inst->Instruction.Opcode;
3603 unsigned target = emit_data->inst->Texture.Texture;
3604 char intr_name[127];
3605 bool has_offset = emit_data->inst->Texture.NumOffsets > 0;
3606 bool is_shadow = tgsi_is_shadow_target(target);
3607 char type[64];
3608 const char *name = "llvm.SI.image.sample";
3609 const char *infix = "";
3610
3611 if (opcode == TGSI_OPCODE_TXQ && target == TGSI_TEXTURE_BUFFER) {
3612 /* Just return the buffer size. */
3613 emit_data->output[emit_data->chan] = emit_data->args[0];
3614 return;
3615 }
3616
3617 if (target == TGSI_TEXTURE_BUFFER) {
3618 emit_data->output[emit_data->chan] = lp_build_intrinsic(
3619 base->gallivm->builder,
3620 "llvm.SI.vs.load.input", emit_data->dst_type,
3621 emit_data->args, emit_data->arg_count,
3622 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
3623 return;
3624 }
3625
3626 switch (opcode) {
3627 case TGSI_OPCODE_TXF:
3628 name = target == TGSI_TEXTURE_2D_MSAA ||
3629 target == TGSI_TEXTURE_2D_ARRAY_MSAA ?
3630 "llvm.SI.image.load" :
3631 "llvm.SI.image.load.mip";
3632 is_shadow = false;
3633 has_offset = false;
3634 break;
3635 case TGSI_OPCODE_TXQ:
3636 name = "llvm.SI.getresinfo";
3637 is_shadow = false;
3638 has_offset = false;
3639 break;
3640 case TGSI_OPCODE_LODQ:
3641 name = "llvm.SI.getlod";
3642 is_shadow = false;
3643 has_offset = false;
3644 break;
3645 case TGSI_OPCODE_TEX:
3646 case TGSI_OPCODE_TEX2:
3647 case TGSI_OPCODE_TXP:
3648 break;
3649 case TGSI_OPCODE_TXB:
3650 case TGSI_OPCODE_TXB2:
3651 infix = ".b";
3652 break;
3653 case TGSI_OPCODE_TXL:
3654 case TGSI_OPCODE_TXL2:
3655 infix = ".l";
3656 break;
3657 case TGSI_OPCODE_TXD:
3658 infix = ".d";
3659 break;
3660 case TGSI_OPCODE_TG4:
3661 name = "llvm.SI.gather4";
3662 break;
3663 default:
3664 assert(0);
3665 return;
3666 }
3667
3668 /* Add the type and suffixes .c, .o if needed. */
3669 build_int_type_name(LLVMTypeOf(emit_data->args[0]), type, sizeof(type));
3670 sprintf(intr_name, "%s%s%s%s.%s",
3671 name, is_shadow ? ".c" : "", infix,
3672 has_offset ? ".o" : "", type);
3673
3674 emit_data->output[emit_data->chan] = lp_build_intrinsic(
3675 base->gallivm->builder, intr_name, emit_data->dst_type,
3676 emit_data->args, emit_data->arg_count,
3677 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
3678
3679 /* Divide the number of layers by 6 to get the number of cubes. */
3680 if (opcode == TGSI_OPCODE_TXQ &&
3681 (target == TGSI_TEXTURE_CUBE_ARRAY ||
3682 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY)) {
3683 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
3684 LLVMValueRef two = lp_build_const_int32(bld_base->base.gallivm, 2);
3685 LLVMValueRef six = lp_build_const_int32(bld_base->base.gallivm, 6);
3686
3687 LLVMValueRef v4 = emit_data->output[emit_data->chan];
3688 LLVMValueRef z = LLVMBuildExtractElement(builder, v4, two, "");
3689 z = LLVMBuildSDiv(builder, z, six, "");
3690
3691 emit_data->output[emit_data->chan] =
3692 LLVMBuildInsertElement(builder, v4, z, two, "");
3693 }
3694 }
3695
3696 static void si_llvm_emit_txqs(
3697 const struct lp_build_tgsi_action *action,
3698 struct lp_build_tgsi_context *bld_base,
3699 struct lp_build_emit_data *emit_data)
3700 {
3701 struct si_shader_context *ctx = si_shader_context(bld_base);
3702 struct gallivm_state *gallivm = bld_base->base.gallivm;
3703 LLVMBuilderRef builder = gallivm->builder;
3704 LLVMValueRef res, samples;
3705 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL;
3706
3707 tex_fetch_ptrs(bld_base, emit_data, &res_ptr, &samp_ptr, &fmask_ptr);
3708
3709
3710 /* Read the samples from the descriptor directly. */
3711 res = LLVMBuildBitCast(builder, res_ptr, ctx->v8i32, "");
3712 samples = LLVMBuildExtractElement(
3713 builder, res,
3714 lp_build_const_int32(gallivm, 3), "");
3715 samples = LLVMBuildLShr(builder, samples,
3716 lp_build_const_int32(gallivm, 16), "");
3717 samples = LLVMBuildAnd(builder, samples,
3718 lp_build_const_int32(gallivm, 0xf), "");
3719 samples = LLVMBuildShl(builder, lp_build_const_int32(gallivm, 1),
3720 samples, "");
3721
3722 emit_data->output[emit_data->chan] = samples;
3723 }
3724
3725 /*
3726 * SI implements derivatives using the local data store (LDS)
3727 * All writes to the LDS happen in all executing threads at
3728 * the same time. TID is the Thread ID for the current
3729 * thread and is a value between 0 and 63, representing
3730 * the thread's position in the wavefront.
3731 *
3732 * For the pixel shader threads are grouped into quads of four pixels.
3733 * The TIDs of the pixels of a quad are:
3734 *
3735 * +------+------+
3736 * |4n + 0|4n + 1|
3737 * +------+------+
3738 * |4n + 2|4n + 3|
3739 * +------+------+
3740 *
3741 * So, masking the TID with 0xfffffffc yields the TID of the top left pixel
3742 * of the quad, masking with 0xfffffffd yields the TID of the top pixel of
3743 * the current pixel's column, and masking with 0xfffffffe yields the TID
3744 * of the left pixel of the current pixel's row.
3745 *
3746 * Adding 1 yields the TID of the pixel to the right of the left pixel, and
3747 * adding 2 yields the TID of the pixel below the top pixel.
3748 */
3749 /* masks for thread ID. */
3750 #define TID_MASK_TOP_LEFT 0xfffffffc
3751 #define TID_MASK_TOP 0xfffffffd
3752 #define TID_MASK_LEFT 0xfffffffe
3753
3754 static void si_llvm_emit_ddxy(
3755 const struct lp_build_tgsi_action *action,
3756 struct lp_build_tgsi_context *bld_base,
3757 struct lp_build_emit_data *emit_data)
3758 {
3759 struct si_shader_context *ctx = si_shader_context(bld_base);
3760 struct gallivm_state *gallivm = bld_base->base.gallivm;
3761 const struct tgsi_full_instruction *inst = emit_data->inst;
3762 unsigned opcode = inst->Instruction.Opcode;
3763 LLVMValueRef indices[2];
3764 LLVMValueRef store_ptr, load_ptr0, load_ptr1;
3765 LLVMValueRef tl, trbl, result[4];
3766 unsigned swizzle[4];
3767 unsigned c;
3768 int idx;
3769 unsigned mask;
3770
3771 indices[0] = bld_base->uint_bld.zero;
3772 indices[1] = lp_build_intrinsic(gallivm->builder, "llvm.SI.tid", ctx->i32,
3773 NULL, 0, LLVMReadNoneAttribute);
3774 store_ptr = LLVMBuildGEP(gallivm->builder, ctx->lds,
3775 indices, 2, "");
3776
3777 if (opcode == TGSI_OPCODE_DDX_FINE)
3778 mask = TID_MASK_LEFT;
3779 else if (opcode == TGSI_OPCODE_DDY_FINE)
3780 mask = TID_MASK_TOP;
3781 else
3782 mask = TID_MASK_TOP_LEFT;
3783
3784 indices[1] = LLVMBuildAnd(gallivm->builder, indices[1],
3785 lp_build_const_int32(gallivm, mask), "");
3786 load_ptr0 = LLVMBuildGEP(gallivm->builder, ctx->lds,
3787 indices, 2, "");
3788
3789 /* for DDX we want to next X pixel, DDY next Y pixel. */
3790 idx = (opcode == TGSI_OPCODE_DDX || opcode == TGSI_OPCODE_DDX_FINE) ? 1 : 2;
3791 indices[1] = LLVMBuildAdd(gallivm->builder, indices[1],
3792 lp_build_const_int32(gallivm, idx), "");
3793 load_ptr1 = LLVMBuildGEP(gallivm->builder, ctx->lds,
3794 indices, 2, "");
3795
3796 for (c = 0; c < 4; ++c) {
3797 unsigned i;
3798
3799 swizzle[c] = tgsi_util_get_full_src_register_swizzle(&inst->Src[0], c);
3800 for (i = 0; i < c; ++i) {
3801 if (swizzle[i] == swizzle[c]) {
3802 result[c] = result[i];
3803 break;
3804 }
3805 }
3806 if (i != c)
3807 continue;
3808
3809 LLVMBuildStore(gallivm->builder,
3810 LLVMBuildBitCast(gallivm->builder,
3811 lp_build_emit_fetch(bld_base, inst, 0, c),
3812 ctx->i32, ""),
3813 store_ptr);
3814
3815 tl = LLVMBuildLoad(gallivm->builder, load_ptr0, "");
3816 tl = LLVMBuildBitCast(gallivm->builder, tl, ctx->f32, "");
3817
3818 trbl = LLVMBuildLoad(gallivm->builder, load_ptr1, "");
3819 trbl = LLVMBuildBitCast(gallivm->builder, trbl, ctx->f32, "");
3820
3821 result[c] = LLVMBuildFSub(gallivm->builder, trbl, tl, "");
3822 }
3823
3824 emit_data->output[0] = lp_build_gather_values(gallivm, result, 4);
3825 }
3826
3827 /*
3828 * this takes an I,J coordinate pair,
3829 * and works out the X and Y derivatives.
3830 * it returns DDX(I), DDX(J), DDY(I), DDY(J).
3831 */
3832 static LLVMValueRef si_llvm_emit_ddxy_interp(
3833 struct lp_build_tgsi_context *bld_base,
3834 LLVMValueRef interp_ij)
3835 {
3836 struct si_shader_context *ctx = si_shader_context(bld_base);
3837 struct gallivm_state *gallivm = bld_base->base.gallivm;
3838 LLVMValueRef indices[2];
3839 LLVMValueRef store_ptr, load_ptr_x, load_ptr_y, load_ptr_ddx, load_ptr_ddy, temp, temp2;
3840 LLVMValueRef tl, tr, bl, result[4];
3841 unsigned c;
3842
3843 indices[0] = bld_base->uint_bld.zero;
3844 indices[1] = lp_build_intrinsic(gallivm->builder, "llvm.SI.tid", ctx->i32,
3845 NULL, 0, LLVMReadNoneAttribute);
3846 store_ptr = LLVMBuildGEP(gallivm->builder, ctx->lds,
3847 indices, 2, "");
3848
3849 temp = LLVMBuildAnd(gallivm->builder, indices[1],
3850 lp_build_const_int32(gallivm, TID_MASK_LEFT), "");
3851
3852 temp2 = LLVMBuildAnd(gallivm->builder, indices[1],
3853 lp_build_const_int32(gallivm, TID_MASK_TOP), "");
3854
3855 indices[1] = temp;
3856 load_ptr_x = LLVMBuildGEP(gallivm->builder, ctx->lds,
3857 indices, 2, "");
3858
3859 indices[1] = temp2;
3860 load_ptr_y = LLVMBuildGEP(gallivm->builder, ctx->lds,
3861 indices, 2, "");
3862
3863 indices[1] = LLVMBuildAdd(gallivm->builder, temp,
3864 lp_build_const_int32(gallivm, 1), "");
3865 load_ptr_ddx = LLVMBuildGEP(gallivm->builder, ctx->lds,
3866 indices, 2, "");
3867
3868 indices[1] = LLVMBuildAdd(gallivm->builder, temp2,
3869 lp_build_const_int32(gallivm, 2), "");
3870 load_ptr_ddy = LLVMBuildGEP(gallivm->builder, ctx->lds,
3871 indices, 2, "");
3872
3873 for (c = 0; c < 2; ++c) {
3874 LLVMValueRef store_val;
3875 LLVMValueRef c_ll = lp_build_const_int32(gallivm, c);
3876
3877 store_val = LLVMBuildExtractElement(gallivm->builder,
3878 interp_ij, c_ll, "");
3879 LLVMBuildStore(gallivm->builder,
3880 store_val,
3881 store_ptr);
3882
3883 tl = LLVMBuildLoad(gallivm->builder, load_ptr_x, "");
3884 tl = LLVMBuildBitCast(gallivm->builder, tl, ctx->f32, "");
3885
3886 tr = LLVMBuildLoad(gallivm->builder, load_ptr_ddx, "");
3887 tr = LLVMBuildBitCast(gallivm->builder, tr, ctx->f32, "");
3888
3889 result[c] = LLVMBuildFSub(gallivm->builder, tr, tl, "");
3890
3891 tl = LLVMBuildLoad(gallivm->builder, load_ptr_y, "");
3892 tl = LLVMBuildBitCast(gallivm->builder, tl, ctx->f32, "");
3893
3894 bl = LLVMBuildLoad(gallivm->builder, load_ptr_ddy, "");
3895 bl = LLVMBuildBitCast(gallivm->builder, bl, ctx->f32, "");
3896
3897 result[c + 2] = LLVMBuildFSub(gallivm->builder, bl, tl, "");
3898 }
3899
3900 return lp_build_gather_values(gallivm, result, 4);
3901 }
3902
3903 static void interp_fetch_args(
3904 struct lp_build_tgsi_context *bld_base,
3905 struct lp_build_emit_data *emit_data)
3906 {
3907 struct si_shader_context *ctx = si_shader_context(bld_base);
3908 struct gallivm_state *gallivm = bld_base->base.gallivm;
3909 const struct tgsi_full_instruction *inst = emit_data->inst;
3910
3911 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET) {
3912 /* offset is in second src, first two channels */
3913 emit_data->args[0] = lp_build_emit_fetch(bld_base,
3914 emit_data->inst, 1,
3915 TGSI_CHAN_X);
3916 emit_data->args[1] = lp_build_emit_fetch(bld_base,
3917 emit_data->inst, 1,
3918 TGSI_CHAN_Y);
3919 emit_data->arg_count = 2;
3920 } else if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
3921 LLVMValueRef sample_position;
3922 LLVMValueRef sample_id;
3923 LLVMValueRef halfval = lp_build_const_float(gallivm, 0.5f);
3924
3925 /* fetch sample ID, then fetch its sample position,
3926 * and place into first two channels.
3927 */
3928 sample_id = lp_build_emit_fetch(bld_base,
3929 emit_data->inst, 1, TGSI_CHAN_X);
3930 sample_id = LLVMBuildBitCast(gallivm->builder, sample_id,
3931 ctx->i32, "");
3932 sample_position = load_sample_position(&ctx->radeon_bld, sample_id);
3933
3934 emit_data->args[0] = LLVMBuildExtractElement(gallivm->builder,
3935 sample_position,
3936 lp_build_const_int32(gallivm, 0), "");
3937
3938 emit_data->args[0] = LLVMBuildFSub(gallivm->builder, emit_data->args[0], halfval, "");
3939 emit_data->args[1] = LLVMBuildExtractElement(gallivm->builder,
3940 sample_position,
3941 lp_build_const_int32(gallivm, 1), "");
3942 emit_data->args[1] = LLVMBuildFSub(gallivm->builder, emit_data->args[1], halfval, "");
3943 emit_data->arg_count = 2;
3944 }
3945 }
3946
3947 static void build_interp_intrinsic(const struct lp_build_tgsi_action *action,
3948 struct lp_build_tgsi_context *bld_base,
3949 struct lp_build_emit_data *emit_data)
3950 {
3951 struct si_shader_context *ctx = si_shader_context(bld_base);
3952 struct si_shader *shader = ctx->shader;
3953 struct gallivm_state *gallivm = bld_base->base.gallivm;
3954 LLVMValueRef interp_param;
3955 const struct tgsi_full_instruction *inst = emit_data->inst;
3956 const char *intr_name;
3957 int input_index = inst->Src[0].Register.Index;
3958 int chan;
3959 int i;
3960 LLVMValueRef attr_number;
3961 LLVMValueRef params = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_PRIM_MASK);
3962 int interp_param_idx;
3963 unsigned interp = shader->selector->info.input_interpolate[input_index];
3964 unsigned location;
3965
3966 assert(inst->Src[0].Register.File == TGSI_FILE_INPUT);
3967
3968 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
3969 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE)
3970 location = TGSI_INTERPOLATE_LOC_CENTER;
3971 else
3972 location = TGSI_INTERPOLATE_LOC_CENTROID;
3973
3974 interp_param_idx = lookup_interp_param_index(interp, location);
3975 if (interp_param_idx == -1)
3976 return;
3977 else if (interp_param_idx)
3978 interp_param = LLVMGetParam(ctx->radeon_bld.main_fn, interp_param_idx);
3979 else
3980 interp_param = NULL;
3981
3982 attr_number = lp_build_const_int32(gallivm, input_index);
3983
3984 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
3985 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
3986 LLVMValueRef ij_out[2];
3987 LLVMValueRef ddxy_out = si_llvm_emit_ddxy_interp(bld_base, interp_param);
3988
3989 /*
3990 * take the I then J parameters, and the DDX/Y for it, and
3991 * calculate the IJ inputs for the interpolator.
3992 * temp1 = ddx * offset/sample.x + I;
3993 * interp_param.I = ddy * offset/sample.y + temp1;
3994 * temp1 = ddx * offset/sample.x + J;
3995 * interp_param.J = ddy * offset/sample.y + temp1;
3996 */
3997 for (i = 0; i < 2; i++) {
3998 LLVMValueRef ix_ll = lp_build_const_int32(gallivm, i);
3999 LLVMValueRef iy_ll = lp_build_const_int32(gallivm, i + 2);
4000 LLVMValueRef ddx_el = LLVMBuildExtractElement(gallivm->builder,
4001 ddxy_out, ix_ll, "");
4002 LLVMValueRef ddy_el = LLVMBuildExtractElement(gallivm->builder,
4003 ddxy_out, iy_ll, "");
4004 LLVMValueRef interp_el = LLVMBuildExtractElement(gallivm->builder,
4005 interp_param, ix_ll, "");
4006 LLVMValueRef temp1, temp2;
4007
4008 interp_el = LLVMBuildBitCast(gallivm->builder, interp_el,
4009 ctx->f32, "");
4010
4011 temp1 = LLVMBuildFMul(gallivm->builder, ddx_el, emit_data->args[0], "");
4012
4013 temp1 = LLVMBuildFAdd(gallivm->builder, temp1, interp_el, "");
4014
4015 temp2 = LLVMBuildFMul(gallivm->builder, ddy_el, emit_data->args[1], "");
4016
4017 temp2 = LLVMBuildFAdd(gallivm->builder, temp2, temp1, "");
4018
4019 ij_out[i] = LLVMBuildBitCast(gallivm->builder,
4020 temp2, ctx->i32, "");
4021 }
4022 interp_param = lp_build_gather_values(bld_base->base.gallivm, ij_out, 2);
4023 }
4024
4025 intr_name = interp_param ? "llvm.SI.fs.interp" : "llvm.SI.fs.constant";
4026 for (chan = 0; chan < 2; chan++) {
4027 LLVMValueRef args[4];
4028 LLVMValueRef llvm_chan;
4029 unsigned schan;
4030
4031 schan = tgsi_util_get_full_src_register_swizzle(&inst->Src[0], chan);
4032 llvm_chan = lp_build_const_int32(gallivm, schan);
4033
4034 args[0] = llvm_chan;
4035 args[1] = attr_number;
4036 args[2] = params;
4037 args[3] = interp_param;
4038
4039 emit_data->output[chan] =
4040 lp_build_intrinsic(gallivm->builder, intr_name,
4041 ctx->f32, args, args[3] ? 4 : 3,
4042 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
4043 }
4044 }
4045
4046 static unsigned si_llvm_get_stream(struct lp_build_tgsi_context *bld_base,
4047 struct lp_build_emit_data *emit_data)
4048 {
4049 LLVMValueRef (*imms)[4] = lp_soa_context(bld_base)->immediates;
4050 struct tgsi_src_register src0 = emit_data->inst->Src[0].Register;
4051 unsigned stream;
4052
4053 assert(src0.File == TGSI_FILE_IMMEDIATE);
4054
4055 stream = LLVMConstIntGetZExtValue(imms[src0.Index][src0.SwizzleX]) & 0x3;
4056 return stream;
4057 }
4058
4059 /* Emit one vertex from the geometry shader */
4060 static void si_llvm_emit_vertex(
4061 const struct lp_build_tgsi_action *action,
4062 struct lp_build_tgsi_context *bld_base,
4063 struct lp_build_emit_data *emit_data)
4064 {
4065 struct si_shader_context *ctx = si_shader_context(bld_base);
4066 struct lp_build_context *uint = &bld_base->uint_bld;
4067 struct si_shader *shader = ctx->shader;
4068 struct tgsi_shader_info *info = &shader->selector->info;
4069 struct gallivm_state *gallivm = bld_base->base.gallivm;
4070 LLVMValueRef soffset = LLVMGetParam(ctx->radeon_bld.main_fn,
4071 SI_PARAM_GS2VS_OFFSET);
4072 LLVMValueRef gs_next_vertex;
4073 LLVMValueRef can_emit, kill;
4074 LLVMValueRef args[2];
4075 unsigned chan;
4076 int i;
4077 unsigned stream;
4078
4079 stream = si_llvm_get_stream(bld_base, emit_data);
4080
4081 /* Write vertex attribute values to GSVS ring */
4082 gs_next_vertex = LLVMBuildLoad(gallivm->builder,
4083 ctx->gs_next_vertex[stream],
4084 "");
4085
4086 /* If this thread has already emitted the declared maximum number of
4087 * vertices, kill it: excessive vertex emissions are not supposed to
4088 * have any effect, and GS threads have no externally observable
4089 * effects other than emitting vertices.
4090 */
4091 can_emit = LLVMBuildICmp(gallivm->builder, LLVMIntULE, gs_next_vertex,
4092 lp_build_const_int32(gallivm,
4093 shader->selector->gs_max_out_vertices), "");
4094 kill = lp_build_select(&bld_base->base, can_emit,
4095 lp_build_const_float(gallivm, 1.0f),
4096 lp_build_const_float(gallivm, -1.0f));
4097
4098 lp_build_intrinsic(gallivm->builder, "llvm.AMDGPU.kill",
4099 ctx->voidt, &kill, 1, 0);
4100
4101 for (i = 0; i < info->num_outputs; i++) {
4102 LLVMValueRef *out_ptr =
4103 ctx->radeon_bld.soa.outputs[i];
4104
4105 for (chan = 0; chan < 4; chan++) {
4106 LLVMValueRef out_val = LLVMBuildLoad(gallivm->builder, out_ptr[chan], "");
4107 LLVMValueRef voffset =
4108 lp_build_const_int32(gallivm, (i * 4 + chan) *
4109 shader->selector->gs_max_out_vertices);
4110
4111 voffset = lp_build_add(uint, voffset, gs_next_vertex);
4112 voffset = lp_build_mul_imm(uint, voffset, 4);
4113
4114 out_val = LLVMBuildBitCast(gallivm->builder, out_val, ctx->i32, "");
4115
4116 build_tbuffer_store(ctx,
4117 ctx->gsvs_ring[stream],
4118 out_val, 1,
4119 voffset, soffset, 0,
4120 V_008F0C_BUF_DATA_FORMAT_32,
4121 V_008F0C_BUF_NUM_FORMAT_UINT,
4122 1, 0, 1, 1, 0);
4123 }
4124 }
4125 gs_next_vertex = lp_build_add(uint, gs_next_vertex,
4126 lp_build_const_int32(gallivm, 1));
4127
4128 LLVMBuildStore(gallivm->builder, gs_next_vertex, ctx->gs_next_vertex[stream]);
4129
4130 /* Signal vertex emission */
4131 args[0] = lp_build_const_int32(gallivm, SENDMSG_GS_OP_EMIT | SENDMSG_GS | (stream << 8));
4132 args[1] = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_GS_WAVE_ID);
4133 lp_build_intrinsic(gallivm->builder, "llvm.SI.sendmsg",
4134 ctx->voidt, args, 2, LLVMNoUnwindAttribute);
4135 }
4136
4137 /* Cut one primitive from the geometry shader */
4138 static void si_llvm_emit_primitive(
4139 const struct lp_build_tgsi_action *action,
4140 struct lp_build_tgsi_context *bld_base,
4141 struct lp_build_emit_data *emit_data)
4142 {
4143 struct si_shader_context *ctx = si_shader_context(bld_base);
4144 struct gallivm_state *gallivm = bld_base->base.gallivm;
4145 LLVMValueRef args[2];
4146 unsigned stream;
4147
4148 /* Signal primitive cut */
4149 stream = si_llvm_get_stream(bld_base, emit_data);
4150 args[0] = lp_build_const_int32(gallivm, SENDMSG_GS_OP_CUT | SENDMSG_GS | (stream << 8));
4151 args[1] = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_GS_WAVE_ID);
4152 lp_build_intrinsic(gallivm->builder, "llvm.SI.sendmsg",
4153 ctx->voidt, args, 2, LLVMNoUnwindAttribute);
4154 }
4155
4156 static void si_llvm_emit_barrier(const struct lp_build_tgsi_action *action,
4157 struct lp_build_tgsi_context *bld_base,
4158 struct lp_build_emit_data *emit_data)
4159 {
4160 struct si_shader_context *ctx = si_shader_context(bld_base);
4161 struct gallivm_state *gallivm = bld_base->base.gallivm;
4162
4163 lp_build_intrinsic(gallivm->builder,
4164 HAVE_LLVM >= 0x0309 ? "llvm.amdgcn.s.barrier"
4165 : "llvm.AMDGPU.barrier.local",
4166 ctx->voidt, NULL, 0, LLVMNoUnwindAttribute);
4167 }
4168
4169 static const struct lp_build_tgsi_action tex_action = {
4170 .fetch_args = tex_fetch_args,
4171 .emit = build_tex_intrinsic,
4172 };
4173
4174 static const struct lp_build_tgsi_action interp_action = {
4175 .fetch_args = interp_fetch_args,
4176 .emit = build_interp_intrinsic,
4177 };
4178
4179 static void si_create_function(struct si_shader_context *ctx,
4180 LLVMTypeRef *returns, unsigned num_returns,
4181 LLVMTypeRef *params, unsigned num_params,
4182 int last_array_pointer, int last_sgpr)
4183 {
4184 int i;
4185
4186 radeon_llvm_create_func(&ctx->radeon_bld, returns, num_returns,
4187 params, num_params);
4188 radeon_llvm_shader_type(ctx->radeon_bld.main_fn, ctx->type);
4189 ctx->return_value = LLVMGetUndef(ctx->radeon_bld.return_type);
4190
4191 for (i = 0; i <= last_sgpr; ++i) {
4192 LLVMValueRef P = LLVMGetParam(ctx->radeon_bld.main_fn, i);
4193
4194 /* We tell llvm that array inputs are passed by value to allow Sinking pass
4195 * to move load. Inputs are constant so this is fine. */
4196 if (i <= last_array_pointer)
4197 LLVMAddAttribute(P, LLVMByValAttribute);
4198 else
4199 LLVMAddAttribute(P, LLVMInRegAttribute);
4200 }
4201 }
4202
4203 static void create_meta_data(struct si_shader_context *ctx)
4204 {
4205 struct gallivm_state *gallivm = ctx->radeon_bld.soa.bld_base.base.gallivm;
4206 LLVMValueRef args[3];
4207
4208 args[0] = LLVMMDStringInContext(gallivm->context, "const", 5);
4209 args[1] = 0;
4210 args[2] = lp_build_const_int32(gallivm, 1);
4211
4212 ctx->const_md = LLVMMDNodeInContext(gallivm->context, args, 3);
4213 }
4214
4215 static void declare_streamout_params(struct si_shader_context *ctx,
4216 struct pipe_stream_output_info *so,
4217 LLVMTypeRef *params, LLVMTypeRef i32,
4218 unsigned *num_params)
4219 {
4220 int i;
4221
4222 /* Streamout SGPRs. */
4223 if (so->num_outputs) {
4224 params[ctx->param_streamout_config = (*num_params)++] = i32;
4225 params[ctx->param_streamout_write_index = (*num_params)++] = i32;
4226 }
4227 /* A streamout buffer offset is loaded if the stride is non-zero. */
4228 for (i = 0; i < 4; i++) {
4229 if (!so->stride[i])
4230 continue;
4231
4232 params[ctx->param_streamout_offset[i] = (*num_params)++] = i32;
4233 }
4234 }
4235
4236 static unsigned llvm_get_type_size(LLVMTypeRef type)
4237 {
4238 LLVMTypeKind kind = LLVMGetTypeKind(type);
4239
4240 switch (kind) {
4241 case LLVMIntegerTypeKind:
4242 return LLVMGetIntTypeWidth(type) / 8;
4243 case LLVMFloatTypeKind:
4244 return 4;
4245 case LLVMPointerTypeKind:
4246 return 8;
4247 case LLVMVectorTypeKind:
4248 return LLVMGetVectorSize(type) *
4249 llvm_get_type_size(LLVMGetElementType(type));
4250 default:
4251 assert(0);
4252 return 0;
4253 }
4254 }
4255
4256 static void declare_tess_lds(struct si_shader_context *ctx)
4257 {
4258 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
4259 LLVMTypeRef i32 = ctx->radeon_bld.soa.bld_base.uint_bld.elem_type;
4260
4261 /* This is the upper bound, maximum is 32 inputs times 32 vertices */
4262 unsigned vertex_data_dw_size = 32*32*4;
4263 unsigned patch_data_dw_size = 32*4;
4264 /* The formula is: TCS inputs + TCS outputs + TCS patch outputs. */
4265 unsigned patch_dw_size = vertex_data_dw_size*2 + patch_data_dw_size;
4266 unsigned lds_dwords = patch_dw_size;
4267
4268 /* The actual size is computed outside of the shader to reduce
4269 * the number of shader variants. */
4270 ctx->lds =
4271 LLVMAddGlobalInAddressSpace(gallivm->module,
4272 LLVMArrayType(i32, lds_dwords),
4273 "tess_lds",
4274 LOCAL_ADDR_SPACE);
4275 }
4276
4277 static void create_function(struct si_shader_context *ctx)
4278 {
4279 struct lp_build_tgsi_context *bld_base = &ctx->radeon_bld.soa.bld_base;
4280 struct gallivm_state *gallivm = bld_base->base.gallivm;
4281 struct si_shader *shader = ctx->shader;
4282 LLVMTypeRef params[SI_NUM_PARAMS + SI_NUM_VERTEX_BUFFERS], v3i32;
4283 LLVMTypeRef returns[16+32*4];
4284 unsigned i, last_array_pointer, last_sgpr, num_params, num_return_sgprs;
4285 unsigned num_returns = 0;
4286
4287 v3i32 = LLVMVectorType(ctx->i32, 3);
4288
4289 params[SI_PARAM_RW_BUFFERS] = const_array(ctx->v16i8, SI_NUM_RW_BUFFERS);
4290 params[SI_PARAM_CONST_BUFFERS] = const_array(ctx->v16i8, SI_NUM_CONST_BUFFERS);
4291 params[SI_PARAM_SAMPLERS] = const_array(ctx->v8i32, SI_NUM_SAMPLERS);
4292 params[SI_PARAM_IMAGES] = const_array(ctx->v8i32, SI_NUM_IMAGES);
4293 last_array_pointer = SI_PARAM_IMAGES;
4294
4295 switch (ctx->type) {
4296 case TGSI_PROCESSOR_VERTEX:
4297 params[SI_PARAM_VERTEX_BUFFERS] = const_array(ctx->v16i8, SI_NUM_VERTEX_BUFFERS);
4298 last_array_pointer = SI_PARAM_VERTEX_BUFFERS;
4299 params[SI_PARAM_BASE_VERTEX] = ctx->i32;
4300 params[SI_PARAM_START_INSTANCE] = ctx->i32;
4301 num_params = SI_PARAM_START_INSTANCE+1;
4302
4303 if (shader->key.vs.as_es) {
4304 params[ctx->param_es2gs_offset = num_params++] = ctx->i32;
4305 } else if (shader->key.vs.as_ls) {
4306 params[SI_PARAM_LS_OUT_LAYOUT] = ctx->i32;
4307 num_params = SI_PARAM_LS_OUT_LAYOUT+1;
4308 } else {
4309 if (ctx->is_gs_copy_shader) {
4310 last_array_pointer = SI_PARAM_CONST_BUFFERS;
4311 num_params = SI_PARAM_CONST_BUFFERS+1;
4312 } else {
4313 params[SI_PARAM_VS_STATE_BITS] = ctx->i32;
4314 num_params = SI_PARAM_VS_STATE_BITS+1;
4315 }
4316
4317 /* The locations of the other parameters are assigned dynamically. */
4318 declare_streamout_params(ctx, &shader->selector->so,
4319 params, ctx->i32, &num_params);
4320 }
4321
4322 last_sgpr = num_params-1;
4323
4324 /* VGPRs */
4325 params[ctx->param_vertex_id = num_params++] = ctx->i32;
4326 params[ctx->param_rel_auto_id = num_params++] = ctx->i32;
4327 params[ctx->param_vs_prim_id = num_params++] = ctx->i32;
4328 params[ctx->param_instance_id = num_params++] = ctx->i32;
4329
4330 if (!ctx->is_monolithic &&
4331 !ctx->is_gs_copy_shader) {
4332 /* Vertex load indices. */
4333 ctx->param_vertex_index0 = num_params;
4334
4335 for (i = 0; i < shader->selector->info.num_inputs; i++)
4336 params[num_params++] = ctx->i32;
4337
4338 /* PrimitiveID output. */
4339 if (!shader->key.vs.as_es && !shader->key.vs.as_ls)
4340 for (i = 0; i <= VS_EPILOG_PRIMID_LOC; i++)
4341 returns[num_returns++] = ctx->f32;
4342 }
4343 break;
4344
4345 case TGSI_PROCESSOR_TESS_CTRL:
4346 params[SI_PARAM_TCS_OUT_OFFSETS] = ctx->i32;
4347 params[SI_PARAM_TCS_OUT_LAYOUT] = ctx->i32;
4348 params[SI_PARAM_TCS_IN_LAYOUT] = ctx->i32;
4349 params[SI_PARAM_TESS_FACTOR_OFFSET] = ctx->i32;
4350 last_sgpr = SI_PARAM_TESS_FACTOR_OFFSET;
4351
4352 /* VGPRs */
4353 params[SI_PARAM_PATCH_ID] = ctx->i32;
4354 params[SI_PARAM_REL_IDS] = ctx->i32;
4355 num_params = SI_PARAM_REL_IDS+1;
4356
4357 if (!ctx->is_monolithic) {
4358 /* PARAM_TESS_FACTOR_OFFSET is after user SGPRs. */
4359 for (i = 0; i <= SI_TCS_NUM_USER_SGPR; i++)
4360 returns[num_returns++] = ctx->i32; /* SGPRs */
4361
4362 for (i = 0; i < 3; i++)
4363 returns[num_returns++] = ctx->f32; /* VGPRs */
4364 }
4365 break;
4366
4367 case TGSI_PROCESSOR_TESS_EVAL:
4368 params[SI_PARAM_TCS_OUT_OFFSETS] = ctx->i32;
4369 params[SI_PARAM_TCS_OUT_LAYOUT] = ctx->i32;
4370 num_params = SI_PARAM_TCS_OUT_LAYOUT+1;
4371
4372 if (shader->key.tes.as_es) {
4373 params[ctx->param_es2gs_offset = num_params++] = ctx->i32;
4374 } else {
4375 declare_streamout_params(ctx, &shader->selector->so,
4376 params, ctx->i32, &num_params);
4377 }
4378 last_sgpr = num_params - 1;
4379
4380 /* VGPRs */
4381 params[ctx->param_tes_u = num_params++] = ctx->f32;
4382 params[ctx->param_tes_v = num_params++] = ctx->f32;
4383 params[ctx->param_tes_rel_patch_id = num_params++] = ctx->i32;
4384 params[ctx->param_tes_patch_id = num_params++] = ctx->i32;
4385
4386 /* PrimitiveID output. */
4387 if (!ctx->is_monolithic && !shader->key.tes.as_es)
4388 for (i = 0; i <= VS_EPILOG_PRIMID_LOC; i++)
4389 returns[num_returns++] = ctx->f32;
4390 break;
4391
4392 case TGSI_PROCESSOR_GEOMETRY:
4393 params[SI_PARAM_GS2VS_OFFSET] = ctx->i32;
4394 params[SI_PARAM_GS_WAVE_ID] = ctx->i32;
4395 last_sgpr = SI_PARAM_GS_WAVE_ID;
4396
4397 /* VGPRs */
4398 params[SI_PARAM_VTX0_OFFSET] = ctx->i32;
4399 params[SI_PARAM_VTX1_OFFSET] = ctx->i32;
4400 params[SI_PARAM_PRIMITIVE_ID] = ctx->i32;
4401 params[SI_PARAM_VTX2_OFFSET] = ctx->i32;
4402 params[SI_PARAM_VTX3_OFFSET] = ctx->i32;
4403 params[SI_PARAM_VTX4_OFFSET] = ctx->i32;
4404 params[SI_PARAM_VTX5_OFFSET] = ctx->i32;
4405 params[SI_PARAM_GS_INSTANCE_ID] = ctx->i32;
4406 num_params = SI_PARAM_GS_INSTANCE_ID+1;
4407 break;
4408
4409 case TGSI_PROCESSOR_FRAGMENT:
4410 params[SI_PARAM_ALPHA_REF] = ctx->f32;
4411 params[SI_PARAM_PRIM_MASK] = ctx->i32;
4412 last_sgpr = SI_PARAM_PRIM_MASK;
4413 params[SI_PARAM_PERSP_SAMPLE] = ctx->v2i32;
4414 params[SI_PARAM_PERSP_CENTER] = ctx->v2i32;
4415 params[SI_PARAM_PERSP_CENTROID] = ctx->v2i32;
4416 params[SI_PARAM_PERSP_PULL_MODEL] = v3i32;
4417 params[SI_PARAM_LINEAR_SAMPLE] = ctx->v2i32;
4418 params[SI_PARAM_LINEAR_CENTER] = ctx->v2i32;
4419 params[SI_PARAM_LINEAR_CENTROID] = ctx->v2i32;
4420 params[SI_PARAM_LINE_STIPPLE_TEX] = ctx->f32;
4421 params[SI_PARAM_POS_X_FLOAT] = ctx->f32;
4422 params[SI_PARAM_POS_Y_FLOAT] = ctx->f32;
4423 params[SI_PARAM_POS_Z_FLOAT] = ctx->f32;
4424 params[SI_PARAM_POS_W_FLOAT] = ctx->f32;
4425 params[SI_PARAM_FRONT_FACE] = ctx->i32;
4426 params[SI_PARAM_ANCILLARY] = ctx->i32;
4427 params[SI_PARAM_SAMPLE_COVERAGE] = ctx->f32;
4428 params[SI_PARAM_POS_FIXED_PT] = ctx->i32;
4429 num_params = SI_PARAM_POS_FIXED_PT+1;
4430
4431 if (!ctx->is_monolithic) {
4432 /* Color inputs from the prolog. */
4433 if (shader->selector->info.colors_read) {
4434 unsigned num_color_elements =
4435 util_bitcount(shader->selector->info.colors_read);
4436
4437 assert(num_params + num_color_elements <= ARRAY_SIZE(params));
4438 for (i = 0; i < num_color_elements; i++)
4439 params[num_params++] = ctx->f32;
4440 }
4441
4442 /* Outputs for the epilog. */
4443 num_return_sgprs = SI_SGPR_ALPHA_REF + 1;
4444 num_returns =
4445 num_return_sgprs +
4446 util_bitcount(shader->selector->info.colors_written) * 4 +
4447 shader->selector->info.writes_z +
4448 shader->selector->info.writes_stencil +
4449 shader->selector->info.writes_samplemask +
4450 1 /* SampleMaskIn */;
4451
4452 num_returns = MAX2(num_returns,
4453 num_return_sgprs +
4454 PS_EPILOG_SAMPLEMASK_MIN_LOC + 1);
4455
4456 for (i = 0; i < num_return_sgprs; i++)
4457 returns[i] = ctx->i32;
4458 for (; i < num_returns; i++)
4459 returns[i] = ctx->f32;
4460 }
4461 break;
4462
4463 default:
4464 assert(0 && "unimplemented shader");
4465 return;
4466 }
4467
4468 assert(num_params <= Elements(params));
4469
4470 si_create_function(ctx, returns, num_returns, params,
4471 num_params, last_array_pointer, last_sgpr);
4472
4473 /* Reserve register locations for VGPR inputs the PS prolog may need. */
4474 if (ctx->type == TGSI_PROCESSOR_FRAGMENT &&
4475 !ctx->is_monolithic) {
4476 radeon_llvm_add_attribute(ctx->radeon_bld.main_fn,
4477 "InitialPSInputAddr",
4478 S_0286D0_PERSP_SAMPLE_ENA(1) |
4479 S_0286D0_PERSP_CENTER_ENA(1) |
4480 S_0286D0_PERSP_CENTROID_ENA(1) |
4481 S_0286D0_LINEAR_SAMPLE_ENA(1) |
4482 S_0286D0_LINEAR_CENTER_ENA(1) |
4483 S_0286D0_LINEAR_CENTROID_ENA(1) |
4484 S_0286D0_FRONT_FACE_ENA(1) |
4485 S_0286D0_POS_FIXED_PT_ENA(1));
4486 }
4487
4488 shader->info.num_input_sgprs = 0;
4489 shader->info.num_input_vgprs = 0;
4490
4491 for (i = 0; i <= last_sgpr; ++i)
4492 shader->info.num_input_sgprs += llvm_get_type_size(params[i]) / 4;
4493
4494 /* Unused fragment shader inputs are eliminated by the compiler,
4495 * so we don't know yet how many there will be.
4496 */
4497 if (ctx->type != TGSI_PROCESSOR_FRAGMENT)
4498 for (; i < num_params; ++i)
4499 shader->info.num_input_vgprs += llvm_get_type_size(params[i]) / 4;
4500
4501 if (bld_base->info &&
4502 (bld_base->info->opcode_count[TGSI_OPCODE_DDX] > 0 ||
4503 bld_base->info->opcode_count[TGSI_OPCODE_DDY] > 0 ||
4504 bld_base->info->opcode_count[TGSI_OPCODE_DDX_FINE] > 0 ||
4505 bld_base->info->opcode_count[TGSI_OPCODE_DDY_FINE] > 0 ||
4506 bld_base->info->opcode_count[TGSI_OPCODE_INTERP_OFFSET] > 0 ||
4507 bld_base->info->opcode_count[TGSI_OPCODE_INTERP_SAMPLE] > 0))
4508 ctx->lds =
4509 LLVMAddGlobalInAddressSpace(gallivm->module,
4510 LLVMArrayType(ctx->i32, 64),
4511 "ddxy_lds",
4512 LOCAL_ADDR_SPACE);
4513
4514 if ((ctx->type == TGSI_PROCESSOR_VERTEX && shader->key.vs.as_ls) ||
4515 ctx->type == TGSI_PROCESSOR_TESS_CTRL ||
4516 ctx->type == TGSI_PROCESSOR_TESS_EVAL)
4517 declare_tess_lds(ctx);
4518 }
4519
4520 static void preload_constants(struct si_shader_context *ctx)
4521 {
4522 struct lp_build_tgsi_context *bld_base = &ctx->radeon_bld.soa.bld_base;
4523 struct gallivm_state *gallivm = bld_base->base.gallivm;
4524 const struct tgsi_shader_info *info = bld_base->info;
4525 unsigned buf;
4526 LLVMValueRef ptr = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_CONST_BUFFERS);
4527
4528 for (buf = 0; buf < SI_NUM_CONST_BUFFERS; buf++) {
4529 unsigned i, num_const = info->const_file_max[buf] + 1;
4530
4531 if (num_const == 0)
4532 continue;
4533
4534 /* Allocate space for the constant values */
4535 ctx->constants[buf] = CALLOC(num_const * 4, sizeof(LLVMValueRef));
4536
4537 /* Load the resource descriptor */
4538 ctx->const_buffers[buf] =
4539 build_indexed_load_const(ctx, ptr, lp_build_const_int32(gallivm, buf));
4540
4541 /* Load the constants, we rely on the code sinking to do the rest */
4542 for (i = 0; i < num_const * 4; ++i) {
4543 ctx->constants[buf][i] =
4544 buffer_load_const(gallivm->builder,
4545 ctx->const_buffers[buf],
4546 lp_build_const_int32(gallivm, i * 4),
4547 ctx->f32);
4548 }
4549 }
4550 }
4551
4552 static void preload_samplers(struct si_shader_context *ctx)
4553 {
4554 struct lp_build_tgsi_context *bld_base = &ctx->radeon_bld.soa.bld_base;
4555 struct gallivm_state *gallivm = bld_base->base.gallivm;
4556 const struct tgsi_shader_info *info = bld_base->info;
4557 unsigned i, num_samplers = info->file_max[TGSI_FILE_SAMPLER] + 1;
4558 LLVMValueRef offset;
4559
4560 if (num_samplers == 0)
4561 return;
4562
4563 /* Load the resources and samplers, we rely on the code sinking to do the rest */
4564 for (i = 0; i < num_samplers; ++i) {
4565 /* Resource */
4566 offset = lp_build_const_int32(gallivm, i);
4567 ctx->sampler_views[i] =
4568 get_sampler_desc(ctx, offset, DESC_IMAGE);
4569
4570 /* FMASK resource */
4571 if (info->is_msaa_sampler[i])
4572 ctx->fmasks[i] =
4573 get_sampler_desc(ctx, offset, DESC_FMASK);
4574 else
4575 ctx->sampler_states[i] =
4576 get_sampler_desc(ctx, offset, DESC_SAMPLER);
4577 }
4578 }
4579
4580 static void preload_images(struct si_shader_context *ctx)
4581 {
4582 struct lp_build_tgsi_context *bld_base = &ctx->radeon_bld.soa.bld_base;
4583 struct gallivm_state *gallivm = bld_base->base.gallivm;
4584 unsigned num_images = bld_base->info->file_max[TGSI_FILE_IMAGE] + 1;
4585 LLVMValueRef res_ptr;
4586 unsigned i;
4587
4588 if (num_images == 0)
4589 return;
4590
4591 res_ptr = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_IMAGES);
4592
4593 for (i = 0; i < num_images; ++i) {
4594 /* Rely on LLVM to shrink the load for buffer resources. */
4595 ctx->images[i] =
4596 build_indexed_load_const(ctx, res_ptr,
4597 lp_build_const_int32(gallivm, i));
4598 }
4599 }
4600
4601 static void preload_streamout_buffers(struct si_shader_context *ctx)
4602 {
4603 struct lp_build_tgsi_context *bld_base = &ctx->radeon_bld.soa.bld_base;
4604 struct gallivm_state *gallivm = bld_base->base.gallivm;
4605 unsigned i;
4606
4607 /* Streamout can only be used if the shader is compiled as VS. */
4608 if (!ctx->shader->selector->so.num_outputs ||
4609 (ctx->type == TGSI_PROCESSOR_VERTEX &&
4610 (ctx->shader->key.vs.as_es ||
4611 ctx->shader->key.vs.as_ls)) ||
4612 (ctx->type == TGSI_PROCESSOR_TESS_EVAL &&
4613 ctx->shader->key.tes.as_es))
4614 return;
4615
4616 LLVMValueRef buf_ptr = LLVMGetParam(ctx->radeon_bld.main_fn,
4617 SI_PARAM_RW_BUFFERS);
4618
4619 /* Load the resources, we rely on the code sinking to do the rest */
4620 for (i = 0; i < 4; ++i) {
4621 if (ctx->shader->selector->so.stride[i]) {
4622 LLVMValueRef offset = lp_build_const_int32(gallivm,
4623 SI_SO_BUF_OFFSET + i);
4624
4625 ctx->so_buffers[i] = build_indexed_load_const(ctx, buf_ptr, offset);
4626 }
4627 }
4628 }
4629
4630 /**
4631 * Load ESGS and GSVS ring buffer resource descriptors and save the variables
4632 * for later use.
4633 */
4634 static void preload_ring_buffers(struct si_shader_context *ctx)
4635 {
4636 struct gallivm_state *gallivm =
4637 ctx->radeon_bld.soa.bld_base.base.gallivm;
4638
4639 LLVMValueRef buf_ptr = LLVMGetParam(ctx->radeon_bld.main_fn,
4640 SI_PARAM_RW_BUFFERS);
4641
4642 if ((ctx->type == TGSI_PROCESSOR_VERTEX &&
4643 ctx->shader->key.vs.as_es) ||
4644 (ctx->type == TGSI_PROCESSOR_TESS_EVAL &&
4645 ctx->shader->key.tes.as_es) ||
4646 ctx->type == TGSI_PROCESSOR_GEOMETRY) {
4647 LLVMValueRef offset = lp_build_const_int32(gallivm, SI_RING_ESGS);
4648
4649 ctx->esgs_ring =
4650 build_indexed_load_const(ctx, buf_ptr, offset);
4651 }
4652
4653 if (ctx->is_gs_copy_shader) {
4654 LLVMValueRef offset = lp_build_const_int32(gallivm, SI_RING_GSVS);
4655
4656 ctx->gsvs_ring[0] =
4657 build_indexed_load_const(ctx, buf_ptr, offset);
4658 }
4659 if (ctx->type == TGSI_PROCESSOR_GEOMETRY) {
4660 int i;
4661 for (i = 0; i < 4; i++) {
4662 LLVMValueRef offset = lp_build_const_int32(gallivm, SI_RING_GSVS + i);
4663
4664 ctx->gsvs_ring[i] =
4665 build_indexed_load_const(ctx, buf_ptr, offset);
4666 }
4667 }
4668 }
4669
4670 static void si_llvm_emit_polygon_stipple(struct si_shader_context *ctx,
4671 LLVMValueRef param_sampler_views,
4672 unsigned param_pos_fixed_pt)
4673 {
4674 struct lp_build_tgsi_context *bld_base =
4675 &ctx->radeon_bld.soa.bld_base;
4676 struct gallivm_state *gallivm = bld_base->base.gallivm;
4677 struct lp_build_emit_data result = {};
4678 struct tgsi_full_instruction inst = {};
4679 LLVMValueRef desc, sampler_index, address[2], pix;
4680
4681 /* Use the fixed-point gl_FragCoord input.
4682 * Since the stipple pattern is 32x32 and it repeats, just get 5 bits
4683 * per coordinate to get the repeating effect.
4684 */
4685 address[0] = unpack_param(ctx, param_pos_fixed_pt, 0, 5);
4686 address[1] = unpack_param(ctx, param_pos_fixed_pt, 16, 5);
4687
4688 /* Load the sampler view descriptor. */
4689 sampler_index = lp_build_const_int32(gallivm, SI_POLY_STIPPLE_SAMPLER);
4690 desc = get_sampler_desc_custom(ctx, param_sampler_views,
4691 sampler_index, DESC_IMAGE);
4692
4693 /* Load the texel. */
4694 inst.Instruction.Opcode = TGSI_OPCODE_TXF;
4695 inst.Texture.Texture = TGSI_TEXTURE_2D_MSAA; /* = use load, not load_mip */
4696 result.inst = &inst;
4697 set_tex_fetch_args(ctx, &result, TGSI_OPCODE_TXF,
4698 inst.Texture.Texture,
4699 desc, NULL, address, ARRAY_SIZE(address), 0xf);
4700 build_tex_intrinsic(&tex_action, bld_base, &result);
4701
4702 /* Kill the thread accordingly. */
4703 pix = LLVMBuildExtractElement(gallivm->builder, result.output[0],
4704 lp_build_const_int32(gallivm, 3), "");
4705 pix = bitcast(bld_base, TGSI_TYPE_FLOAT, pix);
4706 pix = LLVMBuildFNeg(gallivm->builder, pix, "");
4707
4708 lp_build_intrinsic(gallivm->builder, "llvm.AMDGPU.kill",
4709 LLVMVoidTypeInContext(gallivm->context),
4710 &pix, 1, 0);
4711 }
4712
4713 void si_shader_binary_read_config(struct radeon_shader_binary *binary,
4714 struct si_shader_config *conf,
4715 unsigned symbol_offset)
4716 {
4717 unsigned i;
4718 const unsigned char *config =
4719 radeon_shader_binary_config_start(binary, symbol_offset);
4720
4721 /* XXX: We may be able to emit some of these values directly rather than
4722 * extracting fields to be emitted later.
4723 */
4724
4725 for (i = 0; i < binary->config_size_per_symbol; i+= 8) {
4726 unsigned reg = util_le32_to_cpu(*(uint32_t*)(config + i));
4727 unsigned value = util_le32_to_cpu(*(uint32_t*)(config + i + 4));
4728 switch (reg) {
4729 case R_00B028_SPI_SHADER_PGM_RSRC1_PS:
4730 case R_00B128_SPI_SHADER_PGM_RSRC1_VS:
4731 case R_00B228_SPI_SHADER_PGM_RSRC1_GS:
4732 case R_00B848_COMPUTE_PGM_RSRC1:
4733 conf->num_sgprs = MAX2(conf->num_sgprs, (G_00B028_SGPRS(value) + 1) * 8);
4734 conf->num_vgprs = MAX2(conf->num_vgprs, (G_00B028_VGPRS(value) + 1) * 4);
4735 conf->float_mode = G_00B028_FLOAT_MODE(value);
4736 conf->rsrc1 = value;
4737 break;
4738 case R_00B02C_SPI_SHADER_PGM_RSRC2_PS:
4739 conf->lds_size = MAX2(conf->lds_size, G_00B02C_EXTRA_LDS_SIZE(value));
4740 break;
4741 case R_00B84C_COMPUTE_PGM_RSRC2:
4742 conf->lds_size = MAX2(conf->lds_size, G_00B84C_LDS_SIZE(value));
4743 conf->rsrc2 = value;
4744 break;
4745 case R_0286CC_SPI_PS_INPUT_ENA:
4746 conf->spi_ps_input_ena = value;
4747 break;
4748 case R_0286D0_SPI_PS_INPUT_ADDR:
4749 conf->spi_ps_input_addr = value;
4750 break;
4751 case R_0286E8_SPI_TMPRING_SIZE:
4752 case R_00B860_COMPUTE_TMPRING_SIZE:
4753 /* WAVESIZE is in units of 256 dwords. */
4754 conf->scratch_bytes_per_wave =
4755 G_00B860_WAVESIZE(value) * 256 * 4 * 1;
4756 break;
4757 default:
4758 {
4759 static bool printed;
4760
4761 if (!printed) {
4762 fprintf(stderr, "Warning: LLVM emitted unknown "
4763 "config register: 0x%x\n", reg);
4764 printed = true;
4765 }
4766 }
4767 break;
4768 }
4769
4770 if (!conf->spi_ps_input_addr)
4771 conf->spi_ps_input_addr = conf->spi_ps_input_ena;
4772 }
4773 }
4774
4775 void si_shader_apply_scratch_relocs(struct si_context *sctx,
4776 struct si_shader *shader,
4777 uint64_t scratch_va)
4778 {
4779 unsigned i;
4780 uint32_t scratch_rsrc_dword0 = scratch_va;
4781 uint32_t scratch_rsrc_dword1 =
4782 S_008F04_BASE_ADDRESS_HI(scratch_va >> 32)
4783 | S_008F04_STRIDE(shader->config.scratch_bytes_per_wave / 64);
4784
4785 for (i = 0 ; i < shader->binary.reloc_count; i++) {
4786 const struct radeon_shader_reloc *reloc =
4787 &shader->binary.relocs[i];
4788 if (!strcmp(scratch_rsrc_dword0_symbol, reloc->name)) {
4789 util_memcpy_cpu_to_le32(shader->binary.code + reloc->offset,
4790 &scratch_rsrc_dword0, 4);
4791 } else if (!strcmp(scratch_rsrc_dword1_symbol, reloc->name)) {
4792 util_memcpy_cpu_to_le32(shader->binary.code + reloc->offset,
4793 &scratch_rsrc_dword1, 4);
4794 }
4795 }
4796 }
4797
4798 static unsigned si_get_shader_binary_size(struct si_shader *shader)
4799 {
4800 unsigned size = shader->binary.code_size;
4801
4802 if (shader->prolog)
4803 size += shader->prolog->binary.code_size;
4804 if (shader->epilog)
4805 size += shader->epilog->binary.code_size;
4806 return size;
4807 }
4808
4809 int si_shader_binary_upload(struct si_screen *sscreen, struct si_shader *shader)
4810 {
4811 const struct radeon_shader_binary *prolog =
4812 shader->prolog ? &shader->prolog->binary : NULL;
4813 const struct radeon_shader_binary *epilog =
4814 shader->epilog ? &shader->epilog->binary : NULL;
4815 const struct radeon_shader_binary *mainb = &shader->binary;
4816 unsigned bo_size = si_get_shader_binary_size(shader) +
4817 (!epilog ? mainb->rodata_size : 0);
4818 unsigned char *ptr;
4819
4820 assert(!prolog || !prolog->rodata_size);
4821 assert((!prolog && !epilog) || !mainb->rodata_size);
4822 assert(!epilog || !epilog->rodata_size);
4823
4824 r600_resource_reference(&shader->bo, NULL);
4825 shader->bo = si_resource_create_custom(&sscreen->b.b,
4826 PIPE_USAGE_IMMUTABLE,
4827 bo_size);
4828 if (!shader->bo)
4829 return -ENOMEM;
4830
4831 /* Upload. */
4832 ptr = sscreen->b.ws->buffer_map(shader->bo->buf, NULL,
4833 PIPE_TRANSFER_READ_WRITE);
4834
4835 if (prolog) {
4836 util_memcpy_cpu_to_le32(ptr, prolog->code, prolog->code_size);
4837 ptr += prolog->code_size;
4838 }
4839
4840 util_memcpy_cpu_to_le32(ptr, mainb->code, mainb->code_size);
4841 ptr += mainb->code_size;
4842
4843 if (epilog)
4844 util_memcpy_cpu_to_le32(ptr, epilog->code, epilog->code_size);
4845 else if (mainb->rodata_size > 0)
4846 util_memcpy_cpu_to_le32(ptr, mainb->rodata, mainb->rodata_size);
4847
4848 sscreen->b.ws->buffer_unmap(shader->bo->buf);
4849 return 0;
4850 }
4851
4852 static void si_shader_dump_disassembly(const struct radeon_shader_binary *binary,
4853 struct pipe_debug_callback *debug,
4854 const char *name, FILE *file)
4855 {
4856 char *line, *p;
4857 unsigned i, count;
4858
4859 if (binary->disasm_string) {
4860 fprintf(file, "Shader %s disassembly:\n", name);
4861 fprintf(file, "%s", binary->disasm_string);
4862
4863 if (debug && debug->debug_message) {
4864 /* Very long debug messages are cut off, so send the
4865 * disassembly one line at a time. This causes more
4866 * overhead, but on the plus side it simplifies
4867 * parsing of resulting logs.
4868 */
4869 pipe_debug_message(debug, SHADER_INFO,
4870 "Shader Disassembly Begin");
4871
4872 line = binary->disasm_string;
4873 while (*line) {
4874 p = strchrnul(line, '\n');
4875 count = p - line;
4876
4877 if (count) {
4878 pipe_debug_message(debug, SHADER_INFO,
4879 "%.*s", count, line);
4880 }
4881
4882 if (!*p)
4883 break;
4884 line = p + 1;
4885 }
4886
4887 pipe_debug_message(debug, SHADER_INFO,
4888 "Shader Disassembly End");
4889 }
4890 } else {
4891 fprintf(file, "Shader %s binary:\n", name);
4892 for (i = 0; i < binary->code_size; i += 4) {
4893 fprintf(file, "@0x%x: %02x%02x%02x%02x\n", i,
4894 binary->code[i + 3], binary->code[i + 2],
4895 binary->code[i + 1], binary->code[i]);
4896 }
4897 }
4898 }
4899
4900 static void si_shader_dump_stats(struct si_screen *sscreen,
4901 struct si_shader_config *conf,
4902 unsigned num_inputs,
4903 unsigned code_size,
4904 struct pipe_debug_callback *debug,
4905 unsigned processor,
4906 FILE *file)
4907 {
4908 unsigned lds_increment = sscreen->b.chip_class >= CIK ? 512 : 256;
4909 unsigned lds_per_wave = 0;
4910 unsigned max_simd_waves = 10;
4911
4912 /* Compute LDS usage for PS. */
4913 if (processor == TGSI_PROCESSOR_FRAGMENT) {
4914 /* The minimum usage per wave is (num_inputs * 36). The maximum
4915 * usage is (num_inputs * 36 * 16).
4916 * We can get anything in between and it varies between waves.
4917 *
4918 * Other stages don't know the size at compile time or don't
4919 * allocate LDS per wave, but instead they do it per thread group.
4920 */
4921 lds_per_wave = conf->lds_size * lds_increment +
4922 align(num_inputs * 36, lds_increment);
4923 }
4924
4925 /* Compute the per-SIMD wave counts. */
4926 if (conf->num_sgprs) {
4927 if (sscreen->b.chip_class >= VI)
4928 max_simd_waves = MIN2(max_simd_waves, 800 / conf->num_sgprs);
4929 else
4930 max_simd_waves = MIN2(max_simd_waves, 512 / conf->num_sgprs);
4931 }
4932
4933 if (conf->num_vgprs)
4934 max_simd_waves = MIN2(max_simd_waves, 256 / conf->num_vgprs);
4935
4936 /* LDS is 64KB per CU (4 SIMDs), divided into 16KB blocks per SIMD
4937 * that PS can use.
4938 */
4939 if (lds_per_wave)
4940 max_simd_waves = MIN2(max_simd_waves, 16384 / lds_per_wave);
4941
4942 if (file != stderr ||
4943 r600_can_dump_shader(&sscreen->b, processor)) {
4944 if (processor == TGSI_PROCESSOR_FRAGMENT) {
4945 fprintf(file, "*** SHADER CONFIG ***\n"
4946 "SPI_PS_INPUT_ADDR = 0x%04x\n"
4947 "SPI_PS_INPUT_ENA = 0x%04x\n",
4948 conf->spi_ps_input_addr, conf->spi_ps_input_ena);
4949 }
4950
4951 fprintf(file, "*** SHADER STATS ***\n"
4952 "SGPRS: %d\n"
4953 "VGPRS: %d\n"
4954 "Code Size: %d bytes\n"
4955 "LDS: %d blocks\n"
4956 "Scratch: %d bytes per wave\n"
4957 "Max Waves: %d\n"
4958 "********************\n",
4959 conf->num_sgprs, conf->num_vgprs, code_size,
4960 conf->lds_size, conf->scratch_bytes_per_wave,
4961 max_simd_waves);
4962 }
4963
4964 pipe_debug_message(debug, SHADER_INFO,
4965 "Shader Stats: SGPRS: %d VGPRS: %d Code Size: %d "
4966 "LDS: %d Scratch: %d Max Waves: %d",
4967 conf->num_sgprs, conf->num_vgprs, code_size,
4968 conf->lds_size, conf->scratch_bytes_per_wave,
4969 max_simd_waves);
4970 }
4971
4972 static const char *si_get_shader_name(struct si_shader *shader,
4973 unsigned processor)
4974 {
4975 switch (processor) {
4976 case TGSI_PROCESSOR_VERTEX:
4977 if (shader->key.vs.as_es)
4978 return "Vertex Shader as ES";
4979 else if (shader->key.vs.as_ls)
4980 return "Vertex Shader as LS";
4981 else
4982 return "Vertex Shader as VS";
4983 case TGSI_PROCESSOR_TESS_CTRL:
4984 return "Tessellation Control Shader";
4985 case TGSI_PROCESSOR_TESS_EVAL:
4986 if (shader->key.tes.as_es)
4987 return "Tessellation Evaluation Shader as ES";
4988 else
4989 return "Tessellation Evaluation Shader as VS";
4990 case TGSI_PROCESSOR_GEOMETRY:
4991 if (shader->gs_copy_shader == NULL)
4992 return "GS Copy Shader as VS";
4993 else
4994 return "Geometry Shader";
4995 case TGSI_PROCESSOR_FRAGMENT:
4996 return "Pixel Shader";
4997 case TGSI_PROCESSOR_COMPUTE:
4998 return "Compute Shader";
4999 default:
5000 return "Unknown Shader";
5001 }
5002 }
5003
5004 void si_shader_dump(struct si_screen *sscreen, struct si_shader *shader,
5005 struct pipe_debug_callback *debug, unsigned processor,
5006 FILE *file)
5007 {
5008 if (file != stderr ||
5009 (r600_can_dump_shader(&sscreen->b, processor) &&
5010 !(sscreen->b.debug_flags & DBG_NO_ASM))) {
5011 fprintf(file, "\n%s:\n", si_get_shader_name(shader, processor));
5012
5013 if (shader->prolog)
5014 si_shader_dump_disassembly(&shader->prolog->binary,
5015 debug, "prolog", file);
5016
5017 si_shader_dump_disassembly(&shader->binary, debug, "main", file);
5018
5019 if (shader->epilog)
5020 si_shader_dump_disassembly(&shader->epilog->binary,
5021 debug, "epilog", file);
5022 fprintf(file, "\n");
5023 }
5024
5025 si_shader_dump_stats(sscreen, &shader->config,
5026 shader->selector ? shader->selector->info.num_inputs : 0,
5027 si_get_shader_binary_size(shader), debug, processor,
5028 file);
5029 }
5030
5031 int si_compile_llvm(struct si_screen *sscreen,
5032 struct radeon_shader_binary *binary,
5033 struct si_shader_config *conf,
5034 LLVMTargetMachineRef tm,
5035 LLVMModuleRef mod,
5036 struct pipe_debug_callback *debug,
5037 unsigned processor,
5038 const char *name)
5039 {
5040 int r = 0;
5041 unsigned count = p_atomic_inc_return(&sscreen->b.num_compilations);
5042
5043 if (r600_can_dump_shader(&sscreen->b, processor)) {
5044 fprintf(stderr, "radeonsi: Compiling shader %d\n", count);
5045
5046 if (!(sscreen->b.debug_flags & (DBG_NO_IR | DBG_PREOPT_IR))) {
5047 fprintf(stderr, "%s LLVM IR:\n\n", name);
5048 LLVMDumpModule(mod);
5049 fprintf(stderr, "\n");
5050 }
5051 }
5052
5053 if (!si_replace_shader(count, binary)) {
5054 r = radeon_llvm_compile(mod, binary,
5055 r600_get_llvm_processor_name(sscreen->b.family), tm,
5056 debug);
5057 if (r)
5058 return r;
5059 }
5060
5061 si_shader_binary_read_config(binary, conf, 0);
5062
5063 /* Enable 64-bit and 16-bit denormals, because there is no performance
5064 * cost.
5065 *
5066 * If denormals are enabled, all floating-point output modifiers are
5067 * ignored.
5068 *
5069 * Don't enable denormals for 32-bit floats, because:
5070 * - Floating-point output modifiers would be ignored by the hw.
5071 * - Some opcodes don't support denormals, such as v_mad_f32. We would
5072 * have to stop using those.
5073 * - SI & CI would be very slow.
5074 */
5075 conf->float_mode |= V_00B028_FP_64_DENORMS;
5076
5077 FREE(binary->config);
5078 FREE(binary->global_symbol_offsets);
5079 binary->config = NULL;
5080 binary->global_symbol_offsets = NULL;
5081
5082 /* Some shaders can't have rodata because their binaries can be
5083 * concatenated.
5084 */
5085 if (binary->rodata_size &&
5086 (processor == TGSI_PROCESSOR_VERTEX ||
5087 processor == TGSI_PROCESSOR_TESS_CTRL ||
5088 processor == TGSI_PROCESSOR_TESS_EVAL ||
5089 processor == TGSI_PROCESSOR_FRAGMENT)) {
5090 fprintf(stderr, "radeonsi: The shader can't have rodata.");
5091 return -EINVAL;
5092 }
5093
5094 return r;
5095 }
5096
5097 /* Generate code for the hardware VS shader stage to go with a geometry shader */
5098 static int si_generate_gs_copy_shader(struct si_screen *sscreen,
5099 struct si_shader_context *ctx,
5100 struct si_shader *gs,
5101 struct pipe_debug_callback *debug)
5102 {
5103 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
5104 struct lp_build_tgsi_context *bld_base = &ctx->radeon_bld.soa.bld_base;
5105 struct lp_build_context *uint = &bld_base->uint_bld;
5106 struct si_shader_output_values *outputs;
5107 struct tgsi_shader_info *gsinfo = &gs->selector->info;
5108 LLVMValueRef args[9];
5109 int i, r;
5110
5111 outputs = MALLOC(gsinfo->num_outputs * sizeof(outputs[0]));
5112
5113 si_init_shader_ctx(ctx, sscreen, ctx->shader, ctx->tm);
5114 ctx->type = TGSI_PROCESSOR_VERTEX;
5115 ctx->is_gs_copy_shader = true;
5116
5117 create_meta_data(ctx);
5118 create_function(ctx);
5119 preload_streamout_buffers(ctx);
5120 preload_ring_buffers(ctx);
5121
5122 args[0] = ctx->gsvs_ring[0];
5123 args[1] = lp_build_mul_imm(uint,
5124 LLVMGetParam(ctx->radeon_bld.main_fn,
5125 ctx->param_vertex_id),
5126 4);
5127 args[3] = uint->zero;
5128 args[4] = uint->one; /* OFFEN */
5129 args[5] = uint->zero; /* IDXEN */
5130 args[6] = uint->one; /* GLC */
5131 args[7] = uint->one; /* SLC */
5132 args[8] = uint->zero; /* TFE */
5133
5134 /* Fetch vertex data from GSVS ring */
5135 for (i = 0; i < gsinfo->num_outputs; ++i) {
5136 unsigned chan;
5137
5138 outputs[i].name = gsinfo->output_semantic_name[i];
5139 outputs[i].sid = gsinfo->output_semantic_index[i];
5140
5141 for (chan = 0; chan < 4; chan++) {
5142 args[2] = lp_build_const_int32(gallivm,
5143 (i * 4 + chan) *
5144 gs->selector->gs_max_out_vertices * 16 * 4);
5145
5146 outputs[i].values[chan] =
5147 LLVMBuildBitCast(gallivm->builder,
5148 lp_build_intrinsic(gallivm->builder,
5149 "llvm.SI.buffer.load.dword.i32.i32",
5150 ctx->i32, args, 9,
5151 LLVMReadOnlyAttribute | LLVMNoUnwindAttribute),
5152 ctx->f32, "");
5153 }
5154 }
5155
5156 si_llvm_export_vs(bld_base, outputs, gsinfo->num_outputs);
5157
5158 LLVMBuildRet(gallivm->builder, ctx->return_value);
5159
5160 /* Dump LLVM IR before any optimization passes */
5161 if (sscreen->b.debug_flags & DBG_PREOPT_IR &&
5162 r600_can_dump_shader(&sscreen->b, TGSI_PROCESSOR_GEOMETRY))
5163 LLVMDumpModule(bld_base->base.gallivm->module);
5164
5165 radeon_llvm_finalize_module(&ctx->radeon_bld);
5166
5167 r = si_compile_llvm(sscreen, &ctx->shader->binary,
5168 &ctx->shader->config, ctx->tm,
5169 bld_base->base.gallivm->module,
5170 debug, TGSI_PROCESSOR_GEOMETRY,
5171 "GS Copy Shader");
5172 if (!r) {
5173 if (r600_can_dump_shader(&sscreen->b, TGSI_PROCESSOR_GEOMETRY))
5174 fprintf(stderr, "GS Copy Shader:\n");
5175 si_shader_dump(sscreen, ctx->shader, debug,
5176 TGSI_PROCESSOR_GEOMETRY, stderr);
5177 r = si_shader_binary_upload(sscreen, ctx->shader);
5178 }
5179
5180 radeon_llvm_dispose(&ctx->radeon_bld);
5181
5182 FREE(outputs);
5183 return r;
5184 }
5185
5186 void si_dump_shader_key(unsigned shader, union si_shader_key *key, FILE *f)
5187 {
5188 int i;
5189
5190 fprintf(f, "SHADER KEY\n");
5191
5192 switch (shader) {
5193 case PIPE_SHADER_VERTEX:
5194 fprintf(f, " instance_divisors = {");
5195 for (i = 0; i < Elements(key->vs.prolog.instance_divisors); i++)
5196 fprintf(f, !i ? "%u" : ", %u",
5197 key->vs.prolog.instance_divisors[i]);
5198 fprintf(f, "}\n");
5199 fprintf(f, " as_es = %u\n", key->vs.as_es);
5200 fprintf(f, " as_ls = %u\n", key->vs.as_ls);
5201 fprintf(f, " export_prim_id = %u\n", key->vs.epilog.export_prim_id);
5202 break;
5203
5204 case PIPE_SHADER_TESS_CTRL:
5205 fprintf(f, " prim_mode = %u\n", key->tcs.epilog.prim_mode);
5206 break;
5207
5208 case PIPE_SHADER_TESS_EVAL:
5209 fprintf(f, " as_es = %u\n", key->tes.as_es);
5210 fprintf(f, " export_prim_id = %u\n", key->tes.epilog.export_prim_id);
5211 break;
5212
5213 case PIPE_SHADER_GEOMETRY:
5214 break;
5215
5216 case PIPE_SHADER_FRAGMENT:
5217 fprintf(f, " prolog.color_two_side = %u\n", key->ps.prolog.color_two_side);
5218 fprintf(f, " prolog.poly_stipple = %u\n", key->ps.prolog.poly_stipple);
5219 fprintf(f, " prolog.force_persample_interp = %u\n", key->ps.prolog.force_persample_interp);
5220 fprintf(f, " epilog.spi_shader_col_format = 0x%x\n", key->ps.epilog.spi_shader_col_format);
5221 fprintf(f, " epilog.color_is_int8 = 0x%X\n", key->ps.epilog.color_is_int8);
5222 fprintf(f, " epilog.last_cbuf = %u\n", key->ps.epilog.last_cbuf);
5223 fprintf(f, " epilog.alpha_func = %u\n", key->ps.epilog.alpha_func);
5224 fprintf(f, " epilog.alpha_to_one = %u\n", key->ps.epilog.alpha_to_one);
5225 fprintf(f, " epilog.poly_line_smoothing = %u\n", key->ps.epilog.poly_line_smoothing);
5226 fprintf(f, " epilog.clamp_color = %u\n", key->ps.epilog.clamp_color);
5227 break;
5228
5229 default:
5230 assert(0);
5231 }
5232 }
5233
5234 static void si_init_shader_ctx(struct si_shader_context *ctx,
5235 struct si_screen *sscreen,
5236 struct si_shader *shader,
5237 LLVMTargetMachineRef tm)
5238 {
5239 struct lp_build_tgsi_context *bld_base;
5240 struct lp_build_tgsi_action tmpl;
5241
5242 memset(ctx, 0, sizeof(*ctx));
5243 radeon_llvm_context_init(&ctx->radeon_bld, "amdgcn--");
5244 ctx->tm = tm;
5245 ctx->screen = sscreen;
5246 if (shader && shader->selector)
5247 ctx->type = shader->selector->info.processor;
5248 else
5249 ctx->type = -1;
5250 ctx->shader = shader;
5251
5252 ctx->voidt = LLVMVoidTypeInContext(ctx->radeon_bld.gallivm.context);
5253 ctx->i1 = LLVMInt1TypeInContext(ctx->radeon_bld.gallivm.context);
5254 ctx->i8 = LLVMInt8TypeInContext(ctx->radeon_bld.gallivm.context);
5255 ctx->i32 = LLVMInt32TypeInContext(ctx->radeon_bld.gallivm.context);
5256 ctx->i64 = LLVMInt64TypeInContext(ctx->radeon_bld.gallivm.context);
5257 ctx->i128 = LLVMIntTypeInContext(ctx->radeon_bld.gallivm.context, 128);
5258 ctx->f32 = LLVMFloatTypeInContext(ctx->radeon_bld.gallivm.context);
5259 ctx->v16i8 = LLVMVectorType(ctx->i8, 16);
5260 ctx->v2i32 = LLVMVectorType(ctx->i32, 2);
5261 ctx->v4i32 = LLVMVectorType(ctx->i32, 4);
5262 ctx->v4f32 = LLVMVectorType(ctx->f32, 4);
5263 ctx->v8i32 = LLVMVectorType(ctx->i32, 8);
5264
5265 bld_base = &ctx->radeon_bld.soa.bld_base;
5266 if (shader && shader->selector)
5267 bld_base->info = &shader->selector->info;
5268 bld_base->emit_fetch_funcs[TGSI_FILE_CONSTANT] = fetch_constant;
5269
5270 bld_base->op_actions[TGSI_OPCODE_INTERP_CENTROID] = interp_action;
5271 bld_base->op_actions[TGSI_OPCODE_INTERP_SAMPLE] = interp_action;
5272 bld_base->op_actions[TGSI_OPCODE_INTERP_OFFSET] = interp_action;
5273
5274 bld_base->op_actions[TGSI_OPCODE_TEX] = tex_action;
5275 bld_base->op_actions[TGSI_OPCODE_TEX2] = tex_action;
5276 bld_base->op_actions[TGSI_OPCODE_TXB] = tex_action;
5277 bld_base->op_actions[TGSI_OPCODE_TXB2] = tex_action;
5278 bld_base->op_actions[TGSI_OPCODE_TXD] = tex_action;
5279 bld_base->op_actions[TGSI_OPCODE_TXF] = tex_action;
5280 bld_base->op_actions[TGSI_OPCODE_TXL] = tex_action;
5281 bld_base->op_actions[TGSI_OPCODE_TXL2] = tex_action;
5282 bld_base->op_actions[TGSI_OPCODE_TXP] = tex_action;
5283 bld_base->op_actions[TGSI_OPCODE_TXQ] = tex_action;
5284 bld_base->op_actions[TGSI_OPCODE_TG4] = tex_action;
5285 bld_base->op_actions[TGSI_OPCODE_LODQ] = tex_action;
5286 bld_base->op_actions[TGSI_OPCODE_TXQS].emit = si_llvm_emit_txqs;
5287
5288 bld_base->op_actions[TGSI_OPCODE_LOAD].fetch_args = load_fetch_args;
5289 bld_base->op_actions[TGSI_OPCODE_LOAD].emit = load_emit;
5290 bld_base->op_actions[TGSI_OPCODE_STORE].fetch_args = store_fetch_args;
5291 bld_base->op_actions[TGSI_OPCODE_STORE].emit = store_emit;
5292 bld_base->op_actions[TGSI_OPCODE_RESQ].fetch_args = resq_fetch_args;
5293 bld_base->op_actions[TGSI_OPCODE_RESQ].emit = resq_emit;
5294
5295 tmpl.fetch_args = atomic_fetch_args;
5296 tmpl.emit = atomic_emit;
5297 bld_base->op_actions[TGSI_OPCODE_ATOMUADD] = tmpl;
5298 bld_base->op_actions[TGSI_OPCODE_ATOMUADD].intr_name = "add";
5299 bld_base->op_actions[TGSI_OPCODE_ATOMXCHG] = tmpl;
5300 bld_base->op_actions[TGSI_OPCODE_ATOMXCHG].intr_name = "swap";
5301 bld_base->op_actions[TGSI_OPCODE_ATOMCAS] = tmpl;
5302 bld_base->op_actions[TGSI_OPCODE_ATOMCAS].intr_name = "cmpswap";
5303 bld_base->op_actions[TGSI_OPCODE_ATOMAND] = tmpl;
5304 bld_base->op_actions[TGSI_OPCODE_ATOMAND].intr_name = "and";
5305 bld_base->op_actions[TGSI_OPCODE_ATOMOR] = tmpl;
5306 bld_base->op_actions[TGSI_OPCODE_ATOMOR].intr_name = "or";
5307 bld_base->op_actions[TGSI_OPCODE_ATOMXOR] = tmpl;
5308 bld_base->op_actions[TGSI_OPCODE_ATOMXOR].intr_name = "xor";
5309 bld_base->op_actions[TGSI_OPCODE_ATOMUMIN] = tmpl;
5310 bld_base->op_actions[TGSI_OPCODE_ATOMUMIN].intr_name = "umin";
5311 bld_base->op_actions[TGSI_OPCODE_ATOMUMAX] = tmpl;
5312 bld_base->op_actions[TGSI_OPCODE_ATOMUMAX].intr_name = "umax";
5313 bld_base->op_actions[TGSI_OPCODE_ATOMIMIN] = tmpl;
5314 bld_base->op_actions[TGSI_OPCODE_ATOMIMIN].intr_name = "smin";
5315 bld_base->op_actions[TGSI_OPCODE_ATOMIMAX] = tmpl;
5316 bld_base->op_actions[TGSI_OPCODE_ATOMIMAX].intr_name = "smax";
5317
5318 bld_base->op_actions[TGSI_OPCODE_DDX].emit = si_llvm_emit_ddxy;
5319 bld_base->op_actions[TGSI_OPCODE_DDY].emit = si_llvm_emit_ddxy;
5320 bld_base->op_actions[TGSI_OPCODE_DDX_FINE].emit = si_llvm_emit_ddxy;
5321 bld_base->op_actions[TGSI_OPCODE_DDY_FINE].emit = si_llvm_emit_ddxy;
5322
5323 bld_base->op_actions[TGSI_OPCODE_EMIT].emit = si_llvm_emit_vertex;
5324 bld_base->op_actions[TGSI_OPCODE_ENDPRIM].emit = si_llvm_emit_primitive;
5325 bld_base->op_actions[TGSI_OPCODE_BARRIER].emit = si_llvm_emit_barrier;
5326
5327 bld_base->op_actions[TGSI_OPCODE_MAX].emit = build_tgsi_intrinsic_nomem;
5328 bld_base->op_actions[TGSI_OPCODE_MAX].intr_name = "llvm.maxnum.f32";
5329 bld_base->op_actions[TGSI_OPCODE_MIN].emit = build_tgsi_intrinsic_nomem;
5330 bld_base->op_actions[TGSI_OPCODE_MIN].intr_name = "llvm.minnum.f32";
5331 }
5332
5333 int si_compile_tgsi_shader(struct si_screen *sscreen,
5334 LLVMTargetMachineRef tm,
5335 struct si_shader *shader,
5336 bool is_monolithic,
5337 struct pipe_debug_callback *debug)
5338 {
5339 struct si_shader_selector *sel = shader->selector;
5340 struct si_shader_context ctx;
5341 struct lp_build_tgsi_context *bld_base;
5342 LLVMModuleRef mod;
5343 int r = 0;
5344
5345 /* Dump TGSI code before doing TGSI->LLVM conversion in case the
5346 * conversion fails. */
5347 if (r600_can_dump_shader(&sscreen->b, sel->info.processor) &&
5348 !(sscreen->b.debug_flags & DBG_NO_TGSI)) {
5349 si_dump_shader_key(sel->type, &shader->key, stderr);
5350 tgsi_dump(sel->tokens, 0);
5351 si_dump_streamout(&sel->so);
5352 }
5353
5354 si_init_shader_ctx(&ctx, sscreen, shader, tm);
5355 ctx.is_monolithic = is_monolithic;
5356
5357 shader->info.uses_instanceid = sel->info.uses_instanceid;
5358
5359 bld_base = &ctx.radeon_bld.soa.bld_base;
5360 ctx.radeon_bld.load_system_value = declare_system_value;
5361
5362 switch (ctx.type) {
5363 case TGSI_PROCESSOR_VERTEX:
5364 ctx.radeon_bld.load_input = declare_input_vs;
5365 if (shader->key.vs.as_ls)
5366 bld_base->emit_epilogue = si_llvm_emit_ls_epilogue;
5367 else if (shader->key.vs.as_es)
5368 bld_base->emit_epilogue = si_llvm_emit_es_epilogue;
5369 else
5370 bld_base->emit_epilogue = si_llvm_emit_vs_epilogue;
5371 break;
5372 case TGSI_PROCESSOR_TESS_CTRL:
5373 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_tcs;
5374 bld_base->emit_fetch_funcs[TGSI_FILE_OUTPUT] = fetch_output_tcs;
5375 bld_base->emit_store = store_output_tcs;
5376 bld_base->emit_epilogue = si_llvm_emit_tcs_epilogue;
5377 break;
5378 case TGSI_PROCESSOR_TESS_EVAL:
5379 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_tes;
5380 if (shader->key.tes.as_es)
5381 bld_base->emit_epilogue = si_llvm_emit_es_epilogue;
5382 else
5383 bld_base->emit_epilogue = si_llvm_emit_vs_epilogue;
5384 break;
5385 case TGSI_PROCESSOR_GEOMETRY:
5386 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_gs;
5387 bld_base->emit_epilogue = si_llvm_emit_gs_epilogue;
5388 break;
5389 case TGSI_PROCESSOR_FRAGMENT:
5390 ctx.radeon_bld.load_input = declare_input_fs;
5391 if (is_monolithic)
5392 bld_base->emit_epilogue = si_llvm_emit_fs_epilogue;
5393 else
5394 bld_base->emit_epilogue = si_llvm_return_fs_outputs;
5395 break;
5396 default:
5397 assert(!"Unsupported shader type");
5398 return -1;
5399 }
5400
5401 create_meta_data(&ctx);
5402 create_function(&ctx);
5403 preload_constants(&ctx);
5404 preload_samplers(&ctx);
5405 preload_images(&ctx);
5406 preload_streamout_buffers(&ctx);
5407 preload_ring_buffers(&ctx);
5408
5409 if (ctx.is_monolithic && sel->type == PIPE_SHADER_FRAGMENT &&
5410 shader->key.ps.prolog.poly_stipple) {
5411 LLVMValueRef views = LLVMGetParam(ctx.radeon_bld.main_fn,
5412 SI_PARAM_SAMPLERS);
5413 si_llvm_emit_polygon_stipple(&ctx, views,
5414 SI_PARAM_POS_FIXED_PT);
5415 }
5416
5417 if (ctx.type == TGSI_PROCESSOR_GEOMETRY) {
5418 int i;
5419 for (i = 0; i < 4; i++) {
5420 ctx.gs_next_vertex[i] =
5421 lp_build_alloca(bld_base->base.gallivm,
5422 ctx.i32, "");
5423 }
5424 }
5425
5426 if (!lp_build_tgsi_llvm(bld_base, sel->tokens)) {
5427 fprintf(stderr, "Failed to translate shader from TGSI to LLVM\n");
5428 goto out;
5429 }
5430
5431 LLVMBuildRet(bld_base->base.gallivm->builder, ctx.return_value);
5432 mod = bld_base->base.gallivm->module;
5433
5434 /* Dump LLVM IR before any optimization passes */
5435 if (sscreen->b.debug_flags & DBG_PREOPT_IR &&
5436 r600_can_dump_shader(&sscreen->b, ctx.type))
5437 LLVMDumpModule(mod);
5438
5439 radeon_llvm_finalize_module(&ctx.radeon_bld);
5440
5441 r = si_compile_llvm(sscreen, &shader->binary, &shader->config, tm,
5442 mod, debug, ctx.type, "TGSI shader");
5443 if (r) {
5444 fprintf(stderr, "LLVM failed to compile shader\n");
5445 goto out;
5446 }
5447
5448 radeon_llvm_dispose(&ctx.radeon_bld);
5449
5450 /* Calculate the number of fragment input VGPRs. */
5451 if (ctx.type == TGSI_PROCESSOR_FRAGMENT) {
5452 shader->info.num_input_vgprs = 0;
5453 shader->info.face_vgpr_index = -1;
5454
5455 if (G_0286CC_PERSP_SAMPLE_ENA(shader->config.spi_ps_input_addr))
5456 shader->info.num_input_vgprs += 2;
5457 if (G_0286CC_PERSP_CENTER_ENA(shader->config.spi_ps_input_addr))
5458 shader->info.num_input_vgprs += 2;
5459 if (G_0286CC_PERSP_CENTROID_ENA(shader->config.spi_ps_input_addr))
5460 shader->info.num_input_vgprs += 2;
5461 if (G_0286CC_PERSP_PULL_MODEL_ENA(shader->config.spi_ps_input_addr))
5462 shader->info.num_input_vgprs += 3;
5463 if (G_0286CC_LINEAR_SAMPLE_ENA(shader->config.spi_ps_input_addr))
5464 shader->info.num_input_vgprs += 2;
5465 if (G_0286CC_LINEAR_CENTER_ENA(shader->config.spi_ps_input_addr))
5466 shader->info.num_input_vgprs += 2;
5467 if (G_0286CC_LINEAR_CENTROID_ENA(shader->config.spi_ps_input_addr))
5468 shader->info.num_input_vgprs += 2;
5469 if (G_0286CC_LINE_STIPPLE_TEX_ENA(shader->config.spi_ps_input_addr))
5470 shader->info.num_input_vgprs += 1;
5471 if (G_0286CC_POS_X_FLOAT_ENA(shader->config.spi_ps_input_addr))
5472 shader->info.num_input_vgprs += 1;
5473 if (G_0286CC_POS_Y_FLOAT_ENA(shader->config.spi_ps_input_addr))
5474 shader->info.num_input_vgprs += 1;
5475 if (G_0286CC_POS_Z_FLOAT_ENA(shader->config.spi_ps_input_addr))
5476 shader->info.num_input_vgprs += 1;
5477 if (G_0286CC_POS_W_FLOAT_ENA(shader->config.spi_ps_input_addr))
5478 shader->info.num_input_vgprs += 1;
5479 if (G_0286CC_FRONT_FACE_ENA(shader->config.spi_ps_input_addr)) {
5480 shader->info.face_vgpr_index = shader->info.num_input_vgprs;
5481 shader->info.num_input_vgprs += 1;
5482 }
5483 if (G_0286CC_ANCILLARY_ENA(shader->config.spi_ps_input_addr))
5484 shader->info.num_input_vgprs += 1;
5485 if (G_0286CC_SAMPLE_COVERAGE_ENA(shader->config.spi_ps_input_addr))
5486 shader->info.num_input_vgprs += 1;
5487 if (G_0286CC_POS_FIXED_PT_ENA(shader->config.spi_ps_input_addr))
5488 shader->info.num_input_vgprs += 1;
5489 }
5490
5491 if (ctx.type == TGSI_PROCESSOR_GEOMETRY) {
5492 shader->gs_copy_shader = CALLOC_STRUCT(si_shader);
5493 shader->gs_copy_shader->selector = shader->selector;
5494 ctx.shader = shader->gs_copy_shader;
5495 if ((r = si_generate_gs_copy_shader(sscreen, &ctx,
5496 shader, debug))) {
5497 free(shader->gs_copy_shader);
5498 shader->gs_copy_shader = NULL;
5499 goto out;
5500 }
5501 }
5502
5503 out:
5504 for (int i = 0; i < SI_NUM_CONST_BUFFERS; i++)
5505 FREE(ctx.constants[i]);
5506 return r;
5507 }
5508
5509 /**
5510 * Create, compile and return a shader part (prolog or epilog).
5511 *
5512 * \param sscreen screen
5513 * \param list list of shader parts of the same category
5514 * \param key shader part key
5515 * \param tm LLVM target machine
5516 * \param debug debug callback
5517 * \param compile the callback responsible for compilation
5518 * \return non-NULL on success
5519 */
5520 static struct si_shader_part *
5521 si_get_shader_part(struct si_screen *sscreen,
5522 struct si_shader_part **list,
5523 union si_shader_part_key *key,
5524 LLVMTargetMachineRef tm,
5525 struct pipe_debug_callback *debug,
5526 bool (*compile)(struct si_screen *,
5527 LLVMTargetMachineRef,
5528 struct pipe_debug_callback *,
5529 struct si_shader_part *))
5530 {
5531 struct si_shader_part *result;
5532
5533 pipe_mutex_lock(sscreen->shader_parts_mutex);
5534
5535 /* Find existing. */
5536 for (result = *list; result; result = result->next) {
5537 if (memcmp(&result->key, key, sizeof(*key)) == 0) {
5538 pipe_mutex_unlock(sscreen->shader_parts_mutex);
5539 return result;
5540 }
5541 }
5542
5543 /* Compile a new one. */
5544 result = CALLOC_STRUCT(si_shader_part);
5545 result->key = *key;
5546 if (!compile(sscreen, tm, debug, result)) {
5547 FREE(result);
5548 pipe_mutex_unlock(sscreen->shader_parts_mutex);
5549 return NULL;
5550 }
5551
5552 result->next = *list;
5553 *list = result;
5554 pipe_mutex_unlock(sscreen->shader_parts_mutex);
5555 return result;
5556 }
5557
5558 /**
5559 * Create a vertex shader prolog.
5560 *
5561 * The inputs are the same as VS (a lot of SGPRs and 4 VGPR system values).
5562 * All inputs are returned unmodified. The vertex load indices are
5563 * stored after them, which will used by the API VS for fetching inputs.
5564 *
5565 * For example, the expected outputs for instance_divisors[] = {0, 1, 2} are:
5566 * input_v0,
5567 * input_v1,
5568 * input_v2,
5569 * input_v3,
5570 * (VertexID + BaseVertex),
5571 * (InstanceID + StartInstance),
5572 * (InstanceID / 2 + StartInstance)
5573 */
5574 static bool si_compile_vs_prolog(struct si_screen *sscreen,
5575 LLVMTargetMachineRef tm,
5576 struct pipe_debug_callback *debug,
5577 struct si_shader_part *out)
5578 {
5579 union si_shader_part_key *key = &out->key;
5580 struct si_shader shader = {};
5581 struct si_shader_context ctx;
5582 struct gallivm_state *gallivm = &ctx.radeon_bld.gallivm;
5583 LLVMTypeRef *params, *returns;
5584 LLVMValueRef ret, func;
5585 int last_sgpr, num_params, num_returns, i;
5586 bool status = true;
5587
5588 si_init_shader_ctx(&ctx, sscreen, &shader, tm);
5589 ctx.type = TGSI_PROCESSOR_VERTEX;
5590 ctx.param_vertex_id = key->vs_prolog.num_input_sgprs;
5591 ctx.param_instance_id = key->vs_prolog.num_input_sgprs + 3;
5592
5593 /* 4 preloaded VGPRs + vertex load indices as prolog outputs */
5594 params = alloca((key->vs_prolog.num_input_sgprs + 4) *
5595 sizeof(LLVMTypeRef));
5596 returns = alloca((key->vs_prolog.num_input_sgprs + 4 +
5597 key->vs_prolog.last_input + 1) *
5598 sizeof(LLVMTypeRef));
5599 num_params = 0;
5600 num_returns = 0;
5601
5602 /* Declare input and output SGPRs. */
5603 num_params = 0;
5604 for (i = 0; i < key->vs_prolog.num_input_sgprs; i++) {
5605 params[num_params++] = ctx.i32;
5606 returns[num_returns++] = ctx.i32;
5607 }
5608 last_sgpr = num_params - 1;
5609
5610 /* 4 preloaded VGPRs (outputs must be floats) */
5611 for (i = 0; i < 4; i++) {
5612 params[num_params++] = ctx.i32;
5613 returns[num_returns++] = ctx.f32;
5614 }
5615
5616 /* Vertex load indices. */
5617 for (i = 0; i <= key->vs_prolog.last_input; i++)
5618 returns[num_returns++] = ctx.f32;
5619
5620 /* Create the function. */
5621 si_create_function(&ctx, returns, num_returns, params,
5622 num_params, -1, last_sgpr);
5623 func = ctx.radeon_bld.main_fn;
5624
5625 /* Copy inputs to outputs. This should be no-op, as the registers match,
5626 * but it will prevent the compiler from overwriting them unintentionally.
5627 */
5628 ret = ctx.return_value;
5629 for (i = 0; i < key->vs_prolog.num_input_sgprs; i++) {
5630 LLVMValueRef p = LLVMGetParam(func, i);
5631 ret = LLVMBuildInsertValue(gallivm->builder, ret, p, i, "");
5632 }
5633 for (i = num_params - 4; i < num_params; i++) {
5634 LLVMValueRef p = LLVMGetParam(func, i);
5635 p = LLVMBuildBitCast(gallivm->builder, p, ctx.f32, "");
5636 ret = LLVMBuildInsertValue(gallivm->builder, ret, p, i, "");
5637 }
5638
5639 /* Compute vertex load indices from instance divisors. */
5640 for (i = 0; i <= key->vs_prolog.last_input; i++) {
5641 unsigned divisor = key->vs_prolog.states.instance_divisors[i];
5642 LLVMValueRef index;
5643
5644 if (divisor) {
5645 /* InstanceID / Divisor + StartInstance */
5646 index = get_instance_index_for_fetch(&ctx.radeon_bld,
5647 SI_SGPR_START_INSTANCE,
5648 divisor);
5649 } else {
5650 /* VertexID + BaseVertex */
5651 index = LLVMBuildAdd(gallivm->builder,
5652 LLVMGetParam(func, ctx.param_vertex_id),
5653 LLVMGetParam(func, SI_SGPR_BASE_VERTEX), "");
5654 }
5655
5656 index = LLVMBuildBitCast(gallivm->builder, index, ctx.f32, "");
5657 ret = LLVMBuildInsertValue(gallivm->builder, ret, index,
5658 num_params++, "");
5659 }
5660
5661 /* Compile. */
5662 LLVMBuildRet(gallivm->builder, ret);
5663 radeon_llvm_finalize_module(&ctx.radeon_bld);
5664
5665 if (si_compile_llvm(sscreen, &out->binary, &out->config, tm,
5666 gallivm->module, debug, ctx.type,
5667 "Vertex Shader Prolog"))
5668 status = false;
5669
5670 radeon_llvm_dispose(&ctx.radeon_bld);
5671 return status;
5672 }
5673
5674 /**
5675 * Compile the vertex shader epilog. This is also used by the tessellation
5676 * evaluation shader compiled as VS.
5677 *
5678 * The input is PrimitiveID.
5679 *
5680 * If PrimitiveID is required by the pixel shader, export it.
5681 * Otherwise, do nothing.
5682 */
5683 static bool si_compile_vs_epilog(struct si_screen *sscreen,
5684 LLVMTargetMachineRef tm,
5685 struct pipe_debug_callback *debug,
5686 struct si_shader_part *out)
5687 {
5688 union si_shader_part_key *key = &out->key;
5689 struct si_shader_context ctx;
5690 struct gallivm_state *gallivm = &ctx.radeon_bld.gallivm;
5691 struct lp_build_tgsi_context *bld_base = &ctx.radeon_bld.soa.bld_base;
5692 LLVMTypeRef params[5];
5693 int num_params, i;
5694 bool status = true;
5695
5696 si_init_shader_ctx(&ctx, sscreen, NULL, tm);
5697 ctx.type = TGSI_PROCESSOR_VERTEX;
5698
5699 /* Declare input VGPRs. */
5700 num_params = key->vs_epilog.states.export_prim_id ?
5701 (VS_EPILOG_PRIMID_LOC + 1) : 0;
5702 assert(num_params <= ARRAY_SIZE(params));
5703
5704 for (i = 0; i < num_params; i++)
5705 params[i] = ctx.f32;
5706
5707 /* Create the function. */
5708 si_create_function(&ctx, NULL, 0, params, num_params,
5709 -1, -1);
5710
5711 /* Emit exports. */
5712 if (key->vs_epilog.states.export_prim_id) {
5713 struct lp_build_context *base = &bld_base->base;
5714 struct lp_build_context *uint = &bld_base->uint_bld;
5715 LLVMValueRef args[9];
5716
5717 args[0] = lp_build_const_int32(base->gallivm, 0x0); /* enabled channels */
5718 args[1] = uint->zero; /* whether the EXEC mask is valid */
5719 args[2] = uint->zero; /* DONE bit */
5720 args[3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_PARAM +
5721 key->vs_epilog.prim_id_param_offset);
5722 args[4] = uint->zero; /* COMPR flag (0 = 32-bit export) */
5723 args[5] = LLVMGetParam(ctx.radeon_bld.main_fn,
5724 VS_EPILOG_PRIMID_LOC); /* X */
5725 args[6] = uint->undef; /* Y */
5726 args[7] = uint->undef; /* Z */
5727 args[8] = uint->undef; /* W */
5728
5729 lp_build_intrinsic(base->gallivm->builder, "llvm.SI.export",
5730 LLVMVoidTypeInContext(base->gallivm->context),
5731 args, 9, 0);
5732 }
5733
5734 /* Compile. */
5735 LLVMBuildRet(gallivm->builder, ctx.return_value);
5736 radeon_llvm_finalize_module(&ctx.radeon_bld);
5737
5738 if (si_compile_llvm(sscreen, &out->binary, &out->config, tm,
5739 gallivm->module, debug, ctx.type,
5740 "Vertex Shader Epilog"))
5741 status = false;
5742
5743 radeon_llvm_dispose(&ctx.radeon_bld);
5744 return status;
5745 }
5746
5747 /**
5748 * Create & compile a vertex shader epilog. This a helper used by VS and TES.
5749 */
5750 static bool si_get_vs_epilog(struct si_screen *sscreen,
5751 LLVMTargetMachineRef tm,
5752 struct si_shader *shader,
5753 struct pipe_debug_callback *debug,
5754 struct si_vs_epilog_bits *states)
5755 {
5756 union si_shader_part_key epilog_key;
5757
5758 memset(&epilog_key, 0, sizeof(epilog_key));
5759 epilog_key.vs_epilog.states = *states;
5760
5761 /* Set up the PrimitiveID output. */
5762 if (shader->key.vs.epilog.export_prim_id) {
5763 unsigned index = shader->selector->info.num_outputs;
5764 unsigned offset = shader->info.nr_param_exports++;
5765
5766 epilog_key.vs_epilog.prim_id_param_offset = offset;
5767 assert(index < ARRAY_SIZE(shader->info.vs_output_param_offset));
5768 shader->info.vs_output_param_offset[index] = offset;
5769 }
5770
5771 shader->epilog = si_get_shader_part(sscreen, &sscreen->vs_epilogs,
5772 &epilog_key, tm, debug,
5773 si_compile_vs_epilog);
5774 return shader->epilog != NULL;
5775 }
5776
5777 /**
5778 * Select and compile (or reuse) vertex shader parts (prolog & epilog).
5779 */
5780 static bool si_shader_select_vs_parts(struct si_screen *sscreen,
5781 LLVMTargetMachineRef tm,
5782 struct si_shader *shader,
5783 struct pipe_debug_callback *debug)
5784 {
5785 struct tgsi_shader_info *info = &shader->selector->info;
5786 union si_shader_part_key prolog_key;
5787 unsigned i;
5788
5789 /* Get the prolog. */
5790 memset(&prolog_key, 0, sizeof(prolog_key));
5791 prolog_key.vs_prolog.states = shader->key.vs.prolog;
5792 prolog_key.vs_prolog.num_input_sgprs = shader->info.num_input_sgprs;
5793 prolog_key.vs_prolog.last_input = MAX2(1, info->num_inputs) - 1;
5794
5795 /* The prolog is a no-op if there are no inputs. */
5796 if (info->num_inputs) {
5797 shader->prolog =
5798 si_get_shader_part(sscreen, &sscreen->vs_prologs,
5799 &prolog_key, tm, debug,
5800 si_compile_vs_prolog);
5801 if (!shader->prolog)
5802 return false;
5803 }
5804
5805 /* Get the epilog. */
5806 if (!shader->key.vs.as_es && !shader->key.vs.as_ls &&
5807 !si_get_vs_epilog(sscreen, tm, shader, debug,
5808 &shader->key.vs.epilog))
5809 return false;
5810
5811 /* Set the instanceID flag. */
5812 for (i = 0; i < info->num_inputs; i++)
5813 if (prolog_key.vs_prolog.states.instance_divisors[i])
5814 shader->info.uses_instanceid = true;
5815
5816 return true;
5817 }
5818
5819 /**
5820 * Select and compile (or reuse) TES parts (epilog).
5821 */
5822 static bool si_shader_select_tes_parts(struct si_screen *sscreen,
5823 LLVMTargetMachineRef tm,
5824 struct si_shader *shader,
5825 struct pipe_debug_callback *debug)
5826 {
5827 if (shader->key.tes.as_es)
5828 return true;
5829
5830 /* TES compiled as VS. */
5831 return si_get_vs_epilog(sscreen, tm, shader, debug,
5832 &shader->key.tes.epilog);
5833 }
5834
5835 /**
5836 * Compile the TCS epilog. This writes tesselation factors to memory based on
5837 * the output primitive type of the tesselator (determined by TES).
5838 */
5839 static bool si_compile_tcs_epilog(struct si_screen *sscreen,
5840 LLVMTargetMachineRef tm,
5841 struct pipe_debug_callback *debug,
5842 struct si_shader_part *out)
5843 {
5844 union si_shader_part_key *key = &out->key;
5845 struct si_shader shader = {};
5846 struct si_shader_context ctx;
5847 struct gallivm_state *gallivm = &ctx.radeon_bld.gallivm;
5848 struct lp_build_tgsi_context *bld_base = &ctx.radeon_bld.soa.bld_base;
5849 LLVMTypeRef params[16];
5850 LLVMValueRef func;
5851 int last_array_pointer, last_sgpr, num_params;
5852 bool status = true;
5853
5854 si_init_shader_ctx(&ctx, sscreen, &shader, tm);
5855 ctx.type = TGSI_PROCESSOR_TESS_CTRL;
5856 shader.key.tcs.epilog = key->tcs_epilog.states;
5857
5858 /* Declare inputs. Only RW_BUFFERS and TESS_FACTOR_OFFSET are used. */
5859 params[SI_PARAM_RW_BUFFERS] = const_array(ctx.v16i8, SI_NUM_RW_BUFFERS);
5860 last_array_pointer = SI_PARAM_RW_BUFFERS;
5861 params[SI_PARAM_CONST_BUFFERS] = ctx.i64;
5862 params[SI_PARAM_SAMPLERS] = ctx.i64;
5863 params[SI_PARAM_IMAGES] = ctx.i64;
5864 params[SI_PARAM_TCS_OUT_OFFSETS] = ctx.i32;
5865 params[SI_PARAM_TCS_OUT_LAYOUT] = ctx.i32;
5866 params[SI_PARAM_TCS_IN_LAYOUT] = ctx.i32;
5867 params[SI_PARAM_TESS_FACTOR_OFFSET] = ctx.i32;
5868 last_sgpr = SI_PARAM_TESS_FACTOR_OFFSET;
5869 num_params = last_sgpr + 1;
5870
5871 params[num_params++] = ctx.i32; /* patch index within the wave (REL_PATCH_ID) */
5872 params[num_params++] = ctx.i32; /* invocation ID within the patch */
5873 params[num_params++] = ctx.i32; /* LDS offset where tess factors should be loaded from */
5874
5875 /* Create the function. */
5876 si_create_function(&ctx, NULL, 0, params, num_params,
5877 last_array_pointer, last_sgpr);
5878 declare_tess_lds(&ctx);
5879 func = ctx.radeon_bld.main_fn;
5880
5881 si_write_tess_factors(bld_base,
5882 LLVMGetParam(func, last_sgpr + 1),
5883 LLVMGetParam(func, last_sgpr + 2),
5884 LLVMGetParam(func, last_sgpr + 3));
5885
5886 /* Compile. */
5887 LLVMBuildRet(gallivm->builder, ctx.return_value);
5888 radeon_llvm_finalize_module(&ctx.radeon_bld);
5889
5890 if (si_compile_llvm(sscreen, &out->binary, &out->config, tm,
5891 gallivm->module, debug, ctx.type,
5892 "Tessellation Control Shader Epilog"))
5893 status = false;
5894
5895 radeon_llvm_dispose(&ctx.radeon_bld);
5896 return status;
5897 }
5898
5899 /**
5900 * Select and compile (or reuse) TCS parts (epilog).
5901 */
5902 static bool si_shader_select_tcs_parts(struct si_screen *sscreen,
5903 LLVMTargetMachineRef tm,
5904 struct si_shader *shader,
5905 struct pipe_debug_callback *debug)
5906 {
5907 union si_shader_part_key epilog_key;
5908
5909 /* Get the epilog. */
5910 memset(&epilog_key, 0, sizeof(epilog_key));
5911 epilog_key.tcs_epilog.states = shader->key.tcs.epilog;
5912
5913 shader->epilog = si_get_shader_part(sscreen, &sscreen->tcs_epilogs,
5914 &epilog_key, tm, debug,
5915 si_compile_tcs_epilog);
5916 return shader->epilog != NULL;
5917 }
5918
5919 /**
5920 * Compile the pixel shader prolog. This handles:
5921 * - two-side color selection and interpolation
5922 * - overriding interpolation parameters for the API PS
5923 * - polygon stippling
5924 *
5925 * All preloaded SGPRs and VGPRs are passed through unmodified unless they are
5926 * overriden by other states. (e.g. per-sample interpolation)
5927 * Interpolated colors are stored after the preloaded VGPRs.
5928 */
5929 static bool si_compile_ps_prolog(struct si_screen *sscreen,
5930 LLVMTargetMachineRef tm,
5931 struct pipe_debug_callback *debug,
5932 struct si_shader_part *out)
5933 {
5934 union si_shader_part_key *key = &out->key;
5935 struct si_shader shader = {};
5936 struct si_shader_context ctx;
5937 struct gallivm_state *gallivm = &ctx.radeon_bld.gallivm;
5938 LLVMTypeRef *params;
5939 LLVMValueRef ret, func;
5940 int last_sgpr, num_params, num_returns, i, num_color_channels;
5941 bool status = true;
5942
5943 si_init_shader_ctx(&ctx, sscreen, &shader, tm);
5944 ctx.type = TGSI_PROCESSOR_FRAGMENT;
5945 shader.key.ps.prolog = key->ps_prolog.states;
5946
5947 /* Number of inputs + 8 color elements. */
5948 params = alloca((key->ps_prolog.num_input_sgprs +
5949 key->ps_prolog.num_input_vgprs + 8) *
5950 sizeof(LLVMTypeRef));
5951
5952 /* Declare inputs. */
5953 num_params = 0;
5954 for (i = 0; i < key->ps_prolog.num_input_sgprs; i++)
5955 params[num_params++] = ctx.i32;
5956 last_sgpr = num_params - 1;
5957
5958 for (i = 0; i < key->ps_prolog.num_input_vgprs; i++)
5959 params[num_params++] = ctx.f32;
5960
5961 /* Declare outputs (same as inputs + add colors if needed) */
5962 num_returns = num_params;
5963 num_color_channels = util_bitcount(key->ps_prolog.colors_read);
5964 for (i = 0; i < num_color_channels; i++)
5965 params[num_returns++] = ctx.f32;
5966
5967 /* Create the function. */
5968 si_create_function(&ctx, params, num_returns, params,
5969 num_params, -1, last_sgpr);
5970 func = ctx.radeon_bld.main_fn;
5971
5972 /* Copy inputs to outputs. This should be no-op, as the registers match,
5973 * but it will prevent the compiler from overwriting them unintentionally.
5974 */
5975 ret = ctx.return_value;
5976 for (i = 0; i < num_params; i++) {
5977 LLVMValueRef p = LLVMGetParam(func, i);
5978 ret = LLVMBuildInsertValue(gallivm->builder, ret, p, i, "");
5979 }
5980
5981 /* Polygon stippling. */
5982 if (key->ps_prolog.states.poly_stipple) {
5983 /* POS_FIXED_PT is always last. */
5984 unsigned pos = key->ps_prolog.num_input_sgprs +
5985 key->ps_prolog.num_input_vgprs - 1;
5986 LLVMValueRef ptr[2], views;
5987
5988 /* Get the pointer to sampler views. */
5989 ptr[0] = LLVMGetParam(func, SI_SGPR_SAMPLERS);
5990 ptr[1] = LLVMGetParam(func, SI_SGPR_SAMPLERS+1);
5991 views = lp_build_gather_values(gallivm, ptr, 2);
5992 views = LLVMBuildBitCast(gallivm->builder, views, ctx.i64, "");
5993 views = LLVMBuildIntToPtr(gallivm->builder, views,
5994 const_array(ctx.v8i32, SI_NUM_SAMPLERS), "");
5995
5996 si_llvm_emit_polygon_stipple(&ctx, views, pos);
5997 }
5998
5999 /* Interpolate colors. */
6000 for (i = 0; i < 2; i++) {
6001 unsigned writemask = (key->ps_prolog.colors_read >> (i * 4)) & 0xf;
6002 unsigned face_vgpr = key->ps_prolog.num_input_sgprs +
6003 key->ps_prolog.face_vgpr_index;
6004 LLVMValueRef interp[2], color[4];
6005 LLVMValueRef interp_ij = NULL, prim_mask = NULL, face = NULL;
6006
6007 if (!writemask)
6008 continue;
6009
6010 /* If the interpolation qualifier is not CONSTANT (-1). */
6011 if (key->ps_prolog.color_interp_vgpr_index[i] != -1) {
6012 unsigned interp_vgpr = key->ps_prolog.num_input_sgprs +
6013 key->ps_prolog.color_interp_vgpr_index[i];
6014
6015 interp[0] = LLVMGetParam(func, interp_vgpr);
6016 interp[1] = LLVMGetParam(func, interp_vgpr + 1);
6017 interp_ij = lp_build_gather_values(gallivm, interp, 2);
6018 interp_ij = LLVMBuildBitCast(gallivm->builder, interp_ij,
6019 ctx.v2i32, "");
6020 }
6021
6022 /* Use the absolute location of the input. */
6023 prim_mask = LLVMGetParam(func, SI_PS_NUM_USER_SGPR);
6024
6025 if (key->ps_prolog.states.color_two_side) {
6026 face = LLVMGetParam(func, face_vgpr);
6027 face = LLVMBuildBitCast(gallivm->builder, face, ctx.i32, "");
6028 }
6029
6030 interp_fs_input(&ctx,
6031 key->ps_prolog.color_attr_index[i],
6032 TGSI_SEMANTIC_COLOR, i,
6033 key->ps_prolog.num_interp_inputs,
6034 key->ps_prolog.colors_read, interp_ij,
6035 prim_mask, face, color);
6036
6037 while (writemask) {
6038 unsigned chan = u_bit_scan(&writemask);
6039 ret = LLVMBuildInsertValue(gallivm->builder, ret, color[chan],
6040 num_params++, "");
6041 }
6042 }
6043
6044 /* Force per-sample interpolation. */
6045 if (key->ps_prolog.states.force_persample_interp) {
6046 unsigned i, base = key->ps_prolog.num_input_sgprs;
6047 LLVMValueRef persp_sample[2], linear_sample[2];
6048
6049 /* Read PERSP_SAMPLE. */
6050 for (i = 0; i < 2; i++)
6051 persp_sample[i] = LLVMGetParam(func, base + i);
6052 /* Overwrite PERSP_CENTER. */
6053 for (i = 0; i < 2; i++)
6054 ret = LLVMBuildInsertValue(gallivm->builder, ret,
6055 persp_sample[i], base + 2 + i, "");
6056 /* Overwrite PERSP_CENTROID. */
6057 for (i = 0; i < 2; i++)
6058 ret = LLVMBuildInsertValue(gallivm->builder, ret,
6059 persp_sample[i], base + 4 + i, "");
6060 /* Read LINEAR_SAMPLE. */
6061 for (i = 0; i < 2; i++)
6062 linear_sample[i] = LLVMGetParam(func, base + 6 + i);
6063 /* Overwrite LINEAR_CENTER. */
6064 for (i = 0; i < 2; i++)
6065 ret = LLVMBuildInsertValue(gallivm->builder, ret,
6066 linear_sample[i], base + 8 + i, "");
6067 /* Overwrite LINEAR_CENTROID. */
6068 for (i = 0; i < 2; i++)
6069 ret = LLVMBuildInsertValue(gallivm->builder, ret,
6070 linear_sample[i], base + 10 + i, "");
6071 }
6072
6073 /* Compile. */
6074 LLVMBuildRet(gallivm->builder, ret);
6075 radeon_llvm_finalize_module(&ctx.radeon_bld);
6076
6077 if (si_compile_llvm(sscreen, &out->binary, &out->config, tm,
6078 gallivm->module, debug, ctx.type,
6079 "Fragment Shader Prolog"))
6080 status = false;
6081
6082 radeon_llvm_dispose(&ctx.radeon_bld);
6083 return status;
6084 }
6085
6086 /**
6087 * Compile the pixel shader epilog. This handles everything that must be
6088 * emulated for pixel shader exports. (alpha-test, format conversions, etc)
6089 */
6090 static bool si_compile_ps_epilog(struct si_screen *sscreen,
6091 LLVMTargetMachineRef tm,
6092 struct pipe_debug_callback *debug,
6093 struct si_shader_part *out)
6094 {
6095 union si_shader_part_key *key = &out->key;
6096 struct si_shader shader = {};
6097 struct si_shader_context ctx;
6098 struct gallivm_state *gallivm = &ctx.radeon_bld.gallivm;
6099 struct lp_build_tgsi_context *bld_base = &ctx.radeon_bld.soa.bld_base;
6100 LLVMTypeRef params[16+8*4+3];
6101 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
6102 int last_array_pointer, last_sgpr, num_params, i;
6103 bool status = true;
6104
6105 si_init_shader_ctx(&ctx, sscreen, &shader, tm);
6106 ctx.type = TGSI_PROCESSOR_FRAGMENT;
6107 shader.key.ps.epilog = key->ps_epilog.states;
6108
6109 /* Declare input SGPRs. */
6110 params[SI_PARAM_RW_BUFFERS] = ctx.i64;
6111 params[SI_PARAM_CONST_BUFFERS] = ctx.i64;
6112 params[SI_PARAM_SAMPLERS] = ctx.i64;
6113 params[SI_PARAM_IMAGES] = ctx.i64;
6114 params[SI_PARAM_ALPHA_REF] = ctx.f32;
6115 last_array_pointer = -1;
6116 last_sgpr = SI_PARAM_ALPHA_REF;
6117
6118 /* Declare input VGPRs. */
6119 num_params = (last_sgpr + 1) +
6120 util_bitcount(key->ps_epilog.colors_written) * 4 +
6121 key->ps_epilog.writes_z +
6122 key->ps_epilog.writes_stencil +
6123 key->ps_epilog.writes_samplemask;
6124
6125 num_params = MAX2(num_params,
6126 last_sgpr + 1 + PS_EPILOG_SAMPLEMASK_MIN_LOC + 1);
6127
6128 assert(num_params <= ARRAY_SIZE(params));
6129
6130 for (i = last_sgpr + 1; i < num_params; i++)
6131 params[i] = ctx.f32;
6132
6133 /* Create the function. */
6134 si_create_function(&ctx, NULL, 0, params, num_params,
6135 last_array_pointer, last_sgpr);
6136 /* Disable elimination of unused inputs. */
6137 radeon_llvm_add_attribute(ctx.radeon_bld.main_fn,
6138 "InitialPSInputAddr", 0xffffff);
6139
6140 /* Process colors. */
6141 unsigned vgpr = last_sgpr + 1;
6142 unsigned colors_written = key->ps_epilog.colors_written;
6143 int last_color_export = -1;
6144
6145 /* Find the last color export. */
6146 if (!key->ps_epilog.writes_z &&
6147 !key->ps_epilog.writes_stencil &&
6148 !key->ps_epilog.writes_samplemask) {
6149 unsigned spi_format = key->ps_epilog.states.spi_shader_col_format;
6150
6151 /* If last_cbuf > 0, FS_COLOR0_WRITES_ALL_CBUFS is true. */
6152 if (colors_written == 0x1 && key->ps_epilog.states.last_cbuf > 0) {
6153 /* Just set this if any of the colorbuffers are enabled. */
6154 if (spi_format &
6155 ((1llu << (4 * (key->ps_epilog.states.last_cbuf + 1))) - 1))
6156 last_color_export = 0;
6157 } else {
6158 for (i = 0; i < 8; i++)
6159 if (colors_written & (1 << i) &&
6160 (spi_format >> (i * 4)) & 0xf)
6161 last_color_export = i;
6162 }
6163 }
6164
6165 while (colors_written) {
6166 LLVMValueRef color[4];
6167 int mrt = u_bit_scan(&colors_written);
6168
6169 for (i = 0; i < 4; i++)
6170 color[i] = LLVMGetParam(ctx.radeon_bld.main_fn, vgpr++);
6171
6172 si_export_mrt_color(bld_base, color, mrt,
6173 num_params - 1,
6174 mrt == last_color_export);
6175 }
6176
6177 /* Process depth, stencil, samplemask. */
6178 if (key->ps_epilog.writes_z)
6179 depth = LLVMGetParam(ctx.radeon_bld.main_fn, vgpr++);
6180 if (key->ps_epilog.writes_stencil)
6181 stencil = LLVMGetParam(ctx.radeon_bld.main_fn, vgpr++);
6182 if (key->ps_epilog.writes_samplemask)
6183 samplemask = LLVMGetParam(ctx.radeon_bld.main_fn, vgpr++);
6184
6185 if (depth || stencil || samplemask)
6186 si_export_mrt_z(bld_base, depth, stencil, samplemask);
6187 else if (last_color_export == -1)
6188 si_export_null(bld_base);
6189
6190 /* Compile. */
6191 LLVMBuildRetVoid(gallivm->builder);
6192 radeon_llvm_finalize_module(&ctx.radeon_bld);
6193
6194 if (si_compile_llvm(sscreen, &out->binary, &out->config, tm,
6195 gallivm->module, debug, ctx.type,
6196 "Fragment Shader Epilog"))
6197 status = false;
6198
6199 radeon_llvm_dispose(&ctx.radeon_bld);
6200 return status;
6201 }
6202
6203 /**
6204 * Select and compile (or reuse) pixel shader parts (prolog & epilog).
6205 */
6206 static bool si_shader_select_ps_parts(struct si_screen *sscreen,
6207 LLVMTargetMachineRef tm,
6208 struct si_shader *shader,
6209 struct pipe_debug_callback *debug)
6210 {
6211 struct tgsi_shader_info *info = &shader->selector->info;
6212 union si_shader_part_key prolog_key;
6213 union si_shader_part_key epilog_key;
6214 unsigned i;
6215
6216 /* Get the prolog. */
6217 memset(&prolog_key, 0, sizeof(prolog_key));
6218 prolog_key.ps_prolog.states = shader->key.ps.prolog;
6219 prolog_key.ps_prolog.colors_read = info->colors_read;
6220 prolog_key.ps_prolog.num_input_sgprs = shader->info.num_input_sgprs;
6221 prolog_key.ps_prolog.num_input_vgprs = shader->info.num_input_vgprs;
6222
6223 if (info->colors_read) {
6224 unsigned *color = shader->selector->color_attr_index;
6225
6226 if (shader->key.ps.prolog.color_two_side) {
6227 /* BCOLORs are stored after the last input. */
6228 prolog_key.ps_prolog.num_interp_inputs = info->num_inputs;
6229 prolog_key.ps_prolog.face_vgpr_index = shader->info.face_vgpr_index;
6230 shader->config.spi_ps_input_ena |= S_0286CC_FRONT_FACE_ENA(1);
6231 }
6232
6233 for (i = 0; i < 2; i++) {
6234 unsigned location = info->input_interpolate_loc[color[i]];
6235
6236 if (!(info->colors_read & (0xf << i*4)))
6237 continue;
6238
6239 prolog_key.ps_prolog.color_attr_index[i] = color[i];
6240
6241 /* Force per-sample interpolation for the colors here. */
6242 if (shader->key.ps.prolog.force_persample_interp)
6243 location = TGSI_INTERPOLATE_LOC_SAMPLE;
6244
6245 switch (info->input_interpolate[color[i]]) {
6246 case TGSI_INTERPOLATE_CONSTANT:
6247 prolog_key.ps_prolog.color_interp_vgpr_index[i] = -1;
6248 break;
6249 case TGSI_INTERPOLATE_PERSPECTIVE:
6250 case TGSI_INTERPOLATE_COLOR:
6251 switch (location) {
6252 case TGSI_INTERPOLATE_LOC_SAMPLE:
6253 prolog_key.ps_prolog.color_interp_vgpr_index[i] = 0;
6254 shader->config.spi_ps_input_ena |=
6255 S_0286CC_PERSP_SAMPLE_ENA(1);
6256 break;
6257 case TGSI_INTERPOLATE_LOC_CENTER:
6258 prolog_key.ps_prolog.color_interp_vgpr_index[i] = 2;
6259 shader->config.spi_ps_input_ena |=
6260 S_0286CC_PERSP_CENTER_ENA(1);
6261 break;
6262 case TGSI_INTERPOLATE_LOC_CENTROID:
6263 prolog_key.ps_prolog.color_interp_vgpr_index[i] = 4;
6264 shader->config.spi_ps_input_ena |=
6265 S_0286CC_PERSP_CENTROID_ENA(1);
6266 break;
6267 default:
6268 assert(0);
6269 }
6270 break;
6271 case TGSI_INTERPOLATE_LINEAR:
6272 switch (location) {
6273 case TGSI_INTERPOLATE_LOC_SAMPLE:
6274 prolog_key.ps_prolog.color_interp_vgpr_index[i] = 6;
6275 shader->config.spi_ps_input_ena |=
6276 S_0286CC_LINEAR_SAMPLE_ENA(1);
6277 break;
6278 case TGSI_INTERPOLATE_LOC_CENTER:
6279 prolog_key.ps_prolog.color_interp_vgpr_index[i] = 8;
6280 shader->config.spi_ps_input_ena |=
6281 S_0286CC_LINEAR_CENTER_ENA(1);
6282 break;
6283 case TGSI_INTERPOLATE_LOC_CENTROID:
6284 prolog_key.ps_prolog.color_interp_vgpr_index[i] = 10;
6285 shader->config.spi_ps_input_ena |=
6286 S_0286CC_LINEAR_CENTROID_ENA(1);
6287 break;
6288 default:
6289 assert(0);
6290 }
6291 break;
6292 default:
6293 assert(0);
6294 }
6295 }
6296 }
6297
6298 /* The prolog is a no-op if these aren't set. */
6299 if (prolog_key.ps_prolog.colors_read ||
6300 prolog_key.ps_prolog.states.force_persample_interp ||
6301 prolog_key.ps_prolog.states.poly_stipple) {
6302 shader->prolog =
6303 si_get_shader_part(sscreen, &sscreen->ps_prologs,
6304 &prolog_key, tm, debug,
6305 si_compile_ps_prolog);
6306 if (!shader->prolog)
6307 return false;
6308 }
6309
6310 /* Get the epilog. */
6311 memset(&epilog_key, 0, sizeof(epilog_key));
6312 epilog_key.ps_epilog.colors_written = info->colors_written;
6313 epilog_key.ps_epilog.writes_z = info->writes_z;
6314 epilog_key.ps_epilog.writes_stencil = info->writes_stencil;
6315 epilog_key.ps_epilog.writes_samplemask = info->writes_samplemask;
6316 epilog_key.ps_epilog.states = shader->key.ps.epilog;
6317
6318 shader->epilog =
6319 si_get_shader_part(sscreen, &sscreen->ps_epilogs,
6320 &epilog_key, tm, debug,
6321 si_compile_ps_epilog);
6322 if (!shader->epilog)
6323 return false;
6324
6325 /* Enable POS_FIXED_PT if polygon stippling is enabled. */
6326 if (shader->key.ps.prolog.poly_stipple) {
6327 shader->config.spi_ps_input_ena |= S_0286CC_POS_FIXED_PT_ENA(1);
6328 assert(G_0286CC_POS_FIXED_PT_ENA(shader->config.spi_ps_input_addr));
6329 }
6330
6331 /* Set up the enable bits for per-sample shading if needed. */
6332 if (shader->key.ps.prolog.force_persample_interp) {
6333 if (G_0286CC_PERSP_CENTER_ENA(shader->config.spi_ps_input_ena) ||
6334 G_0286CC_PERSP_CENTROID_ENA(shader->config.spi_ps_input_ena)) {
6335 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_CENTER_ENA;
6336 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_CENTROID_ENA;
6337 shader->config.spi_ps_input_ena |= S_0286CC_PERSP_SAMPLE_ENA(1);
6338 }
6339 if (G_0286CC_LINEAR_CENTER_ENA(shader->config.spi_ps_input_ena) ||
6340 G_0286CC_LINEAR_CENTROID_ENA(shader->config.spi_ps_input_ena)) {
6341 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_CENTER_ENA;
6342 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_CENTROID_ENA;
6343 shader->config.spi_ps_input_ena |= S_0286CC_LINEAR_SAMPLE_ENA(1);
6344 }
6345 }
6346
6347 /* POW_W_FLOAT requires that one of the perspective weights is enabled. */
6348 if (G_0286CC_POS_W_FLOAT_ENA(shader->config.spi_ps_input_ena) &&
6349 !(shader->config.spi_ps_input_ena & 0xf)) {
6350 shader->config.spi_ps_input_ena |= S_0286CC_PERSP_CENTER_ENA(1);
6351 assert(G_0286CC_PERSP_CENTER_ENA(shader->config.spi_ps_input_addr));
6352 }
6353
6354 /* At least one pair of interpolation weights must be enabled. */
6355 if (!(shader->config.spi_ps_input_ena & 0x7f)) {
6356 shader->config.spi_ps_input_ena |= S_0286CC_LINEAR_CENTER_ENA(1);
6357 assert(G_0286CC_LINEAR_CENTER_ENA(shader->config.spi_ps_input_addr));
6358 }
6359
6360 /* The sample mask input is always enabled, because the API shader always
6361 * passes it through to the epilog. Disable it here if it's unused.
6362 */
6363 if (!shader->key.ps.epilog.poly_line_smoothing &&
6364 !shader->selector->info.reads_samplemask)
6365 shader->config.spi_ps_input_ena &= C_0286CC_SAMPLE_COVERAGE_ENA;
6366
6367 return true;
6368 }
6369
6370 int si_shader_create(struct si_screen *sscreen, LLVMTargetMachineRef tm,
6371 struct si_shader *shader,
6372 struct pipe_debug_callback *debug)
6373 {
6374 struct si_shader *mainp = shader->selector->main_shader_part;
6375 int r;
6376
6377 /* LS, ES, VS are compiled on demand if the main part hasn't been
6378 * compiled for that stage.
6379 */
6380 if (!mainp ||
6381 (shader->selector->type == PIPE_SHADER_VERTEX &&
6382 (shader->key.vs.as_es != mainp->key.vs.as_es ||
6383 shader->key.vs.as_ls != mainp->key.vs.as_ls)) ||
6384 (shader->selector->type == PIPE_SHADER_TESS_EVAL &&
6385 shader->key.tes.as_es != mainp->key.tes.as_es)) {
6386 /* Monolithic shader (compiled as a whole, has many variants,
6387 * may take a long time to compile).
6388 */
6389 r = si_compile_tgsi_shader(sscreen, tm, shader, true, debug);
6390 if (r)
6391 return r;
6392 } else {
6393 /* The shader consists of 2-3 parts:
6394 *
6395 * - the middle part is the user shader, it has 1 variant only
6396 * and it was compiled during the creation of the shader
6397 * selector
6398 * - the prolog part is inserted at the beginning
6399 * - the epilog part is inserted at the end
6400 *
6401 * The prolog and epilog have many (but simple) variants.
6402 */
6403
6404 /* Copy the compiled TGSI shader data over. */
6405 shader->is_binary_shared = true;
6406 shader->binary = mainp->binary;
6407 shader->config = mainp->config;
6408 shader->info.num_input_sgprs = mainp->info.num_input_sgprs;
6409 shader->info.num_input_vgprs = mainp->info.num_input_vgprs;
6410 shader->info.face_vgpr_index = mainp->info.face_vgpr_index;
6411 memcpy(shader->info.vs_output_param_offset,
6412 mainp->info.vs_output_param_offset,
6413 sizeof(mainp->info.vs_output_param_offset));
6414 shader->info.uses_instanceid = mainp->info.uses_instanceid;
6415 shader->info.nr_pos_exports = mainp->info.nr_pos_exports;
6416 shader->info.nr_param_exports = mainp->info.nr_param_exports;
6417
6418 /* Select prologs and/or epilogs. */
6419 switch (shader->selector->type) {
6420 case PIPE_SHADER_VERTEX:
6421 if (!si_shader_select_vs_parts(sscreen, tm, shader, debug))
6422 return -1;
6423 break;
6424 case PIPE_SHADER_TESS_CTRL:
6425 if (!si_shader_select_tcs_parts(sscreen, tm, shader, debug))
6426 return -1;
6427 break;
6428 case PIPE_SHADER_TESS_EVAL:
6429 if (!si_shader_select_tes_parts(sscreen, tm, shader, debug))
6430 return -1;
6431 break;
6432 case PIPE_SHADER_FRAGMENT:
6433 if (!si_shader_select_ps_parts(sscreen, tm, shader, debug))
6434 return -1;
6435
6436 /* Make sure we have at least as many VGPRs as there
6437 * are allocated inputs.
6438 */
6439 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
6440 shader->info.num_input_vgprs);
6441 break;
6442 }
6443
6444 /* Update SGPR and VGPR counts. */
6445 if (shader->prolog) {
6446 shader->config.num_sgprs = MAX2(shader->config.num_sgprs,
6447 shader->prolog->config.num_sgprs);
6448 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
6449 shader->prolog->config.num_vgprs);
6450 }
6451 if (shader->epilog) {
6452 shader->config.num_sgprs = MAX2(shader->config.num_sgprs,
6453 shader->epilog->config.num_sgprs);
6454 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
6455 shader->epilog->config.num_vgprs);
6456 }
6457 }
6458
6459 si_shader_dump(sscreen, shader, debug, shader->selector->info.processor,
6460 stderr);
6461
6462 /* Upload. */
6463 r = si_shader_binary_upload(sscreen, shader);
6464 if (r) {
6465 fprintf(stderr, "LLVM failed to upload shader\n");
6466 return r;
6467 }
6468
6469 return 0;
6470 }
6471
6472 void si_shader_destroy(struct si_shader *shader)
6473 {
6474 if (shader->gs_copy_shader) {
6475 si_shader_destroy(shader->gs_copy_shader);
6476 FREE(shader->gs_copy_shader);
6477 }
6478
6479 if (shader->scratch_bo)
6480 r600_resource_reference(&shader->scratch_bo, NULL);
6481
6482 r600_resource_reference(&shader->bo, NULL);
6483
6484 if (!shader->is_binary_shared)
6485 radeon_shader_binary_clean(&shader->binary);
6486 }