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radeonsi: dump the shader key when dumping shaders
[mesa.git] / src / gallium / drivers / radeonsi / si_shader.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Tom Stellard <thomas.stellard@amd.com>
25 * Michel Dänzer <michel.daenzer@amd.com>
26 * Christian König <christian.koenig@amd.com>
27 */
28
29 #include "gallivm/lp_bld_const.h"
30 #include "gallivm/lp_bld_gather.h"
31 #include "gallivm/lp_bld_intr.h"
32 #include "gallivm/lp_bld_logic.h"
33 #include "gallivm/lp_bld_arit.h"
34 #include "gallivm/lp_bld_flow.h"
35 #include "radeon/r600_cs.h"
36 #include "radeon/radeon_llvm.h"
37 #include "radeon/radeon_elf_util.h"
38 #include "radeon/radeon_llvm_emit.h"
39 #include "util/u_memory.h"
40 #include "util/u_pstipple.h"
41 #include "tgsi/tgsi_parse.h"
42 #include "tgsi/tgsi_util.h"
43 #include "tgsi/tgsi_dump.h"
44
45 #include "si_pipe.h"
46 #include "si_shader.h"
47 #include "sid.h"
48
49 #include <errno.h>
50
51 static const char *scratch_rsrc_dword0_symbol =
52 "SCRATCH_RSRC_DWORD0";
53
54 static const char *scratch_rsrc_dword1_symbol =
55 "SCRATCH_RSRC_DWORD1";
56
57 struct si_shader_output_values
58 {
59 LLVMValueRef values[4];
60 unsigned name;
61 unsigned sid;
62 };
63
64 struct si_shader_context
65 {
66 struct radeon_llvm_context radeon_bld;
67 struct si_shader *shader;
68 struct si_screen *screen;
69 unsigned type; /* TGSI_PROCESSOR_* specifies the type of shader. */
70 int param_streamout_config;
71 int param_streamout_write_index;
72 int param_streamout_offset[4];
73 int param_vertex_id;
74 int param_instance_id;
75 LLVMValueRef const_md;
76 LLVMValueRef const_resource[SI_NUM_CONST_BUFFERS];
77 LLVMValueRef ddxy_lds;
78 LLVMValueRef *constants[SI_NUM_CONST_BUFFERS];
79 LLVMValueRef resources[SI_NUM_SAMPLER_VIEWS];
80 LLVMValueRef samplers[SI_NUM_SAMPLER_STATES];
81 LLVMValueRef so_buffers[4];
82 LLVMValueRef esgs_ring;
83 LLVMValueRef gsvs_ring;
84 LLVMValueRef gs_next_vertex;
85 };
86
87 static struct si_shader_context * si_shader_context(
88 struct lp_build_tgsi_context * bld_base)
89 {
90 return (struct si_shader_context *)bld_base;
91 }
92
93
94 #define PERSPECTIVE_BASE 0
95 #define LINEAR_BASE 9
96
97 #define SAMPLE_OFFSET 0
98 #define CENTER_OFFSET 2
99 #define CENTROID_OFSET 4
100
101 #define USE_SGPR_MAX_SUFFIX_LEN 5
102 #define CONST_ADDR_SPACE 2
103 #define LOCAL_ADDR_SPACE 3
104 #define USER_SGPR_ADDR_SPACE 8
105
106
107 #define SENDMSG_GS 2
108 #define SENDMSG_GS_DONE 3
109
110 #define SENDMSG_GS_OP_NOP (0 << 4)
111 #define SENDMSG_GS_OP_CUT (1 << 4)
112 #define SENDMSG_GS_OP_EMIT (2 << 4)
113 #define SENDMSG_GS_OP_EMIT_CUT (3 << 4)
114
115 /**
116 * Returns a unique index for a semantic name and index. The index must be
117 * less than 64, so that a 64-bit bitmask of used inputs or outputs can be
118 * calculated.
119 */
120 unsigned si_shader_io_get_unique_index(unsigned semantic_name, unsigned index)
121 {
122 switch (semantic_name) {
123 case TGSI_SEMANTIC_POSITION:
124 return 0;
125 case TGSI_SEMANTIC_PSIZE:
126 return 1;
127 case TGSI_SEMANTIC_CLIPDIST:
128 assert(index <= 1);
129 return 2 + index;
130 case TGSI_SEMANTIC_CLIPVERTEX:
131 return 4;
132 case TGSI_SEMANTIC_COLOR:
133 assert(index <= 1);
134 return 5 + index;
135 case TGSI_SEMANTIC_BCOLOR:
136 assert(index <= 1);
137 return 7 + index;
138 case TGSI_SEMANTIC_FOG:
139 return 9;
140 case TGSI_SEMANTIC_EDGEFLAG:
141 return 10;
142 case TGSI_SEMANTIC_GENERIC:
143 assert(index <= 63-11);
144 return 11 + index;
145 default:
146 assert(0);
147 return 63;
148 }
149 }
150
151 /**
152 * Given a semantic name and index of a parameter and a mask of used parameters
153 * (inputs or outputs), return the index of the parameter in the list of all
154 * used parameters.
155 *
156 * For example, assume this list of parameters:
157 * POSITION, PSIZE, GENERIC0, GENERIC2
158 * which has the mask:
159 * 11000000000101
160 * Then:
161 * querying POSITION returns 0,
162 * querying PSIZE returns 1,
163 * querying GENERIC0 returns 2,
164 * querying GENERIC2 returns 3.
165 *
166 * Which can be used as an offset to a parameter buffer in units of vec4s.
167 */
168 static int get_param_index(unsigned semantic_name, unsigned index,
169 uint64_t mask)
170 {
171 unsigned unique_index = si_shader_io_get_unique_index(semantic_name, index);
172 int i, param_index = 0;
173
174 /* If not present... */
175 if (!((1llu << unique_index) & mask))
176 return -1;
177
178 for (i = 0; mask; i++) {
179 uint64_t bit = 1llu << i;
180
181 if (bit & mask) {
182 if (i == unique_index)
183 return param_index;
184
185 mask &= ~bit;
186 param_index++;
187 }
188 }
189
190 assert(!"unreachable");
191 return -1;
192 }
193
194 /**
195 * Build an LLVM bytecode indexed load using LLVMBuildGEP + LLVMBuildLoad.
196 * It's equivalent to doing a load from &base_ptr[index].
197 *
198 * \param base_ptr Where the array starts.
199 * \param index The element index into the array.
200 */
201 static LLVMValueRef build_indexed_load(struct si_shader_context *si_shader_ctx,
202 LLVMValueRef base_ptr, LLVMValueRef index)
203 {
204 struct lp_build_tgsi_context *bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
205 struct gallivm_state *gallivm = bld_base->base.gallivm;
206 LLVMValueRef indices[2], pointer;
207
208 indices[0] = bld_base->uint_bld.zero;
209 indices[1] = index;
210
211 pointer = LLVMBuildGEP(gallivm->builder, base_ptr, indices, 2, "");
212 return LLVMBuildLoad(gallivm->builder, pointer, "");
213 }
214
215 /**
216 * Do a load from &base_ptr[index], but also add a flag that it's loading
217 * a constant.
218 */
219 static LLVMValueRef build_indexed_load_const(
220 struct si_shader_context * si_shader_ctx,
221 LLVMValueRef base_ptr, LLVMValueRef index)
222 {
223 LLVMValueRef result = build_indexed_load(si_shader_ctx, base_ptr, index);
224 LLVMSetMetadata(result, 1, si_shader_ctx->const_md);
225 return result;
226 }
227
228 static LLVMValueRef get_instance_index_for_fetch(
229 struct radeon_llvm_context * radeon_bld,
230 unsigned divisor)
231 {
232 struct si_shader_context *si_shader_ctx =
233 si_shader_context(&radeon_bld->soa.bld_base);
234 struct gallivm_state * gallivm = radeon_bld->soa.bld_base.base.gallivm;
235
236 LLVMValueRef result = LLVMGetParam(radeon_bld->main_fn,
237 si_shader_ctx->param_instance_id);
238
239 /* The division must be done before START_INSTANCE is added. */
240 if (divisor > 1)
241 result = LLVMBuildUDiv(gallivm->builder, result,
242 lp_build_const_int32(gallivm, divisor), "");
243
244 return LLVMBuildAdd(gallivm->builder, result, LLVMGetParam(
245 radeon_bld->main_fn, SI_PARAM_START_INSTANCE), "");
246 }
247
248 static void declare_input_vs(
249 struct radeon_llvm_context *radeon_bld,
250 unsigned input_index,
251 const struct tgsi_full_declaration *decl)
252 {
253 struct lp_build_context *base = &radeon_bld->soa.bld_base.base;
254 struct gallivm_state *gallivm = base->gallivm;
255 struct si_shader_context *si_shader_ctx =
256 si_shader_context(&radeon_bld->soa.bld_base);
257 unsigned divisor = si_shader_ctx->shader->key.vs.instance_divisors[input_index];
258
259 unsigned chan;
260
261 LLVMValueRef t_list_ptr;
262 LLVMValueRef t_offset;
263 LLVMValueRef t_list;
264 LLVMValueRef attribute_offset;
265 LLVMValueRef buffer_index;
266 LLVMValueRef args[3];
267 LLVMTypeRef vec4_type;
268 LLVMValueRef input;
269
270 /* Load the T list */
271 t_list_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_VERTEX_BUFFER);
272
273 t_offset = lp_build_const_int32(gallivm, input_index);
274
275 t_list = build_indexed_load_const(si_shader_ctx, t_list_ptr, t_offset);
276
277 /* Build the attribute offset */
278 attribute_offset = lp_build_const_int32(gallivm, 0);
279
280 if (divisor) {
281 /* Build index from instance ID, start instance and divisor */
282 si_shader_ctx->shader->uses_instanceid = true;
283 buffer_index = get_instance_index_for_fetch(&si_shader_ctx->radeon_bld, divisor);
284 } else {
285 /* Load the buffer index for vertices. */
286 LLVMValueRef vertex_id = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
287 si_shader_ctx->param_vertex_id);
288 LLVMValueRef base_vertex = LLVMGetParam(radeon_bld->main_fn,
289 SI_PARAM_BASE_VERTEX);
290 buffer_index = LLVMBuildAdd(gallivm->builder, base_vertex, vertex_id, "");
291 }
292
293 vec4_type = LLVMVectorType(base->elem_type, 4);
294 args[0] = t_list;
295 args[1] = attribute_offset;
296 args[2] = buffer_index;
297 input = build_intrinsic(gallivm->builder,
298 "llvm.SI.vs.load.input", vec4_type, args, 3,
299 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
300
301 /* Break up the vec4 into individual components */
302 for (chan = 0; chan < 4; chan++) {
303 LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan);
304 /* XXX: Use a helper function for this. There is one in
305 * tgsi_llvm.c. */
306 si_shader_ctx->radeon_bld.inputs[radeon_llvm_reg_index_soa(input_index, chan)] =
307 LLVMBuildExtractElement(gallivm->builder,
308 input, llvm_chan, "");
309 }
310 }
311
312 static LLVMValueRef fetch_input_gs(
313 struct lp_build_tgsi_context *bld_base,
314 const struct tgsi_full_src_register *reg,
315 enum tgsi_opcode_type type,
316 unsigned swizzle)
317 {
318 struct lp_build_context *base = &bld_base->base;
319 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
320 struct si_shader *shader = si_shader_ctx->shader;
321 struct lp_build_context *uint = &si_shader_ctx->radeon_bld.soa.bld_base.uint_bld;
322 struct gallivm_state *gallivm = base->gallivm;
323 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
324 LLVMValueRef vtx_offset;
325 LLVMValueRef args[9];
326 unsigned vtx_offset_param;
327 struct tgsi_shader_info *info = &shader->selector->info;
328 unsigned semantic_name = info->input_semantic_name[reg->Register.Index];
329 unsigned semantic_index = info->input_semantic_index[reg->Register.Index];
330
331 if (swizzle != ~0 && semantic_name == TGSI_SEMANTIC_PRIMID) {
332 if (swizzle == 0)
333 return LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
334 SI_PARAM_PRIMITIVE_ID);
335 else
336 return uint->zero;
337 }
338
339 if (!reg->Register.Dimension)
340 return NULL;
341
342 if (swizzle == ~0) {
343 LLVMValueRef values[TGSI_NUM_CHANNELS];
344 unsigned chan;
345 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
346 values[chan] = fetch_input_gs(bld_base, reg, type, chan);
347 }
348 return lp_build_gather_values(bld_base->base.gallivm, values,
349 TGSI_NUM_CHANNELS);
350 }
351
352 /* Get the vertex offset parameter */
353 vtx_offset_param = reg->Dimension.Index;
354 if (vtx_offset_param < 2) {
355 vtx_offset_param += SI_PARAM_VTX0_OFFSET;
356 } else {
357 assert(vtx_offset_param < 6);
358 vtx_offset_param += SI_PARAM_VTX2_OFFSET - 2;
359 }
360 vtx_offset = lp_build_mul_imm(uint,
361 LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
362 vtx_offset_param),
363 4);
364
365 args[0] = si_shader_ctx->esgs_ring;
366 args[1] = vtx_offset;
367 args[2] = lp_build_const_int32(gallivm,
368 (get_param_index(semantic_name, semantic_index,
369 shader->selector->gs_used_inputs) * 4 +
370 swizzle) * 256);
371 args[3] = uint->zero;
372 args[4] = uint->one; /* OFFEN */
373 args[5] = uint->zero; /* IDXEN */
374 args[6] = uint->one; /* GLC */
375 args[7] = uint->zero; /* SLC */
376 args[8] = uint->zero; /* TFE */
377
378 return LLVMBuildBitCast(gallivm->builder,
379 build_intrinsic(gallivm->builder,
380 "llvm.SI.buffer.load.dword.i32.i32",
381 i32, args, 9,
382 LLVMReadOnlyAttribute | LLVMNoUnwindAttribute),
383 tgsi2llvmtype(bld_base, type), "");
384 }
385
386 static void declare_input_fs(
387 struct radeon_llvm_context *radeon_bld,
388 unsigned input_index,
389 const struct tgsi_full_declaration *decl)
390 {
391 struct lp_build_context *base = &radeon_bld->soa.bld_base.base;
392 struct si_shader_context *si_shader_ctx =
393 si_shader_context(&radeon_bld->soa.bld_base);
394 struct si_shader *shader = si_shader_ctx->shader;
395 struct lp_build_context *uint = &radeon_bld->soa.bld_base.uint_bld;
396 struct gallivm_state *gallivm = base->gallivm;
397 LLVMTypeRef input_type = LLVMFloatTypeInContext(gallivm->context);
398 LLVMValueRef main_fn = radeon_bld->main_fn;
399
400 LLVMValueRef interp_param;
401 const char * intr_name;
402
403 /* This value is:
404 * [15:0] NewPrimMask (Bit mask for each quad. It is set it the
405 * quad begins a new primitive. Bit 0 always needs
406 * to be unset)
407 * [32:16] ParamOffset
408 *
409 */
410 LLVMValueRef params = LLVMGetParam(main_fn, SI_PARAM_PRIM_MASK);
411 LLVMValueRef attr_number;
412
413 unsigned chan;
414
415 if (decl->Semantic.Name == TGSI_SEMANTIC_POSITION) {
416 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
417 unsigned soa_index =
418 radeon_llvm_reg_index_soa(input_index, chan);
419 radeon_bld->inputs[soa_index] =
420 LLVMGetParam(main_fn, SI_PARAM_POS_X_FLOAT + chan);
421
422 if (chan == 3)
423 /* RCP for fragcoord.w */
424 radeon_bld->inputs[soa_index] =
425 LLVMBuildFDiv(gallivm->builder,
426 lp_build_const_float(gallivm, 1.0f),
427 radeon_bld->inputs[soa_index],
428 "");
429 }
430 return;
431 }
432
433 if (decl->Semantic.Name == TGSI_SEMANTIC_FACE) {
434 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 0)] =
435 LLVMGetParam(main_fn, SI_PARAM_FRONT_FACE);
436 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 1)] =
437 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 2)] =
438 lp_build_const_float(gallivm, 0.0f);
439 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 3)] =
440 lp_build_const_float(gallivm, 1.0f);
441
442 return;
443 }
444
445 shader->ps_input_param_offset[input_index] = shader->nparam++;
446 attr_number = lp_build_const_int32(gallivm,
447 shader->ps_input_param_offset[input_index]);
448
449 switch (decl->Interp.Interpolate) {
450 case TGSI_INTERPOLATE_CONSTANT:
451 interp_param = 0;
452 break;
453 case TGSI_INTERPOLATE_LINEAR:
454 if (decl->Interp.Location == TGSI_INTERPOLATE_LOC_SAMPLE)
455 interp_param = LLVMGetParam(main_fn, SI_PARAM_LINEAR_SAMPLE);
456 else if (decl->Interp.Location == TGSI_INTERPOLATE_LOC_CENTROID)
457 interp_param = LLVMGetParam(main_fn, SI_PARAM_LINEAR_CENTROID);
458 else
459 interp_param = LLVMGetParam(main_fn, SI_PARAM_LINEAR_CENTER);
460 break;
461 case TGSI_INTERPOLATE_COLOR:
462 case TGSI_INTERPOLATE_PERSPECTIVE:
463 if (decl->Interp.Location == TGSI_INTERPOLATE_LOC_SAMPLE)
464 interp_param = LLVMGetParam(main_fn, SI_PARAM_PERSP_SAMPLE);
465 else if (decl->Interp.Location == TGSI_INTERPOLATE_LOC_CENTROID)
466 interp_param = LLVMGetParam(main_fn, SI_PARAM_PERSP_CENTROID);
467 else
468 interp_param = LLVMGetParam(main_fn, SI_PARAM_PERSP_CENTER);
469 break;
470 default:
471 fprintf(stderr, "Warning: Unhandled interpolation mode.\n");
472 return;
473 }
474
475 /* fs.constant returns the param from the middle vertex, so it's not
476 * really useful for flat shading. It's meant to be used for custom
477 * interpolation (but the intrinsic can't fetch from the other two
478 * vertices).
479 *
480 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
481 * to do the right thing. The only reason we use fs.constant is that
482 * fs.interp cannot be used on integers, because they can be equal
483 * to NaN.
484 */
485 intr_name = interp_param ? "llvm.SI.fs.interp" : "llvm.SI.fs.constant";
486
487 if (decl->Semantic.Name == TGSI_SEMANTIC_COLOR &&
488 si_shader_ctx->shader->key.ps.color_two_side) {
489 LLVMValueRef args[4];
490 LLVMValueRef face, is_face_positive;
491 LLVMValueRef back_attr_number =
492 lp_build_const_int32(gallivm,
493 shader->ps_input_param_offset[input_index] + 1);
494
495 face = LLVMGetParam(main_fn, SI_PARAM_FRONT_FACE);
496
497 is_face_positive = LLVMBuildFCmp(gallivm->builder,
498 LLVMRealOGT, face,
499 lp_build_const_float(gallivm, 0.0f),
500 "");
501
502 args[2] = params;
503 args[3] = interp_param;
504 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
505 LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan);
506 unsigned soa_index = radeon_llvm_reg_index_soa(input_index, chan);
507 LLVMValueRef front, back;
508
509 args[0] = llvm_chan;
510 args[1] = attr_number;
511 front = build_intrinsic(gallivm->builder, intr_name,
512 input_type, args, args[3] ? 4 : 3,
513 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
514
515 args[1] = back_attr_number;
516 back = build_intrinsic(gallivm->builder, intr_name,
517 input_type, args, args[3] ? 4 : 3,
518 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
519
520 radeon_bld->inputs[soa_index] =
521 LLVMBuildSelect(gallivm->builder,
522 is_face_positive,
523 front,
524 back,
525 "");
526 }
527
528 shader->nparam++;
529 } else if (decl->Semantic.Name == TGSI_SEMANTIC_FOG) {
530 LLVMValueRef args[4];
531
532 args[0] = uint->zero;
533 args[1] = attr_number;
534 args[2] = params;
535 args[3] = interp_param;
536 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 0)] =
537 build_intrinsic(gallivm->builder, intr_name,
538 input_type, args, args[3] ? 4 : 3,
539 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
540 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 1)] =
541 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 2)] =
542 lp_build_const_float(gallivm, 0.0f);
543 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 3)] =
544 lp_build_const_float(gallivm, 1.0f);
545 } else {
546 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
547 LLVMValueRef args[4];
548 LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan);
549 unsigned soa_index = radeon_llvm_reg_index_soa(input_index, chan);
550 args[0] = llvm_chan;
551 args[1] = attr_number;
552 args[2] = params;
553 args[3] = interp_param;
554 radeon_bld->inputs[soa_index] =
555 build_intrinsic(gallivm->builder, intr_name,
556 input_type, args, args[3] ? 4 : 3,
557 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
558 }
559 }
560 }
561
562 static LLVMValueRef get_sample_id(struct radeon_llvm_context *radeon_bld)
563 {
564 struct gallivm_state *gallivm = &radeon_bld->gallivm;
565 LLVMValueRef value = LLVMGetParam(radeon_bld->main_fn,
566 SI_PARAM_ANCILLARY);
567 value = LLVMBuildLShr(gallivm->builder, value,
568 lp_build_const_int32(gallivm, 8), "");
569 value = LLVMBuildAnd(gallivm->builder, value,
570 lp_build_const_int32(gallivm, 0xf), "");
571 return value;
572 }
573
574 /**
575 * Load a dword from a constant buffer.
576 */
577 static LLVMValueRef buffer_load_const(LLVMBuilderRef builder, LLVMValueRef resource,
578 LLVMValueRef offset, LLVMTypeRef return_type)
579 {
580 LLVMValueRef args[2] = {resource, offset};
581
582 return build_intrinsic(builder, "llvm.SI.load.const", return_type, args, 2,
583 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
584 }
585
586 static void declare_system_value(
587 struct radeon_llvm_context * radeon_bld,
588 unsigned index,
589 const struct tgsi_full_declaration *decl)
590 {
591 struct si_shader_context *si_shader_ctx =
592 si_shader_context(&radeon_bld->soa.bld_base);
593 struct lp_build_context *uint_bld = &radeon_bld->soa.bld_base.uint_bld;
594 struct gallivm_state *gallivm = &radeon_bld->gallivm;
595 LLVMValueRef value = 0;
596
597 switch (decl->Semantic.Name) {
598 case TGSI_SEMANTIC_INSTANCEID:
599 value = LLVMGetParam(radeon_bld->main_fn,
600 si_shader_ctx->param_instance_id);
601 break;
602
603 case TGSI_SEMANTIC_VERTEXID:
604 value = LLVMBuildAdd(gallivm->builder,
605 LLVMGetParam(radeon_bld->main_fn,
606 si_shader_ctx->param_vertex_id),
607 LLVMGetParam(radeon_bld->main_fn,
608 SI_PARAM_BASE_VERTEX), "");
609 break;
610
611 case TGSI_SEMANTIC_VERTEXID_NOBASE:
612 value = LLVMGetParam(radeon_bld->main_fn,
613 si_shader_ctx->param_vertex_id);
614 break;
615
616 case TGSI_SEMANTIC_BASEVERTEX:
617 value = LLVMGetParam(radeon_bld->main_fn,
618 SI_PARAM_BASE_VERTEX);
619 break;
620
621 case TGSI_SEMANTIC_SAMPLEID:
622 value = get_sample_id(radeon_bld);
623 break;
624
625 case TGSI_SEMANTIC_SAMPLEPOS:
626 {
627 LLVMBuilderRef builder = gallivm->builder;
628 LLVMValueRef desc = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_CONST);
629 LLVMValueRef buf_index = lp_build_const_int32(gallivm, SI_DRIVER_STATE_CONST_BUF);
630 LLVMValueRef resource = build_indexed_load_const(si_shader_ctx, desc, buf_index);
631
632 /* offset = sample_id * 8 (8 = 2 floats containing samplepos.xy) */
633 LLVMValueRef offset0 = lp_build_mul_imm(uint_bld, get_sample_id(radeon_bld), 8);
634 LLVMValueRef offset1 = LLVMBuildAdd(builder, offset0, lp_build_const_int32(gallivm, 4), "");
635
636 LLVMValueRef pos[4] = {
637 buffer_load_const(builder, resource, offset0, radeon_bld->soa.bld_base.base.elem_type),
638 buffer_load_const(builder, resource, offset1, radeon_bld->soa.bld_base.base.elem_type),
639 lp_build_const_float(gallivm, 0),
640 lp_build_const_float(gallivm, 0)
641 };
642 value = lp_build_gather_values(gallivm, pos, 4);
643 break;
644 }
645
646 default:
647 assert(!"unknown system value");
648 return;
649 }
650
651 radeon_bld->system_values[index] = value;
652 }
653
654 static LLVMValueRef fetch_constant(
655 struct lp_build_tgsi_context * bld_base,
656 const struct tgsi_full_src_register *reg,
657 enum tgsi_opcode_type type,
658 unsigned swizzle)
659 {
660 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
661 struct lp_build_context * base = &bld_base->base;
662 const struct tgsi_ind_register *ireg = &reg->Indirect;
663 unsigned buf, idx;
664
665 LLVMValueRef addr;
666 LLVMValueRef result;
667
668 if (swizzle == LP_CHAN_ALL) {
669 unsigned chan;
670 LLVMValueRef values[4];
671 for (chan = 0; chan < TGSI_NUM_CHANNELS; ++chan)
672 values[chan] = fetch_constant(bld_base, reg, type, chan);
673
674 return lp_build_gather_values(bld_base->base.gallivm, values, 4);
675 }
676
677 buf = reg->Register.Dimension ? reg->Dimension.Index : 0;
678 idx = reg->Register.Index * 4 + swizzle;
679
680 if (!reg->Register.Indirect)
681 return bitcast(bld_base, type, si_shader_ctx->constants[buf][idx]);
682
683 addr = si_shader_ctx->radeon_bld.soa.addr[ireg->Index][ireg->Swizzle];
684 addr = LLVMBuildLoad(base->gallivm->builder, addr, "load addr reg");
685 addr = lp_build_mul_imm(&bld_base->uint_bld, addr, 16);
686 addr = lp_build_add(&bld_base->uint_bld, addr,
687 lp_build_const_int32(base->gallivm, idx * 4));
688
689 result = buffer_load_const(base->gallivm->builder, si_shader_ctx->const_resource[buf],
690 addr, base->elem_type);
691
692 return bitcast(bld_base, type, result);
693 }
694
695 /* Initialize arguments for the shader export intrinsic */
696 static void si_llvm_init_export_args(struct lp_build_tgsi_context *bld_base,
697 LLVMValueRef *values,
698 unsigned target,
699 LLVMValueRef *args)
700 {
701 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
702 struct lp_build_context *uint =
703 &si_shader_ctx->radeon_bld.soa.bld_base.uint_bld;
704 struct lp_build_context *base = &bld_base->base;
705 unsigned compressed = 0;
706 unsigned chan;
707
708 if (si_shader_ctx->type == TGSI_PROCESSOR_FRAGMENT) {
709 int cbuf = target - V_008DFC_SQ_EXP_MRT;
710
711 if (cbuf >= 0 && cbuf < 8) {
712 compressed = (si_shader_ctx->shader->key.ps.export_16bpc >> cbuf) & 0x1;
713
714 if (compressed)
715 si_shader_ctx->shader->spi_shader_col_format |=
716 V_028714_SPI_SHADER_FP16_ABGR << (4 * cbuf);
717 else
718 si_shader_ctx->shader->spi_shader_col_format |=
719 V_028714_SPI_SHADER_32_ABGR << (4 * cbuf);
720
721 si_shader_ctx->shader->cb_shader_mask |= 0xf << (4 * cbuf);
722 }
723 }
724
725 if (compressed) {
726 /* Pixel shader needs to pack output values before export */
727 for (chan = 0; chan < 2; chan++ ) {
728 args[0] = values[2 * chan];
729 args[1] = values[2 * chan + 1];
730 args[chan + 5] =
731 build_intrinsic(base->gallivm->builder,
732 "llvm.SI.packf16",
733 LLVMInt32TypeInContext(base->gallivm->context),
734 args, 2,
735 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
736 args[chan + 7] = args[chan + 5] =
737 LLVMBuildBitCast(base->gallivm->builder,
738 args[chan + 5],
739 LLVMFloatTypeInContext(base->gallivm->context),
740 "");
741 }
742
743 /* Set COMPR flag */
744 args[4] = uint->one;
745 } else {
746 for (chan = 0; chan < 4; chan++ )
747 /* +5 because the first output value will be
748 * the 6th argument to the intrinsic. */
749 args[chan + 5] = values[chan];
750
751 /* Clear COMPR flag */
752 args[4] = uint->zero;
753 }
754
755 /* XXX: This controls which components of the output
756 * registers actually get exported. (e.g bit 0 means export
757 * X component, bit 1 means export Y component, etc.) I'm
758 * hard coding this to 0xf for now. In the future, we might
759 * want to do something else. */
760 args[0] = lp_build_const_int32(base->gallivm, 0xf);
761
762 /* Specify whether the EXEC mask represents the valid mask */
763 args[1] = uint->zero;
764
765 /* Specify whether this is the last export */
766 args[2] = uint->zero;
767
768 /* Specify the target we are exporting */
769 args[3] = lp_build_const_int32(base->gallivm, target);
770
771 /* XXX: We probably need to keep track of the output
772 * values, so we know what we are passing to the next
773 * stage. */
774 }
775
776 /* Load from output pointers and initialize arguments for the shader export intrinsic */
777 static void si_llvm_init_export_args_load(struct lp_build_tgsi_context *bld_base,
778 LLVMValueRef *out_ptr,
779 unsigned target,
780 LLVMValueRef *args)
781 {
782 struct gallivm_state *gallivm = bld_base->base.gallivm;
783 LLVMValueRef values[4];
784 int i;
785
786 for (i = 0; i < 4; i++)
787 values[i] = LLVMBuildLoad(gallivm->builder, out_ptr[i], "");
788
789 si_llvm_init_export_args(bld_base, values, target, args);
790 }
791
792 static void si_alpha_test(struct lp_build_tgsi_context *bld_base,
793 LLVMValueRef *out_ptr)
794 {
795 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
796 struct gallivm_state *gallivm = bld_base->base.gallivm;
797
798 if (si_shader_ctx->shader->key.ps.alpha_func != PIPE_FUNC_NEVER) {
799 LLVMValueRef alpha_ref = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
800 SI_PARAM_ALPHA_REF);
801
802 LLVMValueRef alpha_pass =
803 lp_build_cmp(&bld_base->base,
804 si_shader_ctx->shader->key.ps.alpha_func,
805 LLVMBuildLoad(gallivm->builder, out_ptr[3], ""),
806 alpha_ref);
807 LLVMValueRef arg =
808 lp_build_select(&bld_base->base,
809 alpha_pass,
810 lp_build_const_float(gallivm, 1.0f),
811 lp_build_const_float(gallivm, -1.0f));
812
813 build_intrinsic(gallivm->builder,
814 "llvm.AMDGPU.kill",
815 LLVMVoidTypeInContext(gallivm->context),
816 &arg, 1, 0);
817 } else {
818 build_intrinsic(gallivm->builder,
819 "llvm.AMDGPU.kilp",
820 LLVMVoidTypeInContext(gallivm->context),
821 NULL, 0, 0);
822 }
823
824 si_shader_ctx->shader->db_shader_control |= S_02880C_KILL_ENABLE(1);
825 }
826
827 static void si_llvm_emit_clipvertex(struct lp_build_tgsi_context * bld_base,
828 LLVMValueRef (*pos)[9], LLVMValueRef *out_elts)
829 {
830 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
831 struct lp_build_context *base = &bld_base->base;
832 struct lp_build_context *uint = &si_shader_ctx->radeon_bld.soa.bld_base.uint_bld;
833 unsigned reg_index;
834 unsigned chan;
835 unsigned const_chan;
836 LLVMValueRef base_elt;
837 LLVMValueRef ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_CONST);
838 LLVMValueRef constbuf_index = lp_build_const_int32(base->gallivm, SI_DRIVER_STATE_CONST_BUF);
839 LLVMValueRef const_resource = build_indexed_load_const(si_shader_ctx, ptr, constbuf_index);
840
841 for (reg_index = 0; reg_index < 2; reg_index ++) {
842 LLVMValueRef *args = pos[2 + reg_index];
843
844 args[5] =
845 args[6] =
846 args[7] =
847 args[8] = lp_build_const_float(base->gallivm, 0.0f);
848
849 /* Compute dot products of position and user clip plane vectors */
850 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
851 for (const_chan = 0; const_chan < TGSI_NUM_CHANNELS; const_chan++) {
852 args[1] = lp_build_const_int32(base->gallivm,
853 ((reg_index * 4 + chan) * 4 +
854 const_chan) * 4);
855 base_elt = buffer_load_const(base->gallivm->builder, const_resource,
856 args[1], base->elem_type);
857 args[5 + chan] =
858 lp_build_add(base, args[5 + chan],
859 lp_build_mul(base, base_elt,
860 out_elts[const_chan]));
861 }
862 }
863
864 args[0] = lp_build_const_int32(base->gallivm, 0xf);
865 args[1] = uint->zero;
866 args[2] = uint->zero;
867 args[3] = lp_build_const_int32(base->gallivm,
868 V_008DFC_SQ_EXP_POS + 2 + reg_index);
869 args[4] = uint->zero;
870 }
871 }
872
873 static void si_dump_streamout(struct pipe_stream_output_info *so)
874 {
875 unsigned i;
876
877 if (so->num_outputs)
878 fprintf(stderr, "STREAMOUT\n");
879
880 for (i = 0; i < so->num_outputs; i++) {
881 unsigned mask = ((1 << so->output[i].num_components) - 1) <<
882 so->output[i].start_component;
883 fprintf(stderr, " %i: BUF%i[%i..%i] <- OUT[%i].%s%s%s%s\n",
884 i, so->output[i].output_buffer,
885 so->output[i].dst_offset, so->output[i].dst_offset + so->output[i].num_components - 1,
886 so->output[i].register_index,
887 mask & 1 ? "x" : "",
888 mask & 2 ? "y" : "",
889 mask & 4 ? "z" : "",
890 mask & 8 ? "w" : "");
891 }
892 }
893
894 /* TBUFFER_STORE_FORMAT_{X,XY,XYZ,XYZW} <- the suffix is selected by num_channels=1..4.
895 * The type of vdata must be one of i32 (num_channels=1), v2i32 (num_channels=2),
896 * or v4i32 (num_channels=3,4). */
897 static void build_tbuffer_store(struct si_shader_context *shader,
898 LLVMValueRef rsrc,
899 LLVMValueRef vdata,
900 unsigned num_channels,
901 LLVMValueRef vaddr,
902 LLVMValueRef soffset,
903 unsigned inst_offset,
904 unsigned dfmt,
905 unsigned nfmt,
906 unsigned offen,
907 unsigned idxen,
908 unsigned glc,
909 unsigned slc,
910 unsigned tfe)
911 {
912 struct gallivm_state *gallivm = &shader->radeon_bld.gallivm;
913 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
914 LLVMValueRef args[] = {
915 rsrc,
916 vdata,
917 LLVMConstInt(i32, num_channels, 0),
918 vaddr,
919 soffset,
920 LLVMConstInt(i32, inst_offset, 0),
921 LLVMConstInt(i32, dfmt, 0),
922 LLVMConstInt(i32, nfmt, 0),
923 LLVMConstInt(i32, offen, 0),
924 LLVMConstInt(i32, idxen, 0),
925 LLVMConstInt(i32, glc, 0),
926 LLVMConstInt(i32, slc, 0),
927 LLVMConstInt(i32, tfe, 0)
928 };
929
930 /* The instruction offset field has 12 bits */
931 assert(offen || inst_offset < (1 << 12));
932
933 /* The intrinsic is overloaded, we need to add a type suffix for overloading to work. */
934 unsigned func = CLAMP(num_channels, 1, 3) - 1;
935 const char *types[] = {"i32", "v2i32", "v4i32"};
936 char name[256];
937 snprintf(name, sizeof(name), "llvm.SI.tbuffer.store.%s", types[func]);
938
939 lp_build_intrinsic(gallivm->builder, name,
940 LLVMVoidTypeInContext(gallivm->context),
941 args, Elements(args));
942 }
943
944 static void build_streamout_store(struct si_shader_context *shader,
945 LLVMValueRef rsrc,
946 LLVMValueRef vdata,
947 unsigned num_channels,
948 LLVMValueRef vaddr,
949 LLVMValueRef soffset,
950 unsigned inst_offset)
951 {
952 static unsigned dfmt[] = {
953 V_008F0C_BUF_DATA_FORMAT_32,
954 V_008F0C_BUF_DATA_FORMAT_32_32,
955 V_008F0C_BUF_DATA_FORMAT_32_32_32,
956 V_008F0C_BUF_DATA_FORMAT_32_32_32_32
957 };
958 assert(num_channels >= 1 && num_channels <= 4);
959
960 build_tbuffer_store(shader, rsrc, vdata, num_channels, vaddr, soffset,
961 inst_offset, dfmt[num_channels-1],
962 V_008F0C_BUF_NUM_FORMAT_UINT, 1, 0, 1, 1, 0);
963 }
964
965 /* On SI, the vertex shader is responsible for writing streamout data
966 * to buffers. */
967 static void si_llvm_emit_streamout(struct si_shader_context *shader,
968 struct si_shader_output_values *outputs,
969 unsigned noutput)
970 {
971 struct pipe_stream_output_info *so = &shader->shader->selector->so;
972 struct gallivm_state *gallivm = &shader->radeon_bld.gallivm;
973 LLVMBuilderRef builder = gallivm->builder;
974 int i, j;
975 struct lp_build_if_state if_ctx;
976
977 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
978
979 LLVMValueRef so_param =
980 LLVMGetParam(shader->radeon_bld.main_fn,
981 shader->param_streamout_config);
982
983 /* Get bits [22:16], i.e. (so_param >> 16) & 127; */
984 LLVMValueRef so_vtx_count =
985 LLVMBuildAnd(builder,
986 LLVMBuildLShr(builder, so_param,
987 LLVMConstInt(i32, 16, 0), ""),
988 LLVMConstInt(i32, 127, 0), "");
989
990 LLVMValueRef tid = build_intrinsic(builder, "llvm.SI.tid", i32,
991 NULL, 0, LLVMReadNoneAttribute);
992
993 /* can_emit = tid < so_vtx_count; */
994 LLVMValueRef can_emit =
995 LLVMBuildICmp(builder, LLVMIntULT, tid, so_vtx_count, "");
996
997 /* Emit the streamout code conditionally. This actually avoids
998 * out-of-bounds buffer access. The hw tells us via the SGPR
999 * (so_vtx_count) which threads are allowed to emit streamout data. */
1000 lp_build_if(&if_ctx, gallivm, can_emit);
1001 {
1002 /* The buffer offset is computed as follows:
1003 * ByteOffset = streamout_offset[buffer_id]*4 +
1004 * (streamout_write_index + thread_id)*stride[buffer_id] +
1005 * attrib_offset
1006 */
1007
1008 LLVMValueRef so_write_index =
1009 LLVMGetParam(shader->radeon_bld.main_fn,
1010 shader->param_streamout_write_index);
1011
1012 /* Compute (streamout_write_index + thread_id). */
1013 so_write_index = LLVMBuildAdd(builder, so_write_index, tid, "");
1014
1015 /* Compute the write offset for each enabled buffer. */
1016 LLVMValueRef so_write_offset[4] = {};
1017 for (i = 0; i < 4; i++) {
1018 if (!so->stride[i])
1019 continue;
1020
1021 LLVMValueRef so_offset = LLVMGetParam(shader->radeon_bld.main_fn,
1022 shader->param_streamout_offset[i]);
1023 so_offset = LLVMBuildMul(builder, so_offset, LLVMConstInt(i32, 4, 0), "");
1024
1025 so_write_offset[i] = LLVMBuildMul(builder, so_write_index,
1026 LLVMConstInt(i32, so->stride[i]*4, 0), "");
1027 so_write_offset[i] = LLVMBuildAdd(builder, so_write_offset[i], so_offset, "");
1028 }
1029
1030 /* Write streamout data. */
1031 for (i = 0; i < so->num_outputs; i++) {
1032 unsigned buf_idx = so->output[i].output_buffer;
1033 unsigned reg = so->output[i].register_index;
1034 unsigned start = so->output[i].start_component;
1035 unsigned num_comps = so->output[i].num_components;
1036 LLVMValueRef out[4];
1037
1038 assert(num_comps && num_comps <= 4);
1039 if (!num_comps || num_comps > 4)
1040 continue;
1041
1042 if (reg >= noutput)
1043 continue;
1044
1045 /* Load the output as int. */
1046 for (j = 0; j < num_comps; j++) {
1047 out[j] = LLVMBuildBitCast(builder,
1048 outputs[reg].values[start+j],
1049 i32, "");
1050 }
1051
1052 /* Pack the output. */
1053 LLVMValueRef vdata = NULL;
1054
1055 switch (num_comps) {
1056 case 1: /* as i32 */
1057 vdata = out[0];
1058 break;
1059 case 2: /* as v2i32 */
1060 case 3: /* as v4i32 (aligned to 4) */
1061 case 4: /* as v4i32 */
1062 vdata = LLVMGetUndef(LLVMVectorType(i32, util_next_power_of_two(num_comps)));
1063 for (j = 0; j < num_comps; j++) {
1064 vdata = LLVMBuildInsertElement(builder, vdata, out[j],
1065 LLVMConstInt(i32, j, 0), "");
1066 }
1067 break;
1068 }
1069
1070 build_streamout_store(shader, shader->so_buffers[buf_idx],
1071 vdata, num_comps,
1072 so_write_offset[buf_idx],
1073 LLVMConstInt(i32, 0, 0),
1074 so->output[i].dst_offset*4);
1075 }
1076 }
1077 lp_build_endif(&if_ctx);
1078 }
1079
1080
1081 /* Generate export instructions for hardware VS shader stage */
1082 static void si_llvm_export_vs(struct lp_build_tgsi_context *bld_base,
1083 struct si_shader_output_values *outputs,
1084 unsigned noutput)
1085 {
1086 struct si_shader_context * si_shader_ctx = si_shader_context(bld_base);
1087 struct si_shader * shader = si_shader_ctx->shader;
1088 struct lp_build_context * base = &bld_base->base;
1089 struct lp_build_context * uint =
1090 &si_shader_ctx->radeon_bld.soa.bld_base.uint_bld;
1091 LLVMValueRef args[9];
1092 LLVMValueRef pos_args[4][9] = { { 0 } };
1093 LLVMValueRef psize_value = NULL, edgeflag_value = NULL, layer_value = NULL;
1094 unsigned semantic_name, semantic_index;
1095 unsigned target;
1096 unsigned param_count = 0;
1097 unsigned pos_idx;
1098 int i;
1099
1100 if (outputs && si_shader_ctx->shader->selector->so.num_outputs) {
1101 si_llvm_emit_streamout(si_shader_ctx, outputs, noutput);
1102 }
1103
1104 for (i = 0; i < noutput; i++) {
1105 semantic_name = outputs[i].name;
1106 semantic_index = outputs[i].sid;
1107
1108 handle_semantic:
1109 /* Select the correct target */
1110 switch(semantic_name) {
1111 case TGSI_SEMANTIC_PSIZE:
1112 psize_value = outputs[i].values[0];
1113 continue;
1114 case TGSI_SEMANTIC_EDGEFLAG:
1115 edgeflag_value = outputs[i].values[0];
1116 continue;
1117 case TGSI_SEMANTIC_LAYER:
1118 layer_value = outputs[i].values[0];
1119 continue;
1120 case TGSI_SEMANTIC_POSITION:
1121 target = V_008DFC_SQ_EXP_POS;
1122 break;
1123 case TGSI_SEMANTIC_COLOR:
1124 case TGSI_SEMANTIC_BCOLOR:
1125 target = V_008DFC_SQ_EXP_PARAM + param_count;
1126 shader->vs_output_param_offset[i] = param_count;
1127 param_count++;
1128 break;
1129 case TGSI_SEMANTIC_CLIPDIST:
1130 target = V_008DFC_SQ_EXP_POS + 2 + semantic_index;
1131 break;
1132 case TGSI_SEMANTIC_CLIPVERTEX:
1133 si_llvm_emit_clipvertex(bld_base, pos_args, outputs[i].values);
1134 continue;
1135 case TGSI_SEMANTIC_PRIMID:
1136 case TGSI_SEMANTIC_FOG:
1137 case TGSI_SEMANTIC_GENERIC:
1138 target = V_008DFC_SQ_EXP_PARAM + param_count;
1139 shader->vs_output_param_offset[i] = param_count;
1140 param_count++;
1141 break;
1142 default:
1143 target = 0;
1144 fprintf(stderr,
1145 "Warning: SI unhandled vs output type:%d\n",
1146 semantic_name);
1147 }
1148
1149 si_llvm_init_export_args(bld_base, outputs[i].values, target, args);
1150
1151 if (target >= V_008DFC_SQ_EXP_POS &&
1152 target <= (V_008DFC_SQ_EXP_POS + 3)) {
1153 memcpy(pos_args[target - V_008DFC_SQ_EXP_POS],
1154 args, sizeof(args));
1155 } else {
1156 lp_build_intrinsic(base->gallivm->builder,
1157 "llvm.SI.export",
1158 LLVMVoidTypeInContext(base->gallivm->context),
1159 args, 9);
1160 }
1161
1162 if (semantic_name == TGSI_SEMANTIC_CLIPDIST) {
1163 semantic_name = TGSI_SEMANTIC_GENERIC;
1164 goto handle_semantic;
1165 }
1166 }
1167
1168 /* We need to add the position output manually if it's missing. */
1169 if (!pos_args[0][0]) {
1170 pos_args[0][0] = lp_build_const_int32(base->gallivm, 0xf); /* writemask */
1171 pos_args[0][1] = uint->zero; /* EXEC mask */
1172 pos_args[0][2] = uint->zero; /* last export? */
1173 pos_args[0][3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_POS);
1174 pos_args[0][4] = uint->zero; /* COMPR flag */
1175 pos_args[0][5] = base->zero; /* X */
1176 pos_args[0][6] = base->zero; /* Y */
1177 pos_args[0][7] = base->zero; /* Z */
1178 pos_args[0][8] = base->one; /* W */
1179 }
1180
1181 /* Write the misc vector (point size, edgeflag, layer, viewport). */
1182 if (shader->selector->info.writes_psize ||
1183 shader->selector->info.writes_edgeflag ||
1184 shader->selector->info.writes_layer) {
1185 pos_args[1][0] = lp_build_const_int32(base->gallivm, /* writemask */
1186 shader->selector->info.writes_psize |
1187 (shader->selector->info.writes_edgeflag << 1) |
1188 (shader->selector->info.writes_layer << 2));
1189 pos_args[1][1] = uint->zero; /* EXEC mask */
1190 pos_args[1][2] = uint->zero; /* last export? */
1191 pos_args[1][3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_POS + 1);
1192 pos_args[1][4] = uint->zero; /* COMPR flag */
1193 pos_args[1][5] = base->zero; /* X */
1194 pos_args[1][6] = base->zero; /* Y */
1195 pos_args[1][7] = base->zero; /* Z */
1196 pos_args[1][8] = base->zero; /* W */
1197
1198 if (shader->selector->info.writes_psize)
1199 pos_args[1][5] = psize_value;
1200
1201 if (shader->selector->info.writes_edgeflag) {
1202 /* The output is a float, but the hw expects an integer
1203 * with the first bit containing the edge flag. */
1204 edgeflag_value = LLVMBuildFPToUI(base->gallivm->builder,
1205 edgeflag_value,
1206 bld_base->uint_bld.elem_type, "");
1207 edgeflag_value = lp_build_min(&bld_base->int_bld,
1208 edgeflag_value,
1209 bld_base->int_bld.one);
1210
1211 /* The LLVM intrinsic expects a float. */
1212 pos_args[1][6] = LLVMBuildBitCast(base->gallivm->builder,
1213 edgeflag_value,
1214 base->elem_type, "");
1215 }
1216
1217 if (shader->selector->info.writes_layer)
1218 pos_args[1][7] = layer_value;
1219 }
1220
1221 for (i = 0; i < 4; i++)
1222 if (pos_args[i][0])
1223 shader->nr_pos_exports++;
1224
1225 pos_idx = 0;
1226 for (i = 0; i < 4; i++) {
1227 if (!pos_args[i][0])
1228 continue;
1229
1230 /* Specify the target we are exporting */
1231 pos_args[i][3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_POS + pos_idx++);
1232
1233 if (pos_idx == shader->nr_pos_exports)
1234 /* Specify that this is the last export */
1235 pos_args[i][2] = uint->one;
1236
1237 lp_build_intrinsic(base->gallivm->builder,
1238 "llvm.SI.export",
1239 LLVMVoidTypeInContext(base->gallivm->context),
1240 pos_args[i], 9);
1241 }
1242 }
1243
1244 static void si_llvm_emit_es_epilogue(struct lp_build_tgsi_context * bld_base)
1245 {
1246 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
1247 struct gallivm_state *gallivm = bld_base->base.gallivm;
1248 struct si_shader *es = si_shader_ctx->shader;
1249 struct tgsi_shader_info *info = &es->selector->info;
1250 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
1251 LLVMValueRef soffset = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
1252 SI_PARAM_ES2GS_OFFSET);
1253 unsigned chan;
1254 int i;
1255
1256 for (i = 0; i < info->num_outputs; i++) {
1257 LLVMValueRef *out_ptr =
1258 si_shader_ctx->radeon_bld.soa.outputs[i];
1259 int param_index = get_param_index(info->output_semantic_name[i],
1260 info->output_semantic_index[i],
1261 es->key.vs.gs_used_inputs);
1262
1263 if (param_index < 0)
1264 continue;
1265
1266 for (chan = 0; chan < 4; chan++) {
1267 LLVMValueRef out_val = LLVMBuildLoad(gallivm->builder, out_ptr[chan], "");
1268 out_val = LLVMBuildBitCast(gallivm->builder, out_val, i32, "");
1269
1270 build_tbuffer_store(si_shader_ctx,
1271 si_shader_ctx->esgs_ring,
1272 out_val, 1,
1273 LLVMGetUndef(i32), soffset,
1274 (4 * param_index + chan) * 4,
1275 V_008F0C_BUF_DATA_FORMAT_32,
1276 V_008F0C_BUF_NUM_FORMAT_UINT,
1277 0, 0, 1, 1, 0);
1278 }
1279 }
1280 }
1281
1282 static void si_llvm_emit_gs_epilogue(struct lp_build_tgsi_context *bld_base)
1283 {
1284 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
1285 struct gallivm_state *gallivm = bld_base->base.gallivm;
1286 LLVMValueRef args[2];
1287
1288 args[0] = lp_build_const_int32(gallivm, SENDMSG_GS_OP_NOP | SENDMSG_GS_DONE);
1289 args[1] = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_GS_WAVE_ID);
1290 build_intrinsic(gallivm->builder, "llvm.SI.sendmsg",
1291 LLVMVoidTypeInContext(gallivm->context), args, 2,
1292 LLVMNoUnwindAttribute);
1293 }
1294
1295 static void si_llvm_emit_vs_epilogue(struct lp_build_tgsi_context * bld_base)
1296 {
1297 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
1298 struct gallivm_state *gallivm = bld_base->base.gallivm;
1299 struct tgsi_shader_info *info = &si_shader_ctx->shader->selector->info;
1300 struct si_shader_output_values *outputs = NULL;
1301 int i,j;
1302
1303 outputs = MALLOC(info->num_outputs * sizeof(outputs[0]));
1304
1305 for (i = 0; i < info->num_outputs; i++) {
1306 outputs[i].name = info->output_semantic_name[i];
1307 outputs[i].sid = info->output_semantic_index[i];
1308
1309 for (j = 0; j < 4; j++)
1310 outputs[i].values[j] =
1311 LLVMBuildLoad(gallivm->builder,
1312 si_shader_ctx->radeon_bld.soa.outputs[i][j],
1313 "");
1314 }
1315
1316 si_llvm_export_vs(bld_base, outputs, info->num_outputs);
1317 FREE(outputs);
1318 }
1319
1320 static void si_llvm_emit_fs_epilogue(struct lp_build_tgsi_context * bld_base)
1321 {
1322 struct si_shader_context * si_shader_ctx = si_shader_context(bld_base);
1323 struct si_shader * shader = si_shader_ctx->shader;
1324 struct lp_build_context * base = &bld_base->base;
1325 struct lp_build_context * uint = &bld_base->uint_bld;
1326 struct tgsi_shader_info *info = &shader->selector->info;
1327 LLVMValueRef args[9];
1328 LLVMValueRef last_args[9] = { 0 };
1329 int depth_index = -1, stencil_index = -1, samplemask_index = -1;
1330 int i;
1331
1332 for (i = 0; i < info->num_outputs; i++) {
1333 unsigned semantic_name = info->output_semantic_name[i];
1334 unsigned semantic_index = info->output_semantic_index[i];
1335 unsigned target;
1336
1337 /* Select the correct target */
1338 switch (semantic_name) {
1339 case TGSI_SEMANTIC_POSITION:
1340 depth_index = i;
1341 continue;
1342 case TGSI_SEMANTIC_STENCIL:
1343 stencil_index = i;
1344 continue;
1345 case TGSI_SEMANTIC_SAMPLEMASK:
1346 samplemask_index = i;
1347 continue;
1348 case TGSI_SEMANTIC_COLOR:
1349 target = V_008DFC_SQ_EXP_MRT + semantic_index;
1350 if (si_shader_ctx->shader->key.ps.alpha_to_one)
1351 LLVMBuildStore(bld_base->base.gallivm->builder,
1352 bld_base->base.one,
1353 si_shader_ctx->radeon_bld.soa.outputs[i][3]);
1354
1355 if (semantic_index == 0 &&
1356 si_shader_ctx->shader->key.ps.alpha_func != PIPE_FUNC_ALWAYS)
1357 si_alpha_test(bld_base,
1358 si_shader_ctx->radeon_bld.soa.outputs[i]);
1359 break;
1360 default:
1361 target = 0;
1362 fprintf(stderr,
1363 "Warning: SI unhandled fs output type:%d\n",
1364 semantic_name);
1365 }
1366
1367 si_llvm_init_export_args_load(bld_base,
1368 si_shader_ctx->radeon_bld.soa.outputs[i],
1369 target, args);
1370
1371 if (semantic_name == TGSI_SEMANTIC_COLOR) {
1372 /* If there is an export instruction waiting to be emitted, do so now. */
1373 if (last_args[0]) {
1374 lp_build_intrinsic(base->gallivm->builder,
1375 "llvm.SI.export",
1376 LLVMVoidTypeInContext(base->gallivm->context),
1377 last_args, 9);
1378 }
1379
1380 /* This instruction will be emitted at the end of the shader. */
1381 memcpy(last_args, args, sizeof(args));
1382
1383 /* Handle FS_COLOR0_WRITES_ALL_CBUFS. */
1384 if (shader->selector->info.properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS] &&
1385 semantic_index == 0 &&
1386 si_shader_ctx->shader->key.ps.last_cbuf > 0) {
1387 for (int c = 1; c <= si_shader_ctx->shader->key.ps.last_cbuf; c++) {
1388 si_llvm_init_export_args_load(bld_base,
1389 si_shader_ctx->radeon_bld.soa.outputs[i],
1390 V_008DFC_SQ_EXP_MRT + c, args);
1391 lp_build_intrinsic(base->gallivm->builder,
1392 "llvm.SI.export",
1393 LLVMVoidTypeInContext(base->gallivm->context),
1394 args, 9);
1395 }
1396 }
1397 } else {
1398 lp_build_intrinsic(base->gallivm->builder,
1399 "llvm.SI.export",
1400 LLVMVoidTypeInContext(base->gallivm->context),
1401 args, 9);
1402 }
1403 }
1404
1405 if (depth_index >= 0 || stencil_index >= 0 || samplemask_index >= 0) {
1406 LLVMValueRef out_ptr;
1407 unsigned mask = 0;
1408
1409 /* Specify the target we are exporting */
1410 args[3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_MRTZ);
1411
1412 args[5] = base->zero; /* R, depth */
1413 args[6] = base->zero; /* G, stencil test value[0:7], stencil op value[8:15] */
1414 args[7] = base->zero; /* B, sample mask */
1415 args[8] = base->zero; /* A, alpha to mask */
1416
1417 if (depth_index >= 0) {
1418 out_ptr = si_shader_ctx->radeon_bld.soa.outputs[depth_index][2];
1419 args[5] = LLVMBuildLoad(base->gallivm->builder, out_ptr, "");
1420 mask |= 0x1;
1421 si_shader_ctx->shader->db_shader_control |= S_02880C_Z_EXPORT_ENABLE(1);
1422 }
1423
1424 if (stencil_index >= 0) {
1425 out_ptr = si_shader_ctx->radeon_bld.soa.outputs[stencil_index][1];
1426 args[6] = LLVMBuildLoad(base->gallivm->builder, out_ptr, "");
1427 mask |= 0x2;
1428 si_shader_ctx->shader->db_shader_control |=
1429 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(1);
1430 }
1431
1432 if (samplemask_index >= 0) {
1433 out_ptr = si_shader_ctx->radeon_bld.soa.outputs[samplemask_index][0];
1434 args[7] = LLVMBuildLoad(base->gallivm->builder, out_ptr, "");
1435 mask |= 0x4;
1436 si_shader_ctx->shader->db_shader_control |= S_02880C_MASK_EXPORT_ENABLE(1);
1437 }
1438
1439 /* SI (except OLAND) has a bug that it only looks
1440 * at the X writemask component. */
1441 if (si_shader_ctx->screen->b.chip_class == SI &&
1442 si_shader_ctx->screen->b.family != CHIP_OLAND)
1443 mask |= 0x1;
1444
1445 if (samplemask_index >= 0)
1446 si_shader_ctx->shader->spi_shader_z_format = V_028710_SPI_SHADER_32_ABGR;
1447 else if (stencil_index >= 0)
1448 si_shader_ctx->shader->spi_shader_z_format = V_028710_SPI_SHADER_32_GR;
1449 else
1450 si_shader_ctx->shader->spi_shader_z_format = V_028710_SPI_SHADER_32_R;
1451
1452 /* Specify which components to enable */
1453 args[0] = lp_build_const_int32(base->gallivm, mask);
1454
1455 args[1] =
1456 args[2] =
1457 args[4] = uint->zero;
1458
1459 if (last_args[0])
1460 lp_build_intrinsic(base->gallivm->builder,
1461 "llvm.SI.export",
1462 LLVMVoidTypeInContext(base->gallivm->context),
1463 args, 9);
1464 else
1465 memcpy(last_args, args, sizeof(args));
1466 }
1467
1468 if (!last_args[0]) {
1469 /* Specify which components to enable */
1470 last_args[0] = lp_build_const_int32(base->gallivm, 0x0);
1471
1472 /* Specify the target we are exporting */
1473 last_args[3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_MRT);
1474
1475 /* Set COMPR flag to zero to export data as 32-bit */
1476 last_args[4] = uint->zero;
1477
1478 /* dummy bits */
1479 last_args[5]= uint->zero;
1480 last_args[6]= uint->zero;
1481 last_args[7]= uint->zero;
1482 last_args[8]= uint->zero;
1483 }
1484
1485 /* Specify whether the EXEC mask represents the valid mask */
1486 last_args[1] = uint->one;
1487
1488 /* Specify that this is the last export */
1489 last_args[2] = lp_build_const_int32(base->gallivm, 1);
1490
1491 lp_build_intrinsic(base->gallivm->builder,
1492 "llvm.SI.export",
1493 LLVMVoidTypeInContext(base->gallivm->context),
1494 last_args, 9);
1495 }
1496
1497 static void build_tex_intrinsic(const struct lp_build_tgsi_action * action,
1498 struct lp_build_tgsi_context * bld_base,
1499 struct lp_build_emit_data * emit_data);
1500
1501 static bool tgsi_is_shadow_sampler(unsigned target)
1502 {
1503 return target == TGSI_TEXTURE_SHADOW1D ||
1504 target == TGSI_TEXTURE_SHADOW1D_ARRAY ||
1505 target == TGSI_TEXTURE_SHADOW2D ||
1506 target == TGSI_TEXTURE_SHADOW2D_ARRAY ||
1507 target == TGSI_TEXTURE_SHADOWCUBE ||
1508 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY ||
1509 target == TGSI_TEXTURE_SHADOWRECT;
1510 }
1511
1512 static const struct lp_build_tgsi_action tex_action;
1513
1514 static void tex_fetch_args(
1515 struct lp_build_tgsi_context * bld_base,
1516 struct lp_build_emit_data * emit_data)
1517 {
1518 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
1519 struct gallivm_state *gallivm = bld_base->base.gallivm;
1520 const struct tgsi_full_instruction * inst = emit_data->inst;
1521 unsigned opcode = inst->Instruction.Opcode;
1522 unsigned target = inst->Texture.Texture;
1523 LLVMValueRef coords[4];
1524 LLVMValueRef address[16];
1525 int ref_pos;
1526 unsigned num_coords = tgsi_util_get_texture_coord_dim(target, &ref_pos);
1527 unsigned count = 0;
1528 unsigned chan;
1529 unsigned sampler_src = emit_data->inst->Instruction.NumSrcRegs - 1;
1530 unsigned sampler_index = emit_data->inst->Src[sampler_src].Register.Index;
1531 bool has_offset = HAVE_LLVM >= 0x0305 ? inst->Texture.NumOffsets > 0 : false;
1532
1533 if (target == TGSI_TEXTURE_BUFFER) {
1534 LLVMTypeRef i128 = LLVMIntTypeInContext(gallivm->context, 128);
1535 LLVMTypeRef v2i128 = LLVMVectorType(i128, 2);
1536 LLVMTypeRef i8 = LLVMInt8TypeInContext(gallivm->context);
1537 LLVMTypeRef v16i8 = LLVMVectorType(i8, 16);
1538
1539 /* Bitcast and truncate v8i32 to v16i8. */
1540 LLVMValueRef res = si_shader_ctx->resources[sampler_index];
1541 res = LLVMBuildBitCast(gallivm->builder, res, v2i128, "");
1542 res = LLVMBuildExtractElement(gallivm->builder, res, bld_base->uint_bld.one, "");
1543 res = LLVMBuildBitCast(gallivm->builder, res, v16i8, "");
1544
1545 emit_data->dst_type = LLVMVectorType(bld_base->base.elem_type, 4);
1546 emit_data->args[0] = res;
1547 emit_data->args[1] = bld_base->uint_bld.zero;
1548 emit_data->args[2] = lp_build_emit_fetch(bld_base, emit_data->inst, 0, 0);
1549 emit_data->arg_count = 3;
1550 return;
1551 }
1552
1553 /* Fetch and project texture coordinates */
1554 coords[3] = lp_build_emit_fetch(bld_base, emit_data->inst, 0, TGSI_CHAN_W);
1555 for (chan = 0; chan < 3; chan++ ) {
1556 coords[chan] = lp_build_emit_fetch(bld_base,
1557 emit_data->inst, 0,
1558 chan);
1559 if (opcode == TGSI_OPCODE_TXP)
1560 coords[chan] = lp_build_emit_llvm_binary(bld_base,
1561 TGSI_OPCODE_DIV,
1562 coords[chan],
1563 coords[3]);
1564 }
1565
1566 if (opcode == TGSI_OPCODE_TXP)
1567 coords[3] = bld_base->base.one;
1568
1569 /* Pack offsets. */
1570 if (has_offset && opcode != TGSI_OPCODE_TXF) {
1571 /* The offsets are six-bit signed integers packed like this:
1572 * X=[5:0], Y=[13:8], and Z=[21:16].
1573 */
1574 LLVMValueRef offset[3], pack;
1575
1576 assert(inst->Texture.NumOffsets == 1);
1577
1578 for (chan = 0; chan < 3; chan++) {
1579 offset[chan] = lp_build_emit_fetch_texoffset(bld_base,
1580 emit_data->inst, 0, chan);
1581 offset[chan] = LLVMBuildAnd(gallivm->builder, offset[chan],
1582 lp_build_const_int32(gallivm, 0x3f), "");
1583 if (chan)
1584 offset[chan] = LLVMBuildShl(gallivm->builder, offset[chan],
1585 lp_build_const_int32(gallivm, chan*8), "");
1586 }
1587
1588 pack = LLVMBuildOr(gallivm->builder, offset[0], offset[1], "");
1589 pack = LLVMBuildOr(gallivm->builder, pack, offset[2], "");
1590 address[count++] = pack;
1591 }
1592
1593 /* Pack LOD bias value */
1594 if (opcode == TGSI_OPCODE_TXB)
1595 address[count++] = coords[3];
1596 if (opcode == TGSI_OPCODE_TXB2)
1597 address[count++] = lp_build_emit_fetch(bld_base, inst, 1, 0);
1598
1599 /* Pack depth comparison value */
1600 if (tgsi_is_shadow_sampler(target) && opcode != TGSI_OPCODE_LODQ) {
1601 if (target == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
1602 address[count++] = lp_build_emit_fetch(bld_base, inst, 1, 0);
1603 } else {
1604 assert(ref_pos >= 0);
1605 address[count++] = coords[ref_pos];
1606 }
1607 }
1608
1609 if (target == TGSI_TEXTURE_CUBE ||
1610 target == TGSI_TEXTURE_CUBE_ARRAY ||
1611 target == TGSI_TEXTURE_SHADOWCUBE ||
1612 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY)
1613 radeon_llvm_emit_prepare_cube_coords(bld_base, emit_data, coords);
1614
1615 /* Pack user derivatives */
1616 if (opcode == TGSI_OPCODE_TXD) {
1617 int num_deriv_channels, param;
1618
1619 switch (target) {
1620 case TGSI_TEXTURE_3D:
1621 num_deriv_channels = 3;
1622 break;
1623 case TGSI_TEXTURE_2D:
1624 case TGSI_TEXTURE_SHADOW2D:
1625 case TGSI_TEXTURE_RECT:
1626 case TGSI_TEXTURE_SHADOWRECT:
1627 case TGSI_TEXTURE_2D_ARRAY:
1628 case TGSI_TEXTURE_SHADOW2D_ARRAY:
1629 case TGSI_TEXTURE_CUBE:
1630 case TGSI_TEXTURE_SHADOWCUBE:
1631 case TGSI_TEXTURE_CUBE_ARRAY:
1632 case TGSI_TEXTURE_SHADOWCUBE_ARRAY:
1633 num_deriv_channels = 2;
1634 break;
1635 case TGSI_TEXTURE_1D:
1636 case TGSI_TEXTURE_SHADOW1D:
1637 case TGSI_TEXTURE_1D_ARRAY:
1638 case TGSI_TEXTURE_SHADOW1D_ARRAY:
1639 num_deriv_channels = 1;
1640 break;
1641 default:
1642 assert(0); /* no other targets are valid here */
1643 }
1644
1645 for (param = 1; param <= 2; param++)
1646 for (chan = 0; chan < num_deriv_channels; chan++)
1647 address[count++] = lp_build_emit_fetch(bld_base, inst, param, chan);
1648 }
1649
1650 /* Pack texture coordinates */
1651 address[count++] = coords[0];
1652 if (num_coords > 1)
1653 address[count++] = coords[1];
1654 if (num_coords > 2)
1655 address[count++] = coords[2];
1656
1657 /* Pack LOD or sample index */
1658 if (opcode == TGSI_OPCODE_TXL || opcode == TGSI_OPCODE_TXF)
1659 address[count++] = coords[3];
1660 else if (opcode == TGSI_OPCODE_TXL2)
1661 address[count++] = lp_build_emit_fetch(bld_base, inst, 1, 0);
1662
1663 if (count > 16) {
1664 assert(!"Cannot handle more than 16 texture address parameters");
1665 count = 16;
1666 }
1667
1668 for (chan = 0; chan < count; chan++ ) {
1669 address[chan] = LLVMBuildBitCast(gallivm->builder,
1670 address[chan],
1671 LLVMInt32TypeInContext(gallivm->context),
1672 "");
1673 }
1674
1675 /* Adjust the sample index according to FMASK.
1676 *
1677 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
1678 * which is the identity mapping. Each nibble says which physical sample
1679 * should be fetched to get that sample.
1680 *
1681 * For example, 0x11111100 means there are only 2 samples stored and
1682 * the second sample covers 3/4 of the pixel. When reading samples 0
1683 * and 1, return physical sample 0 (determined by the first two 0s
1684 * in FMASK), otherwise return physical sample 1.
1685 *
1686 * The sample index should be adjusted as follows:
1687 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
1688 */
1689 if (target == TGSI_TEXTURE_2D_MSAA ||
1690 target == TGSI_TEXTURE_2D_ARRAY_MSAA) {
1691 struct lp_build_context *uint_bld = &bld_base->uint_bld;
1692 struct lp_build_emit_data txf_emit_data = *emit_data;
1693 LLVMValueRef txf_address[4];
1694 unsigned txf_count = count;
1695 struct tgsi_full_instruction inst = {};
1696
1697 memcpy(txf_address, address, sizeof(txf_address));
1698
1699 if (target == TGSI_TEXTURE_2D_MSAA) {
1700 txf_address[2] = bld_base->uint_bld.zero;
1701 }
1702 txf_address[3] = bld_base->uint_bld.zero;
1703
1704 /* Pad to a power-of-two size. */
1705 while (txf_count < util_next_power_of_two(txf_count))
1706 txf_address[txf_count++] = LLVMGetUndef(LLVMInt32TypeInContext(gallivm->context));
1707
1708 /* Read FMASK using TXF. */
1709 inst.Instruction.Opcode = TGSI_OPCODE_TXF;
1710 inst.Texture.Texture = target == TGSI_TEXTURE_2D_MSAA ? TGSI_TEXTURE_2D : TGSI_TEXTURE_2D_ARRAY;
1711 txf_emit_data.inst = &inst;
1712 txf_emit_data.chan = 0;
1713 txf_emit_data.dst_type = LLVMVectorType(
1714 LLVMInt32TypeInContext(gallivm->context), 4);
1715 txf_emit_data.args[0] = lp_build_gather_values(gallivm, txf_address, txf_count);
1716 txf_emit_data.args[1] = si_shader_ctx->resources[SI_FMASK_TEX_OFFSET + sampler_index];
1717 txf_emit_data.args[2] = lp_build_const_int32(gallivm, inst.Texture.Texture);
1718 txf_emit_data.arg_count = 3;
1719
1720 build_tex_intrinsic(&tex_action, bld_base, &txf_emit_data);
1721
1722 /* Initialize some constants. */
1723 LLVMValueRef four = LLVMConstInt(uint_bld->elem_type, 4, 0);
1724 LLVMValueRef F = LLVMConstInt(uint_bld->elem_type, 0xF, 0);
1725
1726 /* Apply the formula. */
1727 LLVMValueRef fmask =
1728 LLVMBuildExtractElement(gallivm->builder,
1729 txf_emit_data.output[0],
1730 uint_bld->zero, "");
1731
1732 unsigned sample_chan = target == TGSI_TEXTURE_2D_MSAA ? 2 : 3;
1733
1734 LLVMValueRef sample_index4 =
1735 LLVMBuildMul(gallivm->builder, address[sample_chan], four, "");
1736
1737 LLVMValueRef shifted_fmask =
1738 LLVMBuildLShr(gallivm->builder, fmask, sample_index4, "");
1739
1740 LLVMValueRef final_sample =
1741 LLVMBuildAnd(gallivm->builder, shifted_fmask, F, "");
1742
1743 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
1744 * resource descriptor is 0 (invalid),
1745 */
1746 LLVMValueRef fmask_desc =
1747 LLVMBuildBitCast(gallivm->builder,
1748 si_shader_ctx->resources[SI_FMASK_TEX_OFFSET + sampler_index],
1749 LLVMVectorType(uint_bld->elem_type, 8), "");
1750
1751 LLVMValueRef fmask_word1 =
1752 LLVMBuildExtractElement(gallivm->builder, fmask_desc,
1753 uint_bld->one, "");
1754
1755 LLVMValueRef word1_is_nonzero =
1756 LLVMBuildICmp(gallivm->builder, LLVMIntNE,
1757 fmask_word1, uint_bld->zero, "");
1758
1759 /* Replace the MSAA sample index. */
1760 address[sample_chan] =
1761 LLVMBuildSelect(gallivm->builder, word1_is_nonzero,
1762 final_sample, address[sample_chan], "");
1763 }
1764
1765 /* Resource */
1766 emit_data->args[1] = si_shader_ctx->resources[sampler_index];
1767
1768 if (opcode == TGSI_OPCODE_TXF) {
1769 /* add tex offsets */
1770 if (inst->Texture.NumOffsets) {
1771 struct lp_build_context *uint_bld = &bld_base->uint_bld;
1772 struct lp_build_tgsi_soa_context *bld = lp_soa_context(bld_base);
1773 const struct tgsi_texture_offset * off = inst->TexOffsets;
1774
1775 assert(inst->Texture.NumOffsets == 1);
1776
1777 switch (target) {
1778 case TGSI_TEXTURE_3D:
1779 address[2] = lp_build_add(uint_bld, address[2],
1780 bld->immediates[off->Index][off->SwizzleZ]);
1781 /* fall through */
1782 case TGSI_TEXTURE_2D:
1783 case TGSI_TEXTURE_SHADOW2D:
1784 case TGSI_TEXTURE_RECT:
1785 case TGSI_TEXTURE_SHADOWRECT:
1786 case TGSI_TEXTURE_2D_ARRAY:
1787 case TGSI_TEXTURE_SHADOW2D_ARRAY:
1788 address[1] =
1789 lp_build_add(uint_bld, address[1],
1790 bld->immediates[off->Index][off->SwizzleY]);
1791 /* fall through */
1792 case TGSI_TEXTURE_1D:
1793 case TGSI_TEXTURE_SHADOW1D:
1794 case TGSI_TEXTURE_1D_ARRAY:
1795 case TGSI_TEXTURE_SHADOW1D_ARRAY:
1796 address[0] =
1797 lp_build_add(uint_bld, address[0],
1798 bld->immediates[off->Index][off->SwizzleX]);
1799 break;
1800 /* texture offsets do not apply to other texture targets */
1801 }
1802 }
1803
1804 emit_data->args[2] = lp_build_const_int32(gallivm, target);
1805 emit_data->arg_count = 3;
1806
1807 emit_data->dst_type = LLVMVectorType(
1808 LLVMInt32TypeInContext(gallivm->context),
1809 4);
1810 } else if (opcode == TGSI_OPCODE_TG4 ||
1811 opcode == TGSI_OPCODE_LODQ ||
1812 has_offset) {
1813 unsigned is_array = target == TGSI_TEXTURE_1D_ARRAY ||
1814 target == TGSI_TEXTURE_SHADOW1D_ARRAY ||
1815 target == TGSI_TEXTURE_2D_ARRAY ||
1816 target == TGSI_TEXTURE_SHADOW2D_ARRAY ||
1817 target == TGSI_TEXTURE_CUBE_ARRAY ||
1818 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY;
1819 unsigned is_rect = target == TGSI_TEXTURE_RECT;
1820 unsigned dmask = 0xf;
1821
1822 if (opcode == TGSI_OPCODE_TG4) {
1823 unsigned gather_comp = 0;
1824
1825 /* DMASK was repurposed for GATHER4. 4 components are always
1826 * returned and DMASK works like a swizzle - it selects
1827 * the component to fetch. The only valid DMASK values are
1828 * 1=red, 2=green, 4=blue, 8=alpha. (e.g. 1 returns
1829 * (red,red,red,red) etc.) The ISA document doesn't mention
1830 * this.
1831 */
1832
1833 /* Get the component index from src1.x for Gather4. */
1834 if (!tgsi_is_shadow_sampler(target)) {
1835 LLVMValueRef (*imms)[4] = lp_soa_context(bld_base)->immediates;
1836 LLVMValueRef comp_imm;
1837 struct tgsi_src_register src1 = inst->Src[1].Register;
1838
1839 assert(src1.File == TGSI_FILE_IMMEDIATE);
1840
1841 comp_imm = imms[src1.Index][src1.SwizzleX];
1842 gather_comp = LLVMConstIntGetZExtValue(comp_imm);
1843 gather_comp = CLAMP(gather_comp, 0, 3);
1844 }
1845
1846 dmask = 1 << gather_comp;
1847 }
1848
1849 emit_data->args[2] = si_shader_ctx->samplers[sampler_index];
1850 emit_data->args[3] = lp_build_const_int32(gallivm, dmask);
1851 emit_data->args[4] = lp_build_const_int32(gallivm, is_rect); /* unorm */
1852 emit_data->args[5] = lp_build_const_int32(gallivm, 0); /* r128 */
1853 emit_data->args[6] = lp_build_const_int32(gallivm, is_array); /* da */
1854 emit_data->args[7] = lp_build_const_int32(gallivm, 0); /* glc */
1855 emit_data->args[8] = lp_build_const_int32(gallivm, 0); /* slc */
1856 emit_data->args[9] = lp_build_const_int32(gallivm, 0); /* tfe */
1857 emit_data->args[10] = lp_build_const_int32(gallivm, 0); /* lwe */
1858
1859 emit_data->arg_count = 11;
1860
1861 emit_data->dst_type = LLVMVectorType(
1862 LLVMFloatTypeInContext(gallivm->context),
1863 4);
1864 } else {
1865 emit_data->args[2] = si_shader_ctx->samplers[sampler_index];
1866 emit_data->args[3] = lp_build_const_int32(gallivm, target);
1867 emit_data->arg_count = 4;
1868
1869 emit_data->dst_type = LLVMVectorType(
1870 LLVMFloatTypeInContext(gallivm->context),
1871 4);
1872 }
1873
1874 /* The fetch opcode has been converted to a 2D array fetch.
1875 * This simplifies the LLVM backend. */
1876 if (target == TGSI_TEXTURE_CUBE_ARRAY)
1877 target = TGSI_TEXTURE_2D_ARRAY;
1878 else if (target == TGSI_TEXTURE_SHADOWCUBE_ARRAY)
1879 target = TGSI_TEXTURE_SHADOW2D_ARRAY;
1880
1881 /* Pad to power of two vector */
1882 while (count < util_next_power_of_two(count))
1883 address[count++] = LLVMGetUndef(LLVMInt32TypeInContext(gallivm->context));
1884
1885 emit_data->args[0] = lp_build_gather_values(gallivm, address, count);
1886 }
1887
1888 static void build_tex_intrinsic(const struct lp_build_tgsi_action * action,
1889 struct lp_build_tgsi_context * bld_base,
1890 struct lp_build_emit_data * emit_data)
1891 {
1892 struct lp_build_context * base = &bld_base->base;
1893 unsigned opcode = emit_data->inst->Instruction.Opcode;
1894 unsigned target = emit_data->inst->Texture.Texture;
1895 char intr_name[127];
1896 bool has_offset = HAVE_LLVM >= 0x0305 ?
1897 emit_data->inst->Texture.NumOffsets > 0 : false;
1898
1899 if (target == TGSI_TEXTURE_BUFFER) {
1900 emit_data->output[emit_data->chan] = build_intrinsic(
1901 base->gallivm->builder,
1902 "llvm.SI.vs.load.input", emit_data->dst_type,
1903 emit_data->args, emit_data->arg_count,
1904 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
1905 return;
1906 }
1907
1908 if (opcode == TGSI_OPCODE_TG4 ||
1909 opcode == TGSI_OPCODE_LODQ ||
1910 (opcode != TGSI_OPCODE_TXF && has_offset)) {
1911 bool is_shadow = tgsi_is_shadow_sampler(target);
1912 const char *name = "llvm.SI.image.sample";
1913 const char *infix = "";
1914
1915 switch (opcode) {
1916 case TGSI_OPCODE_TEX:
1917 case TGSI_OPCODE_TEX2:
1918 case TGSI_OPCODE_TXP:
1919 break;
1920 case TGSI_OPCODE_TXB:
1921 case TGSI_OPCODE_TXB2:
1922 infix = ".b";
1923 break;
1924 case TGSI_OPCODE_TXL:
1925 case TGSI_OPCODE_TXL2:
1926 infix = ".l";
1927 break;
1928 case TGSI_OPCODE_TXD:
1929 infix = ".d";
1930 break;
1931 case TGSI_OPCODE_TG4:
1932 name = "llvm.SI.gather4";
1933 break;
1934 case TGSI_OPCODE_LODQ:
1935 name = "llvm.SI.getlod";
1936 is_shadow = false;
1937 has_offset = false;
1938 break;
1939 default:
1940 assert(0);
1941 return;
1942 }
1943
1944 /* Add the type and suffixes .c, .o if needed. */
1945 sprintf(intr_name, "%s%s%s%s.v%ui32", name,
1946 is_shadow ? ".c" : "", infix, has_offset ? ".o" : "",
1947 LLVMGetVectorSize(LLVMTypeOf(emit_data->args[0])));
1948
1949 emit_data->output[emit_data->chan] = build_intrinsic(
1950 base->gallivm->builder, intr_name, emit_data->dst_type,
1951 emit_data->args, emit_data->arg_count,
1952 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
1953 } else {
1954 LLVMTypeRef i8, v16i8, v32i8;
1955 const char *name;
1956
1957 switch (opcode) {
1958 case TGSI_OPCODE_TEX:
1959 case TGSI_OPCODE_TEX2:
1960 case TGSI_OPCODE_TXP:
1961 name = "llvm.SI.sample";
1962 break;
1963 case TGSI_OPCODE_TXB:
1964 case TGSI_OPCODE_TXB2:
1965 name = "llvm.SI.sampleb";
1966 break;
1967 case TGSI_OPCODE_TXD:
1968 name = "llvm.SI.sampled";
1969 break;
1970 case TGSI_OPCODE_TXF:
1971 name = "llvm.SI.imageload";
1972 break;
1973 case TGSI_OPCODE_TXL:
1974 case TGSI_OPCODE_TXL2:
1975 name = "llvm.SI.samplel";
1976 break;
1977 default:
1978 assert(0);
1979 return;
1980 }
1981
1982 i8 = LLVMInt8TypeInContext(base->gallivm->context);
1983 v16i8 = LLVMVectorType(i8, 16);
1984 v32i8 = LLVMVectorType(i8, 32);
1985
1986 emit_data->args[1] = LLVMBuildBitCast(base->gallivm->builder,
1987 emit_data->args[1], v32i8, "");
1988 if (opcode != TGSI_OPCODE_TXF) {
1989 emit_data->args[2] = LLVMBuildBitCast(base->gallivm->builder,
1990 emit_data->args[2], v16i8, "");
1991 }
1992
1993 sprintf(intr_name, "%s.v%ui32", name,
1994 LLVMGetVectorSize(LLVMTypeOf(emit_data->args[0])));
1995
1996 emit_data->output[emit_data->chan] = build_intrinsic(
1997 base->gallivm->builder, intr_name, emit_data->dst_type,
1998 emit_data->args, emit_data->arg_count,
1999 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
2000 }
2001 }
2002
2003 static void txq_fetch_args(
2004 struct lp_build_tgsi_context * bld_base,
2005 struct lp_build_emit_data * emit_data)
2006 {
2007 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
2008 const struct tgsi_full_instruction *inst = emit_data->inst;
2009 struct gallivm_state *gallivm = bld_base->base.gallivm;
2010 unsigned target = inst->Texture.Texture;
2011
2012 if (target == TGSI_TEXTURE_BUFFER) {
2013 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
2014 LLVMTypeRef v8i32 = LLVMVectorType(i32, 8);
2015
2016 /* Read the size from the buffer descriptor directly. */
2017 LLVMValueRef size = si_shader_ctx->resources[inst->Src[1].Register.Index];
2018 size = LLVMBuildBitCast(gallivm->builder, size, v8i32, "");
2019 size = LLVMBuildExtractElement(gallivm->builder, size,
2020 lp_build_const_int32(gallivm, 6), "");
2021 emit_data->args[0] = size;
2022 return;
2023 }
2024
2025 /* Mip level */
2026 emit_data->args[0] = lp_build_emit_fetch(bld_base, inst, 0, TGSI_CHAN_X);
2027
2028 /* Resource */
2029 emit_data->args[1] = si_shader_ctx->resources[inst->Src[1].Register.Index];
2030
2031 /* Texture target */
2032 if (target == TGSI_TEXTURE_CUBE_ARRAY ||
2033 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY)
2034 target = TGSI_TEXTURE_2D_ARRAY;
2035
2036 emit_data->args[2] = lp_build_const_int32(bld_base->base.gallivm,
2037 target);
2038
2039 emit_data->arg_count = 3;
2040
2041 emit_data->dst_type = LLVMVectorType(
2042 LLVMInt32TypeInContext(bld_base->base.gallivm->context),
2043 4);
2044 }
2045
2046 static void build_txq_intrinsic(const struct lp_build_tgsi_action * action,
2047 struct lp_build_tgsi_context * bld_base,
2048 struct lp_build_emit_data * emit_data)
2049 {
2050 unsigned target = emit_data->inst->Texture.Texture;
2051
2052 if (target == TGSI_TEXTURE_BUFFER) {
2053 /* Just return the buffer size. */
2054 emit_data->output[emit_data->chan] = emit_data->args[0];
2055 return;
2056 }
2057
2058 build_tgsi_intrinsic_nomem(action, bld_base, emit_data);
2059
2060 /* Divide the number of layers by 6 to get the number of cubes. */
2061 if (target == TGSI_TEXTURE_CUBE_ARRAY ||
2062 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
2063 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
2064 LLVMValueRef two = lp_build_const_int32(bld_base->base.gallivm, 2);
2065 LLVMValueRef six = lp_build_const_int32(bld_base->base.gallivm, 6);
2066
2067 LLVMValueRef v4 = emit_data->output[emit_data->chan];
2068 LLVMValueRef z = LLVMBuildExtractElement(builder, v4, two, "");
2069 z = LLVMBuildSDiv(builder, z, six, "");
2070
2071 emit_data->output[emit_data->chan] =
2072 LLVMBuildInsertElement(builder, v4, z, two, "");
2073 }
2074 }
2075
2076 static void si_llvm_emit_ddxy(
2077 const struct lp_build_tgsi_action * action,
2078 struct lp_build_tgsi_context * bld_base,
2079 struct lp_build_emit_data * emit_data)
2080 {
2081 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
2082 struct gallivm_state *gallivm = bld_base->base.gallivm;
2083 struct lp_build_context * base = &bld_base->base;
2084 const struct tgsi_full_instruction *inst = emit_data->inst;
2085 unsigned opcode = inst->Instruction.Opcode;
2086 LLVMValueRef indices[2];
2087 LLVMValueRef store_ptr, load_ptr0, load_ptr1;
2088 LLVMValueRef tl, trbl, result[4];
2089 LLVMTypeRef i32;
2090 unsigned swizzle[4];
2091 unsigned c;
2092
2093 i32 = LLVMInt32TypeInContext(gallivm->context);
2094
2095 indices[0] = bld_base->uint_bld.zero;
2096 indices[1] = build_intrinsic(gallivm->builder, "llvm.SI.tid", i32,
2097 NULL, 0, LLVMReadNoneAttribute);
2098 store_ptr = LLVMBuildGEP(gallivm->builder, si_shader_ctx->ddxy_lds,
2099 indices, 2, "");
2100
2101 indices[1] = LLVMBuildAnd(gallivm->builder, indices[1],
2102 lp_build_const_int32(gallivm, 0xfffffffc), "");
2103 load_ptr0 = LLVMBuildGEP(gallivm->builder, si_shader_ctx->ddxy_lds,
2104 indices, 2, "");
2105
2106 indices[1] = LLVMBuildAdd(gallivm->builder, indices[1],
2107 lp_build_const_int32(gallivm,
2108 opcode == TGSI_OPCODE_DDX ? 1 : 2),
2109 "");
2110 load_ptr1 = LLVMBuildGEP(gallivm->builder, si_shader_ctx->ddxy_lds,
2111 indices, 2, "");
2112
2113 for (c = 0; c < 4; ++c) {
2114 unsigned i;
2115
2116 swizzle[c] = tgsi_util_get_full_src_register_swizzle(&inst->Src[0], c);
2117 for (i = 0; i < c; ++i) {
2118 if (swizzle[i] == swizzle[c]) {
2119 result[c] = result[i];
2120 break;
2121 }
2122 }
2123 if (i != c)
2124 continue;
2125
2126 LLVMBuildStore(gallivm->builder,
2127 LLVMBuildBitCast(gallivm->builder,
2128 lp_build_emit_fetch(bld_base, inst, 0, c),
2129 i32, ""),
2130 store_ptr);
2131
2132 tl = LLVMBuildLoad(gallivm->builder, load_ptr0, "");
2133 tl = LLVMBuildBitCast(gallivm->builder, tl, base->elem_type, "");
2134
2135 trbl = LLVMBuildLoad(gallivm->builder, load_ptr1, "");
2136 trbl = LLVMBuildBitCast(gallivm->builder, trbl, base->elem_type, "");
2137
2138 result[c] = LLVMBuildFSub(gallivm->builder, trbl, tl, "");
2139 }
2140
2141 emit_data->output[0] = lp_build_gather_values(gallivm, result, 4);
2142 }
2143
2144 /* Emit one vertex from the geometry shader */
2145 static void si_llvm_emit_vertex(
2146 const struct lp_build_tgsi_action *action,
2147 struct lp_build_tgsi_context *bld_base,
2148 struct lp_build_emit_data *emit_data)
2149 {
2150 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
2151 struct lp_build_context *uint = &bld_base->uint_bld;
2152 struct si_shader *shader = si_shader_ctx->shader;
2153 struct tgsi_shader_info *info = &shader->selector->info;
2154 struct gallivm_state *gallivm = bld_base->base.gallivm;
2155 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
2156 LLVMValueRef soffset = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
2157 SI_PARAM_GS2VS_OFFSET);
2158 LLVMValueRef gs_next_vertex;
2159 LLVMValueRef can_emit, kill;
2160 LLVMValueRef args[2];
2161 unsigned chan;
2162 int i;
2163
2164 /* Write vertex attribute values to GSVS ring */
2165 gs_next_vertex = LLVMBuildLoad(gallivm->builder, si_shader_ctx->gs_next_vertex, "");
2166
2167 /* If this thread has already emitted the declared maximum number of
2168 * vertices, kill it: excessive vertex emissions are not supposed to
2169 * have any effect, and GS threads have no externally observable
2170 * effects other than emitting vertices.
2171 */
2172 can_emit = LLVMBuildICmp(gallivm->builder, LLVMIntULE, gs_next_vertex,
2173 lp_build_const_int32(gallivm,
2174 shader->selector->gs_max_out_vertices), "");
2175 kill = lp_build_select(&bld_base->base, can_emit,
2176 lp_build_const_float(gallivm, 1.0f),
2177 lp_build_const_float(gallivm, -1.0f));
2178 build_intrinsic(gallivm->builder, "llvm.AMDGPU.kill",
2179 LLVMVoidTypeInContext(gallivm->context), &kill, 1, 0);
2180
2181 for (i = 0; i < info->num_outputs; i++) {
2182 LLVMValueRef *out_ptr =
2183 si_shader_ctx->radeon_bld.soa.outputs[i];
2184
2185 for (chan = 0; chan < 4; chan++) {
2186 LLVMValueRef out_val = LLVMBuildLoad(gallivm->builder, out_ptr[chan], "");
2187 LLVMValueRef voffset =
2188 lp_build_const_int32(gallivm, (i * 4 + chan) *
2189 shader->selector->gs_max_out_vertices);
2190
2191 voffset = lp_build_add(uint, voffset, gs_next_vertex);
2192 voffset = lp_build_mul_imm(uint, voffset, 4);
2193
2194 out_val = LLVMBuildBitCast(gallivm->builder, out_val, i32, "");
2195
2196 build_tbuffer_store(si_shader_ctx,
2197 si_shader_ctx->gsvs_ring,
2198 out_val, 1,
2199 voffset, soffset, 0,
2200 V_008F0C_BUF_DATA_FORMAT_32,
2201 V_008F0C_BUF_NUM_FORMAT_UINT,
2202 1, 0, 1, 1, 0);
2203 }
2204 }
2205 gs_next_vertex = lp_build_add(uint, gs_next_vertex,
2206 lp_build_const_int32(gallivm, 1));
2207 LLVMBuildStore(gallivm->builder, gs_next_vertex, si_shader_ctx->gs_next_vertex);
2208
2209 /* Signal vertex emission */
2210 args[0] = lp_build_const_int32(gallivm, SENDMSG_GS_OP_EMIT | SENDMSG_GS);
2211 args[1] = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_GS_WAVE_ID);
2212 build_intrinsic(gallivm->builder, "llvm.SI.sendmsg",
2213 LLVMVoidTypeInContext(gallivm->context), args, 2,
2214 LLVMNoUnwindAttribute);
2215 }
2216
2217 /* Cut one primitive from the geometry shader */
2218 static void si_llvm_emit_primitive(
2219 const struct lp_build_tgsi_action *action,
2220 struct lp_build_tgsi_context *bld_base,
2221 struct lp_build_emit_data *emit_data)
2222 {
2223 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
2224 struct gallivm_state *gallivm = bld_base->base.gallivm;
2225 LLVMValueRef args[2];
2226
2227 /* Signal primitive cut */
2228 args[0] = lp_build_const_int32(gallivm, SENDMSG_GS_OP_CUT | SENDMSG_GS);
2229 args[1] = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_GS_WAVE_ID);
2230 build_intrinsic(gallivm->builder, "llvm.SI.sendmsg",
2231 LLVMVoidTypeInContext(gallivm->context), args, 2,
2232 LLVMNoUnwindAttribute);
2233 }
2234
2235 static const struct lp_build_tgsi_action tex_action = {
2236 .fetch_args = tex_fetch_args,
2237 .emit = build_tex_intrinsic,
2238 };
2239
2240 static const struct lp_build_tgsi_action txq_action = {
2241 .fetch_args = txq_fetch_args,
2242 .emit = build_txq_intrinsic,
2243 .intr_name = "llvm.SI.resinfo"
2244 };
2245
2246 static void create_meta_data(struct si_shader_context *si_shader_ctx)
2247 {
2248 struct gallivm_state *gallivm = si_shader_ctx->radeon_bld.soa.bld_base.base.gallivm;
2249 LLVMValueRef args[3];
2250
2251 args[0] = LLVMMDStringInContext(gallivm->context, "const", 5);
2252 args[1] = 0;
2253 args[2] = lp_build_const_int32(gallivm, 1);
2254
2255 si_shader_ctx->const_md = LLVMMDNodeInContext(gallivm->context, args, 3);
2256 }
2257
2258 static LLVMTypeRef const_array(LLVMTypeRef elem_type, int num_elements)
2259 {
2260 return LLVMPointerType(LLVMArrayType(elem_type, num_elements),
2261 CONST_ADDR_SPACE);
2262 }
2263
2264 static void create_function(struct si_shader_context *si_shader_ctx)
2265 {
2266 struct lp_build_tgsi_context *bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
2267 struct gallivm_state *gallivm = bld_base->base.gallivm;
2268 struct si_shader *shader = si_shader_ctx->shader;
2269 LLVMTypeRef params[SI_NUM_PARAMS], f32, i8, i32, v2i32, v3i32, v16i8, v4i32, v8i32;
2270 unsigned i, last_array_pointer, last_sgpr, num_params;
2271
2272 i8 = LLVMInt8TypeInContext(gallivm->context);
2273 i32 = LLVMInt32TypeInContext(gallivm->context);
2274 f32 = LLVMFloatTypeInContext(gallivm->context);
2275 v2i32 = LLVMVectorType(i32, 2);
2276 v3i32 = LLVMVectorType(i32, 3);
2277 v4i32 = LLVMVectorType(i32, 4);
2278 v8i32 = LLVMVectorType(i32, 8);
2279 v16i8 = LLVMVectorType(i8, 16);
2280
2281 params[SI_PARAM_RW_BUFFERS] = const_array(v16i8, SI_NUM_RW_BUFFERS);
2282 params[SI_PARAM_CONST] = const_array(v16i8, SI_NUM_CONST_BUFFERS);
2283 params[SI_PARAM_SAMPLER] = const_array(v4i32, SI_NUM_SAMPLER_STATES);
2284 params[SI_PARAM_RESOURCE] = const_array(v8i32, SI_NUM_SAMPLER_VIEWS);
2285 last_array_pointer = SI_PARAM_RESOURCE;
2286
2287 switch (si_shader_ctx->type) {
2288 case TGSI_PROCESSOR_VERTEX:
2289 params[SI_PARAM_VERTEX_BUFFER] = const_array(v16i8, SI_NUM_VERTEX_BUFFERS);
2290 last_array_pointer = SI_PARAM_VERTEX_BUFFER;
2291 params[SI_PARAM_BASE_VERTEX] = i32;
2292 params[SI_PARAM_START_INSTANCE] = i32;
2293 num_params = SI_PARAM_START_INSTANCE+1;
2294
2295 if (shader->key.vs.as_es) {
2296 params[SI_PARAM_ES2GS_OFFSET] = i32;
2297 num_params++;
2298 } else {
2299 if (shader->is_gs_copy_shader) {
2300 last_array_pointer = SI_PARAM_CONST;
2301 num_params = SI_PARAM_CONST+1;
2302 }
2303
2304 /* The locations of the other parameters are assigned dynamically. */
2305
2306 /* Streamout SGPRs. */
2307 if (shader->selector->so.num_outputs) {
2308 params[si_shader_ctx->param_streamout_config = num_params++] = i32;
2309 params[si_shader_ctx->param_streamout_write_index = num_params++] = i32;
2310 }
2311 /* A streamout buffer offset is loaded if the stride is non-zero. */
2312 for (i = 0; i < 4; i++) {
2313 if (!shader->selector->so.stride[i])
2314 continue;
2315
2316 params[si_shader_ctx->param_streamout_offset[i] = num_params++] = i32;
2317 }
2318 }
2319
2320 last_sgpr = num_params-1;
2321
2322 /* VGPRs */
2323 params[si_shader_ctx->param_vertex_id = num_params++] = i32;
2324 params[num_params++] = i32; /* unused*/
2325 params[num_params++] = i32; /* unused */
2326 params[si_shader_ctx->param_instance_id = num_params++] = i32;
2327 break;
2328
2329 case TGSI_PROCESSOR_GEOMETRY:
2330 params[SI_PARAM_GS2VS_OFFSET] = i32;
2331 params[SI_PARAM_GS_WAVE_ID] = i32;
2332 last_sgpr = SI_PARAM_GS_WAVE_ID;
2333
2334 /* VGPRs */
2335 params[SI_PARAM_VTX0_OFFSET] = i32;
2336 params[SI_PARAM_VTX1_OFFSET] = i32;
2337 params[SI_PARAM_PRIMITIVE_ID] = i32;
2338 params[SI_PARAM_VTX2_OFFSET] = i32;
2339 params[SI_PARAM_VTX3_OFFSET] = i32;
2340 params[SI_PARAM_VTX4_OFFSET] = i32;
2341 params[SI_PARAM_VTX5_OFFSET] = i32;
2342 params[SI_PARAM_GS_INSTANCE_ID] = i32;
2343 num_params = SI_PARAM_GS_INSTANCE_ID+1;
2344 break;
2345
2346 case TGSI_PROCESSOR_FRAGMENT:
2347 params[SI_PARAM_ALPHA_REF] = f32;
2348 params[SI_PARAM_PRIM_MASK] = i32;
2349 last_sgpr = SI_PARAM_PRIM_MASK;
2350 params[SI_PARAM_PERSP_SAMPLE] = v2i32;
2351 params[SI_PARAM_PERSP_CENTER] = v2i32;
2352 params[SI_PARAM_PERSP_CENTROID] = v2i32;
2353 params[SI_PARAM_PERSP_PULL_MODEL] = v3i32;
2354 params[SI_PARAM_LINEAR_SAMPLE] = v2i32;
2355 params[SI_PARAM_LINEAR_CENTER] = v2i32;
2356 params[SI_PARAM_LINEAR_CENTROID] = v2i32;
2357 params[SI_PARAM_LINE_STIPPLE_TEX] = f32;
2358 params[SI_PARAM_POS_X_FLOAT] = f32;
2359 params[SI_PARAM_POS_Y_FLOAT] = f32;
2360 params[SI_PARAM_POS_Z_FLOAT] = f32;
2361 params[SI_PARAM_POS_W_FLOAT] = f32;
2362 params[SI_PARAM_FRONT_FACE] = f32;
2363 params[SI_PARAM_ANCILLARY] = i32;
2364 params[SI_PARAM_SAMPLE_COVERAGE] = f32;
2365 params[SI_PARAM_POS_FIXED_PT] = f32;
2366 num_params = SI_PARAM_POS_FIXED_PT+1;
2367 break;
2368
2369 default:
2370 assert(0 && "unimplemented shader");
2371 return;
2372 }
2373
2374 assert(num_params <= Elements(params));
2375 radeon_llvm_create_func(&si_shader_ctx->radeon_bld, params, num_params);
2376 radeon_llvm_shader_type(si_shader_ctx->radeon_bld.main_fn, si_shader_ctx->type);
2377
2378 if (shader->dx10_clamp_mode)
2379 LLVMAddTargetDependentFunctionAttr(si_shader_ctx->radeon_bld.main_fn,
2380 "enable-no-nans-fp-math", "true");
2381
2382 for (i = 0; i <= last_sgpr; ++i) {
2383 LLVMValueRef P = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, i);
2384
2385 /* We tell llvm that array inputs are passed by value to allow Sinking pass
2386 * to move load. Inputs are constant so this is fine. */
2387 if (i <= last_array_pointer)
2388 LLVMAddAttribute(P, LLVMByValAttribute);
2389 else
2390 LLVMAddAttribute(P, LLVMInRegAttribute);
2391 }
2392
2393 if (bld_base->info &&
2394 (bld_base->info->opcode_count[TGSI_OPCODE_DDX] > 0 ||
2395 bld_base->info->opcode_count[TGSI_OPCODE_DDY] > 0))
2396 si_shader_ctx->ddxy_lds =
2397 LLVMAddGlobalInAddressSpace(gallivm->module,
2398 LLVMArrayType(i32, 64),
2399 "ddxy_lds",
2400 LOCAL_ADDR_SPACE);
2401 }
2402
2403 static void preload_constants(struct si_shader_context *si_shader_ctx)
2404 {
2405 struct lp_build_tgsi_context * bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
2406 struct gallivm_state * gallivm = bld_base->base.gallivm;
2407 const struct tgsi_shader_info * info = bld_base->info;
2408 unsigned buf;
2409 LLVMValueRef ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_CONST);
2410
2411 for (buf = 0; buf < SI_NUM_CONST_BUFFERS; buf++) {
2412 unsigned i, num_const = info->const_file_max[buf] + 1;
2413
2414 if (num_const == 0)
2415 continue;
2416
2417 /* Allocate space for the constant values */
2418 si_shader_ctx->constants[buf] = CALLOC(num_const * 4, sizeof(LLVMValueRef));
2419
2420 /* Load the resource descriptor */
2421 si_shader_ctx->const_resource[buf] =
2422 build_indexed_load_const(si_shader_ctx, ptr, lp_build_const_int32(gallivm, buf));
2423
2424 /* Load the constants, we rely on the code sinking to do the rest */
2425 for (i = 0; i < num_const * 4; ++i) {
2426 si_shader_ctx->constants[buf][i] =
2427 buffer_load_const(gallivm->builder,
2428 si_shader_ctx->const_resource[buf],
2429 lp_build_const_int32(gallivm, i * 4),
2430 bld_base->base.elem_type);
2431 }
2432 }
2433 }
2434
2435 static void preload_samplers(struct si_shader_context *si_shader_ctx)
2436 {
2437 struct lp_build_tgsi_context * bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
2438 struct gallivm_state * gallivm = bld_base->base.gallivm;
2439 const struct tgsi_shader_info * info = bld_base->info;
2440
2441 unsigned i, num_samplers = info->file_max[TGSI_FILE_SAMPLER] + 1;
2442
2443 LLVMValueRef res_ptr, samp_ptr;
2444 LLVMValueRef offset;
2445
2446 if (num_samplers == 0)
2447 return;
2448
2449 res_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_RESOURCE);
2450 samp_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_SAMPLER);
2451
2452 /* Load the resources and samplers, we rely on the code sinking to do the rest */
2453 for (i = 0; i < num_samplers; ++i) {
2454 /* Resource */
2455 offset = lp_build_const_int32(gallivm, i);
2456 si_shader_ctx->resources[i] = build_indexed_load_const(si_shader_ctx, res_ptr, offset);
2457
2458 /* Sampler */
2459 offset = lp_build_const_int32(gallivm, i);
2460 si_shader_ctx->samplers[i] = build_indexed_load_const(si_shader_ctx, samp_ptr, offset);
2461
2462 /* FMASK resource */
2463 if (info->is_msaa_sampler[i]) {
2464 offset = lp_build_const_int32(gallivm, SI_FMASK_TEX_OFFSET + i);
2465 si_shader_ctx->resources[SI_FMASK_TEX_OFFSET + i] =
2466 build_indexed_load_const(si_shader_ctx, res_ptr, offset);
2467 }
2468 }
2469 }
2470
2471 static void preload_streamout_buffers(struct si_shader_context *si_shader_ctx)
2472 {
2473 struct lp_build_tgsi_context * bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
2474 struct gallivm_state * gallivm = bld_base->base.gallivm;
2475 unsigned i;
2476
2477 if (si_shader_ctx->type != TGSI_PROCESSOR_VERTEX ||
2478 si_shader_ctx->shader->key.vs.as_es ||
2479 !si_shader_ctx->shader->selector->so.num_outputs)
2480 return;
2481
2482 LLVMValueRef buf_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
2483 SI_PARAM_RW_BUFFERS);
2484
2485 /* Load the resources, we rely on the code sinking to do the rest */
2486 for (i = 0; i < 4; ++i) {
2487 if (si_shader_ctx->shader->selector->so.stride[i]) {
2488 LLVMValueRef offset = lp_build_const_int32(gallivm,
2489 SI_SO_BUF_OFFSET + i);
2490
2491 si_shader_ctx->so_buffers[i] = build_indexed_load_const(si_shader_ctx, buf_ptr, offset);
2492 }
2493 }
2494 }
2495
2496 /**
2497 * Load ESGS and GSVS ring buffer resource descriptors and save the variables
2498 * for later use.
2499 */
2500 static void preload_ring_buffers(struct si_shader_context *si_shader_ctx)
2501 {
2502 struct gallivm_state *gallivm =
2503 si_shader_ctx->radeon_bld.soa.bld_base.base.gallivm;
2504
2505 LLVMValueRef buf_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
2506 SI_PARAM_RW_BUFFERS);
2507
2508 if ((si_shader_ctx->type == TGSI_PROCESSOR_VERTEX &&
2509 si_shader_ctx->shader->key.vs.as_es) ||
2510 si_shader_ctx->type == TGSI_PROCESSOR_GEOMETRY) {
2511 LLVMValueRef offset = lp_build_const_int32(gallivm, SI_RING_ESGS);
2512
2513 si_shader_ctx->esgs_ring =
2514 build_indexed_load_const(si_shader_ctx, buf_ptr, offset);
2515 }
2516
2517 if (si_shader_ctx->type == TGSI_PROCESSOR_GEOMETRY ||
2518 si_shader_ctx->shader->is_gs_copy_shader) {
2519 LLVMValueRef offset = lp_build_const_int32(gallivm, SI_RING_GSVS);
2520
2521 si_shader_ctx->gsvs_ring =
2522 build_indexed_load_const(si_shader_ctx, buf_ptr, offset);
2523 }
2524 }
2525
2526 void si_shader_binary_read_config(const struct si_screen *sscreen,
2527 struct si_shader *shader,
2528 unsigned symbol_offset)
2529 {
2530 unsigned i;
2531 const unsigned char *config =
2532 radeon_shader_binary_config_start(&shader->binary,
2533 symbol_offset);
2534
2535 /* XXX: We may be able to emit some of these values directly rather than
2536 * extracting fields to be emitted later.
2537 */
2538
2539 for (i = 0; i < shader->binary.config_size_per_symbol; i+= 8) {
2540 unsigned reg = util_le32_to_cpu(*(uint32_t*)(config + i));
2541 unsigned value = util_le32_to_cpu(*(uint32_t*)(config + i + 4));
2542 switch (reg) {
2543 case R_00B028_SPI_SHADER_PGM_RSRC1_PS:
2544 case R_00B128_SPI_SHADER_PGM_RSRC1_VS:
2545 case R_00B228_SPI_SHADER_PGM_RSRC1_GS:
2546 case R_00B848_COMPUTE_PGM_RSRC1:
2547 shader->num_sgprs = MAX2(shader->num_sgprs, (G_00B028_SGPRS(value) + 1) * 8);
2548 shader->num_vgprs = MAX2(shader->num_vgprs, (G_00B028_VGPRS(value) + 1) * 4);
2549 break;
2550 case R_00B02C_SPI_SHADER_PGM_RSRC2_PS:
2551 shader->lds_size = MAX2(shader->lds_size, G_00B02C_EXTRA_LDS_SIZE(value));
2552 break;
2553 case R_00B84C_COMPUTE_PGM_RSRC2:
2554 shader->lds_size = MAX2(shader->lds_size, G_00B84C_LDS_SIZE(value));
2555 break;
2556 case R_0286CC_SPI_PS_INPUT_ENA:
2557 shader->spi_ps_input_ena = value;
2558 break;
2559 case R_0286E8_SPI_TMPRING_SIZE:
2560 case R_00B860_COMPUTE_TMPRING_SIZE:
2561 /* WAVESIZE is in units of 256 dwords. */
2562 shader->scratch_bytes_per_wave =
2563 G_00B860_WAVESIZE(value) * 256 * 4 * 1;
2564 break;
2565 default:
2566 fprintf(stderr, "Warning: Compiler emitted unknown "
2567 "config register: 0x%x\n", reg);
2568 break;
2569 }
2570 }
2571 }
2572
2573 void si_shader_apply_scratch_relocs(struct si_context *sctx,
2574 struct si_shader *shader,
2575 uint64_t scratch_va)
2576 {
2577 unsigned i;
2578 uint32_t scratch_rsrc_dword0 = scratch_va & 0xffffffff;
2579 uint32_t scratch_rsrc_dword1 =
2580 S_008F04_BASE_ADDRESS_HI(scratch_va >> 32)
2581 | S_008F04_STRIDE(shader->scratch_bytes_per_wave / 64);
2582
2583 for (i = 0 ; i < shader->binary.reloc_count; i++) {
2584 const struct radeon_shader_reloc *reloc =
2585 &shader->binary.relocs[i];
2586 if (!strcmp(scratch_rsrc_dword0_symbol, reloc->name)) {
2587 util_memcpy_cpu_to_le32(shader->binary.code + reloc->offset,
2588 &scratch_rsrc_dword0, 4);
2589 } else if (!strcmp(scratch_rsrc_dword1_symbol, reloc->name)) {
2590 util_memcpy_cpu_to_le32(shader->binary.code + reloc->offset,
2591 &scratch_rsrc_dword1, 4);
2592 }
2593 }
2594 }
2595
2596 int si_shader_binary_read(struct si_screen *sscreen,
2597 struct si_shader *shader,
2598 const struct radeon_shader_binary *binary)
2599 {
2600
2601 unsigned i;
2602 unsigned code_size;
2603 unsigned char *ptr;
2604 bool dump = r600_can_dump_shader(&sscreen->b,
2605 shader->selector ? shader->selector->tokens : NULL);
2606
2607 if (dump && !binary->disassembled) {
2608 fprintf(stderr, "SI CODE:\n");
2609 for (i = 0; i < binary->code_size; i+=4 ) {
2610 fprintf(stderr, "@0x%x: %02x%02x%02x%02x\n", i, binary->code[i + 3],
2611 binary->code[i + 2], binary->code[i + 1],
2612 binary->code[i]);
2613 }
2614 }
2615
2616 si_shader_binary_read_config(sscreen, shader, 0);
2617
2618 /* copy new shader */
2619 code_size = binary->code_size + binary->rodata_size;
2620 r600_resource_reference(&shader->bo, NULL);
2621 shader->bo = si_resource_create_custom(&sscreen->b.b, PIPE_USAGE_IMMUTABLE,
2622 code_size);
2623 if (shader->bo == NULL) {
2624 return -ENOMEM;
2625 }
2626
2627
2628 ptr = sscreen->b.ws->buffer_map(shader->bo->cs_buf, NULL, PIPE_TRANSFER_READ_WRITE);
2629 util_memcpy_cpu_to_le32(ptr, binary->code, binary->code_size);
2630 if (binary->rodata_size > 0) {
2631 ptr += binary->code_size;
2632 util_memcpy_cpu_to_le32(ptr, binary->rodata, binary->rodata_size);
2633 }
2634
2635 sscreen->b.ws->buffer_unmap(shader->bo->cs_buf);
2636
2637 return 0;
2638 }
2639
2640 int si_compile_llvm(struct si_screen *sscreen, struct si_shader *shader,
2641 LLVMModuleRef mod)
2642 {
2643 int r = 0;
2644 bool dump = r600_can_dump_shader(&sscreen->b,
2645 shader->selector ? shader->selector->tokens : NULL);
2646 r = radeon_llvm_compile(mod, &shader->binary,
2647 r600_get_llvm_processor_name(sscreen->b.family), dump, sscreen->tm);
2648
2649 if (r) {
2650 return r;
2651 }
2652 r = si_shader_binary_read(sscreen, shader, &shader->binary);
2653
2654 FREE(shader->binary.config);
2655 FREE(shader->binary.rodata);
2656 FREE(shader->binary.global_symbol_offsets);
2657 if (shader->scratch_bytes_per_wave == 0) {
2658 FREE(shader->binary.code);
2659 FREE(shader->binary.relocs);
2660 memset(&shader->binary, 0, sizeof(shader->binary));
2661 }
2662 return r;
2663 }
2664
2665 /* Generate code for the hardware VS shader stage to go with a geometry shader */
2666 static int si_generate_gs_copy_shader(struct si_screen *sscreen,
2667 struct si_shader_context *si_shader_ctx,
2668 struct si_shader *gs, bool dump)
2669 {
2670 struct gallivm_state *gallivm = &si_shader_ctx->radeon_bld.gallivm;
2671 struct lp_build_tgsi_context *bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
2672 struct lp_build_context *base = &bld_base->base;
2673 struct lp_build_context *uint = &bld_base->uint_bld;
2674 struct si_shader *shader = si_shader_ctx->shader;
2675 struct si_shader_output_values *outputs;
2676 struct tgsi_shader_info *gsinfo = &gs->selector->info;
2677 LLVMValueRef args[9];
2678 int i, r;
2679
2680 outputs = MALLOC(gsinfo->num_outputs * sizeof(outputs[0]));
2681
2682 si_shader_ctx->type = TGSI_PROCESSOR_VERTEX;
2683 shader->is_gs_copy_shader = true;
2684
2685 radeon_llvm_context_init(&si_shader_ctx->radeon_bld);
2686
2687 create_meta_data(si_shader_ctx);
2688 create_function(si_shader_ctx);
2689 preload_streamout_buffers(si_shader_ctx);
2690 preload_ring_buffers(si_shader_ctx);
2691
2692 args[0] = si_shader_ctx->gsvs_ring;
2693 args[1] = lp_build_mul_imm(uint,
2694 LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
2695 si_shader_ctx->param_vertex_id),
2696 4);
2697 args[3] = uint->zero;
2698 args[4] = uint->one; /* OFFEN */
2699 args[5] = uint->zero; /* IDXEN */
2700 args[6] = uint->one; /* GLC */
2701 args[7] = uint->one; /* SLC */
2702 args[8] = uint->zero; /* TFE */
2703
2704 /* Fetch vertex data from GSVS ring */
2705 for (i = 0; i < gsinfo->num_outputs; ++i) {
2706 unsigned chan;
2707
2708 outputs[i].name = gsinfo->output_semantic_name[i];
2709 outputs[i].sid = gsinfo->output_semantic_index[i];
2710
2711 for (chan = 0; chan < 4; chan++) {
2712 args[2] = lp_build_const_int32(gallivm,
2713 (i * 4 + chan) *
2714 gs->selector->gs_max_out_vertices * 16 * 4);
2715
2716 outputs[i].values[chan] =
2717 LLVMBuildBitCast(gallivm->builder,
2718 build_intrinsic(gallivm->builder,
2719 "llvm.SI.buffer.load.dword.i32.i32",
2720 LLVMInt32TypeInContext(gallivm->context),
2721 args, 9,
2722 LLVMReadOnlyAttribute | LLVMNoUnwindAttribute),
2723 base->elem_type, "");
2724 }
2725 }
2726
2727 si_llvm_export_vs(bld_base, outputs, gsinfo->num_outputs);
2728
2729 radeon_llvm_finalize_module(&si_shader_ctx->radeon_bld);
2730
2731 if (dump)
2732 fprintf(stderr, "Copy Vertex Shader for Geometry Shader:\n\n");
2733
2734 r = si_compile_llvm(sscreen, si_shader_ctx->shader,
2735 bld_base->base.gallivm->module);
2736
2737 radeon_llvm_dispose(&si_shader_ctx->radeon_bld);
2738
2739 FREE(outputs);
2740 return r;
2741 }
2742
2743 static void si_dump_key(unsigned shader, union si_shader_key *key)
2744 {
2745 int i;
2746
2747 fprintf(stderr, "SHADER KEY\n");
2748
2749 switch (shader) {
2750 case PIPE_SHADER_VERTEX:
2751 fprintf(stderr, " instance_divisors = {");
2752 for (i = 0; i < Elements(key->vs.instance_divisors); i++)
2753 fprintf(stderr, !i ? "%u" : ", %u",
2754 key->vs.instance_divisors[i]);
2755 fprintf(stderr, "}\n");
2756
2757 if (key->vs.as_es)
2758 fprintf(stderr, " gs_used_inputs = 0x%"PRIx64"\n",
2759 key->vs.gs_used_inputs);
2760 fprintf(stderr, " as_es = %u\n", key->vs.as_es);
2761 break;
2762
2763 case PIPE_SHADER_GEOMETRY:
2764 break;
2765
2766 case PIPE_SHADER_FRAGMENT:
2767 fprintf(stderr, " export_16bpc = 0x%X\n", key->ps.export_16bpc);
2768 fprintf(stderr, " last_cbuf = %u\n", key->ps.last_cbuf);
2769 fprintf(stderr, " color_two_side = %u\n", key->ps.color_two_side);
2770 fprintf(stderr, " alpha_func = %u\n", key->ps.alpha_func);
2771 fprintf(stderr, " alpha_to_one = %u\n", key->ps.alpha_to_one);
2772 fprintf(stderr, " poly_stipple = %u\n", key->ps.poly_stipple);
2773 break;
2774
2775 default:
2776 assert(0);
2777 }
2778 }
2779
2780 int si_shader_create(struct si_screen *sscreen, struct si_shader *shader)
2781 {
2782 struct si_shader_selector *sel = shader->selector;
2783 struct tgsi_token *tokens = sel->tokens;
2784 struct si_shader_context si_shader_ctx;
2785 struct lp_build_tgsi_context * bld_base;
2786 struct tgsi_shader_info stipple_shader_info;
2787 LLVMModuleRef mod;
2788 int r = 0;
2789 bool poly_stipple = sel->type == PIPE_SHADER_FRAGMENT &&
2790 shader->key.ps.poly_stipple;
2791 bool dump = r600_can_dump_shader(&sscreen->b, sel->tokens);
2792
2793 if (poly_stipple) {
2794 tokens = util_pstipple_create_fragment_shader(tokens, NULL,
2795 SI_POLY_STIPPLE_SAMPLER);
2796 tgsi_scan_shader(tokens, &stipple_shader_info);
2797 }
2798
2799 /* Dump TGSI code before doing TGSI->LLVM conversion in case the
2800 * conversion fails. */
2801 if (dump) {
2802 si_dump_key(sel->type, &shader->key);
2803 tgsi_dump(tokens, 0);
2804 si_dump_streamout(&sel->so);
2805 }
2806
2807 assert(shader->nparam == 0);
2808
2809 memset(&si_shader_ctx, 0, sizeof(si_shader_ctx));
2810 radeon_llvm_context_init(&si_shader_ctx.radeon_bld);
2811 bld_base = &si_shader_ctx.radeon_bld.soa.bld_base;
2812
2813 if (sel->type != PIPE_SHADER_COMPUTE)
2814 shader->dx10_clamp_mode = true;
2815
2816 if (sel->info.uses_kill)
2817 shader->db_shader_control |= S_02880C_KILL_ENABLE(1);
2818
2819 shader->uses_instanceid = sel->info.uses_instanceid;
2820 bld_base->info = poly_stipple ? &stipple_shader_info : &sel->info;
2821 bld_base->emit_fetch_funcs[TGSI_FILE_CONSTANT] = fetch_constant;
2822
2823 bld_base->op_actions[TGSI_OPCODE_TEX] = tex_action;
2824 bld_base->op_actions[TGSI_OPCODE_TEX2] = tex_action;
2825 bld_base->op_actions[TGSI_OPCODE_TXB] = tex_action;
2826 bld_base->op_actions[TGSI_OPCODE_TXB2] = tex_action;
2827 bld_base->op_actions[TGSI_OPCODE_TXD] = tex_action;
2828 bld_base->op_actions[TGSI_OPCODE_TXF] = tex_action;
2829 bld_base->op_actions[TGSI_OPCODE_TXL] = tex_action;
2830 bld_base->op_actions[TGSI_OPCODE_TXL2] = tex_action;
2831 bld_base->op_actions[TGSI_OPCODE_TXP] = tex_action;
2832 bld_base->op_actions[TGSI_OPCODE_TXQ] = txq_action;
2833 bld_base->op_actions[TGSI_OPCODE_TG4] = tex_action;
2834 bld_base->op_actions[TGSI_OPCODE_LODQ] = tex_action;
2835
2836 bld_base->op_actions[TGSI_OPCODE_DDX].emit = si_llvm_emit_ddxy;
2837 bld_base->op_actions[TGSI_OPCODE_DDY].emit = si_llvm_emit_ddxy;
2838
2839 bld_base->op_actions[TGSI_OPCODE_EMIT].emit = si_llvm_emit_vertex;
2840 bld_base->op_actions[TGSI_OPCODE_ENDPRIM].emit = si_llvm_emit_primitive;
2841
2842 if (HAVE_LLVM >= 0x0306) {
2843 bld_base->op_actions[TGSI_OPCODE_MAX].emit = build_tgsi_intrinsic_nomem;
2844 bld_base->op_actions[TGSI_OPCODE_MAX].intr_name = "llvm.maxnum.f32";
2845 bld_base->op_actions[TGSI_OPCODE_MIN].emit = build_tgsi_intrinsic_nomem;
2846 bld_base->op_actions[TGSI_OPCODE_MIN].intr_name = "llvm.minnum.f32";
2847 }
2848
2849 si_shader_ctx.radeon_bld.load_system_value = declare_system_value;
2850 si_shader_ctx.shader = shader;
2851 si_shader_ctx.type = tgsi_get_processor_type(tokens);
2852 si_shader_ctx.screen = sscreen;
2853
2854 switch (si_shader_ctx.type) {
2855 case TGSI_PROCESSOR_VERTEX:
2856 si_shader_ctx.radeon_bld.load_input = declare_input_vs;
2857 if (shader->key.vs.as_es) {
2858 bld_base->emit_epilogue = si_llvm_emit_es_epilogue;
2859 } else {
2860 bld_base->emit_epilogue = si_llvm_emit_vs_epilogue;
2861 }
2862 break;
2863 case TGSI_PROCESSOR_GEOMETRY:
2864 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_gs;
2865 bld_base->emit_epilogue = si_llvm_emit_gs_epilogue;
2866 break;
2867 case TGSI_PROCESSOR_FRAGMENT:
2868 si_shader_ctx.radeon_bld.load_input = declare_input_fs;
2869 bld_base->emit_epilogue = si_llvm_emit_fs_epilogue;
2870
2871 switch (sel->info.properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT]) {
2872 case TGSI_FS_DEPTH_LAYOUT_GREATER:
2873 shader->db_shader_control |=
2874 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_GREATER_THAN_Z);
2875 break;
2876 case TGSI_FS_DEPTH_LAYOUT_LESS:
2877 shader->db_shader_control |=
2878 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_LESS_THAN_Z);
2879 break;
2880 }
2881 break;
2882 default:
2883 assert(!"Unsupported shader type");
2884 return -1;
2885 }
2886
2887 create_meta_data(&si_shader_ctx);
2888 create_function(&si_shader_ctx);
2889 preload_constants(&si_shader_ctx);
2890 preload_samplers(&si_shader_ctx);
2891 preload_streamout_buffers(&si_shader_ctx);
2892 preload_ring_buffers(&si_shader_ctx);
2893
2894 if (si_shader_ctx.type == TGSI_PROCESSOR_GEOMETRY) {
2895 si_shader_ctx.gs_next_vertex =
2896 lp_build_alloca(bld_base->base.gallivm,
2897 bld_base->uint_bld.elem_type, "");
2898 }
2899
2900 if (!lp_build_tgsi_llvm(bld_base, tokens)) {
2901 fprintf(stderr, "Failed to translate shader from TGSI to LLVM\n");
2902 goto out;
2903 }
2904
2905 radeon_llvm_finalize_module(&si_shader_ctx.radeon_bld);
2906
2907 mod = bld_base->base.gallivm->module;
2908 r = si_compile_llvm(sscreen, shader, mod);
2909 if (r) {
2910 fprintf(stderr, "LLVM failed to compile shader\n");
2911 goto out;
2912 }
2913
2914 radeon_llvm_dispose(&si_shader_ctx.radeon_bld);
2915
2916 if (si_shader_ctx.type == TGSI_PROCESSOR_GEOMETRY) {
2917 shader->gs_copy_shader = CALLOC_STRUCT(si_shader);
2918 shader->gs_copy_shader->selector = shader->selector;
2919 shader->gs_copy_shader->key = shader->key;
2920 si_shader_ctx.shader = shader->gs_copy_shader;
2921 if ((r = si_generate_gs_copy_shader(sscreen, &si_shader_ctx,
2922 shader, dump))) {
2923 free(shader->gs_copy_shader);
2924 shader->gs_copy_shader = NULL;
2925 goto out;
2926 }
2927 }
2928
2929 out:
2930 for (int i = 0; i < SI_NUM_CONST_BUFFERS; i++)
2931 FREE(si_shader_ctx.constants[i]);
2932 if (poly_stipple)
2933 tgsi_free_tokens(tokens);
2934 return r;
2935 }
2936
2937 void si_shader_destroy(struct pipe_context *ctx, struct si_shader *shader)
2938 {
2939 if (shader->gs_copy_shader)
2940 si_shader_destroy(ctx, shader->gs_copy_shader);
2941
2942 if (shader->scratch_bo)
2943 r600_resource_reference(&shader->scratch_bo, NULL);
2944
2945 r600_resource_reference(&shader->bo, NULL);
2946
2947 FREE(shader->binary.code);
2948 FREE(shader->binary.relocs);
2949 }