src/gallium/drivers/radeonsi/si_shader.h

   1 /*
   2  * Copyright 2012 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Tom Stellard <thomas.stellard@amd.com>
  25  *      Michel Dänzer <michel.daenzer@amd.com>
  26  *      Christian König <christian.koenig@amd.com>
  27  */
  28
  29 /* How linking tessellation shader inputs and outputs works.
  30  *
  31  * Inputs and outputs between shaders are stored in a buffer. This buffer
  32  * lives in LDS (typical case for tessellation), but it can also live
  33  * in memory. Each input or output has a fixed location within a vertex.
  34  * The highest used input or output determines the stride between vertices.
  35  *
  36  * Since tessellation is only enabled in the OpenGL core profile,
  37  * only these semantics are valid for per-vertex data:
  38  *
  39  *   Name             Location
  40  *
  41  *   POSITION         0
  42  *   PSIZE            1
  43  *   CLIPDIST0..1     2..3
  44  *   CULLDIST0..1     (not implemented)
  45  *   GENERIC0..31     4..35
  46  *
  47  * For example, a shader only writing GENERIC0 has the output stride of 5.
  48  *
  49  * Only these semantics are valid for per-patch data:
  50  *
  51  *   Name             Location
  52  *
  53  *   TESSOUTER        0
  54  *   TESSINNER        1
  55  *   PATCH0..29       2..31
  56  *
  57  * That's how independent shaders agree on input and output locations.
  58  * The si_shader_io_get_unique_index function assigns the locations.
  59  *
  60  * Other required information for calculating the input and output addresses
  61  * like the vertex stride, the patch stride, and the offsets where per-vertex
  62  * and per-patch data start, is passed to the shader via user data SGPRs.
  63  * The offsets and strides are calculated at draw time and aren't available
  64  * at compile time.
  65  *
  66  * The same approach should be used for linking ES->GS in the future.
  67  */
  68
  69 #ifndef SI_SHADER_H
  70 #define SI_SHADER_H
  71
  72 #include <llvm-c/Core.h> /* LLVMModuleRef */
  73 #include "tgsi/tgsi_scan.h"
  74 #include "si_state.h"
  75
  76 struct radeon_shader_binary;
  77 struct radeon_shader_reloc;
  78
  79 #define SI_SGPR_RW_BUFFERS      0  /* rings (& stream-out, VS only) */
  80 #define SI_SGPR_CONST           2
  81 #define SI_SGPR_SAMPLER         4
  82 #define SI_SGPR_RESOURCE        6
  83 #define SI_SGPR_VERTEX_BUFFER   8  /* VS only */
  84 #define SI_SGPR_BASE_VERTEX     10 /* VS only */
  85 #define SI_SGPR_START_INSTANCE  11 /* VS only */
  86 #define SI_SGPR_LS_OUT_LAYOUT   12 /* VS(LS) only */
  87 #define SI_SGPR_TCS_OUT_OFFSETS 8  /* TCS & TES only */
  88 #define SI_SGPR_TCS_OUT_LAYOUT  9  /* TCS & TES only */
  89 #define SI_SGPR_TCS_IN_LAYOUT   10 /* TCS only */
  90 #define SI_SGPR_ALPHA_REF       8  /* PS only */
  91
  92 #define SI_VS_NUM_USER_SGPR     12
  93 #define SI_LS_NUM_USER_SGPR     13
  94 #define SI_TCS_NUM_USER_SGPR    11
  95 #define SI_TES_NUM_USER_SGPR    10
  96 #define SI_GS_NUM_USER_SGPR     8
  97 #define SI_GSCOPY_NUM_USER_SGPR 4
  98 #define SI_PS_NUM_USER_SGPR     9
  99
 100 /* LLVM function parameter indices */
 101 #define SI_PARAM_RW_BUFFERS     0
 102 #define SI_PARAM_CONST          1
 103 #define SI_PARAM_SAMPLER        2
 104 #define SI_PARAM_RESOURCE       3
 105
 106 /* VS only parameters */
 107 #define SI_PARAM_VERTEX_BUFFER  4
 108 #define SI_PARAM_BASE_VERTEX    5
 109 #define SI_PARAM_START_INSTANCE 6
 110 /* the other VS parameters are assigned dynamically */
 111
 112 /* Offsets where TCS outputs and TCS patch outputs live in LDS:
 113  *   [0:15] = TCS output patch0 offset / 16, max = NUM_PATCHES * 32 * 32
 114  *   [16:31] = TCS output patch0 offset for per-patch / 16, max = NUM_PATCHES*32*32* + 32*32
 115  */
 116 #define SI_PARAM_TCS_OUT_OFFSETS 4 /* for TCS & TES */
 117
 118 /* Layout of TCS outputs / TES inputs:
 119  *   [0:12] = stride between output patches in dwords, num_outputs * num_vertices * 4, max = 32*32*4
 120  *   [13:20] = stride between output vertices in dwords = num_inputs * 4, max = 32*4
 121  *   [26:31] = gl_PatchVerticesIn, max = 32
 122  */
 123 #define SI_PARAM_TCS_OUT_LAYOUT 5 /* for TCS & TES */
 124
 125 /* Layout of LS outputs / TCS inputs
 126  *   [0:12] = stride between patches in dwords = num_inputs * num_vertices * 4, max = 32*32*4
 127  *   [13:20] = stride between vertices in dwords = num_inputs * 4, max = 32*4
 128  */
 129 #define SI_PARAM_TCS_IN_LAYOUT  6 /* TCS only */
 130 #define SI_PARAM_LS_OUT_LAYOUT  7 /* same value as TCS_IN_LAYOUT, LS only */
 131
 132 /* TCS only parameters. */
 133 #define SI_PARAM_TESS_FACTOR_OFFSET 7
 134 #define SI_PARAM_PATCH_ID       8
 135 #define SI_PARAM_REL_IDS        9
 136
 137 /* GS only parameters */
 138 #define SI_PARAM_GS2VS_OFFSET   4
 139 #define SI_PARAM_GS_WAVE_ID     5
 140 #define SI_PARAM_VTX0_OFFSET    6
 141 #define SI_PARAM_VTX1_OFFSET    7
 142 #define SI_PARAM_PRIMITIVE_ID   8
 143 #define SI_PARAM_VTX2_OFFSET    9
 144 #define SI_PARAM_VTX3_OFFSET    10
 145 #define SI_PARAM_VTX4_OFFSET    11
 146 #define SI_PARAM_VTX5_OFFSET    12
 147 #define SI_PARAM_GS_INSTANCE_ID 13
 148
 149 /* PS only parameters */
 150 #define SI_PARAM_ALPHA_REF              4
 151 #define SI_PARAM_PRIM_MASK              5
 152 #define SI_PARAM_PERSP_SAMPLE           6
 153 #define SI_PARAM_PERSP_CENTER           7
 154 #define SI_PARAM_PERSP_CENTROID         8
 155 #define SI_PARAM_PERSP_PULL_MODEL       9
 156 #define SI_PARAM_LINEAR_SAMPLE          10
 157 #define SI_PARAM_LINEAR_CENTER          11
 158 #define SI_PARAM_LINEAR_CENTROID        12
 159 #define SI_PARAM_LINE_STIPPLE_TEX       13
 160 #define SI_PARAM_POS_X_FLOAT            14
 161 #define SI_PARAM_POS_Y_FLOAT            15
 162 #define SI_PARAM_POS_Z_FLOAT            16
 163 #define SI_PARAM_POS_W_FLOAT            17
 164 #define SI_PARAM_FRONT_FACE             18
 165 #define SI_PARAM_ANCILLARY              19
 166 #define SI_PARAM_SAMPLE_COVERAGE        20
 167 #define SI_PARAM_POS_FIXED_PT           21
 168
 169 #define SI_NUM_PARAMS (SI_PARAM_POS_FIXED_PT + 1)
 170
 171 struct si_shader;
 172
 173 struct si_shader_selector {
 174         struct si_shader *current;
 175
 176         struct tgsi_token       *tokens;
 177         struct pipe_stream_output_info  so;
 178         struct tgsi_shader_info         info;
 179
 180         unsigned        num_shaders;
 181
 182         /* PIPE_SHADER_[VERTEX|FRAGMENT|...] */
 183         unsigned        type;
 184
 185         unsigned        gs_output_prim;
 186         unsigned        gs_max_out_vertices;
 187         unsigned        gs_num_invocations;
 188
 189         /* masks of "get_unique_index" bits */
 190         uint64_t        inputs_read;
 191         uint64_t        outputs_written;
 192         uint32_t        patch_outputs_written;
 193 };
 194
 195 /* Valid shader configurations:
 196  *
 197  * API shaders       VS | TCS | TES | GS |pass| PS
 198  * are compiled as:     |     |     |    |thru|
 199  *                      |     |     |    |    |
 200  * Only VS & PS:     VS | --  | --  | -- | -- | PS
 201  * With GS:          ES | --  | --  | GS | VS | PS
 202  * With Tessel.:     LS | HS  | VS  | -- | -- | PS
 203  * With both:        LS | HS  | ES  | GS | VS | PS
 204  */
 205
 206 union si_shader_key {
 207         struct {
 208                 unsigned        export_16bpc:8;
 209                 unsigned        last_cbuf:3;
 210                 unsigned        color_two_side:1;
 211                 unsigned        alpha_func:3;
 212                 unsigned        alpha_to_one:1;
 213                 unsigned        poly_stipple:1;
 214                 unsigned        poly_line_smoothing:1;
 215         } ps;
 216         struct {
 217                 unsigned        instance_divisors[SI_NUM_VERTEX_BUFFERS];
 218                 /* Mask of "get_unique_index" bits - which outputs are read
 219                  * by the next stage (needed by ES).
 220                  * This describes how outputs are laid out in memory. */
 221                 uint64_t        es_enabled_outputs;
 222                 unsigned        as_es:1; /* export shader */
 223                 unsigned        as_ls:1; /* local shader */
 224         } vs;
 225         struct {
 226                 unsigned        prim_mode:3;
 227         } tcs; /* tessellation control shader */
 228         struct {
 229                 /* Mask of "get_unique_index" bits - which outputs are read
 230                  * by the next stage (needed by ES).
 231                  * This describes how outputs are laid out in memory. */
 232                 uint64_t        es_enabled_outputs;
 233                 unsigned        as_es:1; /* export shader */
 234         } tes; /* tessellation evaluation shader */
 235 };
 236
 237 struct si_shader {
 238         struct si_shader_selector       *selector;
 239         struct si_shader                *next_variant;
 240
 241         struct si_shader                *gs_copy_shader;
 242         struct si_pm4_state             *pm4;
 243         struct r600_resource            *bo;
 244         struct r600_resource            *scratch_bo;
 245         struct radeon_shader_binary     binary;
 246         unsigned                        num_sgprs;
 247         unsigned                        num_vgprs;
 248         unsigned                        lds_size;
 249         unsigned                        spi_ps_input_ena;
 250         unsigned                        float_mode;
 251         unsigned                        scratch_bytes_per_wave;
 252         unsigned                        spi_shader_col_format;
 253         unsigned                        spi_shader_z_format;
 254         unsigned                        db_shader_control;
 255         unsigned                        cb_shader_mask;
 256         union si_shader_key             key;
 257
 258         unsigned                nparam;
 259         unsigned                vs_output_param_offset[PIPE_MAX_SHADER_OUTPUTS];
 260         unsigned                ps_input_param_offset[PIPE_MAX_SHADER_INPUTS];
 261         unsigned                ps_input_interpolate[PIPE_MAX_SHADER_INPUTS];
 262         bool                    uses_instanceid;
 263         unsigned                nr_pos_exports;
 264         unsigned                nr_param_exports;
 265         bool                    is_gs_copy_shader;
 266         bool                    dx10_clamp_mode; /* convert NaNs to 0 */
 267
 268         unsigned                ls_rsrc1;
 269         unsigned                ls_rsrc2;
 270 };
 271
 272 static inline struct tgsi_shader_info *si_get_vs_info(struct si_context *sctx)
 273 {
 274         if (sctx->gs_shader)
 275                 return &sctx->gs_shader->info;
 276         else if (sctx->tes_shader)
 277                 return &sctx->tes_shader->info;
 278         else
 279                 return &sctx->vs_shader->info;
 280 }
 281
 282 static inline struct si_shader* si_get_vs_state(struct si_context *sctx)
 283 {
 284         if (sctx->gs_shader)
 285                 return sctx->gs_shader->current->gs_copy_shader;
 286         else if (sctx->tes_shader)
 287                 return sctx->tes_shader->current;
 288         else
 289                 return sctx->vs_shader->current;
 290 }
 291
 292 /* radeonsi_shader.c */
 293 int si_shader_create(struct si_screen *sscreen, LLVMTargetMachineRef tm,
 294                      struct si_shader *shader);
 295 int si_compile_llvm(struct si_screen *sscreen, struct si_shader *shader,
 296                     LLVMTargetMachineRef tm, LLVMModuleRef mod);
 297 void si_shader_destroy(struct pipe_context *ctx, struct si_shader *shader);
 298 unsigned si_shader_io_get_unique_index(unsigned semantic_name, unsigned index);
 299 int si_shader_binary_upload(struct si_screen *sscreen, struct si_shader *shader);
 300 int si_shader_binary_read(struct si_screen *sscreen, struct si_shader *shader);
 301 void si_shader_apply_scratch_relocs(struct si_context *sctx,
 302                         struct si_shader *shader,
 303                         uint64_t scratch_va);
 304 void si_shader_binary_read_config(const struct si_screen *sscreen,
 305                                 struct si_shader *shader,
 306                                 unsigned symbol_offset);
 307
 308 #endif