2 * Copyright 2012 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 * Tom Stellard <thomas.stellard@amd.com>
25 * Michel Dänzer <michel.daenzer@amd.com>
26 * Christian König <christian.koenig@amd.com>
29 /* How linking tessellation shader inputs and outputs works.
31 * Inputs and outputs between shaders are stored in a buffer. This buffer
32 * lives in LDS (typical case for tessellation), but it can also live
33 * in memory. Each input or output has a fixed location within a vertex.
34 * The highest used input or output determines the stride between vertices.
36 * Since tessellation is only enabled in the OpenGL core profile,
37 * only these semantics are valid for per-vertex data:
44 * CULLDIST0..1 (not implemented)
47 * For example, a shader only writing GENERIC0 has the output stride of 5.
49 * Only these semantics are valid for per-patch data:
57 * That's how independent shaders agree on input and output locations.
58 * The si_shader_io_get_unique_index function assigns the locations.
60 * Other required information for calculating the input and output addresses
61 * like the vertex stride, the patch stride, and the offsets where per-vertex
62 * and per-patch data start, is passed to the shader via user data SGPRs.
63 * The offsets and strides are calculated at draw time and aren't available
66 * The same approach should be used for linking ES->GS in the future.
72 #include <llvm-c/Core.h> /* LLVMModuleRef */
73 #include "tgsi/tgsi_scan.h"
76 struct radeon_shader_binary
;
77 struct radeon_shader_reloc
;
79 #define SI_SGPR_RW_BUFFERS 0 /* rings (& stream-out, VS only) */
80 #define SI_SGPR_CONST 2
81 #define SI_SGPR_SAMPLER 4
82 #define SI_SGPR_RESOURCE 6
83 #define SI_SGPR_VERTEX_BUFFER 8 /* VS only */
84 #define SI_SGPR_BASE_VERTEX 10 /* VS only */
85 #define SI_SGPR_START_INSTANCE 11 /* VS only */
86 #define SI_SGPR_VS_STATE_BITS 12 /* VS(VS) only */
87 #define SI_SGPR_LS_OUT_LAYOUT 12 /* VS(LS) only */
88 #define SI_SGPR_TCS_OUT_OFFSETS 8 /* TCS & TES only */
89 #define SI_SGPR_TCS_OUT_LAYOUT 9 /* TCS & TES only */
90 #define SI_SGPR_TCS_IN_LAYOUT 10 /* TCS only */
91 #define SI_SGPR_ALPHA_REF 8 /* PS only */
92 #define SI_SGPR_PS_STATE_BITS 9 /* PS only */
94 #define SI_VS_NUM_USER_SGPR 13 /* API VS */
95 #define SI_ES_NUM_USER_SGPR 12 /* API VS */
96 #define SI_LS_NUM_USER_SGPR 13 /* API VS */
97 #define SI_TCS_NUM_USER_SGPR 11
98 #define SI_TES_NUM_USER_SGPR 10
99 #define SI_GS_NUM_USER_SGPR 8
100 #define SI_GSCOPY_NUM_USER_SGPR 4
101 #define SI_PS_NUM_USER_SGPR 10
103 /* LLVM function parameter indices */
104 #define SI_PARAM_RW_BUFFERS 0
105 #define SI_PARAM_CONST 1
106 #define SI_PARAM_SAMPLER 2
107 #define SI_PARAM_RESOURCE 3
109 /* VS only parameters */
110 #define SI_PARAM_VERTEX_BUFFER 4
111 #define SI_PARAM_BASE_VERTEX 5
112 #define SI_PARAM_START_INSTANCE 6
113 /* [0] = clamp vertex color */
114 #define SI_PARAM_VS_STATE_BITS 7
115 /* the other VS parameters are assigned dynamically */
117 /* Offsets where TCS outputs and TCS patch outputs live in LDS:
118 * [0:15] = TCS output patch0 offset / 16, max = NUM_PATCHES * 32 * 32
119 * [16:31] = TCS output patch0 offset for per-patch / 16, max = NUM_PATCHES*32*32* + 32*32
121 #define SI_PARAM_TCS_OUT_OFFSETS 4 /* for TCS & TES */
123 /* Layout of TCS outputs / TES inputs:
124 * [0:12] = stride between output patches in dwords, num_outputs * num_vertices * 4, max = 32*32*4
125 * [13:20] = stride between output vertices in dwords = num_inputs * 4, max = 32*4
126 * [26:31] = gl_PatchVerticesIn, max = 32
128 #define SI_PARAM_TCS_OUT_LAYOUT 5 /* for TCS & TES */
130 /* Layout of LS outputs / TCS inputs
131 * [0:12] = stride between patches in dwords = num_inputs * num_vertices * 4, max = 32*32*4
132 * [13:20] = stride between vertices in dwords = num_inputs * 4, max = 32*4
134 #define SI_PARAM_TCS_IN_LAYOUT 6 /* TCS only */
135 #define SI_PARAM_LS_OUT_LAYOUT 7 /* same value as TCS_IN_LAYOUT, LS only */
137 /* TCS only parameters. */
138 #define SI_PARAM_TESS_FACTOR_OFFSET 7
139 #define SI_PARAM_PATCH_ID 8
140 #define SI_PARAM_REL_IDS 9
142 /* GS only parameters */
143 #define SI_PARAM_GS2VS_OFFSET 4
144 #define SI_PARAM_GS_WAVE_ID 5
145 #define SI_PARAM_VTX0_OFFSET 6
146 #define SI_PARAM_VTX1_OFFSET 7
147 #define SI_PARAM_PRIMITIVE_ID 8
148 #define SI_PARAM_VTX2_OFFSET 9
149 #define SI_PARAM_VTX3_OFFSET 10
150 #define SI_PARAM_VTX4_OFFSET 11
151 #define SI_PARAM_VTX5_OFFSET 12
152 #define SI_PARAM_GS_INSTANCE_ID 13
154 /* PS only parameters */
155 #define SI_PARAM_ALPHA_REF 4
157 * 0: force_persample_interp
159 #define SI_PARAM_PS_STATE_BITS 5
160 #define SI_PARAM_PRIM_MASK 6
161 #define SI_PARAM_PERSP_SAMPLE 7
162 #define SI_PARAM_PERSP_CENTER 8
163 #define SI_PARAM_PERSP_CENTROID 9
164 #define SI_PARAM_PERSP_PULL_MODEL 10
165 #define SI_PARAM_LINEAR_SAMPLE 11
166 #define SI_PARAM_LINEAR_CENTER 12
167 #define SI_PARAM_LINEAR_CENTROID 13
168 #define SI_PARAM_LINE_STIPPLE_TEX 14
169 #define SI_PARAM_POS_X_FLOAT 15
170 #define SI_PARAM_POS_Y_FLOAT 16
171 #define SI_PARAM_POS_Z_FLOAT 17
172 #define SI_PARAM_POS_W_FLOAT 18
173 #define SI_PARAM_FRONT_FACE 19
174 #define SI_PARAM_ANCILLARY 20
175 #define SI_PARAM_SAMPLE_COVERAGE 21
176 #define SI_PARAM_POS_FIXED_PT 22
178 #define SI_NUM_PARAMS (SI_PARAM_POS_FIXED_PT + 1)
182 /* A shader selector is a gallium CSO and contains shader variants and
183 * binaries for one TGSI program. This can be shared by multiple contexts.
185 struct si_shader_selector
{
187 struct si_shader
*first_variant
; /* immutable after the first variant */
188 struct si_shader
*last_variant
; /* mutable */
190 struct tgsi_token
*tokens
;
191 struct pipe_stream_output_info so
;
192 struct tgsi_shader_info info
;
194 /* PIPE_SHADER_[VERTEX|FRAGMENT|...] */
197 /* Whether the shader has to use a conditional assignment to
198 * choose between weights when emulating
199 * pipe_rasterizer_state::force_persample_interp.
200 * If false, "si_emit_spi_ps_input" will take care of it instead.
202 bool forces_persample_interp_for_persp
;
203 bool forces_persample_interp_for_linear
;
205 unsigned gs_output_prim
;
206 unsigned gs_max_out_vertices
;
207 unsigned gs_num_invocations
;
208 unsigned gsvs_itemsize
;
210 /* masks of "get_unique_index" bits */
211 uint64_t inputs_read
;
212 uint64_t outputs_written
;
213 uint32_t patch_outputs_written
;
214 uint32_t ps_colors_written
;
217 /* Valid shader configurations:
219 * API shaders VS | TCS | TES | GS |pass| PS
220 * are compiled as: | | | |thru|
222 * Only VS & PS: VS | -- | -- | -- | -- | PS
223 * With GS: ES | -- | -- | GS | VS | PS
224 * With Tessel.: LS | HS | VS | -- | -- | PS
225 * With both: LS | HS | ES | GS | VS | PS
228 union si_shader_key
{
230 unsigned export_16bpc
:8;
231 unsigned last_cbuf
:3;
232 unsigned color_two_side
:1;
233 unsigned alpha_func
:3;
234 unsigned alpha_to_one
:1;
235 unsigned poly_stipple
:1;
236 unsigned poly_line_smoothing
:1;
237 unsigned clamp_color
:1;
240 unsigned instance_divisors
[SI_NUM_VERTEX_BUFFERS
];
241 /* Mask of "get_unique_index" bits - which outputs are read
242 * by the next stage (needed by ES).
243 * This describes how outputs are laid out in memory. */
244 uint64_t es_enabled_outputs
;
245 unsigned as_es
:1; /* export shader */
246 unsigned as_ls
:1; /* local shader */
247 unsigned export_prim_id
; /* when PS needs it and GS is disabled */
250 unsigned prim_mode
:3;
251 } tcs
; /* tessellation control shader */
253 /* Mask of "get_unique_index" bits - which outputs are read
254 * by the next stage (needed by ES).
255 * This describes how outputs are laid out in memory. */
256 uint64_t es_enabled_outputs
;
257 unsigned as_es
:1; /* export shader */
258 unsigned export_prim_id
; /* when PS needs it and GS is disabled */
259 } tes
; /* tessellation evaluation shader */
263 struct si_shader_selector
*selector
;
264 struct si_shader
*next_variant
;
266 struct si_shader
*gs_copy_shader
;
267 struct si_pm4_state
*pm4
;
268 struct r600_resource
*bo
;
269 struct r600_resource
*scratch_bo
;
270 struct radeon_shader_binary binary
;
274 unsigned spi_ps_input_ena
;
276 unsigned scratch_bytes_per_wave
;
277 unsigned spi_shader_col_format
;
278 unsigned spi_shader_z_format
;
279 unsigned db_shader_control
;
280 unsigned cb_shader_mask
;
281 union si_shader_key key
;
284 unsigned vs_output_param_offset
[PIPE_MAX_SHADER_OUTPUTS
];
285 unsigned ps_input_param_offset
[PIPE_MAX_SHADER_INPUTS
];
286 unsigned ps_input_interpolate
[PIPE_MAX_SHADER_INPUTS
];
287 bool uses_instanceid
;
288 unsigned nr_pos_exports
;
289 unsigned nr_param_exports
;
290 bool is_gs_copy_shader
;
291 bool dx10_clamp_mode
; /* convert NaNs to 0 */
297 static inline struct tgsi_shader_info
*si_get_vs_info(struct si_context
*sctx
)
299 if (sctx
->gs_shader
.cso
)
300 return &sctx
->gs_shader
.cso
->info
;
301 else if (sctx
->tes_shader
.cso
)
302 return &sctx
->tes_shader
.cso
->info
;
303 else if (sctx
->vs_shader
.cso
)
304 return &sctx
->vs_shader
.cso
->info
;
309 static inline struct si_shader
* si_get_vs_state(struct si_context
*sctx
)
311 if (sctx
->gs_shader
.current
)
312 return sctx
->gs_shader
.current
->gs_copy_shader
;
313 else if (sctx
->tes_shader
.current
)
314 return sctx
->tes_shader
.current
;
316 return sctx
->vs_shader
.current
;
319 static inline bool si_vs_exports_prim_id(struct si_shader
*shader
)
321 if (shader
->selector
->type
== PIPE_SHADER_VERTEX
)
322 return shader
->key
.vs
.export_prim_id
;
323 else if (shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
)
324 return shader
->key
.tes
.export_prim_id
;
329 /* radeonsi_shader.c */
330 int si_shader_create(struct si_screen
*sscreen
, LLVMTargetMachineRef tm
,
331 struct si_shader
*shader
);
332 void si_dump_shader_key(unsigned shader
, union si_shader_key
*key
, FILE *f
);
333 int si_compile_llvm(struct si_screen
*sscreen
, struct si_shader
*shader
,
334 LLVMTargetMachineRef tm
, LLVMModuleRef mod
);
335 void si_shader_destroy(struct si_shader
*shader
);
336 unsigned si_shader_io_get_unique_index(unsigned semantic_name
, unsigned index
);
337 int si_shader_binary_upload(struct si_screen
*sscreen
, struct si_shader
*shader
);
338 int si_shader_binary_read(struct si_screen
*sscreen
, struct si_shader
*shader
);
339 void si_shader_apply_scratch_relocs(struct si_context
*sctx
,
340 struct si_shader
*shader
,
341 uint64_t scratch_va
);
342 void si_shader_binary_read_config(const struct si_screen
*sscreen
,
343 struct si_shader
*shader
,
344 unsigned symbol_offset
);