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[mesa.git] / src / gallium / drivers / radeonsi / si_shader.h
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Tom Stellard <thomas.stellard@amd.com>
25 * Michel Dänzer <michel.daenzer@amd.com>
26 * Christian König <christian.koenig@amd.com>
27 */
28
29 /* How linking shader inputs and outputs between vertex, tessellation, and
30 * geometry shaders works.
31 *
32 * Inputs and outputs between shaders are stored in a buffer. This buffer
33 * lives in LDS (typical case for tessellation), but it can also live
34 * in memory (ESGS). Each input or output has a fixed location within a vertex.
35 * The highest used input or output determines the stride between vertices.
36 *
37 * Since GS and tessellation are only possible in the OpenGL core profile,
38 * only these semantics are valid for per-vertex data:
39 *
40 * Name Location
41 *
42 * POSITION 0
43 * PSIZE 1
44 * CLIPDIST0..1 2..3
45 * CULLDIST0..1 (not implemented)
46 * GENERIC0..31 4..35
47 *
48 * For example, a shader only writing GENERIC0 has the output stride of 5.
49 *
50 * Only these semantics are valid for per-patch data:
51 *
52 * Name Location
53 *
54 * TESSOUTER 0
55 * TESSINNER 1
56 * PATCH0..29 2..31
57 *
58 * That's how independent shaders agree on input and output locations.
59 * The si_shader_io_get_unique_index function assigns the locations.
60 *
61 * For tessellation, other required information for calculating the input and
62 * output addresses like the vertex stride, the patch stride, and the offsets
63 * where per-vertex and per-patch data start, is passed to the shader via
64 * user data SGPRs. The offsets and strides are calculated at draw time and
65 * aren't available at compile time.
66 */
67
68 #ifndef SI_SHADER_H
69 #define SI_SHADER_H
70
71 #include <llvm-c/Core.h> /* LLVMModuleRef */
72 #include <llvm-c/TargetMachine.h>
73 #include "tgsi/tgsi_scan.h"
74 #include "util/u_queue.h"
75 #include "si_state.h"
76
77 struct ac_shader_binary;
78
79 #define SI_MAX_VS_OUTPUTS 40
80
81 /* SGPR user data indices */
82 enum {
83 SI_SGPR_RW_BUFFERS, /* rings (& stream-out, VS only) */
84 SI_SGPR_RW_BUFFERS_HI,
85 SI_SGPR_CONST_BUFFERS,
86 SI_SGPR_CONST_BUFFERS_HI,
87 SI_SGPR_SAMPLERS, /* images & sampler states interleaved */
88 SI_SGPR_SAMPLERS_HI,
89 SI_SGPR_IMAGES,
90 SI_SGPR_IMAGES_HI,
91 SI_SGPR_SHADER_BUFFERS,
92 SI_SGPR_SHADER_BUFFERS_HI,
93 SI_NUM_RESOURCE_SGPRS,
94
95 /* all VS variants */
96 SI_SGPR_VERTEX_BUFFERS = SI_NUM_RESOURCE_SGPRS,
97 SI_SGPR_VERTEX_BUFFERS_HI,
98 SI_SGPR_BASE_VERTEX,
99 SI_SGPR_START_INSTANCE,
100 SI_SGPR_DRAWID,
101 SI_SGPR_VS_STATE_BITS,
102 SI_VS_NUM_USER_SGPR,
103
104 /* TES */
105 SI_SGPR_TES_OFFCHIP_LAYOUT = SI_NUM_RESOURCE_SGPRS,
106 SI_TES_NUM_USER_SGPR,
107
108 /* GFX6-8: TCS only */
109 GFX6_SGPR_TCS_OFFCHIP_LAYOUT = SI_NUM_RESOURCE_SGPRS,
110 GFX6_SGPR_TCS_OUT_OFFSETS,
111 GFX6_SGPR_TCS_OUT_LAYOUT,
112 GFX6_SGPR_TCS_IN_LAYOUT,
113 GFX6_TCS_NUM_USER_SGPR,
114
115 /* GFX9: Merged LS-HS (VS-TCS) only. */
116 GFX9_SGPR_TCS_OFFCHIP_LAYOUT = SI_VS_NUM_USER_SGPR,
117 GFX9_SGPR_TCS_OUT_OFFSETS,
118 GFX9_SGPR_TCS_OUT_LAYOUT,
119 GFX9_SGPR_unused_to_align_the_next_pointer,
120 GFX9_SGPR_TCS_CONST_BUFFERS,
121 GFX9_SGPR_TCS_CONST_BUFFERS_HI,
122 GFX9_SGPR_TCS_SAMPLERS, /* images & sampler states interleaved */
123 GFX9_SGPR_TCS_SAMPLERS_HI,
124 GFX9_SGPR_TCS_IMAGES,
125 GFX9_SGPR_TCS_IMAGES_HI,
126 GFX9_SGPR_TCS_SHADER_BUFFERS,
127 GFX9_SGPR_TCS_SHADER_BUFFERS_HI,
128 GFX9_TCS_NUM_USER_SGPR,
129
130 /* GS limits */
131 SI_GS_NUM_USER_SGPR = SI_NUM_RESOURCE_SGPRS,
132 SI_GSCOPY_NUM_USER_SGPR = SI_SGPR_RW_BUFFERS_HI + 1,
133
134 /* PS only */
135 SI_SGPR_ALPHA_REF = SI_NUM_RESOURCE_SGPRS,
136 SI_PS_NUM_USER_SGPR,
137
138 /* CS only */
139 SI_SGPR_GRID_SIZE = SI_NUM_RESOURCE_SGPRS,
140 SI_SGPR_BLOCK_SIZE = SI_SGPR_GRID_SIZE + 3,
141 SI_CS_NUM_USER_SGPR = SI_SGPR_BLOCK_SIZE + 3
142 };
143
144 /* LLVM function parameter indices */
145 enum {
146 SI_PARAM_RW_BUFFERS,
147 SI_PARAM_CONST_BUFFERS,
148 SI_PARAM_SAMPLERS,
149 SI_PARAM_IMAGES,
150 SI_PARAM_SHADER_BUFFERS,
151 SI_NUM_RESOURCE_PARAMS,
152
153 /* VS only parameters */
154 SI_PARAM_VERTEX_BUFFERS = SI_NUM_RESOURCE_PARAMS,
155 SI_PARAM_BASE_VERTEX,
156 SI_PARAM_START_INSTANCE,
157 SI_PARAM_DRAWID,
158 SI_PARAM_VS_STATE_BITS,
159
160 /* Layout of TCS outputs in the offchip buffer
161 * [0:8] = the number of patches per threadgroup.
162 * [9:15] = the number of output vertices per patch.
163 * [16:31] = the offset of per patch attributes in the buffer in bytes.
164 */
165 SI_PARAM_TCS_OFFCHIP_LAYOUT = SI_NUM_RESOURCE_PARAMS, /* for TCS & TES */
166
167 /* TCS only parameters. */
168
169 /* Offsets where TCS outputs and TCS patch outputs live in LDS:
170 * [0:15] = TCS output patch0 offset / 16, max = NUM_PATCHES * 32 * 32
171 * [16:31] = TCS output patch0 offset for per-patch / 16, max = NUM_PATCHES*32*32* + 32*32
172 */
173 SI_PARAM_TCS_OUT_OFFSETS,
174
175 /* Layout of TCS outputs / TES inputs:
176 * [0:12] = stride between output patches in dwords, num_outputs * num_vertices * 4, max = 32*32*4
177 * [13:20] = stride between output vertices in dwords = num_inputs * 4, max = 32*4
178 * [26:31] = gl_PatchVerticesIn, max = 32
179 */
180 SI_PARAM_TCS_OUT_LAYOUT,
181
182 /* Layout of LS outputs / TCS inputs
183 * [8:20] = stride between patches in dwords = num_inputs * num_vertices * 4, max = 32*32*4
184 * [24:31] = stride between vertices in dwords = num_inputs * 4, max = 32*4
185 * (same layout as SI_PARAM_VS_STATE_BITS)
186 */
187 SI_PARAM_TCS_IN_LAYOUT,
188
189 SI_PARAM_TCS_OC_LDS,
190 SI_PARAM_TESS_FACTOR_OFFSET,
191 SI_PARAM_PATCH_ID,
192 SI_PARAM_REL_IDS,
193
194 /* GS only parameters */
195 SI_PARAM_GS2VS_OFFSET = SI_NUM_RESOURCE_PARAMS,
196 SI_PARAM_GS_WAVE_ID,
197 SI_PARAM_VTX0_OFFSET,
198 SI_PARAM_VTX1_OFFSET,
199 SI_PARAM_PRIMITIVE_ID,
200 SI_PARAM_VTX2_OFFSET,
201 SI_PARAM_VTX3_OFFSET,
202 SI_PARAM_VTX4_OFFSET,
203 SI_PARAM_VTX5_OFFSET,
204 SI_PARAM_GS_INSTANCE_ID,
205
206 /* PS only parameters */
207 SI_PARAM_ALPHA_REF = SI_NUM_RESOURCE_PARAMS,
208 SI_PARAM_PRIM_MASK,
209 SI_PARAM_PERSP_SAMPLE,
210 SI_PARAM_PERSP_CENTER,
211 SI_PARAM_PERSP_CENTROID,
212 SI_PARAM_PERSP_PULL_MODEL,
213 SI_PARAM_LINEAR_SAMPLE,
214 SI_PARAM_LINEAR_CENTER,
215 SI_PARAM_LINEAR_CENTROID,
216 SI_PARAM_LINE_STIPPLE_TEX,
217 SI_PARAM_POS_X_FLOAT,
218 SI_PARAM_POS_Y_FLOAT,
219 SI_PARAM_POS_Z_FLOAT,
220 SI_PARAM_POS_W_FLOAT,
221 SI_PARAM_FRONT_FACE,
222 SI_PARAM_ANCILLARY,
223 SI_PARAM_SAMPLE_COVERAGE,
224 SI_PARAM_POS_FIXED_PT,
225
226 /* CS only parameters */
227 SI_PARAM_GRID_SIZE = SI_NUM_RESOURCE_PARAMS,
228 SI_PARAM_BLOCK_SIZE,
229 SI_PARAM_BLOCK_ID,
230 SI_PARAM_THREAD_ID,
231
232 SI_NUM_PARAMS = SI_PARAM_POS_FIXED_PT + 9, /* +8 for COLOR[0..1] */
233 };
234
235 /* Fields of driver-defined VS state SGPR. */
236 /* Clamp vertex color output (only used in VS as VS). */
237 #define S_VS_STATE_CLAMP_VERTEX_COLOR(x) (((unsigned)(x) & 0x1) << 0)
238 #define C_VS_STATE_CLAMP_VERTEX_COLOR 0xFFFFFFFE
239 #define S_VS_STATE_INDEXED(x) (((unsigned)(x) & 0x1) << 1)
240 #define C_VS_STATE_INDEXED 0xFFFFFFFD
241 #define S_VS_STATE_LS_OUT_PATCH_SIZE(x) (((unsigned)(x) & 0x1FFF) << 8)
242 #define C_VS_STATE_LS_OUT_PATCH_SIZE 0xFFE000FF
243 #define S_VS_STATE_LS_OUT_VERTEX_SIZE(x) (((unsigned)(x) & 0xFF) << 24)
244 #define C_VS_STATE_LS_OUT_VERTEX_SIZE 0x00FFFFFF
245
246 /* SI-specific system values. */
247 enum {
248 TGSI_SEMANTIC_DEFAULT_TESSOUTER_SI = TGSI_SEMANTIC_COUNT,
249 TGSI_SEMANTIC_DEFAULT_TESSINNER_SI,
250 };
251
252 /* For VS shader key fix_fetch. */
253 enum {
254 SI_FIX_FETCH_NONE = 0,
255 SI_FIX_FETCH_A2_SNORM,
256 SI_FIX_FETCH_A2_SSCALED,
257 SI_FIX_FETCH_A2_SINT,
258 SI_FIX_FETCH_RGBA_32_UNORM,
259 SI_FIX_FETCH_RGBX_32_UNORM,
260 SI_FIX_FETCH_RGBA_32_SNORM,
261 SI_FIX_FETCH_RGBX_32_SNORM,
262 SI_FIX_FETCH_RGBA_32_USCALED,
263 SI_FIX_FETCH_RGBA_32_SSCALED,
264 SI_FIX_FETCH_RGBA_32_FIXED,
265 SI_FIX_FETCH_RGBX_32_FIXED,
266 SI_FIX_FETCH_RG_64_FLOAT,
267 SI_FIX_FETCH_RGB_64_FLOAT,
268 SI_FIX_FETCH_RGBA_64_FLOAT,
269 SI_FIX_FETCH_RGB_8, /* A = 1.0 */
270 SI_FIX_FETCH_RGB_8_INT, /* A = 1 */
271 SI_FIX_FETCH_RGB_16,
272 SI_FIX_FETCH_RGB_16_INT,
273 };
274
275 struct si_shader;
276
277 /* State of the context creating the shader object. */
278 struct si_compiler_ctx_state {
279 /* Should only be used by si_init_shader_selector_async and
280 * si_build_shader_variant if thread_index == -1 (non-threaded). */
281 LLVMTargetMachineRef tm;
282
283 /* Used if thread_index == -1 or if debug.async is true. */
284 struct pipe_debug_callback debug;
285
286 /* Used for creating the log string for gallium/ddebug. */
287 bool is_debug_context;
288 };
289
290 /* A shader selector is a gallium CSO and contains shader variants and
291 * binaries for one TGSI program. This can be shared by multiple contexts.
292 */
293 struct si_shader_selector {
294 struct si_screen *screen;
295 struct util_queue_fence ready;
296 struct si_compiler_ctx_state compiler_ctx_state;
297
298 mtx_t mutex;
299 struct si_shader *first_variant; /* immutable after the first variant */
300 struct si_shader *last_variant; /* mutable */
301
302 /* The compiled TGSI shader expecting a prolog and/or epilog (not
303 * uploaded to a buffer).
304 */
305 struct si_shader *main_shader_part;
306 struct si_shader *main_shader_part_ls; /* as_ls is set in the key */
307 struct si_shader *main_shader_part_es; /* as_es is set in the key */
308
309 struct si_shader *gs_copy_shader;
310
311 struct tgsi_token *tokens;
312 struct pipe_stream_output_info so;
313 struct tgsi_shader_info info;
314
315 /* PIPE_SHADER_[VERTEX|FRAGMENT|...] */
316 unsigned type;
317 bool vs_needs_prolog;
318
319 /* GS parameters. */
320 unsigned esgs_itemsize;
321 unsigned gs_input_verts_per_prim;
322 unsigned gs_output_prim;
323 unsigned gs_max_out_vertices;
324 unsigned gs_num_invocations;
325 unsigned max_gs_stream; /* count - 1 */
326 unsigned gsvs_vertex_size;
327 unsigned max_gsvs_emit_size;
328
329 /* PS parameters. */
330 unsigned color_attr_index[2];
331 unsigned db_shader_control;
332 /* Set 0xf or 0x0 (4 bits) per each written output.
333 * ANDed with spi_shader_col_format.
334 */
335 unsigned colors_written_4bit;
336
337 /* CS parameters */
338 unsigned local_size;
339
340 uint64_t outputs_written; /* "get_unique_index" bits */
341 uint32_t patch_outputs_written; /* "get_unique_index" bits */
342 uint32_t outputs_written2; /* "get_unique_index2" bits */
343
344 uint64_t inputs_read; /* "get_unique_index" bits */
345 uint32_t inputs_read2; /* "get_unique_index2" bits */
346 };
347
348 /* Valid shader configurations:
349 *
350 * API shaders VS | TCS | TES | GS |pass| PS
351 * are compiled as: | | | |thru|
352 * | | | | |
353 * Only VS & PS: VS | | | | | PS
354 * GFX6 - with GS: ES | | | GS | VS | PS
355 * - with tess: LS | HS | VS | | | PS
356 * - with both: LS | HS | ES | GS | VS | PS
357 * GFX9 - with GS: -> | | | GS | VS | PS
358 * - with tess: -> | HS | VS | | | PS
359 * - with both: -> | HS | -> | GS | VS | PS
360 *
361 * -> = merged with the next stage
362 */
363
364 /* Common VS bits between the shader key and the prolog key. */
365 struct si_vs_prolog_bits {
366 unsigned instance_divisors[SI_MAX_ATTRIBS];
367 };
368
369 /* Common VS bits between the shader key and the epilog key. */
370 struct si_vs_epilog_bits {
371 unsigned export_prim_id:1; /* when PS needs it and GS is disabled */
372 };
373
374 /* Common TCS bits between the shader key and the epilog key. */
375 struct si_tcs_epilog_bits {
376 unsigned prim_mode:3;
377 unsigned tes_reads_tess_factors:1;
378 };
379
380 struct si_gs_prolog_bits {
381 unsigned tri_strip_adj_fix:1;
382 };
383
384 /* Common PS bits between the shader key and the prolog key. */
385 struct si_ps_prolog_bits {
386 unsigned color_two_side:1;
387 unsigned flatshade_colors:1;
388 unsigned poly_stipple:1;
389 unsigned force_persp_sample_interp:1;
390 unsigned force_linear_sample_interp:1;
391 unsigned force_persp_center_interp:1;
392 unsigned force_linear_center_interp:1;
393 unsigned bc_optimize_for_persp:1;
394 unsigned bc_optimize_for_linear:1;
395 };
396
397 /* Common PS bits between the shader key and the epilog key. */
398 struct si_ps_epilog_bits {
399 unsigned spi_shader_col_format;
400 unsigned color_is_int8:8;
401 unsigned color_is_int10:8;
402 unsigned last_cbuf:3;
403 unsigned alpha_func:3;
404 unsigned alpha_to_one:1;
405 unsigned poly_line_smoothing:1;
406 unsigned clamp_color:1;
407 };
408
409 union si_shader_part_key {
410 struct {
411 struct si_vs_prolog_bits states;
412 unsigned num_input_sgprs:6;
413 unsigned last_input:4;
414 } vs_prolog;
415 struct {
416 struct si_vs_epilog_bits states;
417 unsigned prim_id_param_offset:5;
418 } vs_epilog;
419 struct {
420 struct si_tcs_epilog_bits states;
421 } tcs_epilog;
422 struct {
423 struct si_gs_prolog_bits states;
424 } gs_prolog;
425 struct {
426 struct si_ps_prolog_bits states;
427 unsigned num_input_sgprs:6;
428 unsigned num_input_vgprs:5;
429 /* Color interpolation and two-side color selection. */
430 unsigned colors_read:8; /* color input components read */
431 unsigned num_interp_inputs:5; /* BCOLOR is at this location */
432 unsigned face_vgpr_index:5;
433 unsigned wqm:1;
434 char color_attr_index[2];
435 char color_interp_vgpr_index[2]; /* -1 == constant */
436 } ps_prolog;
437 struct {
438 struct si_ps_epilog_bits states;
439 unsigned colors_written:8;
440 unsigned writes_z:1;
441 unsigned writes_stencil:1;
442 unsigned writes_samplemask:1;
443 } ps_epilog;
444 };
445
446 struct si_shader_key {
447 /* Prolog and epilog flags. */
448 union {
449 struct {
450 struct si_vs_prolog_bits prolog;
451 struct si_vs_epilog_bits epilog;
452 } vs;
453 struct {
454 struct si_vs_prolog_bits ls_prolog; /* for merged LS-HS */
455 struct si_shader_selector *ls; /* for merged LS-HS */
456 struct si_tcs_epilog_bits epilog;
457 } tcs; /* tessellation control shader */
458 struct {
459 struct si_vs_epilog_bits epilog; /* same as VS */
460 } tes; /* tessellation evaluation shader */
461 struct {
462 struct si_gs_prolog_bits prolog;
463 } gs;
464 struct {
465 struct si_ps_prolog_bits prolog;
466 struct si_ps_epilog_bits epilog;
467 } ps;
468 } part;
469
470 /* These two are initially set according to the NEXT_SHADER property,
471 * or guessed if the property doesn't seem correct.
472 */
473 unsigned as_es:1; /* export shader, which precedes GS */
474 unsigned as_ls:1; /* local shader, which precedes TCS */
475
476 /* Flags for monolithic compilation only. */
477 struct {
478 /* One byte for every input: SI_FIX_FETCH_* enums. */
479 uint8_t vs_fix_fetch[SI_MAX_ATTRIBS];
480 uint64_t ff_tcs_inputs_to_copy; /* for fixed-func TCS */
481 } mono;
482
483 /* Optimization flags for asynchronous compilation only. */
484 union {
485 struct {
486 uint64_t kill_outputs; /* "get_unique_index" bits */
487 uint32_t kill_outputs2; /* "get_unique_index2" bits */
488 unsigned clip_disable:1;
489 } hw_vs; /* HW VS (it can be VS, TES, GS) */
490 } opt;
491 };
492
493 struct si_shader_config {
494 unsigned num_sgprs;
495 unsigned num_vgprs;
496 unsigned spilled_sgprs;
497 unsigned spilled_vgprs;
498 unsigned private_mem_vgprs;
499 unsigned lds_size;
500 unsigned spi_ps_input_ena;
501 unsigned spi_ps_input_addr;
502 unsigned float_mode;
503 unsigned scratch_bytes_per_wave;
504 unsigned rsrc1;
505 unsigned rsrc2;
506 };
507
508 /* GCN-specific shader info. */
509 struct si_shader_info {
510 ubyte vs_output_param_offset[SI_MAX_VS_OUTPUTS];
511 ubyte num_input_sgprs;
512 ubyte num_input_vgprs;
513 char face_vgpr_index;
514 bool uses_instanceid;
515 ubyte nr_pos_exports;
516 ubyte nr_param_exports;
517 };
518
519 struct si_shader {
520 struct si_compiler_ctx_state compiler_ctx_state;
521
522 struct si_shader_selector *selector;
523 struct si_shader *next_variant;
524
525 struct si_shader_part *prolog;
526 struct si_shader *previous_stage; /* for GFX9 */
527 struct si_shader_part *epilog;
528
529 struct si_pm4_state *pm4;
530 struct r600_resource *bo;
531 struct r600_resource *scratch_bo;
532 struct si_shader_key key;
533 struct util_queue_fence optimized_ready;
534 bool compilation_failed;
535 bool is_monolithic;
536 bool is_optimized;
537 bool is_binary_shared;
538 bool is_gs_copy_shader;
539
540 /* The following data is all that's needed for binary shaders. */
541 struct ac_shader_binary binary;
542 struct si_shader_config config;
543 struct si_shader_info info;
544
545 /* Shader key + LLVM IR + disassembly + statistics.
546 * Generated for debug contexts only.
547 */
548 char *shader_log;
549 size_t shader_log_size;
550 };
551
552 struct si_shader_part {
553 struct si_shader_part *next;
554 union si_shader_part_key key;
555 struct ac_shader_binary binary;
556 struct si_shader_config config;
557 };
558
559 /* si_shader.c */
560 struct si_shader *
561 si_generate_gs_copy_shader(struct si_screen *sscreen,
562 LLVMTargetMachineRef tm,
563 struct si_shader_selector *gs_selector,
564 struct pipe_debug_callback *debug);
565 int si_compile_tgsi_shader(struct si_screen *sscreen,
566 LLVMTargetMachineRef tm,
567 struct si_shader *shader,
568 bool is_monolithic,
569 struct pipe_debug_callback *debug);
570 int si_shader_create(struct si_screen *sscreen, LLVMTargetMachineRef tm,
571 struct si_shader *shader,
572 struct pipe_debug_callback *debug);
573 int si_compile_llvm(struct si_screen *sscreen,
574 struct ac_shader_binary *binary,
575 struct si_shader_config *conf,
576 LLVMTargetMachineRef tm,
577 LLVMModuleRef mod,
578 struct pipe_debug_callback *debug,
579 unsigned processor,
580 const char *name);
581 void si_shader_destroy(struct si_shader *shader);
582 unsigned si_shader_io_get_unique_index(unsigned semantic_name, unsigned index);
583 unsigned si_shader_io_get_unique_index2(unsigned name, unsigned index);
584 int si_shader_binary_upload(struct si_screen *sscreen, struct si_shader *shader);
585 void si_shader_dump(struct si_screen *sscreen, struct si_shader *shader,
586 struct pipe_debug_callback *debug, unsigned processor,
587 FILE *f, bool check_debug_option);
588 void si_multiwave_lds_size_workaround(struct si_screen *sscreen,
589 unsigned *lds_size);
590 void si_shader_apply_scratch_relocs(struct si_context *sctx,
591 struct si_shader *shader,
592 struct si_shader_config *config,
593 uint64_t scratch_va);
594 void si_shader_binary_read_config(struct ac_shader_binary *binary,
595 struct si_shader_config *conf,
596 unsigned symbol_offset);
597 unsigned si_get_spi_shader_z_format(bool writes_z, bool writes_stencil,
598 bool writes_samplemask);
599 const char *si_get_shader_name(struct si_shader *shader, unsigned processor);
600
601 /* Inline helpers. */
602
603 /* Return the pointer to the main shader part's pointer. */
604 static inline struct si_shader **
605 si_get_main_shader_part(struct si_shader_selector *sel,
606 struct si_shader_key *key)
607 {
608 if (key->as_ls)
609 return &sel->main_shader_part_ls;
610 if (key->as_es)
611 return &sel->main_shader_part_es;
612 return &sel->main_shader_part;
613 }
614
615 #endif