src/gallium/drivers/radeonsi/si_shader.h

   1 /*
   2  * Copyright 2012 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Tom Stellard <thomas.stellard@amd.com>
  25  *      Michel Dänzer <michel.daenzer@amd.com>
  26  *      Christian König <christian.koenig@amd.com>
  27  */
  28
  29 /* How linking shader inputs and outputs between vertex, tessellation, and
  30  * geometry shaders works.
  31  *
  32  * Inputs and outputs between shaders are stored in a buffer. This buffer
  33  * lives in LDS (typical case for tessellation), but it can also live
  34  * in memory (ESGS). Each input or output has a fixed location within a vertex.
  35  * The highest used input or output determines the stride between vertices.
  36  *
  37  * Since GS and tessellation are only possible in the OpenGL core profile,
  38  * only these semantics are valid for per-vertex data:
  39  *
  40  *   Name             Location
  41  *
  42  *   POSITION         0
  43  *   PSIZE            1
  44  *   CLIPDIST0..1     2..3
  45  *   CULLDIST0..1     (not implemented)
  46  *   GENERIC0..31     4..35
  47  *
  48  * For example, a shader only writing GENERIC0 has the output stride of 5.
  49  *
  50  * Only these semantics are valid for per-patch data:
  51  *
  52  *   Name             Location
  53  *
  54  *   TESSOUTER        0
  55  *   TESSINNER        1
  56  *   PATCH0..29       2..31
  57  *
  58  * That's how independent shaders agree on input and output locations.
  59  * The si_shader_io_get_unique_index function assigns the locations.
  60  *
  61  * For tessellation, other required information for calculating the input and
  62  * output addresses like the vertex stride, the patch stride, and the offsets
  63  * where per-vertex and per-patch data start, is passed to the shader via
  64  * user data SGPRs. The offsets and strides are calculated at draw time and
  65  * aren't available at compile time.
  66  */
  67
  68 #ifndef SI_SHADER_H
  69 #define SI_SHADER_H
  70
  71 #include <llvm-c/Core.h> /* LLVMModuleRef */
  72 #include <llvm-c/TargetMachine.h>
  73 #include "tgsi/tgsi_scan.h"
  74 #include "util/u_queue.h"
  75 #include "si_state.h"
  76
  77 struct ac_shader_binary;
  78
  79 #define SI_MAX_VS_OUTPUTS       40
  80
  81 /* SGPR user data indices */
  82 enum {
  83         SI_SGPR_RW_BUFFERS,  /* rings (& stream-out, VS only) */
  84         SI_SGPR_RW_BUFFERS_HI,
  85         SI_SGPR_CONST_BUFFERS,
  86         SI_SGPR_CONST_BUFFERS_HI,
  87         SI_SGPR_SAMPLERS,  /* images & sampler states interleaved */
  88         SI_SGPR_SAMPLERS_HI,
  89         SI_SGPR_IMAGES,
  90         SI_SGPR_IMAGES_HI,
  91         SI_SGPR_SHADER_BUFFERS,
  92         SI_SGPR_SHADER_BUFFERS_HI,
  93         SI_NUM_RESOURCE_SGPRS,
  94
  95         /* all VS variants */
  96         SI_SGPR_VERTEX_BUFFERS  = SI_NUM_RESOURCE_SGPRS,
  97         SI_SGPR_VERTEX_BUFFERS_HI,
  98         SI_SGPR_BASE_VERTEX,
  99         SI_SGPR_START_INSTANCE,
 100         SI_SGPR_DRAWID,
 101         SI_SGPR_VS_STATE_BITS,
 102         SI_VS_NUM_USER_SGPR,
 103
 104         /* both TCS and TES */
 105         SI_SGPR_TCS_OFFCHIP_LAYOUT = SI_NUM_RESOURCE_SGPRS,
 106         SI_TES_NUM_USER_SGPR,
 107
 108         /* TCS only */
 109         SI_SGPR_TCS_OUT_OFFSETS = SI_TES_NUM_USER_SGPR,
 110         SI_SGPR_TCS_OUT_LAYOUT,
 111         SI_SGPR_TCS_IN_LAYOUT,
 112         SI_TCS_NUM_USER_SGPR,
 113
 114         /* GS limits */
 115         SI_GS_NUM_USER_SGPR = SI_NUM_RESOURCE_SGPRS,
 116         SI_GSCOPY_NUM_USER_SGPR = SI_SGPR_RW_BUFFERS_HI + 1,
 117
 118         /* PS only */
 119         SI_SGPR_ALPHA_REF       = SI_NUM_RESOURCE_SGPRS,
 120         SI_PS_NUM_USER_SGPR,
 121
 122         /* CS only */
 123         SI_SGPR_GRID_SIZE = SI_NUM_RESOURCE_SGPRS,
 124         SI_SGPR_BLOCK_SIZE = SI_SGPR_GRID_SIZE + 3,
 125         SI_CS_NUM_USER_SGPR = SI_SGPR_BLOCK_SIZE + 3
 126 };
 127
 128 /* LLVM function parameter indices */
 129 enum {
 130         SI_PARAM_RW_BUFFERS,
 131         SI_PARAM_CONST_BUFFERS,
 132         SI_PARAM_SAMPLERS,
 133         SI_PARAM_IMAGES,
 134         SI_PARAM_SHADER_BUFFERS,
 135         SI_NUM_RESOURCE_PARAMS,
 136
 137         /* VS only parameters */
 138         SI_PARAM_VERTEX_BUFFERS = SI_NUM_RESOURCE_PARAMS,
 139         SI_PARAM_BASE_VERTEX,
 140         SI_PARAM_START_INSTANCE,
 141         SI_PARAM_DRAWID,
 142         SI_PARAM_VS_STATE_BITS,
 143
 144         /* Layout of TCS outputs in the offchip buffer
 145          *   [0:8] = the number of patches per threadgroup.
 146          *   [9:15] = the number of output vertices per patch.
 147          *   [16:31] = the offset of per patch attributes in the buffer in bytes.
 148          */
 149         SI_PARAM_TCS_OFFCHIP_LAYOUT = SI_NUM_RESOURCE_PARAMS, /* for TCS & TES */
 150
 151         /* TCS only parameters. */
 152
 153         /* Offsets where TCS outputs and TCS patch outputs live in LDS:
 154          *   [0:15] = TCS output patch0 offset / 16, max = NUM_PATCHES * 32 * 32
 155          *   [16:31] = TCS output patch0 offset for per-patch / 16, max = NUM_PATCHES*32*32* + 32*32
 156          */
 157         SI_PARAM_TCS_OUT_OFFSETS,
 158
 159         /* Layout of TCS outputs / TES inputs:
 160          *   [0:12] = stride between output patches in dwords, num_outputs * num_vertices * 4, max = 32*32*4
 161          *   [13:20] = stride between output vertices in dwords = num_inputs * 4, max = 32*4
 162          *   [26:31] = gl_PatchVerticesIn, max = 32
 163          */
 164         SI_PARAM_TCS_OUT_LAYOUT,
 165
 166         /* Layout of LS outputs / TCS inputs
 167          *   [8:20] = stride between patches in dwords = num_inputs * num_vertices * 4, max = 32*32*4
 168          *   [24:31] = stride between vertices in dwords = num_inputs * 4, max = 32*4
 169          * (same layout as SI_PARAM_VS_STATE_BITS)
 170          */
 171         SI_PARAM_TCS_IN_LAYOUT,
 172
 173         SI_PARAM_TCS_OC_LDS,
 174         SI_PARAM_TESS_FACTOR_OFFSET,
 175         SI_PARAM_PATCH_ID,
 176         SI_PARAM_REL_IDS,
 177
 178         /* GS only parameters */
 179         SI_PARAM_GS2VS_OFFSET = SI_NUM_RESOURCE_PARAMS,
 180         SI_PARAM_GS_WAVE_ID,
 181         SI_PARAM_VTX0_OFFSET,
 182         SI_PARAM_VTX1_OFFSET,
 183         SI_PARAM_PRIMITIVE_ID,
 184         SI_PARAM_VTX2_OFFSET,
 185         SI_PARAM_VTX3_OFFSET,
 186         SI_PARAM_VTX4_OFFSET,
 187         SI_PARAM_VTX5_OFFSET,
 188         SI_PARAM_GS_INSTANCE_ID,
 189
 190         /* PS only parameters */
 191         SI_PARAM_ALPHA_REF = SI_NUM_RESOURCE_PARAMS,
 192         SI_PARAM_PRIM_MASK,
 193         SI_PARAM_PERSP_SAMPLE,
 194         SI_PARAM_PERSP_CENTER,
 195         SI_PARAM_PERSP_CENTROID,
 196         SI_PARAM_PERSP_PULL_MODEL,
 197         SI_PARAM_LINEAR_SAMPLE,
 198         SI_PARAM_LINEAR_CENTER,
 199         SI_PARAM_LINEAR_CENTROID,
 200         SI_PARAM_LINE_STIPPLE_TEX,
 201         SI_PARAM_POS_X_FLOAT,
 202         SI_PARAM_POS_Y_FLOAT,
 203         SI_PARAM_POS_Z_FLOAT,
 204         SI_PARAM_POS_W_FLOAT,
 205         SI_PARAM_FRONT_FACE,
 206         SI_PARAM_ANCILLARY,
 207         SI_PARAM_SAMPLE_COVERAGE,
 208         SI_PARAM_POS_FIXED_PT,
 209
 210         /* CS only parameters */
 211         SI_PARAM_GRID_SIZE = SI_NUM_RESOURCE_PARAMS,
 212         SI_PARAM_BLOCK_SIZE,
 213         SI_PARAM_BLOCK_ID,
 214         SI_PARAM_THREAD_ID,
 215
 216         SI_NUM_PARAMS = SI_PARAM_POS_FIXED_PT + 9, /* +8 for COLOR[0..1] */
 217 };
 218
 219 /* Fields of driver-defined VS state SGPR. */
 220 /* Clamp vertex color output (only used in VS as VS). */
 221 #define S_VS_STATE_CLAMP_VERTEX_COLOR(x)        (((unsigned)(x) & 0x1) << 0)
 222 #define C_VS_STATE_CLAMP_VERTEX_COLOR           0xFFFFFFFE
 223 #define S_VS_STATE_INDEXED(x)                   (((unsigned)(x) & 0x1) << 1)
 224 #define C_VS_STATE_INDEXED                      0xFFFFFFFD
 225 #define S_VS_STATE_LS_OUT_PATCH_SIZE(x)         (((unsigned)(x) & 0x1FFF) << 8)
 226 #define C_VS_STATE_LS_OUT_PATCH_SIZE            0xFFE000FF
 227 #define S_VS_STATE_LS_OUT_VERTEX_SIZE(x)        (((unsigned)(x) & 0xFF) << 24)
 228 #define C_VS_STATE_LS_OUT_VERTEX_SIZE           0x00FFFFFF
 229
 230 /* SI-specific system values. */
 231 enum {
 232         TGSI_SEMANTIC_DEFAULT_TESSOUTER_SI = TGSI_SEMANTIC_COUNT,
 233         TGSI_SEMANTIC_DEFAULT_TESSINNER_SI,
 234 };
 235
 236 /* For VS shader key fix_fetch. */
 237 enum {
 238         SI_FIX_FETCH_NONE = 0,
 239         SI_FIX_FETCH_A2_SNORM,
 240         SI_FIX_FETCH_A2_SSCALED,
 241         SI_FIX_FETCH_A2_SINT,
 242         SI_FIX_FETCH_RGBA_32_UNORM,
 243         SI_FIX_FETCH_RGBX_32_UNORM,
 244         SI_FIX_FETCH_RGBA_32_SNORM,
 245         SI_FIX_FETCH_RGBX_32_SNORM,
 246         SI_FIX_FETCH_RGBA_32_USCALED,
 247         SI_FIX_FETCH_RGBA_32_SSCALED,
 248         SI_FIX_FETCH_RGBA_32_FIXED,
 249         SI_FIX_FETCH_RGBX_32_FIXED,
 250         SI_FIX_FETCH_RG_64_FLOAT,
 251         SI_FIX_FETCH_RGB_64_FLOAT,
 252         SI_FIX_FETCH_RGBA_64_FLOAT,
 253         SI_FIX_FETCH_RGB_8,     /* A = 1.0 */
 254         SI_FIX_FETCH_RGB_8_INT, /* A = 1 */
 255         SI_FIX_FETCH_RGB_16,
 256         SI_FIX_FETCH_RGB_16_INT,
 257 };
 258
 259 struct si_shader;
 260
 261 /* State of the context creating the shader object. */
 262 struct si_compiler_ctx_state {
 263         /* Should only be used by si_init_shader_selector_async and
 264          * si_build_shader_variant if thread_index == -1 (non-threaded). */
 265         LLVMTargetMachineRef            tm;
 266
 267         /* Used if thread_index == -1 or if debug.async is true. */
 268         struct pipe_debug_callback      debug;
 269
 270         /* Used for creating the log string for gallium/ddebug. */
 271         bool                            is_debug_context;
 272 };
 273
 274 /* A shader selector is a gallium CSO and contains shader variants and
 275  * binaries for one TGSI program. This can be shared by multiple contexts.
 276  */
 277 struct si_shader_selector {
 278         struct si_screen        *screen;
 279         struct util_queue_fence ready;
 280         struct si_compiler_ctx_state compiler_ctx_state;
 281
 282         mtx_t           mutex;
 283         struct si_shader        *first_variant; /* immutable after the first variant */
 284         struct si_shader        *last_variant; /* mutable */
 285
 286         /* The compiled TGSI shader expecting a prolog and/or epilog (not
 287          * uploaded to a buffer).
 288          */
 289         struct si_shader        *main_shader_part;
 290         struct si_shader        *main_shader_part_ls; /* as_ls is set in the key */
 291         struct si_shader        *main_shader_part_es; /* as_es is set in the key */
 292
 293         struct si_shader        *gs_copy_shader;
 294
 295         struct tgsi_token       *tokens;
 296         struct pipe_stream_output_info  so;
 297         struct tgsi_shader_info         info;
 298
 299         /* PIPE_SHADER_[VERTEX|FRAGMENT|...] */
 300         unsigned        type;
 301
 302         /* GS parameters. */
 303         unsigned        esgs_itemsize;
 304         unsigned        gs_input_verts_per_prim;
 305         unsigned        gs_output_prim;
 306         unsigned        gs_max_out_vertices;
 307         unsigned        gs_num_invocations;
 308         unsigned        max_gs_stream; /* count - 1 */
 309         unsigned        gsvs_vertex_size;
 310         unsigned        max_gsvs_emit_size;
 311
 312         /* PS parameters. */
 313         unsigned        color_attr_index[2];
 314         unsigned        db_shader_control;
 315         /* Set 0xf or 0x0 (4 bits) per each written output.
 316          * ANDed with spi_shader_col_format.
 317          */
 318         unsigned        colors_written_4bit;
 319
 320         /* CS parameters */
 321         unsigned local_size;
 322
 323         uint64_t        outputs_written;        /* "get_unique_index" bits */
 324         uint32_t        patch_outputs_written;  /* "get_unique_index" bits */
 325         uint32_t        outputs_written2;       /* "get_unique_index2" bits */
 326
 327         uint64_t        inputs_read;            /* "get_unique_index" bits */
 328         uint32_t        inputs_read2;           /* "get_unique_index2" bits */
 329 };
 330
 331 /* Valid shader configurations:
 332  *
 333  * API shaders       VS | TCS | TES | GS |pass| PS
 334  * are compiled as:     |     |     |    |thru|
 335  *                      |     |     |    |    |
 336  * Only VS & PS:     VS | --  | --  | -- | -- | PS
 337  * With GS:          ES | --  | --  | GS | VS | PS
 338  * With Tessel.:     LS | HS  | VS  | -- | -- | PS
 339  * With both:        LS | HS  | ES  | GS | VS | PS
 340  */
 341
 342 /* Common VS bits between the shader key and the prolog key. */
 343 struct si_vs_prolog_bits {
 344         unsigned        instance_divisors[SI_MAX_ATTRIBS];
 345 };
 346
 347 /* Common VS bits between the shader key and the epilog key. */
 348 struct si_vs_epilog_bits {
 349         unsigned        export_prim_id:1; /* when PS needs it and GS is disabled */
 350 };
 351
 352 /* Common TCS bits between the shader key and the epilog key. */
 353 struct si_tcs_epilog_bits {
 354         unsigned        prim_mode:3;
 355         unsigned        tes_reads_tess_factors:1;
 356 };
 357
 358 struct si_gs_prolog_bits {
 359         unsigned        tri_strip_adj_fix:1;
 360 };
 361
 362 /* Common PS bits between the shader key and the prolog key. */
 363 struct si_ps_prolog_bits {
 364         unsigned        color_two_side:1;
 365         unsigned        flatshade_colors:1;
 366         unsigned        poly_stipple:1;
 367         unsigned        force_persp_sample_interp:1;
 368         unsigned        force_linear_sample_interp:1;
 369         unsigned        force_persp_center_interp:1;
 370         unsigned        force_linear_center_interp:1;
 371         unsigned        bc_optimize_for_persp:1;
 372         unsigned        bc_optimize_for_linear:1;
 373 };
 374
 375 /* Common PS bits between the shader key and the epilog key. */
 376 struct si_ps_epilog_bits {
 377         unsigned        spi_shader_col_format;
 378         unsigned        color_is_int8:8;
 379         unsigned        color_is_int10:8;
 380         unsigned        last_cbuf:3;
 381         unsigned        alpha_func:3;
 382         unsigned        alpha_to_one:1;
 383         unsigned        poly_line_smoothing:1;
 384         unsigned        clamp_color:1;
 385 };
 386
 387 union si_shader_part_key {
 388         struct {
 389                 struct si_vs_prolog_bits states;
 390                 unsigned        num_input_sgprs:5;
 391                 unsigned        last_input:4;
 392         } vs_prolog;
 393         struct {
 394                 struct si_vs_epilog_bits states;
 395                 unsigned        prim_id_param_offset:5;
 396         } vs_epilog;
 397         struct {
 398                 struct si_tcs_epilog_bits states;
 399         } tcs_epilog;
 400         struct {
 401                 struct si_gs_prolog_bits states;
 402         } gs_prolog;
 403         struct {
 404                 struct si_ps_prolog_bits states;
 405                 unsigned        num_input_sgprs:5;
 406                 unsigned        num_input_vgprs:5;
 407                 /* Color interpolation and two-side color selection. */
 408                 unsigned        colors_read:8; /* color input components read */
 409                 unsigned        num_interp_inputs:5; /* BCOLOR is at this location */
 410                 unsigned        face_vgpr_index:5;
 411                 unsigned        wqm:1;
 412                 char            color_attr_index[2];
 413                 char            color_interp_vgpr_index[2]; /* -1 == constant */
 414         } ps_prolog;
 415         struct {
 416                 struct si_ps_epilog_bits states;
 417                 unsigned        colors_written:8;
 418                 unsigned        writes_z:1;
 419                 unsigned        writes_stencil:1;
 420                 unsigned        writes_samplemask:1;
 421         } ps_epilog;
 422 };
 423
 424 struct si_shader_key {
 425         /* Prolog and epilog flags. */
 426         union {
 427                 struct {
 428                         struct si_vs_prolog_bits prolog;
 429                         struct si_vs_epilog_bits epilog;
 430                 } vs;
 431                 struct {
 432                         struct si_tcs_epilog_bits epilog;
 433                 } tcs; /* tessellation control shader */
 434                 struct {
 435                         struct si_vs_epilog_bits epilog; /* same as VS */
 436                 } tes; /* tessellation evaluation shader */
 437                 struct {
 438                         struct si_gs_prolog_bits prolog;
 439                 } gs;
 440                 struct {
 441                         struct si_ps_prolog_bits prolog;
 442                         struct si_ps_epilog_bits epilog;
 443                 } ps;
 444         } part;
 445
 446         /* These two are initially set according to the NEXT_SHADER property,
 447          * or guessed if the property doesn't seem correct.
 448          */
 449         unsigned as_es:1; /* export shader, which precedes GS */
 450         unsigned as_ls:1; /* local shader, which precedes TCS */
 451
 452         /* Flags for monolithic compilation only. */
 453         union {
 454                 struct {
 455                         /* One byte for every input: SI_FIX_FETCH_* enums. */
 456                         uint8_t         fix_fetch[SI_MAX_ATTRIBS];
 457                 } vs;
 458                 struct {
 459                         uint64_t        inputs_to_copy; /* for fixed-func TCS */
 460                 } tcs;
 461         } mono;
 462
 463         /* Optimization flags for asynchronous compilation only. */
 464         union {
 465                 struct {
 466                         uint64_t        kill_outputs; /* "get_unique_index" bits */
 467                         uint32_t        kill_outputs2; /* "get_unique_index2" bits */
 468                         unsigned        clip_disable:1;
 469                 } hw_vs; /* HW VS (it can be VS, TES, GS) */
 470         } opt;
 471 };
 472
 473 struct si_shader_config {
 474         unsigned                        num_sgprs;
 475         unsigned                        num_vgprs;
 476         unsigned                        spilled_sgprs;
 477         unsigned                        spilled_vgprs;
 478         unsigned                        private_mem_vgprs;
 479         unsigned                        lds_size;
 480         unsigned                        spi_ps_input_ena;
 481         unsigned                        spi_ps_input_addr;
 482         unsigned                        float_mode;
 483         unsigned                        scratch_bytes_per_wave;
 484         unsigned                        rsrc1;
 485         unsigned                        rsrc2;
 486 };
 487
 488 enum {
 489         /* SPI_PS_INPUT_CNTL_i.OFFSET[0:4] */
 490         EXP_PARAM_OFFSET_0 = 0,
 491         EXP_PARAM_OFFSET_31 = 31,
 492         /* SPI_PS_INPUT_CNTL_i.DEFAULT_VAL[0:1] */
 493         EXP_PARAM_DEFAULT_VAL_0000 = 64,
 494         EXP_PARAM_DEFAULT_VAL_0001,
 495         EXP_PARAM_DEFAULT_VAL_1110,
 496         EXP_PARAM_DEFAULT_VAL_1111,
 497         EXP_PARAM_UNDEFINED = 255,
 498 };
 499
 500 /* GCN-specific shader info. */
 501 struct si_shader_info {
 502         ubyte                   vs_output_param_offset[SI_MAX_VS_OUTPUTS];
 503         ubyte                   num_input_sgprs;
 504         ubyte                   num_input_vgprs;
 505         char                    face_vgpr_index;
 506         bool                    uses_instanceid;
 507         ubyte                   nr_pos_exports;
 508         ubyte                   nr_param_exports;
 509 };
 510
 511 struct si_shader {
 512         struct si_compiler_ctx_state    compiler_ctx_state;
 513
 514         struct si_shader_selector       *selector;
 515         struct si_shader                *next_variant;
 516
 517         struct si_shader_part           *prolog;
 518         struct si_shader_part           *epilog;
 519
 520         struct si_pm4_state             *pm4;
 521         struct r600_resource            *bo;
 522         struct r600_resource            *scratch_bo;
 523         struct si_shader_key            key;
 524         struct util_queue_fence         optimized_ready;
 525         bool                            compilation_failed;
 526         bool                            is_monolithic;
 527         bool                            is_optimized;
 528         bool                            is_binary_shared;
 529         bool                            is_gs_copy_shader;
 530
 531         /* The following data is all that's needed for binary shaders. */
 532         struct ac_shader_binary binary;
 533         struct si_shader_config         config;
 534         struct si_shader_info           info;
 535
 536         /* Shader key + LLVM IR + disassembly + statistics.
 537          * Generated for debug contexts only.
 538          */
 539         char                            *shader_log;
 540         size_t                          shader_log_size;
 541 };
 542
 543 struct si_shader_part {
 544         struct si_shader_part *next;
 545         union si_shader_part_key key;
 546         struct ac_shader_binary binary;
 547         struct si_shader_config config;
 548 };
 549
 550 /* si_shader.c */
 551 struct si_shader *
 552 si_generate_gs_copy_shader(struct si_screen *sscreen,
 553                            LLVMTargetMachineRef tm,
 554                            struct si_shader_selector *gs_selector,
 555                            struct pipe_debug_callback *debug);
 556 int si_compile_tgsi_shader(struct si_screen *sscreen,
 557                            LLVMTargetMachineRef tm,
 558                            struct si_shader *shader,
 559                            bool is_monolithic,
 560                            struct pipe_debug_callback *debug);
 561 int si_shader_create(struct si_screen *sscreen, LLVMTargetMachineRef tm,
 562                      struct si_shader *shader,
 563                      struct pipe_debug_callback *debug);
 564 int si_compile_llvm(struct si_screen *sscreen,
 565                     struct ac_shader_binary *binary,
 566                     struct si_shader_config *conf,
 567                     LLVMTargetMachineRef tm,
 568                     LLVMModuleRef mod,
 569                     struct pipe_debug_callback *debug,
 570                     unsigned processor,
 571                     const char *name);
 572 void si_shader_destroy(struct si_shader *shader);
 573 unsigned si_shader_io_get_unique_index(unsigned semantic_name, unsigned index);
 574 unsigned si_shader_io_get_unique_index2(unsigned name, unsigned index);
 575 int si_shader_binary_upload(struct si_screen *sscreen, struct si_shader *shader);
 576 void si_shader_dump(struct si_screen *sscreen, struct si_shader *shader,
 577                     struct pipe_debug_callback *debug, unsigned processor,
 578                     FILE *f, bool check_debug_option);
 579 void si_multiwave_lds_size_workaround(struct si_screen *sscreen,
 580                                       unsigned *lds_size);
 581 void si_shader_apply_scratch_relocs(struct si_context *sctx,
 582                         struct si_shader *shader,
 583                         struct si_shader_config *config,
 584                         uint64_t scratch_va);
 585 void si_shader_binary_read_config(struct ac_shader_binary *binary,
 586                                   struct si_shader_config *conf,
 587                                   unsigned symbol_offset);
 588 unsigned si_get_spi_shader_z_format(bool writes_z, bool writes_stencil,
 589                                     bool writes_samplemask);
 590 const char *si_get_shader_name(struct si_shader *shader, unsigned processor);
 591
 592 /* Inline helpers. */
 593
 594 /* Return the pointer to the main shader part's pointer. */
 595 static inline struct si_shader **
 596 si_get_main_shader_part(struct si_shader_selector *sel,
 597                         struct si_shader_key *key)
 598 {
 599         if (key->as_ls)
 600                 return &sel->main_shader_part_ls;
 601         if (key->as_es)
 602                 return &sel->main_shader_part_es;
 603         return &sel->main_shader_part;
 604 }
 605
 606 #endif