2 * Copyright 2012 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 * Tom Stellard <thomas.stellard@amd.com>
25 * Michel Dänzer <michel.daenzer@amd.com>
26 * Christian König <christian.koenig@amd.com>
29 /* How linking shader inputs and outputs between vertex, tessellation, and
30 * geometry shaders works.
32 * Inputs and outputs between shaders are stored in a buffer. This buffer
33 * lives in LDS (typical case for tessellation), but it can also live
34 * in memory (ESGS). Each input or output has a fixed location within a vertex.
35 * The highest used input or output determines the stride between vertices.
37 * Since GS and tessellation are only possible in the OpenGL core profile,
38 * only these semantics are valid for per-vertex data:
45 * CULLDIST0..1 (not implemented)
48 * For example, a shader only writing GENERIC0 has the output stride of 5.
50 * Only these semantics are valid for per-patch data:
58 * That's how independent shaders agree on input and output locations.
59 * The si_shader_io_get_unique_index function assigns the locations.
61 * For tessellation, other required information for calculating the input and
62 * output addresses like the vertex stride, the patch stride, and the offsets
63 * where per-vertex and per-patch data start, is passed to the shader via
64 * user data SGPRs. The offsets and strides are calculated at draw time and
65 * aren't available at compile time.
71 #include <llvm-c/Core.h> /* LLVMModuleRef */
72 #include "tgsi/tgsi_scan.h"
75 struct radeon_shader_binary
;
76 struct radeon_shader_reloc
;
78 #define SI_MAX_VS_OUTPUTS 40
80 /* SGPR user data indices */
82 SI_SGPR_RW_BUFFERS
, /* rings (& stream-out, VS only) */
83 SI_SGPR_RW_BUFFERS_HI
,
84 SI_SGPR_CONST_BUFFERS
,
85 SI_SGPR_CONST_BUFFERS_HI
,
86 SI_SGPR_SAMPLERS
, /* images & sampler states interleaved */
90 SI_SGPR_SHADER_BUFFERS
,
91 SI_SGPR_SHADER_BUFFERS_HI
,
92 SI_NUM_RESOURCE_SGPRS
,
95 SI_SGPR_VERTEX_BUFFERS
= SI_NUM_RESOURCE_SGPRS
,
96 SI_SGPR_VERTEX_BUFFERS_HI
,
98 SI_SGPR_START_INSTANCE
,
103 SI_SGPR_VS_STATE_BITS
= SI_ES_NUM_USER_SGPR
,
107 SI_SGPR_LS_OUT_LAYOUT
= SI_ES_NUM_USER_SGPR
,
110 /* both TCS and TES */
111 SI_SGPR_TCS_OFFCHIP_LAYOUT
= SI_NUM_RESOURCE_SGPRS
,
112 SI_TES_NUM_USER_SGPR
,
115 SI_SGPR_TCS_OUT_OFFSETS
= SI_TES_NUM_USER_SGPR
,
116 SI_SGPR_TCS_OUT_LAYOUT
,
117 SI_SGPR_TCS_IN_LAYOUT
,
118 SI_TCS_NUM_USER_SGPR
,
121 SI_GS_NUM_USER_SGPR
= SI_NUM_RESOURCE_SGPRS
,
122 SI_GSCOPY_NUM_USER_SGPR
= SI_SGPR_RW_BUFFERS_HI
+ 1,
125 SI_SGPR_ALPHA_REF
= SI_NUM_RESOURCE_SGPRS
,
129 SI_SGPR_GRID_SIZE
= SI_NUM_RESOURCE_SGPRS
,
130 SI_CS_NUM_USER_SGPR
= SI_SGPR_GRID_SIZE
+ 3
133 /* LLVM function parameter indices */
136 SI_PARAM_CONST_BUFFERS
,
139 SI_PARAM_SHADER_BUFFERS
,
140 SI_NUM_RESOURCE_PARAMS
,
142 /* VS only parameters */
143 SI_PARAM_VERTEX_BUFFERS
= SI_NUM_RESOURCE_PARAMS
,
144 SI_PARAM_BASE_VERTEX
,
145 SI_PARAM_START_INSTANCE
,
147 /* [0] = clamp vertex color, VS as VS only */
148 SI_PARAM_VS_STATE_BITS
,
149 /* same value as TCS_IN_LAYOUT, VS as LS only */
150 SI_PARAM_LS_OUT_LAYOUT
= SI_PARAM_DRAWID
+ 1,
151 /* the other VS parameters are assigned dynamically */
153 /* Layout of TCS outputs in the offchip buffer
154 * [0:8] = the number of patches per threadgroup.
155 * [9:15] = the number of output vertices per patch.
156 * [16:31] = the offset of per patch attributes in the buffer in bytes.
158 SI_PARAM_TCS_OFFCHIP_LAYOUT
= SI_NUM_RESOURCE_PARAMS
, /* for TCS & TES */
160 /* TCS only parameters. */
162 /* Offsets where TCS outputs and TCS patch outputs live in LDS:
163 * [0:15] = TCS output patch0 offset / 16, max = NUM_PATCHES * 32 * 32
164 * [16:31] = TCS output patch0 offset for per-patch / 16, max = NUM_PATCHES*32*32* + 32*32
166 SI_PARAM_TCS_OUT_OFFSETS
,
168 /* Layout of TCS outputs / TES inputs:
169 * [0:12] = stride between output patches in dwords, num_outputs * num_vertices * 4, max = 32*32*4
170 * [13:20] = stride between output vertices in dwords = num_inputs * 4, max = 32*4
171 * [26:31] = gl_PatchVerticesIn, max = 32
173 SI_PARAM_TCS_OUT_LAYOUT
,
175 /* Layout of LS outputs / TCS inputs
176 * [0:12] = stride between patches in dwords = num_inputs * num_vertices * 4, max = 32*32*4
177 * [13:20] = stride between vertices in dwords = num_inputs * 4, max = 32*4
179 SI_PARAM_TCS_IN_LAYOUT
,
182 SI_PARAM_TESS_FACTOR_OFFSET
,
186 /* GS only parameters */
187 SI_PARAM_GS2VS_OFFSET
= SI_NUM_RESOURCE_PARAMS
,
189 SI_PARAM_VTX0_OFFSET
,
190 SI_PARAM_VTX1_OFFSET
,
191 SI_PARAM_PRIMITIVE_ID
,
192 SI_PARAM_VTX2_OFFSET
,
193 SI_PARAM_VTX3_OFFSET
,
194 SI_PARAM_VTX4_OFFSET
,
195 SI_PARAM_VTX5_OFFSET
,
196 SI_PARAM_GS_INSTANCE_ID
,
198 /* PS only parameters */
199 SI_PARAM_ALPHA_REF
= SI_NUM_RESOURCE_PARAMS
,
201 SI_PARAM_PERSP_SAMPLE
,
202 SI_PARAM_PERSP_CENTER
,
203 SI_PARAM_PERSP_CENTROID
,
204 SI_PARAM_PERSP_PULL_MODEL
,
205 SI_PARAM_LINEAR_SAMPLE
,
206 SI_PARAM_LINEAR_CENTER
,
207 SI_PARAM_LINEAR_CENTROID
,
208 SI_PARAM_LINE_STIPPLE_TEX
,
209 SI_PARAM_POS_X_FLOAT
,
210 SI_PARAM_POS_Y_FLOAT
,
211 SI_PARAM_POS_Z_FLOAT
,
212 SI_PARAM_POS_W_FLOAT
,
215 SI_PARAM_SAMPLE_COVERAGE
,
216 SI_PARAM_POS_FIXED_PT
,
218 /* CS only parameters */
219 SI_PARAM_GRID_SIZE
= SI_NUM_RESOURCE_PARAMS
,
223 SI_NUM_PARAMS
= SI_PARAM_POS_FIXED_PT
+ 9, /* +8 for COLOR[0..1] */
226 /* SI-specific system values. */
228 TGSI_SEMANTIC_DEFAULT_TESSOUTER_SI
= TGSI_SEMANTIC_COUNT
,
229 TGSI_SEMANTIC_DEFAULT_TESSINNER_SI
,
234 /* A shader selector is a gallium CSO and contains shader variants and
235 * binaries for one TGSI program. This can be shared by multiple contexts.
237 struct si_shader_selector
{
238 struct si_screen
*screen
;
239 struct util_queue_fence ready
;
241 /* Should only be used by si_init_shader_selector_async
242 * if thread_index == -1 (non-threaded). */
243 LLVMTargetMachineRef tm
;
244 struct pipe_debug_callback debug
;
245 bool is_debug_context
;
248 struct si_shader
*first_variant
; /* immutable after the first variant */
249 struct si_shader
*last_variant
; /* mutable */
251 /* The compiled TGSI shader expecting a prolog and/or epilog (not
252 * uploaded to a buffer).
254 struct si_shader
*main_shader_part
;
256 struct tgsi_token
*tokens
;
257 struct pipe_stream_output_info so
;
258 struct tgsi_shader_info info
;
260 /* PIPE_SHADER_[VERTEX|FRAGMENT|...] */
264 unsigned esgs_itemsize
;
265 unsigned gs_input_verts_per_prim
;
266 unsigned gs_output_prim
;
267 unsigned gs_max_out_vertices
;
268 unsigned gs_num_invocations
;
269 unsigned max_gs_stream
; /* count - 1 */
270 unsigned gsvs_vertex_size
;
271 unsigned max_gsvs_emit_size
;
274 unsigned color_attr_index
[2];
275 unsigned db_shader_control
;
276 /* Set 0xf or 0x0 (4 bits) per each written output.
277 * ANDed with spi_shader_col_format.
279 unsigned colors_written_4bit
;
284 /* masks of "get_unique_index" bits */
285 uint64_t outputs_written
;
286 uint32_t patch_outputs_written
;
289 /* Valid shader configurations:
291 * API shaders VS | TCS | TES | GS |pass| PS
292 * are compiled as: | | | |thru|
294 * Only VS & PS: VS | -- | -- | -- | -- | PS
295 * With GS: ES | -- | -- | GS | VS | PS
296 * With Tessel.: LS | HS | VS | -- | -- | PS
297 * With both: LS | HS | ES | GS | VS | PS
300 /* Common VS bits between the shader key and the prolog key. */
301 struct si_vs_prolog_bits
{
302 unsigned instance_divisors
[SI_NUM_VERTEX_BUFFERS
];
305 /* Common VS bits between the shader key and the epilog key. */
306 struct si_vs_epilog_bits
{
307 unsigned export_prim_id
:1; /* when PS needs it and GS is disabled */
309 * - skip clipdist, culldist (including clipvertex code) exports based
310 * on which clip_plane_enable bits are set
311 * - skip layer, viewport, clipdist, and culldist parameter exports
312 * if PS doesn't read them
316 /* Common TCS bits between the shader key and the epilog key. */
317 struct si_tcs_epilog_bits
{
318 unsigned prim_mode
:3;
319 uint64_t inputs_to_copy
;
322 /* Common PS bits between the shader key and the prolog key. */
323 struct si_ps_prolog_bits
{
324 unsigned color_two_side
:1;
325 unsigned flatshade_colors
:1;
326 unsigned poly_stipple
:1;
327 unsigned force_persp_sample_interp
:1;
328 unsigned force_linear_sample_interp
:1;
329 unsigned force_persp_center_interp
:1;
330 unsigned force_linear_center_interp
:1;
331 unsigned bc_optimize_for_persp
:1;
332 unsigned bc_optimize_for_linear
:1;
335 /* Common PS bits between the shader key and the epilog key. */
336 struct si_ps_epilog_bits
{
337 unsigned spi_shader_col_format
;
338 unsigned color_is_int8
:8;
339 unsigned last_cbuf
:3;
340 unsigned alpha_func
:3;
341 unsigned alpha_to_one
:1;
342 unsigned poly_line_smoothing
:1;
343 unsigned clamp_color
:1;
346 union si_shader_part_key
{
348 struct si_vs_prolog_bits states
;
349 unsigned num_input_sgprs
:5;
350 unsigned last_input
:4;
353 struct si_vs_epilog_bits states
;
354 unsigned prim_id_param_offset
:5;
357 struct si_tcs_epilog_bits states
;
360 struct si_ps_prolog_bits states
;
361 unsigned num_input_sgprs
:5;
362 unsigned num_input_vgprs
:5;
363 /* Color interpolation and two-side color selection. */
364 unsigned colors_read
:8; /* color input components read */
365 unsigned num_interp_inputs
:5; /* BCOLOR is at this location */
366 unsigned face_vgpr_index
:5;
368 char color_attr_index
[2];
369 char color_interp_vgpr_index
[2]; /* -1 == constant */
372 struct si_ps_epilog_bits states
;
373 unsigned colors_written
:8;
375 unsigned writes_stencil
:1;
376 unsigned writes_samplemask
:1;
380 union si_shader_key
{
382 struct si_ps_prolog_bits prolog
;
383 struct si_ps_epilog_bits epilog
;
386 struct si_vs_prolog_bits prolog
;
387 struct si_vs_epilog_bits epilog
;
388 unsigned as_es
:1; /* export shader */
389 unsigned as_ls
:1; /* local shader */
392 struct si_tcs_epilog_bits epilog
;
393 } tcs
; /* tessellation control shader */
395 struct si_vs_epilog_bits epilog
; /* same as VS */
396 unsigned as_es
:1; /* export shader */
397 } tes
; /* tessellation evaluation shader */
400 struct si_shader_config
{
403 unsigned spilled_sgprs
;
404 unsigned spilled_vgprs
;
406 unsigned spi_ps_input_ena
;
407 unsigned spi_ps_input_addr
;
409 unsigned scratch_bytes_per_wave
;
414 /* GCN-specific shader info. */
415 struct si_shader_info
{
416 ubyte vs_output_param_offset
[SI_MAX_VS_OUTPUTS
];
417 ubyte num_input_sgprs
;
418 ubyte num_input_vgprs
;
419 char face_vgpr_index
;
420 bool uses_instanceid
;
421 ubyte nr_pos_exports
;
422 ubyte nr_param_exports
;
426 struct si_shader_selector
*selector
;
427 struct si_shader
*next_variant
;
429 struct si_shader_part
*prolog
;
430 struct si_shader_part
*epilog
;
432 struct si_shader
*gs_copy_shader
;
433 struct si_pm4_state
*pm4
;
434 struct r600_resource
*bo
;
435 struct r600_resource
*scratch_bo
;
436 union si_shader_key key
;
437 bool is_binary_shared
;
440 /* The following data is all that's needed for binary shaders. */
441 struct radeon_shader_binary binary
;
442 struct si_shader_config config
;
443 struct si_shader_info info
;
445 /* Shader key + LLVM IR + disassembly + statistics.
446 * Generated for debug contexts only.
449 size_t shader_log_size
;
452 struct si_shader_part
{
453 struct si_shader_part
*next
;
454 union si_shader_part_key key
;
455 struct radeon_shader_binary binary
;
456 struct si_shader_config config
;
459 static inline struct tgsi_shader_info
*si_get_vs_info(struct si_context
*sctx
)
461 if (sctx
->gs_shader
.cso
)
462 return &sctx
->gs_shader
.cso
->info
;
463 else if (sctx
->tes_shader
.cso
)
464 return &sctx
->tes_shader
.cso
->info
;
465 else if (sctx
->vs_shader
.cso
)
466 return &sctx
->vs_shader
.cso
->info
;
471 static inline struct si_shader
* si_get_vs_state(struct si_context
*sctx
)
473 if (sctx
->gs_shader
.current
)
474 return sctx
->gs_shader
.current
->gs_copy_shader
;
475 else if (sctx
->tes_shader
.current
)
476 return sctx
->tes_shader
.current
;
478 return sctx
->vs_shader
.current
;
481 static inline bool si_vs_exports_prim_id(struct si_shader
*shader
)
483 if (shader
->selector
->type
== PIPE_SHADER_VERTEX
)
484 return shader
->key
.vs
.epilog
.export_prim_id
;
485 else if (shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
)
486 return shader
->key
.tes
.epilog
.export_prim_id
;
492 int si_compile_tgsi_shader(struct si_screen
*sscreen
,
493 LLVMTargetMachineRef tm
,
494 struct si_shader
*shader
,
496 struct pipe_debug_callback
*debug
);
497 int si_shader_create(struct si_screen
*sscreen
, LLVMTargetMachineRef tm
,
498 struct si_shader
*shader
,
499 struct pipe_debug_callback
*debug
);
500 int si_compile_llvm(struct si_screen
*sscreen
,
501 struct radeon_shader_binary
*binary
,
502 struct si_shader_config
*conf
,
503 LLVMTargetMachineRef tm
,
505 struct pipe_debug_callback
*debug
,
508 void si_shader_destroy(struct si_shader
*shader
);
509 unsigned si_shader_io_get_unique_index(unsigned semantic_name
, unsigned index
);
510 int si_shader_binary_upload(struct si_screen
*sscreen
, struct si_shader
*shader
);
511 void si_shader_dump(struct si_screen
*sscreen
, struct si_shader
*shader
,
512 struct pipe_debug_callback
*debug
, unsigned processor
,
514 void si_shader_apply_scratch_relocs(struct si_context
*sctx
,
515 struct si_shader
*shader
,
516 struct si_shader_config
*config
,
517 uint64_t scratch_va
);
518 void si_shader_binary_read_config(struct radeon_shader_binary
*binary
,
519 struct si_shader_config
*conf
,
520 unsigned symbol_offset
);