2 * Copyright 2012 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 * Tom Stellard <thomas.stellard@amd.com>
25 * Michel Dänzer <michel.daenzer@amd.com>
26 * Christian König <christian.koenig@amd.com>
29 /* How linking shader inputs and outputs between vertex, tessellation, and
30 * geometry shaders works.
32 * Inputs and outputs between shaders are stored in a buffer. This buffer
33 * lives in LDS (typical case for tessellation), but it can also live
34 * in memory (ESGS). Each input or output has a fixed location within a vertex.
35 * The highest used input or output determines the stride between vertices.
37 * Since GS and tessellation are only possible in the OpenGL core profile,
38 * only these semantics are valid for per-vertex data:
45 * CULLDIST0..1 (not implemented)
48 * For example, a shader only writing GENERIC0 has the output stride of 5.
50 * Only these semantics are valid for per-patch data:
58 * That's how independent shaders agree on input and output locations.
59 * The si_shader_io_get_unique_index function assigns the locations.
61 * For tessellation, other required information for calculating the input and
62 * output addresses like the vertex stride, the patch stride, and the offsets
63 * where per-vertex and per-patch data start, is passed to the shader via
64 * user data SGPRs. The offsets and strides are calculated at draw time and
65 * aren't available at compile time.
71 #include <llvm-c/Core.h> /* LLVMModuleRef */
72 #include <llvm-c/TargetMachine.h>
73 #include "tgsi/tgsi_scan.h"
74 #include "util/u_queue.h"
77 struct ac_shader_binary
;
79 #define SI_MAX_VS_OUTPUTS 40
81 /* SGPR user data indices */
83 SI_SGPR_RW_BUFFERS
, /* rings (& stream-out, VS only) */
84 SI_SGPR_RW_BUFFERS_HI
,
85 SI_SGPR_CONST_BUFFERS
,
86 SI_SGPR_CONST_BUFFERS_HI
,
87 SI_SGPR_SAMPLERS
, /* images & sampler states interleaved */
91 SI_SGPR_SHADER_BUFFERS
,
92 SI_SGPR_SHADER_BUFFERS_HI
,
93 SI_NUM_RESOURCE_SGPRS
,
96 SI_SGPR_VERTEX_BUFFERS
= SI_NUM_RESOURCE_SGPRS
,
97 SI_SGPR_VERTEX_BUFFERS_HI
,
99 SI_SGPR_START_INSTANCE
,
101 SI_SGPR_VS_STATE_BITS
,
104 /* both TCS and TES */
105 SI_SGPR_TCS_OFFCHIP_LAYOUT
= SI_NUM_RESOURCE_SGPRS
,
106 SI_TES_NUM_USER_SGPR
,
109 SI_SGPR_TCS_OUT_OFFSETS
= SI_TES_NUM_USER_SGPR
,
110 SI_SGPR_TCS_OUT_LAYOUT
,
111 SI_SGPR_TCS_IN_LAYOUT
,
112 SI_TCS_NUM_USER_SGPR
,
115 SI_GS_NUM_USER_SGPR
= SI_NUM_RESOURCE_SGPRS
,
116 SI_GSCOPY_NUM_USER_SGPR
= SI_SGPR_RW_BUFFERS_HI
+ 1,
119 SI_SGPR_ALPHA_REF
= SI_NUM_RESOURCE_SGPRS
,
123 SI_SGPR_GRID_SIZE
= SI_NUM_RESOURCE_SGPRS
,
124 SI_SGPR_BLOCK_SIZE
= SI_SGPR_GRID_SIZE
+ 3,
125 SI_CS_NUM_USER_SGPR
= SI_SGPR_BLOCK_SIZE
+ 3
128 /* LLVM function parameter indices */
131 SI_PARAM_CONST_BUFFERS
,
134 SI_PARAM_SHADER_BUFFERS
,
135 SI_NUM_RESOURCE_PARAMS
,
137 /* VS only parameters */
138 SI_PARAM_VERTEX_BUFFERS
= SI_NUM_RESOURCE_PARAMS
,
139 SI_PARAM_BASE_VERTEX
,
140 SI_PARAM_START_INSTANCE
,
142 SI_PARAM_VS_STATE_BITS
,
144 /* Layout of TCS outputs in the offchip buffer
145 * [0:8] = the number of patches per threadgroup.
146 * [9:15] = the number of output vertices per patch.
147 * [16:31] = the offset of per patch attributes in the buffer in bytes.
149 SI_PARAM_TCS_OFFCHIP_LAYOUT
= SI_NUM_RESOURCE_PARAMS
, /* for TCS & TES */
151 /* TCS only parameters. */
153 /* Offsets where TCS outputs and TCS patch outputs live in LDS:
154 * [0:15] = TCS output patch0 offset / 16, max = NUM_PATCHES * 32 * 32
155 * [16:31] = TCS output patch0 offset for per-patch / 16, max = NUM_PATCHES*32*32* + 32*32
157 SI_PARAM_TCS_OUT_OFFSETS
,
159 /* Layout of TCS outputs / TES inputs:
160 * [0:12] = stride between output patches in dwords, num_outputs * num_vertices * 4, max = 32*32*4
161 * [13:20] = stride between output vertices in dwords = num_inputs * 4, max = 32*4
162 * [26:31] = gl_PatchVerticesIn, max = 32
164 SI_PARAM_TCS_OUT_LAYOUT
,
166 /* Layout of LS outputs / TCS inputs
167 * [8:20] = stride between patches in dwords = num_inputs * num_vertices * 4, max = 32*32*4
168 * [24:31] = stride between vertices in dwords = num_inputs * 4, max = 32*4
169 * (same layout as SI_PARAM_VS_STATE_BITS)
171 SI_PARAM_TCS_IN_LAYOUT
,
174 SI_PARAM_TESS_FACTOR_OFFSET
,
178 /* GS only parameters */
179 SI_PARAM_GS2VS_OFFSET
= SI_NUM_RESOURCE_PARAMS
,
181 SI_PARAM_VTX0_OFFSET
,
182 SI_PARAM_VTX1_OFFSET
,
183 SI_PARAM_PRIMITIVE_ID
,
184 SI_PARAM_VTX2_OFFSET
,
185 SI_PARAM_VTX3_OFFSET
,
186 SI_PARAM_VTX4_OFFSET
,
187 SI_PARAM_VTX5_OFFSET
,
188 SI_PARAM_GS_INSTANCE_ID
,
190 /* PS only parameters */
191 SI_PARAM_ALPHA_REF
= SI_NUM_RESOURCE_PARAMS
,
193 SI_PARAM_PERSP_SAMPLE
,
194 SI_PARAM_PERSP_CENTER
,
195 SI_PARAM_PERSP_CENTROID
,
196 SI_PARAM_PERSP_PULL_MODEL
,
197 SI_PARAM_LINEAR_SAMPLE
,
198 SI_PARAM_LINEAR_CENTER
,
199 SI_PARAM_LINEAR_CENTROID
,
200 SI_PARAM_LINE_STIPPLE_TEX
,
201 SI_PARAM_POS_X_FLOAT
,
202 SI_PARAM_POS_Y_FLOAT
,
203 SI_PARAM_POS_Z_FLOAT
,
204 SI_PARAM_POS_W_FLOAT
,
207 SI_PARAM_SAMPLE_COVERAGE
,
208 SI_PARAM_POS_FIXED_PT
,
210 /* CS only parameters */
211 SI_PARAM_GRID_SIZE
= SI_NUM_RESOURCE_PARAMS
,
216 SI_NUM_PARAMS
= SI_PARAM_POS_FIXED_PT
+ 9, /* +8 for COLOR[0..1] */
219 /* Fields of driver-defined VS state SGPR. */
220 /* Clamp vertex color output (only used in VS as VS). */
221 #define S_VS_STATE_CLAMP_VERTEX_COLOR(x) (((unsigned)(x) & 0x1) << 0)
222 #define C_VS_STATE_CLAMP_VERTEX_COLOR 0xFFFFFFFE
223 #define S_VS_STATE_LS_OUT_PATCH_SIZE(x) (((unsigned)(x) & 0x1FFF) << 8)
224 #define C_VS_STATE_LS_OUT_PATCH_SIZE 0xFFE000FF
225 #define S_VS_STATE_LS_OUT_VERTEX_SIZE(x) (((unsigned)(x) & 0xFF) << 24)
226 #define C_VS_STATE_LS_OUT_VERTEX_SIZE 0x00FFFFFF
228 /* SI-specific system values. */
230 TGSI_SEMANTIC_DEFAULT_TESSOUTER_SI
= TGSI_SEMANTIC_COUNT
,
231 TGSI_SEMANTIC_DEFAULT_TESSINNER_SI
,
234 /* For VS shader key fix_fetch. */
236 SI_FIX_FETCH_NONE
= 0,
237 SI_FIX_FETCH_A2_SNORM
,
238 SI_FIX_FETCH_A2_SSCALED
,
239 SI_FIX_FETCH_A2_SINT
,
240 SI_FIX_FETCH_RGBA_32_UNORM
,
241 SI_FIX_FETCH_RGBX_32_UNORM
,
242 SI_FIX_FETCH_RGBA_32_SNORM
,
243 SI_FIX_FETCH_RGBX_32_SNORM
,
244 SI_FIX_FETCH_RGBA_32_USCALED
,
245 SI_FIX_FETCH_RGBA_32_SSCALED
,
246 SI_FIX_FETCH_RGBA_32_FIXED
,
247 SI_FIX_FETCH_RGBX_32_FIXED
,
248 SI_FIX_FETCH_RG_64_FLOAT
,
249 SI_FIX_FETCH_RGB_64_FLOAT
,
250 SI_FIX_FETCH_RGBA_64_FLOAT
,
251 SI_FIX_FETCH_RGB_8
, /* A = 1.0 */
252 SI_FIX_FETCH_RGB_8_INT
, /* A = 1 */
254 SI_FIX_FETCH_RGB_16_INT
,
259 /* State of the context creating the shader object. */
260 struct si_compiler_ctx_state
{
261 /* Should only be used by si_init_shader_selector_async and
262 * si_build_shader_variant if thread_index == -1 (non-threaded). */
263 LLVMTargetMachineRef tm
;
265 /* Used if thread_index == -1 or if debug.async is true. */
266 struct pipe_debug_callback debug
;
268 /* Used for creating the log string for gallium/ddebug. */
269 bool is_debug_context
;
272 /* A shader selector is a gallium CSO and contains shader variants and
273 * binaries for one TGSI program. This can be shared by multiple contexts.
275 struct si_shader_selector
{
276 struct si_screen
*screen
;
277 struct util_queue_fence ready
;
278 struct si_compiler_ctx_state compiler_ctx_state
;
281 struct si_shader
*first_variant
; /* immutable after the first variant */
282 struct si_shader
*last_variant
; /* mutable */
284 /* The compiled TGSI shader expecting a prolog and/or epilog (not
285 * uploaded to a buffer).
287 struct si_shader
*main_shader_part
;
288 struct si_shader
*main_shader_part_ls
; /* as_ls is set in the key */
289 struct si_shader
*main_shader_part_es
; /* as_es is set in the key */
291 struct si_shader
*gs_copy_shader
;
293 struct tgsi_token
*tokens
;
294 struct pipe_stream_output_info so
;
295 struct tgsi_shader_info info
;
297 /* PIPE_SHADER_[VERTEX|FRAGMENT|...] */
301 unsigned esgs_itemsize
;
302 unsigned gs_input_verts_per_prim
;
303 unsigned gs_output_prim
;
304 unsigned gs_max_out_vertices
;
305 unsigned gs_num_invocations
;
306 unsigned max_gs_stream
; /* count - 1 */
307 unsigned gsvs_vertex_size
;
308 unsigned max_gsvs_emit_size
;
311 unsigned color_attr_index
[2];
312 unsigned db_shader_control
;
313 /* Set 0xf or 0x0 (4 bits) per each written output.
314 * ANDed with spi_shader_col_format.
316 unsigned colors_written_4bit
;
321 uint64_t outputs_written
; /* "get_unique_index" bits */
322 uint32_t patch_outputs_written
; /* "get_unique_index" bits */
323 uint32_t outputs_written2
; /* "get_unique_index2" bits */
325 uint64_t inputs_read
; /* "get_unique_index" bits */
326 uint32_t inputs_read2
; /* "get_unique_index2" bits */
329 /* Valid shader configurations:
331 * API shaders VS | TCS | TES | GS |pass| PS
332 * are compiled as: | | | |thru|
334 * Only VS & PS: VS | -- | -- | -- | -- | PS
335 * With GS: ES | -- | -- | GS | VS | PS
336 * With Tessel.: LS | HS | VS | -- | -- | PS
337 * With both: LS | HS | ES | GS | VS | PS
340 /* Common VS bits between the shader key and the prolog key. */
341 struct si_vs_prolog_bits
{
342 unsigned instance_divisors
[SI_MAX_ATTRIBS
];
345 /* Common VS bits between the shader key and the epilog key. */
346 struct si_vs_epilog_bits
{
347 unsigned export_prim_id
:1; /* when PS needs it and GS is disabled */
350 /* Common TCS bits between the shader key and the epilog key. */
351 struct si_tcs_epilog_bits
{
352 unsigned prim_mode
:3;
353 unsigned tes_reads_tess_factors
:1;
356 struct si_gs_prolog_bits
{
357 unsigned tri_strip_adj_fix
:1;
360 /* Common PS bits between the shader key and the prolog key. */
361 struct si_ps_prolog_bits
{
362 unsigned color_two_side
:1;
363 unsigned flatshade_colors
:1;
364 unsigned poly_stipple
:1;
365 unsigned force_persp_sample_interp
:1;
366 unsigned force_linear_sample_interp
:1;
367 unsigned force_persp_center_interp
:1;
368 unsigned force_linear_center_interp
:1;
369 unsigned bc_optimize_for_persp
:1;
370 unsigned bc_optimize_for_linear
:1;
373 /* Common PS bits between the shader key and the epilog key. */
374 struct si_ps_epilog_bits
{
375 unsigned spi_shader_col_format
;
376 unsigned color_is_int8
:8;
377 unsigned color_is_int10
:8;
378 unsigned last_cbuf
:3;
379 unsigned alpha_func
:3;
380 unsigned alpha_to_one
:1;
381 unsigned poly_line_smoothing
:1;
382 unsigned clamp_color
:1;
385 union si_shader_part_key
{
387 struct si_vs_prolog_bits states
;
388 unsigned num_input_sgprs
:5;
389 unsigned last_input
:4;
392 struct si_vs_epilog_bits states
;
393 unsigned prim_id_param_offset
:5;
396 struct si_tcs_epilog_bits states
;
399 struct si_gs_prolog_bits states
;
402 struct si_ps_prolog_bits states
;
403 unsigned num_input_sgprs
:5;
404 unsigned num_input_vgprs
:5;
405 /* Color interpolation and two-side color selection. */
406 unsigned colors_read
:8; /* color input components read */
407 unsigned num_interp_inputs
:5; /* BCOLOR is at this location */
408 unsigned face_vgpr_index
:5;
410 char color_attr_index
[2];
411 char color_interp_vgpr_index
[2]; /* -1 == constant */
414 struct si_ps_epilog_bits states
;
415 unsigned colors_written
:8;
417 unsigned writes_stencil
:1;
418 unsigned writes_samplemask
:1;
422 struct si_shader_key
{
423 /* Prolog and epilog flags. */
426 struct si_vs_prolog_bits prolog
;
427 struct si_vs_epilog_bits epilog
;
430 struct si_tcs_epilog_bits epilog
;
431 } tcs
; /* tessellation control shader */
433 struct si_vs_epilog_bits epilog
; /* same as VS */
434 } tes
; /* tessellation evaluation shader */
436 struct si_gs_prolog_bits prolog
;
439 struct si_ps_prolog_bits prolog
;
440 struct si_ps_epilog_bits epilog
;
444 /* These two are initially set according to the NEXT_SHADER property,
445 * or guessed if the property doesn't seem correct.
447 unsigned as_es
:1; /* export shader, which precedes GS */
448 unsigned as_ls
:1; /* local shader, which precedes TCS */
450 /* Flags for monolithic compilation only. */
453 /* One byte for every input: SI_FIX_FETCH_* enums. */
454 uint8_t fix_fetch
[SI_MAX_ATTRIBS
];
457 uint64_t inputs_to_copy
; /* for fixed-func TCS */
461 /* Optimization flags for asynchronous compilation only. */
464 uint64_t kill_outputs
; /* "get_unique_index" bits */
465 uint32_t kill_outputs2
; /* "get_unique_index2" bits */
466 unsigned clip_disable
:1;
467 } hw_vs
; /* HW VS (it can be VS, TES, GS) */
471 struct si_shader_config
{
474 unsigned spilled_sgprs
;
475 unsigned spilled_vgprs
;
476 unsigned private_mem_vgprs
;
478 unsigned spi_ps_input_ena
;
479 unsigned spi_ps_input_addr
;
481 unsigned scratch_bytes_per_wave
;
487 /* SPI_PS_INPUT_CNTL_i.OFFSET[0:4] */
488 EXP_PARAM_OFFSET_0
= 0,
489 EXP_PARAM_OFFSET_31
= 31,
490 /* SPI_PS_INPUT_CNTL_i.DEFAULT_VAL[0:1] */
491 EXP_PARAM_DEFAULT_VAL_0000
= 64,
492 EXP_PARAM_DEFAULT_VAL_0001
,
493 EXP_PARAM_DEFAULT_VAL_1110
,
494 EXP_PARAM_DEFAULT_VAL_1111
,
495 EXP_PARAM_UNDEFINED
= 255,
498 /* GCN-specific shader info. */
499 struct si_shader_info
{
500 ubyte vs_output_param_offset
[SI_MAX_VS_OUTPUTS
];
501 ubyte num_input_sgprs
;
502 ubyte num_input_vgprs
;
503 char face_vgpr_index
;
504 bool uses_instanceid
;
505 ubyte nr_pos_exports
;
506 ubyte nr_param_exports
;
510 struct si_compiler_ctx_state compiler_ctx_state
;
512 struct si_shader_selector
*selector
;
513 struct si_shader
*next_variant
;
515 struct si_shader_part
*prolog
;
516 struct si_shader_part
*epilog
;
518 struct si_pm4_state
*pm4
;
519 struct r600_resource
*bo
;
520 struct r600_resource
*scratch_bo
;
521 struct si_shader_key key
;
522 struct util_queue_fence optimized_ready
;
523 bool compilation_failed
;
526 bool is_binary_shared
;
527 bool is_gs_copy_shader
;
529 /* The following data is all that's needed for binary shaders. */
530 struct ac_shader_binary binary
;
531 struct si_shader_config config
;
532 struct si_shader_info info
;
534 /* Shader key + LLVM IR + disassembly + statistics.
535 * Generated for debug contexts only.
538 size_t shader_log_size
;
541 struct si_shader_part
{
542 struct si_shader_part
*next
;
543 union si_shader_part_key key
;
544 struct ac_shader_binary binary
;
545 struct si_shader_config config
;
550 si_generate_gs_copy_shader(struct si_screen
*sscreen
,
551 LLVMTargetMachineRef tm
,
552 struct si_shader_selector
*gs_selector
,
553 struct pipe_debug_callback
*debug
);
554 int si_compile_tgsi_shader(struct si_screen
*sscreen
,
555 LLVMTargetMachineRef tm
,
556 struct si_shader
*shader
,
558 struct pipe_debug_callback
*debug
);
559 int si_shader_create(struct si_screen
*sscreen
, LLVMTargetMachineRef tm
,
560 struct si_shader
*shader
,
561 struct pipe_debug_callback
*debug
);
562 int si_compile_llvm(struct si_screen
*sscreen
,
563 struct ac_shader_binary
*binary
,
564 struct si_shader_config
*conf
,
565 LLVMTargetMachineRef tm
,
567 struct pipe_debug_callback
*debug
,
570 void si_shader_destroy(struct si_shader
*shader
);
571 unsigned si_shader_io_get_unique_index(unsigned semantic_name
, unsigned index
);
572 unsigned si_shader_io_get_unique_index2(unsigned name
, unsigned index
);
573 int si_shader_binary_upload(struct si_screen
*sscreen
, struct si_shader
*shader
);
574 void si_shader_dump(struct si_screen
*sscreen
, struct si_shader
*shader
,
575 struct pipe_debug_callback
*debug
, unsigned processor
,
576 FILE *f
, bool check_debug_option
);
577 void si_multiwave_lds_size_workaround(struct si_screen
*sscreen
,
579 void si_shader_apply_scratch_relocs(struct si_context
*sctx
,
580 struct si_shader
*shader
,
581 struct si_shader_config
*config
,
582 uint64_t scratch_va
);
583 void si_shader_binary_read_config(struct ac_shader_binary
*binary
,
584 struct si_shader_config
*conf
,
585 unsigned symbol_offset
);
586 unsigned si_get_spi_shader_z_format(bool writes_z
, bool writes_stencil
,
587 bool writes_samplemask
);
588 const char *si_get_shader_name(struct si_shader
*shader
, unsigned processor
);
590 /* Inline helpers. */
592 /* Return the pointer to the main shader part's pointer. */
593 static inline struct si_shader
**
594 si_get_main_shader_part(struct si_shader_selector
*sel
,
595 struct si_shader_key
*key
)
598 return &sel
->main_shader_part_ls
;
600 return &sel
->main_shader_part_es
;
601 return &sel
->main_shader_part
;