2 * Copyright 2012 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 * Tom Stellard <thomas.stellard@amd.com>
25 * Michel Dänzer <michel.daenzer@amd.com>
26 * Christian König <christian.koenig@amd.com>
29 /* How linking shader inputs and outputs between vertex, tessellation, and
30 * geometry shaders works.
32 * Inputs and outputs between shaders are stored in a buffer. This buffer
33 * lives in LDS (typical case for tessellation), but it can also live
34 * in memory (ESGS). Each input or output has a fixed location within a vertex.
35 * The highest used input or output determines the stride between vertices.
37 * Since GS and tessellation are only possible in the OpenGL core profile,
38 * only these semantics are valid for per-vertex data:
45 * CULLDIST0..1 (not implemented)
48 * For example, a shader only writing GENERIC0 has the output stride of 5.
50 * Only these semantics are valid for per-patch data:
58 * That's how independent shaders agree on input and output locations.
59 * The si_shader_io_get_unique_index function assigns the locations.
61 * For tessellation, other required information for calculating the input and
62 * output addresses like the vertex stride, the patch stride, and the offsets
63 * where per-vertex and per-patch data start, is passed to the shader via
64 * user data SGPRs. The offsets and strides are calculated at draw time and
65 * aren't available at compile time.
71 #include <llvm-c/Core.h> /* LLVMModuleRef */
72 #include "tgsi/tgsi_scan.h"
75 struct radeon_shader_binary
;
76 struct radeon_shader_reloc
;
78 #define SI_MAX_VS_OUTPUTS 40
80 #define SI_SGPR_RW_BUFFERS 0 /* rings (& stream-out, VS only) */
81 #define SI_SGPR_CONST_BUFFERS 2
82 #define SI_SGPR_SAMPLERS 4 /* images & sampler states interleaved */
83 #define SI_SGPR_IMAGES 6
84 #define SI_SGPR_SHADER_BUFFERS 8
85 #define SI_SGPR_VERTEX_BUFFERS 10 /* VS only */
86 #define SI_SGPR_BASE_VERTEX 12 /* VS only */
87 #define SI_SGPR_START_INSTANCE 13 /* VS only */
88 #define SI_SGPR_VS_STATE_BITS 14 /* VS(VS) only */
89 #define SI_SGPR_LS_OUT_LAYOUT 14 /* VS(LS) only */
90 #define SI_SGPR_TCS_OUT_OFFSETS 10 /* TCS & TES only */
91 #define SI_SGPR_TCS_OUT_LAYOUT 11 /* TCS & TES only */
92 #define SI_SGPR_TCS_IN_LAYOUT 12 /* TCS only */
93 #define SI_SGPR_ALPHA_REF 10 /* PS only */
95 #define SI_VS_NUM_USER_SGPR 15 /* API VS */
96 #define SI_ES_NUM_USER_SGPR 14 /* API VS */
97 #define SI_LS_NUM_USER_SGPR 15 /* API VS */
98 #define SI_TCS_NUM_USER_SGPR 13
99 #define SI_TES_NUM_USER_SGPR 12
100 #define SI_GS_NUM_USER_SGPR 10
101 #define SI_GSCOPY_NUM_USER_SGPR 4
102 #define SI_PS_NUM_USER_SGPR 11
104 /* LLVM function parameter indices */
105 #define SI_PARAM_RW_BUFFERS 0
106 #define SI_PARAM_CONST_BUFFERS 1
107 #define SI_PARAM_SAMPLERS 2
108 #define SI_PARAM_IMAGES 3
109 #define SI_PARAM_SHADER_BUFFERS 4
111 /* VS only parameters */
112 #define SI_PARAM_VERTEX_BUFFERS 5
113 #define SI_PARAM_BASE_VERTEX 6
114 #define SI_PARAM_START_INSTANCE 7
115 /* [0] = clamp vertex color */
116 #define SI_PARAM_VS_STATE_BITS 8
117 /* the other VS parameters are assigned dynamically */
119 /* Offsets where TCS outputs and TCS patch outputs live in LDS:
120 * [0:15] = TCS output patch0 offset / 16, max = NUM_PATCHES * 32 * 32
121 * [16:31] = TCS output patch0 offset for per-patch / 16, max = NUM_PATCHES*32*32* + 32*32
123 #define SI_PARAM_TCS_OUT_OFFSETS 5 /* for TCS & TES */
125 /* Layout of TCS outputs / TES inputs:
126 * [0:12] = stride between output patches in dwords, num_outputs * num_vertices * 4, max = 32*32*4
127 * [13:20] = stride between output vertices in dwords = num_inputs * 4, max = 32*4
128 * [26:31] = gl_PatchVerticesIn, max = 32
130 #define SI_PARAM_TCS_OUT_LAYOUT 6 /* for TCS & TES */
132 /* Layout of LS outputs / TCS inputs
133 * [0:12] = stride between patches in dwords = num_inputs * num_vertices * 4, max = 32*32*4
134 * [13:20] = stride between vertices in dwords = num_inputs * 4, max = 32*4
136 #define SI_PARAM_TCS_IN_LAYOUT 7 /* TCS only */
137 #define SI_PARAM_LS_OUT_LAYOUT 8 /* same value as TCS_IN_LAYOUT, LS only */
139 /* TCS only parameters. */
140 #define SI_PARAM_TESS_FACTOR_OFFSET 8
141 #define SI_PARAM_PATCH_ID 9
142 #define SI_PARAM_REL_IDS 10
144 /* GS only parameters */
145 #define SI_PARAM_GS2VS_OFFSET 5
146 #define SI_PARAM_GS_WAVE_ID 6
147 #define SI_PARAM_VTX0_OFFSET 7
148 #define SI_PARAM_VTX1_OFFSET 8
149 #define SI_PARAM_PRIMITIVE_ID 9
150 #define SI_PARAM_VTX2_OFFSET 10
151 #define SI_PARAM_VTX3_OFFSET 11
152 #define SI_PARAM_VTX4_OFFSET 12
153 #define SI_PARAM_VTX5_OFFSET 13
154 #define SI_PARAM_GS_INSTANCE_ID 14
156 /* PS only parameters */
157 #define SI_PARAM_ALPHA_REF 5
158 #define SI_PARAM_PRIM_MASK 6
159 #define SI_PARAM_PERSP_SAMPLE 7
160 #define SI_PARAM_PERSP_CENTER 8
161 #define SI_PARAM_PERSP_CENTROID 9
162 #define SI_PARAM_PERSP_PULL_MODEL 10
163 #define SI_PARAM_LINEAR_SAMPLE 11
164 #define SI_PARAM_LINEAR_CENTER 12
165 #define SI_PARAM_LINEAR_CENTROID 13
166 #define SI_PARAM_LINE_STIPPLE_TEX 14
167 #define SI_PARAM_POS_X_FLOAT 15
168 #define SI_PARAM_POS_Y_FLOAT 16
169 #define SI_PARAM_POS_Z_FLOAT 17
170 #define SI_PARAM_POS_W_FLOAT 18
171 #define SI_PARAM_FRONT_FACE 19
172 #define SI_PARAM_ANCILLARY 20
173 #define SI_PARAM_SAMPLE_COVERAGE 21
174 #define SI_PARAM_POS_FIXED_PT 22
176 #define SI_NUM_PARAMS (SI_PARAM_POS_FIXED_PT + 9) /* +8 for COLOR[0..1] */
180 /* A shader selector is a gallium CSO and contains shader variants and
181 * binaries for one TGSI program. This can be shared by multiple contexts.
183 struct si_shader_selector
{
185 struct si_shader
*first_variant
; /* immutable after the first variant */
186 struct si_shader
*last_variant
; /* mutable */
188 /* The compiled TGSI shader expecting a prolog and/or epilog (not
189 * uploaded to a buffer).
191 struct si_shader
*main_shader_part
;
193 struct tgsi_token
*tokens
;
194 struct pipe_stream_output_info so
;
195 struct tgsi_shader_info info
;
197 /* PIPE_SHADER_[VERTEX|FRAGMENT|...] */
201 unsigned esgs_itemsize
;
202 unsigned gs_input_verts_per_prim
;
203 unsigned gs_output_prim
;
204 unsigned gs_max_out_vertices
;
205 unsigned gs_num_invocations
;
206 unsigned max_gs_stream
; /* count - 1 */
207 unsigned gsvs_vertex_size
;
208 unsigned max_gsvs_emit_size
;
211 unsigned color_attr_index
[2];
212 unsigned db_shader_control
;
213 /* Set 0xf or 0x0 (4 bits) per each written output.
214 * ANDed with spi_shader_col_format.
216 unsigned colors_written_4bit
;
218 /* masks of "get_unique_index" bits */
219 uint64_t outputs_written
;
220 uint32_t patch_outputs_written
;
223 /* Valid shader configurations:
225 * API shaders VS | TCS | TES | GS |pass| PS
226 * are compiled as: | | | |thru|
228 * Only VS & PS: VS | -- | -- | -- | -- | PS
229 * With GS: ES | -- | -- | GS | VS | PS
230 * With Tessel.: LS | HS | VS | -- | -- | PS
231 * With both: LS | HS | ES | GS | VS | PS
234 /* Common VS bits between the shader key and the prolog key. */
235 struct si_vs_prolog_bits
{
236 unsigned instance_divisors
[SI_NUM_VERTEX_BUFFERS
];
239 /* Common VS bits between the shader key and the epilog key. */
240 struct si_vs_epilog_bits
{
241 unsigned export_prim_id
:1; /* when PS needs it and GS is disabled */
243 * - skip clipdist, culldist (including clipvertex code) exports based
244 * on which clip_plane_enable bits are set
245 * - skip layer, viewport, clipdist, and culldist parameter exports
246 * if PS doesn't read them
250 /* Common TCS bits between the shader key and the epilog key. */
251 struct si_tcs_epilog_bits
{
252 unsigned prim_mode
:3;
255 /* Common PS bits between the shader key and the prolog key. */
256 struct si_ps_prolog_bits
{
257 unsigned color_two_side
:1;
258 /* TODO: add a flatshade bit that skips interpolation for colors */
259 unsigned poly_stipple
:1;
260 unsigned force_persample_interp
:1;
262 * - add force_center_interp if MSAA is disabled and centroid or
264 * - add force_center_interp_bc_optimize to force center interpolation
265 * based on the bc_optimize SGPR bit if MSAA is enabled, centroid is
266 * present and sample isn't present.
270 /* Common PS bits between the shader key and the epilog key. */
271 struct si_ps_epilog_bits
{
272 unsigned spi_shader_col_format
;
273 unsigned color_is_int8
:8;
274 unsigned last_cbuf
:3;
275 unsigned alpha_func
:3;
276 unsigned alpha_to_one
:1;
277 unsigned poly_line_smoothing
:1;
278 unsigned clamp_color
:1;
281 union si_shader_part_key
{
283 struct si_vs_prolog_bits states
;
284 unsigned num_input_sgprs
:5;
285 unsigned last_input
:4;
288 struct si_vs_epilog_bits states
;
289 unsigned prim_id_param_offset
:5;
292 struct si_tcs_epilog_bits states
;
295 struct si_ps_prolog_bits states
;
296 unsigned num_input_sgprs
:5;
297 unsigned num_input_vgprs
:5;
298 /* Color interpolation and two-side color selection. */
299 unsigned colors_read
:8; /* color input components read */
300 unsigned num_interp_inputs
:5; /* BCOLOR is at this location */
301 unsigned face_vgpr_index
:5;
302 char color_attr_index
[2];
303 char color_interp_vgpr_index
[2]; /* -1 == constant */
306 struct si_ps_epilog_bits states
;
307 unsigned colors_written
:8;
309 unsigned writes_stencil
:1;
310 unsigned writes_samplemask
:1;
314 union si_shader_key
{
316 struct si_ps_prolog_bits prolog
;
317 struct si_ps_epilog_bits epilog
;
320 struct si_vs_prolog_bits prolog
;
321 struct si_vs_epilog_bits epilog
;
322 unsigned as_es
:1; /* export shader */
323 unsigned as_ls
:1; /* local shader */
326 struct si_tcs_epilog_bits epilog
;
327 } tcs
; /* tessellation control shader */
329 struct si_vs_epilog_bits epilog
; /* same as VS */
330 unsigned as_es
:1; /* export shader */
331 } tes
; /* tessellation evaluation shader */
334 struct si_shader_config
{
338 unsigned spi_ps_input_ena
;
339 unsigned spi_ps_input_addr
;
341 unsigned scratch_bytes_per_wave
;
346 /* GCN-specific shader info. */
347 struct si_shader_info
{
348 ubyte vs_output_param_offset
[SI_MAX_VS_OUTPUTS
];
349 ubyte num_input_sgprs
;
350 ubyte num_input_vgprs
;
351 char face_vgpr_index
;
352 bool uses_instanceid
;
353 ubyte nr_pos_exports
;
354 ubyte nr_param_exports
;
358 struct si_shader_selector
*selector
;
359 struct si_shader
*next_variant
;
361 struct si_shader_part
*prolog
;
362 struct si_shader_part
*epilog
;
364 struct si_shader
*gs_copy_shader
;
365 struct si_pm4_state
*pm4
;
366 struct r600_resource
*bo
;
367 struct r600_resource
*scratch_bo
;
368 union si_shader_key key
;
369 bool is_binary_shared
;
372 /* The following data is all that's needed for binary shaders. */
373 struct radeon_shader_binary binary
;
374 struct si_shader_config config
;
375 struct si_shader_info info
;
378 struct si_shader_part
{
379 struct si_shader_part
*next
;
380 union si_shader_part_key key
;
381 struct radeon_shader_binary binary
;
382 struct si_shader_config config
;
385 static inline struct tgsi_shader_info
*si_get_vs_info(struct si_context
*sctx
)
387 if (sctx
->gs_shader
.cso
)
388 return &sctx
->gs_shader
.cso
->info
;
389 else if (sctx
->tes_shader
.cso
)
390 return &sctx
->tes_shader
.cso
->info
;
391 else if (sctx
->vs_shader
.cso
)
392 return &sctx
->vs_shader
.cso
->info
;
397 static inline struct si_shader
* si_get_vs_state(struct si_context
*sctx
)
399 if (sctx
->gs_shader
.current
)
400 return sctx
->gs_shader
.current
->gs_copy_shader
;
401 else if (sctx
->tes_shader
.current
)
402 return sctx
->tes_shader
.current
;
404 return sctx
->vs_shader
.current
;
407 static inline bool si_vs_exports_prim_id(struct si_shader
*shader
)
409 if (shader
->selector
->type
== PIPE_SHADER_VERTEX
)
410 return shader
->key
.vs
.epilog
.export_prim_id
;
411 else if (shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
)
412 return shader
->key
.tes
.epilog
.export_prim_id
;
418 int si_compile_tgsi_shader(struct si_screen
*sscreen
,
419 LLVMTargetMachineRef tm
,
420 struct si_shader
*shader
,
422 struct pipe_debug_callback
*debug
);
423 int si_shader_create(struct si_screen
*sscreen
, LLVMTargetMachineRef tm
,
424 struct si_shader
*shader
,
425 struct pipe_debug_callback
*debug
);
426 void si_dump_shader_key(unsigned shader
, union si_shader_key
*key
, FILE *f
);
427 int si_compile_llvm(struct si_screen
*sscreen
,
428 struct radeon_shader_binary
*binary
,
429 struct si_shader_config
*conf
,
430 LLVMTargetMachineRef tm
,
432 struct pipe_debug_callback
*debug
,
435 void si_shader_destroy(struct si_shader
*shader
);
436 unsigned si_shader_io_get_unique_index(unsigned semantic_name
, unsigned index
);
437 int si_shader_binary_upload(struct si_screen
*sscreen
, struct si_shader
*shader
);
438 void si_shader_dump(struct si_screen
*sscreen
, struct si_shader
*shader
,
439 struct pipe_debug_callback
*debug
, unsigned processor
,
441 void si_shader_apply_scratch_relocs(struct si_context
*sctx
,
442 struct si_shader
*shader
,
443 uint64_t scratch_va
);
444 void si_shader_binary_read_config(struct radeon_shader_binary
*binary
,
445 struct si_shader_config
*conf
,
446 unsigned symbol_offset
);