src/gallium/drivers/radeonsi/si_shader.h

   1 /*
   2  * Copyright 2012 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Tom Stellard <thomas.stellard@amd.com>
  25  *      Michel Dänzer <michel.daenzer@amd.com>
  26  *      Christian König <christian.koenig@amd.com>
  27  */
  28
  29 /* How linking shader inputs and outputs between vertex, tessellation, and
  30  * geometry shaders works.
  31  *
  32  * Inputs and outputs between shaders are stored in a buffer. This buffer
  33  * lives in LDS (typical case for tessellation), but it can also live
  34  * in memory (ESGS). Each input or output has a fixed location within a vertex.
  35  * The highest used input or output determines the stride between vertices.
  36  *
  37  * Since GS and tessellation are only possible in the OpenGL core profile,
  38  * only these semantics are valid for per-vertex data:
  39  *
  40  *   Name             Location
  41  *
  42  *   POSITION         0
  43  *   PSIZE            1
  44  *   CLIPDIST0..1     2..3
  45  *   CULLDIST0..1     (not implemented)
  46  *   GENERIC0..31     4..35
  47  *
  48  * For example, a shader only writing GENERIC0 has the output stride of 5.
  49  *
  50  * Only these semantics are valid for per-patch data:
  51  *
  52  *   Name             Location
  53  *
  54  *   TESSOUTER        0
  55  *   TESSINNER        1
  56  *   PATCH0..29       2..31
  57  *
  58  * That's how independent shaders agree on input and output locations.
  59  * The si_shader_io_get_unique_index function assigns the locations.
  60  *
  61  * For tessellation, other required information for calculating the input and
  62  * output addresses like the vertex stride, the patch stride, and the offsets
  63  * where per-vertex and per-patch data start, is passed to the shader via
  64  * user data SGPRs. The offsets and strides are calculated at draw time and
  65  * aren't available at compile time.
  66  */
  67
  68 #ifndef SI_SHADER_H
  69 #define SI_SHADER_H
  70
  71 #include <llvm-c/Core.h> /* LLVMModuleRef */
  72 #include "tgsi/tgsi_scan.h"
  73 #include "si_state.h"
  74
  75 struct radeon_shader_binary;
  76 struct radeon_shader_reloc;
  77
  78 #define SI_MAX_VS_OUTPUTS       40
  79
  80 /* SGPR user data indices */
  81 enum {
  82         SI_SGPR_RW_BUFFERS,  /* rings (& stream-out, VS only) */
  83         SI_SGPR_RW_BUFFERS_HI,
  84         SI_SGPR_CONST_BUFFERS,
  85         SI_SGPR_CONST_BUFFERS_HI,
  86         SI_SGPR_SAMPLERS,  /* images & sampler states interleaved */
  87         SI_SGPR_SAMPLERS_HI,
  88         SI_SGPR_IMAGES,
  89         SI_SGPR_IMAGES_HI,
  90         SI_SGPR_SHADER_BUFFERS,
  91         SI_SGPR_SHADER_BUFFERS_HI,
  92         SI_NUM_RESOURCE_SGPRS,
  93
  94         /* all VS variants */
  95         SI_SGPR_VERTEX_BUFFERS  = SI_NUM_RESOURCE_SGPRS,
  96         SI_SGPR_VERTEX_BUFFERS_HI,
  97         SI_SGPR_BASE_VERTEX,
  98         SI_SGPR_START_INSTANCE,
  99         SI_ES_NUM_USER_SGPR,
 100
 101         /* hw VS only */
 102         SI_SGPR_VS_STATE_BITS   = SI_ES_NUM_USER_SGPR,
 103         SI_VS_NUM_USER_SGPR,
 104
 105         /* hw LS only */
 106         SI_SGPR_LS_OUT_LAYOUT   = SI_ES_NUM_USER_SGPR,
 107         SI_LS_NUM_USER_SGPR,
 108
 109         /* both TCS and TES */
 110         SI_SGPR_TCS_OFFCHIP_LAYOUT = SI_NUM_RESOURCE_SGPRS,
 111         SI_TES_NUM_USER_SGPR,
 112
 113         /* TCS only */
 114         SI_SGPR_TCS_OUT_OFFSETS = SI_TES_NUM_USER_SGPR,
 115         SI_SGPR_TCS_OUT_LAYOUT,
 116         SI_SGPR_TCS_IN_LAYOUT,
 117         SI_TCS_NUM_USER_SGPR,
 118
 119         /* GS limits */
 120         SI_GS_NUM_USER_SGPR = SI_NUM_RESOURCE_SGPRS,
 121         SI_GSCOPY_NUM_USER_SGPR = SI_SGPR_RW_BUFFERS_HI + 1,
 122
 123         /* PS only */
 124         SI_SGPR_ALPHA_REF       = SI_NUM_RESOURCE_SGPRS,
 125         SI_PS_NUM_USER_SGPR,
 126
 127         /* CS only */
 128         SI_SGPR_GRID_SIZE = SI_NUM_RESOURCE_SGPRS,
 129         SI_CS_NUM_USER_SGPR = SI_SGPR_GRID_SIZE + 3
 130 };
 131
 132 /* LLVM function parameter indices */
 133 enum {
 134         SI_PARAM_RW_BUFFERS,
 135         SI_PARAM_CONST_BUFFERS,
 136         SI_PARAM_SAMPLERS,
 137         SI_PARAM_IMAGES,
 138         SI_PARAM_SHADER_BUFFERS,
 139         SI_NUM_RESOURCE_PARAMS,
 140
 141         /* VS only parameters */
 142         SI_PARAM_VERTEX_BUFFERS = SI_NUM_RESOURCE_PARAMS,
 143         SI_PARAM_BASE_VERTEX,
 144         SI_PARAM_START_INSTANCE,
 145         /* [0] = clamp vertex color, VS as VS only */
 146         SI_PARAM_VS_STATE_BITS,
 147         /* same value as TCS_IN_LAYOUT, VS as LS only */
 148         SI_PARAM_LS_OUT_LAYOUT = SI_PARAM_START_INSTANCE + 1,
 149         /* the other VS parameters are assigned dynamically */
 150
 151         /* Layout of TCS outputs in the offchip buffer
 152          *   [0:8] = the number of patches per threadgroup.
 153          *   [9:15] = the number of output vertices per patch.
 154          *   [16:31] = the offset of per patch attributes in the buffer in bytes.
 155          */
 156         SI_PARAM_TCS_OFFCHIP_LAYOUT = SI_NUM_RESOURCE_PARAMS, /* for TCS & TES */
 157
 158         /* TCS only parameters. */
 159
 160         /* Offsets where TCS outputs and TCS patch outputs live in LDS:
 161          *   [0:15] = TCS output patch0 offset / 16, max = NUM_PATCHES * 32 * 32
 162          *   [16:31] = TCS output patch0 offset for per-patch / 16, max = NUM_PATCHES*32*32* + 32*32
 163          */
 164         SI_PARAM_TCS_OUT_OFFSETS,
 165
 166         /* Layout of TCS outputs / TES inputs:
 167          *   [0:12] = stride between output patches in dwords, num_outputs * num_vertices * 4, max = 32*32*4
 168          *   [13:20] = stride between output vertices in dwords = num_inputs * 4, max = 32*4
 169          *   [26:31] = gl_PatchVerticesIn, max = 32
 170          */
 171         SI_PARAM_TCS_OUT_LAYOUT,
 172
 173         /* Layout of LS outputs / TCS inputs
 174          *   [0:12] = stride between patches in dwords = num_inputs * num_vertices * 4, max = 32*32*4
 175          *   [13:20] = stride between vertices in dwords = num_inputs * 4, max = 32*4
 176          */
 177         SI_PARAM_TCS_IN_LAYOUT,
 178
 179         SI_PARAM_TCS_OC_LDS,
 180         SI_PARAM_TESS_FACTOR_OFFSET,
 181         SI_PARAM_PATCH_ID,
 182         SI_PARAM_REL_IDS,
 183
 184         /* GS only parameters */
 185         SI_PARAM_GS2VS_OFFSET = SI_NUM_RESOURCE_PARAMS,
 186         SI_PARAM_GS_WAVE_ID,
 187         SI_PARAM_VTX0_OFFSET,
 188         SI_PARAM_VTX1_OFFSET,
 189         SI_PARAM_PRIMITIVE_ID,
 190         SI_PARAM_VTX2_OFFSET,
 191         SI_PARAM_VTX3_OFFSET,
 192         SI_PARAM_VTX4_OFFSET,
 193         SI_PARAM_VTX5_OFFSET,
 194         SI_PARAM_GS_INSTANCE_ID,
 195
 196         /* PS only parameters */
 197         SI_PARAM_ALPHA_REF = SI_NUM_RESOURCE_PARAMS,
 198         SI_PARAM_PRIM_MASK,
 199         SI_PARAM_PERSP_SAMPLE,
 200         SI_PARAM_PERSP_CENTER,
 201         SI_PARAM_PERSP_CENTROID,
 202         SI_PARAM_PERSP_PULL_MODEL,
 203         SI_PARAM_LINEAR_SAMPLE,
 204         SI_PARAM_LINEAR_CENTER,
 205         SI_PARAM_LINEAR_CENTROID,
 206         SI_PARAM_LINE_STIPPLE_TEX,
 207         SI_PARAM_POS_X_FLOAT,
 208         SI_PARAM_POS_Y_FLOAT,
 209         SI_PARAM_POS_Z_FLOAT,
 210         SI_PARAM_POS_W_FLOAT,
 211         SI_PARAM_FRONT_FACE,
 212         SI_PARAM_ANCILLARY,
 213         SI_PARAM_SAMPLE_COVERAGE,
 214         SI_PARAM_POS_FIXED_PT,
 215
 216         /* CS only parameters */
 217         SI_PARAM_GRID_SIZE = SI_NUM_RESOURCE_PARAMS,
 218         SI_PARAM_BLOCK_ID,
 219         SI_PARAM_THREAD_ID,
 220
 221         SI_NUM_PARAMS = SI_PARAM_POS_FIXED_PT + 9, /* +8 for COLOR[0..1] */
 222 };
 223
 224 /* SI-specific system values. */
 225 enum {
 226         TGSI_SEMANTIC_DEFAULT_TESSOUTER_SI = TGSI_SEMANTIC_COUNT,
 227         TGSI_SEMANTIC_DEFAULT_TESSINNER_SI,
 228 };
 229
 230 struct si_shader;
 231
 232 /* A shader selector is a gallium CSO and contains shader variants and
 233  * binaries for one TGSI program. This can be shared by multiple contexts.
 234  */
 235 struct si_shader_selector {
 236         struct si_screen        *screen;
 237         struct util_queue_fence ready;
 238
 239         /* Should only be used by si_init_shader_selector_async
 240          * if thread_index == -1 (non-threaded). */
 241         LLVMTargetMachineRef    tm;
 242         struct pipe_debug_callback debug;
 243         bool                    is_debug_context;
 244
 245         pipe_mutex              mutex;
 246         struct si_shader        *first_variant; /* immutable after the first variant */
 247         struct si_shader        *last_variant; /* mutable */
 248
 249         /* The compiled TGSI shader expecting a prolog and/or epilog (not
 250          * uploaded to a buffer).
 251          */
 252         struct si_shader        *main_shader_part;
 253
 254         struct tgsi_token       *tokens;
 255         struct pipe_stream_output_info  so;
 256         struct tgsi_shader_info         info;
 257
 258         /* PIPE_SHADER_[VERTEX|FRAGMENT|...] */
 259         unsigned        type;
 260
 261         /* GS parameters. */
 262         unsigned        esgs_itemsize;
 263         unsigned        gs_input_verts_per_prim;
 264         unsigned        gs_output_prim;
 265         unsigned        gs_max_out_vertices;
 266         unsigned        gs_num_invocations;
 267         unsigned        max_gs_stream; /* count - 1 */
 268         unsigned        gsvs_vertex_size;
 269         unsigned        max_gsvs_emit_size;
 270
 271         /* PS parameters. */
 272         unsigned        color_attr_index[2];
 273         unsigned        db_shader_control;
 274         /* Set 0xf or 0x0 (4 bits) per each written output.
 275          * ANDed with spi_shader_col_format.
 276          */
 277         unsigned        colors_written_4bit;
 278
 279         /* CS parameters */
 280         unsigned local_size;
 281
 282         /* masks of "get_unique_index" bits */
 283         uint64_t        outputs_written;
 284         uint32_t        patch_outputs_written;
 285 };
 286
 287 /* Valid shader configurations:
 288  *
 289  * API shaders       VS | TCS | TES | GS |pass| PS
 290  * are compiled as:     |     |     |    |thru|
 291  *                      |     |     |    |    |
 292  * Only VS & PS:     VS | --  | --  | -- | -- | PS
 293  * With GS:          ES | --  | --  | GS | VS | PS
 294  * With Tessel.:     LS | HS  | VS  | -- | -- | PS
 295  * With both:        LS | HS  | ES  | GS | VS | PS
 296  */
 297
 298 /* Common VS bits between the shader key and the prolog key. */
 299 struct si_vs_prolog_bits {
 300         unsigned        instance_divisors[SI_NUM_VERTEX_BUFFERS];
 301 };
 302
 303 /* Common VS bits between the shader key and the epilog key. */
 304 struct si_vs_epilog_bits {
 305         unsigned        export_prim_id:1; /* when PS needs it and GS is disabled */
 306         /* TODO:
 307          * - skip clipdist, culldist (including clipvertex code) exports based
 308          *   on which clip_plane_enable bits are set
 309          * - skip layer, viewport, clipdist, and culldist parameter exports
 310          *   if PS doesn't read them
 311          */
 312 };
 313
 314 /* Common TCS bits between the shader key and the epilog key. */
 315 struct si_tcs_epilog_bits {
 316         unsigned        prim_mode:3;
 317         uint64_t        inputs_to_copy;
 318 };
 319
 320 /* Common PS bits between the shader key and the prolog key. */
 321 struct si_ps_prolog_bits {
 322         unsigned        color_two_side:1;
 323         unsigned        flatshade_colors:1;
 324         unsigned        poly_stipple:1;
 325         unsigned        force_persp_sample_interp:1;
 326         unsigned        force_linear_sample_interp:1;
 327         unsigned        force_persp_center_interp:1;
 328         unsigned        force_linear_center_interp:1;
 329         unsigned        bc_optimize_for_persp:1;
 330         unsigned        bc_optimize_for_linear:1;
 331 };
 332
 333 /* Common PS bits between the shader key and the epilog key. */
 334 struct si_ps_epilog_bits {
 335         unsigned        spi_shader_col_format;
 336         unsigned        color_is_int8:8;
 337         unsigned        last_cbuf:3;
 338         unsigned        alpha_func:3;
 339         unsigned        alpha_to_one:1;
 340         unsigned        poly_line_smoothing:1;
 341         unsigned        clamp_color:1;
 342 };
 343
 344 union si_shader_part_key {
 345         struct {
 346                 struct si_vs_prolog_bits states;
 347                 unsigned        num_input_sgprs:5;
 348                 unsigned        last_input:4;
 349         } vs_prolog;
 350         struct {
 351                 struct si_vs_epilog_bits states;
 352                 unsigned        prim_id_param_offset:5;
 353         } vs_epilog;
 354         struct {
 355                 struct si_tcs_epilog_bits states;
 356         } tcs_epilog;
 357         struct {
 358                 struct si_ps_prolog_bits states;
 359                 unsigned        num_input_sgprs:5;
 360                 unsigned        num_input_vgprs:5;
 361                 /* Color interpolation and two-side color selection. */
 362                 unsigned        colors_read:8; /* color input components read */
 363                 unsigned        num_interp_inputs:5; /* BCOLOR is at this location */
 364                 unsigned        face_vgpr_index:5;
 365                 unsigned        wqm:1;
 366                 char            color_attr_index[2];
 367                 char            color_interp_vgpr_index[2]; /* -1 == constant */
 368         } ps_prolog;
 369         struct {
 370                 struct si_ps_epilog_bits states;
 371                 unsigned        colors_written:8;
 372                 unsigned        writes_z:1;
 373                 unsigned        writes_stencil:1;
 374                 unsigned        writes_samplemask:1;
 375         } ps_epilog;
 376 };
 377
 378 union si_shader_key {
 379         struct {
 380                 struct si_ps_prolog_bits prolog;
 381                 struct si_ps_epilog_bits epilog;
 382         } ps;
 383         struct {
 384                 struct si_vs_prolog_bits prolog;
 385                 struct si_vs_epilog_bits epilog;
 386                 unsigned        as_es:1; /* export shader */
 387                 unsigned        as_ls:1; /* local shader */
 388         } vs;
 389         struct {
 390                 struct si_tcs_epilog_bits epilog;
 391         } tcs; /* tessellation control shader */
 392         struct {
 393                 struct si_vs_epilog_bits epilog; /* same as VS */
 394                 unsigned        as_es:1; /* export shader */
 395         } tes; /* tessellation evaluation shader */
 396 };
 397
 398 struct si_shader_config {
 399         unsigned                        num_sgprs;
 400         unsigned                        num_vgprs;
 401         unsigned                        spilled_sgprs;
 402         unsigned                        spilled_vgprs;
 403         unsigned                        lds_size;
 404         unsigned                        spi_ps_input_ena;
 405         unsigned                        spi_ps_input_addr;
 406         unsigned                        float_mode;
 407         unsigned                        scratch_bytes_per_wave;
 408         unsigned                        rsrc1;
 409         unsigned                        rsrc2;
 410 };
 411
 412 /* GCN-specific shader info. */
 413 struct si_shader_info {
 414         ubyte                   vs_output_param_offset[SI_MAX_VS_OUTPUTS];
 415         ubyte                   num_input_sgprs;
 416         ubyte                   num_input_vgprs;
 417         char                    face_vgpr_index;
 418         bool                    uses_instanceid;
 419         ubyte                   nr_pos_exports;
 420         ubyte                   nr_param_exports;
 421 };
 422
 423 struct si_shader {
 424         struct si_shader_selector       *selector;
 425         struct si_shader                *next_variant;
 426
 427         struct si_shader_part           *prolog;
 428         struct si_shader_part           *epilog;
 429
 430         struct si_shader                *gs_copy_shader;
 431         struct si_pm4_state             *pm4;
 432         struct r600_resource            *bo;
 433         struct r600_resource            *scratch_bo;
 434         union si_shader_key             key;
 435         bool                            is_binary_shared;
 436         unsigned                        z_order;
 437
 438         /* The following data is all that's needed for binary shaders. */
 439         struct radeon_shader_binary     binary;
 440         struct si_shader_config         config;
 441         struct si_shader_info           info;
 442
 443         /* Shader key + LLVM IR + disassembly + statistics.
 444          * Generated for debug contexts only.
 445          */
 446         char                            *shader_log;
 447         size_t                          shader_log_size;
 448 };
 449
 450 struct si_shader_part {
 451         struct si_shader_part *next;
 452         union si_shader_part_key key;
 453         struct radeon_shader_binary binary;
 454         struct si_shader_config config;
 455 };
 456
 457 static inline struct tgsi_shader_info *si_get_vs_info(struct si_context *sctx)
 458 {
 459         if (sctx->gs_shader.cso)
 460                 return &sctx->gs_shader.cso->info;
 461         else if (sctx->tes_shader.cso)
 462                 return &sctx->tes_shader.cso->info;
 463         else if (sctx->vs_shader.cso)
 464                 return &sctx->vs_shader.cso->info;
 465         else
 466                 return NULL;
 467 }
 468
 469 static inline struct si_shader* si_get_vs_state(struct si_context *sctx)
 470 {
 471         if (sctx->gs_shader.current)
 472                 return sctx->gs_shader.current->gs_copy_shader;
 473         else if (sctx->tes_shader.current)
 474                 return sctx->tes_shader.current;
 475         else
 476                 return sctx->vs_shader.current;
 477 }
 478
 479 static inline bool si_vs_exports_prim_id(struct si_shader *shader)
 480 {
 481         if (shader->selector->type == PIPE_SHADER_VERTEX)
 482                 return shader->key.vs.epilog.export_prim_id;
 483         else if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
 484                 return shader->key.tes.epilog.export_prim_id;
 485         else
 486                 return false;
 487 }
 488
 489 /* si_shader.c */
 490 int si_compile_tgsi_shader(struct si_screen *sscreen,
 491                            LLVMTargetMachineRef tm,
 492                            struct si_shader *shader,
 493                            bool is_monolithic,
 494                            struct pipe_debug_callback *debug);
 495 int si_shader_create(struct si_screen *sscreen, LLVMTargetMachineRef tm,
 496                      struct si_shader *shader,
 497                      struct pipe_debug_callback *debug);
 498 int si_compile_llvm(struct si_screen *sscreen,
 499                     struct radeon_shader_binary *binary,
 500                     struct si_shader_config *conf,
 501                     LLVMTargetMachineRef tm,
 502                     LLVMModuleRef mod,
 503                     struct pipe_debug_callback *debug,
 504                     unsigned processor,
 505                     const char *name);
 506 void si_shader_destroy(struct si_shader *shader);
 507 unsigned si_shader_io_get_unique_index(unsigned semantic_name, unsigned index);
 508 int si_shader_binary_upload(struct si_screen *sscreen, struct si_shader *shader);
 509 void si_shader_dump(struct si_screen *sscreen, struct si_shader *shader,
 510                     struct pipe_debug_callback *debug, unsigned processor,
 511                     FILE *f);
 512 void si_shader_apply_scratch_relocs(struct si_context *sctx,
 513                         struct si_shader *shader,
 514                         struct si_shader_config *config,
 515                         uint64_t scratch_va);
 516 void si_shader_binary_read_config(struct radeon_shader_binary *binary,
 517                                   struct si_shader_config *conf,
 518                                   unsigned symbol_offset);
 519
 520 #endif