src/gallium/drivers/radeonsi/si_shader.h

   1 /*
   2  * Copyright 2012 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Tom Stellard <thomas.stellard@amd.com>
  25  *      Michel Dänzer <michel.daenzer@amd.com>
  26  *      Christian König <christian.koenig@amd.com>
  27  */
  28
  29 /* How linking tessellation shader inputs and outputs works.
  30  *
  31  * Inputs and outputs between shaders are stored in a buffer. This buffer
  32  * lives in LDS (typical case for tessellation), but it can also live
  33  * in memory. Each input or output has a fixed location within a vertex.
  34  * The highest used input or output determines the stride between vertices.
  35  *
  36  * Since tessellation is only enabled in the OpenGL core profile,
  37  * only these semantics are valid for per-vertex data:
  38  *
  39  *   Name             Location
  40  *
  41  *   POSITION         0
  42  *   PSIZE            1
  43  *   CLIPDIST0..1     2..3
  44  *   CULLDIST0..1     (not implemented)
  45  *   GENERIC0..31     4..35
  46  *
  47  * For example, a shader only writing GENERIC0 has the output stride of 5.
  48  *
  49  * Only these semantics are valid for per-patch data:
  50  *
  51  *   Name             Location
  52  *
  53  *   TESSOUTER        0
  54  *   TESSINNER        1
  55  *   PATCH0..29       2..31
  56  *
  57  * That's how independent shaders agree on input and output locations.
  58  * The si_shader_io_get_unique_index function assigns the locations.
  59  *
  60  * Other required information for calculating the input and output addresses
  61  * like the vertex stride, the patch stride, and the offsets where per-vertex
  62  * and per-patch data start, is passed to the shader via user data SGPRs.
  63  * The offsets and strides are calculated at draw time and aren't available
  64  * at compile time.
  65  *
  66  * The same approach should be used for linking ES->GS in the future.
  67  */
  68
  69 #ifndef SI_SHADER_H
  70 #define SI_SHADER_H
  71
  72 #include <llvm-c/Core.h> /* LLVMModuleRef */
  73 #include "tgsi/tgsi_scan.h"
  74 #include "si_state.h"
  75
  76 struct radeon_shader_binary;
  77 struct radeon_shader_reloc;
  78
  79 #define SI_SGPR_RW_BUFFERS      0  /* rings (& stream-out, VS only) */
  80 #define SI_SGPR_CONST           2
  81 #define SI_SGPR_SAMPLER         4
  82 #define SI_SGPR_RESOURCE        6
  83 #define SI_SGPR_VERTEX_BUFFER   8  /* VS only */
  84 #define SI_SGPR_BASE_VERTEX     10 /* VS only */
  85 #define SI_SGPR_START_INSTANCE  11 /* VS only */
  86 #define SI_SGPR_LS_OUT_LAYOUT   12 /* VS(LS) only */
  87 #define SI_SGPR_TCS_OUT_OFFSETS 8  /* TCS & TES only */
  88 #define SI_SGPR_TCS_OUT_LAYOUT  9  /* TCS & TES only */
  89 #define SI_SGPR_TCS_IN_LAYOUT   10 /* TCS only */
  90 #define SI_SGPR_ALPHA_REF       8  /* PS only */
  91 #define SI_SGPR_PS_STATE_BITS   9  /* PS only */
  92
  93 #define SI_VS_NUM_USER_SGPR     12
  94 #define SI_LS_NUM_USER_SGPR     13
  95 #define SI_TCS_NUM_USER_SGPR    11
  96 #define SI_TES_NUM_USER_SGPR    10
  97 #define SI_GS_NUM_USER_SGPR     8
  98 #define SI_GSCOPY_NUM_USER_SGPR 4
  99 #define SI_PS_NUM_USER_SGPR     10
 100
 101 /* LLVM function parameter indices */
 102 #define SI_PARAM_RW_BUFFERS     0
 103 #define SI_PARAM_CONST          1
 104 #define SI_PARAM_SAMPLER        2
 105 #define SI_PARAM_RESOURCE       3
 106
 107 /* VS only parameters */
 108 #define SI_PARAM_VERTEX_BUFFER  4
 109 #define SI_PARAM_BASE_VERTEX    5
 110 #define SI_PARAM_START_INSTANCE 6
 111 /* the other VS parameters are assigned dynamically */
 112
 113 /* Offsets where TCS outputs and TCS patch outputs live in LDS:
 114  *   [0:15] = TCS output patch0 offset / 16, max = NUM_PATCHES * 32 * 32
 115  *   [16:31] = TCS output patch0 offset for per-patch / 16, max = NUM_PATCHES*32*32* + 32*32
 116  */
 117 #define SI_PARAM_TCS_OUT_OFFSETS 4 /* for TCS & TES */
 118
 119 /* Layout of TCS outputs / TES inputs:
 120  *   [0:12] = stride between output patches in dwords, num_outputs * num_vertices * 4, max = 32*32*4
 121  *   [13:20] = stride between output vertices in dwords = num_inputs * 4, max = 32*4
 122  *   [26:31] = gl_PatchVerticesIn, max = 32
 123  */
 124 #define SI_PARAM_TCS_OUT_LAYOUT 5 /* for TCS & TES */
 125
 126 /* Layout of LS outputs / TCS inputs
 127  *   [0:12] = stride between patches in dwords = num_inputs * num_vertices * 4, max = 32*32*4
 128  *   [13:20] = stride between vertices in dwords = num_inputs * 4, max = 32*4
 129  */
 130 #define SI_PARAM_TCS_IN_LAYOUT  6 /* TCS only */
 131 #define SI_PARAM_LS_OUT_LAYOUT  7 /* same value as TCS_IN_LAYOUT, LS only */
 132
 133 /* TCS only parameters. */
 134 #define SI_PARAM_TESS_FACTOR_OFFSET 7
 135 #define SI_PARAM_PATCH_ID       8
 136 #define SI_PARAM_REL_IDS        9
 137
 138 /* GS only parameters */
 139 #define SI_PARAM_GS2VS_OFFSET   4
 140 #define SI_PARAM_GS_WAVE_ID     5
 141 #define SI_PARAM_VTX0_OFFSET    6
 142 #define SI_PARAM_VTX1_OFFSET    7
 143 #define SI_PARAM_PRIMITIVE_ID   8
 144 #define SI_PARAM_VTX2_OFFSET    9
 145 #define SI_PARAM_VTX3_OFFSET    10
 146 #define SI_PARAM_VTX4_OFFSET    11
 147 #define SI_PARAM_VTX5_OFFSET    12
 148 #define SI_PARAM_GS_INSTANCE_ID 13
 149
 150 /* PS only parameters */
 151 #define SI_PARAM_ALPHA_REF              4
 152 /* Bits:
 153  * 0: force_persample_interp
 154  */
 155 #define SI_PARAM_PS_STATE_BITS          5
 156 #define SI_PARAM_PRIM_MASK              6
 157 #define SI_PARAM_PERSP_SAMPLE           7
 158 #define SI_PARAM_PERSP_CENTER           8
 159 #define SI_PARAM_PERSP_CENTROID         9
 160 #define SI_PARAM_PERSP_PULL_MODEL       10
 161 #define SI_PARAM_LINEAR_SAMPLE          11
 162 #define SI_PARAM_LINEAR_CENTER          12
 163 #define SI_PARAM_LINEAR_CENTROID        13
 164 #define SI_PARAM_LINE_STIPPLE_TEX       14
 165 #define SI_PARAM_POS_X_FLOAT            15
 166 #define SI_PARAM_POS_Y_FLOAT            16
 167 #define SI_PARAM_POS_Z_FLOAT            17
 168 #define SI_PARAM_POS_W_FLOAT            18
 169 #define SI_PARAM_FRONT_FACE             19
 170 #define SI_PARAM_ANCILLARY              20
 171 #define SI_PARAM_SAMPLE_COVERAGE        21
 172 #define SI_PARAM_POS_FIXED_PT           22
 173
 174 #define SI_NUM_PARAMS (SI_PARAM_POS_FIXED_PT + 1)
 175
 176 struct si_shader;
 177
 178 struct si_shader_selector {
 179         struct si_shader *current;
 180
 181         struct tgsi_token       *tokens;
 182         struct pipe_stream_output_info  so;
 183         struct tgsi_shader_info         info;
 184
 185         unsigned        num_shaders;
 186
 187         /* PIPE_SHADER_[VERTEX|FRAGMENT|...] */
 188         unsigned        type;
 189
 190         /* Whether the shader has to use a conditional assignment to
 191          * choose between weights when emulating
 192          * pipe_rasterizer_state::force_persample_interp.
 193          * If false, "si_emit_spi_ps_input" will take care of it instead.
 194          */
 195         bool            forces_persample_interp_for_persp;
 196         bool            forces_persample_interp_for_linear;
 197
 198         unsigned        gs_output_prim;
 199         unsigned        gs_max_out_vertices;
 200         unsigned        gs_num_invocations;
 201         unsigned        gsvs_itemsize;
 202
 203         /* masks of "get_unique_index" bits */
 204         uint64_t        inputs_read;
 205         uint64_t        outputs_written;
 206         uint32_t        patch_outputs_written;
 207         uint32_t        ps_colors_written;
 208 };
 209
 210 /* Valid shader configurations:
 211  *
 212  * API shaders       VS | TCS | TES | GS |pass| PS
 213  * are compiled as:     |     |     |    |thru|
 214  *                      |     |     |    |    |
 215  * Only VS & PS:     VS | --  | --  | -- | -- | PS
 216  * With GS:          ES | --  | --  | GS | VS | PS
 217  * With Tessel.:     LS | HS  | VS  | -- | -- | PS
 218  * With both:        LS | HS  | ES  | GS | VS | PS
 219  */
 220
 221 union si_shader_key {
 222         struct {
 223                 unsigned        export_16bpc:8;
 224                 unsigned        last_cbuf:3;
 225                 unsigned        color_two_side:1;
 226                 unsigned        alpha_func:3;
 227                 unsigned        alpha_to_one:1;
 228                 unsigned        poly_stipple:1;
 229                 unsigned        poly_line_smoothing:1;
 230                 unsigned        clamp_color:1;
 231         } ps;
 232         struct {
 233                 unsigned        instance_divisors[SI_NUM_VERTEX_BUFFERS];
 234                 /* Mask of "get_unique_index" bits - which outputs are read
 235                  * by the next stage (needed by ES).
 236                  * This describes how outputs are laid out in memory. */
 237                 uint64_t        es_enabled_outputs;
 238                 unsigned        as_es:1; /* export shader */
 239                 unsigned        as_ls:1; /* local shader */
 240                 unsigned        export_prim_id; /* when PS needs it and GS is disabled */
 241         } vs;
 242         struct {
 243                 unsigned        prim_mode:3;
 244         } tcs; /* tessellation control shader */
 245         struct {
 246                 /* Mask of "get_unique_index" bits - which outputs are read
 247                  * by the next stage (needed by ES).
 248                  * This describes how outputs are laid out in memory. */
 249                 uint64_t        es_enabled_outputs;
 250                 unsigned        as_es:1; /* export shader */
 251                 unsigned        export_prim_id; /* when PS needs it and GS is disabled */
 252         } tes; /* tessellation evaluation shader */
 253 };
 254
 255 struct si_shader {
 256         struct si_shader_selector       *selector;
 257         struct si_shader                *next_variant;
 258
 259         struct si_shader                *gs_copy_shader;
 260         struct si_pm4_state             *pm4;
 261         struct r600_resource            *bo;
 262         struct r600_resource            *scratch_bo;
 263         struct radeon_shader_binary     binary;
 264         unsigned                        num_sgprs;
 265         unsigned                        num_vgprs;
 266         unsigned                        lds_size;
 267         unsigned                        spi_ps_input_ena;
 268         unsigned                        float_mode;
 269         unsigned                        scratch_bytes_per_wave;
 270         unsigned                        spi_shader_col_format;
 271         unsigned                        spi_shader_z_format;
 272         unsigned                        db_shader_control;
 273         unsigned                        cb_shader_mask;
 274         union si_shader_key             key;
 275
 276         unsigned                nparam;
 277         unsigned                vs_output_param_offset[PIPE_MAX_SHADER_OUTPUTS];
 278         unsigned                ps_input_param_offset[PIPE_MAX_SHADER_INPUTS];
 279         unsigned                ps_input_interpolate[PIPE_MAX_SHADER_INPUTS];
 280         bool                    uses_instanceid;
 281         unsigned                nr_pos_exports;
 282         unsigned                nr_param_exports;
 283         bool                    is_gs_copy_shader;
 284         bool                    dx10_clamp_mode; /* convert NaNs to 0 */
 285
 286         unsigned                ls_rsrc1;
 287         unsigned                ls_rsrc2;
 288 };
 289
 290 static inline struct tgsi_shader_info *si_get_vs_info(struct si_context *sctx)
 291 {
 292         if (sctx->gs_shader)
 293                 return &sctx->gs_shader->info;
 294         else if (sctx->tes_shader)
 295                 return &sctx->tes_shader->info;
 296         else if (sctx->vs_shader)
 297                 return &sctx->vs_shader->info;
 298         else
 299                 return NULL;
 300 }
 301
 302 static inline struct si_shader* si_get_vs_state(struct si_context *sctx)
 303 {
 304         if (sctx->gs_shader)
 305                 return sctx->gs_shader->current->gs_copy_shader;
 306         else if (sctx->tes_shader)
 307                 return sctx->tes_shader->current;
 308         else
 309                 return sctx->vs_shader->current;
 310 }
 311
 312 static inline bool si_vs_exports_prim_id(struct si_shader *shader)
 313 {
 314         if (shader->selector->type == PIPE_SHADER_VERTEX)
 315                 return shader->key.vs.export_prim_id;
 316         else if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
 317                 return shader->key.tes.export_prim_id;
 318         else
 319                 return false;
 320 }
 321
 322 /* radeonsi_shader.c */
 323 int si_shader_create(struct si_screen *sscreen, LLVMTargetMachineRef tm,
 324                      struct si_shader *shader);
 325 void si_dump_shader_key(unsigned shader, union si_shader_key *key, FILE *f);
 326 int si_compile_llvm(struct si_screen *sscreen, struct si_shader *shader,
 327                     LLVMTargetMachineRef tm, LLVMModuleRef mod);
 328 void si_shader_destroy(struct si_shader *shader);
 329 unsigned si_shader_io_get_unique_index(unsigned semantic_name, unsigned index);
 330 int si_shader_binary_upload(struct si_screen *sscreen, struct si_shader *shader);
 331 int si_shader_binary_read(struct si_screen *sscreen, struct si_shader *shader);
 332 void si_shader_apply_scratch_relocs(struct si_context *sctx,
 333                         struct si_shader *shader,
 334                         uint64_t scratch_va);
 335 void si_shader_binary_read_config(const struct si_screen *sscreen,
 336                                 struct si_shader *shader,
 337                                 unsigned symbol_offset);
 338
 339 #endif