src/gallium/drivers/radeonsi/si_shader.h

   1 /*
   2  * Copyright 2012 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Tom Stellard <thomas.stellard@amd.com>
  25  *      Michel Dänzer <michel.daenzer@amd.com>
  26  *      Christian König <christian.koenig@amd.com>
  27  */
  28
  29 /* How linking shader inputs and outputs between vertex, tessellation, and
  30  * geometry shaders works.
  31  *
  32  * Inputs and outputs between shaders are stored in a buffer. This buffer
  33  * lives in LDS (typical case for tessellation), but it can also live
  34  * in memory (ESGS). Each input or output has a fixed location within a vertex.
  35  * The highest used input or output determines the stride between vertices.
  36  *
  37  * Since GS and tessellation are only possible in the OpenGL core profile,
  38  * only these semantics are valid for per-vertex data:
  39  *
  40  *   Name             Location
  41  *
  42  *   POSITION         0
  43  *   PSIZE            1
  44  *   CLIPDIST0..1     2..3
  45  *   CULLDIST0..1     (not implemented)
  46  *   GENERIC0..31     4..35
  47  *
  48  * For example, a shader only writing GENERIC0 has the output stride of 5.
  49  *
  50  * Only these semantics are valid for per-patch data:
  51  *
  52  *   Name             Location
  53  *
  54  *   TESSOUTER        0
  55  *   TESSINNER        1
  56  *   PATCH0..29       2..31
  57  *
  58  * That's how independent shaders agree on input and output locations.
  59  * The si_shader_io_get_unique_index function assigns the locations.
  60  *
  61  * For tessellation, other required information for calculating the input and
  62  * output addresses like the vertex stride, the patch stride, and the offsets
  63  * where per-vertex and per-patch data start, is passed to the shader via
  64  * user data SGPRs. The offsets and strides are calculated at draw time and
  65  * aren't available at compile time.
  66  */
  67
  68 #ifndef SI_SHADER_H
  69 #define SI_SHADER_H
  70
  71 #include <llvm-c/Core.h> /* LLVMModuleRef */
  72 #include "tgsi/tgsi_scan.h"
  73 #include "si_state.h"
  74
  75 struct radeon_shader_binary;
  76 struct radeon_shader_reloc;
  77
  78 #define SI_SGPR_RW_BUFFERS      0  /* rings (& stream-out, VS only) */
  79 #define SI_SGPR_CONST_BUFFERS   2
  80 #define SI_SGPR_SAMPLER_STATES  4
  81 #define SI_SGPR_SAMPLER_VIEWS   6
  82 #define SI_SGPR_VERTEX_BUFFERS  8  /* VS only */
  83 #define SI_SGPR_BASE_VERTEX     10 /* VS only */
  84 #define SI_SGPR_START_INSTANCE  11 /* VS only */
  85 #define SI_SGPR_VS_STATE_BITS   12 /* VS(VS) only */
  86 #define SI_SGPR_LS_OUT_LAYOUT   12 /* VS(LS) only */
  87 #define SI_SGPR_TCS_OUT_OFFSETS 8  /* TCS & TES only */
  88 #define SI_SGPR_TCS_OUT_LAYOUT  9  /* TCS & TES only */
  89 #define SI_SGPR_TCS_IN_LAYOUT   10 /* TCS only */
  90 #define SI_SGPR_ALPHA_REF       8  /* PS only */
  91 #define SI_SGPR_PS_STATE_BITS   9  /* PS only */
  92
  93 #define SI_VS_NUM_USER_SGPR     13 /* API VS */
  94 #define SI_ES_NUM_USER_SGPR     12 /* API VS */
  95 #define SI_LS_NUM_USER_SGPR     13 /* API VS */
  96 #define SI_TCS_NUM_USER_SGPR    11
  97 #define SI_TES_NUM_USER_SGPR    10
  98 #define SI_GS_NUM_USER_SGPR     8
  99 #define SI_GSCOPY_NUM_USER_SGPR 4
 100 #define SI_PS_NUM_USER_SGPR     10
 101
 102 /* LLVM function parameter indices */
 103 #define SI_PARAM_RW_BUFFERS     0
 104 #define SI_PARAM_CONST_BUFFERS  1
 105 #define SI_PARAM_SAMPLER_STATES 2
 106 #define SI_PARAM_SAMPLER_VIEWS  3
 107
 108 /* VS only parameters */
 109 #define SI_PARAM_VERTEX_BUFFERS 4
 110 #define SI_PARAM_BASE_VERTEX    5
 111 #define SI_PARAM_START_INSTANCE 6
 112 /* [0] = clamp vertex color */
 113 #define SI_PARAM_VS_STATE_BITS  7
 114 /* the other VS parameters are assigned dynamically */
 115
 116 /* Offsets where TCS outputs and TCS patch outputs live in LDS:
 117  *   [0:15] = TCS output patch0 offset / 16, max = NUM_PATCHES * 32 * 32
 118  *   [16:31] = TCS output patch0 offset for per-patch / 16, max = NUM_PATCHES*32*32* + 32*32
 119  */
 120 #define SI_PARAM_TCS_OUT_OFFSETS 4 /* for TCS & TES */
 121
 122 /* Layout of TCS outputs / TES inputs:
 123  *   [0:12] = stride between output patches in dwords, num_outputs * num_vertices * 4, max = 32*32*4
 124  *   [13:20] = stride between output vertices in dwords = num_inputs * 4, max = 32*4
 125  *   [26:31] = gl_PatchVerticesIn, max = 32
 126  */
 127 #define SI_PARAM_TCS_OUT_LAYOUT 5 /* for TCS & TES */
 128
 129 /* Layout of LS outputs / TCS inputs
 130  *   [0:12] = stride between patches in dwords = num_inputs * num_vertices * 4, max = 32*32*4
 131  *   [13:20] = stride between vertices in dwords = num_inputs * 4, max = 32*4
 132  */
 133 #define SI_PARAM_TCS_IN_LAYOUT  6 /* TCS only */
 134 #define SI_PARAM_LS_OUT_LAYOUT  7 /* same value as TCS_IN_LAYOUT, LS only */
 135
 136 /* TCS only parameters. */
 137 #define SI_PARAM_TESS_FACTOR_OFFSET 7
 138 #define SI_PARAM_PATCH_ID       8
 139 #define SI_PARAM_REL_IDS        9
 140
 141 /* GS only parameters */
 142 #define SI_PARAM_GS2VS_OFFSET   4
 143 #define SI_PARAM_GS_WAVE_ID     5
 144 #define SI_PARAM_VTX0_OFFSET    6
 145 #define SI_PARAM_VTX1_OFFSET    7
 146 #define SI_PARAM_PRIMITIVE_ID   8
 147 #define SI_PARAM_VTX2_OFFSET    9
 148 #define SI_PARAM_VTX3_OFFSET    10
 149 #define SI_PARAM_VTX4_OFFSET    11
 150 #define SI_PARAM_VTX5_OFFSET    12
 151 #define SI_PARAM_GS_INSTANCE_ID 13
 152
 153 /* PS only parameters */
 154 #define SI_PARAM_ALPHA_REF              4
 155 /* Bits:
 156  * 0: force_persample_interp
 157  */
 158 #define SI_PARAM_PS_STATE_BITS          5
 159 #define SI_PARAM_PRIM_MASK              6
 160 #define SI_PARAM_PERSP_SAMPLE           7
 161 #define SI_PARAM_PERSP_CENTER           8
 162 #define SI_PARAM_PERSP_CENTROID         9
 163 #define SI_PARAM_PERSP_PULL_MODEL       10
 164 #define SI_PARAM_LINEAR_SAMPLE          11
 165 #define SI_PARAM_LINEAR_CENTER          12
 166 #define SI_PARAM_LINEAR_CENTROID        13
 167 #define SI_PARAM_LINE_STIPPLE_TEX       14
 168 #define SI_PARAM_POS_X_FLOAT            15
 169 #define SI_PARAM_POS_Y_FLOAT            16
 170 #define SI_PARAM_POS_Z_FLOAT            17
 171 #define SI_PARAM_POS_W_FLOAT            18
 172 #define SI_PARAM_FRONT_FACE             19
 173 #define SI_PARAM_ANCILLARY              20
 174 #define SI_PARAM_SAMPLE_COVERAGE        21
 175 #define SI_PARAM_POS_FIXED_PT           22
 176
 177 #define SI_NUM_PARAMS (SI_PARAM_POS_FIXED_PT + 1)
 178
 179 struct si_shader;
 180
 181 /* A shader selector is a gallium CSO and contains shader variants and
 182  * binaries for one TGSI program. This can be shared by multiple contexts.
 183  */
 184 struct si_shader_selector {
 185         pipe_mutex              mutex;
 186         struct si_shader        *first_variant; /* immutable after the first variant */
 187         struct si_shader        *last_variant; /* mutable */
 188
 189         struct tgsi_token       *tokens;
 190         struct pipe_stream_output_info  so;
 191         struct tgsi_shader_info         info;
 192
 193         /* PIPE_SHADER_[VERTEX|FRAGMENT|...] */
 194         unsigned        type;
 195
 196         /* Whether the shader has to use a conditional assignment to
 197          * choose between weights when emulating
 198          * pipe_rasterizer_state::force_persample_interp.
 199          * If false, "si_emit_spi_ps_input" will take care of it instead.
 200          */
 201         bool            forces_persample_interp_for_persp;
 202         bool            forces_persample_interp_for_linear;
 203
 204         /* GS parameters. */
 205         unsigned        esgs_itemsize;
 206         unsigned        gs_input_verts_per_prim;
 207         unsigned        gs_output_prim;
 208         unsigned        gs_max_out_vertices;
 209         unsigned        gs_num_invocations;
 210         unsigned        max_gs_stream; /* count - 1 */
 211         unsigned        gsvs_vertex_size;
 212         unsigned        max_gsvs_emit_size;
 213
 214         /* PS parameters. */
 215         unsigned        db_shader_control;
 216
 217         /* masks of "get_unique_index" bits */
 218         uint64_t        outputs_written;
 219         uint32_t        patch_outputs_written;
 220 };
 221
 222 /* Valid shader configurations:
 223  *
 224  * API shaders       VS | TCS | TES | GS |pass| PS
 225  * are compiled as:     |     |     |    |thru|
 226  *                      |     |     |    |    |
 227  * Only VS & PS:     VS | --  | --  | -- | -- | PS
 228  * With GS:          ES | --  | --  | GS | VS | PS
 229  * With Tessel.:     LS | HS  | VS  | -- | -- | PS
 230  * With both:        LS | HS  | ES  | GS | VS | PS
 231  */
 232
 233 union si_shader_key {
 234         struct {
 235                 unsigned        export_16bpc:8;
 236                 unsigned        last_cbuf:3;
 237                 unsigned        color_two_side:1;
 238                 unsigned        alpha_func:3;
 239                 unsigned        alpha_to_one:1;
 240                 unsigned        poly_stipple:1;
 241                 unsigned        poly_line_smoothing:1;
 242                 unsigned        clamp_color:1;
 243         } ps;
 244         struct {
 245                 unsigned        instance_divisors[SI_NUM_VERTEX_BUFFERS];
 246                 /* Mask of "get_unique_index" bits - which outputs are read
 247                  * by the next stage (needed by ES).
 248                  * This describes how outputs are laid out in memory. */
 249                 unsigned        as_es:1; /* export shader */
 250                 unsigned        as_ls:1; /* local shader */
 251                 unsigned        export_prim_id:1; /* when PS needs it and GS is disabled */
 252         } vs;
 253         struct {
 254                 unsigned        prim_mode:3;
 255         } tcs; /* tessellation control shader */
 256         struct {
 257                 /* Mask of "get_unique_index" bits - which outputs are read
 258                  * by the next stage (needed by ES).
 259                  * This describes how outputs are laid out in memory. */
 260                 unsigned        as_es:1; /* export shader */
 261                 unsigned        export_prim_id:1; /* when PS needs it and GS is disabled */
 262         } tes; /* tessellation evaluation shader */
 263 };
 264
 265 struct si_shader {
 266         struct si_shader_selector       *selector;
 267         struct si_shader                *next_variant;
 268
 269         struct si_shader                *gs_copy_shader;
 270         struct si_pm4_state             *pm4;
 271         struct r600_resource            *bo;
 272         struct r600_resource            *scratch_bo;
 273         struct radeon_shader_binary     binary;
 274         unsigned                        num_sgprs;
 275         unsigned                        num_vgprs;
 276         unsigned                        lds_size;
 277         unsigned                        spi_ps_input_ena;
 278         unsigned                        float_mode;
 279         unsigned                        scratch_bytes_per_wave;
 280         unsigned                        spi_shader_col_format;
 281         unsigned                        spi_shader_z_format;
 282         unsigned                        cb_shader_mask;
 283         union si_shader_key             key;
 284
 285         unsigned                nparam;
 286         unsigned                vs_output_param_offset[PIPE_MAX_SHADER_OUTPUTS];
 287         unsigned                ps_input_param_offset[PIPE_MAX_SHADER_INPUTS];
 288         unsigned                ps_input_interpolate[PIPE_MAX_SHADER_INPUTS];
 289         bool                    uses_instanceid;
 290         unsigned                nr_pos_exports;
 291         unsigned                nr_param_exports;
 292         bool                    is_gs_copy_shader;
 293         bool                    dx10_clamp_mode; /* convert NaNs to 0 */
 294
 295         unsigned                rsrc1;
 296         unsigned                rsrc2;
 297 };
 298
 299 static inline struct tgsi_shader_info *si_get_vs_info(struct si_context *sctx)
 300 {
 301         if (sctx->gs_shader.cso)
 302                 return &sctx->gs_shader.cso->info;
 303         else if (sctx->tes_shader.cso)
 304                 return &sctx->tes_shader.cso->info;
 305         else if (sctx->vs_shader.cso)
 306                 return &sctx->vs_shader.cso->info;
 307         else
 308                 return NULL;
 309 }
 310
 311 static inline struct si_shader* si_get_vs_state(struct si_context *sctx)
 312 {
 313         if (sctx->gs_shader.current)
 314                 return sctx->gs_shader.current->gs_copy_shader;
 315         else if (sctx->tes_shader.current)
 316                 return sctx->tes_shader.current;
 317         else
 318                 return sctx->vs_shader.current;
 319 }
 320
 321 static inline bool si_vs_exports_prim_id(struct si_shader *shader)
 322 {
 323         if (shader->selector->type == PIPE_SHADER_VERTEX)
 324                 return shader->key.vs.export_prim_id;
 325         else if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
 326                 return shader->key.tes.export_prim_id;
 327         else
 328                 return false;
 329 }
 330
 331 /* radeonsi_shader.c */
 332 int si_shader_create(struct si_screen *sscreen, LLVMTargetMachineRef tm,
 333                      struct si_shader *shader,
 334                      struct pipe_debug_callback *debug);
 335 void si_dump_shader_key(unsigned shader, union si_shader_key *key, FILE *f);
 336 int si_compile_llvm(struct si_screen *sscreen, struct si_shader *shader,
 337                     LLVMTargetMachineRef tm, LLVMModuleRef mod,
 338                     struct pipe_debug_callback *debug, unsigned processor);
 339 void si_shader_destroy(struct si_shader *shader);
 340 unsigned si_shader_io_get_unique_index(unsigned semantic_name, unsigned index);
 341 int si_shader_binary_upload(struct si_screen *sscreen, struct si_shader *shader);
 342 void si_shader_binary_read(struct si_screen *sscreen, struct si_shader *shader,
 343                            struct pipe_debug_callback *debug, unsigned processor);
 344 void si_shader_apply_scratch_relocs(struct si_context *sctx,
 345                         struct si_shader *shader,
 346                         uint64_t scratch_va);
 347 void si_shader_binary_read_config(struct si_shader *shader,
 348                                   unsigned symbol_offset);
 349
 350 #endif