src/gallium/drivers/radeonsi/si_shader.h

   1 /*
   2  * Copyright 2012 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Tom Stellard <thomas.stellard@amd.com>
  25  *      Michel Dänzer <michel.daenzer@amd.com>
  26  *      Christian König <christian.koenig@amd.com>
  27  */
  28
  29 /* How linking shader inputs and outputs between vertex, tessellation, and
  30  * geometry shaders works.
  31  *
  32  * Inputs and outputs between shaders are stored in a buffer. This buffer
  33  * lives in LDS (typical case for tessellation), but it can also live
  34  * in memory (ESGS). Each input or output has a fixed location within a vertex.
  35  * The highest used input or output determines the stride between vertices.
  36  *
  37  * Since GS and tessellation are only possible in the OpenGL core profile,
  38  * only these semantics are valid for per-vertex data:
  39  *
  40  *   Name             Location
  41  *
  42  *   POSITION         0
  43  *   PSIZE            1
  44  *   CLIPDIST0..1     2..3
  45  *   CULLDIST0..1     (not implemented)
  46  *   GENERIC0..31     4..35
  47  *
  48  * For example, a shader only writing GENERIC0 has the output stride of 5.
  49  *
  50  * Only these semantics are valid for per-patch data:
  51  *
  52  *   Name             Location
  53  *
  54  *   TESSOUTER        0
  55  *   TESSINNER        1
  56  *   PATCH0..29       2..31
  57  *
  58  * That's how independent shaders agree on input and output locations.
  59  * The si_shader_io_get_unique_index function assigns the locations.
  60  *
  61  * For tessellation, other required information for calculating the input and
  62  * output addresses like the vertex stride, the patch stride, and the offsets
  63  * where per-vertex and per-patch data start, is passed to the shader via
  64  * user data SGPRs. The offsets and strides are calculated at draw time and
  65  * aren't available at compile time.
  66  */
  67
  68 #ifndef SI_SHADER_H
  69 #define SI_SHADER_H
  70
  71 #include <llvm-c/Core.h> /* LLVMModuleRef */
  72 #include "tgsi/tgsi_scan.h"
  73 #include "si_state.h"
  74
  75 struct radeon_shader_binary;
  76 struct radeon_shader_reloc;
  77
  78 #define SI_SGPR_RW_BUFFERS      0  /* rings (& stream-out, VS only) */
  79 #define SI_SGPR_CONST_BUFFERS   2
  80 #define SI_SGPR_SAMPLERS        4  /* images & sampler states interleaved */
  81 /* TODO: gap */
  82 #define SI_SGPR_VERTEX_BUFFERS  8  /* VS only */
  83 #define SI_SGPR_BASE_VERTEX     10 /* VS only */
  84 #define SI_SGPR_START_INSTANCE  11 /* VS only */
  85 #define SI_SGPR_VS_STATE_BITS   12 /* VS(VS) only */
  86 #define SI_SGPR_LS_OUT_LAYOUT   12 /* VS(LS) only */
  87 #define SI_SGPR_TCS_OUT_OFFSETS 8  /* TCS & TES only */
  88 #define SI_SGPR_TCS_OUT_LAYOUT  9  /* TCS & TES only */
  89 #define SI_SGPR_TCS_IN_LAYOUT   10 /* TCS only */
  90 #define SI_SGPR_ALPHA_REF       8  /* PS only */
  91
  92 #define SI_VS_NUM_USER_SGPR     13 /* API VS */
  93 #define SI_ES_NUM_USER_SGPR     12 /* API VS */
  94 #define SI_LS_NUM_USER_SGPR     13 /* API VS */
  95 #define SI_TCS_NUM_USER_SGPR    11
  96 #define SI_TES_NUM_USER_SGPR    10
  97 #define SI_GS_NUM_USER_SGPR     8
  98 #define SI_GSCOPY_NUM_USER_SGPR 4
  99 #define SI_PS_NUM_USER_SGPR     9
 100
 101 /* LLVM function parameter indices */
 102 #define SI_PARAM_RW_BUFFERS     0
 103 #define SI_PARAM_CONST_BUFFERS  1
 104 #define SI_PARAM_SAMPLERS       2
 105 #define SI_PARAM_UNUSED         3 /* TODO: use */
 106
 107 /* VS only parameters */
 108 #define SI_PARAM_VERTEX_BUFFERS 4
 109 #define SI_PARAM_BASE_VERTEX    5
 110 #define SI_PARAM_START_INSTANCE 6
 111 /* [0] = clamp vertex color */
 112 #define SI_PARAM_VS_STATE_BITS  7
 113 /* the other VS parameters are assigned dynamically */
 114
 115 /* Offsets where TCS outputs and TCS patch outputs live in LDS:
 116  *   [0:15] = TCS output patch0 offset / 16, max = NUM_PATCHES * 32 * 32
 117  *   [16:31] = TCS output patch0 offset for per-patch / 16, max = NUM_PATCHES*32*32* + 32*32
 118  */
 119 #define SI_PARAM_TCS_OUT_OFFSETS 4 /* for TCS & TES */
 120
 121 /* Layout of TCS outputs / TES inputs:
 122  *   [0:12] = stride between output patches in dwords, num_outputs * num_vertices * 4, max = 32*32*4
 123  *   [13:20] = stride between output vertices in dwords = num_inputs * 4, max = 32*4
 124  *   [26:31] = gl_PatchVerticesIn, max = 32
 125  */
 126 #define SI_PARAM_TCS_OUT_LAYOUT 5 /* for TCS & TES */
 127
 128 /* Layout of LS outputs / TCS inputs
 129  *   [0:12] = stride between patches in dwords = num_inputs * num_vertices * 4, max = 32*32*4
 130  *   [13:20] = stride between vertices in dwords = num_inputs * 4, max = 32*4
 131  */
 132 #define SI_PARAM_TCS_IN_LAYOUT  6 /* TCS only */
 133 #define SI_PARAM_LS_OUT_LAYOUT  7 /* same value as TCS_IN_LAYOUT, LS only */
 134
 135 /* TCS only parameters. */
 136 #define SI_PARAM_TESS_FACTOR_OFFSET 7
 137 #define SI_PARAM_PATCH_ID       8
 138 #define SI_PARAM_REL_IDS        9
 139
 140 /* GS only parameters */
 141 #define SI_PARAM_GS2VS_OFFSET   4
 142 #define SI_PARAM_GS_WAVE_ID     5
 143 #define SI_PARAM_VTX0_OFFSET    6
 144 #define SI_PARAM_VTX1_OFFSET    7
 145 #define SI_PARAM_PRIMITIVE_ID   8
 146 #define SI_PARAM_VTX2_OFFSET    9
 147 #define SI_PARAM_VTX3_OFFSET    10
 148 #define SI_PARAM_VTX4_OFFSET    11
 149 #define SI_PARAM_VTX5_OFFSET    12
 150 #define SI_PARAM_GS_INSTANCE_ID 13
 151
 152 /* PS only parameters */
 153 #define SI_PARAM_ALPHA_REF              4
 154 #define SI_PARAM_PRIM_MASK              5
 155 #define SI_PARAM_PERSP_SAMPLE           6
 156 #define SI_PARAM_PERSP_CENTER           7
 157 #define SI_PARAM_PERSP_CENTROID         8
 158 #define SI_PARAM_PERSP_PULL_MODEL       9
 159 #define SI_PARAM_LINEAR_SAMPLE          10
 160 #define SI_PARAM_LINEAR_CENTER          11
 161 #define SI_PARAM_LINEAR_CENTROID        12
 162 #define SI_PARAM_LINE_STIPPLE_TEX       13
 163 #define SI_PARAM_POS_X_FLOAT            14
 164 #define SI_PARAM_POS_Y_FLOAT            15
 165 #define SI_PARAM_POS_Z_FLOAT            16
 166 #define SI_PARAM_POS_W_FLOAT            17
 167 #define SI_PARAM_FRONT_FACE             18
 168 #define SI_PARAM_ANCILLARY              19
 169 #define SI_PARAM_SAMPLE_COVERAGE        20
 170 #define SI_PARAM_POS_FIXED_PT           21
 171
 172 #define SI_NUM_PARAMS (SI_PARAM_POS_FIXED_PT + 9) /* +8 for COLOR[0..1] */
 173
 174 struct si_shader;
 175
 176 /* A shader selector is a gallium CSO and contains shader variants and
 177  * binaries for one TGSI program. This can be shared by multiple contexts.
 178  */
 179 struct si_shader_selector {
 180         pipe_mutex              mutex;
 181         struct si_shader        *first_variant; /* immutable after the first variant */
 182         struct si_shader        *last_variant; /* mutable */
 183
 184         /* The compiled TGSI shader expecting a prolog and/or epilog (not
 185          * uploaded to a buffer).
 186          */
 187         struct si_shader        *main_shader_part;
 188
 189         struct tgsi_token       *tokens;
 190         struct pipe_stream_output_info  so;
 191         struct tgsi_shader_info         info;
 192
 193         /* PIPE_SHADER_[VERTEX|FRAGMENT|...] */
 194         unsigned        type;
 195
 196         /* GS parameters. */
 197         unsigned        esgs_itemsize;
 198         unsigned        gs_input_verts_per_prim;
 199         unsigned        gs_output_prim;
 200         unsigned        gs_max_out_vertices;
 201         unsigned        gs_num_invocations;
 202         unsigned        max_gs_stream; /* count - 1 */
 203         unsigned        gsvs_vertex_size;
 204         unsigned        max_gsvs_emit_size;
 205
 206         /* PS parameters. */
 207         unsigned        color_attr_index[2];
 208         unsigned        db_shader_control;
 209         /* Set 0xf or 0x0 (4 bits) per each written output.
 210          * ANDed with spi_shader_col_format.
 211          */
 212         unsigned        colors_written_4bit;
 213
 214         /* masks of "get_unique_index" bits */
 215         uint64_t        outputs_written;
 216         uint32_t        patch_outputs_written;
 217 };
 218
 219 /* Valid shader configurations:
 220  *
 221  * API shaders       VS | TCS | TES | GS |pass| PS
 222  * are compiled as:     |     |     |    |thru|
 223  *                      |     |     |    |    |
 224  * Only VS & PS:     VS | --  | --  | -- | -- | PS
 225  * With GS:          ES | --  | --  | GS | VS | PS
 226  * With Tessel.:     LS | HS  | VS  | -- | -- | PS
 227  * With both:        LS | HS  | ES  | GS | VS | PS
 228  */
 229
 230 /* Common VS bits between the shader key and the prolog key. */
 231 struct si_vs_prolog_bits {
 232         unsigned        instance_divisors[SI_NUM_VERTEX_BUFFERS];
 233 };
 234
 235 /* Common VS bits between the shader key and the epilog key. */
 236 struct si_vs_epilog_bits {
 237         unsigned        export_prim_id:1; /* when PS needs it and GS is disabled */
 238         /* TODO:
 239          * - skip clipdist, culldist (including clipvertex code) exports based
 240          *   on which clip_plane_enable bits are set
 241          * - skip layer, viewport, clipdist, and culldist parameter exports
 242          *   if PS doesn't read them
 243          */
 244 };
 245
 246 /* Common TCS bits between the shader key and the epilog key. */
 247 struct si_tcs_epilog_bits {
 248         unsigned        prim_mode:3;
 249 };
 250
 251 /* Common PS bits between the shader key and the prolog key. */
 252 struct si_ps_prolog_bits {
 253         unsigned        color_two_side:1;
 254         /* TODO: add a flatshade bit that skips interpolation for colors */
 255         unsigned        poly_stipple:1;
 256         unsigned        force_persample_interp:1;
 257         /* TODO:
 258          * - add force_center_interp if MSAA is disabled and centroid or
 259          *   sample are present
 260          * - add force_center_interp_bc_optimize to force center interpolation
 261          *   based on the bc_optimize SGPR bit if MSAA is enabled, centroid is
 262          *   present and sample isn't present.
 263          */
 264 };
 265
 266 /* Common PS bits between the shader key and the epilog key. */
 267 struct si_ps_epilog_bits {
 268         unsigned        spi_shader_col_format;
 269         unsigned        color_is_int8:8;
 270         unsigned        last_cbuf:3;
 271         unsigned        alpha_func:3;
 272         unsigned        alpha_to_one:1;
 273         unsigned        poly_line_smoothing:1;
 274         unsigned        clamp_color:1;
 275 };
 276
 277 union si_shader_part_key {
 278         struct {
 279                 struct si_vs_prolog_bits states;
 280                 unsigned        num_input_sgprs:5;
 281                 unsigned        last_input:4;
 282         } vs_prolog;
 283         struct {
 284                 struct si_vs_epilog_bits states;
 285                 unsigned        prim_id_param_offset:5;
 286         } vs_epilog;
 287         struct {
 288                 struct si_tcs_epilog_bits states;
 289         } tcs_epilog;
 290         struct {
 291                 struct si_ps_prolog_bits states;
 292                 unsigned        num_input_sgprs:5;
 293                 unsigned        num_input_vgprs:5;
 294                 /* Color interpolation and two-side color selection. */
 295                 unsigned        colors_read:8; /* color input components read */
 296                 unsigned        num_interp_inputs:5; /* BCOLOR is at this location */
 297                 unsigned        face_vgpr_index:5;
 298                 char            color_attr_index[2];
 299                 char            color_interp_vgpr_index[2]; /* -1 == constant */
 300         } ps_prolog;
 301         struct {
 302                 struct si_ps_epilog_bits states;
 303                 unsigned        colors_written:8;
 304                 unsigned        writes_z:1;
 305                 unsigned        writes_stencil:1;
 306                 unsigned        writes_samplemask:1;
 307         } ps_epilog;
 308 };
 309
 310 union si_shader_key {
 311         struct {
 312                 struct si_ps_prolog_bits prolog;
 313                 struct si_ps_epilog_bits epilog;
 314         } ps;
 315         struct {
 316                 struct si_vs_prolog_bits prolog;
 317                 struct si_vs_epilog_bits epilog;
 318                 unsigned        as_es:1; /* export shader */
 319                 unsigned        as_ls:1; /* local shader */
 320         } vs;
 321         struct {
 322                 struct si_tcs_epilog_bits epilog;
 323         } tcs; /* tessellation control shader */
 324         struct {
 325                 struct si_vs_epilog_bits epilog; /* same as VS */
 326                 unsigned        as_es:1; /* export shader */
 327         } tes; /* tessellation evaluation shader */
 328 };
 329
 330 struct si_shader_config {
 331         unsigned                        num_sgprs;
 332         unsigned                        num_vgprs;
 333         unsigned                        lds_size;
 334         unsigned                        spi_ps_input_ena;
 335         unsigned                        spi_ps_input_addr;
 336         unsigned                        float_mode;
 337         unsigned                        scratch_bytes_per_wave;
 338         unsigned                        rsrc1;
 339         unsigned                        rsrc2;
 340 };
 341
 342 struct si_shader {
 343         struct si_shader_selector       *selector;
 344         struct si_shader                *next_variant;
 345
 346         struct si_shader_part           *prolog;
 347         struct si_shader_part           *epilog;
 348
 349         struct si_shader                *gs_copy_shader;
 350         struct si_pm4_state             *pm4;
 351         struct r600_resource            *bo;
 352         struct r600_resource            *scratch_bo;
 353         union si_shader_key             key;
 354         struct radeon_shader_binary     binary;
 355         bool                            is_binary_shared;
 356         struct si_shader_config         config;
 357
 358         ubyte                   num_input_sgprs;
 359         ubyte                   num_input_vgprs;
 360         char                    face_vgpr_index;
 361
 362         unsigned                vs_output_param_offset[PIPE_MAX_SHADER_OUTPUTS];
 363         bool                    uses_instanceid;
 364         unsigned                nr_pos_exports;
 365         unsigned                nr_param_exports;
 366 };
 367
 368 struct si_shader_part {
 369         struct si_shader_part *next;
 370         union si_shader_part_key key;
 371         struct radeon_shader_binary binary;
 372         struct si_shader_config config;
 373 };
 374
 375 static inline struct tgsi_shader_info *si_get_vs_info(struct si_context *sctx)
 376 {
 377         if (sctx->gs_shader.cso)
 378                 return &sctx->gs_shader.cso->info;
 379         else if (sctx->tes_shader.cso)
 380                 return &sctx->tes_shader.cso->info;
 381         else if (sctx->vs_shader.cso)
 382                 return &sctx->vs_shader.cso->info;
 383         else
 384                 return NULL;
 385 }
 386
 387 static inline struct si_shader* si_get_vs_state(struct si_context *sctx)
 388 {
 389         if (sctx->gs_shader.current)
 390                 return sctx->gs_shader.current->gs_copy_shader;
 391         else if (sctx->tes_shader.current)
 392                 return sctx->tes_shader.current;
 393         else
 394                 return sctx->vs_shader.current;
 395 }
 396
 397 static inline bool si_vs_exports_prim_id(struct si_shader *shader)
 398 {
 399         if (shader->selector->type == PIPE_SHADER_VERTEX)
 400                 return shader->key.vs.epilog.export_prim_id;
 401         else if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
 402                 return shader->key.tes.epilog.export_prim_id;
 403         else
 404                 return false;
 405 }
 406
 407 /* si_shader.c */
 408 int si_compile_tgsi_shader(struct si_screen *sscreen,
 409                            LLVMTargetMachineRef tm,
 410                            struct si_shader *shader,
 411                            bool is_monolithic,
 412                            struct pipe_debug_callback *debug);
 413 int si_shader_create(struct si_screen *sscreen, LLVMTargetMachineRef tm,
 414                      struct si_shader *shader,
 415                      struct pipe_debug_callback *debug);
 416 void si_dump_shader_key(unsigned shader, union si_shader_key *key, FILE *f);
 417 int si_compile_llvm(struct si_screen *sscreen,
 418                     struct radeon_shader_binary *binary,
 419                     struct si_shader_config *conf,
 420                     LLVMTargetMachineRef tm,
 421                     LLVMModuleRef mod,
 422                     struct pipe_debug_callback *debug,
 423                     unsigned processor,
 424                     const char *name);
 425 void si_shader_destroy(struct si_shader *shader);
 426 unsigned si_shader_io_get_unique_index(unsigned semantic_name, unsigned index);
 427 int si_shader_binary_upload(struct si_screen *sscreen, struct si_shader *shader);
 428 void si_shader_dump(struct si_screen *sscreen, struct si_shader *shader,
 429                     struct pipe_debug_callback *debug, unsigned processor);
 430 void si_shader_apply_scratch_relocs(struct si_context *sctx,
 431                         struct si_shader *shader,
 432                         uint64_t scratch_va);
 433 void si_shader_binary_read_config(struct radeon_shader_binary *binary,
 434                                   struct si_shader_config *conf,
 435                                   unsigned symbol_offset);
 436
 437 #endif