2 * Copyright 2012 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 * Tom Stellard <thomas.stellard@amd.com>
25 * Michel Dänzer <michel.daenzer@amd.com>
26 * Christian König <christian.koenig@amd.com>
29 /* How linking shader inputs and outputs between vertex, tessellation, and
30 * geometry shaders works.
32 * Inputs and outputs between shaders are stored in a buffer. This buffer
33 * lives in LDS (typical case for tessellation), but it can also live
34 * in memory (ESGS). Each input or output has a fixed location within a vertex.
35 * The highest used input or output determines the stride between vertices.
37 * Since GS and tessellation are only possible in the OpenGL core profile,
38 * only these semantics are valid for per-vertex data:
45 * CULLDIST0..1 (not implemented)
48 * For example, a shader only writing GENERIC0 has the output stride of 5.
50 * Only these semantics are valid for per-patch data:
58 * That's how independent shaders agree on input and output locations.
59 * The si_shader_io_get_unique_index function assigns the locations.
61 * For tessellation, other required information for calculating the input and
62 * output addresses like the vertex stride, the patch stride, and the offsets
63 * where per-vertex and per-patch data start, is passed to the shader via
64 * user data SGPRs. The offsets and strides are calculated at draw time and
65 * aren't available at compile time.
71 #include <llvm-c/Core.h> /* LLVMModuleRef */
72 #include <llvm-c/TargetMachine.h>
73 #include "tgsi/tgsi_scan.h"
74 #include "util/u_queue.h"
77 struct radeon_shader_binary
;
78 struct radeon_shader_reloc
;
80 #define SI_MAX_VS_OUTPUTS 40
82 /* SGPR user data indices */
84 SI_SGPR_RW_BUFFERS
, /* rings (& stream-out, VS only) */
85 SI_SGPR_RW_BUFFERS_HI
,
86 SI_SGPR_CONST_BUFFERS
,
87 SI_SGPR_CONST_BUFFERS_HI
,
88 SI_SGPR_SAMPLERS
, /* images & sampler states interleaved */
92 SI_SGPR_SHADER_BUFFERS
,
93 SI_SGPR_SHADER_BUFFERS_HI
,
94 SI_NUM_RESOURCE_SGPRS
,
97 SI_SGPR_VERTEX_BUFFERS
= SI_NUM_RESOURCE_SGPRS
,
98 SI_SGPR_VERTEX_BUFFERS_HI
,
100 SI_SGPR_START_INSTANCE
,
105 SI_SGPR_VS_STATE_BITS
= SI_ES_NUM_USER_SGPR
,
109 SI_SGPR_LS_OUT_LAYOUT
= SI_ES_NUM_USER_SGPR
,
112 /* both TCS and TES */
113 SI_SGPR_TCS_OFFCHIP_LAYOUT
= SI_NUM_RESOURCE_SGPRS
,
114 SI_TES_NUM_USER_SGPR
,
117 SI_SGPR_TCS_OUT_OFFSETS
= SI_TES_NUM_USER_SGPR
,
118 SI_SGPR_TCS_OUT_LAYOUT
,
119 SI_SGPR_TCS_IN_LAYOUT
,
120 SI_TCS_NUM_USER_SGPR
,
123 SI_GS_NUM_USER_SGPR
= SI_NUM_RESOURCE_SGPRS
,
124 SI_GSCOPY_NUM_USER_SGPR
= SI_SGPR_RW_BUFFERS_HI
+ 1,
127 SI_SGPR_ALPHA_REF
= SI_NUM_RESOURCE_SGPRS
,
131 SI_SGPR_GRID_SIZE
= SI_NUM_RESOURCE_SGPRS
,
132 SI_SGPR_BLOCK_SIZE
= SI_SGPR_GRID_SIZE
+ 3,
133 SI_CS_NUM_USER_SGPR
= SI_SGPR_BLOCK_SIZE
+ 3
136 /* LLVM function parameter indices */
139 SI_PARAM_CONST_BUFFERS
,
142 SI_PARAM_SHADER_BUFFERS
,
143 SI_NUM_RESOURCE_PARAMS
,
145 /* VS only parameters */
146 SI_PARAM_VERTEX_BUFFERS
= SI_NUM_RESOURCE_PARAMS
,
147 SI_PARAM_BASE_VERTEX
,
148 SI_PARAM_START_INSTANCE
,
150 /* [0] = clamp vertex color, VS as VS only */
151 SI_PARAM_VS_STATE_BITS
,
152 /* same value as TCS_IN_LAYOUT, VS as LS only */
153 SI_PARAM_LS_OUT_LAYOUT
= SI_PARAM_DRAWID
+ 1,
154 /* the other VS parameters are assigned dynamically */
156 /* Layout of TCS outputs in the offchip buffer
157 * [0:8] = the number of patches per threadgroup.
158 * [9:15] = the number of output vertices per patch.
159 * [16:31] = the offset of per patch attributes in the buffer in bytes.
161 SI_PARAM_TCS_OFFCHIP_LAYOUT
= SI_NUM_RESOURCE_PARAMS
, /* for TCS & TES */
163 /* TCS only parameters. */
165 /* Offsets where TCS outputs and TCS patch outputs live in LDS:
166 * [0:15] = TCS output patch0 offset / 16, max = NUM_PATCHES * 32 * 32
167 * [16:31] = TCS output patch0 offset for per-patch / 16, max = NUM_PATCHES*32*32* + 32*32
169 SI_PARAM_TCS_OUT_OFFSETS
,
171 /* Layout of TCS outputs / TES inputs:
172 * [0:12] = stride between output patches in dwords, num_outputs * num_vertices * 4, max = 32*32*4
173 * [13:20] = stride between output vertices in dwords = num_inputs * 4, max = 32*4
174 * [26:31] = gl_PatchVerticesIn, max = 32
176 SI_PARAM_TCS_OUT_LAYOUT
,
178 /* Layout of LS outputs / TCS inputs
179 * [0:12] = stride between patches in dwords = num_inputs * num_vertices * 4, max = 32*32*4
180 * [13:20] = stride between vertices in dwords = num_inputs * 4, max = 32*4
182 SI_PARAM_TCS_IN_LAYOUT
,
185 SI_PARAM_TESS_FACTOR_OFFSET
,
189 /* GS only parameters */
190 SI_PARAM_GS2VS_OFFSET
= SI_NUM_RESOURCE_PARAMS
,
192 SI_PARAM_VTX0_OFFSET
,
193 SI_PARAM_VTX1_OFFSET
,
194 SI_PARAM_PRIMITIVE_ID
,
195 SI_PARAM_VTX2_OFFSET
,
196 SI_PARAM_VTX3_OFFSET
,
197 SI_PARAM_VTX4_OFFSET
,
198 SI_PARAM_VTX5_OFFSET
,
199 SI_PARAM_GS_INSTANCE_ID
,
201 /* PS only parameters */
202 SI_PARAM_ALPHA_REF
= SI_NUM_RESOURCE_PARAMS
,
204 SI_PARAM_PERSP_SAMPLE
,
205 SI_PARAM_PERSP_CENTER
,
206 SI_PARAM_PERSP_CENTROID
,
207 SI_PARAM_PERSP_PULL_MODEL
,
208 SI_PARAM_LINEAR_SAMPLE
,
209 SI_PARAM_LINEAR_CENTER
,
210 SI_PARAM_LINEAR_CENTROID
,
211 SI_PARAM_LINE_STIPPLE_TEX
,
212 SI_PARAM_POS_X_FLOAT
,
213 SI_PARAM_POS_Y_FLOAT
,
214 SI_PARAM_POS_Z_FLOAT
,
215 SI_PARAM_POS_W_FLOAT
,
218 SI_PARAM_SAMPLE_COVERAGE
,
219 SI_PARAM_POS_FIXED_PT
,
221 /* CS only parameters */
222 SI_PARAM_GRID_SIZE
= SI_NUM_RESOURCE_PARAMS
,
227 SI_NUM_PARAMS
= SI_PARAM_POS_FIXED_PT
+ 9, /* +8 for COLOR[0..1] */
230 /* SI-specific system values. */
232 TGSI_SEMANTIC_DEFAULT_TESSOUTER_SI
= TGSI_SEMANTIC_COUNT
,
233 TGSI_SEMANTIC_DEFAULT_TESSINNER_SI
,
236 /* For VS shader key fix_fetch. */
238 SI_FIX_FETCH_NONE
= 0,
239 SI_FIX_FETCH_A2_SNORM
= 1,
240 SI_FIX_FETCH_A2_SSCALED
= 2,
241 SI_FIX_FETCH_A2_SINT
= 3,
246 /* A shader selector is a gallium CSO and contains shader variants and
247 * binaries for one TGSI program. This can be shared by multiple contexts.
249 struct si_shader_selector
{
250 struct si_screen
*screen
;
251 struct util_queue_fence ready
;
253 /* Should only be used by si_init_shader_selector_async
254 * if thread_index == -1 (non-threaded). */
255 LLVMTargetMachineRef tm
;
256 struct pipe_debug_callback debug
;
257 bool is_debug_context
;
260 struct si_shader
*first_variant
; /* immutable after the first variant */
261 struct si_shader
*last_variant
; /* mutable */
263 /* The compiled TGSI shader expecting a prolog and/or epilog (not
264 * uploaded to a buffer).
266 struct si_shader
*main_shader_part
;
268 struct si_shader
*gs_copy_shader
;
270 struct tgsi_token
*tokens
;
271 struct pipe_stream_output_info so
;
272 struct tgsi_shader_info info
;
274 /* PIPE_SHADER_[VERTEX|FRAGMENT|...] */
278 unsigned esgs_itemsize
;
279 unsigned gs_input_verts_per_prim
;
280 unsigned gs_output_prim
;
281 unsigned gs_max_out_vertices
;
282 unsigned gs_num_invocations
;
283 unsigned max_gs_stream
; /* count - 1 */
284 unsigned gsvs_vertex_size
;
285 unsigned max_gsvs_emit_size
;
288 unsigned color_attr_index
[2];
289 unsigned db_shader_control
;
290 /* Set 0xf or 0x0 (4 bits) per each written output.
291 * ANDed with spi_shader_col_format.
293 unsigned colors_written_4bit
;
298 uint64_t outputs_written
; /* "get_unique_index" bits */
299 uint32_t patch_outputs_written
; /* "get_unique_index" bits */
300 uint32_t outputs_written2
; /* "get_unique_index2" bits */
302 uint64_t inputs_read
; /* "get_unique_index" bits */
303 uint32_t inputs_read2
; /* "get_unique_index2" bits */
306 /* Valid shader configurations:
308 * API shaders VS | TCS | TES | GS |pass| PS
309 * are compiled as: | | | |thru|
311 * Only VS & PS: VS | -- | -- | -- | -- | PS
312 * With GS: ES | -- | -- | GS | VS | PS
313 * With Tessel.: LS | HS | VS | -- | -- | PS
314 * With both: LS | HS | ES | GS | VS | PS
317 /* Common VS bits between the shader key and the prolog key. */
318 struct si_vs_prolog_bits
{
319 unsigned instance_divisors
[SI_NUM_VERTEX_BUFFERS
];
322 /* Common VS bits between the shader key and the epilog key. */
323 struct si_vs_epilog_bits
{
324 unsigned export_prim_id
:1; /* when PS needs it and GS is disabled */
327 /* Common TCS bits between the shader key and the epilog key. */
328 struct si_tcs_epilog_bits
{
329 unsigned prim_mode
:3;
332 struct si_gs_prolog_bits
{
333 unsigned tri_strip_adj_fix
:1;
336 /* Common PS bits between the shader key and the prolog key. */
337 struct si_ps_prolog_bits
{
338 unsigned color_two_side
:1;
339 unsigned flatshade_colors
:1;
340 unsigned poly_stipple
:1;
341 unsigned force_persp_sample_interp
:1;
342 unsigned force_linear_sample_interp
:1;
343 unsigned force_persp_center_interp
:1;
344 unsigned force_linear_center_interp
:1;
345 unsigned bc_optimize_for_persp
:1;
346 unsigned bc_optimize_for_linear
:1;
349 /* Common PS bits between the shader key and the epilog key. */
350 struct si_ps_epilog_bits
{
351 unsigned spi_shader_col_format
;
352 unsigned color_is_int8
:8;
353 unsigned last_cbuf
:3;
354 unsigned alpha_func
:3;
355 unsigned alpha_to_one
:1;
356 unsigned poly_line_smoothing
:1;
357 unsigned clamp_color
:1;
360 union si_shader_part_key
{
362 struct si_vs_prolog_bits states
;
363 unsigned num_input_sgprs
:5;
364 unsigned last_input
:4;
367 struct si_vs_epilog_bits states
;
368 unsigned prim_id_param_offset
:5;
371 struct si_tcs_epilog_bits states
;
374 struct si_gs_prolog_bits states
;
377 struct si_ps_prolog_bits states
;
378 unsigned num_input_sgprs
:5;
379 unsigned num_input_vgprs
:5;
380 /* Color interpolation and two-side color selection. */
381 unsigned colors_read
:8; /* color input components read */
382 unsigned num_interp_inputs
:5; /* BCOLOR is at this location */
383 unsigned face_vgpr_index
:5;
385 char color_attr_index
[2];
386 char color_interp_vgpr_index
[2]; /* -1 == constant */
389 struct si_ps_epilog_bits states
;
390 unsigned colors_written
:8;
392 unsigned writes_stencil
:1;
393 unsigned writes_samplemask
:1;
397 struct si_shader_key
{
398 /* Prolog and epilog flags. */
401 struct si_ps_prolog_bits prolog
;
402 struct si_ps_epilog_bits epilog
;
405 struct si_vs_prolog_bits prolog
;
406 struct si_vs_epilog_bits epilog
;
409 struct si_tcs_epilog_bits epilog
;
410 } tcs
; /* tessellation control shader */
412 struct si_vs_epilog_bits epilog
; /* same as VS */
413 } tes
; /* tessellation evaluation shader */
415 struct si_gs_prolog_bits prolog
;
419 /* These two are initially set according to the NEXT_SHADER property,
420 * or guessed if the property doesn't seem correct.
422 unsigned as_es
:1; /* export shader */
423 unsigned as_ls
:1; /* local shader */
425 /* Flags for monolithic compilation only. */
428 /* One nibble for every input: SI_FIX_FETCH_* enums. */
432 uint64_t inputs_to_copy
; /* for fixed-func TCS */
436 /* Optimization flags for asynchronous compilation only. */
439 uint64_t kill_outputs
; /* "get_unique_index" bits */
440 uint32_t kill_outputs2
; /* "get_unique_index2" bits */
441 unsigned clip_disable
:1;
442 } hw_vs
; /* HW VS (it can be VS, TES, GS) */
446 struct si_shader_config
{
449 unsigned spilled_sgprs
;
450 unsigned spilled_vgprs
;
451 unsigned private_mem_vgprs
;
453 unsigned spi_ps_input_ena
;
454 unsigned spi_ps_input_addr
;
456 unsigned scratch_bytes_per_wave
;
462 /* SPI_PS_INPUT_CNTL_i.OFFSET[0:4] */
463 EXP_PARAM_OFFSET_0
= 0,
464 EXP_PARAM_OFFSET_31
= 31,
465 /* SPI_PS_INPUT_CNTL_i.DEFAULT_VAL[0:1] */
466 EXP_PARAM_DEFAULT_VAL_0000
= 64,
467 EXP_PARAM_DEFAULT_VAL_0001
,
468 EXP_PARAM_DEFAULT_VAL_1110
,
469 EXP_PARAM_DEFAULT_VAL_1111
,
470 EXP_PARAM_UNDEFINED
= 255,
473 /* GCN-specific shader info. */
474 struct si_shader_info
{
475 ubyte vs_output_param_offset
[SI_MAX_VS_OUTPUTS
];
476 ubyte num_input_sgprs
;
477 ubyte num_input_vgprs
;
478 char face_vgpr_index
;
479 bool uses_instanceid
;
480 ubyte nr_pos_exports
;
481 ubyte nr_param_exports
;
485 struct si_shader_selector
*selector
;
486 struct si_shader
*next_variant
;
488 struct si_shader_part
*prolog
;
489 struct si_shader_part
*epilog
;
491 struct si_pm4_state
*pm4
;
492 struct r600_resource
*bo
;
493 struct r600_resource
*scratch_bo
;
494 struct si_shader_key key
;
495 struct util_queue_fence optimized_ready
;
496 bool compilation_failed
;
499 bool is_binary_shared
;
500 bool is_gs_copy_shader
;
502 /* The following data is all that's needed for binary shaders. */
503 struct radeon_shader_binary binary
;
504 struct si_shader_config config
;
505 struct si_shader_info info
;
507 /* Shader key + LLVM IR + disassembly + statistics.
508 * Generated for debug contexts only.
511 size_t shader_log_size
;
514 struct si_shader_part
{
515 struct si_shader_part
*next
;
516 union si_shader_part_key key
;
517 struct radeon_shader_binary binary
;
518 struct si_shader_config config
;
523 si_generate_gs_copy_shader(struct si_screen
*sscreen
,
524 LLVMTargetMachineRef tm
,
525 struct si_shader_selector
*gs_selector
,
526 struct pipe_debug_callback
*debug
);
527 int si_compile_tgsi_shader(struct si_screen
*sscreen
,
528 LLVMTargetMachineRef tm
,
529 struct si_shader
*shader
,
531 struct pipe_debug_callback
*debug
);
532 int si_shader_create(struct si_screen
*sscreen
, LLVMTargetMachineRef tm
,
533 struct si_shader
*shader
,
534 struct pipe_debug_callback
*debug
);
535 int si_compile_llvm(struct si_screen
*sscreen
,
536 struct radeon_shader_binary
*binary
,
537 struct si_shader_config
*conf
,
538 LLVMTargetMachineRef tm
,
540 struct pipe_debug_callback
*debug
,
543 void si_shader_destroy(struct si_shader
*shader
);
544 unsigned si_shader_io_get_unique_index(unsigned semantic_name
, unsigned index
);
545 unsigned si_shader_io_get_unique_index2(unsigned name
, unsigned index
);
546 int si_shader_binary_upload(struct si_screen
*sscreen
, struct si_shader
*shader
);
547 void si_shader_dump(struct si_screen
*sscreen
, struct si_shader
*shader
,
548 struct pipe_debug_callback
*debug
, unsigned processor
,
549 FILE *f
, bool check_debug_option
);
550 void si_multiwave_lds_size_workaround(struct si_screen
*sscreen
,
552 void si_shader_apply_scratch_relocs(struct si_context
*sctx
,
553 struct si_shader
*shader
,
554 struct si_shader_config
*config
,
555 uint64_t scratch_va
);
556 void si_shader_binary_read_config(struct radeon_shader_binary
*binary
,
557 struct si_shader_config
*conf
,
558 unsigned symbol_offset
);
559 unsigned si_get_spi_shader_z_format(bool writes_z
, bool writes_stencil
,
560 bool writes_samplemask
);