src/gallium/drivers/radeonsi/si_shader.h

   1 /*
   2  * Copyright 2012 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Tom Stellard <thomas.stellard@amd.com>
  25  *      Michel Dänzer <michel.daenzer@amd.com>
  26  *      Christian König <christian.koenig@amd.com>
  27  */
  28
  29 /* How linking shader inputs and outputs between vertex, tessellation, and
  30  * geometry shaders works.
  31  *
  32  * Inputs and outputs between shaders are stored in a buffer. This buffer
  33  * lives in LDS (typical case for tessellation), but it can also live
  34  * in memory (ESGS). Each input or output has a fixed location within a vertex.
  35  * The highest used input or output determines the stride between vertices.
  36  *
  37  * Since GS and tessellation are only possible in the OpenGL core profile,
  38  * only these semantics are valid for per-vertex data:
  39  *
  40  *   Name             Location
  41  *
  42  *   POSITION         0
  43  *   PSIZE            1
  44  *   CLIPDIST0..1     2..3
  45  *   CULLDIST0..1     (not implemented)
  46  *   GENERIC0..31     4..35
  47  *
  48  * For example, a shader only writing GENERIC0 has the output stride of 5.
  49  *
  50  * Only these semantics are valid for per-patch data:
  51  *
  52  *   Name             Location
  53  *
  54  *   TESSOUTER        0
  55  *   TESSINNER        1
  56  *   PATCH0..29       2..31
  57  *
  58  * That's how independent shaders agree on input and output locations.
  59  * The si_shader_io_get_unique_index function assigns the locations.
  60  *
  61  * For tessellation, other required information for calculating the input and
  62  * output addresses like the vertex stride, the patch stride, and the offsets
  63  * where per-vertex and per-patch data start, is passed to the shader via
  64  * user data SGPRs. The offsets and strides are calculated at draw time and
  65  * aren't available at compile time.
  66  */
  67
  68 #ifndef SI_SHADER_H
  69 #define SI_SHADER_H
  70
  71 #include <llvm-c/Core.h> /* LLVMModuleRef */
  72 #include "tgsi/tgsi_scan.h"
  73 #include "si_state.h"
  74
  75 struct radeon_shader_binary;
  76 struct radeon_shader_reloc;
  77
  78 #define SI_MAX_VS_OUTPUTS       40
  79
  80 #define SI_SGPR_RW_BUFFERS      0  /* rings (& stream-out, VS only) */
  81 #define SI_SGPR_CONST_BUFFERS   2
  82 #define SI_SGPR_SAMPLERS        4  /* images & sampler states interleaved */
  83 /* TODO: gap */
  84 #define SI_SGPR_VERTEX_BUFFERS  8  /* VS only */
  85 #define SI_SGPR_BASE_VERTEX     10 /* VS only */
  86 #define SI_SGPR_START_INSTANCE  11 /* VS only */
  87 #define SI_SGPR_VS_STATE_BITS   12 /* VS(VS) only */
  88 #define SI_SGPR_LS_OUT_LAYOUT   12 /* VS(LS) only */
  89 #define SI_SGPR_TCS_OUT_OFFSETS 8  /* TCS & TES only */
  90 #define SI_SGPR_TCS_OUT_LAYOUT  9  /* TCS & TES only */
  91 #define SI_SGPR_TCS_IN_LAYOUT   10 /* TCS only */
  92 #define SI_SGPR_ALPHA_REF       8  /* PS only */
  93
  94 #define SI_VS_NUM_USER_SGPR     13 /* API VS */
  95 #define SI_ES_NUM_USER_SGPR     12 /* API VS */
  96 #define SI_LS_NUM_USER_SGPR     13 /* API VS */
  97 #define SI_TCS_NUM_USER_SGPR    11
  98 #define SI_TES_NUM_USER_SGPR    10
  99 #define SI_GS_NUM_USER_SGPR     8
 100 #define SI_GSCOPY_NUM_USER_SGPR 4
 101 #define SI_PS_NUM_USER_SGPR     9
 102
 103 /* LLVM function parameter indices */
 104 #define SI_PARAM_RW_BUFFERS     0
 105 #define SI_PARAM_CONST_BUFFERS  1
 106 #define SI_PARAM_SAMPLERS       2
 107 #define SI_PARAM_UNUSED         3 /* TODO: use */
 108
 109 /* VS only parameters */
 110 #define SI_PARAM_VERTEX_BUFFERS 4
 111 #define SI_PARAM_BASE_VERTEX    5
 112 #define SI_PARAM_START_INSTANCE 6
 113 /* [0] = clamp vertex color */
 114 #define SI_PARAM_VS_STATE_BITS  7
 115 /* the other VS parameters are assigned dynamically */
 116
 117 /* Offsets where TCS outputs and TCS patch outputs live in LDS:
 118  *   [0:15] = TCS output patch0 offset / 16, max = NUM_PATCHES * 32 * 32
 119  *   [16:31] = TCS output patch0 offset for per-patch / 16, max = NUM_PATCHES*32*32* + 32*32
 120  */
 121 #define SI_PARAM_TCS_OUT_OFFSETS 4 /* for TCS & TES */
 122
 123 /* Layout of TCS outputs / TES inputs:
 124  *   [0:12] = stride between output patches in dwords, num_outputs * num_vertices * 4, max = 32*32*4
 125  *   [13:20] = stride between output vertices in dwords = num_inputs * 4, max = 32*4
 126  *   [26:31] = gl_PatchVerticesIn, max = 32
 127  */
 128 #define SI_PARAM_TCS_OUT_LAYOUT 5 /* for TCS & TES */
 129
 130 /* Layout of LS outputs / TCS inputs
 131  *   [0:12] = stride between patches in dwords = num_inputs * num_vertices * 4, max = 32*32*4
 132  *   [13:20] = stride between vertices in dwords = num_inputs * 4, max = 32*4
 133  */
 134 #define SI_PARAM_TCS_IN_LAYOUT  6 /* TCS only */
 135 #define SI_PARAM_LS_OUT_LAYOUT  7 /* same value as TCS_IN_LAYOUT, LS only */
 136
 137 /* TCS only parameters. */
 138 #define SI_PARAM_TESS_FACTOR_OFFSET 7
 139 #define SI_PARAM_PATCH_ID       8
 140 #define SI_PARAM_REL_IDS        9
 141
 142 /* GS only parameters */
 143 #define SI_PARAM_GS2VS_OFFSET   4
 144 #define SI_PARAM_GS_WAVE_ID     5
 145 #define SI_PARAM_VTX0_OFFSET    6
 146 #define SI_PARAM_VTX1_OFFSET    7
 147 #define SI_PARAM_PRIMITIVE_ID   8
 148 #define SI_PARAM_VTX2_OFFSET    9
 149 #define SI_PARAM_VTX3_OFFSET    10
 150 #define SI_PARAM_VTX4_OFFSET    11
 151 #define SI_PARAM_VTX5_OFFSET    12
 152 #define SI_PARAM_GS_INSTANCE_ID 13
 153
 154 /* PS only parameters */
 155 #define SI_PARAM_ALPHA_REF              4
 156 #define SI_PARAM_PRIM_MASK              5
 157 #define SI_PARAM_PERSP_SAMPLE           6
 158 #define SI_PARAM_PERSP_CENTER           7
 159 #define SI_PARAM_PERSP_CENTROID         8
 160 #define SI_PARAM_PERSP_PULL_MODEL       9
 161 #define SI_PARAM_LINEAR_SAMPLE          10
 162 #define SI_PARAM_LINEAR_CENTER          11
 163 #define SI_PARAM_LINEAR_CENTROID        12
 164 #define SI_PARAM_LINE_STIPPLE_TEX       13
 165 #define SI_PARAM_POS_X_FLOAT            14
 166 #define SI_PARAM_POS_Y_FLOAT            15
 167 #define SI_PARAM_POS_Z_FLOAT            16
 168 #define SI_PARAM_POS_W_FLOAT            17
 169 #define SI_PARAM_FRONT_FACE             18
 170 #define SI_PARAM_ANCILLARY              19
 171 #define SI_PARAM_SAMPLE_COVERAGE        20
 172 #define SI_PARAM_POS_FIXED_PT           21
 173
 174 #define SI_NUM_PARAMS (SI_PARAM_POS_FIXED_PT + 9) /* +8 for COLOR[0..1] */
 175
 176 struct si_shader;
 177
 178 /* A shader selector is a gallium CSO and contains shader variants and
 179  * binaries for one TGSI program. This can be shared by multiple contexts.
 180  */
 181 struct si_shader_selector {
 182         pipe_mutex              mutex;
 183         struct si_shader        *first_variant; /* immutable after the first variant */
 184         struct si_shader        *last_variant; /* mutable */
 185
 186         /* The compiled TGSI shader expecting a prolog and/or epilog (not
 187          * uploaded to a buffer).
 188          */
 189         struct si_shader        *main_shader_part;
 190
 191         struct tgsi_token       *tokens;
 192         struct pipe_stream_output_info  so;
 193         struct tgsi_shader_info         info;
 194
 195         /* PIPE_SHADER_[VERTEX|FRAGMENT|...] */
 196         unsigned        type;
 197
 198         /* GS parameters. */
 199         unsigned        esgs_itemsize;
 200         unsigned        gs_input_verts_per_prim;
 201         unsigned        gs_output_prim;
 202         unsigned        gs_max_out_vertices;
 203         unsigned        gs_num_invocations;
 204         unsigned        max_gs_stream; /* count - 1 */
 205         unsigned        gsvs_vertex_size;
 206         unsigned        max_gsvs_emit_size;
 207
 208         /* PS parameters. */
 209         unsigned        color_attr_index[2];
 210         unsigned        db_shader_control;
 211         /* Set 0xf or 0x0 (4 bits) per each written output.
 212          * ANDed with spi_shader_col_format.
 213          */
 214         unsigned        colors_written_4bit;
 215
 216         /* masks of "get_unique_index" bits */
 217         uint64_t        outputs_written;
 218         uint32_t        patch_outputs_written;
 219 };
 220
 221 /* Valid shader configurations:
 222  *
 223  * API shaders       VS | TCS | TES | GS |pass| PS
 224  * are compiled as:     |     |     |    |thru|
 225  *                      |     |     |    |    |
 226  * Only VS & PS:     VS | --  | --  | -- | -- | PS
 227  * With GS:          ES | --  | --  | GS | VS | PS
 228  * With Tessel.:     LS | HS  | VS  | -- | -- | PS
 229  * With both:        LS | HS  | ES  | GS | VS | PS
 230  */
 231
 232 /* Common VS bits between the shader key and the prolog key. */
 233 struct si_vs_prolog_bits {
 234         unsigned        instance_divisors[SI_NUM_VERTEX_BUFFERS];
 235 };
 236
 237 /* Common VS bits between the shader key and the epilog key. */
 238 struct si_vs_epilog_bits {
 239         unsigned        export_prim_id:1; /* when PS needs it and GS is disabled */
 240         /* TODO:
 241          * - skip clipdist, culldist (including clipvertex code) exports based
 242          *   on which clip_plane_enable bits are set
 243          * - skip layer, viewport, clipdist, and culldist parameter exports
 244          *   if PS doesn't read them
 245          */
 246 };
 247
 248 /* Common TCS bits between the shader key and the epilog key. */
 249 struct si_tcs_epilog_bits {
 250         unsigned        prim_mode:3;
 251 };
 252
 253 /* Common PS bits between the shader key and the prolog key. */
 254 struct si_ps_prolog_bits {
 255         unsigned        color_two_side:1;
 256         /* TODO: add a flatshade bit that skips interpolation for colors */
 257         unsigned        poly_stipple:1;
 258         unsigned        force_persample_interp:1;
 259         /* TODO:
 260          * - add force_center_interp if MSAA is disabled and centroid or
 261          *   sample are present
 262          * - add force_center_interp_bc_optimize to force center interpolation
 263          *   based on the bc_optimize SGPR bit if MSAA is enabled, centroid is
 264          *   present and sample isn't present.
 265          */
 266 };
 267
 268 /* Common PS bits between the shader key and the epilog key. */
 269 struct si_ps_epilog_bits {
 270         unsigned        spi_shader_col_format;
 271         unsigned        color_is_int8:8;
 272         unsigned        last_cbuf:3;
 273         unsigned        alpha_func:3;
 274         unsigned        alpha_to_one:1;
 275         unsigned        poly_line_smoothing:1;
 276         unsigned        clamp_color:1;
 277 };
 278
 279 union si_shader_part_key {
 280         struct {
 281                 struct si_vs_prolog_bits states;
 282                 unsigned        num_input_sgprs:5;
 283                 unsigned        last_input:4;
 284         } vs_prolog;
 285         struct {
 286                 struct si_vs_epilog_bits states;
 287                 unsigned        prim_id_param_offset:5;
 288         } vs_epilog;
 289         struct {
 290                 struct si_tcs_epilog_bits states;
 291         } tcs_epilog;
 292         struct {
 293                 struct si_ps_prolog_bits states;
 294                 unsigned        num_input_sgprs:5;
 295                 unsigned        num_input_vgprs:5;
 296                 /* Color interpolation and two-side color selection. */
 297                 unsigned        colors_read:8; /* color input components read */
 298                 unsigned        num_interp_inputs:5; /* BCOLOR is at this location */
 299                 unsigned        face_vgpr_index:5;
 300                 char            color_attr_index[2];
 301                 char            color_interp_vgpr_index[2]; /* -1 == constant */
 302         } ps_prolog;
 303         struct {
 304                 struct si_ps_epilog_bits states;
 305                 unsigned        colors_written:8;
 306                 unsigned        writes_z:1;
 307                 unsigned        writes_stencil:1;
 308                 unsigned        writes_samplemask:1;
 309         } ps_epilog;
 310 };
 311
 312 union si_shader_key {
 313         struct {
 314                 struct si_ps_prolog_bits prolog;
 315                 struct si_ps_epilog_bits epilog;
 316         } ps;
 317         struct {
 318                 struct si_vs_prolog_bits prolog;
 319                 struct si_vs_epilog_bits epilog;
 320                 unsigned        as_es:1; /* export shader */
 321                 unsigned        as_ls:1; /* local shader */
 322         } vs;
 323         struct {
 324                 struct si_tcs_epilog_bits epilog;
 325         } tcs; /* tessellation control shader */
 326         struct {
 327                 struct si_vs_epilog_bits epilog; /* same as VS */
 328                 unsigned        as_es:1; /* export shader */
 329         } tes; /* tessellation evaluation shader */
 330 };
 331
 332 struct si_shader_config {
 333         unsigned                        num_sgprs;
 334         unsigned                        num_vgprs;
 335         unsigned                        lds_size;
 336         unsigned                        spi_ps_input_ena;
 337         unsigned                        spi_ps_input_addr;
 338         unsigned                        float_mode;
 339         unsigned                        scratch_bytes_per_wave;
 340         unsigned                        rsrc1;
 341         unsigned                        rsrc2;
 342 };
 343
 344 /* GCN-specific shader info. */
 345 struct si_shader_info {
 346         ubyte                   vs_output_param_offset[SI_MAX_VS_OUTPUTS];
 347         ubyte                   num_input_sgprs;
 348         ubyte                   num_input_vgprs;
 349         char                    face_vgpr_index;
 350         bool                    uses_instanceid;
 351         ubyte                   nr_pos_exports;
 352         ubyte                   nr_param_exports;
 353 };
 354
 355 struct si_shader {
 356         struct si_shader_selector       *selector;
 357         struct si_shader                *next_variant;
 358
 359         struct si_shader_part           *prolog;
 360         struct si_shader_part           *epilog;
 361
 362         struct si_shader                *gs_copy_shader;
 363         struct si_pm4_state             *pm4;
 364         struct r600_resource            *bo;
 365         struct r600_resource            *scratch_bo;
 366         union si_shader_key             key;
 367         bool                            is_binary_shared;
 368         unsigned                        z_order;
 369
 370         /* The following data is all that's needed for binary shaders. */
 371         struct radeon_shader_binary     binary;
 372         struct si_shader_config         config;
 373         struct si_shader_info           info;
 374 };
 375
 376 struct si_shader_part {
 377         struct si_shader_part *next;
 378         union si_shader_part_key key;
 379         struct radeon_shader_binary binary;
 380         struct si_shader_config config;
 381 };
 382
 383 static inline struct tgsi_shader_info *si_get_vs_info(struct si_context *sctx)
 384 {
 385         if (sctx->gs_shader.cso)
 386                 return &sctx->gs_shader.cso->info;
 387         else if (sctx->tes_shader.cso)
 388                 return &sctx->tes_shader.cso->info;
 389         else if (sctx->vs_shader.cso)
 390                 return &sctx->vs_shader.cso->info;
 391         else
 392                 return NULL;
 393 }
 394
 395 static inline struct si_shader* si_get_vs_state(struct si_context *sctx)
 396 {
 397         if (sctx->gs_shader.current)
 398                 return sctx->gs_shader.current->gs_copy_shader;
 399         else if (sctx->tes_shader.current)
 400                 return sctx->tes_shader.current;
 401         else
 402                 return sctx->vs_shader.current;
 403 }
 404
 405 static inline bool si_vs_exports_prim_id(struct si_shader *shader)
 406 {
 407         if (shader->selector->type == PIPE_SHADER_VERTEX)
 408                 return shader->key.vs.epilog.export_prim_id;
 409         else if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
 410                 return shader->key.tes.epilog.export_prim_id;
 411         else
 412                 return false;
 413 }
 414
 415 /* si_shader.c */
 416 int si_compile_tgsi_shader(struct si_screen *sscreen,
 417                            LLVMTargetMachineRef tm,
 418                            struct si_shader *shader,
 419                            bool is_monolithic,
 420                            struct pipe_debug_callback *debug);
 421 int si_shader_create(struct si_screen *sscreen, LLVMTargetMachineRef tm,
 422                      struct si_shader *shader,
 423                      struct pipe_debug_callback *debug);
 424 void si_dump_shader_key(unsigned shader, union si_shader_key *key, FILE *f);
 425 int si_compile_llvm(struct si_screen *sscreen,
 426                     struct radeon_shader_binary *binary,
 427                     struct si_shader_config *conf,
 428                     LLVMTargetMachineRef tm,
 429                     LLVMModuleRef mod,
 430                     struct pipe_debug_callback *debug,
 431                     unsigned processor,
 432                     const char *name);
 433 void si_shader_destroy(struct si_shader *shader);
 434 unsigned si_shader_io_get_unique_index(unsigned semantic_name, unsigned index);
 435 int si_shader_binary_upload(struct si_screen *sscreen, struct si_shader *shader);
 436 void si_shader_dump(struct si_screen *sscreen, struct si_shader *shader,
 437                     struct pipe_debug_callback *debug, unsigned processor,
 438                     FILE *f);
 439 void si_shader_apply_scratch_relocs(struct si_context *sctx,
 440                         struct si_shader *shader,
 441                         uint64_t scratch_va);
 442 void si_shader_binary_read_config(struct radeon_shader_binary *binary,
 443                                   struct si_shader_config *conf,
 444                                   unsigned symbol_offset);
 445
 446 #endif