src/gallium/drivers/radeonsi/si_shader.h

   1 /*
   2  * Copyright 2012 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Tom Stellard <thomas.stellard@amd.com>
  25  *      Michel Dänzer <michel.daenzer@amd.com>
  26  *      Christian König <christian.koenig@amd.com>
  27  */
  28
  29 /* How linking shader inputs and outputs between vertex, tessellation, and
  30  * geometry shaders works.
  31  *
  32  * Inputs and outputs between shaders are stored in a buffer. This buffer
  33  * lives in LDS (typical case for tessellation), but it can also live
  34  * in memory (ESGS). Each input or output has a fixed location within a vertex.
  35  * The highest used input or output determines the stride between vertices.
  36  *
  37  * Since GS and tessellation are only possible in the OpenGL core profile,
  38  * only these semantics are valid for per-vertex data:
  39  *
  40  *   Name             Location
  41  *
  42  *   POSITION         0
  43  *   PSIZE            1
  44  *   CLIPDIST0..1     2..3
  45  *   CULLDIST0..1     (not implemented)
  46  *   GENERIC0..31     4..35
  47  *
  48  * For example, a shader only writing GENERIC0 has the output stride of 5.
  49  *
  50  * Only these semantics are valid for per-patch data:
  51  *
  52  *   Name             Location
  53  *
  54  *   TESSOUTER        0
  55  *   TESSINNER        1
  56  *   PATCH0..29       2..31
  57  *
  58  * That's how independent shaders agree on input and output locations.
  59  * The si_shader_io_get_unique_index function assigns the locations.
  60  *
  61  * For tessellation, other required information for calculating the input and
  62  * output addresses like the vertex stride, the patch stride, and the offsets
  63  * where per-vertex and per-patch data start, is passed to the shader via
  64  * user data SGPRs. The offsets and strides are calculated at draw time and
  65  * aren't available at compile time.
  66  */
  67
  68 #ifndef SI_SHADER_H
  69 #define SI_SHADER_H
  70
  71 #include <llvm-c/Core.h> /* LLVMModuleRef */
  72 #include "tgsi/tgsi_scan.h"
  73 #include "si_state.h"
  74
  75 struct radeon_shader_binary;
  76 struct radeon_shader_reloc;
  77
  78 #define SI_MAX_VS_OUTPUTS       40
  79
  80 /* SGPR user data indices */
  81 enum {
  82         SI_SGPR_RW_BUFFERS,  /* rings (& stream-out, VS only) */
  83         SI_SGPR_RW_BUFFERS_HI,
  84         SI_SGPR_CONST_BUFFERS,
  85         SI_SGPR_CONST_BUFFERS_HI,
  86         SI_SGPR_SAMPLERS,  /* images & sampler states interleaved */
  87         SI_SGPR_SAMPLERS_HI,
  88         SI_SGPR_IMAGES,
  89         SI_SGPR_IMAGES_HI,
  90         SI_SGPR_SHADER_BUFFERS,
  91         SI_SGPR_SHADER_BUFFERS_HI,
  92         SI_NUM_RESOURCE_SGPRS,
  93
  94         /* all VS variants */
  95         SI_SGPR_VERTEX_BUFFERS  = SI_NUM_RESOURCE_SGPRS,
  96         SI_SGPR_VERTEX_BUFFERS_HI,
  97         SI_SGPR_BASE_VERTEX,
  98         SI_SGPR_START_INSTANCE,
  99         SI_ES_NUM_USER_SGPR,
 100
 101         /* hw VS only */
 102         SI_SGPR_VS_STATE_BITS   = SI_ES_NUM_USER_SGPR,
 103         SI_VS_NUM_USER_SGPR,
 104
 105         /* hw LS only */
 106         SI_SGPR_LS_OUT_LAYOUT   = SI_ES_NUM_USER_SGPR,
 107         SI_LS_NUM_USER_SGPR,
 108
 109         /* both TCS and TES */
 110         SI_SGPR_TCS_OUT_OFFSETS = SI_NUM_RESOURCE_SGPRS,
 111         SI_SGPR_TCS_OUT_LAYOUT,
 112         SI_TES_NUM_USER_SGPR,
 113
 114         /* TCS only */
 115         SI_SGPR_TCS_IN_LAYOUT = SI_TES_NUM_USER_SGPR,
 116         SI_TCS_NUM_USER_SGPR,
 117
 118         /* GS limits */
 119         SI_GS_NUM_USER_SGPR = SI_NUM_RESOURCE_SGPRS,
 120         SI_GSCOPY_NUM_USER_SGPR = SI_SGPR_CONST_BUFFERS_HI + 1,
 121
 122         /* PS only */
 123         SI_SGPR_ALPHA_REF       = SI_NUM_RESOURCE_SGPRS,
 124         SI_PS_NUM_USER_SGPR,
 125
 126         /* CS only */
 127         SI_SGPR_GRID_SIZE = SI_NUM_RESOURCE_SGPRS,
 128         SI_CS_NUM_USER_SGPR = SI_SGPR_GRID_SIZE + 3
 129 };
 130
 131 /* LLVM function parameter indices */
 132 enum {
 133         SI_PARAM_RW_BUFFERS,
 134         SI_PARAM_CONST_BUFFERS,
 135         SI_PARAM_SAMPLERS,
 136         SI_PARAM_IMAGES,
 137         SI_PARAM_SHADER_BUFFERS,
 138         SI_NUM_RESOURCE_PARAMS,
 139
 140         /* VS only parameters */
 141         SI_PARAM_VERTEX_BUFFERS = SI_NUM_RESOURCE_PARAMS,
 142         SI_PARAM_BASE_VERTEX,
 143         SI_PARAM_START_INSTANCE,
 144         /* [0] = clamp vertex color */
 145         SI_PARAM_VS_STATE_BITS,
 146         /* the other VS parameters are assigned dynamically */
 147
 148         /* Offsets where TCS outputs and TCS patch outputs live in LDS:
 149          *   [0:15] = TCS output patch0 offset / 16, max = NUM_PATCHES * 32 * 32
 150          *   [16:31] = TCS output patch0 offset for per-patch / 16, max = NUM_PATCHES*32*32* + 32*32
 151          */
 152         SI_PARAM_TCS_OUT_OFFSETS = SI_NUM_RESOURCE_PARAMS, /* for TCS & TES */
 153
 154         /* Layout of TCS outputs / TES inputs:
 155          *   [0:12] = stride between output patches in dwords, num_outputs * num_vertices * 4, max = 32*32*4
 156          *   [13:20] = stride between output vertices in dwords = num_inputs * 4, max = 32*4
 157          *   [26:31] = gl_PatchVerticesIn, max = 32
 158          */
 159         SI_PARAM_TCS_OUT_LAYOUT, /* for TCS & TES */
 160
 161         /* Layout of LS outputs / TCS inputs
 162          *   [0:12] = stride between patches in dwords = num_inputs * num_vertices * 4, max = 32*32*4
 163          *   [13:20] = stride between vertices in dwords = num_inputs * 4, max = 32*4
 164          */
 165         SI_PARAM_TCS_IN_LAYOUT,  /* TCS only */
 166         SI_PARAM_LS_OUT_LAYOUT,  /* same value as TCS_IN_LAYOUT, LS only */
 167
 168         /* TCS only parameters. */
 169         SI_PARAM_TESS_FACTOR_OFFSET = SI_PARAM_TCS_IN_LAYOUT + 1,
 170         SI_PARAM_PATCH_ID,
 171         SI_PARAM_REL_IDS,
 172
 173         /* GS only parameters */
 174         SI_PARAM_GS2VS_OFFSET = SI_NUM_RESOURCE_PARAMS,
 175         SI_PARAM_GS_WAVE_ID,
 176         SI_PARAM_VTX0_OFFSET,
 177         SI_PARAM_VTX1_OFFSET,
 178         SI_PARAM_PRIMITIVE_ID,
 179         SI_PARAM_VTX2_OFFSET,
 180         SI_PARAM_VTX3_OFFSET,
 181         SI_PARAM_VTX4_OFFSET,
 182         SI_PARAM_VTX5_OFFSET,
 183         SI_PARAM_GS_INSTANCE_ID,
 184
 185         /* PS only parameters */
 186         SI_PARAM_ALPHA_REF = SI_NUM_RESOURCE_PARAMS,
 187         SI_PARAM_PRIM_MASK,
 188         SI_PARAM_PERSP_SAMPLE,
 189         SI_PARAM_PERSP_CENTER,
 190         SI_PARAM_PERSP_CENTROID,
 191         SI_PARAM_PERSP_PULL_MODEL,
 192         SI_PARAM_LINEAR_SAMPLE,
 193         SI_PARAM_LINEAR_CENTER,
 194         SI_PARAM_LINEAR_CENTROID,
 195         SI_PARAM_LINE_STIPPLE_TEX,
 196         SI_PARAM_POS_X_FLOAT,
 197         SI_PARAM_POS_Y_FLOAT,
 198         SI_PARAM_POS_Z_FLOAT,
 199         SI_PARAM_POS_W_FLOAT,
 200         SI_PARAM_FRONT_FACE,
 201         SI_PARAM_ANCILLARY,
 202         SI_PARAM_SAMPLE_COVERAGE,
 203         SI_PARAM_POS_FIXED_PT,
 204
 205         /* CS only parameters */
 206         SI_PARAM_GRID_SIZE = SI_NUM_RESOURCE_PARAMS,
 207         SI_PARAM_BLOCK_ID,
 208         SI_PARAM_THREAD_ID,
 209
 210         SI_NUM_PARAMS = SI_PARAM_POS_FIXED_PT + 9, /* +8 for COLOR[0..1] */
 211 };
 212
 213 struct si_shader;
 214
 215 /* A shader selector is a gallium CSO and contains shader variants and
 216  * binaries for one TGSI program. This can be shared by multiple contexts.
 217  */
 218 struct si_shader_selector {
 219         pipe_mutex              mutex;
 220         struct si_shader        *first_variant; /* immutable after the first variant */
 221         struct si_shader        *last_variant; /* mutable */
 222
 223         /* The compiled TGSI shader expecting a prolog and/or epilog (not
 224          * uploaded to a buffer).
 225          */
 226         struct si_shader        *main_shader_part;
 227
 228         struct tgsi_token       *tokens;
 229         struct pipe_stream_output_info  so;
 230         struct tgsi_shader_info         info;
 231
 232         /* PIPE_SHADER_[VERTEX|FRAGMENT|...] */
 233         unsigned        type;
 234
 235         /* GS parameters. */
 236         unsigned        esgs_itemsize;
 237         unsigned        gs_input_verts_per_prim;
 238         unsigned        gs_output_prim;
 239         unsigned        gs_max_out_vertices;
 240         unsigned        gs_num_invocations;
 241         unsigned        max_gs_stream; /* count - 1 */
 242         unsigned        gsvs_vertex_size;
 243         unsigned        max_gsvs_emit_size;
 244
 245         /* PS parameters. */
 246         unsigned        color_attr_index[2];
 247         unsigned        db_shader_control;
 248         /* Set 0xf or 0x0 (4 bits) per each written output.
 249          * ANDed with spi_shader_col_format.
 250          */
 251         unsigned        colors_written_4bit;
 252
 253         /* CS parameters */
 254         unsigned local_size;
 255
 256         /* masks of "get_unique_index" bits */
 257         uint64_t        outputs_written;
 258         uint32_t        patch_outputs_written;
 259 };
 260
 261 /* Valid shader configurations:
 262  *
 263  * API shaders       VS | TCS | TES | GS |pass| PS
 264  * are compiled as:     |     |     |    |thru|
 265  *                      |     |     |    |    |
 266  * Only VS & PS:     VS | --  | --  | -- | -- | PS
 267  * With GS:          ES | --  | --  | GS | VS | PS
 268  * With Tessel.:     LS | HS  | VS  | -- | -- | PS
 269  * With both:        LS | HS  | ES  | GS | VS | PS
 270  */
 271
 272 /* Common VS bits between the shader key and the prolog key. */
 273 struct si_vs_prolog_bits {
 274         unsigned        instance_divisors[SI_NUM_VERTEX_BUFFERS];
 275 };
 276
 277 /* Common VS bits between the shader key and the epilog key. */
 278 struct si_vs_epilog_bits {
 279         unsigned        export_prim_id:1; /* when PS needs it and GS is disabled */
 280         /* TODO:
 281          * - skip clipdist, culldist (including clipvertex code) exports based
 282          *   on which clip_plane_enable bits are set
 283          * - skip layer, viewport, clipdist, and culldist parameter exports
 284          *   if PS doesn't read them
 285          */
 286 };
 287
 288 /* Common TCS bits between the shader key and the epilog key. */
 289 struct si_tcs_epilog_bits {
 290         unsigned        prim_mode:3;
 291 };
 292
 293 /* Common PS bits between the shader key and the prolog key. */
 294 struct si_ps_prolog_bits {
 295         unsigned        color_two_side:1;
 296         /* TODO: add a flatshade bit that skips interpolation for colors */
 297         unsigned        poly_stipple:1;
 298         unsigned        force_persample_interp:1;
 299         /* TODO:
 300          * - add force_center_interp if MSAA is disabled and centroid or
 301          *   sample are present
 302          * - add force_center_interp_bc_optimize to force center interpolation
 303          *   based on the bc_optimize SGPR bit if MSAA is enabled, centroid is
 304          *   present and sample isn't present.
 305          */
 306 };
 307
 308 /* Common PS bits between the shader key and the epilog key. */
 309 struct si_ps_epilog_bits {
 310         unsigned        spi_shader_col_format;
 311         unsigned        color_is_int8:8;
 312         unsigned        last_cbuf:3;
 313         unsigned        alpha_func:3;
 314         unsigned        alpha_to_one:1;
 315         unsigned        poly_line_smoothing:1;
 316         unsigned        clamp_color:1;
 317 };
 318
 319 union si_shader_part_key {
 320         struct {
 321                 struct si_vs_prolog_bits states;
 322                 unsigned        num_input_sgprs:5;
 323                 unsigned        last_input:4;
 324         } vs_prolog;
 325         struct {
 326                 struct si_vs_epilog_bits states;
 327                 unsigned        prim_id_param_offset:5;
 328         } vs_epilog;
 329         struct {
 330                 struct si_tcs_epilog_bits states;
 331         } tcs_epilog;
 332         struct {
 333                 struct si_ps_prolog_bits states;
 334                 unsigned        num_input_sgprs:5;
 335                 unsigned        num_input_vgprs:5;
 336                 /* Color interpolation and two-side color selection. */
 337                 unsigned        colors_read:8; /* color input components read */
 338                 unsigned        num_interp_inputs:5; /* BCOLOR is at this location */
 339                 unsigned        face_vgpr_index:5;
 340                 char            color_attr_index[2];
 341                 char            color_interp_vgpr_index[2]; /* -1 == constant */
 342         } ps_prolog;
 343         struct {
 344                 struct si_ps_epilog_bits states;
 345                 unsigned        colors_written:8;
 346                 unsigned        writes_z:1;
 347                 unsigned        writes_stencil:1;
 348                 unsigned        writes_samplemask:1;
 349         } ps_epilog;
 350 };
 351
 352 union si_shader_key {
 353         struct {
 354                 struct si_ps_prolog_bits prolog;
 355                 struct si_ps_epilog_bits epilog;
 356         } ps;
 357         struct {
 358                 struct si_vs_prolog_bits prolog;
 359                 struct si_vs_epilog_bits epilog;
 360                 unsigned        as_es:1; /* export shader */
 361                 unsigned        as_ls:1; /* local shader */
 362         } vs;
 363         struct {
 364                 struct si_tcs_epilog_bits epilog;
 365         } tcs; /* tessellation control shader */
 366         struct {
 367                 struct si_vs_epilog_bits epilog; /* same as VS */
 368                 unsigned        as_es:1; /* export shader */
 369         } tes; /* tessellation evaluation shader */
 370 };
 371
 372 struct si_shader_config {
 373         unsigned                        num_sgprs;
 374         unsigned                        num_vgprs;
 375         unsigned                        lds_size;
 376         unsigned                        spi_ps_input_ena;
 377         unsigned                        spi_ps_input_addr;
 378         unsigned                        float_mode;
 379         unsigned                        scratch_bytes_per_wave;
 380         unsigned                        rsrc1;
 381         unsigned                        rsrc2;
 382 };
 383
 384 /* GCN-specific shader info. */
 385 struct si_shader_info {
 386         ubyte                   vs_output_param_offset[SI_MAX_VS_OUTPUTS];
 387         ubyte                   num_input_sgprs;
 388         ubyte                   num_input_vgprs;
 389         char                    face_vgpr_index;
 390         bool                    uses_instanceid;
 391         ubyte                   nr_pos_exports;
 392         ubyte                   nr_param_exports;
 393 };
 394
 395 struct si_shader {
 396         struct si_shader_selector       *selector;
 397         struct si_shader                *next_variant;
 398
 399         struct si_shader_part           *prolog;
 400         struct si_shader_part           *epilog;
 401
 402         struct si_shader                *gs_copy_shader;
 403         struct si_pm4_state             *pm4;
 404         struct r600_resource            *bo;
 405         struct r600_resource            *scratch_bo;
 406         union si_shader_key             key;
 407         bool                            is_binary_shared;
 408         unsigned                        z_order;
 409
 410         /* The following data is all that's needed for binary shaders. */
 411         struct radeon_shader_binary     binary;
 412         struct si_shader_config         config;
 413         struct si_shader_info           info;
 414 };
 415
 416 struct si_shader_part {
 417         struct si_shader_part *next;
 418         union si_shader_part_key key;
 419         struct radeon_shader_binary binary;
 420         struct si_shader_config config;
 421 };
 422
 423 static inline struct tgsi_shader_info *si_get_vs_info(struct si_context *sctx)
 424 {
 425         if (sctx->gs_shader.cso)
 426                 return &sctx->gs_shader.cso->info;
 427         else if (sctx->tes_shader.cso)
 428                 return &sctx->tes_shader.cso->info;
 429         else if (sctx->vs_shader.cso)
 430                 return &sctx->vs_shader.cso->info;
 431         else
 432                 return NULL;
 433 }
 434
 435 static inline struct si_shader* si_get_vs_state(struct si_context *sctx)
 436 {
 437         if (sctx->gs_shader.current)
 438                 return sctx->gs_shader.current->gs_copy_shader;
 439         else if (sctx->tes_shader.current)
 440                 return sctx->tes_shader.current;
 441         else
 442                 return sctx->vs_shader.current;
 443 }
 444
 445 static inline bool si_vs_exports_prim_id(struct si_shader *shader)
 446 {
 447         if (shader->selector->type == PIPE_SHADER_VERTEX)
 448                 return shader->key.vs.epilog.export_prim_id;
 449         else if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
 450                 return shader->key.tes.epilog.export_prim_id;
 451         else
 452                 return false;
 453 }
 454
 455 /* si_shader.c */
 456 int si_compile_tgsi_shader(struct si_screen *sscreen,
 457                            LLVMTargetMachineRef tm,
 458                            struct si_shader *shader,
 459                            bool is_monolithic,
 460                            struct pipe_debug_callback *debug);
 461 int si_shader_create(struct si_screen *sscreen, LLVMTargetMachineRef tm,
 462                      struct si_shader *shader,
 463                      struct pipe_debug_callback *debug);
 464 void si_dump_shader_key(unsigned shader, union si_shader_key *key, FILE *f);
 465 int si_compile_llvm(struct si_screen *sscreen,
 466                     struct radeon_shader_binary *binary,
 467                     struct si_shader_config *conf,
 468                     LLVMTargetMachineRef tm,
 469                     LLVMModuleRef mod,
 470                     struct pipe_debug_callback *debug,
 471                     unsigned processor,
 472                     const char *name);
 473 void si_shader_destroy(struct si_shader *shader);
 474 unsigned si_shader_io_get_unique_index(unsigned semantic_name, unsigned index);
 475 int si_shader_binary_upload(struct si_screen *sscreen, struct si_shader *shader);
 476 void si_shader_dump(struct si_screen *sscreen, struct si_shader *shader,
 477                     struct pipe_debug_callback *debug, unsigned processor,
 478                     FILE *f);
 479 void si_shader_apply_scratch_relocs(struct si_context *sctx,
 480                         struct si_shader *shader,
 481                         uint64_t scratch_va);
 482 void si_shader_binary_read_config(struct radeon_shader_binary *binary,
 483                                   struct si_shader_config *conf,
 484                                   unsigned symbol_offset);
 485
 486 #endif