src/gallium/drivers/radeonsi/si_shader.h

   1 /*
   2  * Copyright 2012 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Tom Stellard <thomas.stellard@amd.com>
  25  *      Michel Dänzer <michel.daenzer@amd.com>
  26  *      Christian König <christian.koenig@amd.com>
  27  */
  28
  29 /* How linking shader inputs and outputs between vertex, tessellation, and
  30  * geometry shaders works.
  31  *
  32  * Inputs and outputs between shaders are stored in a buffer. This buffer
  33  * lives in LDS (typical case for tessellation), but it can also live
  34  * in memory (ESGS). Each input or output has a fixed location within a vertex.
  35  * The highest used input or output determines the stride between vertices.
  36  *
  37  * Since GS and tessellation are only possible in the OpenGL core profile,
  38  * only these semantics are valid for per-vertex data:
  39  *
  40  *   Name             Location
  41  *
  42  *   POSITION         0
  43  *   PSIZE            1
  44  *   CLIPDIST0..1     2..3
  45  *   CULLDIST0..1     (not implemented)
  46  *   GENERIC0..31     4..35
  47  *
  48  * For example, a shader only writing GENERIC0 has the output stride of 5.
  49  *
  50  * Only these semantics are valid for per-patch data:
  51  *
  52  *   Name             Location
  53  *
  54  *   TESSOUTER        0
  55  *   TESSINNER        1
  56  *   PATCH0..29       2..31
  57  *
  58  * That's how independent shaders agree on input and output locations.
  59  * The si_shader_io_get_unique_index function assigns the locations.
  60  *
  61  * For tessellation, other required information for calculating the input and
  62  * output addresses like the vertex stride, the patch stride, and the offsets
  63  * where per-vertex and per-patch data start, is passed to the shader via
  64  * user data SGPRs. The offsets and strides are calculated at draw time and
  65  * aren't available at compile time.
  66  */
  67
  68 #ifndef SI_SHADER_H
  69 #define SI_SHADER_H
  70
  71 #include <llvm-c/Core.h> /* LLVMModuleRef */
  72 #include "tgsi/tgsi_scan.h"
  73 #include "si_state.h"
  74
  75 struct radeon_shader_binary;
  76 struct radeon_shader_reloc;
  77
  78 #define SI_MAX_VS_OUTPUTS       40
  79
  80 /* SGPR user data indices */
  81 enum {
  82         SI_SGPR_RW_BUFFERS,  /* rings (& stream-out, VS only) */
  83         SI_SGPR_RW_BUFFERS_HI,
  84         SI_SGPR_CONST_BUFFERS,
  85         SI_SGPR_CONST_BUFFERS_HI,
  86         SI_SGPR_SAMPLERS,  /* images & sampler states interleaved */
  87         SI_SGPR_SAMPLERS_HI,
  88         SI_SGPR_IMAGES,
  89         SI_SGPR_IMAGES_HI,
  90         SI_SGPR_SHADER_BUFFERS,
  91         SI_SGPR_SHADER_BUFFERS_HI,
  92         SI_NUM_RESOURCE_SGPRS,
  93
  94         /* all VS variants */
  95         SI_SGPR_VERTEX_BUFFERS  = SI_NUM_RESOURCE_SGPRS,
  96         SI_SGPR_VERTEX_BUFFERS_HI,
  97         SI_SGPR_BASE_VERTEX,
  98         SI_SGPR_START_INSTANCE,
  99         SI_ES_NUM_USER_SGPR,
 100
 101         /* hw VS only */
 102         SI_SGPR_VS_STATE_BITS   = SI_ES_NUM_USER_SGPR,
 103         SI_VS_NUM_USER_SGPR,
 104
 105         /* hw LS only */
 106         SI_SGPR_LS_OUT_LAYOUT   = SI_ES_NUM_USER_SGPR,
 107         SI_LS_NUM_USER_SGPR,
 108
 109         /* both TCS and TES */
 110         SI_SGPR_TCS_OFFCHIP_LAYOUT = SI_NUM_RESOURCE_SGPRS,
 111         SI_TES_NUM_USER_SGPR,
 112
 113         /* TCS only */
 114         SI_SGPR_TCS_OUT_OFFSETS = SI_TES_NUM_USER_SGPR,
 115         SI_SGPR_TCS_OUT_LAYOUT,
 116         SI_SGPR_TCS_IN_LAYOUT,
 117         SI_TCS_NUM_USER_SGPR,
 118
 119         /* GS limits */
 120         SI_GS_NUM_USER_SGPR = SI_NUM_RESOURCE_SGPRS,
 121         SI_GSCOPY_NUM_USER_SGPR = SI_SGPR_RW_BUFFERS_HI + 1,
 122
 123         /* PS only */
 124         SI_SGPR_ALPHA_REF       = SI_NUM_RESOURCE_SGPRS,
 125         SI_PS_NUM_USER_SGPR,
 126
 127         /* CS only */
 128         SI_SGPR_GRID_SIZE = SI_NUM_RESOURCE_SGPRS,
 129         SI_CS_NUM_USER_SGPR = SI_SGPR_GRID_SIZE + 3
 130 };
 131
 132 /* LLVM function parameter indices */
 133 enum {
 134         SI_PARAM_RW_BUFFERS,
 135         SI_PARAM_CONST_BUFFERS,
 136         SI_PARAM_SAMPLERS,
 137         SI_PARAM_IMAGES,
 138         SI_PARAM_SHADER_BUFFERS,
 139         SI_NUM_RESOURCE_PARAMS,
 140
 141         /* VS only parameters */
 142         SI_PARAM_VERTEX_BUFFERS = SI_NUM_RESOURCE_PARAMS,
 143         SI_PARAM_BASE_VERTEX,
 144         SI_PARAM_START_INSTANCE,
 145         /* [0] = clamp vertex color, VS as VS only */
 146         SI_PARAM_VS_STATE_BITS,
 147         /* same value as TCS_IN_LAYOUT, VS as LS only */
 148         SI_PARAM_LS_OUT_LAYOUT = SI_PARAM_START_INSTANCE + 1,
 149         /* the other VS parameters are assigned dynamically */
 150
 151         /* Layout of TCS outputs in the offchip buffer
 152          *   [0:8] = the number of patches per threadgroup.
 153          *   [9:15] = the number of output vertices per patch.
 154          *   [16:31] = the offset of per patch attributes in the buffer in bytes.
 155          */
 156         SI_PARAM_TCS_OFFCHIP_LAYOUT = SI_NUM_RESOURCE_PARAMS, /* for TCS & TES */
 157
 158         /* TCS only parameters. */
 159
 160         /* Offsets where TCS outputs and TCS patch outputs live in LDS:
 161          *   [0:15] = TCS output patch0 offset / 16, max = NUM_PATCHES * 32 * 32
 162          *   [16:31] = TCS output patch0 offset for per-patch / 16, max = NUM_PATCHES*32*32* + 32*32
 163          */
 164         SI_PARAM_TCS_OUT_OFFSETS,
 165
 166         /* Layout of TCS outputs / TES inputs:
 167          *   [0:12] = stride between output patches in dwords, num_outputs * num_vertices * 4, max = 32*32*4
 168          *   [13:20] = stride between output vertices in dwords = num_inputs * 4, max = 32*4
 169          *   [26:31] = gl_PatchVerticesIn, max = 32
 170          */
 171         SI_PARAM_TCS_OUT_LAYOUT,
 172
 173         /* Layout of LS outputs / TCS inputs
 174          *   [0:12] = stride between patches in dwords = num_inputs * num_vertices * 4, max = 32*32*4
 175          *   [13:20] = stride between vertices in dwords = num_inputs * 4, max = 32*4
 176          */
 177         SI_PARAM_TCS_IN_LAYOUT,
 178
 179         SI_PARAM_TCS_OC_LDS,
 180         SI_PARAM_TESS_FACTOR_OFFSET,
 181         SI_PARAM_PATCH_ID,
 182         SI_PARAM_REL_IDS,
 183
 184         /* GS only parameters */
 185         SI_PARAM_GS2VS_OFFSET = SI_NUM_RESOURCE_PARAMS,
 186         SI_PARAM_GS_WAVE_ID,
 187         SI_PARAM_VTX0_OFFSET,
 188         SI_PARAM_VTX1_OFFSET,
 189         SI_PARAM_PRIMITIVE_ID,
 190         SI_PARAM_VTX2_OFFSET,
 191         SI_PARAM_VTX3_OFFSET,
 192         SI_PARAM_VTX4_OFFSET,
 193         SI_PARAM_VTX5_OFFSET,
 194         SI_PARAM_GS_INSTANCE_ID,
 195
 196         /* PS only parameters */
 197         SI_PARAM_ALPHA_REF = SI_NUM_RESOURCE_PARAMS,
 198         SI_PARAM_PRIM_MASK,
 199         SI_PARAM_PERSP_SAMPLE,
 200         SI_PARAM_PERSP_CENTER,
 201         SI_PARAM_PERSP_CENTROID,
 202         SI_PARAM_PERSP_PULL_MODEL,
 203         SI_PARAM_LINEAR_SAMPLE,
 204         SI_PARAM_LINEAR_CENTER,
 205         SI_PARAM_LINEAR_CENTROID,
 206         SI_PARAM_LINE_STIPPLE_TEX,
 207         SI_PARAM_POS_X_FLOAT,
 208         SI_PARAM_POS_Y_FLOAT,
 209         SI_PARAM_POS_Z_FLOAT,
 210         SI_PARAM_POS_W_FLOAT,
 211         SI_PARAM_FRONT_FACE,
 212         SI_PARAM_ANCILLARY,
 213         SI_PARAM_SAMPLE_COVERAGE,
 214         SI_PARAM_POS_FIXED_PT,
 215
 216         /* CS only parameters */
 217         SI_PARAM_GRID_SIZE = SI_NUM_RESOURCE_PARAMS,
 218         SI_PARAM_BLOCK_ID,
 219         SI_PARAM_THREAD_ID,
 220
 221         SI_NUM_PARAMS = SI_PARAM_POS_FIXED_PT + 9, /* +8 for COLOR[0..1] */
 222 };
 223
 224 /* SI-specific system values. */
 225 enum {
 226         TGSI_SEMANTIC_DEFAULT_TESSOUTER_SI = TGSI_SEMANTIC_COUNT,
 227         TGSI_SEMANTIC_DEFAULT_TESSINNER_SI,
 228 };
 229
 230 struct si_shader;
 231
 232 /* A shader selector is a gallium CSO and contains shader variants and
 233  * binaries for one TGSI program. This can be shared by multiple contexts.
 234  */
 235 struct si_shader_selector {
 236         pipe_mutex              mutex;
 237         struct si_shader        *first_variant; /* immutable after the first variant */
 238         struct si_shader        *last_variant; /* mutable */
 239
 240         /* The compiled TGSI shader expecting a prolog and/or epilog (not
 241          * uploaded to a buffer).
 242          */
 243         struct si_shader        *main_shader_part;
 244
 245         struct tgsi_token       *tokens;
 246         struct pipe_stream_output_info  so;
 247         struct tgsi_shader_info         info;
 248
 249         /* PIPE_SHADER_[VERTEX|FRAGMENT|...] */
 250         unsigned        type;
 251
 252         /* GS parameters. */
 253         unsigned        esgs_itemsize;
 254         unsigned        gs_input_verts_per_prim;
 255         unsigned        gs_output_prim;
 256         unsigned        gs_max_out_vertices;
 257         unsigned        gs_num_invocations;
 258         unsigned        max_gs_stream; /* count - 1 */
 259         unsigned        gsvs_vertex_size;
 260         unsigned        max_gsvs_emit_size;
 261
 262         /* PS parameters. */
 263         unsigned        color_attr_index[2];
 264         unsigned        db_shader_control;
 265         /* Set 0xf or 0x0 (4 bits) per each written output.
 266          * ANDed with spi_shader_col_format.
 267          */
 268         unsigned        colors_written_4bit;
 269
 270         /* CS parameters */
 271         unsigned local_size;
 272
 273         /* masks of "get_unique_index" bits */
 274         uint64_t        outputs_written;
 275         uint32_t        patch_outputs_written;
 276 };
 277
 278 /* Valid shader configurations:
 279  *
 280  * API shaders       VS | TCS | TES | GS |pass| PS
 281  * are compiled as:     |     |     |    |thru|
 282  *                      |     |     |    |    |
 283  * Only VS & PS:     VS | --  | --  | -- | -- | PS
 284  * With GS:          ES | --  | --  | GS | VS | PS
 285  * With Tessel.:     LS | HS  | VS  | -- | -- | PS
 286  * With both:        LS | HS  | ES  | GS | VS | PS
 287  */
 288
 289 /* Common VS bits between the shader key and the prolog key. */
 290 struct si_vs_prolog_bits {
 291         unsigned        instance_divisors[SI_NUM_VERTEX_BUFFERS];
 292 };
 293
 294 /* Common VS bits between the shader key and the epilog key. */
 295 struct si_vs_epilog_bits {
 296         unsigned        export_prim_id:1; /* when PS needs it and GS is disabled */
 297         /* TODO:
 298          * - skip clipdist, culldist (including clipvertex code) exports based
 299          *   on which clip_plane_enable bits are set
 300          * - skip layer, viewport, clipdist, and culldist parameter exports
 301          *   if PS doesn't read them
 302          */
 303 };
 304
 305 /* Common TCS bits between the shader key and the epilog key. */
 306 struct si_tcs_epilog_bits {
 307         unsigned        prim_mode:3;
 308         uint64_t        inputs_to_copy;
 309 };
 310
 311 /* Common PS bits between the shader key and the prolog key. */
 312 struct si_ps_prolog_bits {
 313         unsigned        color_two_side:1;
 314         /* TODO: add a flatshade bit that skips interpolation for colors */
 315         unsigned        poly_stipple:1;
 316         unsigned        force_persample_interp:1;
 317         /* TODO:
 318          * - add force_center_interp if MSAA is disabled and centroid or
 319          *   sample are present
 320          * - add force_center_interp_bc_optimize to force center interpolation
 321          *   based on the bc_optimize SGPR bit if MSAA is enabled, centroid is
 322          *   present and sample isn't present.
 323          */
 324 };
 325
 326 /* Common PS bits between the shader key and the epilog key. */
 327 struct si_ps_epilog_bits {
 328         unsigned        spi_shader_col_format;
 329         unsigned        color_is_int8:8;
 330         unsigned        last_cbuf:3;
 331         unsigned        alpha_func:3;
 332         unsigned        alpha_to_one:1;
 333         unsigned        poly_line_smoothing:1;
 334         unsigned        clamp_color:1;
 335 };
 336
 337 union si_shader_part_key {
 338         struct {
 339                 struct si_vs_prolog_bits states;
 340                 unsigned        num_input_sgprs:5;
 341                 unsigned        last_input:4;
 342         } vs_prolog;
 343         struct {
 344                 struct si_vs_epilog_bits states;
 345                 unsigned        prim_id_param_offset:5;
 346         } vs_epilog;
 347         struct {
 348                 struct si_tcs_epilog_bits states;
 349         } tcs_epilog;
 350         struct {
 351                 struct si_ps_prolog_bits states;
 352                 unsigned        num_input_sgprs:5;
 353                 unsigned        num_input_vgprs:5;
 354                 /* Color interpolation and two-side color selection. */
 355                 unsigned        colors_read:8; /* color input components read */
 356                 unsigned        num_interp_inputs:5; /* BCOLOR is at this location */
 357                 unsigned        face_vgpr_index:5;
 358                 unsigned        wqm:1;
 359                 char            color_attr_index[2];
 360                 char            color_interp_vgpr_index[2]; /* -1 == constant */
 361         } ps_prolog;
 362         struct {
 363                 struct si_ps_epilog_bits states;
 364                 unsigned        colors_written:8;
 365                 unsigned        writes_z:1;
 366                 unsigned        writes_stencil:1;
 367                 unsigned        writes_samplemask:1;
 368         } ps_epilog;
 369 };
 370
 371 union si_shader_key {
 372         struct {
 373                 struct si_ps_prolog_bits prolog;
 374                 struct si_ps_epilog_bits epilog;
 375         } ps;
 376         struct {
 377                 struct si_vs_prolog_bits prolog;
 378                 struct si_vs_epilog_bits epilog;
 379                 unsigned        as_es:1; /* export shader */
 380                 unsigned        as_ls:1; /* local shader */
 381         } vs;
 382         struct {
 383                 struct si_tcs_epilog_bits epilog;
 384         } tcs; /* tessellation control shader */
 385         struct {
 386                 struct si_vs_epilog_bits epilog; /* same as VS */
 387                 unsigned        as_es:1; /* export shader */
 388         } tes; /* tessellation evaluation shader */
 389 };
 390
 391 struct si_shader_config {
 392         unsigned                        num_sgprs;
 393         unsigned                        num_vgprs;
 394         unsigned                        lds_size;
 395         unsigned                        spi_ps_input_ena;
 396         unsigned                        spi_ps_input_addr;
 397         unsigned                        float_mode;
 398         unsigned                        scratch_bytes_per_wave;
 399         unsigned                        rsrc1;
 400         unsigned                        rsrc2;
 401 };
 402
 403 /* GCN-specific shader info. */
 404 struct si_shader_info {
 405         ubyte                   vs_output_param_offset[SI_MAX_VS_OUTPUTS];
 406         ubyte                   num_input_sgprs;
 407         ubyte                   num_input_vgprs;
 408         char                    face_vgpr_index;
 409         bool                    uses_instanceid;
 410         ubyte                   nr_pos_exports;
 411         ubyte                   nr_param_exports;
 412 };
 413
 414 struct si_shader {
 415         struct si_shader_selector       *selector;
 416         struct si_shader                *next_variant;
 417
 418         struct si_shader_part           *prolog;
 419         struct si_shader_part           *epilog;
 420
 421         struct si_shader                *gs_copy_shader;
 422         struct si_pm4_state             *pm4;
 423         struct r600_resource            *bo;
 424         struct r600_resource            *scratch_bo;
 425         union si_shader_key             key;
 426         bool                            is_binary_shared;
 427         unsigned                        z_order;
 428
 429         /* The following data is all that's needed for binary shaders. */
 430         struct radeon_shader_binary     binary;
 431         struct si_shader_config         config;
 432         struct si_shader_info           info;
 433 };
 434
 435 struct si_shader_part {
 436         struct si_shader_part *next;
 437         union si_shader_part_key key;
 438         struct radeon_shader_binary binary;
 439         struct si_shader_config config;
 440 };
 441
 442 static inline struct tgsi_shader_info *si_get_vs_info(struct si_context *sctx)
 443 {
 444         if (sctx->gs_shader.cso)
 445                 return &sctx->gs_shader.cso->info;
 446         else if (sctx->tes_shader.cso)
 447                 return &sctx->tes_shader.cso->info;
 448         else if (sctx->vs_shader.cso)
 449                 return &sctx->vs_shader.cso->info;
 450         else
 451                 return NULL;
 452 }
 453
 454 static inline struct si_shader* si_get_vs_state(struct si_context *sctx)
 455 {
 456         if (sctx->gs_shader.current)
 457                 return sctx->gs_shader.current->gs_copy_shader;
 458         else if (sctx->tes_shader.current)
 459                 return sctx->tes_shader.current;
 460         else
 461                 return sctx->vs_shader.current;
 462 }
 463
 464 static inline bool si_vs_exports_prim_id(struct si_shader *shader)
 465 {
 466         if (shader->selector->type == PIPE_SHADER_VERTEX)
 467                 return shader->key.vs.epilog.export_prim_id;
 468         else if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
 469                 return shader->key.tes.epilog.export_prim_id;
 470         else
 471                 return false;
 472 }
 473
 474 /* si_shader.c */
 475 int si_compile_tgsi_shader(struct si_screen *sscreen,
 476                            LLVMTargetMachineRef tm,
 477                            struct si_shader *shader,
 478                            bool is_monolithic,
 479                            struct pipe_debug_callback *debug);
 480 int si_shader_create(struct si_screen *sscreen, LLVMTargetMachineRef tm,
 481                      struct si_shader *shader,
 482                      struct pipe_debug_callback *debug);
 483 void si_dump_shader_key(unsigned shader, union si_shader_key *key, FILE *f);
 484 int si_compile_llvm(struct si_screen *sscreen,
 485                     struct radeon_shader_binary *binary,
 486                     struct si_shader_config *conf,
 487                     LLVMTargetMachineRef tm,
 488                     LLVMModuleRef mod,
 489                     struct pipe_debug_callback *debug,
 490                     unsigned processor,
 491                     const char *name);
 492 void si_shader_destroy(struct si_shader *shader);
 493 unsigned si_shader_io_get_unique_index(unsigned semantic_name, unsigned index);
 494 int si_shader_binary_upload(struct si_screen *sscreen, struct si_shader *shader);
 495 void si_shader_dump(struct si_screen *sscreen, struct si_shader *shader,
 496                     struct pipe_debug_callback *debug, unsigned processor,
 497                     FILE *f);
 498 void si_shader_apply_scratch_relocs(struct si_context *sctx,
 499                         struct si_shader *shader,
 500                         struct si_shader_config *config,
 501                         uint64_t scratch_va);
 502 void si_shader_binary_read_config(struct radeon_shader_binary *binary,
 503                                   struct si_shader_config *conf,
 504                                   unsigned symbol_offset);
 505
 506 #endif