2 * Copyright 2012 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 * Tom Stellard <thomas.stellard@amd.com>
25 * Michel Dänzer <michel.daenzer@amd.com>
26 * Christian König <christian.koenig@amd.com>
29 /* How linking tessellation shader inputs and outputs works.
31 * Inputs and outputs between shaders are stored in a buffer. This buffer
32 * lives in LDS (typical case for tessellation), but it can also live
33 * in memory. Each input or output has a fixed location within a vertex.
34 * The highest used input or output determines the stride between vertices.
36 * Since tessellation is only enabled in the OpenGL core profile,
37 * only these semantics are valid for per-vertex data:
44 * CULLDIST0..1 (not implemented)
47 * For example, a shader only writing GENERIC0 has the output stride of 5.
49 * Only these semantics are valid for per-patch data:
57 * That's how independent shaders agree on input and output locations.
58 * The si_shader_io_get_unique_index function assigns the locations.
60 * Other required information for calculating the input and output addresses
61 * like the vertex stride, the patch stride, and the offsets where per-vertex
62 * and per-patch data start, is passed to the shader via user data SGPRs.
63 * The offsets and strides are calculated at draw time and aren't available
66 * The same approach should be used for linking ES->GS in the future.
72 #include <llvm-c/Core.h> /* LLVMModuleRef */
73 #include "tgsi/tgsi_scan.h"
76 struct radeon_shader_binary
;
77 struct radeon_shader_reloc
;
79 #define SI_SGPR_RW_BUFFERS 0 /* rings (& stream-out, VS only) */
80 #define SI_SGPR_CONST 2
81 #define SI_SGPR_SAMPLER 4
82 #define SI_SGPR_RESOURCE 6
83 #define SI_SGPR_VERTEX_BUFFER 8 /* VS only */
84 #define SI_SGPR_BASE_VERTEX 10 /* VS only */
85 #define SI_SGPR_START_INSTANCE 11 /* VS only */
86 #define SI_SGPR_LS_OUT_LAYOUT 12 /* VS(LS) only */
87 #define SI_SGPR_TCS_OUT_OFFSETS 8 /* TCS & TES only */
88 #define SI_SGPR_TCS_OUT_LAYOUT 9 /* TCS & TES only */
89 #define SI_SGPR_TCS_IN_LAYOUT 10 /* TCS only */
90 #define SI_SGPR_ALPHA_REF 8 /* PS only */
92 #define SI_VS_NUM_USER_SGPR 12
93 #define SI_LS_NUM_USER_SGPR 13
94 #define SI_TCS_NUM_USER_SGPR 11
95 #define SI_TES_NUM_USER_SGPR 10
96 #define SI_GS_NUM_USER_SGPR 8
97 #define SI_GSCOPY_NUM_USER_SGPR 4
98 #define SI_PS_NUM_USER_SGPR 9
100 /* LLVM function parameter indices */
101 #define SI_PARAM_RW_BUFFERS 0
102 #define SI_PARAM_CONST 1
103 #define SI_PARAM_SAMPLER 2
104 #define SI_PARAM_RESOURCE 3
106 /* VS only parameters */
107 #define SI_PARAM_VERTEX_BUFFER 4
108 #define SI_PARAM_BASE_VERTEX 5
109 #define SI_PARAM_START_INSTANCE 6
110 /* the other VS parameters are assigned dynamically */
112 /* Offsets where TCS outputs and TCS patch outputs live in LDS:
113 * [0:15] = TCS output patch0 offset / 16, max = NUM_PATCHES * 32 * 32
114 * [16:31] = TCS output patch0 offset for per-patch / 16, max = NUM_PATCHES*32*32* + 32*32
116 #define SI_PARAM_TCS_OUT_OFFSETS 4 /* for TCS & TES */
118 /* Layout of TCS outputs / TES inputs:
119 * [0:12] = stride between output patches in dwords, num_outputs * num_vertices * 4, max = 32*32*4
120 * [13:20] = stride between output vertices in dwords = num_inputs * 4, max = 32*4
121 * [26:31] = gl_PatchVerticesIn, max = 32
123 #define SI_PARAM_TCS_OUT_LAYOUT 5 /* for TCS & TES */
125 /* Layout of LS outputs / TCS inputs
126 * [0:12] = stride between patches in dwords = num_inputs * num_vertices * 4, max = 32*32*4
127 * [13:20] = stride between vertices in dwords = num_inputs * 4, max = 32*4
129 #define SI_PARAM_TCS_IN_LAYOUT 6 /* TCS only */
130 #define SI_PARAM_LS_OUT_LAYOUT 7 /* same value as TCS_IN_LAYOUT, LS only */
132 /* TCS only parameters. */
133 #define SI_PARAM_TESS_FACTOR_OFFSET 7
134 #define SI_PARAM_PATCH_ID 8
135 #define SI_PARAM_REL_IDS 9
137 /* GS only parameters */
138 #define SI_PARAM_GS2VS_OFFSET 4
139 #define SI_PARAM_GS_WAVE_ID 5
140 #define SI_PARAM_VTX0_OFFSET 6
141 #define SI_PARAM_VTX1_OFFSET 7
142 #define SI_PARAM_PRIMITIVE_ID 8
143 #define SI_PARAM_VTX2_OFFSET 9
144 #define SI_PARAM_VTX3_OFFSET 10
145 #define SI_PARAM_VTX4_OFFSET 11
146 #define SI_PARAM_VTX5_OFFSET 12
147 #define SI_PARAM_GS_INSTANCE_ID 13
149 /* PS only parameters */
150 #define SI_PARAM_ALPHA_REF 4
151 #define SI_PARAM_PRIM_MASK 5
152 #define SI_PARAM_PERSP_SAMPLE 6
153 #define SI_PARAM_PERSP_CENTER 7
154 #define SI_PARAM_PERSP_CENTROID 8
155 #define SI_PARAM_PERSP_PULL_MODEL 9
156 #define SI_PARAM_LINEAR_SAMPLE 10
157 #define SI_PARAM_LINEAR_CENTER 11
158 #define SI_PARAM_LINEAR_CENTROID 12
159 #define SI_PARAM_LINE_STIPPLE_TEX 13
160 #define SI_PARAM_POS_X_FLOAT 14
161 #define SI_PARAM_POS_Y_FLOAT 15
162 #define SI_PARAM_POS_Z_FLOAT 16
163 #define SI_PARAM_POS_W_FLOAT 17
164 #define SI_PARAM_FRONT_FACE 18
165 #define SI_PARAM_ANCILLARY 19
166 #define SI_PARAM_SAMPLE_COVERAGE 20
167 #define SI_PARAM_POS_FIXED_PT 21
169 #define SI_NUM_PARAMS (SI_PARAM_POS_FIXED_PT + 1)
173 struct si_shader_selector
{
174 struct si_shader
*current
;
176 struct tgsi_token
*tokens
;
177 struct pipe_stream_output_info so
;
178 struct tgsi_shader_info info
;
180 unsigned num_shaders
;
182 /* PIPE_SHADER_[VERTEX|FRAGMENT|...] */
185 unsigned gs_output_prim
;
186 unsigned gs_max_out_vertices
;
187 unsigned gs_num_invocations
;
188 unsigned gsvs_itemsize
;
190 /* masks of "get_unique_index" bits */
191 uint64_t inputs_read
;
192 uint64_t outputs_written
;
193 uint32_t patch_outputs_written
;
194 uint32_t ps_colors_written
;
197 /* Valid shader configurations:
199 * API shaders VS | TCS | TES | GS |pass| PS
200 * are compiled as: | | | |thru|
202 * Only VS & PS: VS | -- | -- | -- | -- | PS
203 * With GS: ES | -- | -- | GS | VS | PS
204 * With Tessel.: LS | HS | VS | -- | -- | PS
205 * With both: LS | HS | ES | GS | VS | PS
208 union si_shader_key
{
210 unsigned export_16bpc
:8;
211 unsigned last_cbuf
:3;
212 unsigned color_two_side
:1;
213 unsigned alpha_func
:3;
214 unsigned alpha_to_one
:1;
215 unsigned poly_stipple
:1;
216 unsigned poly_line_smoothing
:1;
219 unsigned instance_divisors
[SI_NUM_VERTEX_BUFFERS
];
220 /* Mask of "get_unique_index" bits - which outputs are read
221 * by the next stage (needed by ES).
222 * This describes how outputs are laid out in memory. */
223 uint64_t es_enabled_outputs
;
224 unsigned as_es
:1; /* export shader */
225 unsigned as_ls
:1; /* local shader */
226 unsigned export_prim_id
; /* when PS needs it and GS is disabled */
229 unsigned prim_mode
:3;
230 } tcs
; /* tessellation control shader */
232 /* Mask of "get_unique_index" bits - which outputs are read
233 * by the next stage (needed by ES).
234 * This describes how outputs are laid out in memory. */
235 uint64_t es_enabled_outputs
;
236 unsigned as_es
:1; /* export shader */
237 unsigned export_prim_id
; /* when PS needs it and GS is disabled */
238 } tes
; /* tessellation evaluation shader */
242 struct si_shader_selector
*selector
;
243 struct si_shader
*next_variant
;
245 struct si_shader
*gs_copy_shader
;
246 struct si_pm4_state
*pm4
;
247 struct r600_resource
*bo
;
248 struct r600_resource
*scratch_bo
;
249 struct radeon_shader_binary binary
;
253 unsigned spi_ps_input_ena
;
255 unsigned scratch_bytes_per_wave
;
256 unsigned spi_shader_col_format
;
257 unsigned spi_shader_z_format
;
258 unsigned db_shader_control
;
259 unsigned cb_shader_mask
;
260 union si_shader_key key
;
263 unsigned vs_output_param_offset
[PIPE_MAX_SHADER_OUTPUTS
];
264 unsigned ps_input_param_offset
[PIPE_MAX_SHADER_INPUTS
];
265 unsigned ps_input_interpolate
[PIPE_MAX_SHADER_INPUTS
];
266 bool uses_instanceid
;
267 unsigned nr_pos_exports
;
268 unsigned nr_param_exports
;
269 bool is_gs_copy_shader
;
270 bool dx10_clamp_mode
; /* convert NaNs to 0 */
276 static inline struct tgsi_shader_info
*si_get_vs_info(struct si_context
*sctx
)
279 return &sctx
->gs_shader
->info
;
280 else if (sctx
->tes_shader
)
281 return &sctx
->tes_shader
->info
;
282 else if (sctx
->vs_shader
)
283 return &sctx
->vs_shader
->info
;
288 static inline struct si_shader
* si_get_vs_state(struct si_context
*sctx
)
291 return sctx
->gs_shader
->current
->gs_copy_shader
;
292 else if (sctx
->tes_shader
)
293 return sctx
->tes_shader
->current
;
295 return sctx
->vs_shader
->current
;
298 static inline bool si_vs_exports_prim_id(struct si_shader
*shader
)
300 if (shader
->selector
->type
== PIPE_SHADER_VERTEX
)
301 return shader
->key
.vs
.export_prim_id
;
302 else if (shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
)
303 return shader
->key
.tes
.export_prim_id
;
308 /* radeonsi_shader.c */
309 int si_shader_create(struct si_screen
*sscreen
, LLVMTargetMachineRef tm
,
310 struct si_shader
*shader
);
311 void si_dump_shader_key(unsigned shader
, union si_shader_key
*key
, FILE *f
);
312 int si_compile_llvm(struct si_screen
*sscreen
, struct si_shader
*shader
,
313 LLVMTargetMachineRef tm
, LLVMModuleRef mod
);
314 void si_shader_destroy(struct pipe_context
*ctx
, struct si_shader
*shader
);
315 unsigned si_shader_io_get_unique_index(unsigned semantic_name
, unsigned index
);
316 int si_shader_binary_upload(struct si_screen
*sscreen
, struct si_shader
*shader
);
317 int si_shader_binary_read(struct si_screen
*sscreen
, struct si_shader
*shader
);
318 void si_shader_apply_scratch_relocs(struct si_context
*sctx
,
319 struct si_shader
*shader
,
320 uint64_t scratch_va
);
321 void si_shader_binary_read_config(const struct si_screen
*sscreen
,
322 struct si_shader
*shader
,
323 unsigned symbol_offset
);