2 * Copyright 2012 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 * Tom Stellard <thomas.stellard@amd.com>
25 * Michel Dänzer <michel.daenzer@amd.com>
26 * Christian König <christian.koenig@amd.com>
29 /* How linking shader inputs and outputs between vertex, tessellation, and
30 * geometry shaders works.
32 * Inputs and outputs between shaders are stored in a buffer. This buffer
33 * lives in LDS (typical case for tessellation), but it can also live
34 * in memory (ESGS). Each input or output has a fixed location within a vertex.
35 * The highest used input or output determines the stride between vertices.
37 * Since GS and tessellation are only possible in the OpenGL core profile,
38 * only these semantics are valid for per-vertex data:
45 * CULLDIST0..1 (not implemented)
48 * For example, a shader only writing GENERIC0 has the output stride of 5.
50 * Only these semantics are valid for per-patch data:
58 * That's how independent shaders agree on input and output locations.
59 * The si_shader_io_get_unique_index function assigns the locations.
61 * For tessellation, other required information for calculating the input and
62 * output addresses like the vertex stride, the patch stride, and the offsets
63 * where per-vertex and per-patch data start, is passed to the shader via
64 * user data SGPRs. The offsets and strides are calculated at draw time and
65 * aren't available at compile time.
71 #include <llvm-c/Core.h> /* LLVMModuleRef */
72 #include <llvm-c/TargetMachine.h>
73 #include "tgsi/tgsi_scan.h"
74 #include "util/u_queue.h"
77 struct radeon_shader_binary
;
78 struct radeon_shader_reloc
;
80 #define SI_MAX_VS_OUTPUTS 40
82 /* SGPR user data indices */
84 SI_SGPR_RW_BUFFERS
, /* rings (& stream-out, VS only) */
85 SI_SGPR_RW_BUFFERS_HI
,
86 SI_SGPR_CONST_BUFFERS
,
87 SI_SGPR_CONST_BUFFERS_HI
,
88 SI_SGPR_SAMPLERS
, /* images & sampler states interleaved */
92 SI_SGPR_SHADER_BUFFERS
,
93 SI_SGPR_SHADER_BUFFERS_HI
,
94 SI_NUM_RESOURCE_SGPRS
,
97 SI_SGPR_VERTEX_BUFFERS
= SI_NUM_RESOURCE_SGPRS
,
98 SI_SGPR_VERTEX_BUFFERS_HI
,
100 SI_SGPR_START_INSTANCE
,
105 SI_SGPR_VS_STATE_BITS
= SI_ES_NUM_USER_SGPR
,
109 SI_SGPR_LS_OUT_LAYOUT
= SI_ES_NUM_USER_SGPR
,
112 /* both TCS and TES */
113 SI_SGPR_TCS_OFFCHIP_LAYOUT
= SI_NUM_RESOURCE_SGPRS
,
114 SI_TES_NUM_USER_SGPR
,
117 SI_SGPR_TCS_OUT_OFFSETS
= SI_TES_NUM_USER_SGPR
,
118 SI_SGPR_TCS_OUT_LAYOUT
,
119 SI_SGPR_TCS_IN_LAYOUT
,
120 SI_TCS_NUM_USER_SGPR
,
123 SI_GS_NUM_USER_SGPR
= SI_NUM_RESOURCE_SGPRS
,
124 SI_GSCOPY_NUM_USER_SGPR
= SI_SGPR_RW_BUFFERS_HI
+ 1,
127 SI_SGPR_ALPHA_REF
= SI_NUM_RESOURCE_SGPRS
,
131 SI_SGPR_GRID_SIZE
= SI_NUM_RESOURCE_SGPRS
,
132 SI_SGPR_BLOCK_SIZE
= SI_SGPR_GRID_SIZE
+ 3,
133 SI_CS_NUM_USER_SGPR
= SI_SGPR_BLOCK_SIZE
+ 3
136 /* LLVM function parameter indices */
139 SI_PARAM_CONST_BUFFERS
,
142 SI_PARAM_SHADER_BUFFERS
,
143 SI_NUM_RESOURCE_PARAMS
,
145 /* VS only parameters */
146 SI_PARAM_VERTEX_BUFFERS
= SI_NUM_RESOURCE_PARAMS
,
147 SI_PARAM_BASE_VERTEX
,
148 SI_PARAM_START_INSTANCE
,
150 /* [0] = clamp vertex color, VS as VS only */
151 SI_PARAM_VS_STATE_BITS
,
152 /* same value as TCS_IN_LAYOUT, VS as LS only */
153 SI_PARAM_LS_OUT_LAYOUT
= SI_PARAM_DRAWID
+ 1,
154 /* the other VS parameters are assigned dynamically */
156 /* Layout of TCS outputs in the offchip buffer
157 * [0:8] = the number of patches per threadgroup.
158 * [9:15] = the number of output vertices per patch.
159 * [16:31] = the offset of per patch attributes in the buffer in bytes.
161 SI_PARAM_TCS_OFFCHIP_LAYOUT
= SI_NUM_RESOURCE_PARAMS
, /* for TCS & TES */
163 /* TCS only parameters. */
165 /* Offsets where TCS outputs and TCS patch outputs live in LDS:
166 * [0:15] = TCS output patch0 offset / 16, max = NUM_PATCHES * 32 * 32
167 * [16:31] = TCS output patch0 offset for per-patch / 16, max = NUM_PATCHES*32*32* + 32*32
169 SI_PARAM_TCS_OUT_OFFSETS
,
171 /* Layout of TCS outputs / TES inputs:
172 * [0:12] = stride between output patches in dwords, num_outputs * num_vertices * 4, max = 32*32*4
173 * [13:20] = stride between output vertices in dwords = num_inputs * 4, max = 32*4
174 * [26:31] = gl_PatchVerticesIn, max = 32
176 SI_PARAM_TCS_OUT_LAYOUT
,
178 /* Layout of LS outputs / TCS inputs
179 * [0:12] = stride between patches in dwords = num_inputs * num_vertices * 4, max = 32*32*4
180 * [13:20] = stride between vertices in dwords = num_inputs * 4, max = 32*4
182 SI_PARAM_TCS_IN_LAYOUT
,
185 SI_PARAM_TESS_FACTOR_OFFSET
,
189 /* GS only parameters */
190 SI_PARAM_GS2VS_OFFSET
= SI_NUM_RESOURCE_PARAMS
,
192 SI_PARAM_VTX0_OFFSET
,
193 SI_PARAM_VTX1_OFFSET
,
194 SI_PARAM_PRIMITIVE_ID
,
195 SI_PARAM_VTX2_OFFSET
,
196 SI_PARAM_VTX3_OFFSET
,
197 SI_PARAM_VTX4_OFFSET
,
198 SI_PARAM_VTX5_OFFSET
,
199 SI_PARAM_GS_INSTANCE_ID
,
201 /* PS only parameters */
202 SI_PARAM_ALPHA_REF
= SI_NUM_RESOURCE_PARAMS
,
204 SI_PARAM_PERSP_SAMPLE
,
205 SI_PARAM_PERSP_CENTER
,
206 SI_PARAM_PERSP_CENTROID
,
207 SI_PARAM_PERSP_PULL_MODEL
,
208 SI_PARAM_LINEAR_SAMPLE
,
209 SI_PARAM_LINEAR_CENTER
,
210 SI_PARAM_LINEAR_CENTROID
,
211 SI_PARAM_LINE_STIPPLE_TEX
,
212 SI_PARAM_POS_X_FLOAT
,
213 SI_PARAM_POS_Y_FLOAT
,
214 SI_PARAM_POS_Z_FLOAT
,
215 SI_PARAM_POS_W_FLOAT
,
218 SI_PARAM_SAMPLE_COVERAGE
,
219 SI_PARAM_POS_FIXED_PT
,
221 /* CS only parameters */
222 SI_PARAM_GRID_SIZE
= SI_NUM_RESOURCE_PARAMS
,
227 SI_NUM_PARAMS
= SI_PARAM_POS_FIXED_PT
+ 9, /* +8 for COLOR[0..1] */
230 /* SI-specific system values. */
232 TGSI_SEMANTIC_DEFAULT_TESSOUTER_SI
= TGSI_SEMANTIC_COUNT
,
233 TGSI_SEMANTIC_DEFAULT_TESSINNER_SI
,
236 /* For VS shader key fix_fetch. */
238 SI_FIX_FETCH_NONE
= 0,
239 SI_FIX_FETCH_A2_SNORM
,
240 SI_FIX_FETCH_A2_SSCALED
,
241 SI_FIX_FETCH_A2_SINT
,
242 SI_FIX_FETCH_RGBA_32_UNORM
,
243 SI_FIX_FETCH_RGBX_32_UNORM
,
244 SI_FIX_FETCH_RGBA_32_SNORM
,
245 SI_FIX_FETCH_RGBX_32_SNORM
,
246 SI_FIX_FETCH_RGBA_32_USCALED
,
247 SI_FIX_FETCH_RGBA_32_SSCALED
,
248 SI_FIX_FETCH_RGBA_32_FIXED
,
249 SI_FIX_FETCH_RGBX_32_FIXED
,
250 SI_FIX_FETCH_RG_64_FLOAT
,
251 SI_FIX_FETCH_RGB_64_FLOAT
,
252 SI_FIX_FETCH_RGBA_64_FLOAT
,
253 SI_FIX_FETCH_RGB_8
, /* A = 1.0 */
254 SI_FIX_FETCH_RGB_8_INT
, /* A = 1 */
256 SI_FIX_FETCH_RGB_16_INT
,
261 /* State of the context creating the shader object. */
262 struct si_compiler_ctx_state
{
263 /* Should only be used by si_init_shader_selector_async and
264 * si_build_shader_variant if thread_index == -1 (non-threaded). */
265 LLVMTargetMachineRef tm
;
267 /* Used if thread_index == -1 or if debug.async is true. */
268 struct pipe_debug_callback debug
;
270 /* Used for creating the log string for gallium/ddebug. */
271 bool is_debug_context
;
274 /* A shader selector is a gallium CSO and contains shader variants and
275 * binaries for one TGSI program. This can be shared by multiple contexts.
277 struct si_shader_selector
{
278 struct si_screen
*screen
;
279 struct util_queue_fence ready
;
280 struct si_compiler_ctx_state compiler_ctx_state
;
283 struct si_shader
*first_variant
; /* immutable after the first variant */
284 struct si_shader
*last_variant
; /* mutable */
286 /* The compiled TGSI shader expecting a prolog and/or epilog (not
287 * uploaded to a buffer).
289 struct si_shader
*main_shader_part
;
291 struct si_shader
*gs_copy_shader
;
293 struct tgsi_token
*tokens
;
294 struct pipe_stream_output_info so
;
295 struct tgsi_shader_info info
;
297 /* PIPE_SHADER_[VERTEX|FRAGMENT|...] */
301 unsigned esgs_itemsize
;
302 unsigned gs_input_verts_per_prim
;
303 unsigned gs_output_prim
;
304 unsigned gs_max_out_vertices
;
305 unsigned gs_num_invocations
;
306 unsigned max_gs_stream
; /* count - 1 */
307 unsigned gsvs_vertex_size
;
308 unsigned max_gsvs_emit_size
;
311 unsigned color_attr_index
[2];
312 unsigned db_shader_control
;
313 /* Set 0xf or 0x0 (4 bits) per each written output.
314 * ANDed with spi_shader_col_format.
316 unsigned colors_written_4bit
;
321 uint64_t outputs_written
; /* "get_unique_index" bits */
322 uint32_t patch_outputs_written
; /* "get_unique_index" bits */
323 uint32_t outputs_written2
; /* "get_unique_index2" bits */
325 uint64_t inputs_read
; /* "get_unique_index" bits */
326 uint32_t inputs_read2
; /* "get_unique_index2" bits */
329 /* Valid shader configurations:
331 * API shaders VS | TCS | TES | GS |pass| PS
332 * are compiled as: | | | |thru|
334 * Only VS & PS: VS | -- | -- | -- | -- | PS
335 * With GS: ES | -- | -- | GS | VS | PS
336 * With Tessel.: LS | HS | VS | -- | -- | PS
337 * With both: LS | HS | ES | GS | VS | PS
340 /* Common VS bits between the shader key and the prolog key. */
341 struct si_vs_prolog_bits
{
342 unsigned instance_divisors
[SI_NUM_VERTEX_BUFFERS
];
345 /* Common VS bits between the shader key and the epilog key. */
346 struct si_vs_epilog_bits
{
347 unsigned export_prim_id
:1; /* when PS needs it and GS is disabled */
350 /* Common TCS bits between the shader key and the epilog key. */
351 struct si_tcs_epilog_bits
{
352 unsigned prim_mode
:3;
355 struct si_gs_prolog_bits
{
356 unsigned tri_strip_adj_fix
:1;
359 /* Common PS bits between the shader key and the prolog key. */
360 struct si_ps_prolog_bits
{
361 unsigned color_two_side
:1;
362 unsigned flatshade_colors
:1;
363 unsigned poly_stipple
:1;
364 unsigned force_persp_sample_interp
:1;
365 unsigned force_linear_sample_interp
:1;
366 unsigned force_persp_center_interp
:1;
367 unsigned force_linear_center_interp
:1;
368 unsigned bc_optimize_for_persp
:1;
369 unsigned bc_optimize_for_linear
:1;
372 /* Common PS bits between the shader key and the epilog key. */
373 struct si_ps_epilog_bits
{
374 unsigned spi_shader_col_format
;
375 unsigned color_is_int8
:8;
376 unsigned last_cbuf
:3;
377 unsigned alpha_func
:3;
378 unsigned alpha_to_one
:1;
379 unsigned poly_line_smoothing
:1;
380 unsigned clamp_color
:1;
383 union si_shader_part_key
{
385 struct si_vs_prolog_bits states
;
386 unsigned num_input_sgprs
:5;
387 unsigned last_input
:4;
390 struct si_vs_epilog_bits states
;
391 unsigned prim_id_param_offset
:5;
394 struct si_tcs_epilog_bits states
;
397 struct si_gs_prolog_bits states
;
400 struct si_ps_prolog_bits states
;
401 unsigned num_input_sgprs
:5;
402 unsigned num_input_vgprs
:5;
403 /* Color interpolation and two-side color selection. */
404 unsigned colors_read
:8; /* color input components read */
405 unsigned num_interp_inputs
:5; /* BCOLOR is at this location */
406 unsigned face_vgpr_index
:5;
408 char color_attr_index
[2];
409 char color_interp_vgpr_index
[2]; /* -1 == constant */
412 struct si_ps_epilog_bits states
;
413 unsigned colors_written
:8;
415 unsigned writes_stencil
:1;
416 unsigned writes_samplemask
:1;
420 struct si_shader_key
{
421 /* Prolog and epilog flags. */
424 struct si_ps_prolog_bits prolog
;
425 struct si_ps_epilog_bits epilog
;
428 struct si_vs_prolog_bits prolog
;
429 struct si_vs_epilog_bits epilog
;
432 struct si_tcs_epilog_bits epilog
;
433 } tcs
; /* tessellation control shader */
435 struct si_vs_epilog_bits epilog
; /* same as VS */
436 } tes
; /* tessellation evaluation shader */
438 struct si_gs_prolog_bits prolog
;
442 /* These two are initially set according to the NEXT_SHADER property,
443 * or guessed if the property doesn't seem correct.
445 unsigned as_es
:1; /* export shader */
446 unsigned as_ls
:1; /* local shader */
448 /* Flags for monolithic compilation only. */
451 /* One byte for every input: SI_FIX_FETCH_* enums. */
452 uint8_t fix_fetch
[SI_MAX_ATTRIBS
];
455 uint64_t inputs_to_copy
; /* for fixed-func TCS */
459 /* Optimization flags for asynchronous compilation only. */
462 uint64_t kill_outputs
; /* "get_unique_index" bits */
463 uint32_t kill_outputs2
; /* "get_unique_index2" bits */
464 unsigned clip_disable
:1;
465 } hw_vs
; /* HW VS (it can be VS, TES, GS) */
469 struct si_shader_config
{
472 unsigned spilled_sgprs
;
473 unsigned spilled_vgprs
;
474 unsigned private_mem_vgprs
;
476 unsigned spi_ps_input_ena
;
477 unsigned spi_ps_input_addr
;
479 unsigned scratch_bytes_per_wave
;
485 /* SPI_PS_INPUT_CNTL_i.OFFSET[0:4] */
486 EXP_PARAM_OFFSET_0
= 0,
487 EXP_PARAM_OFFSET_31
= 31,
488 /* SPI_PS_INPUT_CNTL_i.DEFAULT_VAL[0:1] */
489 EXP_PARAM_DEFAULT_VAL_0000
= 64,
490 EXP_PARAM_DEFAULT_VAL_0001
,
491 EXP_PARAM_DEFAULT_VAL_1110
,
492 EXP_PARAM_DEFAULT_VAL_1111
,
493 EXP_PARAM_UNDEFINED
= 255,
496 /* GCN-specific shader info. */
497 struct si_shader_info
{
498 ubyte vs_output_param_offset
[SI_MAX_VS_OUTPUTS
];
499 ubyte num_input_sgprs
;
500 ubyte num_input_vgprs
;
501 char face_vgpr_index
;
502 bool uses_instanceid
;
503 ubyte nr_pos_exports
;
504 ubyte nr_param_exports
;
508 struct si_compiler_ctx_state compiler_ctx_state
;
510 struct si_shader_selector
*selector
;
511 struct si_shader
*next_variant
;
513 struct si_shader_part
*prolog
;
514 struct si_shader_part
*epilog
;
516 struct si_pm4_state
*pm4
;
517 struct r600_resource
*bo
;
518 struct r600_resource
*scratch_bo
;
519 struct si_shader_key key
;
520 struct util_queue_fence optimized_ready
;
521 bool compilation_failed
;
524 bool is_binary_shared
;
525 bool is_gs_copy_shader
;
527 /* The following data is all that's needed for binary shaders. */
528 struct radeon_shader_binary binary
;
529 struct si_shader_config config
;
530 struct si_shader_info info
;
532 /* Shader key + LLVM IR + disassembly + statistics.
533 * Generated for debug contexts only.
536 size_t shader_log_size
;
539 struct si_shader_part
{
540 struct si_shader_part
*next
;
541 union si_shader_part_key key
;
542 struct radeon_shader_binary binary
;
543 struct si_shader_config config
;
548 si_generate_gs_copy_shader(struct si_screen
*sscreen
,
549 LLVMTargetMachineRef tm
,
550 struct si_shader_selector
*gs_selector
,
551 struct pipe_debug_callback
*debug
);
552 int si_compile_tgsi_shader(struct si_screen
*sscreen
,
553 LLVMTargetMachineRef tm
,
554 struct si_shader
*shader
,
556 struct pipe_debug_callback
*debug
);
557 int si_shader_create(struct si_screen
*sscreen
, LLVMTargetMachineRef tm
,
558 struct si_shader
*shader
,
559 struct pipe_debug_callback
*debug
);
560 int si_compile_llvm(struct si_screen
*sscreen
,
561 struct radeon_shader_binary
*binary
,
562 struct si_shader_config
*conf
,
563 LLVMTargetMachineRef tm
,
565 struct pipe_debug_callback
*debug
,
568 void si_shader_destroy(struct si_shader
*shader
);
569 unsigned si_shader_io_get_unique_index(unsigned semantic_name
, unsigned index
);
570 unsigned si_shader_io_get_unique_index2(unsigned name
, unsigned index
);
571 int si_shader_binary_upload(struct si_screen
*sscreen
, struct si_shader
*shader
);
572 void si_shader_dump(struct si_screen
*sscreen
, struct si_shader
*shader
,
573 struct pipe_debug_callback
*debug
, unsigned processor
,
574 FILE *f
, bool check_debug_option
);
575 void si_multiwave_lds_size_workaround(struct si_screen
*sscreen
,
577 void si_shader_apply_scratch_relocs(struct si_context
*sctx
,
578 struct si_shader
*shader
,
579 struct si_shader_config
*config
,
580 uint64_t scratch_va
);
581 void si_shader_binary_read_config(struct radeon_shader_binary
*binary
,
582 struct si_shader_config
*conf
,
583 unsigned symbol_offset
);
584 unsigned si_get_spi_shader_z_format(bool writes_z
, bool writes_stencil
,
585 bool writes_samplemask
);
586 const char *si_get_shader_name(struct si_shader
*shader
, unsigned processor
);