src/gallium/drivers/radeonsi/si_shader.h

   1 /*
   2  * Copyright 2012 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Tom Stellard <thomas.stellard@amd.com>
  25  *      Michel Dänzer <michel.daenzer@amd.com>
  26  *      Christian König <christian.koenig@amd.com>
  27  */
  28
  29 /* How linking shader inputs and outputs between vertex, tessellation, and
  30  * geometry shaders works.
  31  *
  32  * Inputs and outputs between shaders are stored in a buffer. This buffer
  33  * lives in LDS (typical case for tessellation), but it can also live
  34  * in memory (ESGS). Each input or output has a fixed location within a vertex.
  35  * The highest used input or output determines the stride between vertices.
  36  *
  37  * Since GS and tessellation are only possible in the OpenGL core profile,
  38  * only these semantics are valid for per-vertex data:
  39  *
  40  *   Name             Location
  41  *
  42  *   POSITION         0
  43  *   PSIZE            1
  44  *   CLIPDIST0..1     2..3
  45  *   CULLDIST0..1     (not implemented)
  46  *   GENERIC0..31     4..35
  47  *
  48  * For example, a shader only writing GENERIC0 has the output stride of 5.
  49  *
  50  * Only these semantics are valid for per-patch data:
  51  *
  52  *   Name             Location
  53  *
  54  *   TESSOUTER        0
  55  *   TESSINNER        1
  56  *   PATCH0..29       2..31
  57  *
  58  * That's how independent shaders agree on input and output locations.
  59  * The si_shader_io_get_unique_index function assigns the locations.
  60  *
  61  * For tessellation, other required information for calculating the input and
  62  * output addresses like the vertex stride, the patch stride, and the offsets
  63  * where per-vertex and per-patch data start, is passed to the shader via
  64  * user data SGPRs. The offsets and strides are calculated at draw time and
  65  * aren't available at compile time.
  66  */
  67
  68 #ifndef SI_SHADER_H
  69 #define SI_SHADER_H
  70
  71 #include <llvm-c/Core.h> /* LLVMModuleRef */
  72 #include "tgsi/tgsi_scan.h"
  73 #include "si_state.h"
  74
  75 struct radeon_shader_binary;
  76 struct radeon_shader_reloc;
  77
  78 #define SI_MAX_VS_OUTPUTS       40
  79
  80 /* SGPR user data indices */
  81 enum {
  82         SI_SGPR_RW_BUFFERS,  /* rings (& stream-out, VS only) */
  83         SI_SGPR_RW_BUFFERS_HI,
  84         SI_SGPR_CONST_BUFFERS,
  85         SI_SGPR_CONST_BUFFERS_HI,
  86         SI_SGPR_SAMPLERS,  /* images & sampler states interleaved */
  87         SI_SGPR_SAMPLERS_HI,
  88         SI_SGPR_IMAGES,
  89         SI_SGPR_IMAGES_HI,
  90         SI_SGPR_SHADER_BUFFERS,
  91         SI_SGPR_SHADER_BUFFERS_HI,
  92         SI_NUM_RESOURCE_SGPRS,
  93
  94         /* all VS variants */
  95         SI_SGPR_VERTEX_BUFFERS  = SI_NUM_RESOURCE_SGPRS,
  96         SI_SGPR_VERTEX_BUFFERS_HI,
  97         SI_SGPR_BASE_VERTEX,
  98         SI_SGPR_START_INSTANCE,
  99         SI_ES_NUM_USER_SGPR,
 100
 101         /* hw VS only */
 102         SI_SGPR_VS_STATE_BITS   = SI_ES_NUM_USER_SGPR,
 103         SI_VS_NUM_USER_SGPR,
 104
 105         /* hw LS only */
 106         SI_SGPR_LS_OUT_LAYOUT   = SI_ES_NUM_USER_SGPR,
 107         SI_LS_NUM_USER_SGPR,
 108
 109         /* both TCS and TES */
 110         SI_SGPR_TCS_OUT_OFFSETS = SI_NUM_RESOURCE_SGPRS,
 111         SI_SGPR_TCS_OUT_LAYOUT,
 112         SI_TES_NUM_USER_SGPR,
 113
 114         /* TCS only */
 115         SI_SGPR_TCS_IN_LAYOUT = SI_TES_NUM_USER_SGPR,
 116         SI_TCS_NUM_USER_SGPR,
 117
 118         /* GS limits */
 119         SI_GS_NUM_USER_SGPR = SI_NUM_RESOURCE_SGPRS,
 120         SI_GSCOPY_NUM_USER_SGPR = SI_SGPR_CONST_BUFFERS_HI + 1,
 121
 122         /* PS only */
 123         SI_SGPR_ALPHA_REF       = SI_NUM_RESOURCE_SGPRS,
 124         SI_PS_NUM_USER_SGPR,
 125 };
 126
 127 /* LLVM function parameter indices */
 128 enum {
 129         SI_PARAM_RW_BUFFERS,
 130         SI_PARAM_CONST_BUFFERS,
 131         SI_PARAM_SAMPLERS,
 132         SI_PARAM_IMAGES,
 133         SI_PARAM_SHADER_BUFFERS,
 134         SI_NUM_RESOURCE_PARAMS,
 135
 136         /* VS only parameters */
 137         SI_PARAM_VERTEX_BUFFERS = SI_NUM_RESOURCE_PARAMS,
 138         SI_PARAM_BASE_VERTEX,
 139         SI_PARAM_START_INSTANCE,
 140         /* [0] = clamp vertex color */
 141         SI_PARAM_VS_STATE_BITS,
 142         /* the other VS parameters are assigned dynamically */
 143
 144         /* Offsets where TCS outputs and TCS patch outputs live in LDS:
 145          *   [0:15] = TCS output patch0 offset / 16, max = NUM_PATCHES * 32 * 32
 146          *   [16:31] = TCS output patch0 offset for per-patch / 16, max = NUM_PATCHES*32*32* + 32*32
 147          */
 148         SI_PARAM_TCS_OUT_OFFSETS = SI_NUM_RESOURCE_PARAMS, /* for TCS & TES */
 149
 150         /* Layout of TCS outputs / TES inputs:
 151          *   [0:12] = stride between output patches in dwords, num_outputs * num_vertices * 4, max = 32*32*4
 152          *   [13:20] = stride between output vertices in dwords = num_inputs * 4, max = 32*4
 153          *   [26:31] = gl_PatchVerticesIn, max = 32
 154          */
 155         SI_PARAM_TCS_OUT_LAYOUT, /* for TCS & TES */
 156
 157         /* Layout of LS outputs / TCS inputs
 158          *   [0:12] = stride between patches in dwords = num_inputs * num_vertices * 4, max = 32*32*4
 159          *   [13:20] = stride between vertices in dwords = num_inputs * 4, max = 32*4
 160          */
 161         SI_PARAM_TCS_IN_LAYOUT,  /* TCS only */
 162         SI_PARAM_LS_OUT_LAYOUT,  /* same value as TCS_IN_LAYOUT, LS only */
 163
 164         /* TCS only parameters. */
 165         SI_PARAM_TESS_FACTOR_OFFSET = SI_PARAM_TCS_IN_LAYOUT + 1,
 166         SI_PARAM_PATCH_ID,
 167         SI_PARAM_REL_IDS,
 168
 169         /* GS only parameters */
 170         SI_PARAM_GS2VS_OFFSET = SI_NUM_RESOURCE_PARAMS,
 171         SI_PARAM_GS_WAVE_ID,
 172         SI_PARAM_VTX0_OFFSET,
 173         SI_PARAM_VTX1_OFFSET,
 174         SI_PARAM_PRIMITIVE_ID,
 175         SI_PARAM_VTX2_OFFSET,
 176         SI_PARAM_VTX3_OFFSET,
 177         SI_PARAM_VTX4_OFFSET,
 178         SI_PARAM_VTX5_OFFSET,
 179         SI_PARAM_GS_INSTANCE_ID,
 180
 181         /* PS only parameters */
 182         SI_PARAM_ALPHA_REF = SI_NUM_RESOURCE_PARAMS,
 183         SI_PARAM_PRIM_MASK,
 184         SI_PARAM_PERSP_SAMPLE,
 185         SI_PARAM_PERSP_CENTER,
 186         SI_PARAM_PERSP_CENTROID,
 187         SI_PARAM_PERSP_PULL_MODEL,
 188         SI_PARAM_LINEAR_SAMPLE,
 189         SI_PARAM_LINEAR_CENTER,
 190         SI_PARAM_LINEAR_CENTROID,
 191         SI_PARAM_LINE_STIPPLE_TEX,
 192         SI_PARAM_POS_X_FLOAT,
 193         SI_PARAM_POS_Y_FLOAT,
 194         SI_PARAM_POS_Z_FLOAT,
 195         SI_PARAM_POS_W_FLOAT,
 196         SI_PARAM_FRONT_FACE,
 197         SI_PARAM_ANCILLARY,
 198         SI_PARAM_SAMPLE_COVERAGE,
 199         SI_PARAM_POS_FIXED_PT,
 200
 201         SI_NUM_PARAMS = SI_PARAM_POS_FIXED_PT + 9, /* +8 for COLOR[0..1] */
 202 };
 203
 204 struct si_shader;
 205
 206 /* A shader selector is a gallium CSO and contains shader variants and
 207  * binaries for one TGSI program. This can be shared by multiple contexts.
 208  */
 209 struct si_shader_selector {
 210         pipe_mutex              mutex;
 211         struct si_shader        *first_variant; /* immutable after the first variant */
 212         struct si_shader        *last_variant; /* mutable */
 213
 214         /* The compiled TGSI shader expecting a prolog and/or epilog (not
 215          * uploaded to a buffer).
 216          */
 217         struct si_shader        *main_shader_part;
 218
 219         struct tgsi_token       *tokens;
 220         struct pipe_stream_output_info  so;
 221         struct tgsi_shader_info         info;
 222
 223         /* PIPE_SHADER_[VERTEX|FRAGMENT|...] */
 224         unsigned        type;
 225
 226         /* GS parameters. */
 227         unsigned        esgs_itemsize;
 228         unsigned        gs_input_verts_per_prim;
 229         unsigned        gs_output_prim;
 230         unsigned        gs_max_out_vertices;
 231         unsigned        gs_num_invocations;
 232         unsigned        max_gs_stream; /* count - 1 */
 233         unsigned        gsvs_vertex_size;
 234         unsigned        max_gsvs_emit_size;
 235
 236         /* PS parameters. */
 237         unsigned        color_attr_index[2];
 238         unsigned        db_shader_control;
 239         /* Set 0xf or 0x0 (4 bits) per each written output.
 240          * ANDed with spi_shader_col_format.
 241          */
 242         unsigned        colors_written_4bit;
 243
 244         /* masks of "get_unique_index" bits */
 245         uint64_t        outputs_written;
 246         uint32_t        patch_outputs_written;
 247 };
 248
 249 /* Valid shader configurations:
 250  *
 251  * API shaders       VS | TCS | TES | GS |pass| PS
 252  * are compiled as:     |     |     |    |thru|
 253  *                      |     |     |    |    |
 254  * Only VS & PS:     VS | --  | --  | -- | -- | PS
 255  * With GS:          ES | --  | --  | GS | VS | PS
 256  * With Tessel.:     LS | HS  | VS  | -- | -- | PS
 257  * With both:        LS | HS  | ES  | GS | VS | PS
 258  */
 259
 260 /* Common VS bits between the shader key and the prolog key. */
 261 struct si_vs_prolog_bits {
 262         unsigned        instance_divisors[SI_NUM_VERTEX_BUFFERS];
 263 };
 264
 265 /* Common VS bits between the shader key and the epilog key. */
 266 struct si_vs_epilog_bits {
 267         unsigned        export_prim_id:1; /* when PS needs it and GS is disabled */
 268         /* TODO:
 269          * - skip clipdist, culldist (including clipvertex code) exports based
 270          *   on which clip_plane_enable bits are set
 271          * - skip layer, viewport, clipdist, and culldist parameter exports
 272          *   if PS doesn't read them
 273          */
 274 };
 275
 276 /* Common TCS bits between the shader key and the epilog key. */
 277 struct si_tcs_epilog_bits {
 278         unsigned        prim_mode:3;
 279 };
 280
 281 /* Common PS bits between the shader key and the prolog key. */
 282 struct si_ps_prolog_bits {
 283         unsigned        color_two_side:1;
 284         /* TODO: add a flatshade bit that skips interpolation for colors */
 285         unsigned        poly_stipple:1;
 286         unsigned        force_persample_interp:1;
 287         /* TODO:
 288          * - add force_center_interp if MSAA is disabled and centroid or
 289          *   sample are present
 290          * - add force_center_interp_bc_optimize to force center interpolation
 291          *   based on the bc_optimize SGPR bit if MSAA is enabled, centroid is
 292          *   present and sample isn't present.
 293          */
 294 };
 295
 296 /* Common PS bits between the shader key and the epilog key. */
 297 struct si_ps_epilog_bits {
 298         unsigned        spi_shader_col_format;
 299         unsigned        color_is_int8:8;
 300         unsigned        last_cbuf:3;
 301         unsigned        alpha_func:3;
 302         unsigned        alpha_to_one:1;
 303         unsigned        poly_line_smoothing:1;
 304         unsigned        clamp_color:1;
 305 };
 306
 307 union si_shader_part_key {
 308         struct {
 309                 struct si_vs_prolog_bits states;
 310                 unsigned        num_input_sgprs:5;
 311                 unsigned        last_input:4;
 312         } vs_prolog;
 313         struct {
 314                 struct si_vs_epilog_bits states;
 315                 unsigned        prim_id_param_offset:5;
 316         } vs_epilog;
 317         struct {
 318                 struct si_tcs_epilog_bits states;
 319         } tcs_epilog;
 320         struct {
 321                 struct si_ps_prolog_bits states;
 322                 unsigned        num_input_sgprs:5;
 323                 unsigned        num_input_vgprs:5;
 324                 /* Color interpolation and two-side color selection. */
 325                 unsigned        colors_read:8; /* color input components read */
 326                 unsigned        num_interp_inputs:5; /* BCOLOR is at this location */
 327                 unsigned        face_vgpr_index:5;
 328                 char            color_attr_index[2];
 329                 char            color_interp_vgpr_index[2]; /* -1 == constant */
 330         } ps_prolog;
 331         struct {
 332                 struct si_ps_epilog_bits states;
 333                 unsigned        colors_written:8;
 334                 unsigned        writes_z:1;
 335                 unsigned        writes_stencil:1;
 336                 unsigned        writes_samplemask:1;
 337         } ps_epilog;
 338 };
 339
 340 union si_shader_key {
 341         struct {
 342                 struct si_ps_prolog_bits prolog;
 343                 struct si_ps_epilog_bits epilog;
 344         } ps;
 345         struct {
 346                 struct si_vs_prolog_bits prolog;
 347                 struct si_vs_epilog_bits epilog;
 348                 unsigned        as_es:1; /* export shader */
 349                 unsigned        as_ls:1; /* local shader */
 350         } vs;
 351         struct {
 352                 struct si_tcs_epilog_bits epilog;
 353         } tcs; /* tessellation control shader */
 354         struct {
 355                 struct si_vs_epilog_bits epilog; /* same as VS */
 356                 unsigned        as_es:1; /* export shader */
 357         } tes; /* tessellation evaluation shader */
 358 };
 359
 360 struct si_shader_config {
 361         unsigned                        num_sgprs;
 362         unsigned                        num_vgprs;
 363         unsigned                        lds_size;
 364         unsigned                        spi_ps_input_ena;
 365         unsigned                        spi_ps_input_addr;
 366         unsigned                        float_mode;
 367         unsigned                        scratch_bytes_per_wave;
 368         unsigned                        rsrc1;
 369         unsigned                        rsrc2;
 370 };
 371
 372 /* GCN-specific shader info. */
 373 struct si_shader_info {
 374         ubyte                   vs_output_param_offset[SI_MAX_VS_OUTPUTS];
 375         ubyte                   num_input_sgprs;
 376         ubyte                   num_input_vgprs;
 377         char                    face_vgpr_index;
 378         bool                    uses_instanceid;
 379         ubyte                   nr_pos_exports;
 380         ubyte                   nr_param_exports;
 381 };
 382
 383 struct si_shader {
 384         struct si_shader_selector       *selector;
 385         struct si_shader                *next_variant;
 386
 387         struct si_shader_part           *prolog;
 388         struct si_shader_part           *epilog;
 389
 390         struct si_shader                *gs_copy_shader;
 391         struct si_pm4_state             *pm4;
 392         struct r600_resource            *bo;
 393         struct r600_resource            *scratch_bo;
 394         union si_shader_key             key;
 395         bool                            is_binary_shared;
 396         unsigned                        z_order;
 397
 398         /* The following data is all that's needed for binary shaders. */
 399         struct radeon_shader_binary     binary;
 400         struct si_shader_config         config;
 401         struct si_shader_info           info;
 402 };
 403
 404 struct si_shader_part {
 405         struct si_shader_part *next;
 406         union si_shader_part_key key;
 407         struct radeon_shader_binary binary;
 408         struct si_shader_config config;
 409 };
 410
 411 static inline struct tgsi_shader_info *si_get_vs_info(struct si_context *sctx)
 412 {
 413         if (sctx->gs_shader.cso)
 414                 return &sctx->gs_shader.cso->info;
 415         else if (sctx->tes_shader.cso)
 416                 return &sctx->tes_shader.cso->info;
 417         else if (sctx->vs_shader.cso)
 418                 return &sctx->vs_shader.cso->info;
 419         else
 420                 return NULL;
 421 }
 422
 423 static inline struct si_shader* si_get_vs_state(struct si_context *sctx)
 424 {
 425         if (sctx->gs_shader.current)
 426                 return sctx->gs_shader.current->gs_copy_shader;
 427         else if (sctx->tes_shader.current)
 428                 return sctx->tes_shader.current;
 429         else
 430                 return sctx->vs_shader.current;
 431 }
 432
 433 static inline bool si_vs_exports_prim_id(struct si_shader *shader)
 434 {
 435         if (shader->selector->type == PIPE_SHADER_VERTEX)
 436                 return shader->key.vs.epilog.export_prim_id;
 437         else if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
 438                 return shader->key.tes.epilog.export_prim_id;
 439         else
 440                 return false;
 441 }
 442
 443 /* si_shader.c */
 444 int si_compile_tgsi_shader(struct si_screen *sscreen,
 445                            LLVMTargetMachineRef tm,
 446                            struct si_shader *shader,
 447                            bool is_monolithic,
 448                            struct pipe_debug_callback *debug);
 449 int si_shader_create(struct si_screen *sscreen, LLVMTargetMachineRef tm,
 450                      struct si_shader *shader,
 451                      struct pipe_debug_callback *debug);
 452 void si_dump_shader_key(unsigned shader, union si_shader_key *key, FILE *f);
 453 int si_compile_llvm(struct si_screen *sscreen,
 454                     struct radeon_shader_binary *binary,
 455                     struct si_shader_config *conf,
 456                     LLVMTargetMachineRef tm,
 457                     LLVMModuleRef mod,
 458                     struct pipe_debug_callback *debug,
 459                     unsigned processor,
 460                     const char *name);
 461 void si_shader_destroy(struct si_shader *shader);
 462 unsigned si_shader_io_get_unique_index(unsigned semantic_name, unsigned index);
 463 int si_shader_binary_upload(struct si_screen *sscreen, struct si_shader *shader);
 464 void si_shader_dump(struct si_screen *sscreen, struct si_shader *shader,
 465                     struct pipe_debug_callback *debug, unsigned processor,
 466                     FILE *f);
 467 void si_shader_apply_scratch_relocs(struct si_context *sctx,
 468                         struct si_shader *shader,
 469                         uint64_t scratch_va);
 470 void si_shader_binary_read_config(struct radeon_shader_binary *binary,
 471                                   struct si_shader_config *conf,
 472                                   unsigned symbol_offset);
 473
 474 #endif