src/gallium/drivers/radeonsi/si_shader_internal.h

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 #ifndef SI_SHADER_PRIVATE_H
  25 #define SI_SHADER_PRIVATE_H
  26
  27 #include "si_shader.h"
  28 #include "gallivm/lp_bld_init.h"
  29 #include "gallivm/lp_bld_tgsi.h"
  30 #include "tgsi/tgsi_parse.h"
  31
  32 #include <llvm-c/Core.h>
  33 #include <llvm-c/TargetMachine.h>
  34
  35 struct pipe_debug_callback;
  36 struct radeon_shader_binary;
  37
  38 #define RADEON_LLVM_MAX_INPUT_SLOTS 32
  39 #define RADEON_LLVM_MAX_INPUTS 32 * 4
  40 #define RADEON_LLVM_MAX_OUTPUTS 32 * 4
  41
  42 #define RADEON_LLVM_INITIAL_CF_DEPTH 4
  43
  44 #define RADEON_LLVM_MAX_SYSTEM_VALUES 4
  45
  46 struct radeon_llvm_flow;
  47
  48 struct radeon_llvm_context {
  49         struct lp_build_tgsi_soa_context soa;
  50
  51         /*=== Front end configuration ===*/
  52
  53         /* Instructions that are not described by any of the TGSI opcodes. */
  54
  55         /** This function is responsible for initilizing the inputs array and will be
  56           * called once for each input declared in the TGSI shader.
  57           */
  58         void (*load_input)(struct radeon_llvm_context *,
  59                            unsigned input_index,
  60                            const struct tgsi_full_declaration *decl,
  61                            LLVMValueRef out[4]);
  62
  63         void (*load_system_value)(struct radeon_llvm_context *,
  64                                   unsigned index,
  65                                   const struct tgsi_full_declaration *decl);
  66
  67         void (*declare_memory_region)(struct radeon_llvm_context *,
  68                                       const struct tgsi_full_declaration *decl);
  69
  70         /** This array contains the input values for the shader.  Typically these
  71           * values will be in the form of a target intrinsic that will inform the
  72           * backend how to load the actual inputs to the shader.
  73           */
  74         struct tgsi_full_declaration input_decls[RADEON_LLVM_MAX_INPUT_SLOTS];
  75         LLVMValueRef inputs[RADEON_LLVM_MAX_INPUTS];
  76         LLVMValueRef outputs[RADEON_LLVM_MAX_OUTPUTS][TGSI_NUM_CHANNELS];
  77
  78         /** This pointer is used to contain the temporary values.
  79           * The amount of temporary used in tgsi can't be bound to a max value and
  80           * thus we must allocate this array at runtime.
  81           */
  82         LLVMValueRef *temps;
  83         unsigned temps_count;
  84         LLVMValueRef system_values[RADEON_LLVM_MAX_SYSTEM_VALUES];
  85
  86         /*=== Private Members ===*/
  87
  88         struct radeon_llvm_flow *flow;
  89         unsigned flow_depth;
  90         unsigned flow_depth_max;
  91
  92         struct tgsi_array_info *temp_arrays;
  93         LLVMValueRef *temp_array_allocas;
  94
  95         LLVMValueRef undef_alloca;
  96
  97         LLVMValueRef main_fn;
  98         LLVMTypeRef return_type;
  99
 100         unsigned fpmath_md_kind;
 101         LLVMValueRef fpmath_md_2p5_ulp;
 102
 103         struct gallivm_state gallivm;
 104 };
 105
 106 static inline struct radeon_llvm_context *
 107 radeon_llvm_context(struct lp_build_tgsi_context *bld_base)
 108 {
 109         return (struct radeon_llvm_context*)bld_base;
 110 }
 111
 112 void radeon_llvm_add_attribute(LLVMValueRef F, const char *name, int value);
 113 void radeon_llvm_shader_type(LLVMValueRef F, unsigned type);
 114
 115 LLVMTargetRef radeon_llvm_get_r600_target(const char *triple);
 116
 117 unsigned radeon_llvm_compile(LLVMModuleRef M, struct radeon_shader_binary *binary,
 118                              LLVMTargetMachineRef tm,
 119                              struct pipe_debug_callback *debug);
 120
 121 LLVMTypeRef tgsi2llvmtype(struct lp_build_tgsi_context *bld_base,
 122                           enum tgsi_opcode_type type);
 123
 124 LLVMValueRef bitcast(struct lp_build_tgsi_context *bld_base,
 125                      enum tgsi_opcode_type type, LLVMValueRef value);
 126
 127 LLVMValueRef radeon_llvm_bound_index(struct radeon_llvm_context *ctx,
 128                                      LLVMValueRef index,
 129                                      unsigned num);
 130
 131 void radeon_llvm_context_init(struct radeon_llvm_context *ctx,
 132                               const char *triple,
 133                               const struct tgsi_shader_info *info,
 134                               const struct tgsi_token *tokens);
 135
 136 void radeon_llvm_create_func(struct radeon_llvm_context *ctx,
 137                              LLVMTypeRef *return_types, unsigned num_return_elems,
 138                              LLVMTypeRef *ParamTypes, unsigned ParamCount);
 139
 140 void radeon_llvm_dispose(struct radeon_llvm_context *ctx);
 141
 142 void radeon_llvm_finalize_module(struct radeon_llvm_context *ctx,
 143                                  bool run_verifier);
 144
 145 LLVMValueRef radeon_llvm_emit_fetch_64bit(struct lp_build_tgsi_context *bld_base,
 146                                           enum tgsi_opcode_type type,
 147                                           LLVMValueRef ptr,
 148                                           LLVMValueRef ptr2);
 149
 150 LLVMValueRef radeon_llvm_saturate(struct lp_build_tgsi_context *bld_base,
 151                                   LLVMValueRef value);
 152
 153 LLVMValueRef radeon_llvm_emit_fetch(struct lp_build_tgsi_context *bld_base,
 154                                     const struct tgsi_full_src_register *reg,
 155                                     enum tgsi_opcode_type type,
 156                                     unsigned swizzle);
 157
 158 void radeon_llvm_emit_store(struct lp_build_tgsi_context *bld_base,
 159                             const struct tgsi_full_instruction *inst,
 160                             const struct tgsi_opcode_info *info,
 161                             LLVMValueRef dst[4]);
 162
 163 void si_shader_context_init_alu(struct lp_build_tgsi_context *bld_base);
 164 void si_prepare_cube_coords(struct lp_build_tgsi_context *bld_base,
 165                             struct lp_build_emit_data *emit_data,
 166                             LLVMValueRef *coords_arg,
 167                             LLVMValueRef *derivs_arg);
 168
 169 #endif