src/gallium/drivers/radeonsi/si_shader_nir.c

   1 /*
   2  * Copyright 2017 Advanced Micro Devices, Inc.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * on the rights to use, copy, modify, merge, publish, distribute, sub
   9  * license, and/or sell copies of the Software, and to permit persons to whom
  10  * the Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  20  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  21  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  22  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  23  */
  24
  25 #include "ac_nir_to_llvm.h"
  26 #include "compiler/nir/nir.h"
  27 #include "compiler/nir/nir_builder.h"
  28 #include "compiler/nir/nir_deref.h"
  29 #include "compiler/nir_types.h"
  30 #include "si_pipe.h"
  31 #include "si_shader_internal.h"
  32 #include "tgsi/tgsi_from_mesa.h"
  33
  34 static const nir_deref_instr *tex_get_texture_deref(nir_tex_instr *instr)
  35 {
  36    for (unsigned i = 0; i < instr->num_srcs; i++) {
  37       switch (instr->src[i].src_type) {
  38       case nir_tex_src_texture_deref:
  39          return nir_src_as_deref(instr->src[i].src);
  40       default:
  41          break;
  42       }
  43    }
  44
  45    return NULL;
  46 }
  47
  48 static void scan_io_usage(struct si_shader_info *info, nir_intrinsic_instr *intr,
  49                           bool is_input)
  50 {
  51    unsigned interp = INTERP_MODE_FLAT; /* load_input uses flat shading */
  52
  53    if (intr->intrinsic == nir_intrinsic_load_interpolated_input) {
  54       nir_intrinsic_instr *baryc = nir_instr_as_intrinsic(intr->src[0].ssa->parent_instr);
  55
  56       if (baryc) {
  57          if (nir_intrinsic_infos[baryc->intrinsic].index_map[NIR_INTRINSIC_INTERP_MODE] > 0)
  58             interp = nir_intrinsic_interp_mode(baryc);
  59          else
  60             unreachable("unknown barycentric intrinsic");
  61       } else {
  62          unreachable("unknown barycentric expression");
  63       }
  64    }
  65
  66    unsigned mask, bit_size;
  67    bool dual_slot, is_output_load;
  68
  69    if (nir_intrinsic_infos[intr->intrinsic].index_map[NIR_INTRINSIC_WRMASK] > 0) {
  70       mask = nir_intrinsic_write_mask(intr); /* store */
  71       bit_size = nir_src_bit_size(intr->src[0]);
  72       dual_slot = bit_size == 64 && nir_src_num_components(intr->src[0]) >= 3;
  73       is_output_load = false;
  74    } else {
  75       mask = nir_ssa_def_components_read(&intr->dest.ssa); /* load */
  76       bit_size = intr->dest.ssa.bit_size;
  77       dual_slot = bit_size == 64 && intr->dest.ssa.num_components >= 3;
  78       is_output_load = !is_input;
  79    }
  80
  81    /* Convert the 64-bit component mask to a 32-bit component mask. */
  82    if (bit_size == 64) {
  83       unsigned new_mask = 0;
  84       for (unsigned i = 0; i < 4; i++) {
  85          if (mask & (1 << i))
  86             new_mask |= 0x3 << (2 * i);
  87       }
  88       mask = new_mask;
  89    }
  90
  91    /* Convert the 16-bit component mask to a 32-bit component mask. */
  92    if (bit_size == 16) {
  93       unsigned new_mask = 0;
  94       for (unsigned i = 0; i < 4; i++) {
  95          if (mask & (1 << i))
  96             new_mask |= 0x1 << (i / 2);
  97       }
  98       mask = new_mask;
  99    }
 100
 101    mask <<= nir_intrinsic_component(intr);
 102
 103    nir_src offset = *nir_get_io_offset_src(intr);
 104    bool indirect = !nir_src_is_const(offset);
 105    if (!indirect)
 106       assert(nir_src_as_uint(offset) == 0);
 107
 108    unsigned semantic = 0;
 109    /* VS doesn't have semantics. */
 110    if (info->stage != MESA_SHADER_VERTEX || !is_input)
 111       semantic = nir_intrinsic_io_semantics(intr).location;
 112
 113    if (info->stage == MESA_SHADER_FRAGMENT && !is_input) {
 114       /* Never use FRAG_RESULT_COLOR directly. */
 115       if (semantic == FRAG_RESULT_COLOR) {
 116          semantic = FRAG_RESULT_DATA0;
 117          info->properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS] = true;
 118       }
 119       semantic += nir_intrinsic_io_semantics(intr).dual_source_blend_index;
 120    }
 121
 122    unsigned driver_location = nir_intrinsic_base(intr);
 123    unsigned num_slots = indirect ? nir_intrinsic_io_semantics(intr).num_slots : (1 + dual_slot);
 124
 125    if (is_input) {
 126       assert(driver_location + num_slots <= ARRAY_SIZE(info->input_usage_mask));
 127
 128       for (unsigned i = 0; i < num_slots; i++) {
 129          unsigned loc = driver_location + i;
 130          unsigned slot_mask = (dual_slot && i % 2 ? mask >> 4 : mask) & 0xf;
 131
 132          info->input_semantic[loc] = semantic + i;
 133          info->input_interpolate[loc] = interp;
 134
 135          if (slot_mask) {
 136             info->input_usage_mask[loc] |= slot_mask;
 137             info->num_inputs = MAX2(info->num_inputs, loc + 1);
 138
 139             if (semantic == VARYING_SLOT_PRIMITIVE_ID)
 140                info->uses_primid = true;
 141          }
 142       }
 143    } else {
 144       /* Outputs. */
 145       assert(driver_location + num_slots <= ARRAY_SIZE(info->output_usagemask));
 146
 147       for (unsigned i = 0; i < num_slots; i++) {
 148          unsigned loc = driver_location + i;
 149          unsigned slot_mask = (dual_slot && i % 2 ? mask >> 4 : mask) & 0xf;
 150
 151          info->output_semantic[loc] = semantic + i;
 152
 153          if (is_output_load) {
 154             /* Output loads have only a few things that we need to track. */
 155             info->output_readmask[loc] |= slot_mask;
 156
 157             if (info->stage == MESA_SHADER_FRAGMENT &&
 158                 nir_intrinsic_io_semantics(intr).fb_fetch_output)
 159                info->uses_fbfetch = true;
 160          } else if (slot_mask) {
 161             /* Output stores. */
 162             if (info->stage == MESA_SHADER_GEOMETRY) {
 163                unsigned gs_streams = (uint32_t)nir_intrinsic_io_semantics(intr).gs_streams <<
 164                                      (nir_intrinsic_component(intr) * 2);
 165                unsigned new_mask = slot_mask & ~info->output_usagemask[loc];
 166
 167                for (unsigned i = 0; i < 4; i++) {
 168                   unsigned stream = (gs_streams >> (i * 2)) & 0x3;
 169
 170                   if (new_mask & (1 << i)) {
 171                      info->output_streams[loc] |= stream << (i * 2);
 172                      info->num_stream_output_components[stream]++;
 173                   }
 174                }
 175             }
 176
 177             info->output_usagemask[loc] |= slot_mask;
 178             info->num_outputs = MAX2(info->num_outputs, loc + 1);
 179
 180             if (info->stage == MESA_SHADER_FRAGMENT) {
 181                switch (semantic) {
 182                case FRAG_RESULT_DEPTH:
 183                   info->writes_z = true;
 184                   break;
 185                case FRAG_RESULT_STENCIL:
 186                   info->writes_stencil = true;
 187                   break;
 188                case FRAG_RESULT_SAMPLE_MASK:
 189                   info->writes_samplemask = true;
 190                   break;
 191                default:
 192                   if (semantic >= FRAG_RESULT_DATA0 && semantic <= FRAG_RESULT_DATA7) {
 193                      unsigned index = semantic - FRAG_RESULT_DATA0;
 194                      info->colors_written |= 1 << (index + i);
 195                   }
 196                   break;
 197                }
 198             } else {
 199                switch (semantic) {
 200                case VARYING_SLOT_PRIMITIVE_ID:
 201                   info->writes_primid = true;
 202                   break;
 203                case VARYING_SLOT_VIEWPORT:
 204                   info->writes_viewport_index = true;
 205                   break;
 206                case VARYING_SLOT_LAYER:
 207                   info->writes_layer = true;
 208                   break;
 209                case VARYING_SLOT_PSIZ:
 210                   info->writes_psize = true;
 211                   break;
 212                case VARYING_SLOT_CLIP_VERTEX:
 213                   info->writes_clipvertex = true;
 214                   break;
 215                case VARYING_SLOT_EDGE:
 216                   info->writes_edgeflag = true;
 217                   break;
 218                case VARYING_SLOT_POS:
 219                   info->writes_position = true;
 220                   break;
 221                }
 222             }
 223          }
 224       }
 225    }
 226 }
 227
 228 static void scan_instruction(const struct nir_shader *nir, struct si_shader_info *info,
 229                              nir_instr *instr)
 230 {
 231    if (instr->type == nir_instr_type_alu) {
 232       nir_alu_instr *alu = nir_instr_as_alu(instr);
 233
 234       switch (alu->op) {
 235       case nir_op_fddx:
 236       case nir_op_fddy:
 237       case nir_op_fddx_fine:
 238       case nir_op_fddy_fine:
 239       case nir_op_fddx_coarse:
 240       case nir_op_fddy_coarse:
 241          info->uses_derivatives = true;
 242          break;
 243       default:
 244          break;
 245       }
 246    } else if (instr->type == nir_instr_type_tex) {
 247       nir_tex_instr *tex = nir_instr_as_tex(instr);
 248       const nir_deref_instr *deref = tex_get_texture_deref(tex);
 249       nir_variable *var = deref ? nir_deref_instr_get_variable(deref) : NULL;
 250
 251       if (!var) {
 252          info->samplers_declared |= u_bit_consecutive(tex->sampler_index, 1);
 253       } else {
 254          if (deref->mode != nir_var_uniform || var->data.bindless)
 255             info->uses_bindless_samplers = true;
 256       }
 257
 258       switch (tex->op) {
 259       case nir_texop_tex:
 260       case nir_texop_txb:
 261       case nir_texop_lod:
 262          info->uses_derivatives = true;
 263          break;
 264       default:
 265          break;
 266       }
 267    } else if (instr->type == nir_instr_type_intrinsic) {
 268       nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);
 269
 270       switch (intr->intrinsic) {
 271       case nir_intrinsic_load_front_face:
 272          info->uses_frontface = 1;
 273          break;
 274       case nir_intrinsic_load_instance_id:
 275          info->uses_instanceid = 1;
 276          break;
 277       case nir_intrinsic_load_invocation_id:
 278          info->uses_invocationid = true;
 279          break;
 280       case nir_intrinsic_load_num_work_groups:
 281          info->uses_grid_size = true;
 282          break;
 283       case nir_intrinsic_load_local_invocation_index:
 284       case nir_intrinsic_load_subgroup_id:
 285       case nir_intrinsic_load_num_subgroups:
 286          info->uses_subgroup_info = true;
 287          break;
 288       case nir_intrinsic_load_local_group_size:
 289          /* The block size is translated to IMM with a fixed block size. */
 290          if (info->properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] == 0)
 291             info->uses_block_size = true;
 292          break;
 293       case nir_intrinsic_load_local_invocation_id:
 294       case nir_intrinsic_load_work_group_id: {
 295          unsigned mask = nir_ssa_def_components_read(&intr->dest.ssa);
 296          while (mask) {
 297             unsigned i = u_bit_scan(&mask);
 298
 299             if (intr->intrinsic == nir_intrinsic_load_work_group_id)
 300                info->uses_block_id[i] = true;
 301             else
 302                info->uses_thread_id[i] = true;
 303          }
 304          break;
 305       }
 306       case nir_intrinsic_load_vertex_id:
 307          info->uses_vertexid = 1;
 308          break;
 309       case nir_intrinsic_load_vertex_id_zero_base:
 310          info->uses_vertexid_nobase = 1;
 311          break;
 312       case nir_intrinsic_load_base_vertex:
 313          info->uses_basevertex = 1;
 314          break;
 315       case nir_intrinsic_load_draw_id:
 316          info->uses_drawid = 1;
 317          break;
 318       case nir_intrinsic_load_primitive_id:
 319          info->uses_primid = 1;
 320          break;
 321       case nir_intrinsic_load_sample_mask_in:
 322          info->reads_samplemask = true;
 323          break;
 324       case nir_intrinsic_load_tess_level_inner:
 325       case nir_intrinsic_load_tess_level_outer:
 326          info->reads_tess_factors = true;
 327          break;
 328       case nir_intrinsic_bindless_image_load:
 329       case nir_intrinsic_bindless_image_size:
 330       case nir_intrinsic_bindless_image_samples:
 331          info->uses_bindless_images = true;
 332          break;
 333       case nir_intrinsic_bindless_image_store:
 334          info->uses_bindless_images = true;
 335          info->writes_memory = true;
 336          info->num_memory_instructions++; /* we only care about stores */
 337          break;
 338       case nir_intrinsic_image_deref_store:
 339          info->writes_memory = true;
 340          info->num_memory_instructions++; /* we only care about stores */
 341          break;
 342       case nir_intrinsic_bindless_image_atomic_add:
 343       case nir_intrinsic_bindless_image_atomic_imin:
 344       case nir_intrinsic_bindless_image_atomic_umin:
 345       case nir_intrinsic_bindless_image_atomic_imax:
 346       case nir_intrinsic_bindless_image_atomic_umax:
 347       case nir_intrinsic_bindless_image_atomic_and:
 348       case nir_intrinsic_bindless_image_atomic_or:
 349       case nir_intrinsic_bindless_image_atomic_xor:
 350       case nir_intrinsic_bindless_image_atomic_exchange:
 351       case nir_intrinsic_bindless_image_atomic_comp_swap:
 352          info->uses_bindless_images = true;
 353          info->writes_memory = true;
 354          info->num_memory_instructions++; /* we only care about stores */
 355          break;
 356       case nir_intrinsic_image_deref_atomic_add:
 357       case nir_intrinsic_image_deref_atomic_imin:
 358       case nir_intrinsic_image_deref_atomic_umin:
 359       case nir_intrinsic_image_deref_atomic_imax:
 360       case nir_intrinsic_image_deref_atomic_umax:
 361       case nir_intrinsic_image_deref_atomic_and:
 362       case nir_intrinsic_image_deref_atomic_or:
 363       case nir_intrinsic_image_deref_atomic_xor:
 364       case nir_intrinsic_image_deref_atomic_exchange:
 365       case nir_intrinsic_image_deref_atomic_comp_swap:
 366       case nir_intrinsic_image_deref_atomic_inc_wrap:
 367       case nir_intrinsic_image_deref_atomic_dec_wrap:
 368          info->writes_memory = true;
 369          info->num_memory_instructions++; /* we only care about stores */
 370          break;
 371       case nir_intrinsic_store_ssbo:
 372       case nir_intrinsic_ssbo_atomic_add:
 373       case nir_intrinsic_ssbo_atomic_imin:
 374       case nir_intrinsic_ssbo_atomic_umin:
 375       case nir_intrinsic_ssbo_atomic_imax:
 376       case nir_intrinsic_ssbo_atomic_umax:
 377       case nir_intrinsic_ssbo_atomic_and:
 378       case nir_intrinsic_ssbo_atomic_or:
 379       case nir_intrinsic_ssbo_atomic_xor:
 380       case nir_intrinsic_ssbo_atomic_exchange:
 381       case nir_intrinsic_ssbo_atomic_comp_swap:
 382          info->writes_memory = true;
 383          info->num_memory_instructions++; /* we only care about stores */
 384          break;
 385       case nir_intrinsic_load_color0:
 386       case nir_intrinsic_load_color1: {
 387          unsigned index = intr->intrinsic == nir_intrinsic_load_color1;
 388          uint8_t mask = nir_ssa_def_components_read(&intr->dest.ssa);
 389          info->colors_read |= mask << (index * 4);
 390          break;
 391       }
 392       case nir_intrinsic_load_barycentric_pixel:
 393       case nir_intrinsic_load_barycentric_centroid:
 394       case nir_intrinsic_load_barycentric_sample:
 395       case nir_intrinsic_load_barycentric_at_offset:   /* uses center */
 396       case nir_intrinsic_load_barycentric_at_sample: { /* uses center */
 397          unsigned mode = nir_intrinsic_interp_mode(intr);
 398
 399          if (mode == INTERP_MODE_FLAT)
 400             break;
 401
 402          if (mode == INTERP_MODE_NOPERSPECTIVE) {
 403             if (intr->intrinsic == nir_intrinsic_load_barycentric_sample)
 404                info->uses_linear_sample = true;
 405             else if (intr->intrinsic == nir_intrinsic_load_barycentric_centroid)
 406                info->uses_linear_centroid = true;
 407             else
 408                info->uses_linear_center = true;
 409
 410             if (intr->intrinsic == nir_intrinsic_load_barycentric_at_sample)
 411                info->uses_linear_opcode_interp_sample = true;
 412          } else {
 413             if (intr->intrinsic == nir_intrinsic_load_barycentric_sample)
 414                info->uses_persp_sample = true;
 415             else if (intr->intrinsic == nir_intrinsic_load_barycentric_centroid)
 416                info->uses_persp_centroid = true;
 417             else
 418                info->uses_persp_center = true;
 419
 420             if (intr->intrinsic == nir_intrinsic_load_barycentric_at_sample)
 421                info->uses_persp_opcode_interp_sample = true;
 422          }
 423          break;
 424       }
 425       case nir_intrinsic_load_input:
 426       case nir_intrinsic_load_per_vertex_input:
 427       case nir_intrinsic_load_input_vertex:
 428       case nir_intrinsic_load_interpolated_input:
 429          scan_io_usage(info, intr, true);
 430          break;
 431       case nir_intrinsic_load_output:
 432       case nir_intrinsic_load_per_vertex_output:
 433       case nir_intrinsic_store_output:
 434       case nir_intrinsic_store_per_vertex_output:
 435          scan_io_usage(info, intr, false);
 436          break;
 437       case nir_intrinsic_load_deref:
 438       case nir_intrinsic_store_deref:
 439       case nir_intrinsic_interp_deref_at_centroid:
 440       case nir_intrinsic_interp_deref_at_sample:
 441       case nir_intrinsic_interp_deref_at_offset:
 442          unreachable("these opcodes should have been lowered");
 443          break;
 444       default:
 445          break;
 446       }
 447    }
 448 }
 449
 450 void si_nir_scan_shader(const struct nir_shader *nir, struct si_shader_info *info)
 451 {
 452    nir_function *func;
 453
 454    info->stage = nir->info.stage;
 455    info->properties[TGSI_PROPERTY_NEXT_SHADER] = pipe_shader_type_from_mesa(nir->info.next_stage);
 456
 457    if (nir->info.stage == MESA_SHADER_VERTEX) {
 458       info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION] = nir->info.vs.window_space_position;
 459       info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD] = nir->info.vs.blit_sgprs_amd;
 460    }
 461
 462    if (nir->info.stage == MESA_SHADER_TESS_CTRL) {
 463       info->properties[TGSI_PROPERTY_TCS_VERTICES_OUT] = nir->info.tess.tcs_vertices_out;
 464    }
 465
 466    if (nir->info.stage == MESA_SHADER_TESS_EVAL) {
 467       if (nir->info.tess.primitive_mode == GL_ISOLINES)
 468          info->properties[TGSI_PROPERTY_TES_PRIM_MODE] = PIPE_PRIM_LINES;
 469       else
 470          info->properties[TGSI_PROPERTY_TES_PRIM_MODE] = nir->info.tess.primitive_mode;
 471
 472       STATIC_ASSERT((TESS_SPACING_EQUAL + 1) % 3 == PIPE_TESS_SPACING_EQUAL);
 473       STATIC_ASSERT((TESS_SPACING_FRACTIONAL_ODD + 1) % 3 == PIPE_TESS_SPACING_FRACTIONAL_ODD);
 474       STATIC_ASSERT((TESS_SPACING_FRACTIONAL_EVEN + 1) % 3 == PIPE_TESS_SPACING_FRACTIONAL_EVEN);
 475
 476       info->properties[TGSI_PROPERTY_TES_SPACING] = (nir->info.tess.spacing + 1) % 3;
 477       info->properties[TGSI_PROPERTY_TES_VERTEX_ORDER_CW] = !nir->info.tess.ccw;
 478       info->properties[TGSI_PROPERTY_TES_POINT_MODE] = nir->info.tess.point_mode;
 479    }
 480
 481    if (nir->info.stage == MESA_SHADER_GEOMETRY) {
 482       info->properties[TGSI_PROPERTY_GS_INPUT_PRIM] = nir->info.gs.input_primitive;
 483       info->properties[TGSI_PROPERTY_GS_OUTPUT_PRIM] = nir->info.gs.output_primitive;
 484       info->properties[TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES] = nir->info.gs.vertices_out;
 485       info->properties[TGSI_PROPERTY_GS_INVOCATIONS] = nir->info.gs.invocations;
 486    }
 487
 488    if (nir->info.stage == MESA_SHADER_FRAGMENT) {
 489       info->properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL] =
 490          nir->info.fs.early_fragment_tests | nir->info.fs.post_depth_coverage;
 491       info->properties[TGSI_PROPERTY_FS_POST_DEPTH_COVERAGE] = nir->info.fs.post_depth_coverage;
 492
 493       if (nir->info.fs.pixel_center_integer) {
 494          info->properties[TGSI_PROPERTY_FS_COORD_PIXEL_CENTER] = TGSI_FS_COORD_PIXEL_CENTER_INTEGER;
 495       }
 496
 497       if (nir->info.fs.depth_layout != FRAG_DEPTH_LAYOUT_NONE) {
 498          switch (nir->info.fs.depth_layout) {
 499          case FRAG_DEPTH_LAYOUT_ANY:
 500             info->properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT] = TGSI_FS_DEPTH_LAYOUT_ANY;
 501             break;
 502          case FRAG_DEPTH_LAYOUT_GREATER:
 503             info->properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT] = TGSI_FS_DEPTH_LAYOUT_GREATER;
 504             break;
 505          case FRAG_DEPTH_LAYOUT_LESS:
 506             info->properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT] = TGSI_FS_DEPTH_LAYOUT_LESS;
 507             break;
 508          case FRAG_DEPTH_LAYOUT_UNCHANGED:
 509             info->properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT] = TGSI_FS_DEPTH_LAYOUT_UNCHANGED;
 510             break;
 511          default:
 512             unreachable("Unknow depth layout");
 513          }
 514       }
 515
 516       info->color_interpolate[0] = nir->info.fs.color0_interp;
 517       info->color_interpolate[1] = nir->info.fs.color1_interp;
 518       for (unsigned i = 0; i < 2; i++) {
 519          if (info->color_interpolate[i] == INTERP_MODE_NONE)
 520             info->color_interpolate[i] = INTERP_MODE_COLOR;
 521       }
 522
 523       info->color_interpolate_loc[0] = nir->info.fs.color0_sample ? TGSI_INTERPOLATE_LOC_SAMPLE :
 524                                        nir->info.fs.color0_centroid ? TGSI_INTERPOLATE_LOC_CENTROID :
 525                                                                       TGSI_INTERPOLATE_LOC_CENTER;
 526       info->color_interpolate_loc[1] = nir->info.fs.color1_sample ? TGSI_INTERPOLATE_LOC_SAMPLE :
 527                                        nir->info.fs.color1_centroid ? TGSI_INTERPOLATE_LOC_CENTROID :
 528                                                                       TGSI_INTERPOLATE_LOC_CENTER;
 529    }
 530
 531    if (gl_shader_stage_is_compute(nir->info.stage)) {
 532       info->properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] = nir->info.cs.local_size[0];
 533       info->properties[TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT] = nir->info.cs.local_size[1];
 534       info->properties[TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH] = nir->info.cs.local_size[2];
 535       info->properties[TGSI_PROPERTY_CS_USER_DATA_COMPONENTS_AMD] =
 536          nir->info.cs.user_data_components_amd;
 537    }
 538
 539    info->constbuf0_num_slots = nir->num_uniforms;
 540    info->shader_buffers_declared = u_bit_consecutive(0, nir->info.num_ssbos);
 541    info->const_buffers_declared = u_bit_consecutive(0, nir->info.num_ubos);
 542    info->images_declared = u_bit_consecutive(0, nir->info.num_images);
 543    info->msaa_images_declared = nir->info.msaa_images;
 544    info->image_buffers = nir->info.image_buffers;
 545    info->samplers_declared = nir->info.textures_used;
 546
 547    info->num_written_clipdistance = nir->info.clip_distance_array_size;
 548    info->num_written_culldistance = nir->info.cull_distance_array_size;
 549    info->clipdist_writemask = u_bit_consecutive(0, info->num_written_clipdistance);
 550    info->culldist_writemask = u_bit_consecutive(0, info->num_written_culldistance);
 551
 552    if (info->stage == MESA_SHADER_FRAGMENT)
 553       info->uses_kill = nir->info.fs.uses_discard;
 554
 555    if (nir->info.stage == MESA_SHADER_TESS_CTRL) {
 556       info->tessfactors_are_def_in_all_invocs = ac_are_tessfactors_def_in_all_invocs(nir);
 557    }
 558
 559    func = (struct nir_function *)exec_list_get_head_const(&nir->functions);
 560    nir_foreach_block (block, func->impl) {
 561       nir_foreach_instr (instr, block)
 562          scan_instruction(nir, info, instr);
 563    }
 564
 565    /* Add color inputs to the list of inputs. */
 566    if (nir->info.stage == MESA_SHADER_FRAGMENT) {
 567       for (unsigned i = 0; i < 2; i++) {
 568          if ((info->colors_read >> (i * 4)) & 0xf) {
 569             info->input_semantic[info->num_inputs] = VARYING_SLOT_COL0 + i;
 570             info->input_interpolate[info->num_inputs] = info->color_interpolate[i];
 571             info->input_usage_mask[info->num_inputs] = info->colors_read >> (i * 4);
 572             info->num_inputs++;
 573          }
 574       }
 575    }
 576
 577    /* Trim output read masks based on write masks. */
 578    for (unsigned i = 0; i < info->num_outputs; i++)
 579       info->output_readmask[i] &= info->output_usagemask[i];
 580 }
 581
 582 static void si_nir_opts(struct nir_shader *nir, bool first)
 583 {
 584    bool progress;
 585
 586    NIR_PASS_V(nir, nir_lower_vars_to_ssa);
 587    NIR_PASS_V(nir, nir_lower_alu_to_scalar, NULL, NULL);
 588    NIR_PASS_V(nir, nir_lower_phis_to_scalar);
 589
 590    do {
 591       progress = false;
 592       bool lower_alu_to_scalar = false;
 593       bool lower_phis_to_scalar = false;
 594
 595       if (first) {
 596          bool opt_find_array_copies = false;
 597
 598          NIR_PASS(progress, nir, nir_split_array_vars, nir_var_function_temp);
 599          NIR_PASS(lower_alu_to_scalar, nir, nir_shrink_vec_array_vars, nir_var_function_temp);
 600          NIR_PASS(opt_find_array_copies, nir, nir_opt_find_array_copies);
 601          NIR_PASS(progress, nir, nir_opt_copy_prop_vars);
 602
 603          /* Call nir_lower_var_copies() to remove any copies introduced
 604           * by nir_opt_find_array_copies().
 605           */
 606          if (opt_find_array_copies)
 607             NIR_PASS(progress, nir, nir_lower_var_copies);
 608          progress |= opt_find_array_copies;
 609       } else {
 610          NIR_PASS(progress, nir, nir_opt_copy_prop_vars);
 611       }
 612
 613       NIR_PASS(progress, nir, nir_opt_dead_write_vars);
 614
 615       NIR_PASS(lower_alu_to_scalar, nir, nir_opt_trivial_continues);
 616       /* (Constant) copy propagation is needed for txf with offsets. */
 617       NIR_PASS(progress, nir, nir_copy_prop);
 618       NIR_PASS(progress, nir, nir_opt_remove_phis);
 619       NIR_PASS(progress, nir, nir_opt_dce);
 620       NIR_PASS(lower_phis_to_scalar, nir, nir_opt_if, true);
 621       NIR_PASS(progress, nir, nir_opt_dead_cf);
 622
 623       if (lower_alu_to_scalar)
 624          NIR_PASS_V(nir, nir_lower_alu_to_scalar, NULL, NULL);
 625       if (lower_phis_to_scalar)
 626          NIR_PASS_V(nir, nir_lower_phis_to_scalar);
 627       progress |= lower_alu_to_scalar | lower_phis_to_scalar;
 628
 629       NIR_PASS(progress, nir, nir_opt_cse);
 630       NIR_PASS(progress, nir, nir_opt_peephole_select, 8, true, true);
 631
 632       /* Needed for algebraic lowering */
 633       NIR_PASS(progress, nir, nir_opt_algebraic);
 634       NIR_PASS(progress, nir, nir_opt_constant_folding);
 635
 636       if (!nir->info.flrp_lowered) {
 637          unsigned lower_flrp = (nir->options->lower_flrp16 ? 16 : 0) |
 638                                (nir->options->lower_flrp32 ? 32 : 0) |
 639                                (nir->options->lower_flrp64 ? 64 : 0);
 640          assert(lower_flrp);
 641          bool lower_flrp_progress = false;
 642
 643          NIR_PASS(lower_flrp_progress, nir, nir_lower_flrp, lower_flrp, false /* always_precise */,
 644                   nir->options->lower_ffma);
 645          if (lower_flrp_progress) {
 646             NIR_PASS(progress, nir, nir_opt_constant_folding);
 647             progress = true;
 648          }
 649
 650          /* Nothing should rematerialize any flrps, so we only
 651           * need to do this lowering once.
 652           */
 653          nir->info.flrp_lowered = true;
 654       }
 655
 656       NIR_PASS(progress, nir, nir_opt_undef);
 657       NIR_PASS(progress, nir, nir_opt_conditional_discard);
 658       if (nir->options->max_unroll_iterations) {
 659          NIR_PASS(progress, nir, nir_opt_loop_unroll, 0);
 660       }
 661    } while (progress);
 662 }
 663
 664 static int type_size_vec4(const struct glsl_type *type, bool bindless)
 665 {
 666    return glsl_count_attribute_slots(type, false);
 667 }
 668
 669 static void si_nir_lower_color(nir_shader *nir)
 670 {
 671    nir_function_impl *entrypoint = nir_shader_get_entrypoint(nir);
 672
 673    nir_builder b;
 674    nir_builder_init(&b, entrypoint);
 675
 676    nir_foreach_block (block, entrypoint) {
 677       nir_foreach_instr_safe (instr, block) {
 678          if (instr->type != nir_instr_type_intrinsic)
 679             continue;
 680
 681          nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(instr);
 682
 683          if (intrin->intrinsic != nir_intrinsic_load_deref)
 684             continue;
 685
 686          nir_deref_instr *deref = nir_src_as_deref(intrin->src[0]);
 687          if (deref->mode != nir_var_shader_in)
 688             continue;
 689
 690          b.cursor = nir_before_instr(instr);
 691          nir_variable *var = nir_deref_instr_get_variable(deref);
 692          nir_ssa_def *def;
 693
 694          if (var->data.location == VARYING_SLOT_COL0) {
 695             def = nir_load_color0(&b);
 696             nir->info.fs.color0_interp = var->data.interpolation;
 697             nir->info.fs.color0_sample = var->data.sample;
 698             nir->info.fs.color0_centroid = var->data.centroid;
 699          } else if (var->data.location == VARYING_SLOT_COL1) {
 700             def = nir_load_color1(&b);
 701             nir->info.fs.color1_interp = var->data.interpolation;
 702             nir->info.fs.color1_sample = var->data.sample;
 703             nir->info.fs.color1_centroid = var->data.centroid;
 704          } else {
 705             continue;
 706          }
 707
 708          nir_ssa_def_rewrite_uses(&intrin->dest.ssa, nir_src_for_ssa(def));
 709          nir_instr_remove(instr);
 710       }
 711    }
 712 }
 713
 714 static void si_lower_io(struct nir_shader *nir)
 715 {
 716    /* HW supports indirect indexing for: | Enabled in driver
 717     * -------------------------------------------------------
 718     * VS inputs                          | No
 719     * TCS inputs                         | Yes
 720     * TES inputs                         | Yes
 721     * GS inputs                          | No
 722     * -------------------------------------------------------
 723     * VS outputs before TCS              | No
 724     * VS outputs before GS               | No
 725     * TCS outputs                        | Yes
 726     * TES outputs before GS              | No
 727     */
 728    bool has_indirect_inputs = nir->info.stage == MESA_SHADER_TESS_CTRL ||
 729                               nir->info.stage == MESA_SHADER_TESS_EVAL;
 730    bool has_indirect_outputs = nir->info.stage == MESA_SHADER_TESS_CTRL;
 731
 732    if (!has_indirect_inputs || !has_indirect_outputs) {
 733       NIR_PASS_V(nir, nir_lower_io_to_temporaries, nir_shader_get_entrypoint(nir),
 734                  !has_indirect_outputs, !has_indirect_inputs);
 735
 736       /* Since we're doing nir_lower_io_to_temporaries late, we need
 737        * to lower all the copy_deref's introduced by
 738        * lower_io_to_temporaries before calling nir_lower_io.
 739        */
 740       NIR_PASS_V(nir, nir_split_var_copies);
 741       NIR_PASS_V(nir, nir_lower_var_copies);
 742       NIR_PASS_V(nir, nir_lower_global_vars_to_local);
 743    }
 744
 745    if (nir->info.stage == MESA_SHADER_FRAGMENT)
 746       si_nir_lower_color(nir);
 747
 748    NIR_PASS_V(nir, nir_lower_io, nir_var_shader_out | nir_var_shader_in,
 749               type_size_vec4, 0);
 750    nir->info.io_lowered = true;
 751
 752    /* This pass needs actual constants */
 753    NIR_PASS_V(nir, nir_opt_constant_folding);
 754    NIR_PASS_V(nir, nir_io_add_const_offset_to_base, nir_var_shader_in);
 755    NIR_PASS_V(nir, nir_io_add_const_offset_to_base, nir_var_shader_out);
 756
 757    /* Remove dead derefs, so that nir_validate doesn't fail. */
 758    NIR_PASS_V(nir, nir_opt_dce);
 759
 760    /* Remove input and output nir_variables, because we don't need them
 761     * anymore. Also remove uniforms, because those should have been lowered
 762     * to UBOs already.
 763     */
 764    unsigned modes = nir_var_shader_in | nir_var_shader_out | nir_var_uniform;
 765    nir_foreach_variable_with_modes_safe(var, nir, modes) {
 766       if (var->data.mode == nir_var_uniform &&
 767           (glsl_type_get_image_count(var->type) ||
 768            glsl_type_get_sampler_count(var->type)))
 769          continue;
 770
 771       exec_node_remove(&var->node);
 772    }
 773 }
 774
 775 /**
 776  * Perform "lowering" operations on the NIR that are run once when the shader
 777  * selector is created.
 778  */
 779 static void si_lower_nir(struct si_screen *sscreen, struct nir_shader *nir)
 780 {
 781    /* Perform lowerings (and optimizations) of code.
 782     *
 783     * Performance considerations aside, we must:
 784     * - lower certain ALU operations
 785     * - ensure constant offsets for texture instructions are folded
 786     *   and copy-propagated
 787     */
 788
 789    static const struct nir_lower_tex_options lower_tex_options = {
 790       .lower_txp = ~0u,
 791    };
 792    NIR_PASS_V(nir, nir_lower_tex, &lower_tex_options);
 793
 794    const nir_lower_subgroups_options subgroups_options = {
 795       .subgroup_size = 64,
 796       .ballot_bit_size = 64,
 797       .lower_to_scalar = true,
 798       .lower_subgroup_masks = true,
 799       .lower_vote_trivial = false,
 800       .lower_vote_eq_to_ballot = true,
 801    };
 802    NIR_PASS_V(nir, nir_lower_subgroups, &subgroups_options);
 803
 804    /* Lower load constants to scalar and then clean up the mess */
 805    NIR_PASS_V(nir, nir_lower_load_const_to_scalar);
 806    NIR_PASS_V(nir, nir_lower_var_copies);
 807    NIR_PASS_V(nir, nir_lower_pack);
 808    NIR_PASS_V(nir, nir_opt_access);
 809    si_nir_opts(nir, true);
 810
 811    /* Lower large variables that are always constant with load_constant
 812     * intrinsics, which get turned into PC-relative loads from a data
 813     * section next to the shader.
 814     *
 815     * st/mesa calls finalize_nir twice, but we can't call this pass twice.
 816     */
 817    bool changed = false;
 818    if (!nir->constant_data) {
 819       /* The pass crashes if there are dead temps of lowered IO interface types. */
 820       NIR_PASS_V(nir, nir_remove_dead_variables, nir_var_function_temp, NULL);
 821       NIR_PASS(changed, nir, nir_opt_large_constants, glsl_get_natural_size_align_bytes, 16);
 822    }
 823
 824    changed |= ac_lower_indirect_derefs(nir, sscreen->info.chip_class);
 825    if (changed)
 826       si_nir_opts(nir, false);
 827
 828    NIR_PASS_V(nir, nir_lower_bool_to_int32);
 829    NIR_PASS_V(nir, nir_remove_dead_variables, nir_var_function_temp, NULL);
 830
 831    if (sscreen->debug_flags & DBG(FS_CORRECT_DERIVS_AFTER_KILL))
 832       NIR_PASS_V(nir, nir_lower_discard_to_demote);
 833 }
 834
 835 void si_finalize_nir(struct pipe_screen *screen, void *nirptr, bool optimize)
 836 {
 837    struct si_screen *sscreen = (struct si_screen *)screen;
 838    struct nir_shader *nir = (struct nir_shader *)nirptr;
 839
 840    nir_shader_gather_info(nir, nir_shader_get_entrypoint(nir));
 841    si_lower_io(nir);
 842    si_lower_nir(sscreen, nir);
 843 }