2 * Copyright 2017 Advanced Micro Devices, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
25 #include "si_shader_internal.h"
28 #include "ac_nir_to_llvm.h"
30 #include "tgsi/tgsi_from_mesa.h"
32 #include "compiler/nir/nir.h"
33 #include "compiler/nir_types.h"
35 static nir_variable
* tex_get_texture_var(nir_tex_instr
*instr
)
37 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
38 switch (instr
->src
[i
].src_type
) {
39 case nir_tex_src_texture_deref
:
40 return nir_deref_instr_get_variable(nir_src_as_deref(instr
->src
[i
].src
));
49 static nir_variable
* intrinsic_get_var(nir_intrinsic_instr
*instr
)
51 return nir_deref_instr_get_variable(nir_src_as_deref(instr
->src
[0]));
54 static void scan_instruction(struct tgsi_shader_info
*info
,
57 if (instr
->type
== nir_instr_type_alu
) {
58 nir_alu_instr
*alu
= nir_instr_as_alu(instr
);
63 case nir_op_fddx_fine
:
64 case nir_op_fddy_fine
:
65 case nir_op_fddx_coarse
:
66 case nir_op_fddy_coarse
:
67 info
->uses_derivatives
= true;
72 } else if (instr
->type
== nir_instr_type_tex
) {
73 nir_tex_instr
*tex
= nir_instr_as_tex(instr
);
74 nir_variable
*texture
= tex_get_texture_var(tex
);
77 info
->samplers_declared
|=
78 u_bit_consecutive(tex
->sampler_index
, 1);
80 if (texture
->data
.bindless
)
81 info
->uses_bindless_samplers
= true;
88 info
->uses_derivatives
= true;
93 } else if (instr
->type
== nir_instr_type_intrinsic
) {
94 nir_intrinsic_instr
*intr
= nir_instr_as_intrinsic(instr
);
96 switch (intr
->intrinsic
) {
97 case nir_intrinsic_load_front_face
:
98 info
->uses_frontface
= 1;
100 case nir_intrinsic_load_instance_id
:
101 info
->uses_instanceid
= 1;
103 case nir_intrinsic_load_invocation_id
:
104 info
->uses_invocationid
= true;
106 case nir_intrinsic_load_num_work_groups
:
107 info
->uses_grid_size
= true;
109 case nir_intrinsic_load_local_group_size
:
110 /* The block size is translated to IMM with a fixed block size. */
111 if (info
->properties
[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH
] == 0)
112 info
->uses_block_size
= true;
114 case nir_intrinsic_load_local_invocation_id
:
115 case nir_intrinsic_load_work_group_id
: {
116 unsigned mask
= nir_ssa_def_components_read(&intr
->dest
.ssa
);
118 unsigned i
= u_bit_scan(&mask
);
120 if (intr
->intrinsic
== nir_intrinsic_load_work_group_id
)
121 info
->uses_block_id
[i
] = true;
123 info
->uses_thread_id
[i
] = true;
127 case nir_intrinsic_load_vertex_id
:
128 info
->uses_vertexid
= 1;
130 case nir_intrinsic_load_vertex_id_zero_base
:
131 info
->uses_vertexid_nobase
= 1;
133 case nir_intrinsic_load_base_vertex
:
134 info
->uses_basevertex
= 1;
136 case nir_intrinsic_load_primitive_id
:
137 info
->uses_primid
= 1;
139 case nir_intrinsic_load_sample_mask_in
:
140 info
->reads_samplemask
= true;
142 case nir_intrinsic_load_tess_level_inner
:
143 case nir_intrinsic_load_tess_level_outer
:
144 info
->reads_tess_factors
= true;
146 case nir_intrinsic_image_deref_load
:
147 case nir_intrinsic_image_deref_size
:
148 case nir_intrinsic_image_deref_samples
: {
149 nir_variable
*var
= intrinsic_get_var(intr
);
150 if (var
->data
.bindless
)
151 info
->uses_bindless_images
= true;
155 case nir_intrinsic_image_deref_store
:
156 case nir_intrinsic_image_deref_atomic_add
:
157 case nir_intrinsic_image_deref_atomic_min
:
158 case nir_intrinsic_image_deref_atomic_max
:
159 case nir_intrinsic_image_deref_atomic_and
:
160 case nir_intrinsic_image_deref_atomic_or
:
161 case nir_intrinsic_image_deref_atomic_xor
:
162 case nir_intrinsic_image_deref_atomic_exchange
:
163 case nir_intrinsic_image_deref_atomic_comp_swap
: {
164 nir_variable
*var
= intrinsic_get_var(intr
);
165 if (var
->data
.bindless
)
166 info
->uses_bindless_images
= true;
170 case nir_intrinsic_store_ssbo
:
171 case nir_intrinsic_ssbo_atomic_add
:
172 case nir_intrinsic_ssbo_atomic_imin
:
173 case nir_intrinsic_ssbo_atomic_umin
:
174 case nir_intrinsic_ssbo_atomic_imax
:
175 case nir_intrinsic_ssbo_atomic_umax
:
176 case nir_intrinsic_ssbo_atomic_and
:
177 case nir_intrinsic_ssbo_atomic_or
:
178 case nir_intrinsic_ssbo_atomic_xor
:
179 case nir_intrinsic_ssbo_atomic_exchange
:
180 case nir_intrinsic_ssbo_atomic_comp_swap
:
181 info
->writes_memory
= true;
183 case nir_intrinsic_load_deref
: {
184 nir_variable
*var
= intrinsic_get_var(intr
);
185 nir_variable_mode mode
= var
->data
.mode
;
186 enum glsl_base_type base_type
=
187 glsl_get_base_type(glsl_without_array(var
->type
));
189 if (mode
== nir_var_shader_in
) {
190 switch (var
->data
.interpolation
) {
191 case INTERP_MODE_NONE
:
192 if (glsl_base_type_is_integer(base_type
))
196 case INTERP_MODE_SMOOTH
:
197 if (var
->data
.sample
)
198 info
->uses_persp_sample
= true;
199 else if (var
->data
.centroid
)
200 info
->uses_persp_centroid
= true;
202 info
->uses_persp_center
= true;
205 case INTERP_MODE_NOPERSPECTIVE
:
206 if (var
->data
.sample
)
207 info
->uses_linear_sample
= true;
208 else if (var
->data
.centroid
)
209 info
->uses_linear_centroid
= true;
211 info
->uses_linear_center
= true;
217 case nir_intrinsic_interp_deref_at_centroid
:
218 case nir_intrinsic_interp_deref_at_sample
:
219 case nir_intrinsic_interp_deref_at_offset
: {
220 enum glsl_interp_mode interp
= intrinsic_get_var(intr
)->data
.interpolation
;
222 case INTERP_MODE_SMOOTH
:
223 case INTERP_MODE_NONE
:
224 if (intr
->intrinsic
== nir_intrinsic_interp_deref_at_centroid
)
225 info
->uses_persp_opcode_interp_centroid
= true;
226 else if (intr
->intrinsic
== nir_intrinsic_interp_deref_at_sample
)
227 info
->uses_persp_opcode_interp_sample
= true;
229 info
->uses_persp_opcode_interp_offset
= true;
231 case INTERP_MODE_NOPERSPECTIVE
:
232 if (intr
->intrinsic
== nir_intrinsic_interp_deref_at_centroid
)
233 info
->uses_linear_opcode_interp_centroid
= true;
234 else if (intr
->intrinsic
== nir_intrinsic_interp_deref_at_sample
)
235 info
->uses_linear_opcode_interp_sample
= true;
237 info
->uses_linear_opcode_interp_offset
= true;
239 case INTERP_MODE_FLAT
:
242 unreachable("Unsupported interpoation type");
252 void si_nir_scan_tess_ctrl(const struct nir_shader
*nir
,
253 const struct tgsi_shader_info
*info
,
254 struct tgsi_tessctrl_info
*out
)
256 memset(out
, 0, sizeof(*out
));
258 if (nir
->info
.stage
!= MESA_SHADER_TESS_CTRL
)
261 /* Initial value = true. Here the pass will accumulate results from
262 * multiple segments surrounded by barriers. If tess factors aren't
263 * written at all, it's a shader bug and we don't care if this will be
266 out
->tessfactors_are_def_in_all_invocs
= true;
268 /* TODO: Implement scanning of tess factors, see tgsi backend. */
271 void si_nir_scan_shader(const struct nir_shader
*nir
,
272 struct tgsi_shader_info
*info
)
277 info
->processor
= pipe_shader_type_from_mesa(nir
->info
.stage
);
278 info
->num_tokens
= 2; /* indicate that the shader is non-empty */
279 info
->num_instructions
= 2;
281 info
->properties
[TGSI_PROPERTY_NEXT_SHADER
] =
282 pipe_shader_type_from_mesa(nir
->info
.next_stage
);
284 if (nir
->info
.stage
== MESA_SHADER_TESS_CTRL
) {
285 info
->properties
[TGSI_PROPERTY_TCS_VERTICES_OUT
] =
286 nir
->info
.tess
.tcs_vertices_out
;
289 if (nir
->info
.stage
== MESA_SHADER_TESS_EVAL
) {
290 if (nir
->info
.tess
.primitive_mode
== GL_ISOLINES
)
291 info
->properties
[TGSI_PROPERTY_TES_PRIM_MODE
] = PIPE_PRIM_LINES
;
293 info
->properties
[TGSI_PROPERTY_TES_PRIM_MODE
] = nir
->info
.tess
.primitive_mode
;
295 STATIC_ASSERT((TESS_SPACING_EQUAL
+ 1) % 3 == PIPE_TESS_SPACING_EQUAL
);
296 STATIC_ASSERT((TESS_SPACING_FRACTIONAL_ODD
+ 1) % 3 ==
297 PIPE_TESS_SPACING_FRACTIONAL_ODD
);
298 STATIC_ASSERT((TESS_SPACING_FRACTIONAL_EVEN
+ 1) % 3 ==
299 PIPE_TESS_SPACING_FRACTIONAL_EVEN
);
301 info
->properties
[TGSI_PROPERTY_TES_SPACING
] = (nir
->info
.tess
.spacing
+ 1) % 3;
302 info
->properties
[TGSI_PROPERTY_TES_VERTEX_ORDER_CW
] = !nir
->info
.tess
.ccw
;
303 info
->properties
[TGSI_PROPERTY_TES_POINT_MODE
] = nir
->info
.tess
.point_mode
;
306 if (nir
->info
.stage
== MESA_SHADER_GEOMETRY
) {
307 info
->properties
[TGSI_PROPERTY_GS_INPUT_PRIM
] = nir
->info
.gs
.input_primitive
;
308 info
->properties
[TGSI_PROPERTY_GS_OUTPUT_PRIM
] = nir
->info
.gs
.output_primitive
;
309 info
->properties
[TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES
] = nir
->info
.gs
.vertices_out
;
310 info
->properties
[TGSI_PROPERTY_GS_INVOCATIONS
] = nir
->info
.gs
.invocations
;
313 if (nir
->info
.stage
== MESA_SHADER_FRAGMENT
) {
314 info
->properties
[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL
] =
315 nir
->info
.fs
.early_fragment_tests
| nir
->info
.fs
.post_depth_coverage
;
316 info
->properties
[TGSI_PROPERTY_FS_POST_DEPTH_COVERAGE
] = nir
->info
.fs
.post_depth_coverage
;
318 if (nir
->info
.fs
.pixel_center_integer
) {
319 info
->properties
[TGSI_PROPERTY_FS_COORD_PIXEL_CENTER
] =
320 TGSI_FS_COORD_PIXEL_CENTER_INTEGER
;
323 if (nir
->info
.fs
.depth_layout
!= FRAG_DEPTH_LAYOUT_NONE
) {
324 switch (nir
->info
.fs
.depth_layout
) {
325 case FRAG_DEPTH_LAYOUT_ANY
:
326 info
->properties
[TGSI_PROPERTY_FS_DEPTH_LAYOUT
] = TGSI_FS_DEPTH_LAYOUT_ANY
;
328 case FRAG_DEPTH_LAYOUT_GREATER
:
329 info
->properties
[TGSI_PROPERTY_FS_DEPTH_LAYOUT
] = TGSI_FS_DEPTH_LAYOUT_GREATER
;
331 case FRAG_DEPTH_LAYOUT_LESS
:
332 info
->properties
[TGSI_PROPERTY_FS_DEPTH_LAYOUT
] = TGSI_FS_DEPTH_LAYOUT_LESS
;
334 case FRAG_DEPTH_LAYOUT_UNCHANGED
:
335 info
->properties
[TGSI_PROPERTY_FS_DEPTH_LAYOUT
] = TGSI_FS_DEPTH_LAYOUT_UNCHANGED
;
338 unreachable("Unknow depth layout");
343 if (nir
->info
.stage
== MESA_SHADER_COMPUTE
) {
344 info
->properties
[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH
] = nir
->info
.cs
.local_size
[0];
345 info
->properties
[TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT
] = nir
->info
.cs
.local_size
[1];
346 info
->properties
[TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH
] = nir
->info
.cs
.local_size
[2];
350 uint64_t processed_inputs
= 0;
351 unsigned num_inputs
= 0;
352 nir_foreach_variable(variable
, &nir
->inputs
) {
353 unsigned semantic_name
, semantic_index
;
355 const struct glsl_type
*type
= variable
->type
;
356 if (nir_is_per_vertex_io(variable
, nir
->info
.stage
)) {
357 assert(glsl_type_is_array(type
));
358 type
= glsl_get_array_element(type
);
361 unsigned attrib_count
= glsl_count_attribute_slots(type
,
362 nir
->info
.stage
== MESA_SHADER_VERTEX
);
364 i
= variable
->data
.driver_location
;
366 /* Vertex shader inputs don't have semantics. The state
367 * tracker has already mapped them to attributes via
368 * variable->data.driver_location.
370 if (nir
->info
.stage
== MESA_SHADER_VERTEX
) {
371 /* TODO: gather the actual input useage and remove this. */
372 info
->input_usage_mask
[i
] = TGSI_WRITEMASK_XYZW
;
374 if (glsl_type_is_dual_slot(variable
->type
)) {
377 /* TODO: gather the actual input useage and remove this. */
378 info
->input_usage_mask
[i
+1] = TGSI_WRITEMASK_XYZW
;
384 /* Fragment shader position is a system value. */
385 if (nir
->info
.stage
== MESA_SHADER_FRAGMENT
&&
386 variable
->data
.location
== VARYING_SLOT_POS
) {
387 if (variable
->data
.pixel_center_integer
)
388 info
->properties
[TGSI_PROPERTY_FS_COORD_PIXEL_CENTER
] =
389 TGSI_FS_COORD_PIXEL_CENTER_INTEGER
;
395 for (unsigned j
= 0; j
< attrib_count
; j
++, i
++) {
397 if (processed_inputs
& ((uint64_t)1 << i
))
400 processed_inputs
|= ((uint64_t)1 << i
);
403 tgsi_get_gl_varying_semantic(variable
->data
.location
+ j
, true,
404 &semantic_name
, &semantic_index
);
406 info
->input_semantic_name
[i
] = semantic_name
;
407 info
->input_semantic_index
[i
] = semantic_index
;
409 if (semantic_name
== TGSI_SEMANTIC_PRIMID
)
410 info
->uses_primid
= true;
412 if (variable
->data
.sample
)
413 info
->input_interpolate_loc
[i
] = TGSI_INTERPOLATE_LOC_SAMPLE
;
414 else if (variable
->data
.centroid
)
415 info
->input_interpolate_loc
[i
] = TGSI_INTERPOLATE_LOC_CENTROID
;
417 info
->input_interpolate_loc
[i
] = TGSI_INTERPOLATE_LOC_CENTER
;
419 enum glsl_base_type base_type
=
420 glsl_get_base_type(glsl_without_array(variable
->type
));
422 switch (variable
->data
.interpolation
) {
423 case INTERP_MODE_NONE
:
424 if (glsl_base_type_is_integer(base_type
)) {
425 info
->input_interpolate
[i
] = TGSI_INTERPOLATE_CONSTANT
;
429 if (semantic_name
== TGSI_SEMANTIC_COLOR
) {
430 info
->input_interpolate
[i
] = TGSI_INTERPOLATE_COLOR
;
435 case INTERP_MODE_SMOOTH
:
436 assert(!glsl_base_type_is_integer(base_type
));
438 info
->input_interpolate
[i
] = TGSI_INTERPOLATE_PERSPECTIVE
;
441 case INTERP_MODE_NOPERSPECTIVE
:
442 assert(!glsl_base_type_is_integer(base_type
));
444 info
->input_interpolate
[i
] = TGSI_INTERPOLATE_LINEAR
;
447 case INTERP_MODE_FLAT
:
448 info
->input_interpolate
[i
] = TGSI_INTERPOLATE_CONSTANT
;
452 /* TODO make this more precise */
453 if (variable
->data
.location
== VARYING_SLOT_COL0
)
454 info
->colors_read
|= 0x0f;
455 else if (variable
->data
.location
== VARYING_SLOT_COL1
)
456 info
->colors_read
|= 0xf0;
460 info
->num_inputs
= num_inputs
;
464 uint64_t processed_outputs
= 0;
465 unsigned num_outputs
= 0;
466 nir_foreach_variable(variable
, &nir
->outputs
) {
467 unsigned semantic_name
, semantic_index
;
469 i
= variable
->data
.driver_location
;
471 const struct glsl_type
*type
= variable
->type
;
472 if (nir_is_per_vertex_io(variable
, nir
->info
.stage
)) {
473 assert(glsl_type_is_array(type
));
474 type
= glsl_get_array_element(type
);
477 unsigned attrib_count
= glsl_count_attribute_slots(type
, false);
478 for (unsigned k
= 0; k
< attrib_count
; k
++, i
++) {
480 if (nir
->info
.stage
== MESA_SHADER_FRAGMENT
) {
481 tgsi_get_gl_frag_result_semantic(variable
->data
.location
+ k
,
482 &semantic_name
, &semantic_index
);
484 /* Adjust for dual source blending */
485 if (variable
->data
.index
> 0) {
489 tgsi_get_gl_varying_semantic(variable
->data
.location
+ k
, true,
490 &semantic_name
, &semantic_index
);
493 unsigned num_components
= 4;
494 unsigned vector_elements
= glsl_get_vector_elements(glsl_without_array(variable
->type
));
496 num_components
= vector_elements
;
498 unsigned component
= variable
->data
.location_frac
;
499 if (glsl_type_is_64bit(glsl_without_array(variable
->type
))) {
500 if (glsl_type_is_dual_slot(glsl_without_array(variable
->type
)) && k
% 2) {
501 num_components
= (num_components
* 2) - 4;
504 num_components
= MIN2(num_components
* 2, 4);
509 for (unsigned j
= component
; j
< num_components
+ component
; j
++) {
512 usagemask
|= TGSI_WRITEMASK_X
;
515 usagemask
|= TGSI_WRITEMASK_Y
;
518 usagemask
|= TGSI_WRITEMASK_Z
;
521 usagemask
|= TGSI_WRITEMASK_W
;
524 unreachable("error calculating component index");
528 unsigned gs_out_streams
;
529 if (variable
->data
.stream
& (1u << 31)) {
530 gs_out_streams
= variable
->data
.stream
& ~(1u << 31);
532 assert(variable
->data
.stream
< 4);
534 for (unsigned j
= 0; j
< num_components
; ++j
)
535 gs_out_streams
|= variable
->data
.stream
<< (2 * (component
+ j
));
538 unsigned streamx
= gs_out_streams
& 3;
539 unsigned streamy
= (gs_out_streams
>> 2) & 3;
540 unsigned streamz
= (gs_out_streams
>> 4) & 3;
541 unsigned streamw
= (gs_out_streams
>> 6) & 3;
543 if (usagemask
& TGSI_WRITEMASK_X
) {
544 info
->output_usagemask
[i
] |= TGSI_WRITEMASK_X
;
545 info
->output_streams
[i
] |= streamx
;
546 info
->num_stream_output_components
[streamx
]++;
548 if (usagemask
& TGSI_WRITEMASK_Y
) {
549 info
->output_usagemask
[i
] |= TGSI_WRITEMASK_Y
;
550 info
->output_streams
[i
] |= streamy
<< 2;
551 info
->num_stream_output_components
[streamy
]++;
553 if (usagemask
& TGSI_WRITEMASK_Z
) {
554 info
->output_usagemask
[i
] |= TGSI_WRITEMASK_Z
;
555 info
->output_streams
[i
] |= streamz
<< 4;
556 info
->num_stream_output_components
[streamz
]++;
558 if (usagemask
& TGSI_WRITEMASK_W
) {
559 info
->output_usagemask
[i
] |= TGSI_WRITEMASK_W
;
560 info
->output_streams
[i
] |= streamw
<< 6;
561 info
->num_stream_output_components
[streamw
]++;
564 /* make sure we only count this location once against
565 * the num_outputs counter.
567 if (processed_outputs
& ((uint64_t)1 << i
))
570 processed_outputs
|= ((uint64_t)1 << i
);
573 info
->output_semantic_name
[i
] = semantic_name
;
574 info
->output_semantic_index
[i
] = semantic_index
;
576 switch (semantic_name
) {
577 case TGSI_SEMANTIC_PRIMID
:
578 info
->writes_primid
= true;
580 case TGSI_SEMANTIC_VIEWPORT_INDEX
:
581 info
->writes_viewport_index
= true;
583 case TGSI_SEMANTIC_LAYER
:
584 info
->writes_layer
= true;
586 case TGSI_SEMANTIC_PSIZE
:
587 info
->writes_psize
= true;
589 case TGSI_SEMANTIC_CLIPVERTEX
:
590 info
->writes_clipvertex
= true;
592 case TGSI_SEMANTIC_COLOR
:
593 info
->colors_written
|= 1 << semantic_index
;
595 case TGSI_SEMANTIC_STENCIL
:
596 info
->writes_stencil
= true;
598 case TGSI_SEMANTIC_SAMPLEMASK
:
599 info
->writes_samplemask
= true;
601 case TGSI_SEMANTIC_EDGEFLAG
:
602 info
->writes_edgeflag
= true;
604 case TGSI_SEMANTIC_POSITION
:
605 if (info
->processor
== PIPE_SHADER_FRAGMENT
)
606 info
->writes_z
= true;
608 info
->writes_position
= true;
612 if (nir
->info
.stage
== MESA_SHADER_TESS_CTRL
) {
613 switch (semantic_name
) {
614 case TGSI_SEMANTIC_PATCH
:
615 info
->reads_perpatch_outputs
= true;
617 case TGSI_SEMANTIC_TESSINNER
:
618 case TGSI_SEMANTIC_TESSOUTER
:
619 info
->reads_tessfactor_outputs
= true;
622 info
->reads_pervertex_outputs
= true;
627 unsigned loc
= variable
->data
.location
;
628 if (nir
->info
.stage
== MESA_SHADER_FRAGMENT
&&
629 loc
== FRAG_RESULT_COLOR
&&
630 nir
->info
.outputs_written
& (1ull << loc
)) {
631 assert(attrib_count
== 1);
632 info
->properties
[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS
] = true;
636 info
->num_outputs
= num_outputs
;
638 struct set
*ubo_set
= _mesa_set_create(NULL
, _mesa_hash_pointer
,
639 _mesa_key_pointer_equal
);
641 /* Intialise const_file_max[0] */
642 info
->const_file_max
[0] = -1;
644 unsigned ubo_idx
= 1;
645 nir_foreach_variable(variable
, &nir
->uniforms
) {
646 const struct glsl_type
*type
= variable
->type
;
647 enum glsl_base_type base_type
=
648 glsl_get_base_type(glsl_without_array(type
));
649 unsigned aoa_size
= MAX2(1, glsl_get_aoa_size(type
));
651 /* Gather buffers declared bitmasks. Note: radeonsi doesn't
652 * really use the mask (other than ubo_idx == 1 for regular
653 * uniforms) its really only used for getting the buffer count
654 * so we don't need to worry about the ordering.
656 if (variable
->interface_type
!= NULL
) {
657 if (variable
->data
.mode
== nir_var_uniform
) {
659 unsigned block_count
;
660 if (base_type
!= GLSL_TYPE_INTERFACE
) {
661 struct set_entry
*entry
=
662 _mesa_set_search(ubo_set
, variable
->interface_type
);
664 /* Check if we have already processed
665 * a member from this ubo.
672 block_count
= aoa_size
;
675 info
->const_buffers_declared
|= u_bit_consecutive(ubo_idx
, block_count
);
676 ubo_idx
+= block_count
;
678 _mesa_set_add(ubo_set
, variable
->interface_type
);
681 if (variable
->data
.mode
== nir_var_shader_storage
) {
682 /* TODO: make this more accurate */
683 info
->shader_buffers_declared
=
684 u_bit_consecutive(0, SI_NUM_SHADER_BUFFERS
);
690 /* We rely on the fact that nir_lower_samplers_as_deref has
691 * eliminated struct dereferences.
693 if (base_type
== GLSL_TYPE_SAMPLER
) {
694 if (variable
->data
.bindless
) {
695 info
->const_buffers_declared
|= 1;
696 info
->const_file_max
[0] +=
697 glsl_count_attribute_slots(type
, false);
699 info
->samplers_declared
|=
700 u_bit_consecutive(variable
->data
.binding
, aoa_size
);
702 } else if (base_type
== GLSL_TYPE_IMAGE
) {
703 if (variable
->data
.bindless
) {
704 info
->const_buffers_declared
|= 1;
705 info
->const_file_max
[0] +=
706 glsl_count_attribute_slots(type
, false);
708 info
->images_declared
|=
709 u_bit_consecutive(variable
->data
.binding
, aoa_size
);
711 } else if (base_type
!= GLSL_TYPE_ATOMIC_UINT
) {
712 if (strncmp(variable
->name
, "state.", 6) == 0 ||
713 strncmp(variable
->name
, "gl_", 3) == 0) {
714 /* FIXME: figure out why piglit tests with builtin
715 * uniforms are failing without this.
717 info
->const_buffers_declared
=
718 u_bit_consecutive(0, SI_NUM_CONST_BUFFERS
);
720 info
->const_buffers_declared
|= 1;
721 info
->const_file_max
[0] +=
722 glsl_count_attribute_slots(type
, false);
727 _mesa_set_destroy(ubo_set
, NULL
);
729 info
->num_written_clipdistance
= nir
->info
.clip_distance_array_size
;
730 info
->num_written_culldistance
= nir
->info
.cull_distance_array_size
;
731 info
->clipdist_writemask
= u_bit_consecutive(0, info
->num_written_clipdistance
);
732 info
->culldist_writemask
= u_bit_consecutive(0, info
->num_written_culldistance
);
734 if (info
->processor
== PIPE_SHADER_FRAGMENT
)
735 info
->uses_kill
= nir
->info
.fs
.uses_discard
;
737 func
= (struct nir_function
*)exec_list_get_head_const(&nir
->functions
);
738 nir_foreach_block(block
, func
->impl
) {
739 nir_foreach_instr(instr
, block
)
740 scan_instruction(info
, instr
);
745 * Perform "lowering" operations on the NIR that are run once when the shader
746 * selector is created.
749 si_lower_nir(struct si_shader_selector
* sel
)
751 /* Disable const buffer fast path for old LLVM versions */
752 if (sel
->screen
->info
.chip_class
== SI
&& HAVE_LLVM
< 0x0600 &&
753 sel
->info
.const_buffers_declared
== 1 &&
754 sel
->info
.shader_buffers_declared
== 0) {
755 sel
->info
.const_buffers_declared
|= 0x2;
758 /* Adjust the driver location of inputs and outputs. The state tracker
759 * interprets them as slots, while the ac/nir backend interprets them
760 * as individual components.
762 nir_foreach_variable(variable
, &sel
->nir
->inputs
)
763 variable
->data
.driver_location
*= 4;
765 nir_foreach_variable(variable
, &sel
->nir
->outputs
) {
766 variable
->data
.driver_location
*= 4;
768 if (sel
->nir
->info
.stage
== MESA_SHADER_FRAGMENT
) {
769 if (variable
->data
.location
== FRAG_RESULT_DEPTH
)
770 variable
->data
.driver_location
+= 2;
771 else if (variable
->data
.location
== FRAG_RESULT_STENCIL
)
772 variable
->data
.driver_location
+= 1;
776 /* Perform lowerings (and optimizations) of code.
778 * Performance considerations aside, we must:
779 * - lower certain ALU operations
780 * - ensure constant offsets for texture instructions are folded
781 * and copy-propagated
783 NIR_PASS_V(sel
->nir
, nir_lower_returns
);
784 NIR_PASS_V(sel
->nir
, nir_lower_vars_to_ssa
);
785 NIR_PASS_V(sel
->nir
, nir_lower_alu_to_scalar
);
786 NIR_PASS_V(sel
->nir
, nir_lower_phis_to_scalar
);
788 static const struct nir_lower_tex_options lower_tex_options
= {
791 NIR_PASS_V(sel
->nir
, nir_lower_tex
, &lower_tex_options
);
793 const nir_lower_subgroups_options subgroups_options
= {
795 .ballot_bit_size
= 64,
796 .lower_to_scalar
= true,
797 .lower_subgroup_masks
= true,
798 .lower_vote_trivial
= false,
799 .lower_vote_eq_to_ballot
= true,
801 NIR_PASS_V(sel
->nir
, nir_lower_subgroups
, &subgroups_options
);
803 ac_lower_indirect_derefs(sel
->nir
, sel
->screen
->info
.chip_class
);
805 NIR_PASS_V(sel
->nir
, nir_lower_load_const_to_scalar
);
811 /* (Constant) copy propagation is needed for txf with offsets. */
812 NIR_PASS(progress
, sel
->nir
, nir_copy_prop
);
813 NIR_PASS(progress
, sel
->nir
, nir_opt_remove_phis
);
814 NIR_PASS(progress
, sel
->nir
, nir_opt_dce
);
815 if (nir_opt_trivial_continues(sel
->nir
)) {
817 NIR_PASS(progress
, sel
->nir
, nir_copy_prop
);
818 NIR_PASS(progress
, sel
->nir
, nir_opt_dce
);
820 NIR_PASS(progress
, sel
->nir
, nir_opt_if
);
821 NIR_PASS(progress
, sel
->nir
, nir_opt_dead_cf
);
822 NIR_PASS(progress
, sel
->nir
, nir_opt_cse
);
823 NIR_PASS(progress
, sel
->nir
, nir_opt_peephole_select
, 8);
825 /* Needed for algebraic lowering */
826 NIR_PASS(progress
, sel
->nir
, nir_opt_algebraic
);
827 NIR_PASS(progress
, sel
->nir
, nir_opt_constant_folding
);
829 NIR_PASS(progress
, sel
->nir
, nir_opt_undef
);
830 NIR_PASS(progress
, sel
->nir
, nir_opt_conditional_discard
);
831 if (sel
->nir
->options
->max_unroll_iterations
) {
832 NIR_PASS(progress
, sel
->nir
, nir_opt_loop_unroll
, 0);
837 static void declare_nir_input_vs(struct si_shader_context
*ctx
,
838 struct nir_variable
*variable
,
839 unsigned input_index
,
842 si_llvm_load_input_vs(ctx
, input_index
, out
);
845 static void declare_nir_input_fs(struct si_shader_context
*ctx
,
846 struct nir_variable
*variable
,
847 unsigned input_index
,
850 unsigned slot
= variable
->data
.location
;
851 if (slot
== VARYING_SLOT_POS
) {
852 out
[0] = LLVMGetParam(ctx
->main_fn
, SI_PARAM_POS_X_FLOAT
);
853 out
[1] = LLVMGetParam(ctx
->main_fn
, SI_PARAM_POS_Y_FLOAT
);
854 out
[2] = LLVMGetParam(ctx
->main_fn
, SI_PARAM_POS_Z_FLOAT
);
855 out
[3] = ac_build_fdiv(&ctx
->ac
, ctx
->ac
.f32_1
,
856 LLVMGetParam(ctx
->main_fn
, SI_PARAM_POS_W_FLOAT
));
860 si_llvm_load_input_fs(ctx
, input_index
, out
);
864 si_nir_lookup_interp_param(struct ac_shader_abi
*abi
,
865 enum glsl_interp_mode interp
, unsigned location
)
867 struct si_shader_context
*ctx
= si_shader_context_from_abi(abi
);
868 int interp_param_idx
= -1;
871 case INTERP_MODE_FLAT
:
873 case INTERP_MODE_SMOOTH
:
874 case INTERP_MODE_NONE
:
875 if (location
== INTERP_CENTER
)
876 interp_param_idx
= SI_PARAM_PERSP_CENTER
;
877 else if (location
== INTERP_CENTROID
)
878 interp_param_idx
= SI_PARAM_PERSP_CENTROID
;
879 else if (location
== INTERP_SAMPLE
)
880 interp_param_idx
= SI_PARAM_PERSP_SAMPLE
;
882 case INTERP_MODE_NOPERSPECTIVE
:
883 if (location
== INTERP_CENTER
)
884 interp_param_idx
= SI_PARAM_LINEAR_CENTER
;
885 else if (location
== INTERP_CENTROID
)
886 interp_param_idx
= SI_PARAM_LINEAR_CENTROID
;
887 else if (location
== INTERP_SAMPLE
)
888 interp_param_idx
= SI_PARAM_LINEAR_SAMPLE
;
891 assert(!"Unhandled interpolation mode.");
895 return interp_param_idx
!= -1 ?
896 LLVMGetParam(ctx
->main_fn
, interp_param_idx
) : NULL
;
900 si_nir_load_sampler_desc(struct ac_shader_abi
*abi
,
901 unsigned descriptor_set
, unsigned base_index
,
902 unsigned constant_index
, LLVMValueRef dynamic_index
,
903 enum ac_descriptor_type desc_type
, bool image
,
904 bool write
, bool bindless
)
906 struct si_shader_context
*ctx
= si_shader_context_from_abi(abi
);
907 LLVMBuilderRef builder
= ctx
->ac
.builder
;
908 LLVMValueRef list
= LLVMGetParam(ctx
->main_fn
, ctx
->param_samplers_and_images
);
911 assert(!descriptor_set
);
913 dynamic_index
= dynamic_index
? dynamic_index
: ctx
->ac
.i32_0
;
914 index
= LLVMBuildAdd(builder
, dynamic_index
,
915 LLVMConstInt(ctx
->ac
.i32
, base_index
+ constant_index
, false),
919 assert(desc_type
== AC_DESC_IMAGE
|| desc_type
== AC_DESC_BUFFER
);
920 assert(base_index
+ constant_index
< ctx
->num_images
);
923 index
= si_llvm_bound_index(ctx
, index
, ctx
->num_images
);
925 index
= LLVMBuildSub(ctx
->ac
.builder
,
926 LLVMConstInt(ctx
->i32
, SI_NUM_IMAGES
- 1, 0),
929 /* TODO: be smarter about when we use dcc_off */
930 return si_load_image_desc(ctx
, list
, index
, desc_type
, write
);
933 assert(base_index
+ constant_index
< ctx
->num_samplers
);
936 index
= si_llvm_bound_index(ctx
, index
, ctx
->num_samplers
);
938 index
= LLVMBuildAdd(ctx
->ac
.builder
, index
,
939 LLVMConstInt(ctx
->i32
, SI_NUM_IMAGES
/ 2, 0), "");
941 return si_load_sampler_desc(ctx
, list
, index
, desc_type
);
944 static void bitcast_inputs(struct si_shader_context
*ctx
,
945 LLVMValueRef data
[4],
948 for (unsigned chan
= 0; chan
< 4; chan
++) {
949 ctx
->inputs
[input_idx
+ chan
] =
950 LLVMBuildBitCast(ctx
->ac
.builder
, data
[chan
], ctx
->ac
.i32
, "");
954 bool si_nir_build_llvm(struct si_shader_context
*ctx
, struct nir_shader
*nir
)
956 struct tgsi_shader_info
*info
= &ctx
->shader
->selector
->info
;
958 if (nir
->info
.stage
== MESA_SHADER_VERTEX
||
959 nir
->info
.stage
== MESA_SHADER_FRAGMENT
) {
960 uint64_t processed_inputs
= 0;
961 nir_foreach_variable(variable
, &nir
->inputs
) {
962 unsigned attrib_count
= glsl_count_attribute_slots(variable
->type
,
963 nir
->info
.stage
== MESA_SHADER_VERTEX
);
964 unsigned input_idx
= variable
->data
.driver_location
;
966 LLVMValueRef data
[4];
967 unsigned loc
= variable
->data
.location
;
969 for (unsigned i
= 0; i
< attrib_count
; i
++) {
970 /* Packed components share the same location so skip
971 * them if we have already processed the location.
973 if (processed_inputs
& ((uint64_t)1 << (loc
+ i
))) {
978 if (nir
->info
.stage
== MESA_SHADER_VERTEX
) {
979 declare_nir_input_vs(ctx
, variable
, input_idx
/ 4, data
);
980 bitcast_inputs(ctx
, data
, input_idx
);
981 if (glsl_type_is_dual_slot(variable
->type
)) {
983 declare_nir_input_vs(ctx
, variable
, input_idx
/ 4, data
);
984 bitcast_inputs(ctx
, data
, input_idx
);
986 } else if (nir
->info
.stage
== MESA_SHADER_FRAGMENT
) {
987 declare_nir_input_fs(ctx
, variable
, input_idx
/ 4, data
);
988 bitcast_inputs(ctx
, data
, input_idx
);
991 processed_inputs
|= ((uint64_t)1 << (loc
+ i
));
997 ctx
->abi
.inputs
= &ctx
->inputs
[0];
998 ctx
->abi
.load_sampler_desc
= si_nir_load_sampler_desc
;
999 ctx
->abi
.clamp_shadow_reference
= true;
1001 ctx
->num_samplers
= util_last_bit(info
->samplers_declared
);
1002 ctx
->num_images
= util_last_bit(info
->images_declared
);
1004 if (ctx
->shader
->selector
->info
.properties
[TGSI_PROPERTY_CS_LOCAL_SIZE
]) {
1005 assert(nir
->info
.stage
== MESA_SHADER_COMPUTE
);
1006 si_declare_compute_memory(ctx
);
1008 ac_nir_translate(&ctx
->ac
, &ctx
->abi
, nir
);