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[mesa.git] / src / gallium / drivers / radeonsi / si_shader_nir.c
1 /*
2 * Copyright 2017 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23
24 #include "si_shader_internal.h"
25 #include "si_pipe.h"
26
27 #include "ac_nir_to_llvm.h"
28
29 #include "tgsi/tgsi_from_mesa.h"
30
31 #include "compiler/nir/nir.h"
32 #include "compiler/nir_types.h"
33
34
35 static void scan_instruction(struct tgsi_shader_info *info,
36 nir_instr *instr)
37 {
38 if (instr->type == nir_instr_type_alu) {
39 nir_alu_instr *alu = nir_instr_as_alu(instr);
40
41 switch (alu->op) {
42 case nir_op_fddx:
43 case nir_op_fddy:
44 case nir_op_fddx_fine:
45 case nir_op_fddy_fine:
46 case nir_op_fddx_coarse:
47 case nir_op_fddy_coarse:
48 info->uses_derivatives = true;
49 break;
50 default:
51 break;
52 }
53 } else if (instr->type == nir_instr_type_tex) {
54 nir_tex_instr *tex = nir_instr_as_tex(instr);
55
56 if (!tex->texture) {
57 info->samplers_declared |=
58 u_bit_consecutive(tex->sampler_index, 1);
59 }
60
61 switch (tex->op) {
62 case nir_texop_tex:
63 case nir_texop_txb:
64 case nir_texop_lod:
65 info->uses_derivatives = true;
66 break;
67 default:
68 break;
69 }
70 } else if (instr->type == nir_instr_type_intrinsic) {
71 nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);
72
73 switch (intr->intrinsic) {
74 case nir_intrinsic_load_front_face:
75 info->uses_frontface = 1;
76 break;
77 case nir_intrinsic_load_instance_id:
78 info->uses_instanceid = 1;
79 break;
80 case nir_intrinsic_load_invocation_id:
81 info->uses_invocationid = true;
82 break;
83 case nir_intrinsic_load_num_work_groups:
84 info->uses_grid_size = true;
85 break;
86 case nir_intrinsic_load_local_group_size:
87 /* The block size is translated to IMM with a fixed block size. */
88 if (info->properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] == 0)
89 info->uses_block_size = true;
90 break;
91 case nir_intrinsic_load_local_invocation_id:
92 case nir_intrinsic_load_work_group_id: {
93 unsigned mask = nir_ssa_def_components_read(&intr->dest.ssa);
94 while (mask) {
95 unsigned i = u_bit_scan(&mask);
96
97 if (intr->intrinsic == nir_intrinsic_load_work_group_id)
98 info->uses_block_id[i] = true;
99 else
100 info->uses_thread_id[i] = true;
101 }
102 break;
103 }
104 case nir_intrinsic_load_vertex_id:
105 info->uses_vertexid = 1;
106 break;
107 case nir_intrinsic_load_vertex_id_zero_base:
108 info->uses_vertexid_nobase = 1;
109 break;
110 case nir_intrinsic_load_base_vertex:
111 info->uses_basevertex = 1;
112 break;
113 case nir_intrinsic_load_primitive_id:
114 info->uses_primid = 1;
115 break;
116 case nir_intrinsic_load_sample_mask_in:
117 info->reads_samplemask = true;
118 break;
119 case nir_intrinsic_load_tess_level_inner:
120 case nir_intrinsic_load_tess_level_outer:
121 info->reads_tess_factors = true;
122 break;
123 case nir_intrinsic_image_store:
124 case nir_intrinsic_image_atomic_add:
125 case nir_intrinsic_image_atomic_min:
126 case nir_intrinsic_image_atomic_max:
127 case nir_intrinsic_image_atomic_and:
128 case nir_intrinsic_image_atomic_or:
129 case nir_intrinsic_image_atomic_xor:
130 case nir_intrinsic_image_atomic_exchange:
131 case nir_intrinsic_image_atomic_comp_swap:
132 case nir_intrinsic_store_ssbo:
133 case nir_intrinsic_ssbo_atomic_add:
134 case nir_intrinsic_ssbo_atomic_imin:
135 case nir_intrinsic_ssbo_atomic_umin:
136 case nir_intrinsic_ssbo_atomic_imax:
137 case nir_intrinsic_ssbo_atomic_umax:
138 case nir_intrinsic_ssbo_atomic_and:
139 case nir_intrinsic_ssbo_atomic_or:
140 case nir_intrinsic_ssbo_atomic_xor:
141 case nir_intrinsic_ssbo_atomic_exchange:
142 case nir_intrinsic_ssbo_atomic_comp_swap:
143 info->writes_memory = true;
144 break;
145 case nir_intrinsic_load_var: {
146 nir_variable *var = intr->variables[0]->var;
147 nir_variable_mode mode = var->data.mode;
148 enum glsl_base_type base_type =
149 glsl_get_base_type(glsl_without_array(var->type));
150
151 if (mode == nir_var_shader_in) {
152 switch (var->data.interpolation) {
153 case INTERP_MODE_NONE:
154 if (glsl_base_type_is_integer(base_type))
155 break;
156
157 /* fall-through */
158 case INTERP_MODE_SMOOTH:
159 if (var->data.sample)
160 info->uses_persp_sample = true;
161 else if (var->data.centroid)
162 info->uses_persp_centroid = true;
163 else
164 info->uses_persp_center = true;
165 break;
166
167 case INTERP_MODE_NOPERSPECTIVE:
168 if (var->data.sample)
169 info->uses_linear_sample = true;
170 else if (var->data.centroid)
171 info->uses_linear_centroid = true;
172 else
173 info->uses_linear_center = true;
174 break;
175 }
176 }
177 break;
178 }
179 case nir_intrinsic_interp_var_at_centroid:
180 case nir_intrinsic_interp_var_at_sample:
181 case nir_intrinsic_interp_var_at_offset: {
182 enum glsl_interp_mode interp =
183 intr->variables[0]->var->data.interpolation;
184 switch (interp) {
185 case INTERP_MODE_SMOOTH:
186 case INTERP_MODE_NONE:
187 if (intr->intrinsic == nir_intrinsic_interp_var_at_centroid)
188 info->uses_persp_opcode_interp_centroid = true;
189 else if (intr->intrinsic == nir_intrinsic_interp_var_at_sample)
190 info->uses_persp_opcode_interp_sample = true;
191 else
192 info->uses_persp_opcode_interp_offset = true;
193 break;
194 case INTERP_MODE_NOPERSPECTIVE:
195 if (intr->intrinsic == nir_intrinsic_interp_var_at_centroid)
196 info->uses_linear_opcode_interp_centroid = true;
197 else if (intr->intrinsic == nir_intrinsic_interp_var_at_sample)
198 info->uses_linear_opcode_interp_sample = true;
199 else
200 info->uses_linear_opcode_interp_offset = true;
201 break;
202 case INTERP_MODE_FLAT:
203 break;
204 default:
205 unreachable("Unsupported interpoation type");
206 }
207 break;
208 }
209 default:
210 break;
211 }
212 }
213 }
214
215 void si_nir_scan_tess_ctrl(const struct nir_shader *nir,
216 const struct tgsi_shader_info *info,
217 struct tgsi_tessctrl_info *out)
218 {
219 memset(out, 0, sizeof(*out));
220
221 if (nir->info.stage != MESA_SHADER_TESS_CTRL)
222 return;
223
224 /* Initial value = true. Here the pass will accumulate results from
225 * multiple segments surrounded by barriers. If tess factors aren't
226 * written at all, it's a shader bug and we don't care if this will be
227 * true.
228 */
229 out->tessfactors_are_def_in_all_invocs = true;
230
231 /* TODO: Implement scanning of tess factors, see tgsi backend. */
232 }
233
234 void si_nir_scan_shader(const struct nir_shader *nir,
235 struct tgsi_shader_info *info)
236 {
237 nir_function *func;
238 unsigned i;
239
240 info->processor = pipe_shader_type_from_mesa(nir->info.stage);
241 info->num_tokens = 2; /* indicate that the shader is non-empty */
242 info->num_instructions = 2;
243
244 if (nir->info.stage == MESA_SHADER_TESS_CTRL) {
245 info->properties[TGSI_PROPERTY_TCS_VERTICES_OUT] =
246 nir->info.tess.tcs_vertices_out;
247 }
248
249 if (nir->info.stage == MESA_SHADER_TESS_EVAL) {
250 if (nir->info.tess.primitive_mode == GL_ISOLINES)
251 info->properties[TGSI_PROPERTY_TES_PRIM_MODE] = PIPE_PRIM_LINES;
252 else
253 info->properties[TGSI_PROPERTY_TES_PRIM_MODE] = nir->info.tess.primitive_mode;
254
255 STATIC_ASSERT((TESS_SPACING_EQUAL + 1) % 3 == PIPE_TESS_SPACING_EQUAL);
256 STATIC_ASSERT((TESS_SPACING_FRACTIONAL_ODD + 1) % 3 ==
257 PIPE_TESS_SPACING_FRACTIONAL_ODD);
258 STATIC_ASSERT((TESS_SPACING_FRACTIONAL_EVEN + 1) % 3 ==
259 PIPE_TESS_SPACING_FRACTIONAL_EVEN);
260
261 info->properties[TGSI_PROPERTY_TES_SPACING] = (nir->info.tess.spacing + 1) % 3;
262 info->properties[TGSI_PROPERTY_TES_VERTEX_ORDER_CW] = !nir->info.tess.ccw;
263 info->properties[TGSI_PROPERTY_TES_POINT_MODE] = nir->info.tess.point_mode;
264 }
265
266 if (nir->info.stage == MESA_SHADER_GEOMETRY) {
267 info->properties[TGSI_PROPERTY_GS_INPUT_PRIM] = nir->info.gs.input_primitive;
268 info->properties[TGSI_PROPERTY_GS_OUTPUT_PRIM] = nir->info.gs.output_primitive;
269 info->properties[TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES] = nir->info.gs.vertices_out;
270 info->properties[TGSI_PROPERTY_GS_INVOCATIONS] = nir->info.gs.invocations;
271 }
272
273 if (nir->info.stage == MESA_SHADER_FRAGMENT) {
274 info->properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL] =
275 nir->info.fs.early_fragment_tests | nir->info.fs.post_depth_coverage;
276 info->properties[TGSI_PROPERTY_FS_POST_DEPTH_COVERAGE] = nir->info.fs.post_depth_coverage;
277
278 if (nir->info.fs.pixel_center_integer) {
279 info->properties[TGSI_PROPERTY_FS_COORD_PIXEL_CENTER] =
280 TGSI_FS_COORD_PIXEL_CENTER_INTEGER;
281 }
282
283 if (nir->info.fs.depth_layout != FRAG_DEPTH_LAYOUT_NONE) {
284 switch (nir->info.fs.depth_layout) {
285 case FRAG_DEPTH_LAYOUT_ANY:
286 info->properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT] = TGSI_FS_DEPTH_LAYOUT_ANY;
287 break;
288 case FRAG_DEPTH_LAYOUT_GREATER:
289 info->properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT] = TGSI_FS_DEPTH_LAYOUT_GREATER;
290 break;
291 case FRAG_DEPTH_LAYOUT_LESS:
292 info->properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT] = TGSI_FS_DEPTH_LAYOUT_LESS;
293 break;
294 case FRAG_DEPTH_LAYOUT_UNCHANGED:
295 info->properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT] = TGSI_FS_DEPTH_LAYOUT_UNCHANGED;
296 break;
297 default:
298 unreachable("Unknow depth layout");
299 }
300 }
301 }
302
303 if (nir->info.stage == MESA_SHADER_COMPUTE) {
304 info->properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] = nir->info.cs.local_size[0];
305 info->properties[TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT] = nir->info.cs.local_size[1];
306 info->properties[TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH] = nir->info.cs.local_size[2];
307 }
308
309 i = 0;
310 uint64_t processed_inputs = 0;
311 unsigned num_inputs = 0;
312 nir_foreach_variable(variable, &nir->inputs) {
313 unsigned semantic_name, semantic_index;
314
315 const struct glsl_type *type = variable->type;
316 if (nir_is_per_vertex_io(variable, nir->info.stage)) {
317 assert(glsl_type_is_array(type));
318 type = glsl_get_array_element(type);
319 }
320
321 unsigned attrib_count = glsl_count_attribute_slots(type,
322 nir->info.stage == MESA_SHADER_VERTEX);
323
324 i = variable->data.driver_location;
325
326 /* Vertex shader inputs don't have semantics. The state
327 * tracker has already mapped them to attributes via
328 * variable->data.driver_location.
329 */
330 if (nir->info.stage == MESA_SHADER_VERTEX) {
331 /* TODO: gather the actual input useage and remove this. */
332 info->input_usage_mask[i] = TGSI_WRITEMASK_XYZW;
333
334 if (glsl_type_is_dual_slot(variable->type)) {
335 num_inputs += 2;
336
337 /* TODO: gather the actual input useage and remove this. */
338 info->input_usage_mask[i+1] = TGSI_WRITEMASK_XYZW;
339 } else
340 num_inputs++;
341 continue;
342 }
343
344 /* Fragment shader position is a system value. */
345 if (nir->info.stage == MESA_SHADER_FRAGMENT &&
346 variable->data.location == VARYING_SLOT_POS) {
347 if (variable->data.pixel_center_integer)
348 info->properties[TGSI_PROPERTY_FS_COORD_PIXEL_CENTER] =
349 TGSI_FS_COORD_PIXEL_CENTER_INTEGER;
350
351 num_inputs++;
352 continue;
353 }
354
355 for (unsigned j = 0; j < attrib_count; j++, i++) {
356
357 if (processed_inputs & ((uint64_t)1 << i))
358 continue;
359
360 processed_inputs |= ((uint64_t)1 << i);
361 num_inputs++;
362
363 tgsi_get_gl_varying_semantic(variable->data.location + j, true,
364 &semantic_name, &semantic_index);
365
366 info->input_semantic_name[i] = semantic_name;
367 info->input_semantic_index[i] = semantic_index;
368
369 if (semantic_name == TGSI_SEMANTIC_PRIMID)
370 info->uses_primid = true;
371
372 if (variable->data.sample)
373 info->input_interpolate_loc[i] = TGSI_INTERPOLATE_LOC_SAMPLE;
374 else if (variable->data.centroid)
375 info->input_interpolate_loc[i] = TGSI_INTERPOLATE_LOC_CENTROID;
376 else
377 info->input_interpolate_loc[i] = TGSI_INTERPOLATE_LOC_CENTER;
378
379 enum glsl_base_type base_type =
380 glsl_get_base_type(glsl_without_array(variable->type));
381
382 switch (variable->data.interpolation) {
383 case INTERP_MODE_NONE:
384 if (glsl_base_type_is_integer(base_type)) {
385 info->input_interpolate[i] = TGSI_INTERPOLATE_CONSTANT;
386 break;
387 }
388
389 if (semantic_name == TGSI_SEMANTIC_COLOR) {
390 info->input_interpolate[i] = TGSI_INTERPOLATE_COLOR;
391 break;
392 }
393 /* fall-through */
394
395 case INTERP_MODE_SMOOTH:
396 assert(!glsl_base_type_is_integer(base_type));
397
398 info->input_interpolate[i] = TGSI_INTERPOLATE_PERSPECTIVE;
399 break;
400
401 case INTERP_MODE_NOPERSPECTIVE:
402 assert(!glsl_base_type_is_integer(base_type));
403
404 info->input_interpolate[i] = TGSI_INTERPOLATE_LINEAR;
405 break;
406
407 case INTERP_MODE_FLAT:
408 info->input_interpolate[i] = TGSI_INTERPOLATE_CONSTANT;
409 break;
410 }
411
412 /* TODO make this more precise */
413 if (variable->data.location == VARYING_SLOT_COL0)
414 info->colors_read |= 0x0f;
415 else if (variable->data.location == VARYING_SLOT_COL1)
416 info->colors_read |= 0xf0;
417 }
418 }
419
420 info->num_inputs = num_inputs;
421
422
423 i = 0;
424 uint64_t processed_outputs = 0;
425 unsigned num_outputs = 0;
426 nir_foreach_variable(variable, &nir->outputs) {
427 unsigned semantic_name, semantic_index;
428
429 if (nir->info.stage == MESA_SHADER_FRAGMENT) {
430 tgsi_get_gl_frag_result_semantic(variable->data.location,
431 &semantic_name, &semantic_index);
432
433 /* Adjust for dual source blending */
434 if (variable->data.index > 0) {
435 semantic_index++;
436 }
437 } else {
438 tgsi_get_gl_varying_semantic(variable->data.location, true,
439 &semantic_name, &semantic_index);
440 }
441
442 i = variable->data.driver_location;
443
444 unsigned num_components = 4;
445 unsigned vector_elements = glsl_get_vector_elements(glsl_without_array(variable->type));
446 if (vector_elements)
447 num_components = vector_elements;
448
449 if (glsl_type_is_64bit(glsl_without_array(variable->type)))
450 num_components = MIN2(num_components * 2, 4);
451
452 ubyte usagemask = 0;
453 for (unsigned j = 0; j < num_components; j++) {
454 switch (j + variable->data.location_frac) {
455 case 0:
456 usagemask |= TGSI_WRITEMASK_X;
457 break;
458 case 1:
459 usagemask |= TGSI_WRITEMASK_Y;
460 break;
461 case 2:
462 usagemask |= TGSI_WRITEMASK_Z;
463 break;
464 case 3:
465 usagemask |= TGSI_WRITEMASK_W;
466 break;
467 default:
468 unreachable("error calculating component index");
469 }
470 }
471
472 unsigned gs_out_streams;
473 if (variable->data.stream & (1u << 31)) {
474 gs_out_streams = variable->data.stream & ~(1u << 31);
475 } else {
476 assert(variable->data.stream < 4);
477 gs_out_streams = 0;
478 for (unsigned j = 0; j < num_components; ++j)
479 gs_out_streams |= variable->data.stream << (2 * (variable->data.location_frac + j));
480 }
481
482 unsigned streamx = gs_out_streams & 3;
483 unsigned streamy = (gs_out_streams >> 2) & 3;
484 unsigned streamz = (gs_out_streams >> 4) & 3;
485 unsigned streamw = (gs_out_streams >> 6) & 3;
486
487 if (usagemask & TGSI_WRITEMASK_X) {
488 info->output_usagemask[i] |= TGSI_WRITEMASK_X;
489 info->output_streams[i] |= streamx;
490 info->num_stream_output_components[streamx]++;
491 }
492 if (usagemask & TGSI_WRITEMASK_Y) {
493 info->output_usagemask[i] |= TGSI_WRITEMASK_Y;
494 info->output_streams[i] |= streamy << 2;
495 info->num_stream_output_components[streamy]++;
496 }
497 if (usagemask & TGSI_WRITEMASK_Z) {
498 info->output_usagemask[i] |= TGSI_WRITEMASK_Z;
499 info->output_streams[i] |= streamz << 4;
500 info->num_stream_output_components[streamz]++;
501 }
502 if (usagemask & TGSI_WRITEMASK_W) {
503 info->output_usagemask[i] |= TGSI_WRITEMASK_W;
504 info->output_streams[i] |= streamw << 6;
505 info->num_stream_output_components[streamw]++;
506 }
507
508 /* make sure we only count this location once against the
509 * num_outputs counter.
510 */
511 if (processed_outputs & ((uint64_t)1 << i))
512 continue;
513
514 processed_outputs |= ((uint64_t)1 << i);
515 num_outputs++;
516
517 info->output_semantic_name[i] = semantic_name;
518 info->output_semantic_index[i] = semantic_index;
519
520 switch (semantic_name) {
521 case TGSI_SEMANTIC_PRIMID:
522 info->writes_primid = true;
523 break;
524 case TGSI_SEMANTIC_VIEWPORT_INDEX:
525 info->writes_viewport_index = true;
526 break;
527 case TGSI_SEMANTIC_LAYER:
528 info->writes_layer = true;
529 break;
530 case TGSI_SEMANTIC_PSIZE:
531 info->writes_psize = true;
532 break;
533 case TGSI_SEMANTIC_CLIPVERTEX:
534 info->writes_clipvertex = true;
535 break;
536 case TGSI_SEMANTIC_COLOR:
537 info->colors_written |= 1 << semantic_index;
538 break;
539 case TGSI_SEMANTIC_STENCIL:
540 info->writes_stencil = true;
541 break;
542 case TGSI_SEMANTIC_SAMPLEMASK:
543 info->writes_samplemask = true;
544 break;
545 case TGSI_SEMANTIC_EDGEFLAG:
546 info->writes_edgeflag = true;
547 break;
548 case TGSI_SEMANTIC_POSITION:
549 if (info->processor == PIPE_SHADER_FRAGMENT)
550 info->writes_z = true;
551 else
552 info->writes_position = true;
553 break;
554 }
555
556 if (nir->info.stage == MESA_SHADER_TESS_CTRL) {
557 switch (semantic_name) {
558 case TGSI_SEMANTIC_PATCH:
559 info->reads_perpatch_outputs = true;
560 break;
561 case TGSI_SEMANTIC_TESSINNER:
562 case TGSI_SEMANTIC_TESSOUTER:
563 info->reads_tessfactor_outputs = true;
564 break;
565 default:
566 info->reads_pervertex_outputs = true;
567 }
568 }
569
570 unsigned loc = variable->data.location;
571 if (loc == FRAG_RESULT_COLOR &&
572 nir->info.outputs_written & (1ull << loc)) {
573 info->properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS] = true;
574 }
575 }
576
577 info->num_outputs = num_outputs;
578
579 nir_foreach_variable(variable, &nir->uniforms) {
580 const struct glsl_type *type = variable->type;
581 enum glsl_base_type base_type =
582 glsl_get_base_type(glsl_without_array(type));
583 unsigned aoa_size = MAX2(1, glsl_get_aoa_size(type));
584
585 /* We rely on the fact that nir_lower_samplers_as_deref has
586 * eliminated struct dereferences.
587 */
588 if (base_type == GLSL_TYPE_SAMPLER)
589 info->samplers_declared |=
590 u_bit_consecutive(variable->data.binding, aoa_size);
591 else if (base_type == GLSL_TYPE_IMAGE)
592 info->images_declared |=
593 u_bit_consecutive(variable->data.binding, aoa_size);
594 }
595
596 info->num_written_clipdistance = nir->info.clip_distance_array_size;
597 info->num_written_culldistance = nir->info.cull_distance_array_size;
598 info->clipdist_writemask = u_bit_consecutive(0, info->num_written_clipdistance);
599 info->culldist_writemask = u_bit_consecutive(0, info->num_written_culldistance);
600
601 if (info->processor == PIPE_SHADER_FRAGMENT)
602 info->uses_kill = nir->info.fs.uses_discard;
603
604 /* TODO make this more accurate */
605 info->const_buffers_declared = u_bit_consecutive(0, SI_NUM_CONST_BUFFERS);
606 info->shader_buffers_declared = u_bit_consecutive(0, SI_NUM_SHADER_BUFFERS);
607
608 func = (struct nir_function *)exec_list_get_head_const(&nir->functions);
609 nir_foreach_block(block, func->impl) {
610 nir_foreach_instr(instr, block)
611 scan_instruction(info, instr);
612 }
613 }
614
615 /**
616 * Perform "lowering" operations on the NIR that are run once when the shader
617 * selector is created.
618 */
619 void
620 si_lower_nir(struct si_shader_selector* sel)
621 {
622 /* Adjust the driver location of inputs and outputs. The state tracker
623 * interprets them as slots, while the ac/nir backend interprets them
624 * as individual components.
625 */
626 nir_foreach_variable(variable, &sel->nir->inputs)
627 variable->data.driver_location *= 4;
628
629 nir_foreach_variable(variable, &sel->nir->outputs) {
630 variable->data.driver_location *= 4;
631
632 if (sel->nir->info.stage == MESA_SHADER_FRAGMENT) {
633 if (variable->data.location == FRAG_RESULT_DEPTH)
634 variable->data.driver_location += 2;
635 else if (variable->data.location == FRAG_RESULT_STENCIL)
636 variable->data.driver_location += 1;
637 }
638 }
639
640 /* Perform lowerings (and optimizations) of code.
641 *
642 * Performance considerations aside, we must:
643 * - lower certain ALU operations
644 * - ensure constant offsets for texture instructions are folded
645 * and copy-propagated
646 */
647 NIR_PASS_V(sel->nir, nir_lower_returns);
648 NIR_PASS_V(sel->nir, nir_lower_vars_to_ssa);
649 NIR_PASS_V(sel->nir, nir_lower_alu_to_scalar);
650 NIR_PASS_V(sel->nir, nir_lower_phis_to_scalar);
651
652 static const struct nir_lower_tex_options lower_tex_options = {
653 .lower_txp = ~0u,
654 };
655 NIR_PASS_V(sel->nir, nir_lower_tex, &lower_tex_options);
656
657 const nir_lower_subgroups_options subgroups_options = {
658 .subgroup_size = 64,
659 .ballot_bit_size = 64,
660 .lower_to_scalar = true,
661 .lower_subgroup_masks = true,
662 .lower_vote_trivial = false,
663 .lower_vote_eq_to_ballot = true,
664 };
665 NIR_PASS_V(sel->nir, nir_lower_subgroups, &subgroups_options);
666
667 ac_lower_indirect_derefs(sel->nir, sel->screen->info.chip_class);
668
669 bool progress;
670 do {
671 progress = false;
672
673 /* (Constant) copy propagation is needed for txf with offsets. */
674 NIR_PASS(progress, sel->nir, nir_copy_prop);
675 NIR_PASS(progress, sel->nir, nir_opt_remove_phis);
676 NIR_PASS(progress, sel->nir, nir_opt_dce);
677 if (nir_opt_trivial_continues(sel->nir)) {
678 progress = true;
679 NIR_PASS(progress, sel->nir, nir_copy_prop);
680 NIR_PASS(progress, sel->nir, nir_opt_dce);
681 }
682 NIR_PASS(progress, sel->nir, nir_opt_if);
683 NIR_PASS(progress, sel->nir, nir_opt_dead_cf);
684 NIR_PASS(progress, sel->nir, nir_opt_cse);
685 NIR_PASS(progress, sel->nir, nir_opt_peephole_select, 8);
686
687 /* Needed for algebraic lowering */
688 NIR_PASS(progress, sel->nir, nir_opt_algebraic);
689 NIR_PASS(progress, sel->nir, nir_opt_constant_folding);
690
691 NIR_PASS(progress, sel->nir, nir_opt_undef);
692 NIR_PASS(progress, sel->nir, nir_opt_conditional_discard);
693 if (sel->nir->options->max_unroll_iterations) {
694 NIR_PASS(progress, sel->nir, nir_opt_loop_unroll, 0);
695 }
696 } while (progress);
697 }
698
699 static void declare_nir_input_vs(struct si_shader_context *ctx,
700 struct nir_variable *variable,
701 unsigned input_index,
702 LLVMValueRef out[4])
703 {
704 si_llvm_load_input_vs(ctx, input_index, out);
705 }
706
707 static void declare_nir_input_fs(struct si_shader_context *ctx,
708 struct nir_variable *variable,
709 unsigned input_index,
710 LLVMValueRef out[4])
711 {
712 unsigned slot = variable->data.location;
713 if (slot == VARYING_SLOT_POS) {
714 out[0] = LLVMGetParam(ctx->main_fn, SI_PARAM_POS_X_FLOAT);
715 out[1] = LLVMGetParam(ctx->main_fn, SI_PARAM_POS_Y_FLOAT);
716 out[2] = LLVMGetParam(ctx->main_fn, SI_PARAM_POS_Z_FLOAT);
717 out[3] = ac_build_fdiv(&ctx->ac, ctx->ac.f32_1,
718 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_W_FLOAT));
719 return;
720 }
721
722 si_llvm_load_input_fs(ctx, input_index, out);
723 }
724
725 LLVMValueRef
726 si_nir_lookup_interp_param(struct ac_shader_abi *abi,
727 enum glsl_interp_mode interp, unsigned location)
728 {
729 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
730 int interp_param_idx = -1;
731
732 switch (interp) {
733 case INTERP_MODE_FLAT:
734 return NULL;
735 case INTERP_MODE_SMOOTH:
736 case INTERP_MODE_NONE:
737 if (location == INTERP_CENTER)
738 interp_param_idx = SI_PARAM_PERSP_CENTER;
739 else if (location == INTERP_CENTROID)
740 interp_param_idx = SI_PARAM_PERSP_CENTROID;
741 else if (location == INTERP_SAMPLE)
742 interp_param_idx = SI_PARAM_PERSP_SAMPLE;
743 break;
744 case INTERP_MODE_NOPERSPECTIVE:
745 if (location == INTERP_CENTER)
746 interp_param_idx = SI_PARAM_LINEAR_CENTER;
747 else if (location == INTERP_CENTROID)
748 interp_param_idx = SI_PARAM_LINEAR_CENTROID;
749 else if (location == INTERP_SAMPLE)
750 interp_param_idx = SI_PARAM_LINEAR_SAMPLE;
751 break;
752 default:
753 assert(!"Unhandled interpolation mode.");
754 return NULL;
755 }
756
757 return interp_param_idx != -1 ?
758 LLVMGetParam(ctx->main_fn, interp_param_idx) : NULL;
759 }
760
761 static LLVMValueRef
762 si_nir_load_sampler_desc(struct ac_shader_abi *abi,
763 unsigned descriptor_set, unsigned base_index,
764 unsigned constant_index, LLVMValueRef dynamic_index,
765 enum ac_descriptor_type desc_type, bool image,
766 bool write)
767 {
768 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
769 LLVMBuilderRef builder = ctx->ac.builder;
770 LLVMValueRef list = LLVMGetParam(ctx->main_fn, ctx->param_samplers_and_images);
771 LLVMValueRef index = dynamic_index;
772
773 assert(!descriptor_set);
774
775 if (!index)
776 index = ctx->ac.i32_0;
777
778 index = LLVMBuildAdd(builder, index,
779 LLVMConstInt(ctx->ac.i32, base_index + constant_index, false),
780 "");
781
782 if (image) {
783 assert(desc_type == AC_DESC_IMAGE || desc_type == AC_DESC_BUFFER);
784 assert(base_index + constant_index < ctx->num_images);
785
786 if (dynamic_index)
787 index = si_llvm_bound_index(ctx, index, ctx->num_images);
788
789 index = LLVMBuildSub(ctx->gallivm.builder,
790 LLVMConstInt(ctx->i32, SI_NUM_IMAGES - 1, 0),
791 index, "");
792
793 /* TODO: be smarter about when we use dcc_off */
794 return si_load_image_desc(ctx, list, index, desc_type, write);
795 }
796
797 assert(base_index + constant_index < ctx->num_samplers);
798
799 if (dynamic_index)
800 index = si_llvm_bound_index(ctx, index, ctx->num_samplers);
801
802 index = LLVMBuildAdd(ctx->gallivm.builder, index,
803 LLVMConstInt(ctx->i32, SI_NUM_IMAGES / 2, 0), "");
804
805 return si_load_sampler_desc(ctx, list, index, desc_type);
806 }
807
808 static void bitcast_inputs(struct si_shader_context *ctx,
809 LLVMValueRef data[4],
810 unsigned input_idx)
811 {
812 for (unsigned chan = 0; chan < 4; chan++) {
813 ctx->inputs[input_idx + chan] =
814 LLVMBuildBitCast(ctx->ac.builder, data[chan], ctx->ac.i32, "");
815 }
816 }
817
818 bool si_nir_build_llvm(struct si_shader_context *ctx, struct nir_shader *nir)
819 {
820 struct tgsi_shader_info *info = &ctx->shader->selector->info;
821
822 if (nir->info.stage == MESA_SHADER_VERTEX ||
823 nir->info.stage == MESA_SHADER_FRAGMENT) {
824 uint64_t processed_inputs = 0;
825 nir_foreach_variable(variable, &nir->inputs) {
826 unsigned attrib_count = glsl_count_attribute_slots(variable->type,
827 nir->info.stage == MESA_SHADER_VERTEX);
828 unsigned input_idx = variable->data.driver_location;
829
830 LLVMValueRef data[4];
831 unsigned loc = variable->data.location;
832
833 for (unsigned i = 0; i < attrib_count; i++) {
834 /* Packed components share the same location so skip
835 * them if we have already processed the location.
836 */
837 if (processed_inputs & ((uint64_t)1 << loc)) {
838 input_idx += 4;
839 continue;
840 }
841
842 if (nir->info.stage == MESA_SHADER_VERTEX) {
843 declare_nir_input_vs(ctx, variable, input_idx / 4, data);
844 bitcast_inputs(ctx, data, input_idx);
845 if (glsl_type_is_dual_slot(variable->type)) {
846 input_idx += 4;
847 declare_nir_input_vs(ctx, variable, input_idx / 4, data);
848 bitcast_inputs(ctx, data, input_idx);
849 }
850 } else if (nir->info.stage == MESA_SHADER_FRAGMENT) {
851 declare_nir_input_fs(ctx, variable, input_idx / 4, data);
852 bitcast_inputs(ctx, data, input_idx);
853 }
854
855 processed_inputs |= ((uint64_t)1 << loc);
856 loc++;
857 input_idx += 4;
858 }
859 }
860 }
861
862 ctx->abi.inputs = &ctx->inputs[0];
863 ctx->abi.load_sampler_desc = si_nir_load_sampler_desc;
864 ctx->abi.clamp_shadow_reference = true;
865
866 ctx->num_samplers = util_last_bit(info->samplers_declared);
867 ctx->num_images = util_last_bit(info->images_declared);
868
869 if (ctx->shader->selector->local_size) {
870 assert(nir->info.stage == MESA_SHADER_COMPUTE);
871 si_declare_compute_memory(ctx);
872 }
873 ac_nir_translate(&ctx->ac, &ctx->abi, nir);
874
875 return true;
876 }