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[mesa.git] / src / gallium / drivers / radeonsi / si_shader_nir.c
1 /*
2 * Copyright 2017 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 #include "si_shader_internal.h"
26 #include "si_pipe.h"
27
28 #include "ac_nir_to_llvm.h"
29
30 #include "tgsi/tgsi_from_mesa.h"
31
32 #include "compiler/nir/nir.h"
33 #include "compiler/nir_types.h"
34
35
36 static void scan_instruction(struct tgsi_shader_info *info,
37 nir_instr *instr)
38 {
39 if (instr->type == nir_instr_type_alu) {
40 nir_alu_instr *alu = nir_instr_as_alu(instr);
41
42 switch (alu->op) {
43 case nir_op_fddx:
44 case nir_op_fddy:
45 case nir_op_fddx_fine:
46 case nir_op_fddy_fine:
47 case nir_op_fddx_coarse:
48 case nir_op_fddy_coarse:
49 info->uses_derivatives = true;
50 break;
51 default:
52 break;
53 }
54 } else if (instr->type == nir_instr_type_tex) {
55 nir_tex_instr *tex = nir_instr_as_tex(instr);
56
57 if (!tex->texture) {
58 info->samplers_declared |=
59 u_bit_consecutive(tex->sampler_index, 1);
60 } else {
61 if (tex->texture->var->data.bindless)
62 info->uses_bindless_samplers = true;
63 }
64
65 switch (tex->op) {
66 case nir_texop_tex:
67 case nir_texop_txb:
68 case nir_texop_lod:
69 info->uses_derivatives = true;
70 break;
71 default:
72 break;
73 }
74 } else if (instr->type == nir_instr_type_intrinsic) {
75 nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);
76
77 switch (intr->intrinsic) {
78 case nir_intrinsic_load_front_face:
79 info->uses_frontface = 1;
80 break;
81 case nir_intrinsic_load_instance_id:
82 info->uses_instanceid = 1;
83 break;
84 case nir_intrinsic_load_invocation_id:
85 info->uses_invocationid = true;
86 break;
87 case nir_intrinsic_load_num_work_groups:
88 info->uses_grid_size = true;
89 break;
90 case nir_intrinsic_load_local_group_size:
91 /* The block size is translated to IMM with a fixed block size. */
92 if (info->properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] == 0)
93 info->uses_block_size = true;
94 break;
95 case nir_intrinsic_load_local_invocation_id:
96 case nir_intrinsic_load_work_group_id: {
97 unsigned mask = nir_ssa_def_components_read(&intr->dest.ssa);
98 while (mask) {
99 unsigned i = u_bit_scan(&mask);
100
101 if (intr->intrinsic == nir_intrinsic_load_work_group_id)
102 info->uses_block_id[i] = true;
103 else
104 info->uses_thread_id[i] = true;
105 }
106 break;
107 }
108 case nir_intrinsic_load_vertex_id:
109 info->uses_vertexid = 1;
110 break;
111 case nir_intrinsic_load_vertex_id_zero_base:
112 info->uses_vertexid_nobase = 1;
113 break;
114 case nir_intrinsic_load_base_vertex:
115 info->uses_basevertex = 1;
116 break;
117 case nir_intrinsic_load_primitive_id:
118 info->uses_primid = 1;
119 break;
120 case nir_intrinsic_load_sample_mask_in:
121 info->reads_samplemask = true;
122 break;
123 case nir_intrinsic_load_tess_level_inner:
124 case nir_intrinsic_load_tess_level_outer:
125 info->reads_tess_factors = true;
126 break;
127 case nir_intrinsic_image_var_load:
128 case nir_intrinsic_image_var_size:
129 case nir_intrinsic_image_var_samples: {
130 nir_variable *var = intr->variables[0]->var;
131 if (var->data.bindless)
132 info->uses_bindless_images = true;
133
134 break;
135 }
136 case nir_intrinsic_image_var_store:
137 case nir_intrinsic_image_var_atomic_add:
138 case nir_intrinsic_image_var_atomic_min:
139 case nir_intrinsic_image_var_atomic_max:
140 case nir_intrinsic_image_var_atomic_and:
141 case nir_intrinsic_image_var_atomic_or:
142 case nir_intrinsic_image_var_atomic_xor:
143 case nir_intrinsic_image_var_atomic_exchange:
144 case nir_intrinsic_image_var_atomic_comp_swap: {
145 nir_variable *var = intr->variables[0]->var;
146 if (var->data.bindless)
147 info->uses_bindless_images = true;
148
149 /* fall-through */
150 }
151 case nir_intrinsic_store_ssbo:
152 case nir_intrinsic_ssbo_atomic_add:
153 case nir_intrinsic_ssbo_atomic_imin:
154 case nir_intrinsic_ssbo_atomic_umin:
155 case nir_intrinsic_ssbo_atomic_imax:
156 case nir_intrinsic_ssbo_atomic_umax:
157 case nir_intrinsic_ssbo_atomic_and:
158 case nir_intrinsic_ssbo_atomic_or:
159 case nir_intrinsic_ssbo_atomic_xor:
160 case nir_intrinsic_ssbo_atomic_exchange:
161 case nir_intrinsic_ssbo_atomic_comp_swap:
162 info->writes_memory = true;
163 break;
164 case nir_intrinsic_load_var: {
165 nir_variable *var = intr->variables[0]->var;
166 nir_variable_mode mode = var->data.mode;
167 enum glsl_base_type base_type =
168 glsl_get_base_type(glsl_without_array(var->type));
169
170 if (mode == nir_var_shader_in) {
171 switch (var->data.interpolation) {
172 case INTERP_MODE_NONE:
173 if (glsl_base_type_is_integer(base_type))
174 break;
175
176 /* fall-through */
177 case INTERP_MODE_SMOOTH:
178 if (var->data.sample)
179 info->uses_persp_sample = true;
180 else if (var->data.centroid)
181 info->uses_persp_centroid = true;
182 else
183 info->uses_persp_center = true;
184 break;
185
186 case INTERP_MODE_NOPERSPECTIVE:
187 if (var->data.sample)
188 info->uses_linear_sample = true;
189 else if (var->data.centroid)
190 info->uses_linear_centroid = true;
191 else
192 info->uses_linear_center = true;
193 break;
194 }
195 }
196 break;
197 }
198 case nir_intrinsic_interp_var_at_centroid:
199 case nir_intrinsic_interp_var_at_sample:
200 case nir_intrinsic_interp_var_at_offset: {
201 enum glsl_interp_mode interp =
202 intr->variables[0]->var->data.interpolation;
203 switch (interp) {
204 case INTERP_MODE_SMOOTH:
205 case INTERP_MODE_NONE:
206 if (intr->intrinsic == nir_intrinsic_interp_var_at_centroid)
207 info->uses_persp_opcode_interp_centroid = true;
208 else if (intr->intrinsic == nir_intrinsic_interp_var_at_sample)
209 info->uses_persp_opcode_interp_sample = true;
210 else
211 info->uses_persp_opcode_interp_offset = true;
212 break;
213 case INTERP_MODE_NOPERSPECTIVE:
214 if (intr->intrinsic == nir_intrinsic_interp_var_at_centroid)
215 info->uses_linear_opcode_interp_centroid = true;
216 else if (intr->intrinsic == nir_intrinsic_interp_var_at_sample)
217 info->uses_linear_opcode_interp_sample = true;
218 else
219 info->uses_linear_opcode_interp_offset = true;
220 break;
221 case INTERP_MODE_FLAT:
222 break;
223 default:
224 unreachable("Unsupported interpoation type");
225 }
226 break;
227 }
228 default:
229 break;
230 }
231 }
232 }
233
234 void si_nir_scan_tess_ctrl(const struct nir_shader *nir,
235 const struct tgsi_shader_info *info,
236 struct tgsi_tessctrl_info *out)
237 {
238 memset(out, 0, sizeof(*out));
239
240 if (nir->info.stage != MESA_SHADER_TESS_CTRL)
241 return;
242
243 /* Initial value = true. Here the pass will accumulate results from
244 * multiple segments surrounded by barriers. If tess factors aren't
245 * written at all, it's a shader bug and we don't care if this will be
246 * true.
247 */
248 out->tessfactors_are_def_in_all_invocs = true;
249
250 /* TODO: Implement scanning of tess factors, see tgsi backend. */
251 }
252
253 void si_nir_scan_shader(const struct nir_shader *nir,
254 struct tgsi_shader_info *info)
255 {
256 nir_function *func;
257 unsigned i;
258
259 info->processor = pipe_shader_type_from_mesa(nir->info.stage);
260 info->num_tokens = 2; /* indicate that the shader is non-empty */
261 info->num_instructions = 2;
262
263 info->properties[TGSI_PROPERTY_NEXT_SHADER] =
264 pipe_shader_type_from_mesa(nir->info.next_stage);
265
266 if (nir->info.stage == MESA_SHADER_TESS_CTRL) {
267 info->properties[TGSI_PROPERTY_TCS_VERTICES_OUT] =
268 nir->info.tess.tcs_vertices_out;
269 }
270
271 if (nir->info.stage == MESA_SHADER_TESS_EVAL) {
272 if (nir->info.tess.primitive_mode == GL_ISOLINES)
273 info->properties[TGSI_PROPERTY_TES_PRIM_MODE] = PIPE_PRIM_LINES;
274 else
275 info->properties[TGSI_PROPERTY_TES_PRIM_MODE] = nir->info.tess.primitive_mode;
276
277 STATIC_ASSERT((TESS_SPACING_EQUAL + 1) % 3 == PIPE_TESS_SPACING_EQUAL);
278 STATIC_ASSERT((TESS_SPACING_FRACTIONAL_ODD + 1) % 3 ==
279 PIPE_TESS_SPACING_FRACTIONAL_ODD);
280 STATIC_ASSERT((TESS_SPACING_FRACTIONAL_EVEN + 1) % 3 ==
281 PIPE_TESS_SPACING_FRACTIONAL_EVEN);
282
283 info->properties[TGSI_PROPERTY_TES_SPACING] = (nir->info.tess.spacing + 1) % 3;
284 info->properties[TGSI_PROPERTY_TES_VERTEX_ORDER_CW] = !nir->info.tess.ccw;
285 info->properties[TGSI_PROPERTY_TES_POINT_MODE] = nir->info.tess.point_mode;
286 }
287
288 if (nir->info.stage == MESA_SHADER_GEOMETRY) {
289 info->properties[TGSI_PROPERTY_GS_INPUT_PRIM] = nir->info.gs.input_primitive;
290 info->properties[TGSI_PROPERTY_GS_OUTPUT_PRIM] = nir->info.gs.output_primitive;
291 info->properties[TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES] = nir->info.gs.vertices_out;
292 info->properties[TGSI_PROPERTY_GS_INVOCATIONS] = nir->info.gs.invocations;
293 }
294
295 if (nir->info.stage == MESA_SHADER_FRAGMENT) {
296 info->properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL] =
297 nir->info.fs.early_fragment_tests | nir->info.fs.post_depth_coverage;
298 info->properties[TGSI_PROPERTY_FS_POST_DEPTH_COVERAGE] = nir->info.fs.post_depth_coverage;
299
300 if (nir->info.fs.pixel_center_integer) {
301 info->properties[TGSI_PROPERTY_FS_COORD_PIXEL_CENTER] =
302 TGSI_FS_COORD_PIXEL_CENTER_INTEGER;
303 }
304
305 if (nir->info.fs.depth_layout != FRAG_DEPTH_LAYOUT_NONE) {
306 switch (nir->info.fs.depth_layout) {
307 case FRAG_DEPTH_LAYOUT_ANY:
308 info->properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT] = TGSI_FS_DEPTH_LAYOUT_ANY;
309 break;
310 case FRAG_DEPTH_LAYOUT_GREATER:
311 info->properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT] = TGSI_FS_DEPTH_LAYOUT_GREATER;
312 break;
313 case FRAG_DEPTH_LAYOUT_LESS:
314 info->properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT] = TGSI_FS_DEPTH_LAYOUT_LESS;
315 break;
316 case FRAG_DEPTH_LAYOUT_UNCHANGED:
317 info->properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT] = TGSI_FS_DEPTH_LAYOUT_UNCHANGED;
318 break;
319 default:
320 unreachable("Unknow depth layout");
321 }
322 }
323 }
324
325 if (nir->info.stage == MESA_SHADER_COMPUTE) {
326 info->properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] = nir->info.cs.local_size[0];
327 info->properties[TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT] = nir->info.cs.local_size[1];
328 info->properties[TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH] = nir->info.cs.local_size[2];
329 }
330
331 i = 0;
332 uint64_t processed_inputs = 0;
333 unsigned num_inputs = 0;
334 nir_foreach_variable(variable, &nir->inputs) {
335 unsigned semantic_name, semantic_index;
336
337 const struct glsl_type *type = variable->type;
338 if (nir_is_per_vertex_io(variable, nir->info.stage)) {
339 assert(glsl_type_is_array(type));
340 type = glsl_get_array_element(type);
341 }
342
343 unsigned attrib_count = glsl_count_attribute_slots(type,
344 nir->info.stage == MESA_SHADER_VERTEX);
345
346 i = variable->data.driver_location;
347
348 /* Vertex shader inputs don't have semantics. The state
349 * tracker has already mapped them to attributes via
350 * variable->data.driver_location.
351 */
352 if (nir->info.stage == MESA_SHADER_VERTEX) {
353 /* TODO: gather the actual input useage and remove this. */
354 info->input_usage_mask[i] = TGSI_WRITEMASK_XYZW;
355
356 if (glsl_type_is_dual_slot(variable->type)) {
357 num_inputs += 2;
358
359 /* TODO: gather the actual input useage and remove this. */
360 info->input_usage_mask[i+1] = TGSI_WRITEMASK_XYZW;
361 } else
362 num_inputs++;
363 continue;
364 }
365
366 /* Fragment shader position is a system value. */
367 if (nir->info.stage == MESA_SHADER_FRAGMENT &&
368 variable->data.location == VARYING_SLOT_POS) {
369 if (variable->data.pixel_center_integer)
370 info->properties[TGSI_PROPERTY_FS_COORD_PIXEL_CENTER] =
371 TGSI_FS_COORD_PIXEL_CENTER_INTEGER;
372
373 num_inputs++;
374 continue;
375 }
376
377 for (unsigned j = 0; j < attrib_count; j++, i++) {
378
379 if (processed_inputs & ((uint64_t)1 << i))
380 continue;
381
382 processed_inputs |= ((uint64_t)1 << i);
383 num_inputs++;
384
385 tgsi_get_gl_varying_semantic(variable->data.location + j, true,
386 &semantic_name, &semantic_index);
387
388 info->input_semantic_name[i] = semantic_name;
389 info->input_semantic_index[i] = semantic_index;
390
391 if (semantic_name == TGSI_SEMANTIC_PRIMID)
392 info->uses_primid = true;
393
394 if (variable->data.sample)
395 info->input_interpolate_loc[i] = TGSI_INTERPOLATE_LOC_SAMPLE;
396 else if (variable->data.centroid)
397 info->input_interpolate_loc[i] = TGSI_INTERPOLATE_LOC_CENTROID;
398 else
399 info->input_interpolate_loc[i] = TGSI_INTERPOLATE_LOC_CENTER;
400
401 enum glsl_base_type base_type =
402 glsl_get_base_type(glsl_without_array(variable->type));
403
404 switch (variable->data.interpolation) {
405 case INTERP_MODE_NONE:
406 if (glsl_base_type_is_integer(base_type)) {
407 info->input_interpolate[i] = TGSI_INTERPOLATE_CONSTANT;
408 break;
409 }
410
411 if (semantic_name == TGSI_SEMANTIC_COLOR) {
412 info->input_interpolate[i] = TGSI_INTERPOLATE_COLOR;
413 break;
414 }
415 /* fall-through */
416
417 case INTERP_MODE_SMOOTH:
418 assert(!glsl_base_type_is_integer(base_type));
419
420 info->input_interpolate[i] = TGSI_INTERPOLATE_PERSPECTIVE;
421 break;
422
423 case INTERP_MODE_NOPERSPECTIVE:
424 assert(!glsl_base_type_is_integer(base_type));
425
426 info->input_interpolate[i] = TGSI_INTERPOLATE_LINEAR;
427 break;
428
429 case INTERP_MODE_FLAT:
430 info->input_interpolate[i] = TGSI_INTERPOLATE_CONSTANT;
431 break;
432 }
433
434 /* TODO make this more precise */
435 if (variable->data.location == VARYING_SLOT_COL0)
436 info->colors_read |= 0x0f;
437 else if (variable->data.location == VARYING_SLOT_COL1)
438 info->colors_read |= 0xf0;
439 }
440 }
441
442 info->num_inputs = num_inputs;
443
444
445 i = 0;
446 uint64_t processed_outputs = 0;
447 unsigned num_outputs = 0;
448 nir_foreach_variable(variable, &nir->outputs) {
449 unsigned semantic_name, semantic_index;
450
451 i = variable->data.driver_location;
452
453 const struct glsl_type *type = variable->type;
454 if (nir_is_per_vertex_io(variable, nir->info.stage)) {
455 assert(glsl_type_is_array(type));
456 type = glsl_get_array_element(type);
457 }
458
459 unsigned attrib_count = glsl_count_attribute_slots(type, false);
460 for (unsigned k = 0; k < attrib_count; k++, i++) {
461
462 if (nir->info.stage == MESA_SHADER_FRAGMENT) {
463 tgsi_get_gl_frag_result_semantic(variable->data.location + k,
464 &semantic_name, &semantic_index);
465
466 /* Adjust for dual source blending */
467 if (variable->data.index > 0) {
468 semantic_index++;
469 }
470 } else {
471 tgsi_get_gl_varying_semantic(variable->data.location + k, true,
472 &semantic_name, &semantic_index);
473 }
474
475 unsigned num_components = 4;
476 unsigned vector_elements = glsl_get_vector_elements(glsl_without_array(variable->type));
477 if (vector_elements)
478 num_components = vector_elements;
479
480 unsigned component = variable->data.location_frac;
481 if (glsl_type_is_64bit(glsl_without_array(variable->type))) {
482 if (glsl_type_is_dual_slot(glsl_without_array(variable->type)) && k % 2) {
483 num_components = (num_components * 2) - 4;
484 component = 0;
485 } else {
486 num_components = MIN2(num_components * 2, 4);
487 }
488 }
489
490 ubyte usagemask = 0;
491 for (unsigned j = component; j < num_components + component; j++) {
492 switch (j) {
493 case 0:
494 usagemask |= TGSI_WRITEMASK_X;
495 break;
496 case 1:
497 usagemask |= TGSI_WRITEMASK_Y;
498 break;
499 case 2:
500 usagemask |= TGSI_WRITEMASK_Z;
501 break;
502 case 3:
503 usagemask |= TGSI_WRITEMASK_W;
504 break;
505 default:
506 unreachable("error calculating component index");
507 }
508 }
509
510 unsigned gs_out_streams;
511 if (variable->data.stream & (1u << 31)) {
512 gs_out_streams = variable->data.stream & ~(1u << 31);
513 } else {
514 assert(variable->data.stream < 4);
515 gs_out_streams = 0;
516 for (unsigned j = 0; j < num_components; ++j)
517 gs_out_streams |= variable->data.stream << (2 * (component + j));
518 }
519
520 unsigned streamx = gs_out_streams & 3;
521 unsigned streamy = (gs_out_streams >> 2) & 3;
522 unsigned streamz = (gs_out_streams >> 4) & 3;
523 unsigned streamw = (gs_out_streams >> 6) & 3;
524
525 if (usagemask & TGSI_WRITEMASK_X) {
526 info->output_usagemask[i] |= TGSI_WRITEMASK_X;
527 info->output_streams[i] |= streamx;
528 info->num_stream_output_components[streamx]++;
529 }
530 if (usagemask & TGSI_WRITEMASK_Y) {
531 info->output_usagemask[i] |= TGSI_WRITEMASK_Y;
532 info->output_streams[i] |= streamy << 2;
533 info->num_stream_output_components[streamy]++;
534 }
535 if (usagemask & TGSI_WRITEMASK_Z) {
536 info->output_usagemask[i] |= TGSI_WRITEMASK_Z;
537 info->output_streams[i] |= streamz << 4;
538 info->num_stream_output_components[streamz]++;
539 }
540 if (usagemask & TGSI_WRITEMASK_W) {
541 info->output_usagemask[i] |= TGSI_WRITEMASK_W;
542 info->output_streams[i] |= streamw << 6;
543 info->num_stream_output_components[streamw]++;
544 }
545
546 /* make sure we only count this location once against
547 * the num_outputs counter.
548 */
549 if (processed_outputs & ((uint64_t)1 << i))
550 continue;
551
552 processed_outputs |= ((uint64_t)1 << i);
553 num_outputs++;
554
555 info->output_semantic_name[i] = semantic_name;
556 info->output_semantic_index[i] = semantic_index;
557
558 switch (semantic_name) {
559 case TGSI_SEMANTIC_PRIMID:
560 info->writes_primid = true;
561 break;
562 case TGSI_SEMANTIC_VIEWPORT_INDEX:
563 info->writes_viewport_index = true;
564 break;
565 case TGSI_SEMANTIC_LAYER:
566 info->writes_layer = true;
567 break;
568 case TGSI_SEMANTIC_PSIZE:
569 info->writes_psize = true;
570 break;
571 case TGSI_SEMANTIC_CLIPVERTEX:
572 info->writes_clipvertex = true;
573 break;
574 case TGSI_SEMANTIC_COLOR:
575 info->colors_written |= 1 << semantic_index;
576 break;
577 case TGSI_SEMANTIC_STENCIL:
578 info->writes_stencil = true;
579 break;
580 case TGSI_SEMANTIC_SAMPLEMASK:
581 info->writes_samplemask = true;
582 break;
583 case TGSI_SEMANTIC_EDGEFLAG:
584 info->writes_edgeflag = true;
585 break;
586 case TGSI_SEMANTIC_POSITION:
587 if (info->processor == PIPE_SHADER_FRAGMENT)
588 info->writes_z = true;
589 else
590 info->writes_position = true;
591 break;
592 }
593
594 if (nir->info.stage == MESA_SHADER_TESS_CTRL) {
595 switch (semantic_name) {
596 case TGSI_SEMANTIC_PATCH:
597 info->reads_perpatch_outputs = true;
598 break;
599 case TGSI_SEMANTIC_TESSINNER:
600 case TGSI_SEMANTIC_TESSOUTER:
601 info->reads_tessfactor_outputs = true;
602 break;
603 default:
604 info->reads_pervertex_outputs = true;
605 }
606 }
607 }
608
609 unsigned loc = variable->data.location;
610 if (nir->info.stage == MESA_SHADER_FRAGMENT &&
611 loc == FRAG_RESULT_COLOR &&
612 nir->info.outputs_written & (1ull << loc)) {
613 assert(attrib_count == 1);
614 info->properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS] = true;
615 }
616 }
617
618 info->num_outputs = num_outputs;
619
620 struct set *ubo_set = _mesa_set_create(NULL, _mesa_hash_pointer,
621 _mesa_key_pointer_equal);
622
623 /* Intialise const_file_max[0] */
624 info->const_file_max[0] = -1;
625
626 unsigned ubo_idx = 1;
627 nir_foreach_variable(variable, &nir->uniforms) {
628 const struct glsl_type *type = variable->type;
629 enum glsl_base_type base_type =
630 glsl_get_base_type(glsl_without_array(type));
631 unsigned aoa_size = MAX2(1, glsl_get_aoa_size(type));
632
633 /* Gather buffers declared bitmasks. Note: radeonsi doesn't
634 * really use the mask (other than ubo_idx == 1 for regular
635 * uniforms) its really only used for getting the buffer count
636 * so we don't need to worry about the ordering.
637 */
638 if (variable->interface_type != NULL) {
639 if (variable->data.mode == nir_var_uniform) {
640
641 unsigned block_count;
642 if (base_type != GLSL_TYPE_INTERFACE) {
643 struct set_entry *entry =
644 _mesa_set_search(ubo_set, variable->interface_type);
645
646 /* Check if we have already processed
647 * a member from this ubo.
648 */
649 if (entry)
650 continue;
651
652 block_count = 1;
653 } else {
654 block_count = aoa_size;
655 }
656
657 info->const_buffers_declared |= u_bit_consecutive(ubo_idx, block_count);
658 ubo_idx += block_count;
659
660 _mesa_set_add(ubo_set, variable->interface_type);
661 }
662
663 if (variable->data.mode == nir_var_shader_storage) {
664 /* TODO: make this more accurate */
665 info->shader_buffers_declared =
666 u_bit_consecutive(0, SI_NUM_SHADER_BUFFERS);
667 }
668
669 continue;
670 }
671
672 /* We rely on the fact that nir_lower_samplers_as_deref has
673 * eliminated struct dereferences.
674 */
675 if (base_type == GLSL_TYPE_SAMPLER) {
676 if (variable->data.bindless) {
677 info->const_buffers_declared |= 1;
678 info->const_file_max[0] +=
679 glsl_count_attribute_slots(type, false);
680 } else {
681 info->samplers_declared |=
682 u_bit_consecutive(variable->data.binding, aoa_size);
683 }
684 } else if (base_type == GLSL_TYPE_IMAGE) {
685 if (variable->data.bindless) {
686 info->const_buffers_declared |= 1;
687 info->const_file_max[0] +=
688 glsl_count_attribute_slots(type, false);
689 } else {
690 info->images_declared |=
691 u_bit_consecutive(variable->data.binding, aoa_size);
692 }
693 } else if (base_type != GLSL_TYPE_ATOMIC_UINT) {
694 if (strncmp(variable->name, "state.", 6) == 0 ||
695 strncmp(variable->name, "gl_", 3) == 0) {
696 /* FIXME: figure out why piglit tests with builtin
697 * uniforms are failing without this.
698 */
699 info->const_buffers_declared =
700 u_bit_consecutive(0, SI_NUM_CONST_BUFFERS);
701 } else {
702 info->const_buffers_declared |= 1;
703 info->const_file_max[0] +=
704 glsl_count_attribute_slots(type, false);
705 }
706 }
707 }
708
709 _mesa_set_destroy(ubo_set, NULL);
710
711 info->num_written_clipdistance = nir->info.clip_distance_array_size;
712 info->num_written_culldistance = nir->info.cull_distance_array_size;
713 info->clipdist_writemask = u_bit_consecutive(0, info->num_written_clipdistance);
714 info->culldist_writemask = u_bit_consecutive(0, info->num_written_culldistance);
715
716 if (info->processor == PIPE_SHADER_FRAGMENT)
717 info->uses_kill = nir->info.fs.uses_discard;
718
719 func = (struct nir_function *)exec_list_get_head_const(&nir->functions);
720 nir_foreach_block(block, func->impl) {
721 nir_foreach_instr(instr, block)
722 scan_instruction(info, instr);
723 }
724 }
725
726 /**
727 * Perform "lowering" operations on the NIR that are run once when the shader
728 * selector is created.
729 */
730 void
731 si_lower_nir(struct si_shader_selector* sel)
732 {
733 /* Disable const buffer fast path for old LLVM versions */
734 if (sel->screen->info.chip_class == SI && HAVE_LLVM < 0x0600 &&
735 sel->info.const_buffers_declared == 1 &&
736 sel->info.shader_buffers_declared == 0) {
737 sel->info.const_buffers_declared |= 0x2;
738 }
739
740 /* Adjust the driver location of inputs and outputs. The state tracker
741 * interprets them as slots, while the ac/nir backend interprets them
742 * as individual components.
743 */
744 nir_foreach_variable(variable, &sel->nir->inputs)
745 variable->data.driver_location *= 4;
746
747 nir_foreach_variable(variable, &sel->nir->outputs) {
748 variable->data.driver_location *= 4;
749
750 if (sel->nir->info.stage == MESA_SHADER_FRAGMENT) {
751 if (variable->data.location == FRAG_RESULT_DEPTH)
752 variable->data.driver_location += 2;
753 else if (variable->data.location == FRAG_RESULT_STENCIL)
754 variable->data.driver_location += 1;
755 }
756 }
757
758 /* Perform lowerings (and optimizations) of code.
759 *
760 * Performance considerations aside, we must:
761 * - lower certain ALU operations
762 * - ensure constant offsets for texture instructions are folded
763 * and copy-propagated
764 */
765 NIR_PASS_V(sel->nir, nir_lower_returns);
766 NIR_PASS_V(sel->nir, nir_lower_vars_to_ssa);
767 NIR_PASS_V(sel->nir, nir_lower_alu_to_scalar);
768 NIR_PASS_V(sel->nir, nir_lower_phis_to_scalar);
769
770 static const struct nir_lower_tex_options lower_tex_options = {
771 .lower_txp = ~0u,
772 };
773 NIR_PASS_V(sel->nir, nir_lower_tex, &lower_tex_options);
774
775 const nir_lower_subgroups_options subgroups_options = {
776 .subgroup_size = 64,
777 .ballot_bit_size = 64,
778 .lower_to_scalar = true,
779 .lower_subgroup_masks = true,
780 .lower_vote_trivial = false,
781 .lower_vote_eq_to_ballot = true,
782 };
783 NIR_PASS_V(sel->nir, nir_lower_subgroups, &subgroups_options);
784
785 ac_lower_indirect_derefs(sel->nir, sel->screen->info.chip_class);
786
787 bool progress;
788 do {
789 progress = false;
790
791 /* (Constant) copy propagation is needed for txf with offsets. */
792 NIR_PASS(progress, sel->nir, nir_copy_prop);
793 NIR_PASS(progress, sel->nir, nir_opt_remove_phis);
794 NIR_PASS(progress, sel->nir, nir_opt_dce);
795 if (nir_opt_trivial_continues(sel->nir)) {
796 progress = true;
797 NIR_PASS(progress, sel->nir, nir_copy_prop);
798 NIR_PASS(progress, sel->nir, nir_opt_dce);
799 }
800 NIR_PASS(progress, sel->nir, nir_opt_if);
801 NIR_PASS(progress, sel->nir, nir_opt_dead_cf);
802 NIR_PASS(progress, sel->nir, nir_opt_cse);
803 NIR_PASS(progress, sel->nir, nir_opt_peephole_select, 8);
804
805 /* Needed for algebraic lowering */
806 NIR_PASS(progress, sel->nir, nir_opt_algebraic);
807 NIR_PASS(progress, sel->nir, nir_opt_constant_folding);
808
809 NIR_PASS(progress, sel->nir, nir_opt_undef);
810 NIR_PASS(progress, sel->nir, nir_opt_conditional_discard);
811 if (sel->nir->options->max_unroll_iterations) {
812 NIR_PASS(progress, sel->nir, nir_opt_loop_unroll, 0);
813 }
814 } while (progress);
815 }
816
817 static void declare_nir_input_vs(struct si_shader_context *ctx,
818 struct nir_variable *variable,
819 unsigned input_index,
820 LLVMValueRef out[4])
821 {
822 si_llvm_load_input_vs(ctx, input_index, out);
823 }
824
825 static void declare_nir_input_fs(struct si_shader_context *ctx,
826 struct nir_variable *variable,
827 unsigned input_index,
828 LLVMValueRef out[4])
829 {
830 unsigned slot = variable->data.location;
831 if (slot == VARYING_SLOT_POS) {
832 out[0] = LLVMGetParam(ctx->main_fn, SI_PARAM_POS_X_FLOAT);
833 out[1] = LLVMGetParam(ctx->main_fn, SI_PARAM_POS_Y_FLOAT);
834 out[2] = LLVMGetParam(ctx->main_fn, SI_PARAM_POS_Z_FLOAT);
835 out[3] = ac_build_fdiv(&ctx->ac, ctx->ac.f32_1,
836 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_W_FLOAT));
837 return;
838 }
839
840 si_llvm_load_input_fs(ctx, input_index, out);
841 }
842
843 LLVMValueRef
844 si_nir_lookup_interp_param(struct ac_shader_abi *abi,
845 enum glsl_interp_mode interp, unsigned location)
846 {
847 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
848 int interp_param_idx = -1;
849
850 switch (interp) {
851 case INTERP_MODE_FLAT:
852 return NULL;
853 case INTERP_MODE_SMOOTH:
854 case INTERP_MODE_NONE:
855 if (location == INTERP_CENTER)
856 interp_param_idx = SI_PARAM_PERSP_CENTER;
857 else if (location == INTERP_CENTROID)
858 interp_param_idx = SI_PARAM_PERSP_CENTROID;
859 else if (location == INTERP_SAMPLE)
860 interp_param_idx = SI_PARAM_PERSP_SAMPLE;
861 break;
862 case INTERP_MODE_NOPERSPECTIVE:
863 if (location == INTERP_CENTER)
864 interp_param_idx = SI_PARAM_LINEAR_CENTER;
865 else if (location == INTERP_CENTROID)
866 interp_param_idx = SI_PARAM_LINEAR_CENTROID;
867 else if (location == INTERP_SAMPLE)
868 interp_param_idx = SI_PARAM_LINEAR_SAMPLE;
869 break;
870 default:
871 assert(!"Unhandled interpolation mode.");
872 return NULL;
873 }
874
875 return interp_param_idx != -1 ?
876 LLVMGetParam(ctx->main_fn, interp_param_idx) : NULL;
877 }
878
879 static LLVMValueRef
880 si_nir_load_sampler_desc(struct ac_shader_abi *abi,
881 unsigned descriptor_set, unsigned base_index,
882 unsigned constant_index, LLVMValueRef dynamic_index,
883 enum ac_descriptor_type desc_type, bool image,
884 bool write, bool bindless)
885 {
886 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
887 LLVMBuilderRef builder = ctx->ac.builder;
888 LLVMValueRef list = LLVMGetParam(ctx->main_fn, ctx->param_samplers_and_images);
889 LLVMValueRef index;
890
891 assert(!descriptor_set);
892
893 dynamic_index = dynamic_index ? dynamic_index : ctx->ac.i32_0;
894 index = LLVMBuildAdd(builder, dynamic_index,
895 LLVMConstInt(ctx->ac.i32, base_index + constant_index, false),
896 "");
897
898 if (image) {
899 assert(desc_type == AC_DESC_IMAGE || desc_type == AC_DESC_BUFFER);
900 assert(base_index + constant_index < ctx->num_images);
901
902 if (dynamic_index)
903 index = si_llvm_bound_index(ctx, index, ctx->num_images);
904
905 index = LLVMBuildSub(ctx->gallivm.builder,
906 LLVMConstInt(ctx->i32, SI_NUM_IMAGES - 1, 0),
907 index, "");
908
909 /* TODO: be smarter about when we use dcc_off */
910 return si_load_image_desc(ctx, list, index, desc_type, write);
911 }
912
913 assert(base_index + constant_index < ctx->num_samplers);
914
915 if (dynamic_index)
916 index = si_llvm_bound_index(ctx, index, ctx->num_samplers);
917
918 index = LLVMBuildAdd(ctx->gallivm.builder, index,
919 LLVMConstInt(ctx->i32, SI_NUM_IMAGES / 2, 0), "");
920
921 return si_load_sampler_desc(ctx, list, index, desc_type);
922 }
923
924 static void bitcast_inputs(struct si_shader_context *ctx,
925 LLVMValueRef data[4],
926 unsigned input_idx)
927 {
928 for (unsigned chan = 0; chan < 4; chan++) {
929 ctx->inputs[input_idx + chan] =
930 LLVMBuildBitCast(ctx->ac.builder, data[chan], ctx->ac.i32, "");
931 }
932 }
933
934 bool si_nir_build_llvm(struct si_shader_context *ctx, struct nir_shader *nir)
935 {
936 struct tgsi_shader_info *info = &ctx->shader->selector->info;
937
938 if (nir->info.stage == MESA_SHADER_VERTEX ||
939 nir->info.stage == MESA_SHADER_FRAGMENT) {
940 uint64_t processed_inputs = 0;
941 nir_foreach_variable(variable, &nir->inputs) {
942 unsigned attrib_count = glsl_count_attribute_slots(variable->type,
943 nir->info.stage == MESA_SHADER_VERTEX);
944 unsigned input_idx = variable->data.driver_location;
945
946 LLVMValueRef data[4];
947 unsigned loc = variable->data.location;
948
949 for (unsigned i = 0; i < attrib_count; i++) {
950 /* Packed components share the same location so skip
951 * them if we have already processed the location.
952 */
953 if (processed_inputs & ((uint64_t)1 << (loc + i))) {
954 input_idx += 4;
955 continue;
956 }
957
958 if (nir->info.stage == MESA_SHADER_VERTEX) {
959 declare_nir_input_vs(ctx, variable, input_idx / 4, data);
960 bitcast_inputs(ctx, data, input_idx);
961 if (glsl_type_is_dual_slot(variable->type)) {
962 input_idx += 4;
963 declare_nir_input_vs(ctx, variable, input_idx / 4, data);
964 bitcast_inputs(ctx, data, input_idx);
965 }
966 } else if (nir->info.stage == MESA_SHADER_FRAGMENT) {
967 declare_nir_input_fs(ctx, variable, input_idx / 4, data);
968 bitcast_inputs(ctx, data, input_idx);
969 }
970
971 processed_inputs |= ((uint64_t)1 << (loc + i));
972 input_idx += 4;
973 }
974 }
975 }
976
977 ctx->abi.inputs = &ctx->inputs[0];
978 ctx->abi.load_sampler_desc = si_nir_load_sampler_desc;
979 ctx->abi.clamp_shadow_reference = true;
980
981 ctx->num_samplers = util_last_bit(info->samplers_declared);
982 ctx->num_images = util_last_bit(info->images_declared);
983
984 if (ctx->shader->selector->local_size) {
985 assert(nir->info.stage == MESA_SHADER_COMPUTE);
986 si_declare_compute_memory(ctx);
987 }
988 ac_nir_translate(&ctx->ac, &ctx->abi, nir);
989
990 return true;
991 }