2 * Copyright 2017 Advanced Micro Devices, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
25 #include "si_shader_internal.h"
28 #include "ac_nir_to_llvm.h"
30 #include "tgsi/tgsi_from_mesa.h"
32 #include "compiler/nir/nir.h"
33 #include "compiler/nir_types.h"
34 #include "compiler/nir/nir_builder.h"
36 static nir_variable
* tex_get_texture_var(nir_tex_instr
*instr
)
38 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
39 switch (instr
->src
[i
].src_type
) {
40 case nir_tex_src_texture_deref
:
41 return nir_deref_instr_get_variable(nir_src_as_deref(instr
->src
[i
].src
));
50 static nir_variable
* intrinsic_get_var(nir_intrinsic_instr
*instr
)
52 return nir_deref_instr_get_variable(nir_src_as_deref(instr
->src
[0]));
55 static void gather_intrinsic_load_deref_input_info(const nir_shader
*nir
,
56 const nir_intrinsic_instr
*instr
,
58 struct tgsi_shader_info
*info
)
60 assert(var
&& var
->data
.mode
== nir_var_shader_in
);
62 switch (nir
->info
.stage
) {
63 case MESA_SHADER_VERTEX
: {
64 unsigned i
= var
->data
.driver_location
;
65 unsigned attrib_count
= glsl_count_attribute_slots(var
->type
, false);
66 uint8_t mask
= nir_ssa_def_components_read(&instr
->dest
.ssa
);
68 for (unsigned j
= 0; j
< attrib_count
; j
++, i
++) {
69 if (glsl_type_is_64bit(glsl_without_array(var
->type
))) {
70 unsigned dmask
= mask
;
72 if (glsl_type_is_dual_slot(glsl_without_array(var
->type
)) && j
% 2)
75 dmask
<<= var
->data
.location_frac
/ 2;
78 info
->input_usage_mask
[i
] |= TGSI_WRITEMASK_XY
;
80 info
->input_usage_mask
[i
] |= TGSI_WRITEMASK_ZW
;
82 info
->input_usage_mask
[i
] |=
83 (mask
<< var
->data
.location_frac
) & 0xf;
92 static void gather_intrinsic_load_deref_output_info(const nir_shader
*nir
,
93 const nir_intrinsic_instr
*instr
,
95 struct tgsi_shader_info
*info
)
97 assert(var
&& var
->data
.mode
== nir_var_shader_out
);
99 switch (nir
->info
.stage
) {
100 case MESA_SHADER_TESS_CTRL
:
101 if (var
->data
.location
== VARYING_SLOT_TESS_LEVEL_INNER
||
102 var
->data
.location
== VARYING_SLOT_TESS_LEVEL_OUTER
)
103 info
->reads_tessfactor_outputs
= true;
104 else if (var
->data
.patch
)
105 info
->reads_perpatch_outputs
= true;
107 info
->reads_pervertex_outputs
= true;
110 case MESA_SHADER_FRAGMENT
:
111 if (var
->data
.fb_fetch_output
)
112 info
->uses_fbfetch
= true;
118 static void gather_intrinsic_store_deref_output_info(const nir_shader
*nir
,
119 const nir_intrinsic_instr
*instr
,
121 struct tgsi_shader_info
*info
)
123 assert(var
&& var
->data
.mode
== nir_var_shader_out
);
125 switch (nir
->info
.stage
) {
126 case MESA_SHADER_VERTEX
: /* needed by LS, ES */
127 case MESA_SHADER_TESS_EVAL
: /* needed by ES */
128 case MESA_SHADER_GEOMETRY
: {
129 unsigned i
= var
->data
.driver_location
;
130 unsigned attrib_count
= glsl_count_attribute_slots(var
->type
, false);
131 unsigned mask
= nir_intrinsic_write_mask(instr
);
133 assert(!var
->data
.compact
);
135 for (unsigned j
= 0; j
< attrib_count
; j
++, i
++) {
136 if (glsl_type_is_64bit(glsl_without_array(var
->type
))) {
137 unsigned dmask
= mask
;
139 if (glsl_type_is_dual_slot(glsl_without_array(var
->type
)) && j
% 2)
142 dmask
<<= var
->data
.location_frac
/ 2;
145 info
->output_usagemask
[i
] |= TGSI_WRITEMASK_XY
;
147 info
->output_usagemask
[i
] |= TGSI_WRITEMASK_ZW
;
149 info
->output_usagemask
[i
] |=
150 (mask
<< var
->data
.location_frac
) & 0xf;
160 static void scan_instruction(const struct nir_shader
*nir
,
161 struct tgsi_shader_info
*info
,
164 if (instr
->type
== nir_instr_type_alu
) {
165 nir_alu_instr
*alu
= nir_instr_as_alu(instr
);
170 case nir_op_fddx_fine
:
171 case nir_op_fddy_fine
:
172 case nir_op_fddx_coarse
:
173 case nir_op_fddy_coarse
:
174 info
->uses_derivatives
= true;
179 } else if (instr
->type
== nir_instr_type_tex
) {
180 nir_tex_instr
*tex
= nir_instr_as_tex(instr
);
181 nir_variable
*texture
= tex_get_texture_var(tex
);
184 info
->samplers_declared
|=
185 u_bit_consecutive(tex
->sampler_index
, 1);
187 if (texture
->data
.bindless
)
188 info
->uses_bindless_samplers
= true;
195 info
->uses_derivatives
= true;
200 } else if (instr
->type
== nir_instr_type_intrinsic
) {
201 nir_intrinsic_instr
*intr
= nir_instr_as_intrinsic(instr
);
203 switch (intr
->intrinsic
) {
204 case nir_intrinsic_load_front_face
:
205 info
->uses_frontface
= 1;
207 case nir_intrinsic_load_instance_id
:
208 info
->uses_instanceid
= 1;
210 case nir_intrinsic_load_invocation_id
:
211 info
->uses_invocationid
= true;
213 case nir_intrinsic_load_num_work_groups
:
214 info
->uses_grid_size
= true;
216 case nir_intrinsic_load_local_group_size
:
217 /* The block size is translated to IMM with a fixed block size. */
218 if (info
->properties
[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH
] == 0)
219 info
->uses_block_size
= true;
221 case nir_intrinsic_load_local_invocation_id
:
222 case nir_intrinsic_load_work_group_id
: {
223 unsigned mask
= nir_ssa_def_components_read(&intr
->dest
.ssa
);
225 unsigned i
= u_bit_scan(&mask
);
227 if (intr
->intrinsic
== nir_intrinsic_load_work_group_id
)
228 info
->uses_block_id
[i
] = true;
230 info
->uses_thread_id
[i
] = true;
234 case nir_intrinsic_load_vertex_id
:
235 info
->uses_vertexid
= 1;
237 case nir_intrinsic_load_vertex_id_zero_base
:
238 info
->uses_vertexid_nobase
= 1;
240 case nir_intrinsic_load_base_vertex
:
241 info
->uses_basevertex
= 1;
243 case nir_intrinsic_load_draw_id
:
244 info
->uses_drawid
= 1;
246 case nir_intrinsic_load_primitive_id
:
247 info
->uses_primid
= 1;
249 case nir_intrinsic_load_sample_mask_in
:
250 info
->reads_samplemask
= true;
252 case nir_intrinsic_load_tess_level_inner
:
253 case nir_intrinsic_load_tess_level_outer
:
254 info
->reads_tess_factors
= true;
256 case nir_intrinsic_bindless_image_load
:
257 info
->uses_bindless_images
= true;
259 if (nir_intrinsic_image_dim(intr
) == GLSL_SAMPLER_DIM_BUF
)
260 info
->uses_bindless_buffer_load
= true;
262 info
->uses_bindless_image_load
= true;
264 case nir_intrinsic_bindless_image_size
:
265 case nir_intrinsic_bindless_image_samples
:
266 info
->uses_bindless_images
= true;
268 case nir_intrinsic_bindless_image_store
:
269 info
->uses_bindless_images
= true;
271 if (nir_intrinsic_image_dim(intr
) == GLSL_SAMPLER_DIM_BUF
)
272 info
->uses_bindless_buffer_store
= true;
274 info
->uses_bindless_image_store
= true;
276 info
->writes_memory
= true;
277 info
->num_memory_instructions
++; /* we only care about stores */
279 case nir_intrinsic_image_deref_store
:
280 info
->writes_memory
= true;
281 info
->num_memory_instructions
++; /* we only care about stores */
283 case nir_intrinsic_bindless_image_atomic_add
:
284 case nir_intrinsic_bindless_image_atomic_min
:
285 case nir_intrinsic_bindless_image_atomic_max
:
286 case nir_intrinsic_bindless_image_atomic_and
:
287 case nir_intrinsic_bindless_image_atomic_or
:
288 case nir_intrinsic_bindless_image_atomic_xor
:
289 case nir_intrinsic_bindless_image_atomic_exchange
:
290 case nir_intrinsic_bindless_image_atomic_comp_swap
:
291 info
->uses_bindless_images
= true;
293 if (nir_intrinsic_image_dim(intr
) == GLSL_SAMPLER_DIM_BUF
)
294 info
->uses_bindless_buffer_atomic
= true;
296 info
->uses_bindless_image_atomic
= true;
298 info
->writes_memory
= true;
299 info
->num_memory_instructions
++; /* we only care about stores */
301 case nir_intrinsic_image_deref_atomic_add
:
302 case nir_intrinsic_image_deref_atomic_min
:
303 case nir_intrinsic_image_deref_atomic_max
:
304 case nir_intrinsic_image_deref_atomic_and
:
305 case nir_intrinsic_image_deref_atomic_or
:
306 case nir_intrinsic_image_deref_atomic_xor
:
307 case nir_intrinsic_image_deref_atomic_exchange
:
308 case nir_intrinsic_image_deref_atomic_comp_swap
:
309 case nir_intrinsic_image_deref_atomic_inc_wrap
:
310 case nir_intrinsic_image_deref_atomic_dec_wrap
:
311 info
->writes_memory
= true;
312 info
->num_memory_instructions
++; /* we only care about stores */
314 case nir_intrinsic_store_ssbo
:
315 case nir_intrinsic_ssbo_atomic_add
:
316 case nir_intrinsic_ssbo_atomic_imin
:
317 case nir_intrinsic_ssbo_atomic_umin
:
318 case nir_intrinsic_ssbo_atomic_imax
:
319 case nir_intrinsic_ssbo_atomic_umax
:
320 case nir_intrinsic_ssbo_atomic_and
:
321 case nir_intrinsic_ssbo_atomic_or
:
322 case nir_intrinsic_ssbo_atomic_xor
:
323 case nir_intrinsic_ssbo_atomic_exchange
:
324 case nir_intrinsic_ssbo_atomic_comp_swap
:
325 info
->writes_memory
= true;
326 info
->num_memory_instructions
++; /* we only care about stores */
328 case nir_intrinsic_load_color0
:
329 case nir_intrinsic_load_color1
: {
330 unsigned index
= intr
->intrinsic
== nir_intrinsic_load_color1
;
331 uint8_t mask
= nir_ssa_def_components_read(&intr
->dest
.ssa
);
332 info
->colors_read
|= mask
<< (index
* 4);
335 case nir_intrinsic_load_barycentric_pixel
:
336 case nir_intrinsic_load_barycentric_centroid
:
337 case nir_intrinsic_load_barycentric_sample
:
338 case nir_intrinsic_load_barycentric_at_offset
: /* uses center */
339 case nir_intrinsic_load_barycentric_at_sample
: { /* uses center */
340 unsigned mode
= nir_intrinsic_interp_mode(intr
);
342 if (mode
== INTERP_MODE_FLAT
)
345 if (mode
== INTERP_MODE_NOPERSPECTIVE
) {
346 if (intr
->intrinsic
== nir_intrinsic_load_barycentric_sample
)
347 info
->uses_linear_sample
= true;
348 else if (intr
->intrinsic
== nir_intrinsic_load_barycentric_centroid
)
349 info
->uses_linear_centroid
= true;
351 info
->uses_linear_center
= true;
353 if (intr
->intrinsic
== nir_intrinsic_load_barycentric_at_sample
)
354 info
->uses_linear_opcode_interp_sample
= true;
356 if (intr
->intrinsic
== nir_intrinsic_load_barycentric_sample
)
357 info
->uses_persp_sample
= true;
358 else if (intr
->intrinsic
== nir_intrinsic_load_barycentric_centroid
)
359 info
->uses_persp_centroid
= true;
361 info
->uses_persp_center
= true;
363 if (intr
->intrinsic
== nir_intrinsic_load_barycentric_at_sample
)
364 info
->uses_persp_opcode_interp_sample
= true;
368 case nir_intrinsic_load_deref
: {
369 nir_variable
*var
= intrinsic_get_var(intr
);
370 nir_variable_mode mode
= var
->data
.mode
;
372 if (mode
== nir_var_shader_in
) {
373 /* PS inputs use the interpolated load intrinsics. */
374 assert(nir
->info
.stage
!= MESA_SHADER_FRAGMENT
);
375 gather_intrinsic_load_deref_input_info(nir
, intr
, var
, info
);
376 } else if (mode
== nir_var_shader_out
) {
377 gather_intrinsic_load_deref_output_info(nir
, intr
, var
, info
);
381 case nir_intrinsic_store_deref
: {
382 nir_variable
*var
= intrinsic_get_var(intr
);
384 if (var
->data
.mode
== nir_var_shader_out
)
385 gather_intrinsic_store_deref_output_info(nir
, intr
, var
, info
);
388 case nir_intrinsic_interp_deref_at_centroid
:
389 case nir_intrinsic_interp_deref_at_sample
:
390 case nir_intrinsic_interp_deref_at_offset
:
391 unreachable("interp opcodes should have been lowered");
399 void si_nir_scan_tess_ctrl(const struct nir_shader
*nir
,
400 struct tgsi_tessctrl_info
*out
)
402 memset(out
, 0, sizeof(*out
));
404 if (nir
->info
.stage
!= MESA_SHADER_TESS_CTRL
)
407 out
->tessfactors_are_def_in_all_invocs
=
408 ac_are_tessfactors_def_in_all_invocs(nir
);
411 void si_nir_scan_shader(const struct nir_shader
*nir
,
412 struct tgsi_shader_info
*info
)
417 info
->processor
= pipe_shader_type_from_mesa(nir
->info
.stage
);
418 info
->num_tokens
= 2; /* indicate that the shader is non-empty */
419 info
->num_instructions
= 2;
421 info
->properties
[TGSI_PROPERTY_NEXT_SHADER
] =
422 pipe_shader_type_from_mesa(nir
->info
.next_stage
);
424 if (nir
->info
.stage
== MESA_SHADER_VERTEX
) {
425 info
->properties
[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION
] =
426 nir
->info
.vs
.window_space_position
;
427 info
->properties
[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD
] =
428 nir
->info
.vs
.blit_sgprs_amd
;
431 if (nir
->info
.stage
== MESA_SHADER_TESS_CTRL
) {
432 info
->properties
[TGSI_PROPERTY_TCS_VERTICES_OUT
] =
433 nir
->info
.tess
.tcs_vertices_out
;
436 if (nir
->info
.stage
== MESA_SHADER_TESS_EVAL
) {
437 if (nir
->info
.tess
.primitive_mode
== GL_ISOLINES
)
438 info
->properties
[TGSI_PROPERTY_TES_PRIM_MODE
] = PIPE_PRIM_LINES
;
440 info
->properties
[TGSI_PROPERTY_TES_PRIM_MODE
] = nir
->info
.tess
.primitive_mode
;
442 STATIC_ASSERT((TESS_SPACING_EQUAL
+ 1) % 3 == PIPE_TESS_SPACING_EQUAL
);
443 STATIC_ASSERT((TESS_SPACING_FRACTIONAL_ODD
+ 1) % 3 ==
444 PIPE_TESS_SPACING_FRACTIONAL_ODD
);
445 STATIC_ASSERT((TESS_SPACING_FRACTIONAL_EVEN
+ 1) % 3 ==
446 PIPE_TESS_SPACING_FRACTIONAL_EVEN
);
448 info
->properties
[TGSI_PROPERTY_TES_SPACING
] = (nir
->info
.tess
.spacing
+ 1) % 3;
449 info
->properties
[TGSI_PROPERTY_TES_VERTEX_ORDER_CW
] = !nir
->info
.tess
.ccw
;
450 info
->properties
[TGSI_PROPERTY_TES_POINT_MODE
] = nir
->info
.tess
.point_mode
;
453 if (nir
->info
.stage
== MESA_SHADER_GEOMETRY
) {
454 info
->properties
[TGSI_PROPERTY_GS_INPUT_PRIM
] = nir
->info
.gs
.input_primitive
;
455 info
->properties
[TGSI_PROPERTY_GS_OUTPUT_PRIM
] = nir
->info
.gs
.output_primitive
;
456 info
->properties
[TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES
] = nir
->info
.gs
.vertices_out
;
457 info
->properties
[TGSI_PROPERTY_GS_INVOCATIONS
] = nir
->info
.gs
.invocations
;
460 if (nir
->info
.stage
== MESA_SHADER_FRAGMENT
) {
461 info
->properties
[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL
] =
462 nir
->info
.fs
.early_fragment_tests
| nir
->info
.fs
.post_depth_coverage
;
463 info
->properties
[TGSI_PROPERTY_FS_POST_DEPTH_COVERAGE
] = nir
->info
.fs
.post_depth_coverage
;
465 if (nir
->info
.fs
.pixel_center_integer
) {
466 info
->properties
[TGSI_PROPERTY_FS_COORD_PIXEL_CENTER
] =
467 TGSI_FS_COORD_PIXEL_CENTER_INTEGER
;
470 if (nir
->info
.fs
.depth_layout
!= FRAG_DEPTH_LAYOUT_NONE
) {
471 switch (nir
->info
.fs
.depth_layout
) {
472 case FRAG_DEPTH_LAYOUT_ANY
:
473 info
->properties
[TGSI_PROPERTY_FS_DEPTH_LAYOUT
] = TGSI_FS_DEPTH_LAYOUT_ANY
;
475 case FRAG_DEPTH_LAYOUT_GREATER
:
476 info
->properties
[TGSI_PROPERTY_FS_DEPTH_LAYOUT
] = TGSI_FS_DEPTH_LAYOUT_GREATER
;
478 case FRAG_DEPTH_LAYOUT_LESS
:
479 info
->properties
[TGSI_PROPERTY_FS_DEPTH_LAYOUT
] = TGSI_FS_DEPTH_LAYOUT_LESS
;
481 case FRAG_DEPTH_LAYOUT_UNCHANGED
:
482 info
->properties
[TGSI_PROPERTY_FS_DEPTH_LAYOUT
] = TGSI_FS_DEPTH_LAYOUT_UNCHANGED
;
485 unreachable("Unknow depth layout");
490 if (gl_shader_stage_is_compute(nir
->info
.stage
)) {
491 info
->properties
[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH
] = nir
->info
.cs
.local_size
[0];
492 info
->properties
[TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT
] = nir
->info
.cs
.local_size
[1];
493 info
->properties
[TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH
] = nir
->info
.cs
.local_size
[2];
494 info
->properties
[TGSI_PROPERTY_CS_USER_DATA_COMPONENTS_AMD
] = nir
->info
.cs
.user_data_components_amd
;
498 uint64_t processed_inputs
= 0;
499 nir_foreach_variable(variable
, &nir
->inputs
) {
500 unsigned semantic_name
, semantic_index
;
502 const struct glsl_type
*type
= variable
->type
;
503 if (nir_is_per_vertex_io(variable
, nir
->info
.stage
)) {
504 assert(glsl_type_is_array(type
));
505 type
= glsl_get_array_element(type
);
508 unsigned attrib_count
= glsl_count_attribute_slots(type
,
509 nir
->info
.stage
== MESA_SHADER_VERTEX
);
511 i
= variable
->data
.driver_location
;
513 /* Vertex shader inputs don't have semantics. The state
514 * tracker has already mapped them to attributes via
515 * variable->data.driver_location.
517 if (nir
->info
.stage
== MESA_SHADER_VERTEX
) {
518 processed_inputs
|= 1ull << i
;
520 if (glsl_type_is_dual_slot(glsl_without_array(variable
->type
)))
521 processed_inputs
|= 2ull << i
;
525 for (unsigned j
= 0; j
< attrib_count
; j
++, i
++) {
527 if (processed_inputs
& ((uint64_t)1 << i
))
530 processed_inputs
|= ((uint64_t)1 << i
);
532 tgsi_get_gl_varying_semantic(variable
->data
.location
+ j
, true,
533 &semantic_name
, &semantic_index
);
535 info
->input_semantic_name
[i
] = semantic_name
;
536 info
->input_semantic_index
[i
] = semantic_index
;
538 if (semantic_name
== TGSI_SEMANTIC_PRIMID
)
539 info
->uses_primid
= true;
541 if (semantic_name
== TGSI_SEMANTIC_COLOR
) {
542 /* We only need this for color inputs. */
543 if (variable
->data
.sample
)
544 info
->input_interpolate_loc
[i
] = TGSI_INTERPOLATE_LOC_SAMPLE
;
545 else if (variable
->data
.centroid
)
546 info
->input_interpolate_loc
[i
] = TGSI_INTERPOLATE_LOC_CENTROID
;
548 info
->input_interpolate_loc
[i
] = TGSI_INTERPOLATE_LOC_CENTER
;
551 enum glsl_base_type base_type
=
552 glsl_get_base_type(glsl_without_array(variable
->type
));
554 switch (variable
->data
.interpolation
) {
555 case INTERP_MODE_NONE
:
556 if (glsl_base_type_is_integer(base_type
)) {
557 info
->input_interpolate
[i
] = TGSI_INTERPOLATE_CONSTANT
;
561 if (semantic_name
== TGSI_SEMANTIC_COLOR
) {
562 info
->input_interpolate
[i
] = TGSI_INTERPOLATE_COLOR
;
567 case INTERP_MODE_SMOOTH
:
568 assert(!glsl_base_type_is_integer(base_type
));
570 info
->input_interpolate
[i
] = TGSI_INTERPOLATE_PERSPECTIVE
;
573 case INTERP_MODE_NOPERSPECTIVE
:
574 assert(!glsl_base_type_is_integer(base_type
));
576 info
->input_interpolate
[i
] = TGSI_INTERPOLATE_LINEAR
;
579 case INTERP_MODE_FLAT
:
580 info
->input_interpolate
[i
] = TGSI_INTERPOLATE_CONSTANT
;
587 uint64_t processed_outputs
= 0;
588 nir_foreach_variable(variable
, &nir
->outputs
) {
589 unsigned semantic_name
, semantic_index
;
591 i
= variable
->data
.driver_location
;
593 const struct glsl_type
*type
= variable
->type
;
594 if (nir_is_per_vertex_io(variable
, nir
->info
.stage
)) {
595 assert(glsl_type_is_array(type
));
596 type
= glsl_get_array_element(type
);
599 unsigned attrib_count
= glsl_count_attribute_slots(type
, false);
600 for (unsigned k
= 0; k
< attrib_count
; k
++, i
++) {
602 if (nir
->info
.stage
== MESA_SHADER_FRAGMENT
) {
603 tgsi_get_gl_frag_result_semantic(variable
->data
.location
+ k
,
604 &semantic_name
, &semantic_index
);
606 /* Adjust for dual source blending */
607 if (variable
->data
.index
> 0) {
611 tgsi_get_gl_varying_semantic(variable
->data
.location
+ k
, true,
612 &semantic_name
, &semantic_index
);
615 unsigned num_components
= 4;
616 unsigned vector_elements
= glsl_get_vector_elements(glsl_without_array(variable
->type
));
618 num_components
= vector_elements
;
620 unsigned component
= variable
->data
.location_frac
;
621 if (glsl_type_is_64bit(glsl_without_array(variable
->type
))) {
622 if (glsl_type_is_dual_slot(glsl_without_array(variable
->type
)) && k
% 2) {
623 num_components
= (num_components
* 2) - 4;
626 num_components
= MIN2(num_components
* 2, 4);
631 for (unsigned j
= component
; j
< num_components
+ component
; j
++) {
634 usagemask
|= TGSI_WRITEMASK_X
;
637 usagemask
|= TGSI_WRITEMASK_Y
;
640 usagemask
|= TGSI_WRITEMASK_Z
;
643 usagemask
|= TGSI_WRITEMASK_W
;
646 unreachable("error calculating component index");
650 unsigned gs_out_streams
;
651 if (variable
->data
.stream
& (1u << 31)) {
652 gs_out_streams
= variable
->data
.stream
& ~(1u << 31);
654 assert(variable
->data
.stream
< 4);
656 for (unsigned j
= 0; j
< num_components
; ++j
)
657 gs_out_streams
|= variable
->data
.stream
<< (2 * (component
+ j
));
660 unsigned streamx
= gs_out_streams
& 3;
661 unsigned streamy
= (gs_out_streams
>> 2) & 3;
662 unsigned streamz
= (gs_out_streams
>> 4) & 3;
663 unsigned streamw
= (gs_out_streams
>> 6) & 3;
665 if (usagemask
& TGSI_WRITEMASK_X
) {
666 info
->output_streams
[i
] |= streamx
;
667 info
->num_stream_output_components
[streamx
]++;
669 if (usagemask
& TGSI_WRITEMASK_Y
) {
670 info
->output_streams
[i
] |= streamy
<< 2;
671 info
->num_stream_output_components
[streamy
]++;
673 if (usagemask
& TGSI_WRITEMASK_Z
) {
674 info
->output_streams
[i
] |= streamz
<< 4;
675 info
->num_stream_output_components
[streamz
]++;
677 if (usagemask
& TGSI_WRITEMASK_W
) {
678 info
->output_streams
[i
] |= streamw
<< 6;
679 info
->num_stream_output_components
[streamw
]++;
682 /* make sure we only count this location once against
683 * the num_outputs counter.
685 if (processed_outputs
& ((uint64_t)1 << i
))
688 processed_outputs
|= ((uint64_t)1 << i
);
690 info
->output_semantic_name
[i
] = semantic_name
;
691 info
->output_semantic_index
[i
] = semantic_index
;
693 switch (semantic_name
) {
694 case TGSI_SEMANTIC_PRIMID
:
695 info
->writes_primid
= true;
697 case TGSI_SEMANTIC_VIEWPORT_INDEX
:
698 info
->writes_viewport_index
= true;
700 case TGSI_SEMANTIC_LAYER
:
701 info
->writes_layer
= true;
703 case TGSI_SEMANTIC_PSIZE
:
704 info
->writes_psize
= true;
706 case TGSI_SEMANTIC_CLIPVERTEX
:
707 info
->writes_clipvertex
= true;
709 case TGSI_SEMANTIC_COLOR
:
710 info
->colors_written
|= 1 << semantic_index
;
712 case TGSI_SEMANTIC_STENCIL
:
713 info
->writes_stencil
= true;
715 case TGSI_SEMANTIC_SAMPLEMASK
:
716 info
->writes_samplemask
= true;
718 case TGSI_SEMANTIC_EDGEFLAG
:
719 info
->writes_edgeflag
= true;
721 case TGSI_SEMANTIC_POSITION
:
722 if (info
->processor
== PIPE_SHADER_FRAGMENT
)
723 info
->writes_z
= true;
725 info
->writes_position
= true;
730 unsigned loc
= variable
->data
.location
;
731 if (nir
->info
.stage
== MESA_SHADER_FRAGMENT
&&
732 loc
== FRAG_RESULT_COLOR
&&
733 nir
->info
.outputs_written
& (1ull << loc
)) {
734 assert(attrib_count
== 1);
735 info
->properties
[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS
] = true;
739 info
->num_inputs
= util_last_bit64(processed_inputs
);
740 info
->num_outputs
= util_last_bit64(processed_outputs
);
742 /* Inputs and outputs can't have holes. If this fails, use
743 * nir_assign_io_var_locations to re-assign driver_location.
745 assert(processed_inputs
== u_bit_consecutive64(0, info
->num_inputs
));
746 assert(processed_outputs
== u_bit_consecutive64(0, info
->num_outputs
));
748 struct set
*ubo_set
= _mesa_set_create(NULL
, _mesa_hash_pointer
,
749 _mesa_key_pointer_equal
);
750 struct set
*ssbo_set
= _mesa_set_create(NULL
, _mesa_hash_pointer
,
751 _mesa_key_pointer_equal
);
753 /* Intialise const_file_max[0] */
754 info
->const_file_max
[0] = -1;
756 /* The first 8 are reserved for atomic counters using ssbo */
757 unsigned ssbo_idx
= 8;
759 unsigned ubo_idx
= 1;
760 nir_foreach_variable(variable
, &nir
->uniforms
) {
761 const struct glsl_type
*type
= variable
->type
;
762 enum glsl_base_type base_type
=
763 glsl_get_base_type(glsl_without_array(type
));
764 unsigned aoa_size
= MAX2(1, glsl_get_aoa_size(type
));
765 unsigned loc
= variable
->data
.driver_location
/ 4;
766 int slot_count
= glsl_count_attribute_slots(type
, false);
767 int max_slot
= MAX2(info
->const_file_max
[0], (int) loc
) + slot_count
;
769 /* Gather buffers declared bitmasks. Note: radeonsi doesn't
770 * really use the mask (other than ubo_idx == 1 for regular
771 * uniforms) its really only used for getting the buffer count
772 * so we don't need to worry about the ordering.
774 if (variable
->interface_type
!= NULL
) {
775 if (variable
->data
.mode
== nir_var_uniform
||
776 variable
->data
.mode
== nir_var_mem_ubo
||
777 variable
->data
.mode
== nir_var_mem_ssbo
) {
779 struct set
*buf_set
= variable
->data
.mode
== nir_var_mem_ssbo
?
782 unsigned block_count
;
783 if (base_type
!= GLSL_TYPE_INTERFACE
) {
784 struct set_entry
*entry
=
785 _mesa_set_search(buf_set
, variable
->interface_type
);
787 /* Check if we have already processed
788 * a member from this ubo.
795 block_count
= aoa_size
;
798 if (variable
->data
.mode
== nir_var_uniform
||
799 variable
->data
.mode
== nir_var_mem_ubo
) {
800 info
->const_buffers_declared
|= u_bit_consecutive(ubo_idx
, block_count
);
801 ubo_idx
+= block_count
;
803 assert(variable
->data
.mode
== nir_var_mem_ssbo
);
805 info
->shader_buffers_declared
|= u_bit_consecutive(ssbo_idx
, block_count
);
806 ssbo_idx
+= block_count
;
809 _mesa_set_add(buf_set
, variable
->interface_type
);
815 /* We rely on the fact that nir_lower_samplers_as_deref has
816 * eliminated struct dereferences.
818 if (base_type
== GLSL_TYPE_SAMPLER
&& !variable
->data
.bindless
) {
819 info
->samplers_declared
|=
820 u_bit_consecutive(variable
->data
.binding
, aoa_size
);
821 } else if (base_type
== GLSL_TYPE_IMAGE
&& !variable
->data
.bindless
) {
822 info
->images_declared
|=
823 u_bit_consecutive(variable
->data
.binding
, aoa_size
);
824 } else if (base_type
!= GLSL_TYPE_ATOMIC_UINT
) {
825 info
->const_buffers_declared
|= 1;
826 info
->const_file_max
[0] = max_slot
;
830 _mesa_set_destroy(ubo_set
, NULL
);
831 _mesa_set_destroy(ssbo_set
, NULL
);
833 info
->num_written_clipdistance
= nir
->info
.clip_distance_array_size
;
834 info
->num_written_culldistance
= nir
->info
.cull_distance_array_size
;
835 info
->clipdist_writemask
= u_bit_consecutive(0, info
->num_written_clipdistance
);
836 info
->culldist_writemask
= u_bit_consecutive(0, info
->num_written_culldistance
);
838 if (info
->processor
== PIPE_SHADER_FRAGMENT
)
839 info
->uses_kill
= nir
->info
.fs
.uses_discard
;
841 func
= (struct nir_function
*)exec_list_get_head_const(&nir
->functions
);
842 nir_foreach_block(block
, func
->impl
) {
843 nir_foreach_instr(instr
, block
)
844 scan_instruction(nir
, info
, instr
);
849 si_nir_opts(struct nir_shader
*nir
)
852 unsigned lower_flrp
=
853 (nir
->options
->lower_flrp16
? 16 : 0) |
854 (nir
->options
->lower_flrp32
? 32 : 0) |
855 (nir
->options
->lower_flrp64
? 64 : 0);
860 NIR_PASS_V(nir
, nir_lower_vars_to_ssa
);
862 NIR_PASS(progress
, nir
, nir_opt_copy_prop_vars
);
863 NIR_PASS(progress
, nir
, nir_opt_dead_write_vars
);
865 NIR_PASS_V(nir
, nir_lower_alu_to_scalar
, NULL
);
866 NIR_PASS_V(nir
, nir_lower_phis_to_scalar
);
868 /* (Constant) copy propagation is needed for txf with offsets. */
869 NIR_PASS(progress
, nir
, nir_copy_prop
);
870 NIR_PASS(progress
, nir
, nir_opt_remove_phis
);
871 NIR_PASS(progress
, nir
, nir_opt_dce
);
872 if (nir_opt_trivial_continues(nir
)) {
874 NIR_PASS(progress
, nir
, nir_copy_prop
);
875 NIR_PASS(progress
, nir
, nir_opt_dce
);
877 NIR_PASS(progress
, nir
, nir_opt_if
, true);
878 NIR_PASS(progress
, nir
, nir_opt_dead_cf
);
879 NIR_PASS(progress
, nir
, nir_opt_cse
);
880 NIR_PASS(progress
, nir
, nir_opt_peephole_select
, 8, true, true);
882 /* Needed for algebraic lowering */
883 NIR_PASS(progress
, nir
, nir_opt_algebraic
);
884 NIR_PASS(progress
, nir
, nir_opt_constant_folding
);
886 if (lower_flrp
!= 0) {
887 bool lower_flrp_progress
= false;
889 NIR_PASS(lower_flrp_progress
, nir
, nir_lower_flrp
,
891 false /* always_precise */,
892 nir
->options
->lower_ffma
);
893 if (lower_flrp_progress
) {
894 NIR_PASS(progress
, nir
,
895 nir_opt_constant_folding
);
899 /* Nothing should rematerialize any flrps, so we only
900 * need to do this lowering once.
905 NIR_PASS(progress
, nir
, nir_opt_undef
);
906 NIR_PASS(progress
, nir
, nir_opt_conditional_discard
);
907 if (nir
->options
->max_unroll_iterations
) {
908 NIR_PASS(progress
, nir
, nir_opt_loop_unroll
, 0);
914 type_size_vec4(const struct glsl_type
*type
, bool bindless
)
916 return glsl_count_attribute_slots(type
, false);
920 si_nir_lower_color(nir_shader
*nir
)
922 nir_function_impl
*entrypoint
= nir_shader_get_entrypoint(nir
);
925 nir_builder_init(&b
, entrypoint
);
927 nir_foreach_block(block
, entrypoint
) {
928 nir_foreach_instr_safe(instr
, block
) {
929 if (instr
->type
!= nir_instr_type_intrinsic
)
932 nir_intrinsic_instr
*intrin
=
933 nir_instr_as_intrinsic(instr
);
935 if (intrin
->intrinsic
!= nir_intrinsic_load_deref
)
938 nir_deref_instr
*deref
= nir_src_as_deref(intrin
->src
[0]);
939 if (deref
->mode
!= nir_var_shader_in
)
942 b
.cursor
= nir_before_instr(instr
);
943 nir_variable
*var
= nir_deref_instr_get_variable(deref
);
946 if (var
->data
.location
== VARYING_SLOT_COL0
) {
947 def
= nir_load_color0(&b
);
948 } else if (var
->data
.location
== VARYING_SLOT_COL1
) {
949 def
= nir_load_color1(&b
);
954 nir_ssa_def_rewrite_uses(&intrin
->dest
.ssa
, nir_src_for_ssa(def
));
955 nir_instr_remove(instr
);
960 void si_nir_lower_ps_inputs(struct nir_shader
*nir
)
962 if (nir
->info
.stage
!= MESA_SHADER_FRAGMENT
)
965 NIR_PASS_V(nir
, nir_lower_io_to_temporaries
,
966 nir_shader_get_entrypoint(nir
), false, true);
968 /* Since we're doing nir_lower_io_to_temporaries late, we need
969 * to lower all the copy_deref's introduced by
970 * lower_io_to_temporaries before calling nir_lower_io.
972 NIR_PASS_V(nir
, nir_split_var_copies
);
973 NIR_PASS_V(nir
, nir_lower_var_copies
);
974 NIR_PASS_V(nir
, nir_lower_global_vars_to_local
);
976 si_nir_lower_color(nir
);
977 NIR_PASS_V(nir
, nir_lower_io
, nir_var_shader_in
, type_size_vec4
, 0);
979 /* This pass needs actual constants */
980 NIR_PASS_V(nir
, nir_opt_constant_folding
);
981 NIR_PASS_V(nir
, nir_io_add_const_offset_to_base
,
986 * Perform "lowering" operations on the NIR that are run once when the shader
987 * selector is created.
990 si_lower_nir(struct si_shader_selector
* sel
, unsigned wave_size
)
992 /* Adjust the driver location of inputs and outputs. The state tracker
993 * interprets them as slots, while the ac/nir backend interprets them
994 * as individual components.
996 if (sel
->nir
->info
.stage
!= MESA_SHADER_FRAGMENT
) {
997 nir_foreach_variable(variable
, &sel
->nir
->inputs
)
998 variable
->data
.driver_location
*= 4;
1001 nir_foreach_variable(variable
, &sel
->nir
->outputs
) {
1002 variable
->data
.driver_location
*= 4;
1004 if (sel
->nir
->info
.stage
== MESA_SHADER_FRAGMENT
) {
1005 if (variable
->data
.location
== FRAG_RESULT_DEPTH
)
1006 variable
->data
.driver_location
+= 2;
1007 else if (variable
->data
.location
== FRAG_RESULT_STENCIL
)
1008 variable
->data
.driver_location
+= 1;
1012 /* Perform lowerings (and optimizations) of code.
1014 * Performance considerations aside, we must:
1015 * - lower certain ALU operations
1016 * - ensure constant offsets for texture instructions are folded
1017 * and copy-propagated
1020 static const struct nir_lower_tex_options lower_tex_options
= {
1023 NIR_PASS_V(sel
->nir
, nir_lower_tex
, &lower_tex_options
);
1025 const nir_lower_subgroups_options subgroups_options
= {
1026 .subgroup_size
= wave_size
,
1027 .ballot_bit_size
= wave_size
,
1028 .lower_to_scalar
= true,
1029 .lower_subgroup_masks
= true,
1030 .lower_vote_trivial
= false,
1031 .lower_vote_eq_to_ballot
= true,
1033 NIR_PASS_V(sel
->nir
, nir_lower_subgroups
, &subgroups_options
);
1035 ac_lower_indirect_derefs(sel
->nir
, sel
->screen
->info
.chip_class
);
1037 si_nir_opts(sel
->nir
);
1039 NIR_PASS_V(sel
->nir
, nir_lower_bool_to_int32
);
1041 /* Strip the resulting shader so that the shader cache is more likely
1042 * to hit from other similar shaders.
1044 nir_strip(sel
->nir
);
1047 static void declare_nir_input_vs(struct si_shader_context
*ctx
,
1048 struct nir_variable
*variable
,
1049 unsigned input_index
,
1050 LLVMValueRef out
[4])
1052 si_llvm_load_input_vs(ctx
, input_index
, out
);
1056 si_nir_lookup_interp_param(struct ac_shader_abi
*abi
,
1057 enum glsl_interp_mode interp
, unsigned location
)
1059 struct si_shader_context
*ctx
= si_shader_context_from_abi(abi
);
1060 int interp_param_idx
= -1;
1063 case INTERP_MODE_FLAT
:
1065 case INTERP_MODE_SMOOTH
:
1066 case INTERP_MODE_NONE
:
1067 if (location
== INTERP_CENTER
)
1068 interp_param_idx
= SI_PARAM_PERSP_CENTER
;
1069 else if (location
== INTERP_CENTROID
)
1070 interp_param_idx
= SI_PARAM_PERSP_CENTROID
;
1071 else if (location
== INTERP_SAMPLE
)
1072 interp_param_idx
= SI_PARAM_PERSP_SAMPLE
;
1074 case INTERP_MODE_NOPERSPECTIVE
:
1075 if (location
== INTERP_CENTER
)
1076 interp_param_idx
= SI_PARAM_LINEAR_CENTER
;
1077 else if (location
== INTERP_CENTROID
)
1078 interp_param_idx
= SI_PARAM_LINEAR_CENTROID
;
1079 else if (location
== INTERP_SAMPLE
)
1080 interp_param_idx
= SI_PARAM_LINEAR_SAMPLE
;
1083 assert(!"Unhandled interpolation mode.");
1087 return interp_param_idx
!= -1 ?
1088 LLVMGetParam(ctx
->main_fn
, interp_param_idx
) : NULL
;
1092 si_nir_load_sampler_desc(struct ac_shader_abi
*abi
,
1093 unsigned descriptor_set
, unsigned base_index
,
1094 unsigned constant_index
, LLVMValueRef dynamic_index
,
1095 enum ac_descriptor_type desc_type
, bool image
,
1096 bool write
, bool bindless
)
1098 struct si_shader_context
*ctx
= si_shader_context_from_abi(abi
);
1099 LLVMBuilderRef builder
= ctx
->ac
.builder
;
1100 unsigned const_index
= base_index
+ constant_index
;
1102 assert(!descriptor_set
);
1103 assert(!image
|| desc_type
== AC_DESC_IMAGE
|| desc_type
== AC_DESC_BUFFER
);
1107 LLVMGetParam(ctx
->main_fn
, ctx
->param_bindless_samplers_and_images
);
1109 /* dynamic_index is the bindless handle */
1111 /* For simplicity, bindless image descriptors use fixed
1112 * 16-dword slots for now.
1114 dynamic_index
= LLVMBuildMul(ctx
->ac
.builder
, dynamic_index
,
1115 LLVMConstInt(ctx
->i64
, 2, 0), "");
1117 return si_load_image_desc(ctx
, list
, dynamic_index
, desc_type
,
1121 /* Since bindless handle arithmetic can contain an unsigned integer
1122 * wraparound and si_load_sampler_desc assumes there isn't any,
1123 * use GEP without "inbounds" (inside ac_build_pointer_add)
1124 * to prevent incorrect code generation and hangs.
1126 dynamic_index
= LLVMBuildMul(ctx
->ac
.builder
, dynamic_index
,
1127 LLVMConstInt(ctx
->i64
, 2, 0), "");
1128 list
= ac_build_pointer_add(&ctx
->ac
, list
, dynamic_index
);
1129 return si_load_sampler_desc(ctx
, list
, ctx
->i32_0
, desc_type
);
1132 unsigned num_slots
= image
? ctx
->num_images
: ctx
->num_samplers
;
1133 assert(const_index
< num_slots
|| dynamic_index
);
1135 LLVMValueRef list
= LLVMGetParam(ctx
->main_fn
, ctx
->param_samplers_and_images
);
1136 LLVMValueRef index
= LLVMConstInt(ctx
->ac
.i32
, const_index
, false);
1138 if (dynamic_index
) {
1139 index
= LLVMBuildAdd(builder
, index
, dynamic_index
, "");
1141 /* From the GL_ARB_shader_image_load_store extension spec:
1143 * If a shader performs an image load, store, or atomic
1144 * operation using an image variable declared as an array,
1145 * and if the index used to select an individual element is
1146 * negative or greater than or equal to the size of the
1147 * array, the results of the operation are undefined but may
1148 * not lead to termination.
1150 index
= si_llvm_bound_index(ctx
, index
, num_slots
);
1154 index
= LLVMBuildSub(ctx
->ac
.builder
,
1155 LLVMConstInt(ctx
->i32
, SI_NUM_IMAGES
- 1, 0),
1157 return si_load_image_desc(ctx
, list
, index
, desc_type
, write
, false);
1160 index
= LLVMBuildAdd(ctx
->ac
.builder
, index
,
1161 LLVMConstInt(ctx
->i32
, SI_NUM_IMAGES
/ 2, 0), "");
1162 return si_load_sampler_desc(ctx
, list
, index
, desc_type
);
1165 static void bitcast_inputs(struct si_shader_context
*ctx
,
1166 LLVMValueRef data
[4],
1169 for (unsigned chan
= 0; chan
< 4; chan
++) {
1170 ctx
->inputs
[input_idx
+ chan
] =
1171 LLVMBuildBitCast(ctx
->ac
.builder
, data
[chan
], ctx
->ac
.i32
, "");
1175 bool si_nir_build_llvm(struct si_shader_context
*ctx
, struct nir_shader
*nir
)
1177 struct tgsi_shader_info
*info
= &ctx
->shader
->selector
->info
;
1179 if (nir
->info
.stage
== MESA_SHADER_VERTEX
) {
1180 uint64_t processed_inputs
= 0;
1181 nir_foreach_variable(variable
, &nir
->inputs
) {
1182 unsigned attrib_count
= glsl_count_attribute_slots(variable
->type
,
1184 unsigned input_idx
= variable
->data
.driver_location
;
1186 LLVMValueRef data
[4];
1187 unsigned loc
= variable
->data
.location
;
1189 for (unsigned i
= 0; i
< attrib_count
; i
++) {
1190 /* Packed components share the same location so skip
1191 * them if we have already processed the location.
1193 if (processed_inputs
& ((uint64_t)1 << (loc
+ i
))) {
1198 declare_nir_input_vs(ctx
, variable
, input_idx
/ 4, data
);
1199 bitcast_inputs(ctx
, data
, input_idx
);
1200 if (glsl_type_is_dual_slot(variable
->type
)) {
1202 declare_nir_input_vs(ctx
, variable
, input_idx
/ 4, data
);
1203 bitcast_inputs(ctx
, data
, input_idx
);
1206 processed_inputs
|= ((uint64_t)1 << (loc
+ i
));
1210 } else if (nir
->info
.stage
== MESA_SHADER_FRAGMENT
) {
1211 unsigned colors_read
=
1212 ctx
->shader
->selector
->info
.colors_read
;
1213 LLVMValueRef main_fn
= ctx
->main_fn
;
1215 LLVMValueRef undef
= LLVMGetUndef(ctx
->f32
);
1217 unsigned offset
= SI_PARAM_POS_FIXED_PT
+ 1;
1219 if (colors_read
& 0x0f) {
1220 unsigned mask
= colors_read
& 0x0f;
1221 LLVMValueRef values
[4];
1222 values
[0] = mask
& 0x1 ? LLVMGetParam(main_fn
, offset
++) : undef
;
1223 values
[1] = mask
& 0x2 ? LLVMGetParam(main_fn
, offset
++) : undef
;
1224 values
[2] = mask
& 0x4 ? LLVMGetParam(main_fn
, offset
++) : undef
;
1225 values
[3] = mask
& 0x8 ? LLVMGetParam(main_fn
, offset
++) : undef
;
1227 ac_to_integer(&ctx
->ac
,
1228 ac_build_gather_values(&ctx
->ac
, values
, 4));
1230 if (colors_read
& 0xf0) {
1231 unsigned mask
= (colors_read
& 0xf0) >> 4;
1232 LLVMValueRef values
[4];
1233 values
[0] = mask
& 0x1 ? LLVMGetParam(main_fn
, offset
++) : undef
;
1234 values
[1] = mask
& 0x2 ? LLVMGetParam(main_fn
, offset
++) : undef
;
1235 values
[2] = mask
& 0x4 ? LLVMGetParam(main_fn
, offset
++) : undef
;
1236 values
[3] = mask
& 0x8 ? LLVMGetParam(main_fn
, offset
++) : undef
;
1238 ac_to_integer(&ctx
->ac
,
1239 ac_build_gather_values(&ctx
->ac
, values
, 4));
1242 ctx
->abi
.interp_at_sample_force_center
=
1243 ctx
->shader
->key
.mono
.u
.ps
.interpolate_at_sample_force_center
;
1244 } else if (nir
->info
.stage
== MESA_SHADER_COMPUTE
) {
1245 if (nir
->info
.cs
.user_data_components_amd
) {
1246 ctx
->abi
.user_data
= LLVMGetParam(ctx
->main_fn
, ctx
->param_cs_user_data
);
1247 ctx
->abi
.user_data
= ac_build_expand_to_vec4(&ctx
->ac
, ctx
->abi
.user_data
,
1248 nir
->info
.cs
.user_data_components_amd
);
1252 ctx
->abi
.inputs
= &ctx
->inputs
[0];
1253 ctx
->abi
.load_sampler_desc
= si_nir_load_sampler_desc
;
1254 ctx
->abi
.clamp_shadow_reference
= true;
1255 ctx
->abi
.robust_buffer_access
= true;
1257 ctx
->num_samplers
= util_last_bit(info
->samplers_declared
);
1258 ctx
->num_images
= util_last_bit(info
->images_declared
);
1260 if (ctx
->shader
->selector
->info
.properties
[TGSI_PROPERTY_CS_LOCAL_SIZE
]) {
1261 assert(gl_shader_stage_is_compute(nir
->info
.stage
));
1262 si_declare_compute_memory(ctx
);
1264 ac_nir_translate(&ctx
->ac
, &ctx
->abi
, nir
);