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radeonsi/nir: Use nir stripping pass
[mesa.git] / src / gallium / drivers / radeonsi / si_shader_nir.c
1 /*
2 * Copyright 2017 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 #include "si_shader_internal.h"
26 #include "si_pipe.h"
27
28 #include "ac_nir_to_llvm.h"
29
30 #include "tgsi/tgsi_from_mesa.h"
31
32 #include "compiler/nir/nir.h"
33 #include "compiler/nir_types.h"
34
35 static nir_variable* tex_get_texture_var(nir_tex_instr *instr)
36 {
37 for (unsigned i = 0; i < instr->num_srcs; i++) {
38 switch (instr->src[i].src_type) {
39 case nir_tex_src_texture_deref:
40 return nir_deref_instr_get_variable(nir_src_as_deref(instr->src[i].src));
41 default:
42 break;
43 }
44 }
45
46 return NULL;
47 }
48
49 static nir_variable* intrinsic_get_var(nir_intrinsic_instr *instr)
50 {
51 return nir_deref_instr_get_variable(nir_src_as_deref(instr->src[0]));
52 }
53
54 static void gather_intrinsic_load_deref_info(const nir_shader *nir,
55 const nir_intrinsic_instr *instr,
56 nir_variable *var,
57 struct tgsi_shader_info *info)
58 {
59 assert(var && var->data.mode == nir_var_shader_in);
60
61 switch (nir->info.stage) {
62 case MESA_SHADER_VERTEX: {
63 unsigned i = var->data.driver_location;
64 unsigned attrib_count = glsl_count_attribute_slots(var->type, false);
65
66 for (unsigned j = 0; j < attrib_count; j++, i++) {
67 if (glsl_type_is_64bit(glsl_without_array(var->type))) {
68 /* TODO: set usage mask more accurately for doubles */
69 info->input_usage_mask[i] = TGSI_WRITEMASK_XYZW;
70 } else {
71 uint8_t mask = nir_ssa_def_components_read(&instr->dest.ssa);
72 info->input_usage_mask[i] |= mask << var->data.location_frac;
73 }
74 }
75 break;
76 }
77 default: {
78 unsigned semantic_name, semantic_index;
79 tgsi_get_gl_varying_semantic(var->data.location, true,
80 &semantic_name, &semantic_index);
81
82 if (semantic_name == TGSI_SEMANTIC_COLOR) {
83 uint8_t mask = nir_ssa_def_components_read(&instr->dest.ssa);
84 info->colors_read |= mask << (semantic_index * 4);
85 }
86 break;
87 }
88 }
89 }
90
91 static void scan_instruction(const struct nir_shader *nir,
92 struct tgsi_shader_info *info,
93 nir_instr *instr)
94 {
95 if (instr->type == nir_instr_type_alu) {
96 nir_alu_instr *alu = nir_instr_as_alu(instr);
97
98 switch (alu->op) {
99 case nir_op_fddx:
100 case nir_op_fddy:
101 case nir_op_fddx_fine:
102 case nir_op_fddy_fine:
103 case nir_op_fddx_coarse:
104 case nir_op_fddy_coarse:
105 info->uses_derivatives = true;
106 break;
107 default:
108 break;
109 }
110 } else if (instr->type == nir_instr_type_tex) {
111 nir_tex_instr *tex = nir_instr_as_tex(instr);
112 nir_variable *texture = tex_get_texture_var(tex);
113
114 if (!texture) {
115 info->samplers_declared |=
116 u_bit_consecutive(tex->sampler_index, 1);
117 } else {
118 if (texture->data.bindless)
119 info->uses_bindless_samplers = true;
120 }
121
122 switch (tex->op) {
123 case nir_texop_tex:
124 case nir_texop_txb:
125 case nir_texop_lod:
126 info->uses_derivatives = true;
127 break;
128 default:
129 break;
130 }
131 } else if (instr->type == nir_instr_type_intrinsic) {
132 nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);
133
134 switch (intr->intrinsic) {
135 case nir_intrinsic_load_front_face:
136 info->uses_frontface = 1;
137 break;
138 case nir_intrinsic_load_instance_id:
139 info->uses_instanceid = 1;
140 break;
141 case nir_intrinsic_load_invocation_id:
142 info->uses_invocationid = true;
143 break;
144 case nir_intrinsic_load_num_work_groups:
145 info->uses_grid_size = true;
146 break;
147 case nir_intrinsic_load_local_group_size:
148 /* The block size is translated to IMM with a fixed block size. */
149 if (info->properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] == 0)
150 info->uses_block_size = true;
151 break;
152 case nir_intrinsic_load_local_invocation_id:
153 case nir_intrinsic_load_work_group_id: {
154 unsigned mask = nir_ssa_def_components_read(&intr->dest.ssa);
155 while (mask) {
156 unsigned i = u_bit_scan(&mask);
157
158 if (intr->intrinsic == nir_intrinsic_load_work_group_id)
159 info->uses_block_id[i] = true;
160 else
161 info->uses_thread_id[i] = true;
162 }
163 break;
164 }
165 case nir_intrinsic_load_vertex_id:
166 info->uses_vertexid = 1;
167 break;
168 case nir_intrinsic_load_vertex_id_zero_base:
169 info->uses_vertexid_nobase = 1;
170 break;
171 case nir_intrinsic_load_base_vertex:
172 info->uses_basevertex = 1;
173 break;
174 case nir_intrinsic_load_primitive_id:
175 info->uses_primid = 1;
176 break;
177 case nir_intrinsic_load_sample_mask_in:
178 info->reads_samplemask = true;
179 break;
180 case nir_intrinsic_load_tess_level_inner:
181 case nir_intrinsic_load_tess_level_outer:
182 info->reads_tess_factors = true;
183 break;
184 case nir_intrinsic_image_deref_load: {
185 nir_variable *var = intrinsic_get_var(intr);
186 if (var->data.bindless) {
187 info->uses_bindless_images = true;
188
189 if (glsl_get_sampler_dim(var->type) == GLSL_SAMPLER_DIM_BUF)
190 info->uses_bindless_buffer_load = true;
191 else
192 info->uses_bindless_image_load = true;
193 }
194 break;
195 }
196 case nir_intrinsic_image_deref_size:
197 case nir_intrinsic_image_deref_samples: {
198 nir_variable *var = intrinsic_get_var(intr);
199 if (var->data.bindless)
200 info->uses_bindless_images = true;
201 break;
202 }
203 case nir_intrinsic_image_deref_store: {
204 const nir_deref_instr *image_deref = nir_instr_as_deref(intr->src[0].ssa->parent_instr);
205 nir_variable *var = intrinsic_get_var(intr);
206 if (var->data.bindless) {
207 info->uses_bindless_images = true;
208
209 if (glsl_get_sampler_dim(image_deref->type) == GLSL_SAMPLER_DIM_BUF)
210 info->uses_bindless_buffer_store = true;
211 else
212 info->uses_bindless_image_store = true;
213 }
214 info->writes_memory = true;
215 break;
216 }
217 case nir_intrinsic_image_deref_atomic_add:
218 case nir_intrinsic_image_deref_atomic_min:
219 case nir_intrinsic_image_deref_atomic_max:
220 case nir_intrinsic_image_deref_atomic_and:
221 case nir_intrinsic_image_deref_atomic_or:
222 case nir_intrinsic_image_deref_atomic_xor:
223 case nir_intrinsic_image_deref_atomic_exchange:
224 case nir_intrinsic_image_deref_atomic_comp_swap: {
225 nir_variable *var = intrinsic_get_var(intr);
226 if (var->data.bindless) {
227 info->uses_bindless_images = true;
228
229 if (glsl_get_sampler_dim(var->type) == GLSL_SAMPLER_DIM_BUF)
230 info->uses_bindless_buffer_atomic = true;
231 else
232 info->uses_bindless_image_atomic = true;
233 }
234 info->writes_memory = true;
235 break;
236 }
237 case nir_intrinsic_store_ssbo:
238 case nir_intrinsic_ssbo_atomic_add:
239 case nir_intrinsic_ssbo_atomic_imin:
240 case nir_intrinsic_ssbo_atomic_umin:
241 case nir_intrinsic_ssbo_atomic_imax:
242 case nir_intrinsic_ssbo_atomic_umax:
243 case nir_intrinsic_ssbo_atomic_and:
244 case nir_intrinsic_ssbo_atomic_or:
245 case nir_intrinsic_ssbo_atomic_xor:
246 case nir_intrinsic_ssbo_atomic_exchange:
247 case nir_intrinsic_ssbo_atomic_comp_swap:
248 info->writes_memory = true;
249 break;
250 case nir_intrinsic_load_deref: {
251 nir_variable *var = intrinsic_get_var(intr);
252 nir_variable_mode mode = var->data.mode;
253 enum glsl_base_type base_type =
254 glsl_get_base_type(glsl_without_array(var->type));
255
256 if (mode == nir_var_shader_in) {
257 gather_intrinsic_load_deref_info(nir, intr, var, info);
258
259 switch (var->data.interpolation) {
260 case INTERP_MODE_NONE:
261 if (glsl_base_type_is_integer(base_type))
262 break;
263
264 /* fall-through */
265 case INTERP_MODE_SMOOTH:
266 if (var->data.sample)
267 info->uses_persp_sample = true;
268 else if (var->data.centroid)
269 info->uses_persp_centroid = true;
270 else
271 info->uses_persp_center = true;
272 break;
273
274 case INTERP_MODE_NOPERSPECTIVE:
275 if (var->data.sample)
276 info->uses_linear_sample = true;
277 else if (var->data.centroid)
278 info->uses_linear_centroid = true;
279 else
280 info->uses_linear_center = true;
281 break;
282 }
283 }
284 break;
285 }
286 case nir_intrinsic_interp_deref_at_centroid:
287 case nir_intrinsic_interp_deref_at_sample:
288 case nir_intrinsic_interp_deref_at_offset: {
289 enum glsl_interp_mode interp = intrinsic_get_var(intr)->data.interpolation;
290 switch (interp) {
291 case INTERP_MODE_SMOOTH:
292 case INTERP_MODE_NONE:
293 if (intr->intrinsic == nir_intrinsic_interp_deref_at_centroid)
294 info->uses_persp_opcode_interp_centroid = true;
295 else if (intr->intrinsic == nir_intrinsic_interp_deref_at_sample)
296 info->uses_persp_opcode_interp_sample = true;
297 else
298 info->uses_persp_opcode_interp_offset = true;
299 break;
300 case INTERP_MODE_NOPERSPECTIVE:
301 if (intr->intrinsic == nir_intrinsic_interp_deref_at_centroid)
302 info->uses_linear_opcode_interp_centroid = true;
303 else if (intr->intrinsic == nir_intrinsic_interp_deref_at_sample)
304 info->uses_linear_opcode_interp_sample = true;
305 else
306 info->uses_linear_opcode_interp_offset = true;
307 break;
308 case INTERP_MODE_FLAT:
309 break;
310 default:
311 unreachable("Unsupported interpoation type");
312 }
313 break;
314 }
315 default:
316 break;
317 }
318 }
319 }
320
321 void si_nir_scan_tess_ctrl(const struct nir_shader *nir,
322 struct tgsi_tessctrl_info *out)
323 {
324 memset(out, 0, sizeof(*out));
325
326 if (nir->info.stage != MESA_SHADER_TESS_CTRL)
327 return;
328
329 out->tessfactors_are_def_in_all_invocs =
330 ac_are_tessfactors_def_in_all_invocs(nir);
331 }
332
333 void si_nir_scan_shader(const struct nir_shader *nir,
334 struct tgsi_shader_info *info)
335 {
336 nir_function *func;
337 unsigned i;
338
339 info->processor = pipe_shader_type_from_mesa(nir->info.stage);
340 info->num_tokens = 2; /* indicate that the shader is non-empty */
341 info->num_instructions = 2;
342
343 info->properties[TGSI_PROPERTY_NEXT_SHADER] =
344 pipe_shader_type_from_mesa(nir->info.next_stage);
345
346 if (nir->info.stage == MESA_SHADER_VERTEX) {
347 info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION] =
348 nir->info.vs.window_space_position;
349 }
350
351 if (nir->info.stage == MESA_SHADER_TESS_CTRL) {
352 info->properties[TGSI_PROPERTY_TCS_VERTICES_OUT] =
353 nir->info.tess.tcs_vertices_out;
354 }
355
356 if (nir->info.stage == MESA_SHADER_TESS_EVAL) {
357 if (nir->info.tess.primitive_mode == GL_ISOLINES)
358 info->properties[TGSI_PROPERTY_TES_PRIM_MODE] = PIPE_PRIM_LINES;
359 else
360 info->properties[TGSI_PROPERTY_TES_PRIM_MODE] = nir->info.tess.primitive_mode;
361
362 STATIC_ASSERT((TESS_SPACING_EQUAL + 1) % 3 == PIPE_TESS_SPACING_EQUAL);
363 STATIC_ASSERT((TESS_SPACING_FRACTIONAL_ODD + 1) % 3 ==
364 PIPE_TESS_SPACING_FRACTIONAL_ODD);
365 STATIC_ASSERT((TESS_SPACING_FRACTIONAL_EVEN + 1) % 3 ==
366 PIPE_TESS_SPACING_FRACTIONAL_EVEN);
367
368 info->properties[TGSI_PROPERTY_TES_SPACING] = (nir->info.tess.spacing + 1) % 3;
369 info->properties[TGSI_PROPERTY_TES_VERTEX_ORDER_CW] = !nir->info.tess.ccw;
370 info->properties[TGSI_PROPERTY_TES_POINT_MODE] = nir->info.tess.point_mode;
371 }
372
373 if (nir->info.stage == MESA_SHADER_GEOMETRY) {
374 info->properties[TGSI_PROPERTY_GS_INPUT_PRIM] = nir->info.gs.input_primitive;
375 info->properties[TGSI_PROPERTY_GS_OUTPUT_PRIM] = nir->info.gs.output_primitive;
376 info->properties[TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES] = nir->info.gs.vertices_out;
377 info->properties[TGSI_PROPERTY_GS_INVOCATIONS] = nir->info.gs.invocations;
378 }
379
380 if (nir->info.stage == MESA_SHADER_FRAGMENT) {
381 info->properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL] =
382 nir->info.fs.early_fragment_tests | nir->info.fs.post_depth_coverage;
383 info->properties[TGSI_PROPERTY_FS_POST_DEPTH_COVERAGE] = nir->info.fs.post_depth_coverage;
384
385 if (nir->info.fs.pixel_center_integer) {
386 info->properties[TGSI_PROPERTY_FS_COORD_PIXEL_CENTER] =
387 TGSI_FS_COORD_PIXEL_CENTER_INTEGER;
388 }
389
390 if (nir->info.fs.depth_layout != FRAG_DEPTH_LAYOUT_NONE) {
391 switch (nir->info.fs.depth_layout) {
392 case FRAG_DEPTH_LAYOUT_ANY:
393 info->properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT] = TGSI_FS_DEPTH_LAYOUT_ANY;
394 break;
395 case FRAG_DEPTH_LAYOUT_GREATER:
396 info->properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT] = TGSI_FS_DEPTH_LAYOUT_GREATER;
397 break;
398 case FRAG_DEPTH_LAYOUT_LESS:
399 info->properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT] = TGSI_FS_DEPTH_LAYOUT_LESS;
400 break;
401 case FRAG_DEPTH_LAYOUT_UNCHANGED:
402 info->properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT] = TGSI_FS_DEPTH_LAYOUT_UNCHANGED;
403 break;
404 default:
405 unreachable("Unknow depth layout");
406 }
407 }
408 }
409
410 if (gl_shader_stage_is_compute(nir->info.stage)) {
411 info->properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] = nir->info.cs.local_size[0];
412 info->properties[TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT] = nir->info.cs.local_size[1];
413 info->properties[TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH] = nir->info.cs.local_size[2];
414 }
415
416 i = 0;
417 uint64_t processed_inputs = 0;
418 unsigned num_inputs = 0;
419 nir_foreach_variable(variable, &nir->inputs) {
420 unsigned semantic_name, semantic_index;
421
422 const struct glsl_type *type = variable->type;
423 if (nir_is_per_vertex_io(variable, nir->info.stage)) {
424 assert(glsl_type_is_array(type));
425 type = glsl_get_array_element(type);
426 }
427
428 unsigned attrib_count = glsl_count_attribute_slots(type,
429 nir->info.stage == MESA_SHADER_VERTEX);
430
431 i = variable->data.driver_location;
432
433 /* Vertex shader inputs don't have semantics. The state
434 * tracker has already mapped them to attributes via
435 * variable->data.driver_location.
436 */
437 if (nir->info.stage == MESA_SHADER_VERTEX) {
438 if (glsl_type_is_dual_slot(glsl_without_array(variable->type)))
439 num_inputs++;
440
441 num_inputs++;
442 continue;
443 }
444
445 /* Fragment shader position is a system value. */
446 if (nir->info.stage == MESA_SHADER_FRAGMENT &&
447 variable->data.location == VARYING_SLOT_POS) {
448 if (nir->info.fs.pixel_center_integer)
449 info->properties[TGSI_PROPERTY_FS_COORD_PIXEL_CENTER] =
450 TGSI_FS_COORD_PIXEL_CENTER_INTEGER;
451
452 num_inputs++;
453 continue;
454 }
455
456 for (unsigned j = 0; j < attrib_count; j++, i++) {
457
458 if (processed_inputs & ((uint64_t)1 << i))
459 continue;
460
461 processed_inputs |= ((uint64_t)1 << i);
462 num_inputs++;
463
464 tgsi_get_gl_varying_semantic(variable->data.location + j, true,
465 &semantic_name, &semantic_index);
466
467 info->input_semantic_name[i] = semantic_name;
468 info->input_semantic_index[i] = semantic_index;
469
470 if (semantic_name == TGSI_SEMANTIC_PRIMID)
471 info->uses_primid = true;
472
473 if (variable->data.sample)
474 info->input_interpolate_loc[i] = TGSI_INTERPOLATE_LOC_SAMPLE;
475 else if (variable->data.centroid)
476 info->input_interpolate_loc[i] = TGSI_INTERPOLATE_LOC_CENTROID;
477 else
478 info->input_interpolate_loc[i] = TGSI_INTERPOLATE_LOC_CENTER;
479
480 enum glsl_base_type base_type =
481 glsl_get_base_type(glsl_without_array(variable->type));
482
483 switch (variable->data.interpolation) {
484 case INTERP_MODE_NONE:
485 if (glsl_base_type_is_integer(base_type)) {
486 info->input_interpolate[i] = TGSI_INTERPOLATE_CONSTANT;
487 break;
488 }
489
490 if (semantic_name == TGSI_SEMANTIC_COLOR) {
491 info->input_interpolate[i] = TGSI_INTERPOLATE_COLOR;
492 break;
493 }
494 /* fall-through */
495
496 case INTERP_MODE_SMOOTH:
497 assert(!glsl_base_type_is_integer(base_type));
498
499 info->input_interpolate[i] = TGSI_INTERPOLATE_PERSPECTIVE;
500 break;
501
502 case INTERP_MODE_NOPERSPECTIVE:
503 assert(!glsl_base_type_is_integer(base_type));
504
505 info->input_interpolate[i] = TGSI_INTERPOLATE_LINEAR;
506 break;
507
508 case INTERP_MODE_FLAT:
509 info->input_interpolate[i] = TGSI_INTERPOLATE_CONSTANT;
510 break;
511 }
512 }
513 }
514
515 info->num_inputs = num_inputs;
516
517
518 i = 0;
519 uint64_t processed_outputs = 0;
520 unsigned num_outputs = 0;
521 nir_foreach_variable(variable, &nir->outputs) {
522 unsigned semantic_name, semantic_index;
523
524 i = variable->data.driver_location;
525
526 const struct glsl_type *type = variable->type;
527 if (nir_is_per_vertex_io(variable, nir->info.stage)) {
528 assert(glsl_type_is_array(type));
529 type = glsl_get_array_element(type);
530 }
531
532 unsigned attrib_count = glsl_count_attribute_slots(type, false);
533 for (unsigned k = 0; k < attrib_count; k++, i++) {
534
535 if (nir->info.stage == MESA_SHADER_FRAGMENT) {
536 tgsi_get_gl_frag_result_semantic(variable->data.location + k,
537 &semantic_name, &semantic_index);
538
539 /* Adjust for dual source blending */
540 if (variable->data.index > 0) {
541 semantic_index++;
542 }
543 } else {
544 tgsi_get_gl_varying_semantic(variable->data.location + k, true,
545 &semantic_name, &semantic_index);
546 }
547
548 unsigned num_components = 4;
549 unsigned vector_elements = glsl_get_vector_elements(glsl_without_array(variable->type));
550 if (vector_elements)
551 num_components = vector_elements;
552
553 unsigned component = variable->data.location_frac;
554 if (glsl_type_is_64bit(glsl_without_array(variable->type))) {
555 if (glsl_type_is_dual_slot(glsl_without_array(variable->type)) && k % 2) {
556 num_components = (num_components * 2) - 4;
557 component = 0;
558 } else {
559 num_components = MIN2(num_components * 2, 4);
560 }
561 }
562
563 ubyte usagemask = 0;
564 for (unsigned j = component; j < num_components + component; j++) {
565 switch (j) {
566 case 0:
567 usagemask |= TGSI_WRITEMASK_X;
568 break;
569 case 1:
570 usagemask |= TGSI_WRITEMASK_Y;
571 break;
572 case 2:
573 usagemask |= TGSI_WRITEMASK_Z;
574 break;
575 case 3:
576 usagemask |= TGSI_WRITEMASK_W;
577 break;
578 default:
579 unreachable("error calculating component index");
580 }
581 }
582
583 unsigned gs_out_streams;
584 if (variable->data.stream & (1u << 31)) {
585 gs_out_streams = variable->data.stream & ~(1u << 31);
586 } else {
587 assert(variable->data.stream < 4);
588 gs_out_streams = 0;
589 for (unsigned j = 0; j < num_components; ++j)
590 gs_out_streams |= variable->data.stream << (2 * (component + j));
591 }
592
593 unsigned streamx = gs_out_streams & 3;
594 unsigned streamy = (gs_out_streams >> 2) & 3;
595 unsigned streamz = (gs_out_streams >> 4) & 3;
596 unsigned streamw = (gs_out_streams >> 6) & 3;
597
598 if (usagemask & TGSI_WRITEMASK_X) {
599 info->output_usagemask[i] |= TGSI_WRITEMASK_X;
600 info->output_streams[i] |= streamx;
601 info->num_stream_output_components[streamx]++;
602 }
603 if (usagemask & TGSI_WRITEMASK_Y) {
604 info->output_usagemask[i] |= TGSI_WRITEMASK_Y;
605 info->output_streams[i] |= streamy << 2;
606 info->num_stream_output_components[streamy]++;
607 }
608 if (usagemask & TGSI_WRITEMASK_Z) {
609 info->output_usagemask[i] |= TGSI_WRITEMASK_Z;
610 info->output_streams[i] |= streamz << 4;
611 info->num_stream_output_components[streamz]++;
612 }
613 if (usagemask & TGSI_WRITEMASK_W) {
614 info->output_usagemask[i] |= TGSI_WRITEMASK_W;
615 info->output_streams[i] |= streamw << 6;
616 info->num_stream_output_components[streamw]++;
617 }
618
619 /* make sure we only count this location once against
620 * the num_outputs counter.
621 */
622 if (processed_outputs & ((uint64_t)1 << i))
623 continue;
624
625 processed_outputs |= ((uint64_t)1 << i);
626 num_outputs++;
627
628 info->output_semantic_name[i] = semantic_name;
629 info->output_semantic_index[i] = semantic_index;
630
631 switch (semantic_name) {
632 case TGSI_SEMANTIC_PRIMID:
633 info->writes_primid = true;
634 break;
635 case TGSI_SEMANTIC_VIEWPORT_INDEX:
636 info->writes_viewport_index = true;
637 break;
638 case TGSI_SEMANTIC_LAYER:
639 info->writes_layer = true;
640 break;
641 case TGSI_SEMANTIC_PSIZE:
642 info->writes_psize = true;
643 break;
644 case TGSI_SEMANTIC_CLIPVERTEX:
645 info->writes_clipvertex = true;
646 break;
647 case TGSI_SEMANTIC_COLOR:
648 info->colors_written |= 1 << semantic_index;
649 break;
650 case TGSI_SEMANTIC_STENCIL:
651 info->writes_stencil = true;
652 break;
653 case TGSI_SEMANTIC_SAMPLEMASK:
654 info->writes_samplemask = true;
655 break;
656 case TGSI_SEMANTIC_EDGEFLAG:
657 info->writes_edgeflag = true;
658 break;
659 case TGSI_SEMANTIC_POSITION:
660 if (info->processor == PIPE_SHADER_FRAGMENT)
661 info->writes_z = true;
662 else
663 info->writes_position = true;
664 break;
665 }
666
667 if (nir->info.stage == MESA_SHADER_TESS_CTRL) {
668 switch (semantic_name) {
669 case TGSI_SEMANTIC_PATCH:
670 info->reads_perpatch_outputs = true;
671 break;
672 case TGSI_SEMANTIC_TESSINNER:
673 case TGSI_SEMANTIC_TESSOUTER:
674 info->reads_tessfactor_outputs = true;
675 break;
676 default:
677 info->reads_pervertex_outputs = true;
678 }
679 }
680 }
681
682 unsigned loc = variable->data.location;
683 if (nir->info.stage == MESA_SHADER_FRAGMENT &&
684 loc == FRAG_RESULT_COLOR &&
685 nir->info.outputs_written & (1ull << loc)) {
686 assert(attrib_count == 1);
687 info->properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS] = true;
688 }
689 }
690
691 info->num_outputs = num_outputs;
692
693 struct set *ubo_set = _mesa_set_create(NULL, _mesa_hash_pointer,
694 _mesa_key_pointer_equal);
695 struct set *ssbo_set = _mesa_set_create(NULL, _mesa_hash_pointer,
696 _mesa_key_pointer_equal);
697
698 /* Intialise const_file_max[0] */
699 info->const_file_max[0] = -1;
700
701 /* The first 8 are reserved for atomic counters using ssbo */
702 unsigned ssbo_idx = 8;
703
704 unsigned ubo_idx = 1;
705 nir_foreach_variable(variable, &nir->uniforms) {
706 const struct glsl_type *type = variable->type;
707 enum glsl_base_type base_type =
708 glsl_get_base_type(glsl_without_array(type));
709 unsigned aoa_size = MAX2(1, glsl_get_aoa_size(type));
710 unsigned loc = variable->data.location;
711 int slot_count = glsl_count_attribute_slots(type, false);
712 int max_slot = MAX2(info->const_file_max[0], (int) loc) + slot_count;
713
714 /* Gather buffers declared bitmasks. Note: radeonsi doesn't
715 * really use the mask (other than ubo_idx == 1 for regular
716 * uniforms) its really only used for getting the buffer count
717 * so we don't need to worry about the ordering.
718 */
719 if (variable->interface_type != NULL) {
720 if (variable->data.mode == nir_var_uniform ||
721 variable->data.mode == nir_var_mem_ubo ||
722 variable->data.mode == nir_var_mem_ssbo) {
723
724 struct set *buf_set = variable->data.mode == nir_var_mem_ssbo ?
725 ssbo_set : ubo_set;
726
727 unsigned block_count;
728 if (base_type != GLSL_TYPE_INTERFACE) {
729 struct set_entry *entry =
730 _mesa_set_search(buf_set, variable->interface_type);
731
732 /* Check if we have already processed
733 * a member from this ubo.
734 */
735 if (entry)
736 continue;
737
738 block_count = 1;
739 } else {
740 block_count = aoa_size;
741 }
742
743 if (variable->data.mode == nir_var_uniform ||
744 variable->data.mode == nir_var_mem_ubo) {
745 info->const_buffers_declared |= u_bit_consecutive(ubo_idx, block_count);
746 ubo_idx += block_count;
747 } else {
748 assert(variable->data.mode == nir_var_mem_ssbo);
749
750 info->shader_buffers_declared |= u_bit_consecutive(ssbo_idx, block_count);
751 ssbo_idx += block_count;
752 }
753
754 _mesa_set_add(buf_set, variable->interface_type);
755 }
756
757 continue;
758 }
759
760 /* We rely on the fact that nir_lower_samplers_as_deref has
761 * eliminated struct dereferences.
762 */
763 if (base_type == GLSL_TYPE_SAMPLER) {
764 if (variable->data.bindless) {
765 info->const_buffers_declared |= 1;
766 info->const_file_max[0] = max_slot;
767 } else {
768 info->samplers_declared |=
769 u_bit_consecutive(variable->data.binding, aoa_size);
770 }
771 } else if (base_type == GLSL_TYPE_IMAGE) {
772 if (variable->data.bindless) {
773 info->const_buffers_declared |= 1;
774 info->const_file_max[0] = max_slot;
775 } else {
776 info->images_declared |=
777 u_bit_consecutive(variable->data.binding, aoa_size);
778 }
779 } else if (base_type != GLSL_TYPE_ATOMIC_UINT) {
780 if (strncmp(variable->name, "state.", 6) == 0 ||
781 strncmp(variable->name, "gl_", 3) == 0) {
782 /* FIXME: figure out why piglit tests with builtin
783 * uniforms are failing without this.
784 */
785 info->const_buffers_declared =
786 u_bit_consecutive(0, SI_NUM_CONST_BUFFERS);
787 } else {
788 info->const_buffers_declared |= 1;
789 info->const_file_max[0] = max_slot;
790 }
791 }
792 }
793
794 _mesa_set_destroy(ubo_set, NULL);
795 _mesa_set_destroy(ssbo_set, NULL);
796
797 info->num_written_clipdistance = nir->info.clip_distance_array_size;
798 info->num_written_culldistance = nir->info.cull_distance_array_size;
799 info->clipdist_writemask = u_bit_consecutive(0, info->num_written_clipdistance);
800 info->culldist_writemask = u_bit_consecutive(0, info->num_written_culldistance);
801
802 if (info->processor == PIPE_SHADER_FRAGMENT)
803 info->uses_kill = nir->info.fs.uses_discard;
804
805 func = (struct nir_function *)exec_list_get_head_const(&nir->functions);
806 nir_foreach_block(block, func->impl) {
807 nir_foreach_instr(instr, block)
808 scan_instruction(nir, info, instr);
809 }
810 }
811
812 /**
813 * Perform "lowering" operations on the NIR that are run once when the shader
814 * selector is created.
815 */
816 void
817 si_lower_nir(struct si_shader_selector* sel)
818 {
819 /* Adjust the driver location of inputs and outputs. The state tracker
820 * interprets them as slots, while the ac/nir backend interprets them
821 * as individual components.
822 */
823 nir_foreach_variable(variable, &sel->nir->inputs)
824 variable->data.driver_location *= 4;
825
826 nir_foreach_variable(variable, &sel->nir->outputs) {
827 variable->data.driver_location *= 4;
828
829 if (sel->nir->info.stage == MESA_SHADER_FRAGMENT) {
830 if (variable->data.location == FRAG_RESULT_DEPTH)
831 variable->data.driver_location += 2;
832 else if (variable->data.location == FRAG_RESULT_STENCIL)
833 variable->data.driver_location += 1;
834 }
835 }
836
837 /* Perform lowerings (and optimizations) of code.
838 *
839 * Performance considerations aside, we must:
840 * - lower certain ALU operations
841 * - ensure constant offsets for texture instructions are folded
842 * and copy-propagated
843 */
844 NIR_PASS_V(sel->nir, nir_lower_vars_to_ssa);
845 NIR_PASS_V(sel->nir, nir_lower_alu_to_scalar);
846 NIR_PASS_V(sel->nir, nir_lower_phis_to_scalar);
847
848 static const struct nir_lower_tex_options lower_tex_options = {
849 .lower_txp = ~0u,
850 };
851 NIR_PASS_V(sel->nir, nir_lower_tex, &lower_tex_options);
852
853 const nir_lower_subgroups_options subgroups_options = {
854 .subgroup_size = 64,
855 .ballot_bit_size = 64,
856 .lower_to_scalar = true,
857 .lower_subgroup_masks = true,
858 .lower_vote_trivial = false,
859 .lower_vote_eq_to_ballot = true,
860 };
861 NIR_PASS_V(sel->nir, nir_lower_subgroups, &subgroups_options);
862
863 ac_lower_indirect_derefs(sel->nir, sel->screen->info.chip_class);
864
865 bool progress;
866 do {
867 progress = false;
868
869 /* (Constant) copy propagation is needed for txf with offsets. */
870 NIR_PASS(progress, sel->nir, nir_copy_prop);
871 NIR_PASS(progress, sel->nir, nir_opt_remove_phis);
872 NIR_PASS(progress, sel->nir, nir_opt_dce);
873 if (nir_opt_trivial_continues(sel->nir)) {
874 progress = true;
875 NIR_PASS(progress, sel->nir, nir_copy_prop);
876 NIR_PASS(progress, sel->nir, nir_opt_dce);
877 }
878 NIR_PASS(progress, sel->nir, nir_opt_if);
879 NIR_PASS(progress, sel->nir, nir_opt_dead_cf);
880 NIR_PASS(progress, sel->nir, nir_opt_cse);
881 NIR_PASS(progress, sel->nir, nir_opt_peephole_select, 8, true, true);
882
883 /* Needed for algebraic lowering */
884 NIR_PASS(progress, sel->nir, nir_opt_algebraic);
885 NIR_PASS(progress, sel->nir, nir_opt_constant_folding);
886
887 NIR_PASS(progress, sel->nir, nir_opt_undef);
888 NIR_PASS(progress, sel->nir, nir_opt_conditional_discard);
889 if (sel->nir->options->max_unroll_iterations) {
890 NIR_PASS(progress, sel->nir, nir_opt_loop_unroll, 0);
891 }
892 } while (progress);
893
894 NIR_PASS_V(sel->nir, nir_lower_bool_to_int32);
895
896 /* Strip the resulting shader so that the shader cache is more likely
897 * to hit from other similar shaders.
898 */
899 nir_strip(sel->nir);
900 }
901
902 static void declare_nir_input_vs(struct si_shader_context *ctx,
903 struct nir_variable *variable,
904 unsigned input_index,
905 LLVMValueRef out[4])
906 {
907 si_llvm_load_input_vs(ctx, input_index, out);
908 }
909
910 static void declare_nir_input_fs(struct si_shader_context *ctx,
911 struct nir_variable *variable,
912 unsigned input_index,
913 LLVMValueRef out[4])
914 {
915 unsigned slot = variable->data.location;
916 if (slot == VARYING_SLOT_POS) {
917 out[0] = LLVMGetParam(ctx->main_fn, SI_PARAM_POS_X_FLOAT);
918 out[1] = LLVMGetParam(ctx->main_fn, SI_PARAM_POS_Y_FLOAT);
919 out[2] = LLVMGetParam(ctx->main_fn, SI_PARAM_POS_Z_FLOAT);
920 out[3] = ac_build_fdiv(&ctx->ac, ctx->ac.f32_1,
921 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_W_FLOAT));
922 return;
923 }
924
925 si_llvm_load_input_fs(ctx, input_index, out);
926 }
927
928 LLVMValueRef
929 si_nir_lookup_interp_param(struct ac_shader_abi *abi,
930 enum glsl_interp_mode interp, unsigned location)
931 {
932 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
933 int interp_param_idx = -1;
934
935 switch (interp) {
936 case INTERP_MODE_FLAT:
937 return NULL;
938 case INTERP_MODE_SMOOTH:
939 case INTERP_MODE_NONE:
940 if (location == INTERP_CENTER)
941 interp_param_idx = SI_PARAM_PERSP_CENTER;
942 else if (location == INTERP_CENTROID)
943 interp_param_idx = SI_PARAM_PERSP_CENTROID;
944 else if (location == INTERP_SAMPLE)
945 interp_param_idx = SI_PARAM_PERSP_SAMPLE;
946 break;
947 case INTERP_MODE_NOPERSPECTIVE:
948 if (location == INTERP_CENTER)
949 interp_param_idx = SI_PARAM_LINEAR_CENTER;
950 else if (location == INTERP_CENTROID)
951 interp_param_idx = SI_PARAM_LINEAR_CENTROID;
952 else if (location == INTERP_SAMPLE)
953 interp_param_idx = SI_PARAM_LINEAR_SAMPLE;
954 break;
955 default:
956 assert(!"Unhandled interpolation mode.");
957 return NULL;
958 }
959
960 return interp_param_idx != -1 ?
961 LLVMGetParam(ctx->main_fn, interp_param_idx) : NULL;
962 }
963
964 static LLVMValueRef
965 si_nir_load_sampler_desc(struct ac_shader_abi *abi,
966 unsigned descriptor_set, unsigned base_index,
967 unsigned constant_index, LLVMValueRef dynamic_index,
968 enum ac_descriptor_type desc_type, bool image,
969 bool write, bool bindless)
970 {
971 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
972 const struct tgsi_shader_info *info = &ctx->shader->selector->info;
973 LLVMBuilderRef builder = ctx->ac.builder;
974 unsigned const_index = base_index + constant_index;
975 bool dcc_off = write;
976
977 /* TODO: images_store and images_atomic are not set */
978 if (!dynamic_index && image &&
979 (info->images_store | info->images_atomic) & (1 << const_index))
980 dcc_off = true;
981
982 assert(!descriptor_set);
983 assert(!image || desc_type == AC_DESC_IMAGE || desc_type == AC_DESC_BUFFER);
984
985 if (bindless) {
986 LLVMValueRef list =
987 LLVMGetParam(ctx->main_fn, ctx->param_bindless_samplers_and_images);
988
989 /* dynamic_index is the bindless handle */
990 if (image) {
991 /* For simplicity, bindless image descriptors use fixed
992 * 16-dword slots for now.
993 */
994 dynamic_index = LLVMBuildMul(ctx->ac.builder, dynamic_index,
995 LLVMConstInt(ctx->i32, 2, 0), "");
996
997 return si_load_image_desc(ctx, list, dynamic_index, desc_type,
998 dcc_off, true);
999 }
1000
1001 /* Since bindless handle arithmetic can contain an unsigned integer
1002 * wraparound and si_load_sampler_desc assumes there isn't any,
1003 * use GEP without "inbounds" (inside ac_build_pointer_add)
1004 * to prevent incorrect code generation and hangs.
1005 */
1006 dynamic_index = LLVMBuildMul(ctx->ac.builder, dynamic_index,
1007 LLVMConstInt(ctx->i32, 2, 0), "");
1008 list = ac_build_pointer_add(&ctx->ac, list, dynamic_index);
1009 return si_load_sampler_desc(ctx, list, ctx->i32_0, desc_type);
1010 }
1011
1012 unsigned num_slots = image ? ctx->num_images : ctx->num_samplers;
1013 assert(const_index < num_slots);
1014
1015 LLVMValueRef list = LLVMGetParam(ctx->main_fn, ctx->param_samplers_and_images);
1016 LLVMValueRef index = LLVMConstInt(ctx->ac.i32, const_index, false);
1017
1018 if (dynamic_index) {
1019 index = LLVMBuildAdd(builder, index, dynamic_index, "");
1020
1021 /* From the GL_ARB_shader_image_load_store extension spec:
1022 *
1023 * If a shader performs an image load, store, or atomic
1024 * operation using an image variable declared as an array,
1025 * and if the index used to select an individual element is
1026 * negative or greater than or equal to the size of the
1027 * array, the results of the operation are undefined but may
1028 * not lead to termination.
1029 */
1030 index = si_llvm_bound_index(ctx, index, num_slots);
1031 }
1032
1033 if (image) {
1034 index = LLVMBuildSub(ctx->ac.builder,
1035 LLVMConstInt(ctx->i32, SI_NUM_IMAGES - 1, 0),
1036 index, "");
1037 return si_load_image_desc(ctx, list, index, desc_type, dcc_off, false);
1038 }
1039
1040 index = LLVMBuildAdd(ctx->ac.builder, index,
1041 LLVMConstInt(ctx->i32, SI_NUM_IMAGES / 2, 0), "");
1042 return si_load_sampler_desc(ctx, list, index, desc_type);
1043 }
1044
1045 static void bitcast_inputs(struct si_shader_context *ctx,
1046 LLVMValueRef data[4],
1047 unsigned input_idx)
1048 {
1049 for (unsigned chan = 0; chan < 4; chan++) {
1050 ctx->inputs[input_idx + chan] =
1051 LLVMBuildBitCast(ctx->ac.builder, data[chan], ctx->ac.i32, "");
1052 }
1053 }
1054
1055 bool si_nir_build_llvm(struct si_shader_context *ctx, struct nir_shader *nir)
1056 {
1057 struct tgsi_shader_info *info = &ctx->shader->selector->info;
1058
1059 if (nir->info.stage == MESA_SHADER_VERTEX ||
1060 nir->info.stage == MESA_SHADER_FRAGMENT) {
1061 uint64_t processed_inputs = 0;
1062 nir_foreach_variable(variable, &nir->inputs) {
1063 unsigned attrib_count = glsl_count_attribute_slots(variable->type,
1064 nir->info.stage == MESA_SHADER_VERTEX);
1065 unsigned input_idx = variable->data.driver_location;
1066
1067 LLVMValueRef data[4];
1068 unsigned loc = variable->data.location;
1069
1070 if (loc >= VARYING_SLOT_VAR0 && nir->info.stage == MESA_SHADER_FRAGMENT)
1071 ctx->abi.fs_input_attr_indices[loc - VARYING_SLOT_VAR0] = input_idx / 4;
1072
1073 for (unsigned i = 0; i < attrib_count; i++) {
1074 /* Packed components share the same location so skip
1075 * them if we have already processed the location.
1076 */
1077 if (processed_inputs & ((uint64_t)1 << (loc + i))) {
1078 input_idx += 4;
1079 continue;
1080 }
1081
1082 if (nir->info.stage == MESA_SHADER_VERTEX) {
1083 declare_nir_input_vs(ctx, variable, input_idx / 4, data);
1084 bitcast_inputs(ctx, data, input_idx);
1085 if (glsl_type_is_dual_slot(variable->type)) {
1086 input_idx += 4;
1087 declare_nir_input_vs(ctx, variable, input_idx / 4, data);
1088 bitcast_inputs(ctx, data, input_idx);
1089 }
1090 } else if (nir->info.stage == MESA_SHADER_FRAGMENT) {
1091 declare_nir_input_fs(ctx, variable, input_idx / 4, data);
1092 bitcast_inputs(ctx, data, input_idx);
1093 }
1094
1095 processed_inputs |= ((uint64_t)1 << (loc + i));
1096 input_idx += 4;
1097 }
1098 }
1099 }
1100
1101 ctx->abi.inputs = &ctx->inputs[0];
1102 ctx->abi.load_sampler_desc = si_nir_load_sampler_desc;
1103 ctx->abi.clamp_shadow_reference = true;
1104
1105 ctx->num_samplers = util_last_bit(info->samplers_declared);
1106 ctx->num_images = util_last_bit(info->images_declared);
1107
1108 if (ctx->shader->selector->info.properties[TGSI_PROPERTY_CS_LOCAL_SIZE]) {
1109 assert(gl_shader_stage_is_compute(nir->info.stage));
1110 si_declare_compute_memory(ctx);
1111 }
1112 ac_nir_translate(&ctx->ac, &ctx->abi, nir);
1113
1114 return true;
1115 }