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radeonsi/nir: set tgsi_shader_info::uses_fbfetch for KHR_blend_equation_adv.
[mesa.git] / src / gallium / drivers / radeonsi / si_shader_nir.c
1 /*
2 * Copyright 2017 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 #include "si_shader_internal.h"
26 #include "si_pipe.h"
27
28 #include "ac_nir_to_llvm.h"
29
30 #include "tgsi/tgsi_from_mesa.h"
31
32 #include "compiler/nir/nir.h"
33 #include "compiler/nir_types.h"
34 #include "compiler/nir/nir_builder.h"
35
36 static nir_variable* tex_get_texture_var(nir_tex_instr *instr)
37 {
38 for (unsigned i = 0; i < instr->num_srcs; i++) {
39 switch (instr->src[i].src_type) {
40 case nir_tex_src_texture_deref:
41 return nir_deref_instr_get_variable(nir_src_as_deref(instr->src[i].src));
42 default:
43 break;
44 }
45 }
46
47 return NULL;
48 }
49
50 static nir_variable* intrinsic_get_var(nir_intrinsic_instr *instr)
51 {
52 return nir_deref_instr_get_variable(nir_src_as_deref(instr->src[0]));
53 }
54
55 static void gather_intrinsic_load_deref_input_info(const nir_shader *nir,
56 const nir_intrinsic_instr *instr,
57 nir_variable *var,
58 struct tgsi_shader_info *info)
59 {
60 assert(var && var->data.mode == nir_var_shader_in);
61
62 switch (nir->info.stage) {
63 case MESA_SHADER_VERTEX: {
64 unsigned i = var->data.driver_location;
65 unsigned attrib_count = glsl_count_attribute_slots(var->type, false);
66
67 for (unsigned j = 0; j < attrib_count; j++, i++) {
68 if (glsl_type_is_64bit(glsl_without_array(var->type))) {
69 /* TODO: set usage mask more accurately for doubles */
70 info->input_usage_mask[i] = TGSI_WRITEMASK_XYZW;
71 } else {
72 uint8_t mask = nir_ssa_def_components_read(&instr->dest.ssa);
73 info->input_usage_mask[i] |= mask << var->data.location_frac;
74 }
75 }
76 break;
77 }
78 default: {
79 unsigned semantic_name, semantic_index;
80 tgsi_get_gl_varying_semantic(var->data.location, true,
81 &semantic_name, &semantic_index);
82
83 if (semantic_name == TGSI_SEMANTIC_COLOR) {
84 uint8_t mask = nir_ssa_def_components_read(&instr->dest.ssa);
85 info->colors_read |= mask << (semantic_index * 4);
86 }
87 break;
88 }
89 }
90 }
91
92 static void gather_intrinsic_load_deref_output_info(const nir_shader *nir,
93 const nir_intrinsic_instr *instr,
94 nir_variable *var,
95 struct tgsi_shader_info *info)
96 {
97 assert(var && var->data.mode == nir_var_shader_out);
98
99 switch (nir->info.stage) {
100 case MESA_SHADER_FRAGMENT:
101 if (var->data.fb_fetch_output)
102 info->uses_fbfetch = true;
103 break;
104 default:;
105 }
106 }
107
108 static void scan_instruction(const struct nir_shader *nir,
109 struct tgsi_shader_info *info,
110 nir_instr *instr)
111 {
112 if (instr->type == nir_instr_type_alu) {
113 nir_alu_instr *alu = nir_instr_as_alu(instr);
114
115 switch (alu->op) {
116 case nir_op_fddx:
117 case nir_op_fddy:
118 case nir_op_fddx_fine:
119 case nir_op_fddy_fine:
120 case nir_op_fddx_coarse:
121 case nir_op_fddy_coarse:
122 info->uses_derivatives = true;
123 break;
124 default:
125 break;
126 }
127 } else if (instr->type == nir_instr_type_tex) {
128 nir_tex_instr *tex = nir_instr_as_tex(instr);
129 nir_variable *texture = tex_get_texture_var(tex);
130
131 if (!texture) {
132 info->samplers_declared |=
133 u_bit_consecutive(tex->sampler_index, 1);
134 } else {
135 if (texture->data.bindless)
136 info->uses_bindless_samplers = true;
137 }
138
139 switch (tex->op) {
140 case nir_texop_tex:
141 case nir_texop_txb:
142 case nir_texop_lod:
143 info->uses_derivatives = true;
144 break;
145 default:
146 break;
147 }
148 } else if (instr->type == nir_instr_type_intrinsic) {
149 nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);
150
151 switch (intr->intrinsic) {
152 case nir_intrinsic_load_front_face:
153 info->uses_frontface = 1;
154 break;
155 case nir_intrinsic_load_instance_id:
156 info->uses_instanceid = 1;
157 break;
158 case nir_intrinsic_load_invocation_id:
159 info->uses_invocationid = true;
160 break;
161 case nir_intrinsic_load_num_work_groups:
162 info->uses_grid_size = true;
163 break;
164 case nir_intrinsic_load_local_group_size:
165 /* The block size is translated to IMM with a fixed block size. */
166 if (info->properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] == 0)
167 info->uses_block_size = true;
168 break;
169 case nir_intrinsic_load_local_invocation_id:
170 case nir_intrinsic_load_work_group_id: {
171 unsigned mask = nir_ssa_def_components_read(&intr->dest.ssa);
172 while (mask) {
173 unsigned i = u_bit_scan(&mask);
174
175 if (intr->intrinsic == nir_intrinsic_load_work_group_id)
176 info->uses_block_id[i] = true;
177 else
178 info->uses_thread_id[i] = true;
179 }
180 break;
181 }
182 case nir_intrinsic_load_vertex_id:
183 info->uses_vertexid = 1;
184 break;
185 case nir_intrinsic_load_vertex_id_zero_base:
186 info->uses_vertexid_nobase = 1;
187 break;
188 case nir_intrinsic_load_base_vertex:
189 info->uses_basevertex = 1;
190 break;
191 case nir_intrinsic_load_draw_id:
192 info->uses_drawid = 1;
193 break;
194 case nir_intrinsic_load_primitive_id:
195 info->uses_primid = 1;
196 break;
197 case nir_intrinsic_load_sample_mask_in:
198 info->reads_samplemask = true;
199 break;
200 case nir_intrinsic_load_tess_level_inner:
201 case nir_intrinsic_load_tess_level_outer:
202 info->reads_tess_factors = true;
203 break;
204 case nir_intrinsic_bindless_image_load:
205 info->uses_bindless_images = true;
206
207 if (nir_intrinsic_image_dim(intr) == GLSL_SAMPLER_DIM_BUF)
208 info->uses_bindless_buffer_load = true;
209 else
210 info->uses_bindless_image_load = true;
211 break;
212 case nir_intrinsic_bindless_image_size:
213 case nir_intrinsic_bindless_image_samples:
214 info->uses_bindless_images = true;
215 break;
216 case nir_intrinsic_bindless_image_store:
217 info->uses_bindless_images = true;
218
219 if (nir_intrinsic_image_dim(intr) == GLSL_SAMPLER_DIM_BUF)
220 info->uses_bindless_buffer_store = true;
221 else
222 info->uses_bindless_image_store = true;
223
224 info->writes_memory = true;
225 break;
226 case nir_intrinsic_image_deref_store:
227 info->writes_memory = true;
228 break;
229 case nir_intrinsic_bindless_image_atomic_add:
230 case nir_intrinsic_bindless_image_atomic_min:
231 case nir_intrinsic_bindless_image_atomic_max:
232 case nir_intrinsic_bindless_image_atomic_and:
233 case nir_intrinsic_bindless_image_atomic_or:
234 case nir_intrinsic_bindless_image_atomic_xor:
235 case nir_intrinsic_bindless_image_atomic_exchange:
236 case nir_intrinsic_bindless_image_atomic_comp_swap:
237 info->uses_bindless_images = true;
238
239 if (nir_intrinsic_image_dim(intr) == GLSL_SAMPLER_DIM_BUF)
240 info->uses_bindless_buffer_atomic = true;
241 else
242 info->uses_bindless_image_atomic = true;
243
244 info->writes_memory = true;
245 break;
246 case nir_intrinsic_image_deref_atomic_add:
247 case nir_intrinsic_image_deref_atomic_min:
248 case nir_intrinsic_image_deref_atomic_max:
249 case nir_intrinsic_image_deref_atomic_and:
250 case nir_intrinsic_image_deref_atomic_or:
251 case nir_intrinsic_image_deref_atomic_xor:
252 case nir_intrinsic_image_deref_atomic_exchange:
253 case nir_intrinsic_image_deref_atomic_comp_swap:
254 info->writes_memory = true;
255 break;
256 case nir_intrinsic_store_ssbo:
257 case nir_intrinsic_ssbo_atomic_add:
258 case nir_intrinsic_ssbo_atomic_imin:
259 case nir_intrinsic_ssbo_atomic_umin:
260 case nir_intrinsic_ssbo_atomic_imax:
261 case nir_intrinsic_ssbo_atomic_umax:
262 case nir_intrinsic_ssbo_atomic_and:
263 case nir_intrinsic_ssbo_atomic_or:
264 case nir_intrinsic_ssbo_atomic_xor:
265 case nir_intrinsic_ssbo_atomic_exchange:
266 case nir_intrinsic_ssbo_atomic_comp_swap:
267 info->writes_memory = true;
268 break;
269 case nir_intrinsic_load_deref: {
270 nir_variable *var = intrinsic_get_var(intr);
271 nir_variable_mode mode = var->data.mode;
272 enum glsl_base_type base_type =
273 glsl_get_base_type(glsl_without_array(var->type));
274
275 if (mode == nir_var_shader_in) {
276 gather_intrinsic_load_deref_input_info(nir, intr, var, info);
277
278 switch (var->data.interpolation) {
279 case INTERP_MODE_NONE:
280 if (glsl_base_type_is_integer(base_type))
281 break;
282
283 /* fall-through */
284 case INTERP_MODE_SMOOTH:
285 if (var->data.sample)
286 info->uses_persp_sample = true;
287 else if (var->data.centroid)
288 info->uses_persp_centroid = true;
289 else
290 info->uses_persp_center = true;
291 break;
292
293 case INTERP_MODE_NOPERSPECTIVE:
294 if (var->data.sample)
295 info->uses_linear_sample = true;
296 else if (var->data.centroid)
297 info->uses_linear_centroid = true;
298 else
299 info->uses_linear_center = true;
300 break;
301 }
302 } else if (mode == nir_var_shader_out) {
303 gather_intrinsic_load_deref_output_info(nir, intr, var, info);
304 }
305 break;
306 }
307 case nir_intrinsic_interp_deref_at_centroid:
308 case nir_intrinsic_interp_deref_at_sample:
309 case nir_intrinsic_interp_deref_at_offset: {
310 enum glsl_interp_mode interp = intrinsic_get_var(intr)->data.interpolation;
311 switch (interp) {
312 case INTERP_MODE_SMOOTH:
313 case INTERP_MODE_NONE:
314 if (intr->intrinsic == nir_intrinsic_interp_deref_at_centroid)
315 info->uses_persp_opcode_interp_centroid = true;
316 else if (intr->intrinsic == nir_intrinsic_interp_deref_at_sample)
317 info->uses_persp_opcode_interp_sample = true;
318 else
319 info->uses_persp_opcode_interp_offset = true;
320 break;
321 case INTERP_MODE_NOPERSPECTIVE:
322 if (intr->intrinsic == nir_intrinsic_interp_deref_at_centroid)
323 info->uses_linear_opcode_interp_centroid = true;
324 else if (intr->intrinsic == nir_intrinsic_interp_deref_at_sample)
325 info->uses_linear_opcode_interp_sample = true;
326 else
327 info->uses_linear_opcode_interp_offset = true;
328 break;
329 case INTERP_MODE_FLAT:
330 break;
331 default:
332 unreachable("Unsupported interpoation type");
333 }
334 break;
335 }
336 default:
337 break;
338 }
339 }
340 }
341
342 void si_nir_scan_tess_ctrl(const struct nir_shader *nir,
343 struct tgsi_tessctrl_info *out)
344 {
345 memset(out, 0, sizeof(*out));
346
347 if (nir->info.stage != MESA_SHADER_TESS_CTRL)
348 return;
349
350 out->tessfactors_are_def_in_all_invocs =
351 ac_are_tessfactors_def_in_all_invocs(nir);
352 }
353
354 void si_nir_scan_shader(const struct nir_shader *nir,
355 struct tgsi_shader_info *info)
356 {
357 nir_function *func;
358 unsigned i;
359
360 info->processor = pipe_shader_type_from_mesa(nir->info.stage);
361 info->num_tokens = 2; /* indicate that the shader is non-empty */
362 info->num_instructions = 2;
363
364 info->properties[TGSI_PROPERTY_NEXT_SHADER] =
365 pipe_shader_type_from_mesa(nir->info.next_stage);
366
367 if (nir->info.stage == MESA_SHADER_VERTEX) {
368 info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION] =
369 nir->info.vs.window_space_position;
370 }
371
372 if (nir->info.stage == MESA_SHADER_TESS_CTRL) {
373 info->properties[TGSI_PROPERTY_TCS_VERTICES_OUT] =
374 nir->info.tess.tcs_vertices_out;
375 }
376
377 if (nir->info.stage == MESA_SHADER_TESS_EVAL) {
378 if (nir->info.tess.primitive_mode == GL_ISOLINES)
379 info->properties[TGSI_PROPERTY_TES_PRIM_MODE] = PIPE_PRIM_LINES;
380 else
381 info->properties[TGSI_PROPERTY_TES_PRIM_MODE] = nir->info.tess.primitive_mode;
382
383 STATIC_ASSERT((TESS_SPACING_EQUAL + 1) % 3 == PIPE_TESS_SPACING_EQUAL);
384 STATIC_ASSERT((TESS_SPACING_FRACTIONAL_ODD + 1) % 3 ==
385 PIPE_TESS_SPACING_FRACTIONAL_ODD);
386 STATIC_ASSERT((TESS_SPACING_FRACTIONAL_EVEN + 1) % 3 ==
387 PIPE_TESS_SPACING_FRACTIONAL_EVEN);
388
389 info->properties[TGSI_PROPERTY_TES_SPACING] = (nir->info.tess.spacing + 1) % 3;
390 info->properties[TGSI_PROPERTY_TES_VERTEX_ORDER_CW] = !nir->info.tess.ccw;
391 info->properties[TGSI_PROPERTY_TES_POINT_MODE] = nir->info.tess.point_mode;
392 }
393
394 if (nir->info.stage == MESA_SHADER_GEOMETRY) {
395 info->properties[TGSI_PROPERTY_GS_INPUT_PRIM] = nir->info.gs.input_primitive;
396 info->properties[TGSI_PROPERTY_GS_OUTPUT_PRIM] = nir->info.gs.output_primitive;
397 info->properties[TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES] = nir->info.gs.vertices_out;
398 info->properties[TGSI_PROPERTY_GS_INVOCATIONS] = nir->info.gs.invocations;
399 }
400
401 if (nir->info.stage == MESA_SHADER_FRAGMENT) {
402 info->properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL] =
403 nir->info.fs.early_fragment_tests | nir->info.fs.post_depth_coverage;
404 info->properties[TGSI_PROPERTY_FS_POST_DEPTH_COVERAGE] = nir->info.fs.post_depth_coverage;
405
406 if (nir->info.fs.pixel_center_integer) {
407 info->properties[TGSI_PROPERTY_FS_COORD_PIXEL_CENTER] =
408 TGSI_FS_COORD_PIXEL_CENTER_INTEGER;
409 }
410
411 if (nir->info.fs.depth_layout != FRAG_DEPTH_LAYOUT_NONE) {
412 switch (nir->info.fs.depth_layout) {
413 case FRAG_DEPTH_LAYOUT_ANY:
414 info->properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT] = TGSI_FS_DEPTH_LAYOUT_ANY;
415 break;
416 case FRAG_DEPTH_LAYOUT_GREATER:
417 info->properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT] = TGSI_FS_DEPTH_LAYOUT_GREATER;
418 break;
419 case FRAG_DEPTH_LAYOUT_LESS:
420 info->properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT] = TGSI_FS_DEPTH_LAYOUT_LESS;
421 break;
422 case FRAG_DEPTH_LAYOUT_UNCHANGED:
423 info->properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT] = TGSI_FS_DEPTH_LAYOUT_UNCHANGED;
424 break;
425 default:
426 unreachable("Unknow depth layout");
427 }
428 }
429 }
430
431 if (gl_shader_stage_is_compute(nir->info.stage)) {
432 info->properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] = nir->info.cs.local_size[0];
433 info->properties[TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT] = nir->info.cs.local_size[1];
434 info->properties[TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH] = nir->info.cs.local_size[2];
435 }
436
437 i = 0;
438 uint64_t processed_inputs = 0;
439 unsigned num_inputs = 0;
440 nir_foreach_variable(variable, &nir->inputs) {
441 unsigned semantic_name, semantic_index;
442
443 const struct glsl_type *type = variable->type;
444 if (nir_is_per_vertex_io(variable, nir->info.stage)) {
445 assert(glsl_type_is_array(type));
446 type = glsl_get_array_element(type);
447 }
448
449 unsigned attrib_count = glsl_count_attribute_slots(type,
450 nir->info.stage == MESA_SHADER_VERTEX);
451
452 i = variable->data.driver_location;
453
454 /* Vertex shader inputs don't have semantics. The state
455 * tracker has already mapped them to attributes via
456 * variable->data.driver_location.
457 */
458 if (nir->info.stage == MESA_SHADER_VERTEX) {
459 if (glsl_type_is_dual_slot(glsl_without_array(variable->type)))
460 num_inputs++;
461
462 num_inputs++;
463 continue;
464 }
465
466 for (unsigned j = 0; j < attrib_count; j++, i++) {
467
468 if (processed_inputs & ((uint64_t)1 << i))
469 continue;
470
471 processed_inputs |= ((uint64_t)1 << i);
472 num_inputs++;
473
474 tgsi_get_gl_varying_semantic(variable->data.location + j, true,
475 &semantic_name, &semantic_index);
476
477 info->input_semantic_name[i] = semantic_name;
478 info->input_semantic_index[i] = semantic_index;
479
480 if (semantic_name == TGSI_SEMANTIC_PRIMID)
481 info->uses_primid = true;
482
483 enum glsl_base_type base_type =
484 glsl_get_base_type(glsl_without_array(variable->type));
485
486 switch (variable->data.interpolation) {
487 case INTERP_MODE_NONE:
488 if (glsl_base_type_is_integer(base_type)) {
489 info->input_interpolate[i] = TGSI_INTERPOLATE_CONSTANT;
490 break;
491 }
492
493 if (semantic_name == TGSI_SEMANTIC_COLOR) {
494 info->input_interpolate[i] = TGSI_INTERPOLATE_COLOR;
495 break;
496 }
497 /* fall-through */
498
499 case INTERP_MODE_SMOOTH:
500 assert(!glsl_base_type_is_integer(base_type));
501
502 info->input_interpolate[i] = TGSI_INTERPOLATE_PERSPECTIVE;
503 break;
504
505 case INTERP_MODE_NOPERSPECTIVE:
506 assert(!glsl_base_type_is_integer(base_type));
507
508 info->input_interpolate[i] = TGSI_INTERPOLATE_LINEAR;
509 break;
510
511 case INTERP_MODE_FLAT:
512 info->input_interpolate[i] = TGSI_INTERPOLATE_CONSTANT;
513 break;
514 }
515 }
516 }
517
518 info->num_inputs = num_inputs;
519
520 i = 0;
521 uint64_t processed_outputs = 0;
522 unsigned num_outputs = 0;
523 nir_foreach_variable(variable, &nir->outputs) {
524 unsigned semantic_name, semantic_index;
525
526 i = variable->data.driver_location;
527
528 const struct glsl_type *type = variable->type;
529 if (nir_is_per_vertex_io(variable, nir->info.stage)) {
530 assert(glsl_type_is_array(type));
531 type = glsl_get_array_element(type);
532 }
533
534 unsigned attrib_count = glsl_count_attribute_slots(type, false);
535 for (unsigned k = 0; k < attrib_count; k++, i++) {
536
537 if (nir->info.stage == MESA_SHADER_FRAGMENT) {
538 tgsi_get_gl_frag_result_semantic(variable->data.location + k,
539 &semantic_name, &semantic_index);
540
541 /* Adjust for dual source blending */
542 if (variable->data.index > 0) {
543 semantic_index++;
544 }
545 } else {
546 tgsi_get_gl_varying_semantic(variable->data.location + k, true,
547 &semantic_name, &semantic_index);
548 }
549
550 unsigned num_components = 4;
551 unsigned vector_elements = glsl_get_vector_elements(glsl_without_array(variable->type));
552 if (vector_elements)
553 num_components = vector_elements;
554
555 unsigned component = variable->data.location_frac;
556 if (glsl_type_is_64bit(glsl_without_array(variable->type))) {
557 if (glsl_type_is_dual_slot(glsl_without_array(variable->type)) && k % 2) {
558 num_components = (num_components * 2) - 4;
559 component = 0;
560 } else {
561 num_components = MIN2(num_components * 2, 4);
562 }
563 }
564
565 ubyte usagemask = 0;
566 for (unsigned j = component; j < num_components + component; j++) {
567 switch (j) {
568 case 0:
569 usagemask |= TGSI_WRITEMASK_X;
570 break;
571 case 1:
572 usagemask |= TGSI_WRITEMASK_Y;
573 break;
574 case 2:
575 usagemask |= TGSI_WRITEMASK_Z;
576 break;
577 case 3:
578 usagemask |= TGSI_WRITEMASK_W;
579 break;
580 default:
581 unreachable("error calculating component index");
582 }
583 }
584
585 unsigned gs_out_streams;
586 if (variable->data.stream & (1u << 31)) {
587 gs_out_streams = variable->data.stream & ~(1u << 31);
588 } else {
589 assert(variable->data.stream < 4);
590 gs_out_streams = 0;
591 for (unsigned j = 0; j < num_components; ++j)
592 gs_out_streams |= variable->data.stream << (2 * (component + j));
593 }
594
595 unsigned streamx = gs_out_streams & 3;
596 unsigned streamy = (gs_out_streams >> 2) & 3;
597 unsigned streamz = (gs_out_streams >> 4) & 3;
598 unsigned streamw = (gs_out_streams >> 6) & 3;
599
600 if (usagemask & TGSI_WRITEMASK_X) {
601 info->output_usagemask[i] |= TGSI_WRITEMASK_X;
602 info->output_streams[i] |= streamx;
603 info->num_stream_output_components[streamx]++;
604 }
605 if (usagemask & TGSI_WRITEMASK_Y) {
606 info->output_usagemask[i] |= TGSI_WRITEMASK_Y;
607 info->output_streams[i] |= streamy << 2;
608 info->num_stream_output_components[streamy]++;
609 }
610 if (usagemask & TGSI_WRITEMASK_Z) {
611 info->output_usagemask[i] |= TGSI_WRITEMASK_Z;
612 info->output_streams[i] |= streamz << 4;
613 info->num_stream_output_components[streamz]++;
614 }
615 if (usagemask & TGSI_WRITEMASK_W) {
616 info->output_usagemask[i] |= TGSI_WRITEMASK_W;
617 info->output_streams[i] |= streamw << 6;
618 info->num_stream_output_components[streamw]++;
619 }
620
621 /* make sure we only count this location once against
622 * the num_outputs counter.
623 */
624 if (processed_outputs & ((uint64_t)1 << i))
625 continue;
626
627 processed_outputs |= ((uint64_t)1 << i);
628 num_outputs++;
629
630 info->output_semantic_name[i] = semantic_name;
631 info->output_semantic_index[i] = semantic_index;
632
633 switch (semantic_name) {
634 case TGSI_SEMANTIC_PRIMID:
635 info->writes_primid = true;
636 break;
637 case TGSI_SEMANTIC_VIEWPORT_INDEX:
638 info->writes_viewport_index = true;
639 break;
640 case TGSI_SEMANTIC_LAYER:
641 info->writes_layer = true;
642 break;
643 case TGSI_SEMANTIC_PSIZE:
644 info->writes_psize = true;
645 break;
646 case TGSI_SEMANTIC_CLIPVERTEX:
647 info->writes_clipvertex = true;
648 break;
649 case TGSI_SEMANTIC_COLOR:
650 info->colors_written |= 1 << semantic_index;
651 break;
652 case TGSI_SEMANTIC_STENCIL:
653 info->writes_stencil = true;
654 break;
655 case TGSI_SEMANTIC_SAMPLEMASK:
656 info->writes_samplemask = true;
657 break;
658 case TGSI_SEMANTIC_EDGEFLAG:
659 info->writes_edgeflag = true;
660 break;
661 case TGSI_SEMANTIC_POSITION:
662 if (info->processor == PIPE_SHADER_FRAGMENT)
663 info->writes_z = true;
664 else
665 info->writes_position = true;
666 break;
667 }
668
669 if (nir->info.stage == MESA_SHADER_TESS_CTRL) {
670 switch (semantic_name) {
671 case TGSI_SEMANTIC_PATCH:
672 info->reads_perpatch_outputs = true;
673 break;
674 case TGSI_SEMANTIC_TESSINNER:
675 case TGSI_SEMANTIC_TESSOUTER:
676 info->reads_tessfactor_outputs = true;
677 break;
678 default:
679 info->reads_pervertex_outputs = true;
680 }
681 }
682 }
683
684 unsigned loc = variable->data.location;
685 if (nir->info.stage == MESA_SHADER_FRAGMENT &&
686 loc == FRAG_RESULT_COLOR &&
687 nir->info.outputs_written & (1ull << loc)) {
688 assert(attrib_count == 1);
689 info->properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS] = true;
690 }
691 }
692
693 info->num_outputs = num_outputs;
694
695 struct set *ubo_set = _mesa_set_create(NULL, _mesa_hash_pointer,
696 _mesa_key_pointer_equal);
697 struct set *ssbo_set = _mesa_set_create(NULL, _mesa_hash_pointer,
698 _mesa_key_pointer_equal);
699
700 /* Intialise const_file_max[0] */
701 info->const_file_max[0] = -1;
702
703 /* The first 8 are reserved for atomic counters using ssbo */
704 unsigned ssbo_idx = 8;
705
706 unsigned ubo_idx = 1;
707 nir_foreach_variable(variable, &nir->uniforms) {
708 const struct glsl_type *type = variable->type;
709 enum glsl_base_type base_type =
710 glsl_get_base_type(glsl_without_array(type));
711 unsigned aoa_size = MAX2(1, glsl_get_aoa_size(type));
712 unsigned loc = variable->data.driver_location / 4;
713 int slot_count = glsl_count_attribute_slots(type, false);
714 int max_slot = MAX2(info->const_file_max[0], (int) loc) + slot_count;
715
716 /* Gather buffers declared bitmasks. Note: radeonsi doesn't
717 * really use the mask (other than ubo_idx == 1 for regular
718 * uniforms) its really only used for getting the buffer count
719 * so we don't need to worry about the ordering.
720 */
721 if (variable->interface_type != NULL) {
722 if (variable->data.mode == nir_var_uniform ||
723 variable->data.mode == nir_var_mem_ubo ||
724 variable->data.mode == nir_var_mem_ssbo) {
725
726 struct set *buf_set = variable->data.mode == nir_var_mem_ssbo ?
727 ssbo_set : ubo_set;
728
729 unsigned block_count;
730 if (base_type != GLSL_TYPE_INTERFACE) {
731 struct set_entry *entry =
732 _mesa_set_search(buf_set, variable->interface_type);
733
734 /* Check if we have already processed
735 * a member from this ubo.
736 */
737 if (entry)
738 continue;
739
740 block_count = 1;
741 } else {
742 block_count = aoa_size;
743 }
744
745 if (variable->data.mode == nir_var_uniform ||
746 variable->data.mode == nir_var_mem_ubo) {
747 info->const_buffers_declared |= u_bit_consecutive(ubo_idx, block_count);
748 ubo_idx += block_count;
749 } else {
750 assert(variable->data.mode == nir_var_mem_ssbo);
751
752 info->shader_buffers_declared |= u_bit_consecutive(ssbo_idx, block_count);
753 ssbo_idx += block_count;
754 }
755
756 _mesa_set_add(buf_set, variable->interface_type);
757 }
758
759 continue;
760 }
761
762 /* We rely on the fact that nir_lower_samplers_as_deref has
763 * eliminated struct dereferences.
764 */
765 if (base_type == GLSL_TYPE_SAMPLER) {
766 if (variable->data.bindless) {
767 info->const_buffers_declared |= 1;
768 info->const_file_max[0] = max_slot;
769 } else {
770 info->samplers_declared |=
771 u_bit_consecutive(variable->data.binding, aoa_size);
772 }
773 } else if (base_type == GLSL_TYPE_IMAGE) {
774 if (variable->data.bindless) {
775 info->const_buffers_declared |= 1;
776 info->const_file_max[0] = max_slot;
777 } else {
778 info->images_declared |=
779 u_bit_consecutive(variable->data.binding, aoa_size);
780 }
781 } else if (base_type != GLSL_TYPE_ATOMIC_UINT) {
782 info->const_buffers_declared |= 1;
783 info->const_file_max[0] = max_slot;
784 }
785 }
786
787 _mesa_set_destroy(ubo_set, NULL);
788 _mesa_set_destroy(ssbo_set, NULL);
789
790 info->num_written_clipdistance = nir->info.clip_distance_array_size;
791 info->num_written_culldistance = nir->info.cull_distance_array_size;
792 info->clipdist_writemask = u_bit_consecutive(0, info->num_written_clipdistance);
793 info->culldist_writemask = u_bit_consecutive(0, info->num_written_culldistance);
794
795 if (info->processor == PIPE_SHADER_FRAGMENT)
796 info->uses_kill = nir->info.fs.uses_discard;
797
798 func = (struct nir_function *)exec_list_get_head_const(&nir->functions);
799 nir_foreach_block(block, func->impl) {
800 nir_foreach_instr(instr, block)
801 scan_instruction(nir, info, instr);
802 }
803 }
804
805 void
806 si_nir_opts(struct nir_shader *nir)
807 {
808 bool progress;
809 unsigned lower_flrp =
810 (nir->options->lower_flrp16 ? 16 : 0) |
811 (nir->options->lower_flrp32 ? 32 : 0) |
812 (nir->options->lower_flrp64 ? 64 : 0);
813
814 do {
815 progress = false;
816
817 NIR_PASS_V(nir, nir_lower_vars_to_ssa);
818
819 NIR_PASS(progress, nir, nir_opt_copy_prop_vars);
820 NIR_PASS(progress, nir, nir_opt_dead_write_vars);
821
822 NIR_PASS_V(nir, nir_lower_alu_to_scalar, NULL);
823 NIR_PASS_V(nir, nir_lower_phis_to_scalar);
824
825 /* (Constant) copy propagation is needed for txf with offsets. */
826 NIR_PASS(progress, nir, nir_copy_prop);
827 NIR_PASS(progress, nir, nir_opt_remove_phis);
828 NIR_PASS(progress, nir, nir_opt_dce);
829 if (nir_opt_trivial_continues(nir)) {
830 progress = true;
831 NIR_PASS(progress, nir, nir_copy_prop);
832 NIR_PASS(progress, nir, nir_opt_dce);
833 }
834 NIR_PASS(progress, nir, nir_opt_if, true);
835 NIR_PASS(progress, nir, nir_opt_dead_cf);
836 NIR_PASS(progress, nir, nir_opt_cse);
837 NIR_PASS(progress, nir, nir_opt_peephole_select, 8, true, true);
838
839 /* Needed for algebraic lowering */
840 NIR_PASS(progress, nir, nir_opt_algebraic);
841 NIR_PASS(progress, nir, nir_opt_constant_folding);
842
843 if (lower_flrp != 0) {
844 bool lower_flrp_progress = false;
845
846 NIR_PASS(lower_flrp_progress, nir, nir_lower_flrp,
847 lower_flrp,
848 false /* always_precise */,
849 nir->options->lower_ffma);
850 if (lower_flrp_progress) {
851 NIR_PASS(progress, nir,
852 nir_opt_constant_folding);
853 progress = true;
854 }
855
856 /* Nothing should rematerialize any flrps, so we only
857 * need to do this lowering once.
858 */
859 lower_flrp = 0;
860 }
861
862 NIR_PASS(progress, nir, nir_opt_undef);
863 NIR_PASS(progress, nir, nir_opt_conditional_discard);
864 if (nir->options->max_unroll_iterations) {
865 NIR_PASS(progress, nir, nir_opt_loop_unroll, 0);
866 }
867 } while (progress);
868 }
869
870 static int
871 type_size_vec4(const struct glsl_type *type, bool bindless)
872 {
873 return glsl_count_attribute_slots(type, false);
874 }
875
876 static void
877 si_nir_lower_color(nir_shader *nir)
878 {
879 nir_function_impl *entrypoint = nir_shader_get_entrypoint(nir);
880
881 nir_builder b;
882 nir_builder_init(&b, entrypoint);
883
884 nir_foreach_block(block, entrypoint) {
885 nir_foreach_instr_safe(instr, block) {
886 if (instr->type != nir_instr_type_intrinsic)
887 continue;
888
889 nir_intrinsic_instr *intrin =
890 nir_instr_as_intrinsic(instr);
891
892 if (intrin->intrinsic != nir_intrinsic_load_deref)
893 continue;
894
895 nir_deref_instr *deref = nir_src_as_deref(intrin->src[0]);
896 if (deref->mode != nir_var_shader_in)
897 continue;
898
899 b.cursor = nir_before_instr(instr);
900 nir_variable *var = nir_deref_instr_get_variable(deref);
901 nir_ssa_def *def;
902
903 if (var->data.location == VARYING_SLOT_COL0) {
904 def = nir_load_color0(&b);
905 } else if (var->data.location == VARYING_SLOT_COL1) {
906 def = nir_load_color1(&b);
907 } else {
908 continue;
909 }
910
911 nir_ssa_def_rewrite_uses(&intrin->dest.ssa, nir_src_for_ssa(def));
912 nir_instr_remove(instr);
913 }
914 }
915 }
916
917 /**
918 * Perform "lowering" operations on the NIR that are run once when the shader
919 * selector is created.
920 */
921 void
922 si_lower_nir(struct si_shader_selector* sel, unsigned wave_size)
923 {
924 /* Adjust the driver location of inputs and outputs. The state tracker
925 * interprets them as slots, while the ac/nir backend interprets them
926 * as individual components.
927 */
928 if (sel->nir->info.stage != MESA_SHADER_FRAGMENT) {
929 nir_foreach_variable(variable, &sel->nir->inputs)
930 variable->data.driver_location *= 4;
931 } else {
932 NIR_PASS_V(sel->nir, nir_lower_io_to_temporaries,
933 nir_shader_get_entrypoint(sel->nir), false, true);
934
935 /* Since we're doing nir_lower_io_to_temporaries late, we need
936 * to lower all the copy_deref's introduced by
937 * lower_io_to_temporaries before calling nir_lower_io.
938 */
939 NIR_PASS_V(sel->nir, nir_split_var_copies);
940 NIR_PASS_V(sel->nir, nir_lower_var_copies);
941 NIR_PASS_V(sel->nir, nir_lower_global_vars_to_local);
942
943 si_nir_lower_color(sel->nir);
944 NIR_PASS_V(sel->nir, nir_lower_io, nir_var_shader_in, type_size_vec4, 0);
945
946 /* This pass needs actual constants */
947 NIR_PASS_V(sel->nir, nir_opt_constant_folding);
948 NIR_PASS_V(sel->nir, nir_io_add_const_offset_to_base,
949 nir_var_shader_in);
950 }
951
952 nir_foreach_variable(variable, &sel->nir->outputs) {
953 variable->data.driver_location *= 4;
954
955 if (sel->nir->info.stage == MESA_SHADER_FRAGMENT) {
956 if (variable->data.location == FRAG_RESULT_DEPTH)
957 variable->data.driver_location += 2;
958 else if (variable->data.location == FRAG_RESULT_STENCIL)
959 variable->data.driver_location += 1;
960 }
961 }
962
963 /* Perform lowerings (and optimizations) of code.
964 *
965 * Performance considerations aside, we must:
966 * - lower certain ALU operations
967 * - ensure constant offsets for texture instructions are folded
968 * and copy-propagated
969 */
970
971 static const struct nir_lower_tex_options lower_tex_options = {
972 .lower_txp = ~0u,
973 };
974 NIR_PASS_V(sel->nir, nir_lower_tex, &lower_tex_options);
975
976 const nir_lower_subgroups_options subgroups_options = {
977 .subgroup_size = wave_size,
978 .ballot_bit_size = wave_size,
979 .lower_to_scalar = true,
980 .lower_subgroup_masks = true,
981 .lower_vote_trivial = false,
982 .lower_vote_eq_to_ballot = true,
983 };
984 NIR_PASS_V(sel->nir, nir_lower_subgroups, &subgroups_options);
985
986 ac_lower_indirect_derefs(sel->nir, sel->screen->info.chip_class);
987
988 si_nir_opts(sel->nir);
989
990 NIR_PASS_V(sel->nir, nir_lower_bool_to_int32);
991
992 /* Strip the resulting shader so that the shader cache is more likely
993 * to hit from other similar shaders.
994 */
995 nir_strip(sel->nir);
996 }
997
998 static void declare_nir_input_vs(struct si_shader_context *ctx,
999 struct nir_variable *variable,
1000 unsigned input_index,
1001 LLVMValueRef out[4])
1002 {
1003 si_llvm_load_input_vs(ctx, input_index, out);
1004 }
1005
1006 LLVMValueRef
1007 si_nir_lookup_interp_param(struct ac_shader_abi *abi,
1008 enum glsl_interp_mode interp, unsigned location)
1009 {
1010 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1011 int interp_param_idx = -1;
1012
1013 switch (interp) {
1014 case INTERP_MODE_FLAT:
1015 return NULL;
1016 case INTERP_MODE_SMOOTH:
1017 case INTERP_MODE_NONE:
1018 if (location == INTERP_CENTER)
1019 interp_param_idx = SI_PARAM_PERSP_CENTER;
1020 else if (location == INTERP_CENTROID)
1021 interp_param_idx = SI_PARAM_PERSP_CENTROID;
1022 else if (location == INTERP_SAMPLE)
1023 interp_param_idx = SI_PARAM_PERSP_SAMPLE;
1024 break;
1025 case INTERP_MODE_NOPERSPECTIVE:
1026 if (location == INTERP_CENTER)
1027 interp_param_idx = SI_PARAM_LINEAR_CENTER;
1028 else if (location == INTERP_CENTROID)
1029 interp_param_idx = SI_PARAM_LINEAR_CENTROID;
1030 else if (location == INTERP_SAMPLE)
1031 interp_param_idx = SI_PARAM_LINEAR_SAMPLE;
1032 break;
1033 default:
1034 assert(!"Unhandled interpolation mode.");
1035 return NULL;
1036 }
1037
1038 return interp_param_idx != -1 ?
1039 LLVMGetParam(ctx->main_fn, interp_param_idx) : NULL;
1040 }
1041
1042 static LLVMValueRef
1043 si_nir_load_sampler_desc(struct ac_shader_abi *abi,
1044 unsigned descriptor_set, unsigned base_index,
1045 unsigned constant_index, LLVMValueRef dynamic_index,
1046 enum ac_descriptor_type desc_type, bool image,
1047 bool write, bool bindless)
1048 {
1049 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1050 LLVMBuilderRef builder = ctx->ac.builder;
1051 unsigned const_index = base_index + constant_index;
1052
1053 assert(!descriptor_set);
1054 assert(!image || desc_type == AC_DESC_IMAGE || desc_type == AC_DESC_BUFFER);
1055
1056 if (bindless) {
1057 LLVMValueRef list =
1058 LLVMGetParam(ctx->main_fn, ctx->param_bindless_samplers_and_images);
1059
1060 /* dynamic_index is the bindless handle */
1061 if (image) {
1062 /* For simplicity, bindless image descriptors use fixed
1063 * 16-dword slots for now.
1064 */
1065 dynamic_index = LLVMBuildMul(ctx->ac.builder, dynamic_index,
1066 LLVMConstInt(ctx->i64, 2, 0), "");
1067
1068 return si_load_image_desc(ctx, list, dynamic_index, desc_type,
1069 write, true);
1070 }
1071
1072 /* Since bindless handle arithmetic can contain an unsigned integer
1073 * wraparound and si_load_sampler_desc assumes there isn't any,
1074 * use GEP without "inbounds" (inside ac_build_pointer_add)
1075 * to prevent incorrect code generation and hangs.
1076 */
1077 dynamic_index = LLVMBuildMul(ctx->ac.builder, dynamic_index,
1078 LLVMConstInt(ctx->i64, 2, 0), "");
1079 list = ac_build_pointer_add(&ctx->ac, list, dynamic_index);
1080 return si_load_sampler_desc(ctx, list, ctx->i32_0, desc_type);
1081 }
1082
1083 unsigned num_slots = image ? ctx->num_images : ctx->num_samplers;
1084 assert(const_index < num_slots);
1085
1086 LLVMValueRef list = LLVMGetParam(ctx->main_fn, ctx->param_samplers_and_images);
1087 LLVMValueRef index = LLVMConstInt(ctx->ac.i32, const_index, false);
1088
1089 if (dynamic_index) {
1090 index = LLVMBuildAdd(builder, index, dynamic_index, "");
1091
1092 /* From the GL_ARB_shader_image_load_store extension spec:
1093 *
1094 * If a shader performs an image load, store, or atomic
1095 * operation using an image variable declared as an array,
1096 * and if the index used to select an individual element is
1097 * negative or greater than or equal to the size of the
1098 * array, the results of the operation are undefined but may
1099 * not lead to termination.
1100 */
1101 index = si_llvm_bound_index(ctx, index, num_slots);
1102 }
1103
1104 if (image) {
1105 index = LLVMBuildSub(ctx->ac.builder,
1106 LLVMConstInt(ctx->i32, SI_NUM_IMAGES - 1, 0),
1107 index, "");
1108 return si_load_image_desc(ctx, list, index, desc_type, write, false);
1109 }
1110
1111 index = LLVMBuildAdd(ctx->ac.builder, index,
1112 LLVMConstInt(ctx->i32, SI_NUM_IMAGES / 2, 0), "");
1113 return si_load_sampler_desc(ctx, list, index, desc_type);
1114 }
1115
1116 static void bitcast_inputs(struct si_shader_context *ctx,
1117 LLVMValueRef data[4],
1118 unsigned input_idx)
1119 {
1120 for (unsigned chan = 0; chan < 4; chan++) {
1121 ctx->inputs[input_idx + chan] =
1122 LLVMBuildBitCast(ctx->ac.builder, data[chan], ctx->ac.i32, "");
1123 }
1124 }
1125
1126 bool si_nir_build_llvm(struct si_shader_context *ctx, struct nir_shader *nir)
1127 {
1128 struct tgsi_shader_info *info = &ctx->shader->selector->info;
1129
1130 if (nir->info.stage == MESA_SHADER_VERTEX) {
1131 uint64_t processed_inputs = 0;
1132 nir_foreach_variable(variable, &nir->inputs) {
1133 unsigned attrib_count = glsl_count_attribute_slots(variable->type,
1134 true);
1135 unsigned input_idx = variable->data.driver_location;
1136
1137 LLVMValueRef data[4];
1138 unsigned loc = variable->data.location;
1139
1140 for (unsigned i = 0; i < attrib_count; i++) {
1141 /* Packed components share the same location so skip
1142 * them if we have already processed the location.
1143 */
1144 if (processed_inputs & ((uint64_t)1 << (loc + i))) {
1145 input_idx += 4;
1146 continue;
1147 }
1148
1149 declare_nir_input_vs(ctx, variable, input_idx / 4, data);
1150 bitcast_inputs(ctx, data, input_idx);
1151 if (glsl_type_is_dual_slot(variable->type)) {
1152 input_idx += 4;
1153 declare_nir_input_vs(ctx, variable, input_idx / 4, data);
1154 bitcast_inputs(ctx, data, input_idx);
1155 }
1156
1157 processed_inputs |= ((uint64_t)1 << (loc + i));
1158 input_idx += 4;
1159 }
1160 }
1161 } else if (nir->info.stage == MESA_SHADER_FRAGMENT) {
1162 unsigned colors_read =
1163 ctx->shader->selector->info.colors_read;
1164 LLVMValueRef main_fn = ctx->main_fn;
1165
1166 LLVMValueRef undef = LLVMGetUndef(ctx->f32);
1167
1168 unsigned offset = SI_PARAM_POS_FIXED_PT + 1;
1169
1170 if (colors_read & 0x0f) {
1171 unsigned mask = colors_read & 0x0f;
1172 LLVMValueRef values[4];
1173 values[0] = mask & 0x1 ? LLVMGetParam(main_fn, offset++) : undef;
1174 values[1] = mask & 0x2 ? LLVMGetParam(main_fn, offset++) : undef;
1175 values[2] = mask & 0x4 ? LLVMGetParam(main_fn, offset++) : undef;
1176 values[3] = mask & 0x8 ? LLVMGetParam(main_fn, offset++) : undef;
1177 ctx->abi.color0 =
1178 ac_to_integer(&ctx->ac,
1179 ac_build_gather_values(&ctx->ac, values, 4));
1180 }
1181 if (colors_read & 0xf0) {
1182 unsigned mask = (colors_read & 0xf0) >> 4;
1183 LLVMValueRef values[4];
1184 values[0] = mask & 0x1 ? LLVMGetParam(main_fn, offset++) : undef;
1185 values[1] = mask & 0x2 ? LLVMGetParam(main_fn, offset++) : undef;
1186 values[2] = mask & 0x4 ? LLVMGetParam(main_fn, offset++) : undef;
1187 values[3] = mask & 0x8 ? LLVMGetParam(main_fn, offset++) : undef;
1188 ctx->abi.color1 =
1189 ac_to_integer(&ctx->ac,
1190 ac_build_gather_values(&ctx->ac, values, 4));
1191 }
1192 }
1193
1194 ctx->abi.inputs = &ctx->inputs[0];
1195 ctx->abi.load_sampler_desc = si_nir_load_sampler_desc;
1196 ctx->abi.clamp_shadow_reference = true;
1197
1198 ctx->num_samplers = util_last_bit(info->samplers_declared);
1199 ctx->num_images = util_last_bit(info->images_declared);
1200
1201 if (ctx->shader->selector->info.properties[TGSI_PROPERTY_CS_LOCAL_SIZE]) {
1202 assert(gl_shader_stage_is_compute(nir->info.stage));
1203 si_declare_compute_memory(ctx);
1204 }
1205 ac_nir_translate(&ctx->ac, &ctx->abi, nir);
1206
1207 return true;
1208 }