projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
radeonsi/nir: accurately set reads_*_outputs for TCS
[mesa.git] / src / gallium / drivers / radeonsi / si_shader_nir.c
1 /*
2 * Copyright 2017 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 #include "si_shader_internal.h"
26 #include "si_pipe.h"
27
28 #include "ac_nir_to_llvm.h"
29
30 #include "tgsi/tgsi_from_mesa.h"
31
32 #include "compiler/nir/nir.h"
33 #include "compiler/nir_types.h"
34 #include "compiler/nir/nir_builder.h"
35
36 static nir_variable* tex_get_texture_var(nir_tex_instr *instr)
37 {
38 for (unsigned i = 0; i < instr->num_srcs; i++) {
39 switch (instr->src[i].src_type) {
40 case nir_tex_src_texture_deref:
41 return nir_deref_instr_get_variable(nir_src_as_deref(instr->src[i].src));
42 default:
43 break;
44 }
45 }
46
47 return NULL;
48 }
49
50 static nir_variable* intrinsic_get_var(nir_intrinsic_instr *instr)
51 {
52 return nir_deref_instr_get_variable(nir_src_as_deref(instr->src[0]));
53 }
54
55 static void gather_intrinsic_load_deref_input_info(const nir_shader *nir,
56 const nir_intrinsic_instr *instr,
57 nir_variable *var,
58 struct tgsi_shader_info *info)
59 {
60 assert(var && var->data.mode == nir_var_shader_in);
61
62 switch (nir->info.stage) {
63 case MESA_SHADER_VERTEX: {
64 unsigned i = var->data.driver_location;
65 unsigned attrib_count = glsl_count_attribute_slots(var->type, false);
66
67 for (unsigned j = 0; j < attrib_count; j++, i++) {
68 if (glsl_type_is_64bit(glsl_without_array(var->type))) {
69 /* TODO: set usage mask more accurately for doubles */
70 info->input_usage_mask[i] = TGSI_WRITEMASK_XYZW;
71 } else {
72 uint8_t mask = nir_ssa_def_components_read(&instr->dest.ssa);
73 info->input_usage_mask[i] |= mask << var->data.location_frac;
74 }
75 }
76 break;
77 }
78 case MESA_SHADER_FRAGMENT:
79 if (var->data.location == VARYING_SLOT_COL0 ||
80 var->data.location == VARYING_SLOT_COL1) {
81 unsigned index = var->data.location == VARYING_SLOT_COL1;
82 uint8_t mask = nir_ssa_def_components_read(&instr->dest.ssa);
83 info->colors_read |= mask << (index * 4);
84 }
85 break;
86 default:;
87 }
88 }
89
90 static void gather_intrinsic_load_deref_output_info(const nir_shader *nir,
91 const nir_intrinsic_instr *instr,
92 nir_variable *var,
93 struct tgsi_shader_info *info)
94 {
95 assert(var && var->data.mode == nir_var_shader_out);
96
97 switch (nir->info.stage) {
98 case MESA_SHADER_TESS_CTRL:
99 if (var->data.location == VARYING_SLOT_TESS_LEVEL_INNER ||
100 var->data.location == VARYING_SLOT_TESS_LEVEL_OUTER)
101 info->reads_tessfactor_outputs = true;
102 else if (var->data.patch)
103 info->reads_perpatch_outputs = true;
104 else
105 info->reads_pervertex_outputs = true;
106 break;
107
108 case MESA_SHADER_FRAGMENT:
109 if (var->data.fb_fetch_output)
110 info->uses_fbfetch = true;
111 break;
112 default:;
113 }
114 }
115
116 static void scan_instruction(const struct nir_shader *nir,
117 struct tgsi_shader_info *info,
118 nir_instr *instr)
119 {
120 if (instr->type == nir_instr_type_alu) {
121 nir_alu_instr *alu = nir_instr_as_alu(instr);
122
123 switch (alu->op) {
124 case nir_op_fddx:
125 case nir_op_fddy:
126 case nir_op_fddx_fine:
127 case nir_op_fddy_fine:
128 case nir_op_fddx_coarse:
129 case nir_op_fddy_coarse:
130 info->uses_derivatives = true;
131 break;
132 default:
133 break;
134 }
135 } else if (instr->type == nir_instr_type_tex) {
136 nir_tex_instr *tex = nir_instr_as_tex(instr);
137 nir_variable *texture = tex_get_texture_var(tex);
138
139 if (!texture) {
140 info->samplers_declared |=
141 u_bit_consecutive(tex->sampler_index, 1);
142 } else {
143 if (texture->data.bindless)
144 info->uses_bindless_samplers = true;
145 }
146
147 switch (tex->op) {
148 case nir_texop_tex:
149 case nir_texop_txb:
150 case nir_texop_lod:
151 info->uses_derivatives = true;
152 break;
153 default:
154 break;
155 }
156 } else if (instr->type == nir_instr_type_intrinsic) {
157 nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);
158
159 switch (intr->intrinsic) {
160 case nir_intrinsic_load_front_face:
161 info->uses_frontface = 1;
162 break;
163 case nir_intrinsic_load_instance_id:
164 info->uses_instanceid = 1;
165 break;
166 case nir_intrinsic_load_invocation_id:
167 info->uses_invocationid = true;
168 break;
169 case nir_intrinsic_load_num_work_groups:
170 info->uses_grid_size = true;
171 break;
172 case nir_intrinsic_load_local_group_size:
173 /* The block size is translated to IMM with a fixed block size. */
174 if (info->properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] == 0)
175 info->uses_block_size = true;
176 break;
177 case nir_intrinsic_load_local_invocation_id:
178 case nir_intrinsic_load_work_group_id: {
179 unsigned mask = nir_ssa_def_components_read(&intr->dest.ssa);
180 while (mask) {
181 unsigned i = u_bit_scan(&mask);
182
183 if (intr->intrinsic == nir_intrinsic_load_work_group_id)
184 info->uses_block_id[i] = true;
185 else
186 info->uses_thread_id[i] = true;
187 }
188 break;
189 }
190 case nir_intrinsic_load_vertex_id:
191 info->uses_vertexid = 1;
192 break;
193 case nir_intrinsic_load_vertex_id_zero_base:
194 info->uses_vertexid_nobase = 1;
195 break;
196 case nir_intrinsic_load_base_vertex:
197 info->uses_basevertex = 1;
198 break;
199 case nir_intrinsic_load_draw_id:
200 info->uses_drawid = 1;
201 break;
202 case nir_intrinsic_load_primitive_id:
203 info->uses_primid = 1;
204 break;
205 case nir_intrinsic_load_sample_mask_in:
206 info->reads_samplemask = true;
207 break;
208 case nir_intrinsic_load_tess_level_inner:
209 case nir_intrinsic_load_tess_level_outer:
210 info->reads_tess_factors = true;
211 break;
212 case nir_intrinsic_bindless_image_load:
213 info->uses_bindless_images = true;
214
215 if (nir_intrinsic_image_dim(intr) == GLSL_SAMPLER_DIM_BUF)
216 info->uses_bindless_buffer_load = true;
217 else
218 info->uses_bindless_image_load = true;
219 break;
220 case nir_intrinsic_bindless_image_size:
221 case nir_intrinsic_bindless_image_samples:
222 info->uses_bindless_images = true;
223 break;
224 case nir_intrinsic_bindless_image_store:
225 info->uses_bindless_images = true;
226
227 if (nir_intrinsic_image_dim(intr) == GLSL_SAMPLER_DIM_BUF)
228 info->uses_bindless_buffer_store = true;
229 else
230 info->uses_bindless_image_store = true;
231
232 info->writes_memory = true;
233 break;
234 case nir_intrinsic_image_deref_store:
235 info->writes_memory = true;
236 break;
237 case nir_intrinsic_bindless_image_atomic_add:
238 case nir_intrinsic_bindless_image_atomic_min:
239 case nir_intrinsic_bindless_image_atomic_max:
240 case nir_intrinsic_bindless_image_atomic_and:
241 case nir_intrinsic_bindless_image_atomic_or:
242 case nir_intrinsic_bindless_image_atomic_xor:
243 case nir_intrinsic_bindless_image_atomic_exchange:
244 case nir_intrinsic_bindless_image_atomic_comp_swap:
245 info->uses_bindless_images = true;
246
247 if (nir_intrinsic_image_dim(intr) == GLSL_SAMPLER_DIM_BUF)
248 info->uses_bindless_buffer_atomic = true;
249 else
250 info->uses_bindless_image_atomic = true;
251
252 info->writes_memory = true;
253 break;
254 case nir_intrinsic_image_deref_atomic_add:
255 case nir_intrinsic_image_deref_atomic_min:
256 case nir_intrinsic_image_deref_atomic_max:
257 case nir_intrinsic_image_deref_atomic_and:
258 case nir_intrinsic_image_deref_atomic_or:
259 case nir_intrinsic_image_deref_atomic_xor:
260 case nir_intrinsic_image_deref_atomic_exchange:
261 case nir_intrinsic_image_deref_atomic_comp_swap:
262 info->writes_memory = true;
263 break;
264 case nir_intrinsic_store_ssbo:
265 case nir_intrinsic_ssbo_atomic_add:
266 case nir_intrinsic_ssbo_atomic_imin:
267 case nir_intrinsic_ssbo_atomic_umin:
268 case nir_intrinsic_ssbo_atomic_imax:
269 case nir_intrinsic_ssbo_atomic_umax:
270 case nir_intrinsic_ssbo_atomic_and:
271 case nir_intrinsic_ssbo_atomic_or:
272 case nir_intrinsic_ssbo_atomic_xor:
273 case nir_intrinsic_ssbo_atomic_exchange:
274 case nir_intrinsic_ssbo_atomic_comp_swap:
275 info->writes_memory = true;
276 break;
277 case nir_intrinsic_load_deref: {
278 nir_variable *var = intrinsic_get_var(intr);
279 nir_variable_mode mode = var->data.mode;
280 enum glsl_base_type base_type =
281 glsl_get_base_type(glsl_without_array(var->type));
282
283 if (mode == nir_var_shader_in) {
284 gather_intrinsic_load_deref_input_info(nir, intr, var, info);
285
286 switch (var->data.interpolation) {
287 case INTERP_MODE_NONE:
288 if (glsl_base_type_is_integer(base_type))
289 break;
290
291 /* fall-through */
292 case INTERP_MODE_SMOOTH:
293 if (var->data.sample)
294 info->uses_persp_sample = true;
295 else if (var->data.centroid)
296 info->uses_persp_centroid = true;
297 else
298 info->uses_persp_center = true;
299 break;
300
301 case INTERP_MODE_NOPERSPECTIVE:
302 if (var->data.sample)
303 info->uses_linear_sample = true;
304 else if (var->data.centroid)
305 info->uses_linear_centroid = true;
306 else
307 info->uses_linear_center = true;
308 break;
309 }
310 } else if (mode == nir_var_shader_out) {
311 gather_intrinsic_load_deref_output_info(nir, intr, var, info);
312 }
313 break;
314 }
315 case nir_intrinsic_interp_deref_at_centroid:
316 case nir_intrinsic_interp_deref_at_sample:
317 case nir_intrinsic_interp_deref_at_offset: {
318 enum glsl_interp_mode interp = intrinsic_get_var(intr)->data.interpolation;
319 switch (interp) {
320 case INTERP_MODE_SMOOTH:
321 case INTERP_MODE_NONE:
322 if (intr->intrinsic == nir_intrinsic_interp_deref_at_centroid)
323 info->uses_persp_opcode_interp_centroid = true;
324 else if (intr->intrinsic == nir_intrinsic_interp_deref_at_sample)
325 info->uses_persp_opcode_interp_sample = true;
326 else
327 info->uses_persp_opcode_interp_offset = true;
328 break;
329 case INTERP_MODE_NOPERSPECTIVE:
330 if (intr->intrinsic == nir_intrinsic_interp_deref_at_centroid)
331 info->uses_linear_opcode_interp_centroid = true;
332 else if (intr->intrinsic == nir_intrinsic_interp_deref_at_sample)
333 info->uses_linear_opcode_interp_sample = true;
334 else
335 info->uses_linear_opcode_interp_offset = true;
336 break;
337 case INTERP_MODE_FLAT:
338 break;
339 default:
340 unreachable("Unsupported interpoation type");
341 }
342 break;
343 }
344 default:
345 break;
346 }
347 }
348 }
349
350 void si_nir_scan_tess_ctrl(const struct nir_shader *nir,
351 struct tgsi_tessctrl_info *out)
352 {
353 memset(out, 0, sizeof(*out));
354
355 if (nir->info.stage != MESA_SHADER_TESS_CTRL)
356 return;
357
358 out->tessfactors_are_def_in_all_invocs =
359 ac_are_tessfactors_def_in_all_invocs(nir);
360 }
361
362 void si_nir_scan_shader(const struct nir_shader *nir,
363 struct tgsi_shader_info *info)
364 {
365 nir_function *func;
366 unsigned i;
367
368 info->processor = pipe_shader_type_from_mesa(nir->info.stage);
369 info->num_tokens = 2; /* indicate that the shader is non-empty */
370 info->num_instructions = 2;
371
372 info->properties[TGSI_PROPERTY_NEXT_SHADER] =
373 pipe_shader_type_from_mesa(nir->info.next_stage);
374
375 if (nir->info.stage == MESA_SHADER_VERTEX) {
376 info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION] =
377 nir->info.vs.window_space_position;
378 }
379
380 if (nir->info.stage == MESA_SHADER_TESS_CTRL) {
381 info->properties[TGSI_PROPERTY_TCS_VERTICES_OUT] =
382 nir->info.tess.tcs_vertices_out;
383 }
384
385 if (nir->info.stage == MESA_SHADER_TESS_EVAL) {
386 if (nir->info.tess.primitive_mode == GL_ISOLINES)
387 info->properties[TGSI_PROPERTY_TES_PRIM_MODE] = PIPE_PRIM_LINES;
388 else
389 info->properties[TGSI_PROPERTY_TES_PRIM_MODE] = nir->info.tess.primitive_mode;
390
391 STATIC_ASSERT((TESS_SPACING_EQUAL + 1) % 3 == PIPE_TESS_SPACING_EQUAL);
392 STATIC_ASSERT((TESS_SPACING_FRACTIONAL_ODD + 1) % 3 ==
393 PIPE_TESS_SPACING_FRACTIONAL_ODD);
394 STATIC_ASSERT((TESS_SPACING_FRACTIONAL_EVEN + 1) % 3 ==
395 PIPE_TESS_SPACING_FRACTIONAL_EVEN);
396
397 info->properties[TGSI_PROPERTY_TES_SPACING] = (nir->info.tess.spacing + 1) % 3;
398 info->properties[TGSI_PROPERTY_TES_VERTEX_ORDER_CW] = !nir->info.tess.ccw;
399 info->properties[TGSI_PROPERTY_TES_POINT_MODE] = nir->info.tess.point_mode;
400 }
401
402 if (nir->info.stage == MESA_SHADER_GEOMETRY) {
403 info->properties[TGSI_PROPERTY_GS_INPUT_PRIM] = nir->info.gs.input_primitive;
404 info->properties[TGSI_PROPERTY_GS_OUTPUT_PRIM] = nir->info.gs.output_primitive;
405 info->properties[TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES] = nir->info.gs.vertices_out;
406 info->properties[TGSI_PROPERTY_GS_INVOCATIONS] = nir->info.gs.invocations;
407 }
408
409 if (nir->info.stage == MESA_SHADER_FRAGMENT) {
410 info->properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL] =
411 nir->info.fs.early_fragment_tests | nir->info.fs.post_depth_coverage;
412 info->properties[TGSI_PROPERTY_FS_POST_DEPTH_COVERAGE] = nir->info.fs.post_depth_coverage;
413
414 if (nir->info.fs.pixel_center_integer) {
415 info->properties[TGSI_PROPERTY_FS_COORD_PIXEL_CENTER] =
416 TGSI_FS_COORD_PIXEL_CENTER_INTEGER;
417 }
418
419 if (nir->info.fs.depth_layout != FRAG_DEPTH_LAYOUT_NONE) {
420 switch (nir->info.fs.depth_layout) {
421 case FRAG_DEPTH_LAYOUT_ANY:
422 info->properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT] = TGSI_FS_DEPTH_LAYOUT_ANY;
423 break;
424 case FRAG_DEPTH_LAYOUT_GREATER:
425 info->properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT] = TGSI_FS_DEPTH_LAYOUT_GREATER;
426 break;
427 case FRAG_DEPTH_LAYOUT_LESS:
428 info->properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT] = TGSI_FS_DEPTH_LAYOUT_LESS;
429 break;
430 case FRAG_DEPTH_LAYOUT_UNCHANGED:
431 info->properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT] = TGSI_FS_DEPTH_LAYOUT_UNCHANGED;
432 break;
433 default:
434 unreachable("Unknow depth layout");
435 }
436 }
437 }
438
439 if (gl_shader_stage_is_compute(nir->info.stage)) {
440 info->properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] = nir->info.cs.local_size[0];
441 info->properties[TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT] = nir->info.cs.local_size[1];
442 info->properties[TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH] = nir->info.cs.local_size[2];
443 }
444
445 i = 0;
446 uint64_t processed_inputs = 0;
447 unsigned num_inputs = 0;
448 nir_foreach_variable(variable, &nir->inputs) {
449 unsigned semantic_name, semantic_index;
450
451 const struct glsl_type *type = variable->type;
452 if (nir_is_per_vertex_io(variable, nir->info.stage)) {
453 assert(glsl_type_is_array(type));
454 type = glsl_get_array_element(type);
455 }
456
457 unsigned attrib_count = glsl_count_attribute_slots(type,
458 nir->info.stage == MESA_SHADER_VERTEX);
459
460 i = variable->data.driver_location;
461
462 /* Vertex shader inputs don't have semantics. The state
463 * tracker has already mapped them to attributes via
464 * variable->data.driver_location.
465 */
466 if (nir->info.stage == MESA_SHADER_VERTEX) {
467 if (glsl_type_is_dual_slot(glsl_without_array(variable->type)))
468 num_inputs++;
469
470 num_inputs++;
471 continue;
472 }
473
474 for (unsigned j = 0; j < attrib_count; j++, i++) {
475
476 if (processed_inputs & ((uint64_t)1 << i))
477 continue;
478
479 processed_inputs |= ((uint64_t)1 << i);
480 num_inputs++;
481
482 tgsi_get_gl_varying_semantic(variable->data.location + j, true,
483 &semantic_name, &semantic_index);
484
485 info->input_semantic_name[i] = semantic_name;
486 info->input_semantic_index[i] = semantic_index;
487
488 if (semantic_name == TGSI_SEMANTIC_PRIMID)
489 info->uses_primid = true;
490
491 enum glsl_base_type base_type =
492 glsl_get_base_type(glsl_without_array(variable->type));
493
494 switch (variable->data.interpolation) {
495 case INTERP_MODE_NONE:
496 if (glsl_base_type_is_integer(base_type)) {
497 info->input_interpolate[i] = TGSI_INTERPOLATE_CONSTANT;
498 break;
499 }
500
501 if (semantic_name == TGSI_SEMANTIC_COLOR) {
502 info->input_interpolate[i] = TGSI_INTERPOLATE_COLOR;
503 break;
504 }
505 /* fall-through */
506
507 case INTERP_MODE_SMOOTH:
508 assert(!glsl_base_type_is_integer(base_type));
509
510 info->input_interpolate[i] = TGSI_INTERPOLATE_PERSPECTIVE;
511 break;
512
513 case INTERP_MODE_NOPERSPECTIVE:
514 assert(!glsl_base_type_is_integer(base_type));
515
516 info->input_interpolate[i] = TGSI_INTERPOLATE_LINEAR;
517 break;
518
519 case INTERP_MODE_FLAT:
520 info->input_interpolate[i] = TGSI_INTERPOLATE_CONSTANT;
521 break;
522 }
523 }
524 }
525
526 info->num_inputs = num_inputs;
527
528 i = 0;
529 uint64_t processed_outputs = 0;
530 unsigned num_outputs = 0;
531 nir_foreach_variable(variable, &nir->outputs) {
532 unsigned semantic_name, semantic_index;
533
534 i = variable->data.driver_location;
535
536 const struct glsl_type *type = variable->type;
537 if (nir_is_per_vertex_io(variable, nir->info.stage)) {
538 assert(glsl_type_is_array(type));
539 type = glsl_get_array_element(type);
540 }
541
542 unsigned attrib_count = glsl_count_attribute_slots(type, false);
543 for (unsigned k = 0; k < attrib_count; k++, i++) {
544
545 if (nir->info.stage == MESA_SHADER_FRAGMENT) {
546 tgsi_get_gl_frag_result_semantic(variable->data.location + k,
547 &semantic_name, &semantic_index);
548
549 /* Adjust for dual source blending */
550 if (variable->data.index > 0) {
551 semantic_index++;
552 }
553 } else {
554 tgsi_get_gl_varying_semantic(variable->data.location + k, true,
555 &semantic_name, &semantic_index);
556 }
557
558 unsigned num_components = 4;
559 unsigned vector_elements = glsl_get_vector_elements(glsl_without_array(variable->type));
560 if (vector_elements)
561 num_components = vector_elements;
562
563 unsigned component = variable->data.location_frac;
564 if (glsl_type_is_64bit(glsl_without_array(variable->type))) {
565 if (glsl_type_is_dual_slot(glsl_without_array(variable->type)) && k % 2) {
566 num_components = (num_components * 2) - 4;
567 component = 0;
568 } else {
569 num_components = MIN2(num_components * 2, 4);
570 }
571 }
572
573 ubyte usagemask = 0;
574 for (unsigned j = component; j < num_components + component; j++) {
575 switch (j) {
576 case 0:
577 usagemask |= TGSI_WRITEMASK_X;
578 break;
579 case 1:
580 usagemask |= TGSI_WRITEMASK_Y;
581 break;
582 case 2:
583 usagemask |= TGSI_WRITEMASK_Z;
584 break;
585 case 3:
586 usagemask |= TGSI_WRITEMASK_W;
587 break;
588 default:
589 unreachable("error calculating component index");
590 }
591 }
592
593 unsigned gs_out_streams;
594 if (variable->data.stream & (1u << 31)) {
595 gs_out_streams = variable->data.stream & ~(1u << 31);
596 } else {
597 assert(variable->data.stream < 4);
598 gs_out_streams = 0;
599 for (unsigned j = 0; j < num_components; ++j)
600 gs_out_streams |= variable->data.stream << (2 * (component + j));
601 }
602
603 unsigned streamx = gs_out_streams & 3;
604 unsigned streamy = (gs_out_streams >> 2) & 3;
605 unsigned streamz = (gs_out_streams >> 4) & 3;
606 unsigned streamw = (gs_out_streams >> 6) & 3;
607
608 if (usagemask & TGSI_WRITEMASK_X) {
609 info->output_usagemask[i] |= TGSI_WRITEMASK_X;
610 info->output_streams[i] |= streamx;
611 info->num_stream_output_components[streamx]++;
612 }
613 if (usagemask & TGSI_WRITEMASK_Y) {
614 info->output_usagemask[i] |= TGSI_WRITEMASK_Y;
615 info->output_streams[i] |= streamy << 2;
616 info->num_stream_output_components[streamy]++;
617 }
618 if (usagemask & TGSI_WRITEMASK_Z) {
619 info->output_usagemask[i] |= TGSI_WRITEMASK_Z;
620 info->output_streams[i] |= streamz << 4;
621 info->num_stream_output_components[streamz]++;
622 }
623 if (usagemask & TGSI_WRITEMASK_W) {
624 info->output_usagemask[i] |= TGSI_WRITEMASK_W;
625 info->output_streams[i] |= streamw << 6;
626 info->num_stream_output_components[streamw]++;
627 }
628
629 /* make sure we only count this location once against
630 * the num_outputs counter.
631 */
632 if (processed_outputs & ((uint64_t)1 << i))
633 continue;
634
635 processed_outputs |= ((uint64_t)1 << i);
636 num_outputs++;
637
638 info->output_semantic_name[i] = semantic_name;
639 info->output_semantic_index[i] = semantic_index;
640
641 switch (semantic_name) {
642 case TGSI_SEMANTIC_PRIMID:
643 info->writes_primid = true;
644 break;
645 case TGSI_SEMANTIC_VIEWPORT_INDEX:
646 info->writes_viewport_index = true;
647 break;
648 case TGSI_SEMANTIC_LAYER:
649 info->writes_layer = true;
650 break;
651 case TGSI_SEMANTIC_PSIZE:
652 info->writes_psize = true;
653 break;
654 case TGSI_SEMANTIC_CLIPVERTEX:
655 info->writes_clipvertex = true;
656 break;
657 case TGSI_SEMANTIC_COLOR:
658 info->colors_written |= 1 << semantic_index;
659 break;
660 case TGSI_SEMANTIC_STENCIL:
661 info->writes_stencil = true;
662 break;
663 case TGSI_SEMANTIC_SAMPLEMASK:
664 info->writes_samplemask = true;
665 break;
666 case TGSI_SEMANTIC_EDGEFLAG:
667 info->writes_edgeflag = true;
668 break;
669 case TGSI_SEMANTIC_POSITION:
670 if (info->processor == PIPE_SHADER_FRAGMENT)
671 info->writes_z = true;
672 else
673 info->writes_position = true;
674 break;
675 }
676 }
677
678 unsigned loc = variable->data.location;
679 if (nir->info.stage == MESA_SHADER_FRAGMENT &&
680 loc == FRAG_RESULT_COLOR &&
681 nir->info.outputs_written & (1ull << loc)) {
682 assert(attrib_count == 1);
683 info->properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS] = true;
684 }
685 }
686
687 info->num_outputs = num_outputs;
688
689 struct set *ubo_set = _mesa_set_create(NULL, _mesa_hash_pointer,
690 _mesa_key_pointer_equal);
691 struct set *ssbo_set = _mesa_set_create(NULL, _mesa_hash_pointer,
692 _mesa_key_pointer_equal);
693
694 /* Intialise const_file_max[0] */
695 info->const_file_max[0] = -1;
696
697 /* The first 8 are reserved for atomic counters using ssbo */
698 unsigned ssbo_idx = 8;
699
700 unsigned ubo_idx = 1;
701 nir_foreach_variable(variable, &nir->uniforms) {
702 const struct glsl_type *type = variable->type;
703 enum glsl_base_type base_type =
704 glsl_get_base_type(glsl_without_array(type));
705 unsigned aoa_size = MAX2(1, glsl_get_aoa_size(type));
706 unsigned loc = variable->data.driver_location / 4;
707 int slot_count = glsl_count_attribute_slots(type, false);
708 int max_slot = MAX2(info->const_file_max[0], (int) loc) + slot_count;
709
710 /* Gather buffers declared bitmasks. Note: radeonsi doesn't
711 * really use the mask (other than ubo_idx == 1 for regular
712 * uniforms) its really only used for getting the buffer count
713 * so we don't need to worry about the ordering.
714 */
715 if (variable->interface_type != NULL) {
716 if (variable->data.mode == nir_var_uniform ||
717 variable->data.mode == nir_var_mem_ubo ||
718 variable->data.mode == nir_var_mem_ssbo) {
719
720 struct set *buf_set = variable->data.mode == nir_var_mem_ssbo ?
721 ssbo_set : ubo_set;
722
723 unsigned block_count;
724 if (base_type != GLSL_TYPE_INTERFACE) {
725 struct set_entry *entry =
726 _mesa_set_search(buf_set, variable->interface_type);
727
728 /* Check if we have already processed
729 * a member from this ubo.
730 */
731 if (entry)
732 continue;
733
734 block_count = 1;
735 } else {
736 block_count = aoa_size;
737 }
738
739 if (variable->data.mode == nir_var_uniform ||
740 variable->data.mode == nir_var_mem_ubo) {
741 info->const_buffers_declared |= u_bit_consecutive(ubo_idx, block_count);
742 ubo_idx += block_count;
743 } else {
744 assert(variable->data.mode == nir_var_mem_ssbo);
745
746 info->shader_buffers_declared |= u_bit_consecutive(ssbo_idx, block_count);
747 ssbo_idx += block_count;
748 }
749
750 _mesa_set_add(buf_set, variable->interface_type);
751 }
752
753 continue;
754 }
755
756 /* We rely on the fact that nir_lower_samplers_as_deref has
757 * eliminated struct dereferences.
758 */
759 if (base_type == GLSL_TYPE_SAMPLER && !variable->data.bindless) {
760 info->samplers_declared |=
761 u_bit_consecutive(variable->data.binding, aoa_size);
762 } else if (base_type == GLSL_TYPE_IMAGE && !variable->data.bindless) {
763 info->images_declared |=
764 u_bit_consecutive(variable->data.binding, aoa_size);
765 } else if (base_type != GLSL_TYPE_ATOMIC_UINT) {
766 info->const_buffers_declared |= 1;
767 info->const_file_max[0] = max_slot;
768 }
769 }
770
771 _mesa_set_destroy(ubo_set, NULL);
772 _mesa_set_destroy(ssbo_set, NULL);
773
774 info->num_written_clipdistance = nir->info.clip_distance_array_size;
775 info->num_written_culldistance = nir->info.cull_distance_array_size;
776 info->clipdist_writemask = u_bit_consecutive(0, info->num_written_clipdistance);
777 info->culldist_writemask = u_bit_consecutive(0, info->num_written_culldistance);
778
779 if (info->processor == PIPE_SHADER_FRAGMENT)
780 info->uses_kill = nir->info.fs.uses_discard;
781
782 func = (struct nir_function *)exec_list_get_head_const(&nir->functions);
783 nir_foreach_block(block, func->impl) {
784 nir_foreach_instr(instr, block)
785 scan_instruction(nir, info, instr);
786 }
787 }
788
789 void
790 si_nir_opts(struct nir_shader *nir)
791 {
792 bool progress;
793 unsigned lower_flrp =
794 (nir->options->lower_flrp16 ? 16 : 0) |
795 (nir->options->lower_flrp32 ? 32 : 0) |
796 (nir->options->lower_flrp64 ? 64 : 0);
797
798 do {
799 progress = false;
800
801 NIR_PASS_V(nir, nir_lower_vars_to_ssa);
802
803 NIR_PASS(progress, nir, nir_opt_copy_prop_vars);
804 NIR_PASS(progress, nir, nir_opt_dead_write_vars);
805
806 NIR_PASS_V(nir, nir_lower_alu_to_scalar, NULL);
807 NIR_PASS_V(nir, nir_lower_phis_to_scalar);
808
809 /* (Constant) copy propagation is needed for txf with offsets. */
810 NIR_PASS(progress, nir, nir_copy_prop);
811 NIR_PASS(progress, nir, nir_opt_remove_phis);
812 NIR_PASS(progress, nir, nir_opt_dce);
813 if (nir_opt_trivial_continues(nir)) {
814 progress = true;
815 NIR_PASS(progress, nir, nir_copy_prop);
816 NIR_PASS(progress, nir, nir_opt_dce);
817 }
818 NIR_PASS(progress, nir, nir_opt_if, true);
819 NIR_PASS(progress, nir, nir_opt_dead_cf);
820 NIR_PASS(progress, nir, nir_opt_cse);
821 NIR_PASS(progress, nir, nir_opt_peephole_select, 8, true, true);
822
823 /* Needed for algebraic lowering */
824 NIR_PASS(progress, nir, nir_opt_algebraic);
825 NIR_PASS(progress, nir, nir_opt_constant_folding);
826
827 if (lower_flrp != 0) {
828 bool lower_flrp_progress = false;
829
830 NIR_PASS(lower_flrp_progress, nir, nir_lower_flrp,
831 lower_flrp,
832 false /* always_precise */,
833 nir->options->lower_ffma);
834 if (lower_flrp_progress) {
835 NIR_PASS(progress, nir,
836 nir_opt_constant_folding);
837 progress = true;
838 }
839
840 /* Nothing should rematerialize any flrps, so we only
841 * need to do this lowering once.
842 */
843 lower_flrp = 0;
844 }
845
846 NIR_PASS(progress, nir, nir_opt_undef);
847 NIR_PASS(progress, nir, nir_opt_conditional_discard);
848 if (nir->options->max_unroll_iterations) {
849 NIR_PASS(progress, nir, nir_opt_loop_unroll, 0);
850 }
851 } while (progress);
852 }
853
854 static int
855 type_size_vec4(const struct glsl_type *type, bool bindless)
856 {
857 return glsl_count_attribute_slots(type, false);
858 }
859
860 static void
861 si_nir_lower_color(nir_shader *nir)
862 {
863 nir_function_impl *entrypoint = nir_shader_get_entrypoint(nir);
864
865 nir_builder b;
866 nir_builder_init(&b, entrypoint);
867
868 nir_foreach_block(block, entrypoint) {
869 nir_foreach_instr_safe(instr, block) {
870 if (instr->type != nir_instr_type_intrinsic)
871 continue;
872
873 nir_intrinsic_instr *intrin =
874 nir_instr_as_intrinsic(instr);
875
876 if (intrin->intrinsic != nir_intrinsic_load_deref)
877 continue;
878
879 nir_deref_instr *deref = nir_src_as_deref(intrin->src[0]);
880 if (deref->mode != nir_var_shader_in)
881 continue;
882
883 b.cursor = nir_before_instr(instr);
884 nir_variable *var = nir_deref_instr_get_variable(deref);
885 nir_ssa_def *def;
886
887 if (var->data.location == VARYING_SLOT_COL0) {
888 def = nir_load_color0(&b);
889 } else if (var->data.location == VARYING_SLOT_COL1) {
890 def = nir_load_color1(&b);
891 } else {
892 continue;
893 }
894
895 nir_ssa_def_rewrite_uses(&intrin->dest.ssa, nir_src_for_ssa(def));
896 nir_instr_remove(instr);
897 }
898 }
899 }
900
901 /**
902 * Perform "lowering" operations on the NIR that are run once when the shader
903 * selector is created.
904 */
905 void
906 si_lower_nir(struct si_shader_selector* sel, unsigned wave_size)
907 {
908 /* Adjust the driver location of inputs and outputs. The state tracker
909 * interprets them as slots, while the ac/nir backend interprets them
910 * as individual components.
911 */
912 if (sel->nir->info.stage != MESA_SHADER_FRAGMENT) {
913 nir_foreach_variable(variable, &sel->nir->inputs)
914 variable->data.driver_location *= 4;
915 } else {
916 NIR_PASS_V(sel->nir, nir_lower_io_to_temporaries,
917 nir_shader_get_entrypoint(sel->nir), false, true);
918
919 /* Since we're doing nir_lower_io_to_temporaries late, we need
920 * to lower all the copy_deref's introduced by
921 * lower_io_to_temporaries before calling nir_lower_io.
922 */
923 NIR_PASS_V(sel->nir, nir_split_var_copies);
924 NIR_PASS_V(sel->nir, nir_lower_var_copies);
925 NIR_PASS_V(sel->nir, nir_lower_global_vars_to_local);
926
927 si_nir_lower_color(sel->nir);
928 NIR_PASS_V(sel->nir, nir_lower_io, nir_var_shader_in, type_size_vec4, 0);
929
930 /* This pass needs actual constants */
931 NIR_PASS_V(sel->nir, nir_opt_constant_folding);
932 NIR_PASS_V(sel->nir, nir_io_add_const_offset_to_base,
933 nir_var_shader_in);
934 }
935
936 nir_foreach_variable(variable, &sel->nir->outputs) {
937 variable->data.driver_location *= 4;
938
939 if (sel->nir->info.stage == MESA_SHADER_FRAGMENT) {
940 if (variable->data.location == FRAG_RESULT_DEPTH)
941 variable->data.driver_location += 2;
942 else if (variable->data.location == FRAG_RESULT_STENCIL)
943 variable->data.driver_location += 1;
944 }
945 }
946
947 /* Perform lowerings (and optimizations) of code.
948 *
949 * Performance considerations aside, we must:
950 * - lower certain ALU operations
951 * - ensure constant offsets for texture instructions are folded
952 * and copy-propagated
953 */
954
955 static const struct nir_lower_tex_options lower_tex_options = {
956 .lower_txp = ~0u,
957 };
958 NIR_PASS_V(sel->nir, nir_lower_tex, &lower_tex_options);
959
960 const nir_lower_subgroups_options subgroups_options = {
961 .subgroup_size = wave_size,
962 .ballot_bit_size = wave_size,
963 .lower_to_scalar = true,
964 .lower_subgroup_masks = true,
965 .lower_vote_trivial = false,
966 .lower_vote_eq_to_ballot = true,
967 };
968 NIR_PASS_V(sel->nir, nir_lower_subgroups, &subgroups_options);
969
970 ac_lower_indirect_derefs(sel->nir, sel->screen->info.chip_class);
971
972 si_nir_opts(sel->nir);
973
974 NIR_PASS_V(sel->nir, nir_lower_bool_to_int32);
975
976 /* Strip the resulting shader so that the shader cache is more likely
977 * to hit from other similar shaders.
978 */
979 nir_strip(sel->nir);
980 }
981
982 static void declare_nir_input_vs(struct si_shader_context *ctx,
983 struct nir_variable *variable,
984 unsigned input_index,
985 LLVMValueRef out[4])
986 {
987 si_llvm_load_input_vs(ctx, input_index, out);
988 }
989
990 LLVMValueRef
991 si_nir_lookup_interp_param(struct ac_shader_abi *abi,
992 enum glsl_interp_mode interp, unsigned location)
993 {
994 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
995 int interp_param_idx = -1;
996
997 switch (interp) {
998 case INTERP_MODE_FLAT:
999 return NULL;
1000 case INTERP_MODE_SMOOTH:
1001 case INTERP_MODE_NONE:
1002 if (location == INTERP_CENTER)
1003 interp_param_idx = SI_PARAM_PERSP_CENTER;
1004 else if (location == INTERP_CENTROID)
1005 interp_param_idx = SI_PARAM_PERSP_CENTROID;
1006 else if (location == INTERP_SAMPLE)
1007 interp_param_idx = SI_PARAM_PERSP_SAMPLE;
1008 break;
1009 case INTERP_MODE_NOPERSPECTIVE:
1010 if (location == INTERP_CENTER)
1011 interp_param_idx = SI_PARAM_LINEAR_CENTER;
1012 else if (location == INTERP_CENTROID)
1013 interp_param_idx = SI_PARAM_LINEAR_CENTROID;
1014 else if (location == INTERP_SAMPLE)
1015 interp_param_idx = SI_PARAM_LINEAR_SAMPLE;
1016 break;
1017 default:
1018 assert(!"Unhandled interpolation mode.");
1019 return NULL;
1020 }
1021
1022 return interp_param_idx != -1 ?
1023 LLVMGetParam(ctx->main_fn, interp_param_idx) : NULL;
1024 }
1025
1026 static LLVMValueRef
1027 si_nir_load_sampler_desc(struct ac_shader_abi *abi,
1028 unsigned descriptor_set, unsigned base_index,
1029 unsigned constant_index, LLVMValueRef dynamic_index,
1030 enum ac_descriptor_type desc_type, bool image,
1031 bool write, bool bindless)
1032 {
1033 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1034 LLVMBuilderRef builder = ctx->ac.builder;
1035 unsigned const_index = base_index + constant_index;
1036
1037 assert(!descriptor_set);
1038 assert(!image || desc_type == AC_DESC_IMAGE || desc_type == AC_DESC_BUFFER);
1039
1040 if (bindless) {
1041 LLVMValueRef list =
1042 LLVMGetParam(ctx->main_fn, ctx->param_bindless_samplers_and_images);
1043
1044 /* dynamic_index is the bindless handle */
1045 if (image) {
1046 /* For simplicity, bindless image descriptors use fixed
1047 * 16-dword slots for now.
1048 */
1049 dynamic_index = LLVMBuildMul(ctx->ac.builder, dynamic_index,
1050 LLVMConstInt(ctx->i64, 2, 0), "");
1051
1052 return si_load_image_desc(ctx, list, dynamic_index, desc_type,
1053 write, true);
1054 }
1055
1056 /* Since bindless handle arithmetic can contain an unsigned integer
1057 * wraparound and si_load_sampler_desc assumes there isn't any,
1058 * use GEP without "inbounds" (inside ac_build_pointer_add)
1059 * to prevent incorrect code generation and hangs.
1060 */
1061 dynamic_index = LLVMBuildMul(ctx->ac.builder, dynamic_index,
1062 LLVMConstInt(ctx->i64, 2, 0), "");
1063 list = ac_build_pointer_add(&ctx->ac, list, dynamic_index);
1064 return si_load_sampler_desc(ctx, list, ctx->i32_0, desc_type);
1065 }
1066
1067 unsigned num_slots = image ? ctx->num_images : ctx->num_samplers;
1068 assert(const_index < num_slots);
1069
1070 LLVMValueRef list = LLVMGetParam(ctx->main_fn, ctx->param_samplers_and_images);
1071 LLVMValueRef index = LLVMConstInt(ctx->ac.i32, const_index, false);
1072
1073 if (dynamic_index) {
1074 index = LLVMBuildAdd(builder, index, dynamic_index, "");
1075
1076 /* From the GL_ARB_shader_image_load_store extension spec:
1077 *
1078 * If a shader performs an image load, store, or atomic
1079 * operation using an image variable declared as an array,
1080 * and if the index used to select an individual element is
1081 * negative or greater than or equal to the size of the
1082 * array, the results of the operation are undefined but may
1083 * not lead to termination.
1084 */
1085 index = si_llvm_bound_index(ctx, index, num_slots);
1086 }
1087
1088 if (image) {
1089 index = LLVMBuildSub(ctx->ac.builder,
1090 LLVMConstInt(ctx->i32, SI_NUM_IMAGES - 1, 0),
1091 index, "");
1092 return si_load_image_desc(ctx, list, index, desc_type, write, false);
1093 }
1094
1095 index = LLVMBuildAdd(ctx->ac.builder, index,
1096 LLVMConstInt(ctx->i32, SI_NUM_IMAGES / 2, 0), "");
1097 return si_load_sampler_desc(ctx, list, index, desc_type);
1098 }
1099
1100 static void bitcast_inputs(struct si_shader_context *ctx,
1101 LLVMValueRef data[4],
1102 unsigned input_idx)
1103 {
1104 for (unsigned chan = 0; chan < 4; chan++) {
1105 ctx->inputs[input_idx + chan] =
1106 LLVMBuildBitCast(ctx->ac.builder, data[chan], ctx->ac.i32, "");
1107 }
1108 }
1109
1110 bool si_nir_build_llvm(struct si_shader_context *ctx, struct nir_shader *nir)
1111 {
1112 struct tgsi_shader_info *info = &ctx->shader->selector->info;
1113
1114 if (nir->info.stage == MESA_SHADER_VERTEX) {
1115 uint64_t processed_inputs = 0;
1116 nir_foreach_variable(variable, &nir->inputs) {
1117 unsigned attrib_count = glsl_count_attribute_slots(variable->type,
1118 true);
1119 unsigned input_idx = variable->data.driver_location;
1120
1121 LLVMValueRef data[4];
1122 unsigned loc = variable->data.location;
1123
1124 for (unsigned i = 0; i < attrib_count; i++) {
1125 /* Packed components share the same location so skip
1126 * them if we have already processed the location.
1127 */
1128 if (processed_inputs & ((uint64_t)1 << (loc + i))) {
1129 input_idx += 4;
1130 continue;
1131 }
1132
1133 declare_nir_input_vs(ctx, variable, input_idx / 4, data);
1134 bitcast_inputs(ctx, data, input_idx);
1135 if (glsl_type_is_dual_slot(variable->type)) {
1136 input_idx += 4;
1137 declare_nir_input_vs(ctx, variable, input_idx / 4, data);
1138 bitcast_inputs(ctx, data, input_idx);
1139 }
1140
1141 processed_inputs |= ((uint64_t)1 << (loc + i));
1142 input_idx += 4;
1143 }
1144 }
1145 } else if (nir->info.stage == MESA_SHADER_FRAGMENT) {
1146 unsigned colors_read =
1147 ctx->shader->selector->info.colors_read;
1148 LLVMValueRef main_fn = ctx->main_fn;
1149
1150 LLVMValueRef undef = LLVMGetUndef(ctx->f32);
1151
1152 unsigned offset = SI_PARAM_POS_FIXED_PT + 1;
1153
1154 if (colors_read & 0x0f) {
1155 unsigned mask = colors_read & 0x0f;
1156 LLVMValueRef values[4];
1157 values[0] = mask & 0x1 ? LLVMGetParam(main_fn, offset++) : undef;
1158 values[1] = mask & 0x2 ? LLVMGetParam(main_fn, offset++) : undef;
1159 values[2] = mask & 0x4 ? LLVMGetParam(main_fn, offset++) : undef;
1160 values[3] = mask & 0x8 ? LLVMGetParam(main_fn, offset++) : undef;
1161 ctx->abi.color0 =
1162 ac_to_integer(&ctx->ac,
1163 ac_build_gather_values(&ctx->ac, values, 4));
1164 }
1165 if (colors_read & 0xf0) {
1166 unsigned mask = (colors_read & 0xf0) >> 4;
1167 LLVMValueRef values[4];
1168 values[0] = mask & 0x1 ? LLVMGetParam(main_fn, offset++) : undef;
1169 values[1] = mask & 0x2 ? LLVMGetParam(main_fn, offset++) : undef;
1170 values[2] = mask & 0x4 ? LLVMGetParam(main_fn, offset++) : undef;
1171 values[3] = mask & 0x8 ? LLVMGetParam(main_fn, offset++) : undef;
1172 ctx->abi.color1 =
1173 ac_to_integer(&ctx->ac,
1174 ac_build_gather_values(&ctx->ac, values, 4));
1175 }
1176 }
1177
1178 ctx->abi.inputs = &ctx->inputs[0];
1179 ctx->abi.load_sampler_desc = si_nir_load_sampler_desc;
1180 ctx->abi.clamp_shadow_reference = true;
1181
1182 ctx->num_samplers = util_last_bit(info->samplers_declared);
1183 ctx->num_images = util_last_bit(info->images_declared);
1184
1185 if (ctx->shader->selector->info.properties[TGSI_PROPERTY_CS_LOCAL_SIZE]) {
1186 assert(gl_shader_stage_is_compute(nir->info.stage));
1187 si_declare_compute_memory(ctx);
1188 }
1189 ac_nir_translate(&ctx->ac, &ctx->abi, nir);
1190
1191 return true;
1192 }