radeonsi: gather stream info in nir path
[mesa.git] / src / gallium / drivers / radeonsi / si_shader_nir.c
1 /*
2 * Copyright 2017 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23
24 #include "si_shader.h"
25 #include "si_shader_internal.h"
26
27 #include "ac_nir_to_llvm.h"
28
29 #include "tgsi/tgsi_from_mesa.h"
30
31 #include "compiler/nir/nir.h"
32 #include "compiler/nir_types.h"
33
34
35 static int
36 type_size(const struct glsl_type *type)
37 {
38 return glsl_count_attribute_slots(type, false);
39 }
40
41 static void scan_instruction(struct tgsi_shader_info *info,
42 nir_instr *instr)
43 {
44 if (instr->type == nir_instr_type_alu) {
45 nir_alu_instr *alu = nir_instr_as_alu(instr);
46
47 switch (alu->op) {
48 case nir_op_fddx:
49 case nir_op_fddy:
50 case nir_op_fddx_fine:
51 case nir_op_fddy_fine:
52 case nir_op_fddx_coarse:
53 case nir_op_fddy_coarse:
54 info->uses_derivatives = true;
55 break;
56 default:
57 break;
58 }
59 } else if (instr->type == nir_instr_type_tex) {
60 nir_tex_instr *tex = nir_instr_as_tex(instr);
61
62 if (!tex->texture) {
63 info->samplers_declared |=
64 u_bit_consecutive(tex->sampler_index, 1);
65 }
66
67 switch (tex->op) {
68 case nir_texop_tex:
69 case nir_texop_txb:
70 case nir_texop_lod:
71 info->uses_derivatives = true;
72 break;
73 default:
74 break;
75 }
76 } else if (instr->type == nir_instr_type_intrinsic) {
77 nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);
78
79 switch (intr->intrinsic) {
80 case nir_intrinsic_load_front_face:
81 info->uses_frontface = 1;
82 break;
83 case nir_intrinsic_load_instance_id:
84 info->uses_instanceid = 1;
85 break;
86 case nir_intrinsic_load_vertex_id:
87 info->uses_vertexid = 1;
88 break;
89 case nir_intrinsic_load_vertex_id_zero_base:
90 info->uses_vertexid_nobase = 1;
91 break;
92 case nir_intrinsic_load_base_vertex:
93 info->uses_basevertex = 1;
94 break;
95 case nir_intrinsic_load_primitive_id:
96 info->uses_primid = 1;
97 break;
98 case nir_intrinsic_image_store:
99 case nir_intrinsic_image_atomic_add:
100 case nir_intrinsic_image_atomic_min:
101 case nir_intrinsic_image_atomic_max:
102 case nir_intrinsic_image_atomic_and:
103 case nir_intrinsic_image_atomic_or:
104 case nir_intrinsic_image_atomic_xor:
105 case nir_intrinsic_image_atomic_exchange:
106 case nir_intrinsic_image_atomic_comp_swap:
107 case nir_intrinsic_store_ssbo:
108 case nir_intrinsic_ssbo_atomic_add:
109 case nir_intrinsic_ssbo_atomic_imin:
110 case nir_intrinsic_ssbo_atomic_umin:
111 case nir_intrinsic_ssbo_atomic_imax:
112 case nir_intrinsic_ssbo_atomic_umax:
113 case nir_intrinsic_ssbo_atomic_and:
114 case nir_intrinsic_ssbo_atomic_or:
115 case nir_intrinsic_ssbo_atomic_xor:
116 case nir_intrinsic_ssbo_atomic_exchange:
117 case nir_intrinsic_ssbo_atomic_comp_swap:
118 info->writes_memory = true;
119 break;
120 default:
121 break;
122 }
123 }
124 }
125
126 void si_nir_scan_shader(const struct nir_shader *nir,
127 struct tgsi_shader_info *info)
128 {
129 nir_function *func;
130 unsigned i;
131
132 assert(nir->info.stage == MESA_SHADER_VERTEX ||
133 nir->info.stage == MESA_SHADER_FRAGMENT);
134
135 info->processor = pipe_shader_type_from_mesa(nir->info.stage);
136 info->num_tokens = 2; /* indicate that the shader is non-empty */
137 info->num_instructions = 2;
138
139 info->num_inputs = nir->num_inputs;
140 info->num_outputs = nir->num_outputs;
141
142 i = 0;
143 nir_foreach_variable(variable, &nir->inputs) {
144 unsigned semantic_name, semantic_index;
145 unsigned attrib_count = glsl_count_attribute_slots(variable->type,
146 nir->info.stage == MESA_SHADER_VERTEX);
147
148 assert(attrib_count == 1 && "not implemented");
149
150 /* Vertex shader inputs don't have semantics. The state
151 * tracker has already mapped them to attributes via
152 * variable->data.driver_location.
153 */
154 if (nir->info.stage == MESA_SHADER_VERTEX)
155 continue;
156
157 /* Fragment shader position is a system value. */
158 if (nir->info.stage == MESA_SHADER_FRAGMENT &&
159 variable->data.location == VARYING_SLOT_POS) {
160 if (variable->data.pixel_center_integer)
161 info->properties[TGSI_PROPERTY_FS_COORD_PIXEL_CENTER] =
162 TGSI_FS_COORD_PIXEL_CENTER_INTEGER;
163 continue;
164 }
165
166 tgsi_get_gl_varying_semantic(variable->data.location, true,
167 &semantic_name, &semantic_index);
168
169 info->input_semantic_name[i] = semantic_name;
170 info->input_semantic_index[i] = semantic_index;
171
172 if (variable->data.sample)
173 info->input_interpolate_loc[i] = TGSI_INTERPOLATE_LOC_SAMPLE;
174 else if (variable->data.centroid)
175 info->input_interpolate_loc[i] = TGSI_INTERPOLATE_LOC_CENTROID;
176 else
177 info->input_interpolate_loc[i] = TGSI_INTERPOLATE_LOC_CENTER;
178
179 enum glsl_base_type base_type =
180 glsl_get_base_type(glsl_without_array(variable->type));
181
182 switch (variable->data.interpolation) {
183 case INTERP_MODE_NONE:
184 if (glsl_base_type_is_integer(base_type)) {
185 info->input_interpolate[i] = TGSI_INTERPOLATE_CONSTANT;
186 break;
187 }
188
189 if (semantic_name == TGSI_SEMANTIC_COLOR) {
190 info->input_interpolate[i] = TGSI_INTERPOLATE_COLOR;
191 goto persp_locations;
192 }
193 /* fall-through */
194 case INTERP_MODE_SMOOTH:
195 assert(!glsl_base_type_is_integer(base_type));
196
197 info->input_interpolate[i] = TGSI_INTERPOLATE_PERSPECTIVE;
198
199 persp_locations:
200 if (variable->data.sample)
201 info->uses_persp_sample = true;
202 else if (variable->data.centroid)
203 info->uses_persp_centroid = true;
204 else
205 info->uses_persp_center = true;
206 break;
207
208 case INTERP_MODE_NOPERSPECTIVE:
209 assert(!glsl_base_type_is_integer(base_type));
210
211 info->input_interpolate[i] = TGSI_INTERPOLATE_LINEAR;
212
213 if (variable->data.sample)
214 info->uses_linear_sample = true;
215 else if (variable->data.centroid)
216 info->uses_linear_centroid = true;
217 else
218 info->uses_linear_center = true;
219 break;
220
221 case INTERP_MODE_FLAT:
222 info->input_interpolate[i] = TGSI_INTERPOLATE_CONSTANT;
223 break;
224 }
225
226 /* TODO make this more precise */
227 if (variable->data.location == VARYING_SLOT_COL0)
228 info->colors_read |= 0x0f;
229 else if (variable->data.location == VARYING_SLOT_COL1)
230 info->colors_read |= 0xf0;
231
232 i++;
233 }
234
235 i = 0;
236 nir_foreach_variable(variable, &nir->outputs) {
237 unsigned semantic_name, semantic_index;
238
239 if (nir->info.stage == MESA_SHADER_FRAGMENT) {
240 tgsi_get_gl_frag_result_semantic(variable->data.location,
241 &semantic_name, &semantic_index);
242 } else {
243 tgsi_get_gl_varying_semantic(variable->data.location, true,
244 &semantic_name, &semantic_index);
245 }
246
247 info->output_semantic_name[i] = semantic_name;
248 info->output_semantic_index[i] = semantic_index;
249 info->output_usagemask[i] = TGSI_WRITEMASK_XYZW;
250
251 unsigned num_components = 4;
252 unsigned vector_elements = glsl_get_vector_elements(glsl_without_array(variable->type));
253 if (vector_elements)
254 num_components = vector_elements;
255
256 unsigned gs_out_streams;
257 if (variable->data.stream & (1u << 31)) {
258 gs_out_streams = variable->data.stream & ~(1u << 31);
259 } else {
260 assert(variable->data.stream < 4);
261 gs_out_streams = 0;
262 for (unsigned j = 0; j < num_components; ++j)
263 gs_out_streams |= variable->data.stream << (2 * (variable->data.location_frac + j));
264 }
265
266 unsigned streamx = gs_out_streams & 3;
267 unsigned streamy = (gs_out_streams >> 2) & 3;
268 unsigned streamz = (gs_out_streams >> 4) & 3;
269 unsigned streamw = (gs_out_streams >> 6) & 3;
270
271 if (info->output_usagemask[i] & TGSI_WRITEMASK_X) {
272 info->output_streams[i] |= streamx;
273 info->num_stream_output_components[streamx]++;
274 }
275 if (info->output_usagemask[i] & TGSI_WRITEMASK_Y) {
276 info->output_streams[i] |= streamy << 2;
277 info->num_stream_output_components[streamy]++;
278 }
279 if (info->output_usagemask[i] & TGSI_WRITEMASK_Z) {
280 info->output_streams[i] |= streamz << 4;
281 info->num_stream_output_components[streamz]++;
282 }
283 if (info->output_usagemask[i] & TGSI_WRITEMASK_W) {
284 info->output_streams[i] |= streamw << 6;
285 info->num_stream_output_components[streamw]++;
286 }
287
288 switch (semantic_name) {
289 case TGSI_SEMANTIC_PRIMID:
290 info->writes_primid = true;
291 break;
292 case TGSI_SEMANTIC_VIEWPORT_INDEX:
293 info->writes_viewport_index = true;
294 break;
295 case TGSI_SEMANTIC_LAYER:
296 info->writes_layer = true;
297 break;
298 case TGSI_SEMANTIC_PSIZE:
299 info->writes_psize = true;
300 break;
301 case TGSI_SEMANTIC_CLIPVERTEX:
302 info->writes_clipvertex = true;
303 break;
304 case TGSI_SEMANTIC_COLOR:
305 info->colors_written |= 1 << semantic_index;
306 break;
307 case TGSI_SEMANTIC_STENCIL:
308 info->writes_stencil = true;
309 break;
310 case TGSI_SEMANTIC_SAMPLEMASK:
311 info->writes_samplemask = true;
312 break;
313 case TGSI_SEMANTIC_EDGEFLAG:
314 info->writes_edgeflag = true;
315 break;
316 case TGSI_SEMANTIC_POSITION:
317 if (info->processor == PIPE_SHADER_FRAGMENT)
318 info->writes_z = true;
319 else
320 info->writes_position = true;
321 break;
322 }
323
324 i++;
325 }
326
327 nir_foreach_variable(variable, &nir->uniforms) {
328 const struct glsl_type *type = variable->type;
329 enum glsl_base_type base_type =
330 glsl_get_base_type(glsl_without_array(type));
331 unsigned aoa_size = MAX2(1, glsl_get_aoa_size(type));
332
333 /* We rely on the fact that nir_lower_samplers_as_deref has
334 * eliminated struct dereferences.
335 */
336 if (base_type == GLSL_TYPE_SAMPLER)
337 info->samplers_declared |=
338 u_bit_consecutive(variable->data.binding, aoa_size);
339 else if (base_type == GLSL_TYPE_IMAGE)
340 info->images_declared |=
341 u_bit_consecutive(variable->data.binding, aoa_size);
342 }
343
344 info->num_written_clipdistance = nir->info.clip_distance_array_size;
345 info->num_written_culldistance = nir->info.cull_distance_array_size;
346 info->clipdist_writemask = u_bit_consecutive(0, info->num_written_clipdistance);
347 info->culldist_writemask = u_bit_consecutive(0, info->num_written_culldistance);
348
349 if (info->processor == PIPE_SHADER_FRAGMENT)
350 info->uses_kill = nir->info.fs.uses_discard;
351
352 /* TODO make this more accurate */
353 info->const_buffers_declared = u_bit_consecutive(0, SI_NUM_CONST_BUFFERS);
354 info->shader_buffers_declared = u_bit_consecutive(0, SI_NUM_SHADER_BUFFERS);
355
356 func = (struct nir_function *)exec_list_get_head_const(&nir->functions);
357 nir_foreach_block(block, func->impl) {
358 nir_foreach_instr(instr, block)
359 scan_instruction(info, instr);
360 }
361 }
362
363 /**
364 * Perform "lowering" operations on the NIR that are run once when the shader
365 * selector is created.
366 */
367 void
368 si_lower_nir(struct si_shader_selector* sel)
369 {
370 /* Adjust the driver location of inputs and outputs. The state tracker
371 * interprets them as slots, while the ac/nir backend interprets them
372 * as individual components.
373 */
374 nir_foreach_variable(variable, &sel->nir->inputs)
375 variable->data.driver_location *= 4;
376
377 nir_foreach_variable(variable, &sel->nir->outputs) {
378 variable->data.driver_location *= 4;
379
380 if (sel->nir->info.stage == MESA_SHADER_FRAGMENT) {
381 if (variable->data.location == FRAG_RESULT_DEPTH)
382 variable->data.driver_location += 2;
383 else if (variable->data.location == FRAG_RESULT_STENCIL)
384 variable->data.driver_location += 1;
385 }
386 }
387
388 /* Perform lowerings (and optimizations) of code.
389 *
390 * Performance considerations aside, we must:
391 * - lower certain ALU operations
392 * - ensure constant offsets for texture instructions are folded
393 * and copy-propagated
394 */
395 NIR_PASS_V(sel->nir, nir_lower_io, nir_var_uniform, type_size,
396 (nir_lower_io_options)0);
397 NIR_PASS_V(sel->nir, nir_lower_uniforms_to_ubo);
398
399 NIR_PASS_V(sel->nir, nir_lower_returns);
400 NIR_PASS_V(sel->nir, nir_lower_vars_to_ssa);
401 NIR_PASS_V(sel->nir, nir_lower_alu_to_scalar);
402 NIR_PASS_V(sel->nir, nir_lower_phis_to_scalar);
403
404 static const struct nir_lower_tex_options lower_tex_options = {
405 .lower_txp = ~0u,
406 };
407 NIR_PASS_V(sel->nir, nir_lower_tex, &lower_tex_options);
408
409 bool progress;
410 do {
411 progress = false;
412
413 /* (Constant) copy propagation is needed for txf with offsets. */
414 NIR_PASS(progress, sel->nir, nir_copy_prop);
415 NIR_PASS(progress, sel->nir, nir_opt_remove_phis);
416 NIR_PASS(progress, sel->nir, nir_opt_dce);
417 if (nir_opt_trivial_continues(sel->nir)) {
418 progress = true;
419 NIR_PASS(progress, sel->nir, nir_copy_prop);
420 NIR_PASS(progress, sel->nir, nir_opt_dce);
421 }
422 NIR_PASS(progress, sel->nir, nir_opt_if);
423 NIR_PASS(progress, sel->nir, nir_opt_dead_cf);
424 NIR_PASS(progress, sel->nir, nir_opt_cse);
425 NIR_PASS(progress, sel->nir, nir_opt_peephole_select, 8);
426
427 /* Needed for algebraic lowering */
428 NIR_PASS(progress, sel->nir, nir_opt_algebraic);
429 NIR_PASS(progress, sel->nir, nir_opt_constant_folding);
430
431 NIR_PASS(progress, sel->nir, nir_opt_undef);
432 NIR_PASS(progress, sel->nir, nir_opt_conditional_discard);
433 if (sel->nir->options->max_unroll_iterations) {
434 NIR_PASS(progress, sel->nir, nir_opt_loop_unroll, 0);
435 }
436 } while (progress);
437 }
438
439 static void declare_nir_input_vs(struct si_shader_context *ctx,
440 struct nir_variable *variable, unsigned rel,
441 LLVMValueRef out[4])
442 {
443 si_llvm_load_input_vs(ctx, variable->data.driver_location / 4 + rel, out);
444 }
445
446 static void declare_nir_input_fs(struct si_shader_context *ctx,
447 struct nir_variable *variable, unsigned rel,
448 unsigned *fs_attr_idx,
449 LLVMValueRef out[4])
450 {
451 unsigned slot = variable->data.location + rel;
452
453 assert(variable->data.location >= VARYING_SLOT_VAR0 || rel == 0);
454
455 if (slot == VARYING_SLOT_POS) {
456 out[0] = LLVMGetParam(ctx->main_fn, SI_PARAM_POS_X_FLOAT);
457 out[1] = LLVMGetParam(ctx->main_fn, SI_PARAM_POS_Y_FLOAT);
458 out[2] = LLVMGetParam(ctx->main_fn, SI_PARAM_POS_Z_FLOAT);
459 out[3] = ac_build_fdiv(&ctx->ac, ctx->ac.f32_1,
460 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_W_FLOAT));
461 return;
462 }
463
464 si_llvm_load_input_fs(ctx, *fs_attr_idx, out);
465 (*fs_attr_idx)++;
466 }
467
468 static LLVMValueRef
469 si_nir_load_sampler_desc(struct ac_shader_abi *abi,
470 unsigned descriptor_set, unsigned base_index,
471 unsigned constant_index, LLVMValueRef dynamic_index,
472 enum ac_descriptor_type desc_type, bool image,
473 bool write)
474 {
475 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
476 LLVMBuilderRef builder = ctx->ac.builder;
477 LLVMValueRef list = LLVMGetParam(ctx->main_fn, ctx->param_samplers_and_images);
478 LLVMValueRef index = dynamic_index;
479
480 assert(!descriptor_set);
481
482 if (!index)
483 index = ctx->ac.i32_0;
484
485 index = LLVMBuildAdd(builder, index,
486 LLVMConstInt(ctx->ac.i32, base_index + constant_index, false),
487 "");
488
489 if (image) {
490 assert(desc_type == AC_DESC_IMAGE || desc_type == AC_DESC_BUFFER);
491 assert(base_index + constant_index < ctx->num_images);
492
493 if (dynamic_index)
494 index = si_llvm_bound_index(ctx, index, ctx->num_images);
495
496 index = LLVMBuildSub(ctx->gallivm.builder,
497 LLVMConstInt(ctx->i32, SI_NUM_IMAGES - 1, 0),
498 index, "");
499
500 /* TODO: be smarter about when we use dcc_off */
501 return si_load_image_desc(ctx, list, index, desc_type, write);
502 }
503
504 assert(base_index + constant_index < ctx->num_samplers);
505
506 if (dynamic_index)
507 index = si_llvm_bound_index(ctx, index, ctx->num_samplers);
508
509 index = LLVMBuildAdd(ctx->gallivm.builder, index,
510 LLVMConstInt(ctx->i32, SI_NUM_IMAGES / 2, 0), "");
511
512 return si_load_sampler_desc(ctx, list, index, desc_type);
513 }
514
515 bool si_nir_build_llvm(struct si_shader_context *ctx, struct nir_shader *nir)
516 {
517 struct tgsi_shader_info *info = &ctx->shader->selector->info;
518
519 unsigned fs_attr_idx = 0;
520 nir_foreach_variable(variable, &nir->inputs) {
521 unsigned attrib_count = glsl_count_attribute_slots(variable->type,
522 nir->info.stage == MESA_SHADER_VERTEX);
523 unsigned input_idx = variable->data.driver_location;
524
525 for (unsigned i = 0; i < attrib_count; ++i) {
526 LLVMValueRef data[4];
527
528 if (nir->info.stage == MESA_SHADER_VERTEX)
529 declare_nir_input_vs(ctx, variable, i, data);
530 else if (nir->info.stage == MESA_SHADER_FRAGMENT)
531 declare_nir_input_fs(ctx, variable, i, &fs_attr_idx, data);
532
533 for (unsigned chan = 0; chan < 4; chan++) {
534 ctx->inputs[input_idx + chan] =
535 LLVMBuildBitCast(ctx->ac.builder, data[chan], ctx->ac.i32, "");
536 }
537 }
538 }
539
540 ctx->abi.inputs = &ctx->inputs[0];
541 ctx->abi.load_sampler_desc = si_nir_load_sampler_desc;
542 ctx->abi.clamp_shadow_reference = true;
543
544 ctx->num_samplers = util_last_bit(info->samplers_declared);
545 ctx->num_images = util_last_bit(info->images_declared);
546
547 ac_nir_translate(&ctx->ac, &ctx->abi, nir, NULL);
548
549 return true;
550 }