2 * Copyright 2017 Advanced Micro Devices, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
25 #include "si_shader_internal.h"
28 #include "ac_nir_to_llvm.h"
30 #include "tgsi/tgsi_from_mesa.h"
32 #include "compiler/nir/nir.h"
33 #include "compiler/nir_types.h"
35 static nir_variable
* tex_get_texture_var(nir_tex_instr
*instr
)
37 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
38 switch (instr
->src
[i
].src_type
) {
39 case nir_tex_src_texture_deref
:
40 return nir_deref_instr_get_variable(nir_src_as_deref(instr
->src
[i
].src
));
49 static nir_variable
* intrinsic_get_var(nir_intrinsic_instr
*instr
)
51 return nir_deref_instr_get_variable(nir_src_as_deref(instr
->src
[0]));
54 static void scan_instruction(struct tgsi_shader_info
*info
,
57 if (instr
->type
== nir_instr_type_alu
) {
58 nir_alu_instr
*alu
= nir_instr_as_alu(instr
);
63 case nir_op_fddx_fine
:
64 case nir_op_fddy_fine
:
65 case nir_op_fddx_coarse
:
66 case nir_op_fddy_coarse
:
67 info
->uses_derivatives
= true;
72 } else if (instr
->type
== nir_instr_type_tex
) {
73 nir_tex_instr
*tex
= nir_instr_as_tex(instr
);
74 nir_variable
*texture
= tex_get_texture_var(tex
);
77 info
->samplers_declared
|=
78 u_bit_consecutive(tex
->sampler_index
, 1);
80 if (texture
->data
.bindless
)
81 info
->uses_bindless_samplers
= true;
88 info
->uses_derivatives
= true;
93 } else if (instr
->type
== nir_instr_type_intrinsic
) {
94 nir_intrinsic_instr
*intr
= nir_instr_as_intrinsic(instr
);
96 switch (intr
->intrinsic
) {
97 case nir_intrinsic_load_front_face
:
98 info
->uses_frontface
= 1;
100 case nir_intrinsic_load_instance_id
:
101 info
->uses_instanceid
= 1;
103 case nir_intrinsic_load_invocation_id
:
104 info
->uses_invocationid
= true;
106 case nir_intrinsic_load_num_work_groups
:
107 info
->uses_grid_size
= true;
109 case nir_intrinsic_load_local_group_size
:
110 /* The block size is translated to IMM with a fixed block size. */
111 if (info
->properties
[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH
] == 0)
112 info
->uses_block_size
= true;
114 case nir_intrinsic_load_local_invocation_id
:
115 case nir_intrinsic_load_work_group_id
: {
116 unsigned mask
= nir_ssa_def_components_read(&intr
->dest
.ssa
);
118 unsigned i
= u_bit_scan(&mask
);
120 if (intr
->intrinsic
== nir_intrinsic_load_work_group_id
)
121 info
->uses_block_id
[i
] = true;
123 info
->uses_thread_id
[i
] = true;
127 case nir_intrinsic_load_vertex_id
:
128 info
->uses_vertexid
= 1;
130 case nir_intrinsic_load_vertex_id_zero_base
:
131 info
->uses_vertexid_nobase
= 1;
133 case nir_intrinsic_load_base_vertex
:
134 info
->uses_basevertex
= 1;
136 case nir_intrinsic_load_primitive_id
:
137 info
->uses_primid
= 1;
139 case nir_intrinsic_load_sample_mask_in
:
140 info
->reads_samplemask
= true;
142 case nir_intrinsic_load_tess_level_inner
:
143 case nir_intrinsic_load_tess_level_outer
:
144 info
->reads_tess_factors
= true;
146 case nir_intrinsic_image_deref_load
: {
147 nir_variable
*var
= intrinsic_get_var(intr
);
148 if (var
->data
.bindless
) {
149 info
->uses_bindless_images
= true;
151 if (glsl_get_sampler_dim(var
->type
) == GLSL_SAMPLER_DIM_BUF
)
152 info
->uses_bindless_buffer_load
= true;
154 info
->uses_bindless_image_load
= true;
158 case nir_intrinsic_image_deref_size
:
159 case nir_intrinsic_image_deref_samples
: {
160 nir_variable
*var
= intrinsic_get_var(intr
);
161 if (var
->data
.bindless
)
162 info
->uses_bindless_images
= true;
165 case nir_intrinsic_image_deref_store
: {
166 const nir_deref_instr
*image_deref
= nir_instr_as_deref(intr
->src
[0].ssa
->parent_instr
);
167 nir_variable
*var
= intrinsic_get_var(intr
);
168 if (var
->data
.bindless
) {
169 info
->uses_bindless_images
= true;
171 if (glsl_get_sampler_dim(image_deref
->type
) == GLSL_SAMPLER_DIM_BUF
)
172 info
->uses_bindless_buffer_store
= true;
174 info
->uses_bindless_image_store
= true;
176 info
->writes_memory
= true;
179 case nir_intrinsic_image_deref_atomic_add
:
180 case nir_intrinsic_image_deref_atomic_min
:
181 case nir_intrinsic_image_deref_atomic_max
:
182 case nir_intrinsic_image_deref_atomic_and
:
183 case nir_intrinsic_image_deref_atomic_or
:
184 case nir_intrinsic_image_deref_atomic_xor
:
185 case nir_intrinsic_image_deref_atomic_exchange
:
186 case nir_intrinsic_image_deref_atomic_comp_swap
: {
187 nir_variable
*var
= intrinsic_get_var(intr
);
188 if (var
->data
.bindless
) {
189 info
->uses_bindless_images
= true;
191 if (glsl_get_sampler_dim(var
->type
) == GLSL_SAMPLER_DIM_BUF
)
192 info
->uses_bindless_buffer_atomic
= true;
194 info
->uses_bindless_image_atomic
= true;
196 info
->writes_memory
= true;
199 case nir_intrinsic_store_ssbo
:
200 case nir_intrinsic_ssbo_atomic_add
:
201 case nir_intrinsic_ssbo_atomic_imin
:
202 case nir_intrinsic_ssbo_atomic_umin
:
203 case nir_intrinsic_ssbo_atomic_imax
:
204 case nir_intrinsic_ssbo_atomic_umax
:
205 case nir_intrinsic_ssbo_atomic_and
:
206 case nir_intrinsic_ssbo_atomic_or
:
207 case nir_intrinsic_ssbo_atomic_xor
:
208 case nir_intrinsic_ssbo_atomic_exchange
:
209 case nir_intrinsic_ssbo_atomic_comp_swap
:
210 info
->writes_memory
= true;
212 case nir_intrinsic_load_deref
: {
213 nir_variable
*var
= intrinsic_get_var(intr
);
214 nir_variable_mode mode
= var
->data
.mode
;
215 enum glsl_base_type base_type
=
216 glsl_get_base_type(glsl_without_array(var
->type
));
218 if (mode
== nir_var_shader_in
) {
219 switch (var
->data
.interpolation
) {
220 case INTERP_MODE_NONE
:
221 if (glsl_base_type_is_integer(base_type
))
225 case INTERP_MODE_SMOOTH
:
226 if (var
->data
.sample
)
227 info
->uses_persp_sample
= true;
228 else if (var
->data
.centroid
)
229 info
->uses_persp_centroid
= true;
231 info
->uses_persp_center
= true;
234 case INTERP_MODE_NOPERSPECTIVE
:
235 if (var
->data
.sample
)
236 info
->uses_linear_sample
= true;
237 else if (var
->data
.centroid
)
238 info
->uses_linear_centroid
= true;
240 info
->uses_linear_center
= true;
246 case nir_intrinsic_interp_deref_at_centroid
:
247 case nir_intrinsic_interp_deref_at_sample
:
248 case nir_intrinsic_interp_deref_at_offset
: {
249 enum glsl_interp_mode interp
= intrinsic_get_var(intr
)->data
.interpolation
;
251 case INTERP_MODE_SMOOTH
:
252 case INTERP_MODE_NONE
:
253 if (intr
->intrinsic
== nir_intrinsic_interp_deref_at_centroid
)
254 info
->uses_persp_opcode_interp_centroid
= true;
255 else if (intr
->intrinsic
== nir_intrinsic_interp_deref_at_sample
)
256 info
->uses_persp_opcode_interp_sample
= true;
258 info
->uses_persp_opcode_interp_offset
= true;
260 case INTERP_MODE_NOPERSPECTIVE
:
261 if (intr
->intrinsic
== nir_intrinsic_interp_deref_at_centroid
)
262 info
->uses_linear_opcode_interp_centroid
= true;
263 else if (intr
->intrinsic
== nir_intrinsic_interp_deref_at_sample
)
264 info
->uses_linear_opcode_interp_sample
= true;
266 info
->uses_linear_opcode_interp_offset
= true;
268 case INTERP_MODE_FLAT
:
271 unreachable("Unsupported interpoation type");
281 void si_nir_scan_tess_ctrl(const struct nir_shader
*nir
,
282 struct tgsi_tessctrl_info
*out
)
284 memset(out
, 0, sizeof(*out
));
286 if (nir
->info
.stage
!= MESA_SHADER_TESS_CTRL
)
289 out
->tessfactors_are_def_in_all_invocs
=
290 ac_are_tessfactors_def_in_all_invocs(nir
);
293 void si_nir_scan_shader(const struct nir_shader
*nir
,
294 struct tgsi_shader_info
*info
)
299 info
->processor
= pipe_shader_type_from_mesa(nir
->info
.stage
);
300 info
->num_tokens
= 2; /* indicate that the shader is non-empty */
301 info
->num_instructions
= 2;
303 info
->properties
[TGSI_PROPERTY_NEXT_SHADER
] =
304 pipe_shader_type_from_mesa(nir
->info
.next_stage
);
306 if (nir
->info
.stage
== MESA_SHADER_TESS_CTRL
) {
307 info
->properties
[TGSI_PROPERTY_TCS_VERTICES_OUT
] =
308 nir
->info
.tess
.tcs_vertices_out
;
311 if (nir
->info
.stage
== MESA_SHADER_TESS_EVAL
) {
312 if (nir
->info
.tess
.primitive_mode
== GL_ISOLINES
)
313 info
->properties
[TGSI_PROPERTY_TES_PRIM_MODE
] = PIPE_PRIM_LINES
;
315 info
->properties
[TGSI_PROPERTY_TES_PRIM_MODE
] = nir
->info
.tess
.primitive_mode
;
317 STATIC_ASSERT((TESS_SPACING_EQUAL
+ 1) % 3 == PIPE_TESS_SPACING_EQUAL
);
318 STATIC_ASSERT((TESS_SPACING_FRACTIONAL_ODD
+ 1) % 3 ==
319 PIPE_TESS_SPACING_FRACTIONAL_ODD
);
320 STATIC_ASSERT((TESS_SPACING_FRACTIONAL_EVEN
+ 1) % 3 ==
321 PIPE_TESS_SPACING_FRACTIONAL_EVEN
);
323 info
->properties
[TGSI_PROPERTY_TES_SPACING
] = (nir
->info
.tess
.spacing
+ 1) % 3;
324 info
->properties
[TGSI_PROPERTY_TES_VERTEX_ORDER_CW
] = !nir
->info
.tess
.ccw
;
325 info
->properties
[TGSI_PROPERTY_TES_POINT_MODE
] = nir
->info
.tess
.point_mode
;
328 if (nir
->info
.stage
== MESA_SHADER_GEOMETRY
) {
329 info
->properties
[TGSI_PROPERTY_GS_INPUT_PRIM
] = nir
->info
.gs
.input_primitive
;
330 info
->properties
[TGSI_PROPERTY_GS_OUTPUT_PRIM
] = nir
->info
.gs
.output_primitive
;
331 info
->properties
[TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES
] = nir
->info
.gs
.vertices_out
;
332 info
->properties
[TGSI_PROPERTY_GS_INVOCATIONS
] = nir
->info
.gs
.invocations
;
335 if (nir
->info
.stage
== MESA_SHADER_FRAGMENT
) {
336 info
->properties
[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL
] =
337 nir
->info
.fs
.early_fragment_tests
| nir
->info
.fs
.post_depth_coverage
;
338 info
->properties
[TGSI_PROPERTY_FS_POST_DEPTH_COVERAGE
] = nir
->info
.fs
.post_depth_coverage
;
340 if (nir
->info
.fs
.pixel_center_integer
) {
341 info
->properties
[TGSI_PROPERTY_FS_COORD_PIXEL_CENTER
] =
342 TGSI_FS_COORD_PIXEL_CENTER_INTEGER
;
345 if (nir
->info
.fs
.depth_layout
!= FRAG_DEPTH_LAYOUT_NONE
) {
346 switch (nir
->info
.fs
.depth_layout
) {
347 case FRAG_DEPTH_LAYOUT_ANY
:
348 info
->properties
[TGSI_PROPERTY_FS_DEPTH_LAYOUT
] = TGSI_FS_DEPTH_LAYOUT_ANY
;
350 case FRAG_DEPTH_LAYOUT_GREATER
:
351 info
->properties
[TGSI_PROPERTY_FS_DEPTH_LAYOUT
] = TGSI_FS_DEPTH_LAYOUT_GREATER
;
353 case FRAG_DEPTH_LAYOUT_LESS
:
354 info
->properties
[TGSI_PROPERTY_FS_DEPTH_LAYOUT
] = TGSI_FS_DEPTH_LAYOUT_LESS
;
356 case FRAG_DEPTH_LAYOUT_UNCHANGED
:
357 info
->properties
[TGSI_PROPERTY_FS_DEPTH_LAYOUT
] = TGSI_FS_DEPTH_LAYOUT_UNCHANGED
;
360 unreachable("Unknow depth layout");
365 if (gl_shader_stage_is_compute(nir
->info
.stage
)) {
366 info
->properties
[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH
] = nir
->info
.cs
.local_size
[0];
367 info
->properties
[TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT
] = nir
->info
.cs
.local_size
[1];
368 info
->properties
[TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH
] = nir
->info
.cs
.local_size
[2];
372 uint64_t processed_inputs
= 0;
373 unsigned num_inputs
= 0;
374 nir_foreach_variable(variable
, &nir
->inputs
) {
375 unsigned semantic_name
, semantic_index
;
377 const struct glsl_type
*type
= variable
->type
;
378 if (nir_is_per_vertex_io(variable
, nir
->info
.stage
)) {
379 assert(glsl_type_is_array(type
));
380 type
= glsl_get_array_element(type
);
383 unsigned attrib_count
= glsl_count_attribute_slots(type
,
384 nir
->info
.stage
== MESA_SHADER_VERTEX
);
386 i
= variable
->data
.driver_location
;
388 /* Vertex shader inputs don't have semantics. The state
389 * tracker has already mapped them to attributes via
390 * variable->data.driver_location.
392 if (nir
->info
.stage
== MESA_SHADER_VERTEX
) {
393 /* TODO: gather the actual input useage and remove this. */
394 info
->input_usage_mask
[i
] = TGSI_WRITEMASK_XYZW
;
396 if (glsl_type_is_dual_slot(variable
->type
)) {
399 /* TODO: gather the actual input useage and remove this. */
400 info
->input_usage_mask
[i
+1] = TGSI_WRITEMASK_XYZW
;
406 /* Fragment shader position is a system value. */
407 if (nir
->info
.stage
== MESA_SHADER_FRAGMENT
&&
408 variable
->data
.location
== VARYING_SLOT_POS
) {
409 if (variable
->data
.pixel_center_integer
)
410 info
->properties
[TGSI_PROPERTY_FS_COORD_PIXEL_CENTER
] =
411 TGSI_FS_COORD_PIXEL_CENTER_INTEGER
;
417 for (unsigned j
= 0; j
< attrib_count
; j
++, i
++) {
419 if (processed_inputs
& ((uint64_t)1 << i
))
422 processed_inputs
|= ((uint64_t)1 << i
);
425 tgsi_get_gl_varying_semantic(variable
->data
.location
+ j
, true,
426 &semantic_name
, &semantic_index
);
428 info
->input_semantic_name
[i
] = semantic_name
;
429 info
->input_semantic_index
[i
] = semantic_index
;
431 if (semantic_name
== TGSI_SEMANTIC_PRIMID
)
432 info
->uses_primid
= true;
434 if (variable
->data
.sample
)
435 info
->input_interpolate_loc
[i
] = TGSI_INTERPOLATE_LOC_SAMPLE
;
436 else if (variable
->data
.centroid
)
437 info
->input_interpolate_loc
[i
] = TGSI_INTERPOLATE_LOC_CENTROID
;
439 info
->input_interpolate_loc
[i
] = TGSI_INTERPOLATE_LOC_CENTER
;
441 enum glsl_base_type base_type
=
442 glsl_get_base_type(glsl_without_array(variable
->type
));
444 switch (variable
->data
.interpolation
) {
445 case INTERP_MODE_NONE
:
446 if (glsl_base_type_is_integer(base_type
)) {
447 info
->input_interpolate
[i
] = TGSI_INTERPOLATE_CONSTANT
;
451 if (semantic_name
== TGSI_SEMANTIC_COLOR
) {
452 info
->input_interpolate
[i
] = TGSI_INTERPOLATE_COLOR
;
457 case INTERP_MODE_SMOOTH
:
458 assert(!glsl_base_type_is_integer(base_type
));
460 info
->input_interpolate
[i
] = TGSI_INTERPOLATE_PERSPECTIVE
;
463 case INTERP_MODE_NOPERSPECTIVE
:
464 assert(!glsl_base_type_is_integer(base_type
));
466 info
->input_interpolate
[i
] = TGSI_INTERPOLATE_LINEAR
;
469 case INTERP_MODE_FLAT
:
470 info
->input_interpolate
[i
] = TGSI_INTERPOLATE_CONSTANT
;
474 /* TODO make this more precise */
475 if (variable
->data
.location
== VARYING_SLOT_COL0
)
476 info
->colors_read
|= 0x0f;
477 else if (variable
->data
.location
== VARYING_SLOT_COL1
)
478 info
->colors_read
|= 0xf0;
482 info
->num_inputs
= num_inputs
;
486 uint64_t processed_outputs
= 0;
487 unsigned num_outputs
= 0;
488 nir_foreach_variable(variable
, &nir
->outputs
) {
489 unsigned semantic_name
, semantic_index
;
491 i
= variable
->data
.driver_location
;
493 const struct glsl_type
*type
= variable
->type
;
494 if (nir_is_per_vertex_io(variable
, nir
->info
.stage
)) {
495 assert(glsl_type_is_array(type
));
496 type
= glsl_get_array_element(type
);
499 unsigned attrib_count
= glsl_count_attribute_slots(type
, false);
500 for (unsigned k
= 0; k
< attrib_count
; k
++, i
++) {
502 if (nir
->info
.stage
== MESA_SHADER_FRAGMENT
) {
503 tgsi_get_gl_frag_result_semantic(variable
->data
.location
+ k
,
504 &semantic_name
, &semantic_index
);
506 /* Adjust for dual source blending */
507 if (variable
->data
.index
> 0) {
511 tgsi_get_gl_varying_semantic(variable
->data
.location
+ k
, true,
512 &semantic_name
, &semantic_index
);
515 unsigned num_components
= 4;
516 unsigned vector_elements
= glsl_get_vector_elements(glsl_without_array(variable
->type
));
518 num_components
= vector_elements
;
520 unsigned component
= variable
->data
.location_frac
;
521 if (glsl_type_is_64bit(glsl_without_array(variable
->type
))) {
522 if (glsl_type_is_dual_slot(glsl_without_array(variable
->type
)) && k
% 2) {
523 num_components
= (num_components
* 2) - 4;
526 num_components
= MIN2(num_components
* 2, 4);
531 for (unsigned j
= component
; j
< num_components
+ component
; j
++) {
534 usagemask
|= TGSI_WRITEMASK_X
;
537 usagemask
|= TGSI_WRITEMASK_Y
;
540 usagemask
|= TGSI_WRITEMASK_Z
;
543 usagemask
|= TGSI_WRITEMASK_W
;
546 unreachable("error calculating component index");
550 unsigned gs_out_streams
;
551 if (variable
->data
.stream
& (1u << 31)) {
552 gs_out_streams
= variable
->data
.stream
& ~(1u << 31);
554 assert(variable
->data
.stream
< 4);
556 for (unsigned j
= 0; j
< num_components
; ++j
)
557 gs_out_streams
|= variable
->data
.stream
<< (2 * (component
+ j
));
560 unsigned streamx
= gs_out_streams
& 3;
561 unsigned streamy
= (gs_out_streams
>> 2) & 3;
562 unsigned streamz
= (gs_out_streams
>> 4) & 3;
563 unsigned streamw
= (gs_out_streams
>> 6) & 3;
565 if (usagemask
& TGSI_WRITEMASK_X
) {
566 info
->output_usagemask
[i
] |= TGSI_WRITEMASK_X
;
567 info
->output_streams
[i
] |= streamx
;
568 info
->num_stream_output_components
[streamx
]++;
570 if (usagemask
& TGSI_WRITEMASK_Y
) {
571 info
->output_usagemask
[i
] |= TGSI_WRITEMASK_Y
;
572 info
->output_streams
[i
] |= streamy
<< 2;
573 info
->num_stream_output_components
[streamy
]++;
575 if (usagemask
& TGSI_WRITEMASK_Z
) {
576 info
->output_usagemask
[i
] |= TGSI_WRITEMASK_Z
;
577 info
->output_streams
[i
] |= streamz
<< 4;
578 info
->num_stream_output_components
[streamz
]++;
580 if (usagemask
& TGSI_WRITEMASK_W
) {
581 info
->output_usagemask
[i
] |= TGSI_WRITEMASK_W
;
582 info
->output_streams
[i
] |= streamw
<< 6;
583 info
->num_stream_output_components
[streamw
]++;
586 /* make sure we only count this location once against
587 * the num_outputs counter.
589 if (processed_outputs
& ((uint64_t)1 << i
))
592 processed_outputs
|= ((uint64_t)1 << i
);
595 info
->output_semantic_name
[i
] = semantic_name
;
596 info
->output_semantic_index
[i
] = semantic_index
;
598 switch (semantic_name
) {
599 case TGSI_SEMANTIC_PRIMID
:
600 info
->writes_primid
= true;
602 case TGSI_SEMANTIC_VIEWPORT_INDEX
:
603 info
->writes_viewport_index
= true;
605 case TGSI_SEMANTIC_LAYER
:
606 info
->writes_layer
= true;
608 case TGSI_SEMANTIC_PSIZE
:
609 info
->writes_psize
= true;
611 case TGSI_SEMANTIC_CLIPVERTEX
:
612 info
->writes_clipvertex
= true;
614 case TGSI_SEMANTIC_COLOR
:
615 info
->colors_written
|= 1 << semantic_index
;
617 case TGSI_SEMANTIC_STENCIL
:
618 info
->writes_stencil
= true;
620 case TGSI_SEMANTIC_SAMPLEMASK
:
621 info
->writes_samplemask
= true;
623 case TGSI_SEMANTIC_EDGEFLAG
:
624 info
->writes_edgeflag
= true;
626 case TGSI_SEMANTIC_POSITION
:
627 if (info
->processor
== PIPE_SHADER_FRAGMENT
)
628 info
->writes_z
= true;
630 info
->writes_position
= true;
634 if (nir
->info
.stage
== MESA_SHADER_TESS_CTRL
) {
635 switch (semantic_name
) {
636 case TGSI_SEMANTIC_PATCH
:
637 info
->reads_perpatch_outputs
= true;
639 case TGSI_SEMANTIC_TESSINNER
:
640 case TGSI_SEMANTIC_TESSOUTER
:
641 info
->reads_tessfactor_outputs
= true;
644 info
->reads_pervertex_outputs
= true;
649 unsigned loc
= variable
->data
.location
;
650 if (nir
->info
.stage
== MESA_SHADER_FRAGMENT
&&
651 loc
== FRAG_RESULT_COLOR
&&
652 nir
->info
.outputs_written
& (1ull << loc
)) {
653 assert(attrib_count
== 1);
654 info
->properties
[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS
] = true;
658 info
->num_outputs
= num_outputs
;
660 struct set
*ubo_set
= _mesa_set_create(NULL
, _mesa_hash_pointer
,
661 _mesa_key_pointer_equal
);
663 /* Intialise const_file_max[0] */
664 info
->const_file_max
[0] = -1;
666 unsigned ubo_idx
= 1;
667 nir_foreach_variable(variable
, &nir
->uniforms
) {
668 const struct glsl_type
*type
= variable
->type
;
669 enum glsl_base_type base_type
=
670 glsl_get_base_type(glsl_without_array(type
));
671 unsigned aoa_size
= MAX2(1, glsl_get_aoa_size(type
));
673 /* Gather buffers declared bitmasks. Note: radeonsi doesn't
674 * really use the mask (other than ubo_idx == 1 for regular
675 * uniforms) its really only used for getting the buffer count
676 * so we don't need to worry about the ordering.
678 if (variable
->interface_type
!= NULL
) {
679 if (variable
->data
.mode
== nir_var_uniform
||
680 variable
->data
.mode
== nir_var_mem_ubo
) {
682 unsigned block_count
;
683 if (base_type
!= GLSL_TYPE_INTERFACE
) {
684 struct set_entry
*entry
=
685 _mesa_set_search(ubo_set
, variable
->interface_type
);
687 /* Check if we have already processed
688 * a member from this ubo.
695 block_count
= aoa_size
;
698 info
->const_buffers_declared
|= u_bit_consecutive(ubo_idx
, block_count
);
699 ubo_idx
+= block_count
;
701 _mesa_set_add(ubo_set
, variable
->interface_type
);
704 if (variable
->data
.mode
== nir_var_mem_ssbo
) {
705 /* TODO: make this more accurate */
706 info
->shader_buffers_declared
=
707 u_bit_consecutive(0, SI_NUM_SHADER_BUFFERS
);
713 /* We rely on the fact that nir_lower_samplers_as_deref has
714 * eliminated struct dereferences.
716 if (base_type
== GLSL_TYPE_SAMPLER
) {
717 if (variable
->data
.bindless
) {
718 info
->const_buffers_declared
|= 1;
719 info
->const_file_max
[0] +=
720 glsl_count_attribute_slots(type
, false);
722 info
->samplers_declared
|=
723 u_bit_consecutive(variable
->data
.binding
, aoa_size
);
725 } else if (base_type
== GLSL_TYPE_IMAGE
) {
726 if (variable
->data
.bindless
) {
727 info
->const_buffers_declared
|= 1;
728 info
->const_file_max
[0] +=
729 glsl_count_attribute_slots(type
, false);
731 info
->images_declared
|=
732 u_bit_consecutive(variable
->data
.binding
, aoa_size
);
734 } else if (base_type
!= GLSL_TYPE_ATOMIC_UINT
) {
735 if (strncmp(variable
->name
, "state.", 6) == 0 ||
736 strncmp(variable
->name
, "gl_", 3) == 0) {
737 /* FIXME: figure out why piglit tests with builtin
738 * uniforms are failing without this.
740 info
->const_buffers_declared
=
741 u_bit_consecutive(0, SI_NUM_CONST_BUFFERS
);
743 info
->const_buffers_declared
|= 1;
744 info
->const_file_max
[0] +=
745 glsl_count_attribute_slots(type
, false);
750 _mesa_set_destroy(ubo_set
, NULL
);
752 info
->num_written_clipdistance
= nir
->info
.clip_distance_array_size
;
753 info
->num_written_culldistance
= nir
->info
.cull_distance_array_size
;
754 info
->clipdist_writemask
= u_bit_consecutive(0, info
->num_written_clipdistance
);
755 info
->culldist_writemask
= u_bit_consecutive(0, info
->num_written_culldistance
);
757 if (info
->processor
== PIPE_SHADER_FRAGMENT
)
758 info
->uses_kill
= nir
->info
.fs
.uses_discard
;
760 func
= (struct nir_function
*)exec_list_get_head_const(&nir
->functions
);
761 nir_foreach_block(block
, func
->impl
) {
762 nir_foreach_instr(instr
, block
)
763 scan_instruction(info
, instr
);
768 * Perform "lowering" operations on the NIR that are run once when the shader
769 * selector is created.
772 si_lower_nir(struct si_shader_selector
* sel
)
774 /* Adjust the driver location of inputs and outputs. The state tracker
775 * interprets them as slots, while the ac/nir backend interprets them
776 * as individual components.
778 nir_foreach_variable(variable
, &sel
->nir
->inputs
)
779 variable
->data
.driver_location
*= 4;
781 nir_foreach_variable(variable
, &sel
->nir
->outputs
) {
782 variable
->data
.driver_location
*= 4;
784 if (sel
->nir
->info
.stage
== MESA_SHADER_FRAGMENT
) {
785 if (variable
->data
.location
== FRAG_RESULT_DEPTH
)
786 variable
->data
.driver_location
+= 2;
787 else if (variable
->data
.location
== FRAG_RESULT_STENCIL
)
788 variable
->data
.driver_location
+= 1;
792 /* Perform lowerings (and optimizations) of code.
794 * Performance considerations aside, we must:
795 * - lower certain ALU operations
796 * - ensure constant offsets for texture instructions are folded
797 * and copy-propagated
799 NIR_PASS_V(sel
->nir
, nir_lower_returns
);
800 NIR_PASS_V(sel
->nir
, nir_lower_vars_to_ssa
);
801 NIR_PASS_V(sel
->nir
, nir_lower_alu_to_scalar
);
802 NIR_PASS_V(sel
->nir
, nir_lower_phis_to_scalar
);
804 static const struct nir_lower_tex_options lower_tex_options
= {
807 NIR_PASS_V(sel
->nir
, nir_lower_tex
, &lower_tex_options
);
809 const nir_lower_subgroups_options subgroups_options
= {
811 .ballot_bit_size
= 64,
812 .lower_to_scalar
= true,
813 .lower_subgroup_masks
= true,
814 .lower_vote_trivial
= false,
815 .lower_vote_eq_to_ballot
= true,
817 NIR_PASS_V(sel
->nir
, nir_lower_subgroups
, &subgroups_options
);
819 ac_lower_indirect_derefs(sel
->nir
, sel
->screen
->info
.chip_class
);
825 /* (Constant) copy propagation is needed for txf with offsets. */
826 NIR_PASS(progress
, sel
->nir
, nir_copy_prop
);
827 NIR_PASS(progress
, sel
->nir
, nir_opt_remove_phis
);
828 NIR_PASS(progress
, sel
->nir
, nir_opt_dce
);
829 if (nir_opt_trivial_continues(sel
->nir
)) {
831 NIR_PASS(progress
, sel
->nir
, nir_copy_prop
);
832 NIR_PASS(progress
, sel
->nir
, nir_opt_dce
);
834 NIR_PASS(progress
, sel
->nir
, nir_opt_if
);
835 NIR_PASS(progress
, sel
->nir
, nir_opt_dead_cf
);
836 NIR_PASS(progress
, sel
->nir
, nir_opt_cse
);
837 NIR_PASS(progress
, sel
->nir
, nir_opt_peephole_select
, 8, true, true);
839 /* Needed for algebraic lowering */
840 NIR_PASS(progress
, sel
->nir
, nir_opt_algebraic
);
841 NIR_PASS(progress
, sel
->nir
, nir_opt_constant_folding
);
843 NIR_PASS(progress
, sel
->nir
, nir_opt_undef
);
844 NIR_PASS(progress
, sel
->nir
, nir_opt_conditional_discard
);
845 if (sel
->nir
->options
->max_unroll_iterations
) {
846 NIR_PASS(progress
, sel
->nir
, nir_opt_loop_unroll
, 0);
850 NIR_PASS_V(sel
->nir
, nir_lower_bool_to_int32
);
853 static void declare_nir_input_vs(struct si_shader_context
*ctx
,
854 struct nir_variable
*variable
,
855 unsigned input_index
,
858 si_llvm_load_input_vs(ctx
, input_index
, out
);
861 static void declare_nir_input_fs(struct si_shader_context
*ctx
,
862 struct nir_variable
*variable
,
863 unsigned input_index
,
866 unsigned slot
= variable
->data
.location
;
867 if (slot
== VARYING_SLOT_POS
) {
868 out
[0] = LLVMGetParam(ctx
->main_fn
, SI_PARAM_POS_X_FLOAT
);
869 out
[1] = LLVMGetParam(ctx
->main_fn
, SI_PARAM_POS_Y_FLOAT
);
870 out
[2] = LLVMGetParam(ctx
->main_fn
, SI_PARAM_POS_Z_FLOAT
);
871 out
[3] = ac_build_fdiv(&ctx
->ac
, ctx
->ac
.f32_1
,
872 LLVMGetParam(ctx
->main_fn
, SI_PARAM_POS_W_FLOAT
));
876 si_llvm_load_input_fs(ctx
, input_index
, out
);
880 si_nir_lookup_interp_param(struct ac_shader_abi
*abi
,
881 enum glsl_interp_mode interp
, unsigned location
)
883 struct si_shader_context
*ctx
= si_shader_context_from_abi(abi
);
884 int interp_param_idx
= -1;
887 case INTERP_MODE_FLAT
:
889 case INTERP_MODE_SMOOTH
:
890 case INTERP_MODE_NONE
:
891 if (location
== INTERP_CENTER
)
892 interp_param_idx
= SI_PARAM_PERSP_CENTER
;
893 else if (location
== INTERP_CENTROID
)
894 interp_param_idx
= SI_PARAM_PERSP_CENTROID
;
895 else if (location
== INTERP_SAMPLE
)
896 interp_param_idx
= SI_PARAM_PERSP_SAMPLE
;
898 case INTERP_MODE_NOPERSPECTIVE
:
899 if (location
== INTERP_CENTER
)
900 interp_param_idx
= SI_PARAM_LINEAR_CENTER
;
901 else if (location
== INTERP_CENTROID
)
902 interp_param_idx
= SI_PARAM_LINEAR_CENTROID
;
903 else if (location
== INTERP_SAMPLE
)
904 interp_param_idx
= SI_PARAM_LINEAR_SAMPLE
;
907 assert(!"Unhandled interpolation mode.");
911 return interp_param_idx
!= -1 ?
912 LLVMGetParam(ctx
->main_fn
, interp_param_idx
) : NULL
;
916 si_nir_load_sampler_desc(struct ac_shader_abi
*abi
,
917 unsigned descriptor_set
, unsigned base_index
,
918 unsigned constant_index
, LLVMValueRef dynamic_index
,
919 enum ac_descriptor_type desc_type
, bool image
,
920 bool write
, bool bindless
)
922 struct si_shader_context
*ctx
= si_shader_context_from_abi(abi
);
923 const struct tgsi_shader_info
*info
= &ctx
->shader
->selector
->info
;
924 LLVMBuilderRef builder
= ctx
->ac
.builder
;
925 unsigned const_index
= base_index
+ constant_index
;
926 bool dcc_off
= write
;
928 /* TODO: images_store and images_atomic are not set */
929 if (!dynamic_index
&& image
&&
930 (info
->images_store
| info
->images_atomic
) & (1 << const_index
))
933 assert(!descriptor_set
);
934 assert(!image
|| desc_type
== AC_DESC_IMAGE
|| desc_type
== AC_DESC_BUFFER
);
938 LLVMGetParam(ctx
->main_fn
, ctx
->param_bindless_samplers_and_images
);
940 /* dynamic_index is the bindless handle */
942 return si_load_image_desc(ctx
, list
, dynamic_index
, desc_type
,
946 /* Since bindless handle arithmetic can contain an unsigned integer
947 * wraparound and si_load_sampler_desc assumes there isn't any,
948 * use GEP without "inbounds" (inside ac_build_pointer_add)
949 * to prevent incorrect code generation and hangs.
951 dynamic_index
= LLVMBuildMul(ctx
->ac
.builder
, dynamic_index
,
952 LLVMConstInt(ctx
->i32
, 2, 0), "");
953 list
= ac_build_pointer_add(&ctx
->ac
, list
, dynamic_index
);
954 return si_load_sampler_desc(ctx
, list
, ctx
->i32_0
, desc_type
);
957 unsigned num_slots
= image
? ctx
->num_images
: ctx
->num_samplers
;
958 assert(const_index
< num_slots
);
960 LLVMValueRef list
= LLVMGetParam(ctx
->main_fn
, ctx
->param_samplers_and_images
);
961 LLVMValueRef index
= LLVMConstInt(ctx
->ac
.i32
, const_index
, false);
964 index
= LLVMBuildAdd(builder
, index
, dynamic_index
, "");
966 /* From the GL_ARB_shader_image_load_store extension spec:
968 * If a shader performs an image load, store, or atomic
969 * operation using an image variable declared as an array,
970 * and if the index used to select an individual element is
971 * negative or greater than or equal to the size of the
972 * array, the results of the operation are undefined but may
973 * not lead to termination.
975 index
= si_llvm_bound_index(ctx
, index
, num_slots
);
979 index
= LLVMBuildSub(ctx
->ac
.builder
,
980 LLVMConstInt(ctx
->i32
, SI_NUM_IMAGES
- 1, 0),
982 return si_load_image_desc(ctx
, list
, index
, desc_type
, dcc_off
, false);
985 index
= LLVMBuildAdd(ctx
->ac
.builder
, index
,
986 LLVMConstInt(ctx
->i32
, SI_NUM_IMAGES
/ 2, 0), "");
987 return si_load_sampler_desc(ctx
, list
, index
, desc_type
);
990 static void bitcast_inputs(struct si_shader_context
*ctx
,
991 LLVMValueRef data
[4],
994 for (unsigned chan
= 0; chan
< 4; chan
++) {
995 ctx
->inputs
[input_idx
+ chan
] =
996 LLVMBuildBitCast(ctx
->ac
.builder
, data
[chan
], ctx
->ac
.i32
, "");
1000 bool si_nir_build_llvm(struct si_shader_context
*ctx
, struct nir_shader
*nir
)
1002 struct tgsi_shader_info
*info
= &ctx
->shader
->selector
->info
;
1004 if (nir
->info
.stage
== MESA_SHADER_VERTEX
||
1005 nir
->info
.stage
== MESA_SHADER_FRAGMENT
) {
1006 uint64_t processed_inputs
= 0;
1007 nir_foreach_variable(variable
, &nir
->inputs
) {
1008 unsigned attrib_count
= glsl_count_attribute_slots(variable
->type
,
1009 nir
->info
.stage
== MESA_SHADER_VERTEX
);
1010 unsigned input_idx
= variable
->data
.driver_location
;
1012 LLVMValueRef data
[4];
1013 unsigned loc
= variable
->data
.location
;
1015 if (loc
>= VARYING_SLOT_VAR0
&& nir
->info
.stage
== MESA_SHADER_FRAGMENT
)
1016 ctx
->abi
.fs_input_attr_indices
[loc
- VARYING_SLOT_VAR0
] = input_idx
/ 4;
1018 for (unsigned i
= 0; i
< attrib_count
; i
++) {
1019 /* Packed components share the same location so skip
1020 * them if we have already processed the location.
1022 if (processed_inputs
& ((uint64_t)1 << (loc
+ i
))) {
1027 if (nir
->info
.stage
== MESA_SHADER_VERTEX
) {
1028 declare_nir_input_vs(ctx
, variable
, input_idx
/ 4, data
);
1029 bitcast_inputs(ctx
, data
, input_idx
);
1030 if (glsl_type_is_dual_slot(variable
->type
)) {
1032 declare_nir_input_vs(ctx
, variable
, input_idx
/ 4, data
);
1033 bitcast_inputs(ctx
, data
, input_idx
);
1035 } else if (nir
->info
.stage
== MESA_SHADER_FRAGMENT
) {
1036 declare_nir_input_fs(ctx
, variable
, input_idx
/ 4, data
);
1037 bitcast_inputs(ctx
, data
, input_idx
);
1040 processed_inputs
|= ((uint64_t)1 << (loc
+ i
));
1046 ctx
->abi
.inputs
= &ctx
->inputs
[0];
1047 ctx
->abi
.load_sampler_desc
= si_nir_load_sampler_desc
;
1048 ctx
->abi
.clamp_shadow_reference
= true;
1050 ctx
->num_samplers
= util_last_bit(info
->samplers_declared
);
1051 ctx
->num_images
= util_last_bit(info
->images_declared
);
1053 if (ctx
->shader
->selector
->info
.properties
[TGSI_PROPERTY_CS_LOCAL_SIZE
]) {
1054 assert(gl_shader_stage_is_compute(nir
->info
.stage
));
1055 si_declare_compute_memory(ctx
);
1057 ac_nir_translate(&ctx
->ac
, &ctx
->abi
, nir
);