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radeonsi/nir: set colors_read properly
[mesa.git] / src / gallium / drivers / radeonsi / si_shader_nir.c
1 /*
2 * Copyright 2017 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 #include "si_shader_internal.h"
26 #include "si_pipe.h"
27
28 #include "ac_nir_to_llvm.h"
29
30 #include "tgsi/tgsi_from_mesa.h"
31
32 #include "compiler/nir/nir.h"
33 #include "compiler/nir_types.h"
34
35 static nir_variable* tex_get_texture_var(nir_tex_instr *instr)
36 {
37 for (unsigned i = 0; i < instr->num_srcs; i++) {
38 switch (instr->src[i].src_type) {
39 case nir_tex_src_texture_deref:
40 return nir_deref_instr_get_variable(nir_src_as_deref(instr->src[i].src));
41 default:
42 break;
43 }
44 }
45
46 return NULL;
47 }
48
49 static nir_variable* intrinsic_get_var(nir_intrinsic_instr *instr)
50 {
51 return nir_deref_instr_get_variable(nir_src_as_deref(instr->src[0]));
52 }
53
54 static void gather_intrinsic_load_deref_info(const nir_shader *nir,
55 const nir_intrinsic_instr *instr,
56 nir_variable *var,
57 struct tgsi_shader_info *info)
58 {
59 assert(var && var->data.mode == nir_var_shader_in);
60
61 switch (nir->info.stage) {
62 case MESA_SHADER_VERTEX: {
63 unsigned i = var->data.driver_location;
64 unsigned attrib_count = glsl_count_attribute_slots(var->type, false);
65
66 for (unsigned j = 0; j < attrib_count; j++, i++) {
67 if (glsl_type_is_64bit(glsl_without_array(var->type))) {
68 /* TODO: set usage mask more accurately for doubles */
69 info->input_usage_mask[i] = TGSI_WRITEMASK_XYZW;
70 } else {
71 uint8_t mask = nir_ssa_def_components_read(&instr->dest.ssa);
72 info->input_usage_mask[i] |= mask << var->data.location_frac;
73 }
74 }
75 break;
76 }
77 default: {
78 unsigned semantic_name, semantic_index;
79 tgsi_get_gl_varying_semantic(var->data.location, true,
80 &semantic_name, &semantic_index);
81
82 if (semantic_name == TGSI_SEMANTIC_COLOR) {
83 uint8_t mask = nir_ssa_def_components_read(&instr->dest.ssa);
84 info->colors_read |= mask << (semantic_index * 4);
85 }
86 break;
87 }
88 }
89 }
90
91 static void scan_instruction(const struct nir_shader *nir,
92 struct tgsi_shader_info *info,
93 nir_instr *instr)
94 {
95 if (instr->type == nir_instr_type_alu) {
96 nir_alu_instr *alu = nir_instr_as_alu(instr);
97
98 switch (alu->op) {
99 case nir_op_fddx:
100 case nir_op_fddy:
101 case nir_op_fddx_fine:
102 case nir_op_fddy_fine:
103 case nir_op_fddx_coarse:
104 case nir_op_fddy_coarse:
105 info->uses_derivatives = true;
106 break;
107 default:
108 break;
109 }
110 } else if (instr->type == nir_instr_type_tex) {
111 nir_tex_instr *tex = nir_instr_as_tex(instr);
112 nir_variable *texture = tex_get_texture_var(tex);
113
114 if (!texture) {
115 info->samplers_declared |=
116 u_bit_consecutive(tex->sampler_index, 1);
117 } else {
118 if (texture->data.bindless)
119 info->uses_bindless_samplers = true;
120 }
121
122 switch (tex->op) {
123 case nir_texop_tex:
124 case nir_texop_txb:
125 case nir_texop_lod:
126 info->uses_derivatives = true;
127 break;
128 default:
129 break;
130 }
131 } else if (instr->type == nir_instr_type_intrinsic) {
132 nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);
133
134 switch (intr->intrinsic) {
135 case nir_intrinsic_load_front_face:
136 info->uses_frontface = 1;
137 break;
138 case nir_intrinsic_load_instance_id:
139 info->uses_instanceid = 1;
140 break;
141 case nir_intrinsic_load_invocation_id:
142 info->uses_invocationid = true;
143 break;
144 case nir_intrinsic_load_num_work_groups:
145 info->uses_grid_size = true;
146 break;
147 case nir_intrinsic_load_local_group_size:
148 /* The block size is translated to IMM with a fixed block size. */
149 if (info->properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] == 0)
150 info->uses_block_size = true;
151 break;
152 case nir_intrinsic_load_local_invocation_id:
153 case nir_intrinsic_load_work_group_id: {
154 unsigned mask = nir_ssa_def_components_read(&intr->dest.ssa);
155 while (mask) {
156 unsigned i = u_bit_scan(&mask);
157
158 if (intr->intrinsic == nir_intrinsic_load_work_group_id)
159 info->uses_block_id[i] = true;
160 else
161 info->uses_thread_id[i] = true;
162 }
163 break;
164 }
165 case nir_intrinsic_load_vertex_id:
166 info->uses_vertexid = 1;
167 break;
168 case nir_intrinsic_load_vertex_id_zero_base:
169 info->uses_vertexid_nobase = 1;
170 break;
171 case nir_intrinsic_load_base_vertex:
172 info->uses_basevertex = 1;
173 break;
174 case nir_intrinsic_load_primitive_id:
175 info->uses_primid = 1;
176 break;
177 case nir_intrinsic_load_sample_mask_in:
178 info->reads_samplemask = true;
179 break;
180 case nir_intrinsic_load_tess_level_inner:
181 case nir_intrinsic_load_tess_level_outer:
182 info->reads_tess_factors = true;
183 break;
184 case nir_intrinsic_image_deref_load: {
185 nir_variable *var = intrinsic_get_var(intr);
186 if (var->data.bindless) {
187 info->uses_bindless_images = true;
188
189 if (glsl_get_sampler_dim(var->type) == GLSL_SAMPLER_DIM_BUF)
190 info->uses_bindless_buffer_load = true;
191 else
192 info->uses_bindless_image_load = true;
193 }
194 break;
195 }
196 case nir_intrinsic_image_deref_size:
197 case nir_intrinsic_image_deref_samples: {
198 nir_variable *var = intrinsic_get_var(intr);
199 if (var->data.bindless)
200 info->uses_bindless_images = true;
201 break;
202 }
203 case nir_intrinsic_image_deref_store: {
204 const nir_deref_instr *image_deref = nir_instr_as_deref(intr->src[0].ssa->parent_instr);
205 nir_variable *var = intrinsic_get_var(intr);
206 if (var->data.bindless) {
207 info->uses_bindless_images = true;
208
209 if (glsl_get_sampler_dim(image_deref->type) == GLSL_SAMPLER_DIM_BUF)
210 info->uses_bindless_buffer_store = true;
211 else
212 info->uses_bindless_image_store = true;
213 }
214 info->writes_memory = true;
215 break;
216 }
217 case nir_intrinsic_image_deref_atomic_add:
218 case nir_intrinsic_image_deref_atomic_min:
219 case nir_intrinsic_image_deref_atomic_max:
220 case nir_intrinsic_image_deref_atomic_and:
221 case nir_intrinsic_image_deref_atomic_or:
222 case nir_intrinsic_image_deref_atomic_xor:
223 case nir_intrinsic_image_deref_atomic_exchange:
224 case nir_intrinsic_image_deref_atomic_comp_swap: {
225 nir_variable *var = intrinsic_get_var(intr);
226 if (var->data.bindless) {
227 info->uses_bindless_images = true;
228
229 if (glsl_get_sampler_dim(var->type) == GLSL_SAMPLER_DIM_BUF)
230 info->uses_bindless_buffer_atomic = true;
231 else
232 info->uses_bindless_image_atomic = true;
233 }
234 info->writes_memory = true;
235 break;
236 }
237 case nir_intrinsic_store_ssbo:
238 case nir_intrinsic_ssbo_atomic_add:
239 case nir_intrinsic_ssbo_atomic_imin:
240 case nir_intrinsic_ssbo_atomic_umin:
241 case nir_intrinsic_ssbo_atomic_imax:
242 case nir_intrinsic_ssbo_atomic_umax:
243 case nir_intrinsic_ssbo_atomic_and:
244 case nir_intrinsic_ssbo_atomic_or:
245 case nir_intrinsic_ssbo_atomic_xor:
246 case nir_intrinsic_ssbo_atomic_exchange:
247 case nir_intrinsic_ssbo_atomic_comp_swap:
248 info->writes_memory = true;
249 break;
250 case nir_intrinsic_load_deref: {
251 nir_variable *var = intrinsic_get_var(intr);
252 nir_variable_mode mode = var->data.mode;
253 enum glsl_base_type base_type =
254 glsl_get_base_type(glsl_without_array(var->type));
255
256 if (mode == nir_var_shader_in) {
257 gather_intrinsic_load_deref_info(nir, intr, var, info);
258
259 switch (var->data.interpolation) {
260 case INTERP_MODE_NONE:
261 if (glsl_base_type_is_integer(base_type))
262 break;
263
264 /* fall-through */
265 case INTERP_MODE_SMOOTH:
266 if (var->data.sample)
267 info->uses_persp_sample = true;
268 else if (var->data.centroid)
269 info->uses_persp_centroid = true;
270 else
271 info->uses_persp_center = true;
272 break;
273
274 case INTERP_MODE_NOPERSPECTIVE:
275 if (var->data.sample)
276 info->uses_linear_sample = true;
277 else if (var->data.centroid)
278 info->uses_linear_centroid = true;
279 else
280 info->uses_linear_center = true;
281 break;
282 }
283 }
284 break;
285 }
286 case nir_intrinsic_interp_deref_at_centroid:
287 case nir_intrinsic_interp_deref_at_sample:
288 case nir_intrinsic_interp_deref_at_offset: {
289 enum glsl_interp_mode interp = intrinsic_get_var(intr)->data.interpolation;
290 switch (interp) {
291 case INTERP_MODE_SMOOTH:
292 case INTERP_MODE_NONE:
293 if (intr->intrinsic == nir_intrinsic_interp_deref_at_centroid)
294 info->uses_persp_opcode_interp_centroid = true;
295 else if (intr->intrinsic == nir_intrinsic_interp_deref_at_sample)
296 info->uses_persp_opcode_interp_sample = true;
297 else
298 info->uses_persp_opcode_interp_offset = true;
299 break;
300 case INTERP_MODE_NOPERSPECTIVE:
301 if (intr->intrinsic == nir_intrinsic_interp_deref_at_centroid)
302 info->uses_linear_opcode_interp_centroid = true;
303 else if (intr->intrinsic == nir_intrinsic_interp_deref_at_sample)
304 info->uses_linear_opcode_interp_sample = true;
305 else
306 info->uses_linear_opcode_interp_offset = true;
307 break;
308 case INTERP_MODE_FLAT:
309 break;
310 default:
311 unreachable("Unsupported interpoation type");
312 }
313 break;
314 }
315 default:
316 break;
317 }
318 }
319 }
320
321 void si_nir_scan_tess_ctrl(const struct nir_shader *nir,
322 struct tgsi_tessctrl_info *out)
323 {
324 memset(out, 0, sizeof(*out));
325
326 if (nir->info.stage != MESA_SHADER_TESS_CTRL)
327 return;
328
329 out->tessfactors_are_def_in_all_invocs =
330 ac_are_tessfactors_def_in_all_invocs(nir);
331 }
332
333 void si_nir_scan_shader(const struct nir_shader *nir,
334 struct tgsi_shader_info *info)
335 {
336 nir_function *func;
337 unsigned i;
338
339 info->processor = pipe_shader_type_from_mesa(nir->info.stage);
340 info->num_tokens = 2; /* indicate that the shader is non-empty */
341 info->num_instructions = 2;
342
343 info->properties[TGSI_PROPERTY_NEXT_SHADER] =
344 pipe_shader_type_from_mesa(nir->info.next_stage);
345
346 if (nir->info.stage == MESA_SHADER_TESS_CTRL) {
347 info->properties[TGSI_PROPERTY_TCS_VERTICES_OUT] =
348 nir->info.tess.tcs_vertices_out;
349 }
350
351 if (nir->info.stage == MESA_SHADER_TESS_EVAL) {
352 if (nir->info.tess.primitive_mode == GL_ISOLINES)
353 info->properties[TGSI_PROPERTY_TES_PRIM_MODE] = PIPE_PRIM_LINES;
354 else
355 info->properties[TGSI_PROPERTY_TES_PRIM_MODE] = nir->info.tess.primitive_mode;
356
357 STATIC_ASSERT((TESS_SPACING_EQUAL + 1) % 3 == PIPE_TESS_SPACING_EQUAL);
358 STATIC_ASSERT((TESS_SPACING_FRACTIONAL_ODD + 1) % 3 ==
359 PIPE_TESS_SPACING_FRACTIONAL_ODD);
360 STATIC_ASSERT((TESS_SPACING_FRACTIONAL_EVEN + 1) % 3 ==
361 PIPE_TESS_SPACING_FRACTIONAL_EVEN);
362
363 info->properties[TGSI_PROPERTY_TES_SPACING] = (nir->info.tess.spacing + 1) % 3;
364 info->properties[TGSI_PROPERTY_TES_VERTEX_ORDER_CW] = !nir->info.tess.ccw;
365 info->properties[TGSI_PROPERTY_TES_POINT_MODE] = nir->info.tess.point_mode;
366 }
367
368 if (nir->info.stage == MESA_SHADER_GEOMETRY) {
369 info->properties[TGSI_PROPERTY_GS_INPUT_PRIM] = nir->info.gs.input_primitive;
370 info->properties[TGSI_PROPERTY_GS_OUTPUT_PRIM] = nir->info.gs.output_primitive;
371 info->properties[TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES] = nir->info.gs.vertices_out;
372 info->properties[TGSI_PROPERTY_GS_INVOCATIONS] = nir->info.gs.invocations;
373 }
374
375 if (nir->info.stage == MESA_SHADER_FRAGMENT) {
376 info->properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL] =
377 nir->info.fs.early_fragment_tests | nir->info.fs.post_depth_coverage;
378 info->properties[TGSI_PROPERTY_FS_POST_DEPTH_COVERAGE] = nir->info.fs.post_depth_coverage;
379
380 if (nir->info.fs.pixel_center_integer) {
381 info->properties[TGSI_PROPERTY_FS_COORD_PIXEL_CENTER] =
382 TGSI_FS_COORD_PIXEL_CENTER_INTEGER;
383 }
384
385 if (nir->info.fs.depth_layout != FRAG_DEPTH_LAYOUT_NONE) {
386 switch (nir->info.fs.depth_layout) {
387 case FRAG_DEPTH_LAYOUT_ANY:
388 info->properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT] = TGSI_FS_DEPTH_LAYOUT_ANY;
389 break;
390 case FRAG_DEPTH_LAYOUT_GREATER:
391 info->properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT] = TGSI_FS_DEPTH_LAYOUT_GREATER;
392 break;
393 case FRAG_DEPTH_LAYOUT_LESS:
394 info->properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT] = TGSI_FS_DEPTH_LAYOUT_LESS;
395 break;
396 case FRAG_DEPTH_LAYOUT_UNCHANGED:
397 info->properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT] = TGSI_FS_DEPTH_LAYOUT_UNCHANGED;
398 break;
399 default:
400 unreachable("Unknow depth layout");
401 }
402 }
403 }
404
405 if (gl_shader_stage_is_compute(nir->info.stage)) {
406 info->properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] = nir->info.cs.local_size[0];
407 info->properties[TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT] = nir->info.cs.local_size[1];
408 info->properties[TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH] = nir->info.cs.local_size[2];
409 }
410
411 i = 0;
412 uint64_t processed_inputs = 0;
413 unsigned num_inputs = 0;
414 nir_foreach_variable(variable, &nir->inputs) {
415 unsigned semantic_name, semantic_index;
416
417 const struct glsl_type *type = variable->type;
418 if (nir_is_per_vertex_io(variable, nir->info.stage)) {
419 assert(glsl_type_is_array(type));
420 type = glsl_get_array_element(type);
421 }
422
423 unsigned attrib_count = glsl_count_attribute_slots(type,
424 nir->info.stage == MESA_SHADER_VERTEX);
425
426 i = variable->data.driver_location;
427
428 /* Vertex shader inputs don't have semantics. The state
429 * tracker has already mapped them to attributes via
430 * variable->data.driver_location.
431 */
432 if (nir->info.stage == MESA_SHADER_VERTEX) {
433 if (glsl_type_is_dual_slot(glsl_without_array(variable->type)))
434 num_inputs++;
435
436 num_inputs++;
437 continue;
438 }
439
440 /* Fragment shader position is a system value. */
441 if (nir->info.stage == MESA_SHADER_FRAGMENT &&
442 variable->data.location == VARYING_SLOT_POS) {
443 if (variable->data.pixel_center_integer)
444 info->properties[TGSI_PROPERTY_FS_COORD_PIXEL_CENTER] =
445 TGSI_FS_COORD_PIXEL_CENTER_INTEGER;
446
447 num_inputs++;
448 continue;
449 }
450
451 for (unsigned j = 0; j < attrib_count; j++, i++) {
452
453 if (processed_inputs & ((uint64_t)1 << i))
454 continue;
455
456 processed_inputs |= ((uint64_t)1 << i);
457 num_inputs++;
458
459 tgsi_get_gl_varying_semantic(variable->data.location + j, true,
460 &semantic_name, &semantic_index);
461
462 info->input_semantic_name[i] = semantic_name;
463 info->input_semantic_index[i] = semantic_index;
464
465 if (semantic_name == TGSI_SEMANTIC_PRIMID)
466 info->uses_primid = true;
467
468 if (variable->data.sample)
469 info->input_interpolate_loc[i] = TGSI_INTERPOLATE_LOC_SAMPLE;
470 else if (variable->data.centroid)
471 info->input_interpolate_loc[i] = TGSI_INTERPOLATE_LOC_CENTROID;
472 else
473 info->input_interpolate_loc[i] = TGSI_INTERPOLATE_LOC_CENTER;
474
475 enum glsl_base_type base_type =
476 glsl_get_base_type(glsl_without_array(variable->type));
477
478 switch (variable->data.interpolation) {
479 case INTERP_MODE_NONE:
480 if (glsl_base_type_is_integer(base_type)) {
481 info->input_interpolate[i] = TGSI_INTERPOLATE_CONSTANT;
482 break;
483 }
484
485 if (semantic_name == TGSI_SEMANTIC_COLOR) {
486 info->input_interpolate[i] = TGSI_INTERPOLATE_COLOR;
487 break;
488 }
489 /* fall-through */
490
491 case INTERP_MODE_SMOOTH:
492 assert(!glsl_base_type_is_integer(base_type));
493
494 info->input_interpolate[i] = TGSI_INTERPOLATE_PERSPECTIVE;
495 break;
496
497 case INTERP_MODE_NOPERSPECTIVE:
498 assert(!glsl_base_type_is_integer(base_type));
499
500 info->input_interpolate[i] = TGSI_INTERPOLATE_LINEAR;
501 break;
502
503 case INTERP_MODE_FLAT:
504 info->input_interpolate[i] = TGSI_INTERPOLATE_CONSTANT;
505 break;
506 }
507 }
508 }
509
510 info->num_inputs = num_inputs;
511
512
513 i = 0;
514 uint64_t processed_outputs = 0;
515 unsigned num_outputs = 0;
516 nir_foreach_variable(variable, &nir->outputs) {
517 unsigned semantic_name, semantic_index;
518
519 i = variable->data.driver_location;
520
521 const struct glsl_type *type = variable->type;
522 if (nir_is_per_vertex_io(variable, nir->info.stage)) {
523 assert(glsl_type_is_array(type));
524 type = glsl_get_array_element(type);
525 }
526
527 unsigned attrib_count = glsl_count_attribute_slots(type, false);
528 for (unsigned k = 0; k < attrib_count; k++, i++) {
529
530 if (nir->info.stage == MESA_SHADER_FRAGMENT) {
531 tgsi_get_gl_frag_result_semantic(variable->data.location + k,
532 &semantic_name, &semantic_index);
533
534 /* Adjust for dual source blending */
535 if (variable->data.index > 0) {
536 semantic_index++;
537 }
538 } else {
539 tgsi_get_gl_varying_semantic(variable->data.location + k, true,
540 &semantic_name, &semantic_index);
541 }
542
543 unsigned num_components = 4;
544 unsigned vector_elements = glsl_get_vector_elements(glsl_without_array(variable->type));
545 if (vector_elements)
546 num_components = vector_elements;
547
548 unsigned component = variable->data.location_frac;
549 if (glsl_type_is_64bit(glsl_without_array(variable->type))) {
550 if (glsl_type_is_dual_slot(glsl_without_array(variable->type)) && k % 2) {
551 num_components = (num_components * 2) - 4;
552 component = 0;
553 } else {
554 num_components = MIN2(num_components * 2, 4);
555 }
556 }
557
558 ubyte usagemask = 0;
559 for (unsigned j = component; j < num_components + component; j++) {
560 switch (j) {
561 case 0:
562 usagemask |= TGSI_WRITEMASK_X;
563 break;
564 case 1:
565 usagemask |= TGSI_WRITEMASK_Y;
566 break;
567 case 2:
568 usagemask |= TGSI_WRITEMASK_Z;
569 break;
570 case 3:
571 usagemask |= TGSI_WRITEMASK_W;
572 break;
573 default:
574 unreachable("error calculating component index");
575 }
576 }
577
578 unsigned gs_out_streams;
579 if (variable->data.stream & (1u << 31)) {
580 gs_out_streams = variable->data.stream & ~(1u << 31);
581 } else {
582 assert(variable->data.stream < 4);
583 gs_out_streams = 0;
584 for (unsigned j = 0; j < num_components; ++j)
585 gs_out_streams |= variable->data.stream << (2 * (component + j));
586 }
587
588 unsigned streamx = gs_out_streams & 3;
589 unsigned streamy = (gs_out_streams >> 2) & 3;
590 unsigned streamz = (gs_out_streams >> 4) & 3;
591 unsigned streamw = (gs_out_streams >> 6) & 3;
592
593 if (usagemask & TGSI_WRITEMASK_X) {
594 info->output_usagemask[i] |= TGSI_WRITEMASK_X;
595 info->output_streams[i] |= streamx;
596 info->num_stream_output_components[streamx]++;
597 }
598 if (usagemask & TGSI_WRITEMASK_Y) {
599 info->output_usagemask[i] |= TGSI_WRITEMASK_Y;
600 info->output_streams[i] |= streamy << 2;
601 info->num_stream_output_components[streamy]++;
602 }
603 if (usagemask & TGSI_WRITEMASK_Z) {
604 info->output_usagemask[i] |= TGSI_WRITEMASK_Z;
605 info->output_streams[i] |= streamz << 4;
606 info->num_stream_output_components[streamz]++;
607 }
608 if (usagemask & TGSI_WRITEMASK_W) {
609 info->output_usagemask[i] |= TGSI_WRITEMASK_W;
610 info->output_streams[i] |= streamw << 6;
611 info->num_stream_output_components[streamw]++;
612 }
613
614 /* make sure we only count this location once against
615 * the num_outputs counter.
616 */
617 if (processed_outputs & ((uint64_t)1 << i))
618 continue;
619
620 processed_outputs |= ((uint64_t)1 << i);
621 num_outputs++;
622
623 info->output_semantic_name[i] = semantic_name;
624 info->output_semantic_index[i] = semantic_index;
625
626 switch (semantic_name) {
627 case TGSI_SEMANTIC_PRIMID:
628 info->writes_primid = true;
629 break;
630 case TGSI_SEMANTIC_VIEWPORT_INDEX:
631 info->writes_viewport_index = true;
632 break;
633 case TGSI_SEMANTIC_LAYER:
634 info->writes_layer = true;
635 break;
636 case TGSI_SEMANTIC_PSIZE:
637 info->writes_psize = true;
638 break;
639 case TGSI_SEMANTIC_CLIPVERTEX:
640 info->writes_clipvertex = true;
641 break;
642 case TGSI_SEMANTIC_COLOR:
643 info->colors_written |= 1 << semantic_index;
644 break;
645 case TGSI_SEMANTIC_STENCIL:
646 info->writes_stencil = true;
647 break;
648 case TGSI_SEMANTIC_SAMPLEMASK:
649 info->writes_samplemask = true;
650 break;
651 case TGSI_SEMANTIC_EDGEFLAG:
652 info->writes_edgeflag = true;
653 break;
654 case TGSI_SEMANTIC_POSITION:
655 if (info->processor == PIPE_SHADER_FRAGMENT)
656 info->writes_z = true;
657 else
658 info->writes_position = true;
659 break;
660 }
661
662 if (nir->info.stage == MESA_SHADER_TESS_CTRL) {
663 switch (semantic_name) {
664 case TGSI_SEMANTIC_PATCH:
665 info->reads_perpatch_outputs = true;
666 break;
667 case TGSI_SEMANTIC_TESSINNER:
668 case TGSI_SEMANTIC_TESSOUTER:
669 info->reads_tessfactor_outputs = true;
670 break;
671 default:
672 info->reads_pervertex_outputs = true;
673 }
674 }
675 }
676
677 unsigned loc = variable->data.location;
678 if (nir->info.stage == MESA_SHADER_FRAGMENT &&
679 loc == FRAG_RESULT_COLOR &&
680 nir->info.outputs_written & (1ull << loc)) {
681 assert(attrib_count == 1);
682 info->properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS] = true;
683 }
684 }
685
686 info->num_outputs = num_outputs;
687
688 struct set *ubo_set = _mesa_set_create(NULL, _mesa_hash_pointer,
689 _mesa_key_pointer_equal);
690
691 /* Intialise const_file_max[0] */
692 info->const_file_max[0] = -1;
693
694 unsigned ubo_idx = 1;
695 nir_foreach_variable(variable, &nir->uniforms) {
696 const struct glsl_type *type = variable->type;
697 enum glsl_base_type base_type =
698 glsl_get_base_type(glsl_without_array(type));
699 unsigned aoa_size = MAX2(1, glsl_get_aoa_size(type));
700 unsigned loc = variable->data.location;
701 int slot_count = glsl_count_attribute_slots(type, false);
702 int max_slot = MAX2(info->const_file_max[0], (int) loc) + slot_count;
703
704 /* Gather buffers declared bitmasks. Note: radeonsi doesn't
705 * really use the mask (other than ubo_idx == 1 for regular
706 * uniforms) its really only used for getting the buffer count
707 * so we don't need to worry about the ordering.
708 */
709 if (variable->interface_type != NULL) {
710 if (variable->data.mode == nir_var_uniform ||
711 variable->data.mode == nir_var_mem_ubo) {
712
713 unsigned block_count;
714 if (base_type != GLSL_TYPE_INTERFACE) {
715 struct set_entry *entry =
716 _mesa_set_search(ubo_set, variable->interface_type);
717
718 /* Check if we have already processed
719 * a member from this ubo.
720 */
721 if (entry)
722 continue;
723
724 block_count = 1;
725 } else {
726 block_count = aoa_size;
727 }
728
729 info->const_buffers_declared |= u_bit_consecutive(ubo_idx, block_count);
730 ubo_idx += block_count;
731
732 _mesa_set_add(ubo_set, variable->interface_type);
733 }
734
735 if (variable->data.mode == nir_var_mem_ssbo) {
736 /* TODO: make this more accurate */
737 info->shader_buffers_declared =
738 u_bit_consecutive(0, SI_NUM_SHADER_BUFFERS);
739 }
740
741 continue;
742 }
743
744 /* We rely on the fact that nir_lower_samplers_as_deref has
745 * eliminated struct dereferences.
746 */
747 if (base_type == GLSL_TYPE_SAMPLER) {
748 if (variable->data.bindless) {
749 info->const_buffers_declared |= 1;
750 info->const_file_max[0] = max_slot;
751 } else {
752 info->samplers_declared |=
753 u_bit_consecutive(variable->data.binding, aoa_size);
754 }
755 } else if (base_type == GLSL_TYPE_IMAGE) {
756 if (variable->data.bindless) {
757 info->const_buffers_declared |= 1;
758 info->const_file_max[0] = max_slot;
759 } else {
760 info->images_declared |=
761 u_bit_consecutive(variable->data.binding, aoa_size);
762 }
763 } else if (base_type != GLSL_TYPE_ATOMIC_UINT) {
764 if (strncmp(variable->name, "state.", 6) == 0 ||
765 strncmp(variable->name, "gl_", 3) == 0) {
766 /* FIXME: figure out why piglit tests with builtin
767 * uniforms are failing without this.
768 */
769 info->const_buffers_declared =
770 u_bit_consecutive(0, SI_NUM_CONST_BUFFERS);
771 } else {
772 info->const_buffers_declared |= 1;
773 info->const_file_max[0] = max_slot;
774 }
775 }
776 }
777
778 _mesa_set_destroy(ubo_set, NULL);
779
780 info->num_written_clipdistance = nir->info.clip_distance_array_size;
781 info->num_written_culldistance = nir->info.cull_distance_array_size;
782 info->clipdist_writemask = u_bit_consecutive(0, info->num_written_clipdistance);
783 info->culldist_writemask = u_bit_consecutive(0, info->num_written_culldistance);
784
785 if (info->processor == PIPE_SHADER_FRAGMENT)
786 info->uses_kill = nir->info.fs.uses_discard;
787
788 func = (struct nir_function *)exec_list_get_head_const(&nir->functions);
789 nir_foreach_block(block, func->impl) {
790 nir_foreach_instr(instr, block)
791 scan_instruction(nir, info, instr);
792 }
793 }
794
795 /**
796 * Perform "lowering" operations on the NIR that are run once when the shader
797 * selector is created.
798 */
799 void
800 si_lower_nir(struct si_shader_selector* sel)
801 {
802 /* Adjust the driver location of inputs and outputs. The state tracker
803 * interprets them as slots, while the ac/nir backend interprets them
804 * as individual components.
805 */
806 nir_foreach_variable(variable, &sel->nir->inputs)
807 variable->data.driver_location *= 4;
808
809 nir_foreach_variable(variable, &sel->nir->outputs) {
810 variable->data.driver_location *= 4;
811
812 if (sel->nir->info.stage == MESA_SHADER_FRAGMENT) {
813 if (variable->data.location == FRAG_RESULT_DEPTH)
814 variable->data.driver_location += 2;
815 else if (variable->data.location == FRAG_RESULT_STENCIL)
816 variable->data.driver_location += 1;
817 }
818 }
819
820 /* Perform lowerings (and optimizations) of code.
821 *
822 * Performance considerations aside, we must:
823 * - lower certain ALU operations
824 * - ensure constant offsets for texture instructions are folded
825 * and copy-propagated
826 */
827 NIR_PASS_V(sel->nir, nir_lower_returns);
828 NIR_PASS_V(sel->nir, nir_lower_vars_to_ssa);
829 NIR_PASS_V(sel->nir, nir_lower_alu_to_scalar);
830 NIR_PASS_V(sel->nir, nir_lower_phis_to_scalar);
831
832 static const struct nir_lower_tex_options lower_tex_options = {
833 .lower_txp = ~0u,
834 };
835 NIR_PASS_V(sel->nir, nir_lower_tex, &lower_tex_options);
836
837 const nir_lower_subgroups_options subgroups_options = {
838 .subgroup_size = 64,
839 .ballot_bit_size = 64,
840 .lower_to_scalar = true,
841 .lower_subgroup_masks = true,
842 .lower_vote_trivial = false,
843 .lower_vote_eq_to_ballot = true,
844 };
845 NIR_PASS_V(sel->nir, nir_lower_subgroups, &subgroups_options);
846
847 ac_lower_indirect_derefs(sel->nir, sel->screen->info.chip_class);
848
849 bool progress;
850 do {
851 progress = false;
852
853 /* (Constant) copy propagation is needed for txf with offsets. */
854 NIR_PASS(progress, sel->nir, nir_copy_prop);
855 NIR_PASS(progress, sel->nir, nir_opt_remove_phis);
856 NIR_PASS(progress, sel->nir, nir_opt_dce);
857 if (nir_opt_trivial_continues(sel->nir)) {
858 progress = true;
859 NIR_PASS(progress, sel->nir, nir_copy_prop);
860 NIR_PASS(progress, sel->nir, nir_opt_dce);
861 }
862 NIR_PASS(progress, sel->nir, nir_opt_if);
863 NIR_PASS(progress, sel->nir, nir_opt_dead_cf);
864 NIR_PASS(progress, sel->nir, nir_opt_cse);
865 NIR_PASS(progress, sel->nir, nir_opt_peephole_select, 8, true, true);
866
867 /* Needed for algebraic lowering */
868 NIR_PASS(progress, sel->nir, nir_opt_algebraic);
869 NIR_PASS(progress, sel->nir, nir_opt_constant_folding);
870
871 NIR_PASS(progress, sel->nir, nir_opt_undef);
872 NIR_PASS(progress, sel->nir, nir_opt_conditional_discard);
873 if (sel->nir->options->max_unroll_iterations) {
874 NIR_PASS(progress, sel->nir, nir_opt_loop_unroll, 0);
875 }
876 } while (progress);
877
878 NIR_PASS_V(sel->nir, nir_lower_bool_to_int32);
879 }
880
881 static void declare_nir_input_vs(struct si_shader_context *ctx,
882 struct nir_variable *variable,
883 unsigned input_index,
884 LLVMValueRef out[4])
885 {
886 si_llvm_load_input_vs(ctx, input_index, out);
887 }
888
889 static void declare_nir_input_fs(struct si_shader_context *ctx,
890 struct nir_variable *variable,
891 unsigned input_index,
892 LLVMValueRef out[4])
893 {
894 unsigned slot = variable->data.location;
895 if (slot == VARYING_SLOT_POS) {
896 out[0] = LLVMGetParam(ctx->main_fn, SI_PARAM_POS_X_FLOAT);
897 out[1] = LLVMGetParam(ctx->main_fn, SI_PARAM_POS_Y_FLOAT);
898 out[2] = LLVMGetParam(ctx->main_fn, SI_PARAM_POS_Z_FLOAT);
899 out[3] = ac_build_fdiv(&ctx->ac, ctx->ac.f32_1,
900 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_W_FLOAT));
901 return;
902 }
903
904 si_llvm_load_input_fs(ctx, input_index, out);
905 }
906
907 LLVMValueRef
908 si_nir_lookup_interp_param(struct ac_shader_abi *abi,
909 enum glsl_interp_mode interp, unsigned location)
910 {
911 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
912 int interp_param_idx = -1;
913
914 switch (interp) {
915 case INTERP_MODE_FLAT:
916 return NULL;
917 case INTERP_MODE_SMOOTH:
918 case INTERP_MODE_NONE:
919 if (location == INTERP_CENTER)
920 interp_param_idx = SI_PARAM_PERSP_CENTER;
921 else if (location == INTERP_CENTROID)
922 interp_param_idx = SI_PARAM_PERSP_CENTROID;
923 else if (location == INTERP_SAMPLE)
924 interp_param_idx = SI_PARAM_PERSP_SAMPLE;
925 break;
926 case INTERP_MODE_NOPERSPECTIVE:
927 if (location == INTERP_CENTER)
928 interp_param_idx = SI_PARAM_LINEAR_CENTER;
929 else if (location == INTERP_CENTROID)
930 interp_param_idx = SI_PARAM_LINEAR_CENTROID;
931 else if (location == INTERP_SAMPLE)
932 interp_param_idx = SI_PARAM_LINEAR_SAMPLE;
933 break;
934 default:
935 assert(!"Unhandled interpolation mode.");
936 return NULL;
937 }
938
939 return interp_param_idx != -1 ?
940 LLVMGetParam(ctx->main_fn, interp_param_idx) : NULL;
941 }
942
943 static LLVMValueRef
944 si_nir_load_sampler_desc(struct ac_shader_abi *abi,
945 unsigned descriptor_set, unsigned base_index,
946 unsigned constant_index, LLVMValueRef dynamic_index,
947 enum ac_descriptor_type desc_type, bool image,
948 bool write, bool bindless)
949 {
950 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
951 const struct tgsi_shader_info *info = &ctx->shader->selector->info;
952 LLVMBuilderRef builder = ctx->ac.builder;
953 unsigned const_index = base_index + constant_index;
954 bool dcc_off = write;
955
956 /* TODO: images_store and images_atomic are not set */
957 if (!dynamic_index && image &&
958 (info->images_store | info->images_atomic) & (1 << const_index))
959 dcc_off = true;
960
961 assert(!descriptor_set);
962 assert(!image || desc_type == AC_DESC_IMAGE || desc_type == AC_DESC_BUFFER);
963
964 if (bindless) {
965 LLVMValueRef list =
966 LLVMGetParam(ctx->main_fn, ctx->param_bindless_samplers_and_images);
967
968 /* dynamic_index is the bindless handle */
969 if (image) {
970 /* For simplicity, bindless image descriptors use fixed
971 * 16-dword slots for now.
972 */
973 dynamic_index = LLVMBuildMul(ctx->ac.builder, dynamic_index,
974 LLVMConstInt(ctx->i32, 2, 0), "");
975
976 return si_load_image_desc(ctx, list, dynamic_index, desc_type,
977 dcc_off, true);
978 }
979
980 /* Since bindless handle arithmetic can contain an unsigned integer
981 * wraparound and si_load_sampler_desc assumes there isn't any,
982 * use GEP without "inbounds" (inside ac_build_pointer_add)
983 * to prevent incorrect code generation and hangs.
984 */
985 dynamic_index = LLVMBuildMul(ctx->ac.builder, dynamic_index,
986 LLVMConstInt(ctx->i32, 2, 0), "");
987 list = ac_build_pointer_add(&ctx->ac, list, dynamic_index);
988 return si_load_sampler_desc(ctx, list, ctx->i32_0, desc_type);
989 }
990
991 unsigned num_slots = image ? ctx->num_images : ctx->num_samplers;
992 assert(const_index < num_slots);
993
994 LLVMValueRef list = LLVMGetParam(ctx->main_fn, ctx->param_samplers_and_images);
995 LLVMValueRef index = LLVMConstInt(ctx->ac.i32, const_index, false);
996
997 if (dynamic_index) {
998 index = LLVMBuildAdd(builder, index, dynamic_index, "");
999
1000 /* From the GL_ARB_shader_image_load_store extension spec:
1001 *
1002 * If a shader performs an image load, store, or atomic
1003 * operation using an image variable declared as an array,
1004 * and if the index used to select an individual element is
1005 * negative or greater than or equal to the size of the
1006 * array, the results of the operation are undefined but may
1007 * not lead to termination.
1008 */
1009 index = si_llvm_bound_index(ctx, index, num_slots);
1010 }
1011
1012 if (image) {
1013 index = LLVMBuildSub(ctx->ac.builder,
1014 LLVMConstInt(ctx->i32, SI_NUM_IMAGES - 1, 0),
1015 index, "");
1016 return si_load_image_desc(ctx, list, index, desc_type, dcc_off, false);
1017 }
1018
1019 index = LLVMBuildAdd(ctx->ac.builder, index,
1020 LLVMConstInt(ctx->i32, SI_NUM_IMAGES / 2, 0), "");
1021 return si_load_sampler_desc(ctx, list, index, desc_type);
1022 }
1023
1024 static void bitcast_inputs(struct si_shader_context *ctx,
1025 LLVMValueRef data[4],
1026 unsigned input_idx)
1027 {
1028 for (unsigned chan = 0; chan < 4; chan++) {
1029 ctx->inputs[input_idx + chan] =
1030 LLVMBuildBitCast(ctx->ac.builder, data[chan], ctx->ac.i32, "");
1031 }
1032 }
1033
1034 bool si_nir_build_llvm(struct si_shader_context *ctx, struct nir_shader *nir)
1035 {
1036 struct tgsi_shader_info *info = &ctx->shader->selector->info;
1037
1038 if (nir->info.stage == MESA_SHADER_VERTEX ||
1039 nir->info.stage == MESA_SHADER_FRAGMENT) {
1040 uint64_t processed_inputs = 0;
1041 nir_foreach_variable(variable, &nir->inputs) {
1042 unsigned attrib_count = glsl_count_attribute_slots(variable->type,
1043 nir->info.stage == MESA_SHADER_VERTEX);
1044 unsigned input_idx = variable->data.driver_location;
1045
1046 LLVMValueRef data[4];
1047 unsigned loc = variable->data.location;
1048
1049 if (loc >= VARYING_SLOT_VAR0 && nir->info.stage == MESA_SHADER_FRAGMENT)
1050 ctx->abi.fs_input_attr_indices[loc - VARYING_SLOT_VAR0] = input_idx / 4;
1051
1052 for (unsigned i = 0; i < attrib_count; i++) {
1053 /* Packed components share the same location so skip
1054 * them if we have already processed the location.
1055 */
1056 if (processed_inputs & ((uint64_t)1 << (loc + i))) {
1057 input_idx += 4;
1058 continue;
1059 }
1060
1061 if (nir->info.stage == MESA_SHADER_VERTEX) {
1062 declare_nir_input_vs(ctx, variable, input_idx / 4, data);
1063 bitcast_inputs(ctx, data, input_idx);
1064 if (glsl_type_is_dual_slot(variable->type)) {
1065 input_idx += 4;
1066 declare_nir_input_vs(ctx, variable, input_idx / 4, data);
1067 bitcast_inputs(ctx, data, input_idx);
1068 }
1069 } else if (nir->info.stage == MESA_SHADER_FRAGMENT) {
1070 declare_nir_input_fs(ctx, variable, input_idx / 4, data);
1071 bitcast_inputs(ctx, data, input_idx);
1072 }
1073
1074 processed_inputs |= ((uint64_t)1 << (loc + i));
1075 input_idx += 4;
1076 }
1077 }
1078 }
1079
1080 ctx->abi.inputs = &ctx->inputs[0];
1081 ctx->abi.load_sampler_desc = si_nir_load_sampler_desc;
1082 ctx->abi.clamp_shadow_reference = true;
1083
1084 ctx->num_samplers = util_last_bit(info->samplers_declared);
1085 ctx->num_images = util_last_bit(info->images_declared);
1086
1087 if (ctx->shader->selector->info.properties[TGSI_PROPERTY_CS_LOCAL_SIZE]) {
1088 assert(gl_shader_stage_is_compute(nir->info.stage));
1089 si_declare_compute_memory(ctx);
1090 }
1091 ac_nir_translate(&ctx->ac, &ctx->abi, nir);
1092
1093 return true;
1094 }