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radeonsi/nir: Don't recompute num_inputs and num_outputs
[mesa.git] / src / gallium / drivers / radeonsi / si_shader_nir.c
1 /*
2 * Copyright 2017 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 #include "si_shader_internal.h"
26 #include "si_pipe.h"
27
28 #include "ac_nir_to_llvm.h"
29
30 #include "tgsi/tgsi_from_mesa.h"
31
32 #include "compiler/nir/nir.h"
33 #include "compiler/nir_types.h"
34 #include "compiler/nir/nir_builder.h"
35
36 static nir_variable* tex_get_texture_var(nir_tex_instr *instr)
37 {
38 for (unsigned i = 0; i < instr->num_srcs; i++) {
39 switch (instr->src[i].src_type) {
40 case nir_tex_src_texture_deref:
41 return nir_deref_instr_get_variable(nir_src_as_deref(instr->src[i].src));
42 default:
43 break;
44 }
45 }
46
47 return NULL;
48 }
49
50 static nir_variable* intrinsic_get_var(nir_intrinsic_instr *instr)
51 {
52 return nir_deref_instr_get_variable(nir_src_as_deref(instr->src[0]));
53 }
54
55 static void gather_intrinsic_load_deref_input_info(const nir_shader *nir,
56 const nir_intrinsic_instr *instr,
57 nir_variable *var,
58 struct tgsi_shader_info *info)
59 {
60 assert(var && var->data.mode == nir_var_shader_in);
61
62 switch (nir->info.stage) {
63 case MESA_SHADER_VERTEX: {
64 unsigned i = var->data.driver_location;
65 unsigned attrib_count = glsl_count_attribute_slots(var->type, false);
66 uint8_t mask = nir_ssa_def_components_read(&instr->dest.ssa);
67
68 for (unsigned j = 0; j < attrib_count; j++, i++) {
69 if (glsl_type_is_64bit(glsl_without_array(var->type))) {
70 unsigned dmask = mask;
71
72 if (glsl_type_is_dual_slot(glsl_without_array(var->type)) && j % 2)
73 dmask >>= 2;
74
75 dmask <<= var->data.location_frac / 2;
76
77 if (dmask & 0x1)
78 info->input_usage_mask[i] |= TGSI_WRITEMASK_XY;
79 if (dmask & 0x2)
80 info->input_usage_mask[i] |= TGSI_WRITEMASK_ZW;
81 } else {
82 info->input_usage_mask[i] |=
83 (mask << var->data.location_frac) & 0xf;
84 }
85 }
86 break;
87 }
88 default:;
89 }
90 }
91
92 static void gather_intrinsic_load_deref_output_info(const nir_shader *nir,
93 const nir_intrinsic_instr *instr,
94 nir_variable *var,
95 struct tgsi_shader_info *info)
96 {
97 assert(var && var->data.mode == nir_var_shader_out);
98
99 switch (nir->info.stage) {
100 case MESA_SHADER_TESS_CTRL:
101 if (var->data.location == VARYING_SLOT_TESS_LEVEL_INNER ||
102 var->data.location == VARYING_SLOT_TESS_LEVEL_OUTER)
103 info->reads_tessfactor_outputs = true;
104 else if (var->data.patch)
105 info->reads_perpatch_outputs = true;
106 else
107 info->reads_pervertex_outputs = true;
108 break;
109
110 case MESA_SHADER_FRAGMENT:
111 if (var->data.fb_fetch_output)
112 info->uses_fbfetch = true;
113 break;
114 default:;
115 }
116 }
117
118 static void gather_intrinsic_store_deref_output_info(const nir_shader *nir,
119 const nir_intrinsic_instr *instr,
120 nir_variable *var,
121 struct tgsi_shader_info *info)
122 {
123 assert(var && var->data.mode == nir_var_shader_out);
124
125 switch (nir->info.stage) {
126 case MESA_SHADER_VERTEX: /* needed by LS, ES */
127 case MESA_SHADER_TESS_EVAL: /* needed by ES */
128 case MESA_SHADER_GEOMETRY: {
129 unsigned i = var->data.driver_location;
130 unsigned attrib_count = glsl_count_attribute_slots(var->type, false);
131 unsigned mask = nir_intrinsic_write_mask(instr);
132
133 assert(!var->data.compact);
134
135 for (unsigned j = 0; j < attrib_count; j++, i++) {
136 if (glsl_type_is_64bit(glsl_without_array(var->type))) {
137 unsigned dmask = mask;
138
139 if (glsl_type_is_dual_slot(glsl_without_array(var->type)) && j % 2)
140 dmask >>= 2;
141
142 dmask <<= var->data.location_frac / 2;
143
144 if (dmask & 0x1)
145 info->output_usagemask[i] |= TGSI_WRITEMASK_XY;
146 if (dmask & 0x2)
147 info->output_usagemask[i] |= TGSI_WRITEMASK_ZW;
148 } else {
149 info->output_usagemask[i] |=
150 (mask << var->data.location_frac) & 0xf;
151 }
152
153 }
154 break;
155 }
156 default:;
157 }
158 }
159
160 static void scan_instruction(const struct nir_shader *nir,
161 struct tgsi_shader_info *info,
162 nir_instr *instr)
163 {
164 if (instr->type == nir_instr_type_alu) {
165 nir_alu_instr *alu = nir_instr_as_alu(instr);
166
167 switch (alu->op) {
168 case nir_op_fddx:
169 case nir_op_fddy:
170 case nir_op_fddx_fine:
171 case nir_op_fddy_fine:
172 case nir_op_fddx_coarse:
173 case nir_op_fddy_coarse:
174 info->uses_derivatives = true;
175 break;
176 default:
177 break;
178 }
179 } else if (instr->type == nir_instr_type_tex) {
180 nir_tex_instr *tex = nir_instr_as_tex(instr);
181 nir_variable *texture = tex_get_texture_var(tex);
182
183 if (!texture) {
184 info->samplers_declared |=
185 u_bit_consecutive(tex->sampler_index, 1);
186 } else {
187 if (texture->data.bindless)
188 info->uses_bindless_samplers = true;
189 }
190
191 switch (tex->op) {
192 case nir_texop_tex:
193 case nir_texop_txb:
194 case nir_texop_lod:
195 info->uses_derivatives = true;
196 break;
197 default:
198 break;
199 }
200 } else if (instr->type == nir_instr_type_intrinsic) {
201 nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);
202
203 switch (intr->intrinsic) {
204 case nir_intrinsic_load_front_face:
205 info->uses_frontface = 1;
206 break;
207 case nir_intrinsic_load_instance_id:
208 info->uses_instanceid = 1;
209 break;
210 case nir_intrinsic_load_invocation_id:
211 info->uses_invocationid = true;
212 break;
213 case nir_intrinsic_load_num_work_groups:
214 info->uses_grid_size = true;
215 break;
216 case nir_intrinsic_load_local_group_size:
217 /* The block size is translated to IMM with a fixed block size. */
218 if (info->properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] == 0)
219 info->uses_block_size = true;
220 break;
221 case nir_intrinsic_load_local_invocation_id:
222 case nir_intrinsic_load_work_group_id: {
223 unsigned mask = nir_ssa_def_components_read(&intr->dest.ssa);
224 while (mask) {
225 unsigned i = u_bit_scan(&mask);
226
227 if (intr->intrinsic == nir_intrinsic_load_work_group_id)
228 info->uses_block_id[i] = true;
229 else
230 info->uses_thread_id[i] = true;
231 }
232 break;
233 }
234 case nir_intrinsic_load_vertex_id:
235 info->uses_vertexid = 1;
236 break;
237 case nir_intrinsic_load_vertex_id_zero_base:
238 info->uses_vertexid_nobase = 1;
239 break;
240 case nir_intrinsic_load_base_vertex:
241 info->uses_basevertex = 1;
242 break;
243 case nir_intrinsic_load_draw_id:
244 info->uses_drawid = 1;
245 break;
246 case nir_intrinsic_load_primitive_id:
247 info->uses_primid = 1;
248 break;
249 case nir_intrinsic_load_sample_mask_in:
250 info->reads_samplemask = true;
251 break;
252 case nir_intrinsic_load_tess_level_inner:
253 case nir_intrinsic_load_tess_level_outer:
254 info->reads_tess_factors = true;
255 break;
256 case nir_intrinsic_bindless_image_load:
257 info->uses_bindless_images = true;
258
259 if (nir_intrinsic_image_dim(intr) == GLSL_SAMPLER_DIM_BUF)
260 info->uses_bindless_buffer_load = true;
261 else
262 info->uses_bindless_image_load = true;
263 break;
264 case nir_intrinsic_bindless_image_size:
265 case nir_intrinsic_bindless_image_samples:
266 info->uses_bindless_images = true;
267 break;
268 case nir_intrinsic_bindless_image_store:
269 info->uses_bindless_images = true;
270
271 if (nir_intrinsic_image_dim(intr) == GLSL_SAMPLER_DIM_BUF)
272 info->uses_bindless_buffer_store = true;
273 else
274 info->uses_bindless_image_store = true;
275
276 info->writes_memory = true;
277 info->num_memory_instructions++; /* we only care about stores */
278 break;
279 case nir_intrinsic_image_deref_store:
280 info->writes_memory = true;
281 info->num_memory_instructions++; /* we only care about stores */
282 break;
283 case nir_intrinsic_bindless_image_atomic_add:
284 case nir_intrinsic_bindless_image_atomic_imin:
285 case nir_intrinsic_bindless_image_atomic_umin:
286 case nir_intrinsic_bindless_image_atomic_imax:
287 case nir_intrinsic_bindless_image_atomic_umax:
288 case nir_intrinsic_bindless_image_atomic_and:
289 case nir_intrinsic_bindless_image_atomic_or:
290 case nir_intrinsic_bindless_image_atomic_xor:
291 case nir_intrinsic_bindless_image_atomic_exchange:
292 case nir_intrinsic_bindless_image_atomic_comp_swap:
293 info->uses_bindless_images = true;
294
295 if (nir_intrinsic_image_dim(intr) == GLSL_SAMPLER_DIM_BUF)
296 info->uses_bindless_buffer_atomic = true;
297 else
298 info->uses_bindless_image_atomic = true;
299
300 info->writes_memory = true;
301 info->num_memory_instructions++; /* we only care about stores */
302 break;
303 case nir_intrinsic_image_deref_atomic_add:
304 case nir_intrinsic_image_deref_atomic_imin:
305 case nir_intrinsic_image_deref_atomic_umin:
306 case nir_intrinsic_image_deref_atomic_imax:
307 case nir_intrinsic_image_deref_atomic_umax:
308 case nir_intrinsic_image_deref_atomic_and:
309 case nir_intrinsic_image_deref_atomic_or:
310 case nir_intrinsic_image_deref_atomic_xor:
311 case nir_intrinsic_image_deref_atomic_exchange:
312 case nir_intrinsic_image_deref_atomic_comp_swap:
313 case nir_intrinsic_image_deref_atomic_inc_wrap:
314 case nir_intrinsic_image_deref_atomic_dec_wrap:
315 info->writes_memory = true;
316 info->num_memory_instructions++; /* we only care about stores */
317 break;
318 case nir_intrinsic_store_ssbo:
319 case nir_intrinsic_ssbo_atomic_add:
320 case nir_intrinsic_ssbo_atomic_imin:
321 case nir_intrinsic_ssbo_atomic_umin:
322 case nir_intrinsic_ssbo_atomic_imax:
323 case nir_intrinsic_ssbo_atomic_umax:
324 case nir_intrinsic_ssbo_atomic_and:
325 case nir_intrinsic_ssbo_atomic_or:
326 case nir_intrinsic_ssbo_atomic_xor:
327 case nir_intrinsic_ssbo_atomic_exchange:
328 case nir_intrinsic_ssbo_atomic_comp_swap:
329 info->writes_memory = true;
330 info->num_memory_instructions++; /* we only care about stores */
331 break;
332 case nir_intrinsic_load_color0:
333 case nir_intrinsic_load_color1: {
334 unsigned index = intr->intrinsic == nir_intrinsic_load_color1;
335 uint8_t mask = nir_ssa_def_components_read(&intr->dest.ssa);
336 info->colors_read |= mask << (index * 4);
337 break;
338 }
339 case nir_intrinsic_load_barycentric_pixel:
340 case nir_intrinsic_load_barycentric_centroid:
341 case nir_intrinsic_load_barycentric_sample:
342 case nir_intrinsic_load_barycentric_at_offset: /* uses center */
343 case nir_intrinsic_load_barycentric_at_sample: { /* uses center */
344 unsigned mode = nir_intrinsic_interp_mode(intr);
345
346 if (mode == INTERP_MODE_FLAT)
347 break;
348
349 if (mode == INTERP_MODE_NOPERSPECTIVE) {
350 if (intr->intrinsic == nir_intrinsic_load_barycentric_sample)
351 info->uses_linear_sample = true;
352 else if (intr->intrinsic == nir_intrinsic_load_barycentric_centroid)
353 info->uses_linear_centroid = true;
354 else
355 info->uses_linear_center = true;
356
357 if (intr->intrinsic == nir_intrinsic_load_barycentric_at_sample)
358 info->uses_linear_opcode_interp_sample = true;
359 } else {
360 if (intr->intrinsic == nir_intrinsic_load_barycentric_sample)
361 info->uses_persp_sample = true;
362 else if (intr->intrinsic == nir_intrinsic_load_barycentric_centroid)
363 info->uses_persp_centroid = true;
364 else
365 info->uses_persp_center = true;
366
367 if (intr->intrinsic == nir_intrinsic_load_barycentric_at_sample)
368 info->uses_persp_opcode_interp_sample = true;
369 }
370 break;
371 }
372 case nir_intrinsic_load_deref: {
373 nir_variable *var = intrinsic_get_var(intr);
374 nir_variable_mode mode = var->data.mode;
375
376 if (mode == nir_var_shader_in) {
377 /* PS inputs use the interpolated load intrinsics. */
378 assert(nir->info.stage != MESA_SHADER_FRAGMENT);
379 gather_intrinsic_load_deref_input_info(nir, intr, var, info);
380 } else if (mode == nir_var_shader_out) {
381 gather_intrinsic_load_deref_output_info(nir, intr, var, info);
382 }
383 break;
384 }
385 case nir_intrinsic_store_deref: {
386 nir_variable *var = intrinsic_get_var(intr);
387
388 if (var->data.mode == nir_var_shader_out)
389 gather_intrinsic_store_deref_output_info(nir, intr, var, info);
390 break;
391 }
392 case nir_intrinsic_interp_deref_at_centroid:
393 case nir_intrinsic_interp_deref_at_sample:
394 case nir_intrinsic_interp_deref_at_offset:
395 unreachable("interp opcodes should have been lowered");
396 break;
397 default:
398 break;
399 }
400 }
401 }
402
403 void si_nir_scan_tess_ctrl(const struct nir_shader *nir,
404 struct tgsi_tessctrl_info *out)
405 {
406 memset(out, 0, sizeof(*out));
407
408 if (nir->info.stage != MESA_SHADER_TESS_CTRL)
409 return;
410
411 out->tessfactors_are_def_in_all_invocs =
412 ac_are_tessfactors_def_in_all_invocs(nir);
413 }
414
415 void si_nir_scan_shader(const struct nir_shader *nir,
416 struct tgsi_shader_info *info)
417 {
418 nir_function *func;
419 unsigned i;
420
421 info->processor = pipe_shader_type_from_mesa(nir->info.stage);
422 info->num_tokens = 2; /* indicate that the shader is non-empty */
423 info->num_instructions = 2;
424
425 info->properties[TGSI_PROPERTY_NEXT_SHADER] =
426 pipe_shader_type_from_mesa(nir->info.next_stage);
427
428 if (nir->info.stage == MESA_SHADER_VERTEX) {
429 info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION] =
430 nir->info.vs.window_space_position;
431 info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD] =
432 nir->info.vs.blit_sgprs_amd;
433 }
434
435 if (nir->info.stage == MESA_SHADER_TESS_CTRL) {
436 info->properties[TGSI_PROPERTY_TCS_VERTICES_OUT] =
437 nir->info.tess.tcs_vertices_out;
438 }
439
440 if (nir->info.stage == MESA_SHADER_TESS_EVAL) {
441 if (nir->info.tess.primitive_mode == GL_ISOLINES)
442 info->properties[TGSI_PROPERTY_TES_PRIM_MODE] = PIPE_PRIM_LINES;
443 else
444 info->properties[TGSI_PROPERTY_TES_PRIM_MODE] = nir->info.tess.primitive_mode;
445
446 STATIC_ASSERT((TESS_SPACING_EQUAL + 1) % 3 == PIPE_TESS_SPACING_EQUAL);
447 STATIC_ASSERT((TESS_SPACING_FRACTIONAL_ODD + 1) % 3 ==
448 PIPE_TESS_SPACING_FRACTIONAL_ODD);
449 STATIC_ASSERT((TESS_SPACING_FRACTIONAL_EVEN + 1) % 3 ==
450 PIPE_TESS_SPACING_FRACTIONAL_EVEN);
451
452 info->properties[TGSI_PROPERTY_TES_SPACING] = (nir->info.tess.spacing + 1) % 3;
453 info->properties[TGSI_PROPERTY_TES_VERTEX_ORDER_CW] = !nir->info.tess.ccw;
454 info->properties[TGSI_PROPERTY_TES_POINT_MODE] = nir->info.tess.point_mode;
455 }
456
457 if (nir->info.stage == MESA_SHADER_GEOMETRY) {
458 info->properties[TGSI_PROPERTY_GS_INPUT_PRIM] = nir->info.gs.input_primitive;
459 info->properties[TGSI_PROPERTY_GS_OUTPUT_PRIM] = nir->info.gs.output_primitive;
460 info->properties[TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES] = nir->info.gs.vertices_out;
461 info->properties[TGSI_PROPERTY_GS_INVOCATIONS] = nir->info.gs.invocations;
462 }
463
464 if (nir->info.stage == MESA_SHADER_FRAGMENT) {
465 info->properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL] =
466 nir->info.fs.early_fragment_tests | nir->info.fs.post_depth_coverage;
467 info->properties[TGSI_PROPERTY_FS_POST_DEPTH_COVERAGE] = nir->info.fs.post_depth_coverage;
468
469 if (nir->info.fs.pixel_center_integer) {
470 info->properties[TGSI_PROPERTY_FS_COORD_PIXEL_CENTER] =
471 TGSI_FS_COORD_PIXEL_CENTER_INTEGER;
472 }
473
474 if (nir->info.fs.depth_layout != FRAG_DEPTH_LAYOUT_NONE) {
475 switch (nir->info.fs.depth_layout) {
476 case FRAG_DEPTH_LAYOUT_ANY:
477 info->properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT] = TGSI_FS_DEPTH_LAYOUT_ANY;
478 break;
479 case FRAG_DEPTH_LAYOUT_GREATER:
480 info->properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT] = TGSI_FS_DEPTH_LAYOUT_GREATER;
481 break;
482 case FRAG_DEPTH_LAYOUT_LESS:
483 info->properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT] = TGSI_FS_DEPTH_LAYOUT_LESS;
484 break;
485 case FRAG_DEPTH_LAYOUT_UNCHANGED:
486 info->properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT] = TGSI_FS_DEPTH_LAYOUT_UNCHANGED;
487 break;
488 default:
489 unreachable("Unknow depth layout");
490 }
491 }
492 }
493
494 if (gl_shader_stage_is_compute(nir->info.stage)) {
495 info->properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] = nir->info.cs.local_size[0];
496 info->properties[TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT] = nir->info.cs.local_size[1];
497 info->properties[TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH] = nir->info.cs.local_size[2];
498 info->properties[TGSI_PROPERTY_CS_USER_DATA_COMPONENTS_AMD] = nir->info.cs.user_data_components_amd;
499 }
500
501 i = 0;
502 uint64_t processed_inputs = 0;
503 nir_foreach_variable(variable, &nir->inputs) {
504 unsigned semantic_name, semantic_index;
505
506 const struct glsl_type *type = variable->type;
507 if (nir_is_per_vertex_io(variable, nir->info.stage)) {
508 assert(glsl_type_is_array(type));
509 type = glsl_get_array_element(type);
510 }
511
512 unsigned attrib_count = glsl_count_attribute_slots(type,
513 nir->info.stage == MESA_SHADER_VERTEX);
514
515 i = variable->data.driver_location;
516
517 /* Vertex shader inputs don't have semantics. The state
518 * tracker has already mapped them to attributes via
519 * variable->data.driver_location.
520 */
521 if (nir->info.stage == MESA_SHADER_VERTEX)
522 continue;
523
524 for (unsigned j = 0; j < attrib_count; j++, i++) {
525
526 if (processed_inputs & ((uint64_t)1 << i))
527 continue;
528
529 processed_inputs |= ((uint64_t)1 << i);
530
531 tgsi_get_gl_varying_semantic(variable->data.location + j, true,
532 &semantic_name, &semantic_index);
533
534 info->input_semantic_name[i] = semantic_name;
535 info->input_semantic_index[i] = semantic_index;
536
537 if (semantic_name == TGSI_SEMANTIC_PRIMID)
538 info->uses_primid = true;
539
540 if (semantic_name == TGSI_SEMANTIC_COLOR) {
541 /* We only need this for color inputs. */
542 if (variable->data.sample)
543 info->input_interpolate_loc[i] = TGSI_INTERPOLATE_LOC_SAMPLE;
544 else if (variable->data.centroid)
545 info->input_interpolate_loc[i] = TGSI_INTERPOLATE_LOC_CENTROID;
546 else
547 info->input_interpolate_loc[i] = TGSI_INTERPOLATE_LOC_CENTER;
548 }
549
550 enum glsl_base_type base_type =
551 glsl_get_base_type(glsl_without_array(variable->type));
552
553 switch (variable->data.interpolation) {
554 case INTERP_MODE_NONE:
555 if (glsl_base_type_is_integer(base_type)) {
556 info->input_interpolate[i] = TGSI_INTERPOLATE_CONSTANT;
557 break;
558 }
559
560 if (semantic_name == TGSI_SEMANTIC_COLOR) {
561 info->input_interpolate[i] = TGSI_INTERPOLATE_COLOR;
562 break;
563 }
564 /* fall-through */
565
566 case INTERP_MODE_SMOOTH:
567 assert(!glsl_base_type_is_integer(base_type));
568
569 info->input_interpolate[i] = TGSI_INTERPOLATE_PERSPECTIVE;
570 break;
571
572 case INTERP_MODE_NOPERSPECTIVE:
573 assert(!glsl_base_type_is_integer(base_type));
574
575 info->input_interpolate[i] = TGSI_INTERPOLATE_LINEAR;
576 break;
577
578 case INTERP_MODE_FLAT:
579 info->input_interpolate[i] = TGSI_INTERPOLATE_CONSTANT;
580 break;
581 }
582 }
583 }
584
585 nir_foreach_variable(variable, &nir->outputs) {
586 unsigned semantic_name, semantic_index;
587
588 i = variable->data.driver_location;
589
590 const struct glsl_type *type = variable->type;
591 if (nir_is_per_vertex_io(variable, nir->info.stage)) {
592 assert(glsl_type_is_array(type));
593 type = glsl_get_array_element(type);
594 }
595
596 unsigned attrib_count = glsl_count_attribute_slots(type, false);
597 for (unsigned k = 0; k < attrib_count; k++, i++) {
598
599 if (nir->info.stage == MESA_SHADER_FRAGMENT) {
600 tgsi_get_gl_frag_result_semantic(variable->data.location + k,
601 &semantic_name, &semantic_index);
602
603 /* Adjust for dual source blending */
604 if (variable->data.index > 0) {
605 semantic_index++;
606 }
607 } else {
608 tgsi_get_gl_varying_semantic(variable->data.location + k, true,
609 &semantic_name, &semantic_index);
610 }
611
612 unsigned num_components = 4;
613 unsigned vector_elements = glsl_get_vector_elements(glsl_without_array(variable->type));
614 if (vector_elements)
615 num_components = vector_elements;
616
617 unsigned component = variable->data.location_frac;
618 if (glsl_type_is_64bit(glsl_without_array(variable->type))) {
619 if (glsl_type_is_dual_slot(glsl_without_array(variable->type)) && k % 2) {
620 num_components = (num_components * 2) - 4;
621 component = 0;
622 } else {
623 num_components = MIN2(num_components * 2, 4);
624 }
625 }
626
627 ubyte usagemask = 0;
628 for (unsigned j = component; j < num_components + component; j++) {
629 switch (j) {
630 case 0:
631 usagemask |= TGSI_WRITEMASK_X;
632 break;
633 case 1:
634 usagemask |= TGSI_WRITEMASK_Y;
635 break;
636 case 2:
637 usagemask |= TGSI_WRITEMASK_Z;
638 break;
639 case 3:
640 usagemask |= TGSI_WRITEMASK_W;
641 break;
642 default:
643 unreachable("error calculating component index");
644 }
645 }
646
647 unsigned gs_out_streams;
648 if (variable->data.stream & (1u << 31)) {
649 gs_out_streams = variable->data.stream & ~(1u << 31);
650 } else {
651 assert(variable->data.stream < 4);
652 gs_out_streams = 0;
653 for (unsigned j = 0; j < num_components; ++j)
654 gs_out_streams |= variable->data.stream << (2 * (component + j));
655 }
656
657 unsigned streamx = gs_out_streams & 3;
658 unsigned streamy = (gs_out_streams >> 2) & 3;
659 unsigned streamz = (gs_out_streams >> 4) & 3;
660 unsigned streamw = (gs_out_streams >> 6) & 3;
661
662 if (usagemask & TGSI_WRITEMASK_X) {
663 info->output_streams[i] |= streamx;
664 info->num_stream_output_components[streamx]++;
665 }
666 if (usagemask & TGSI_WRITEMASK_Y) {
667 info->output_streams[i] |= streamy << 2;
668 info->num_stream_output_components[streamy]++;
669 }
670 if (usagemask & TGSI_WRITEMASK_Z) {
671 info->output_streams[i] |= streamz << 4;
672 info->num_stream_output_components[streamz]++;
673 }
674 if (usagemask & TGSI_WRITEMASK_W) {
675 info->output_streams[i] |= streamw << 6;
676 info->num_stream_output_components[streamw]++;
677 }
678
679 info->output_semantic_name[i] = semantic_name;
680 info->output_semantic_index[i] = semantic_index;
681
682 switch (semantic_name) {
683 case TGSI_SEMANTIC_PRIMID:
684 info->writes_primid = true;
685 break;
686 case TGSI_SEMANTIC_VIEWPORT_INDEX:
687 info->writes_viewport_index = true;
688 break;
689 case TGSI_SEMANTIC_LAYER:
690 info->writes_layer = true;
691 break;
692 case TGSI_SEMANTIC_PSIZE:
693 info->writes_psize = true;
694 break;
695 case TGSI_SEMANTIC_CLIPVERTEX:
696 info->writes_clipvertex = true;
697 break;
698 case TGSI_SEMANTIC_COLOR:
699 info->colors_written |= 1 << semantic_index;
700 break;
701 case TGSI_SEMANTIC_STENCIL:
702 info->writes_stencil = true;
703 break;
704 case TGSI_SEMANTIC_SAMPLEMASK:
705 info->writes_samplemask = true;
706 break;
707 case TGSI_SEMANTIC_EDGEFLAG:
708 info->writes_edgeflag = true;
709 break;
710 case TGSI_SEMANTIC_POSITION:
711 if (info->processor == PIPE_SHADER_FRAGMENT)
712 info->writes_z = true;
713 else
714 info->writes_position = true;
715 break;
716 }
717 }
718
719 unsigned loc = variable->data.location;
720 if (nir->info.stage == MESA_SHADER_FRAGMENT &&
721 loc == FRAG_RESULT_COLOR &&
722 nir->info.outputs_written & (1ull << loc)) {
723 assert(attrib_count == 1);
724 info->properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS] = true;
725 }
726 }
727
728 info->num_inputs = nir->num_inputs;
729 info->num_outputs = nir->num_outputs;
730
731 struct set *ubo_set = _mesa_set_create(NULL, _mesa_hash_pointer,
732 _mesa_key_pointer_equal);
733 struct set *ssbo_set = _mesa_set_create(NULL, _mesa_hash_pointer,
734 _mesa_key_pointer_equal);
735
736 /* Intialise const_file_max[0] */
737 info->const_file_max[0] = -1;
738
739 /* The first 8 are reserved for atomic counters using ssbo */
740 unsigned ssbo_idx = 8;
741
742 unsigned ubo_idx = 1;
743 nir_foreach_variable(variable, &nir->uniforms) {
744 const struct glsl_type *type = variable->type;
745 enum glsl_base_type base_type =
746 glsl_get_base_type(glsl_without_array(type));
747 unsigned aoa_size = MAX2(1, glsl_get_aoa_size(type));
748 unsigned loc = variable->data.driver_location / 4;
749 int slot_count = glsl_count_attribute_slots(type, false);
750 int max_slot = MAX2(info->const_file_max[0], (int) loc) + slot_count;
751
752 /* Gather buffers declared bitmasks. Note: radeonsi doesn't
753 * really use the mask (other than ubo_idx == 1 for regular
754 * uniforms) its really only used for getting the buffer count
755 * so we don't need to worry about the ordering.
756 */
757 if (variable->interface_type != NULL) {
758 if (variable->data.mode == nir_var_uniform ||
759 variable->data.mode == nir_var_mem_ubo ||
760 variable->data.mode == nir_var_mem_ssbo) {
761
762 struct set *buf_set = variable->data.mode == nir_var_mem_ssbo ?
763 ssbo_set : ubo_set;
764
765 unsigned block_count;
766 if (base_type != GLSL_TYPE_INTERFACE) {
767 struct set_entry *entry =
768 _mesa_set_search(buf_set, variable->interface_type);
769
770 /* Check if we have already processed
771 * a member from this ubo.
772 */
773 if (entry)
774 continue;
775
776 block_count = 1;
777 } else {
778 block_count = aoa_size;
779 }
780
781 if (variable->data.mode == nir_var_uniform ||
782 variable->data.mode == nir_var_mem_ubo) {
783 info->const_buffers_declared |= u_bit_consecutive(ubo_idx, block_count);
784 ubo_idx += block_count;
785 } else {
786 assert(variable->data.mode == nir_var_mem_ssbo);
787
788 info->shader_buffers_declared |= u_bit_consecutive(ssbo_idx, block_count);
789 ssbo_idx += block_count;
790 }
791
792 _mesa_set_add(buf_set, variable->interface_type);
793 }
794
795 continue;
796 }
797
798 /* We rely on the fact that nir_lower_samplers_as_deref has
799 * eliminated struct dereferences.
800 */
801 if (base_type == GLSL_TYPE_SAMPLER && !variable->data.bindless) {
802 info->samplers_declared |=
803 u_bit_consecutive(variable->data.binding, aoa_size);
804 } else if (base_type == GLSL_TYPE_IMAGE && !variable->data.bindless) {
805 info->images_declared |=
806 u_bit_consecutive(variable->data.binding, aoa_size);
807 } else if (base_type != GLSL_TYPE_ATOMIC_UINT) {
808 info->const_buffers_declared |= 1;
809 info->const_file_max[0] = max_slot;
810 }
811 }
812
813 _mesa_set_destroy(ubo_set, NULL);
814 _mesa_set_destroy(ssbo_set, NULL);
815
816 info->num_written_clipdistance = nir->info.clip_distance_array_size;
817 info->num_written_culldistance = nir->info.cull_distance_array_size;
818 info->clipdist_writemask = u_bit_consecutive(0, info->num_written_clipdistance);
819 info->culldist_writemask = u_bit_consecutive(0, info->num_written_culldistance);
820
821 if (info->processor == PIPE_SHADER_FRAGMENT)
822 info->uses_kill = nir->info.fs.uses_discard;
823
824 func = (struct nir_function *)exec_list_get_head_const(&nir->functions);
825 nir_foreach_block(block, func->impl) {
826 nir_foreach_instr(instr, block)
827 scan_instruction(nir, info, instr);
828 }
829 }
830
831 void
832 si_nir_opts(struct nir_shader *nir)
833 {
834 bool progress;
835 unsigned lower_flrp =
836 (nir->options->lower_flrp16 ? 16 : 0) |
837 (nir->options->lower_flrp32 ? 32 : 0) |
838 (nir->options->lower_flrp64 ? 64 : 0);
839
840 do {
841 progress = false;
842
843 NIR_PASS_V(nir, nir_lower_vars_to_ssa);
844
845 NIR_PASS(progress, nir, nir_opt_copy_prop_vars);
846 NIR_PASS(progress, nir, nir_opt_dead_write_vars);
847
848 NIR_PASS_V(nir, nir_lower_alu_to_scalar, NULL);
849 NIR_PASS_V(nir, nir_lower_phis_to_scalar);
850
851 /* (Constant) copy propagation is needed for txf with offsets. */
852 NIR_PASS(progress, nir, nir_copy_prop);
853 NIR_PASS(progress, nir, nir_opt_remove_phis);
854 NIR_PASS(progress, nir, nir_opt_dce);
855 if (nir_opt_trivial_continues(nir)) {
856 progress = true;
857 NIR_PASS(progress, nir, nir_copy_prop);
858 NIR_PASS(progress, nir, nir_opt_dce);
859 }
860 NIR_PASS(progress, nir, nir_opt_if, true);
861 NIR_PASS(progress, nir, nir_opt_dead_cf);
862 NIR_PASS(progress, nir, nir_opt_cse);
863 NIR_PASS(progress, nir, nir_opt_peephole_select, 8, true, true);
864
865 /* Needed for algebraic lowering */
866 NIR_PASS(progress, nir, nir_opt_algebraic);
867 NIR_PASS(progress, nir, nir_opt_constant_folding);
868
869 if (lower_flrp != 0) {
870 bool lower_flrp_progress = false;
871
872 NIR_PASS(lower_flrp_progress, nir, nir_lower_flrp,
873 lower_flrp,
874 false /* always_precise */,
875 nir->options->lower_ffma);
876 if (lower_flrp_progress) {
877 NIR_PASS(progress, nir,
878 nir_opt_constant_folding);
879 progress = true;
880 }
881
882 /* Nothing should rematerialize any flrps, so we only
883 * need to do this lowering once.
884 */
885 lower_flrp = 0;
886 }
887
888 NIR_PASS(progress, nir, nir_opt_undef);
889 NIR_PASS(progress, nir, nir_opt_conditional_discard);
890 if (nir->options->max_unroll_iterations) {
891 NIR_PASS(progress, nir, nir_opt_loop_unroll, 0);
892 }
893 } while (progress);
894 }
895
896 static int
897 type_size_vec4(const struct glsl_type *type, bool bindless)
898 {
899 return glsl_count_attribute_slots(type, false);
900 }
901
902 static void
903 si_nir_lower_color(nir_shader *nir)
904 {
905 nir_function_impl *entrypoint = nir_shader_get_entrypoint(nir);
906
907 nir_builder b;
908 nir_builder_init(&b, entrypoint);
909
910 nir_foreach_block(block, entrypoint) {
911 nir_foreach_instr_safe(instr, block) {
912 if (instr->type != nir_instr_type_intrinsic)
913 continue;
914
915 nir_intrinsic_instr *intrin =
916 nir_instr_as_intrinsic(instr);
917
918 if (intrin->intrinsic != nir_intrinsic_load_deref)
919 continue;
920
921 nir_deref_instr *deref = nir_src_as_deref(intrin->src[0]);
922 if (deref->mode != nir_var_shader_in)
923 continue;
924
925 b.cursor = nir_before_instr(instr);
926 nir_variable *var = nir_deref_instr_get_variable(deref);
927 nir_ssa_def *def;
928
929 if (var->data.location == VARYING_SLOT_COL0) {
930 def = nir_load_color0(&b);
931 } else if (var->data.location == VARYING_SLOT_COL1) {
932 def = nir_load_color1(&b);
933 } else {
934 continue;
935 }
936
937 nir_ssa_def_rewrite_uses(&intrin->dest.ssa, nir_src_for_ssa(def));
938 nir_instr_remove(instr);
939 }
940 }
941 }
942
943 void si_nir_lower_ps_inputs(struct nir_shader *nir)
944 {
945 if (nir->info.stage != MESA_SHADER_FRAGMENT)
946 return;
947
948 NIR_PASS_V(nir, nir_lower_io_to_temporaries,
949 nir_shader_get_entrypoint(nir), false, true);
950
951 /* Since we're doing nir_lower_io_to_temporaries late, we need
952 * to lower all the copy_deref's introduced by
953 * lower_io_to_temporaries before calling nir_lower_io.
954 */
955 NIR_PASS_V(nir, nir_split_var_copies);
956 NIR_PASS_V(nir, nir_lower_var_copies);
957 NIR_PASS_V(nir, nir_lower_global_vars_to_local);
958
959 si_nir_lower_color(nir);
960 NIR_PASS_V(nir, nir_lower_io, nir_var_shader_in, type_size_vec4, 0);
961
962 /* This pass needs actual constants */
963 NIR_PASS_V(nir, nir_opt_constant_folding);
964 NIR_PASS_V(nir, nir_io_add_const_offset_to_base,
965 nir_var_shader_in);
966 }
967
968 /**
969 * Perform "lowering" operations on the NIR that are run once when the shader
970 * selector is created.
971 */
972 void si_lower_nir(struct si_shader_selector *sel)
973 {
974 /* Adjust the driver location of inputs and outputs. The state tracker
975 * interprets them as slots, while the ac/nir backend interprets them
976 * as individual components.
977 */
978 if (sel->nir->info.stage != MESA_SHADER_FRAGMENT) {
979 nir_foreach_variable(variable, &sel->nir->inputs)
980 variable->data.driver_location *= 4;
981 }
982
983 nir_foreach_variable(variable, &sel->nir->outputs) {
984 variable->data.driver_location *= 4;
985
986 if (sel->nir->info.stage == MESA_SHADER_FRAGMENT) {
987 if (variable->data.location == FRAG_RESULT_DEPTH)
988 variable->data.driver_location += 2;
989 else if (variable->data.location == FRAG_RESULT_STENCIL)
990 variable->data.driver_location += 1;
991 }
992 }
993
994 /* Perform lowerings (and optimizations) of code.
995 *
996 * Performance considerations aside, we must:
997 * - lower certain ALU operations
998 * - ensure constant offsets for texture instructions are folded
999 * and copy-propagated
1000 */
1001
1002 static const struct nir_lower_tex_options lower_tex_options = {
1003 .lower_txp = ~0u,
1004 };
1005 NIR_PASS_V(sel->nir, nir_lower_tex, &lower_tex_options);
1006
1007 const nir_lower_subgroups_options subgroups_options = {
1008 .subgroup_size = 64,
1009 .ballot_bit_size = 64,
1010 .lower_to_scalar = true,
1011 .lower_subgroup_masks = true,
1012 .lower_vote_trivial = false,
1013 .lower_vote_eq_to_ballot = true,
1014 };
1015 NIR_PASS_V(sel->nir, nir_lower_subgroups, &subgroups_options);
1016
1017 ac_lower_indirect_derefs(sel->nir, sel->screen->info.chip_class);
1018
1019 si_nir_opts(sel->nir);
1020
1021 NIR_PASS_V(sel->nir, nir_lower_bool_to_int32);
1022
1023 /* Strip the resulting shader so that the shader cache is more likely
1024 * to hit from other similar shaders.
1025 */
1026 nir_strip(sel->nir);
1027 }
1028
1029 static void declare_nir_input_vs(struct si_shader_context *ctx,
1030 struct nir_variable *variable,
1031 unsigned input_index,
1032 LLVMValueRef out[4])
1033 {
1034 si_llvm_load_input_vs(ctx, input_index, out);
1035 }
1036
1037 LLVMValueRef
1038 si_nir_lookup_interp_param(struct ac_shader_abi *abi,
1039 enum glsl_interp_mode interp, unsigned location)
1040 {
1041 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1042 int interp_param_idx = -1;
1043
1044 switch (interp) {
1045 case INTERP_MODE_FLAT:
1046 return NULL;
1047 case INTERP_MODE_SMOOTH:
1048 case INTERP_MODE_NONE:
1049 if (location == INTERP_CENTER)
1050 interp_param_idx = SI_PARAM_PERSP_CENTER;
1051 else if (location == INTERP_CENTROID)
1052 interp_param_idx = SI_PARAM_PERSP_CENTROID;
1053 else if (location == INTERP_SAMPLE)
1054 interp_param_idx = SI_PARAM_PERSP_SAMPLE;
1055 break;
1056 case INTERP_MODE_NOPERSPECTIVE:
1057 if (location == INTERP_CENTER)
1058 interp_param_idx = SI_PARAM_LINEAR_CENTER;
1059 else if (location == INTERP_CENTROID)
1060 interp_param_idx = SI_PARAM_LINEAR_CENTROID;
1061 else if (location == INTERP_SAMPLE)
1062 interp_param_idx = SI_PARAM_LINEAR_SAMPLE;
1063 break;
1064 default:
1065 assert(!"Unhandled interpolation mode.");
1066 return NULL;
1067 }
1068
1069 return interp_param_idx != -1 ?
1070 LLVMGetParam(ctx->main_fn, interp_param_idx) : NULL;
1071 }
1072
1073 static LLVMValueRef
1074 si_nir_load_sampler_desc(struct ac_shader_abi *abi,
1075 unsigned descriptor_set, unsigned base_index,
1076 unsigned constant_index, LLVMValueRef dynamic_index,
1077 enum ac_descriptor_type desc_type, bool image,
1078 bool write, bool bindless)
1079 {
1080 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1081 LLVMBuilderRef builder = ctx->ac.builder;
1082 unsigned const_index = base_index + constant_index;
1083
1084 assert(!descriptor_set);
1085 assert(!image || desc_type == AC_DESC_IMAGE || desc_type == AC_DESC_BUFFER);
1086
1087 if (bindless) {
1088 LLVMValueRef list =
1089 LLVMGetParam(ctx->main_fn, ctx->param_bindless_samplers_and_images);
1090
1091 /* dynamic_index is the bindless handle */
1092 if (image) {
1093 /* For simplicity, bindless image descriptors use fixed
1094 * 16-dword slots for now.
1095 */
1096 dynamic_index = LLVMBuildMul(ctx->ac.builder, dynamic_index,
1097 LLVMConstInt(ctx->i64, 2, 0), "");
1098
1099 return si_load_image_desc(ctx, list, dynamic_index, desc_type,
1100 write, true);
1101 }
1102
1103 /* Since bindless handle arithmetic can contain an unsigned integer
1104 * wraparound and si_load_sampler_desc assumes there isn't any,
1105 * use GEP without "inbounds" (inside ac_build_pointer_add)
1106 * to prevent incorrect code generation and hangs.
1107 */
1108 dynamic_index = LLVMBuildMul(ctx->ac.builder, dynamic_index,
1109 LLVMConstInt(ctx->i64, 2, 0), "");
1110 list = ac_build_pointer_add(&ctx->ac, list, dynamic_index);
1111 return si_load_sampler_desc(ctx, list, ctx->i32_0, desc_type);
1112 }
1113
1114 unsigned num_slots = image ? ctx->num_images : ctx->num_samplers;
1115 assert(const_index < num_slots || dynamic_index);
1116
1117 LLVMValueRef list = LLVMGetParam(ctx->main_fn, ctx->param_samplers_and_images);
1118 LLVMValueRef index = LLVMConstInt(ctx->ac.i32, const_index, false);
1119
1120 if (dynamic_index) {
1121 index = LLVMBuildAdd(builder, index, dynamic_index, "");
1122
1123 /* From the GL_ARB_shader_image_load_store extension spec:
1124 *
1125 * If a shader performs an image load, store, or atomic
1126 * operation using an image variable declared as an array,
1127 * and if the index used to select an individual element is
1128 * negative or greater than or equal to the size of the
1129 * array, the results of the operation are undefined but may
1130 * not lead to termination.
1131 */
1132 index = si_llvm_bound_index(ctx, index, num_slots);
1133 }
1134
1135 if (image) {
1136 index = LLVMBuildSub(ctx->ac.builder,
1137 LLVMConstInt(ctx->i32, SI_NUM_IMAGES - 1, 0),
1138 index, "");
1139 return si_load_image_desc(ctx, list, index, desc_type, write, false);
1140 }
1141
1142 index = LLVMBuildAdd(ctx->ac.builder, index,
1143 LLVMConstInt(ctx->i32, SI_NUM_IMAGES / 2, 0), "");
1144 return si_load_sampler_desc(ctx, list, index, desc_type);
1145 }
1146
1147 static void bitcast_inputs(struct si_shader_context *ctx,
1148 LLVMValueRef data[4],
1149 unsigned input_idx)
1150 {
1151 for (unsigned chan = 0; chan < 4; chan++) {
1152 ctx->inputs[input_idx + chan] =
1153 LLVMBuildBitCast(ctx->ac.builder, data[chan], ctx->ac.i32, "");
1154 }
1155 }
1156
1157 bool si_nir_build_llvm(struct si_shader_context *ctx, struct nir_shader *nir)
1158 {
1159 struct tgsi_shader_info *info = &ctx->shader->selector->info;
1160
1161 if (nir->info.stage == MESA_SHADER_VERTEX) {
1162 uint64_t processed_inputs = 0;
1163 nir_foreach_variable(variable, &nir->inputs) {
1164 unsigned attrib_count = glsl_count_attribute_slots(variable->type,
1165 true);
1166 unsigned input_idx = variable->data.driver_location;
1167
1168 LLVMValueRef data[4];
1169 unsigned loc = variable->data.location;
1170
1171 for (unsigned i = 0; i < attrib_count; i++) {
1172 /* Packed components share the same location so skip
1173 * them if we have already processed the location.
1174 */
1175 if (processed_inputs & ((uint64_t)1 << (loc + i))) {
1176 input_idx += 4;
1177 continue;
1178 }
1179
1180 declare_nir_input_vs(ctx, variable, input_idx / 4, data);
1181 bitcast_inputs(ctx, data, input_idx);
1182 if (glsl_type_is_dual_slot(variable->type)) {
1183 input_idx += 4;
1184 declare_nir_input_vs(ctx, variable, input_idx / 4, data);
1185 bitcast_inputs(ctx, data, input_idx);
1186 }
1187
1188 processed_inputs |= ((uint64_t)1 << (loc + i));
1189 input_idx += 4;
1190 }
1191 }
1192 } else if (nir->info.stage == MESA_SHADER_FRAGMENT) {
1193 unsigned colors_read =
1194 ctx->shader->selector->info.colors_read;
1195 LLVMValueRef main_fn = ctx->main_fn;
1196
1197 LLVMValueRef undef = LLVMGetUndef(ctx->f32);
1198
1199 unsigned offset = SI_PARAM_POS_FIXED_PT + 1;
1200
1201 if (colors_read & 0x0f) {
1202 unsigned mask = colors_read & 0x0f;
1203 LLVMValueRef values[4];
1204 values[0] = mask & 0x1 ? LLVMGetParam(main_fn, offset++) : undef;
1205 values[1] = mask & 0x2 ? LLVMGetParam(main_fn, offset++) : undef;
1206 values[2] = mask & 0x4 ? LLVMGetParam(main_fn, offset++) : undef;
1207 values[3] = mask & 0x8 ? LLVMGetParam(main_fn, offset++) : undef;
1208 ctx->abi.color0 =
1209 ac_to_integer(&ctx->ac,
1210 ac_build_gather_values(&ctx->ac, values, 4));
1211 }
1212 if (colors_read & 0xf0) {
1213 unsigned mask = (colors_read & 0xf0) >> 4;
1214 LLVMValueRef values[4];
1215 values[0] = mask & 0x1 ? LLVMGetParam(main_fn, offset++) : undef;
1216 values[1] = mask & 0x2 ? LLVMGetParam(main_fn, offset++) : undef;
1217 values[2] = mask & 0x4 ? LLVMGetParam(main_fn, offset++) : undef;
1218 values[3] = mask & 0x8 ? LLVMGetParam(main_fn, offset++) : undef;
1219 ctx->abi.color1 =
1220 ac_to_integer(&ctx->ac,
1221 ac_build_gather_values(&ctx->ac, values, 4));
1222 }
1223
1224 ctx->abi.interp_at_sample_force_center =
1225 ctx->shader->key.mono.u.ps.interpolate_at_sample_force_center;
1226 } else if (nir->info.stage == MESA_SHADER_COMPUTE) {
1227 if (nir->info.cs.user_data_components_amd) {
1228 ctx->abi.user_data = LLVMGetParam(ctx->main_fn, ctx->param_cs_user_data);
1229 ctx->abi.user_data = ac_build_expand_to_vec4(&ctx->ac, ctx->abi.user_data,
1230 nir->info.cs.user_data_components_amd);
1231 }
1232 }
1233
1234 ctx->abi.inputs = &ctx->inputs[0];
1235 ctx->abi.load_sampler_desc = si_nir_load_sampler_desc;
1236 ctx->abi.clamp_shadow_reference = true;
1237 ctx->abi.robust_buffer_access = true;
1238
1239 ctx->num_samplers = util_last_bit(info->samplers_declared);
1240 ctx->num_images = util_last_bit(info->images_declared);
1241
1242 if (ctx->shader->selector->info.properties[TGSI_PROPERTY_CS_LOCAL_SIZE]) {
1243 assert(gl_shader_stage_is_compute(nir->info.stage));
1244 si_declare_compute_memory(ctx);
1245 }
1246 ac_nir_translate(&ctx->ac, &ctx->abi, nir);
1247
1248 return true;
1249 }