radeonsi/nir: perform lowering of input/output driver locations
[mesa.git] / src / gallium / drivers / radeonsi / si_shader_nir.c
1 /*
2 * Copyright 2017 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23
24 #include "si_shader.h"
25 #include "si_shader_internal.h"
26
27 #include "ac_nir_to_llvm.h"
28
29 #include "tgsi/tgsi_from_mesa.h"
30
31 #include "compiler/nir/nir.h"
32 #include "compiler/nir_types.h"
33
34
35 static void scan_instruction(struct tgsi_shader_info *info,
36 nir_instr *instr)
37 {
38 if (instr->type == nir_instr_type_alu) {
39 nir_alu_instr *alu = nir_instr_as_alu(instr);
40
41 switch (alu->op) {
42 case nir_op_fddx:
43 case nir_op_fddy:
44 case nir_op_fddx_fine:
45 case nir_op_fddy_fine:
46 case nir_op_fddx_coarse:
47 case nir_op_fddy_coarse:
48 info->uses_derivatives = true;
49 break;
50 default:
51 break;
52 }
53 } else if (instr->type == nir_instr_type_tex) {
54 nir_tex_instr *tex = nir_instr_as_tex(instr);
55
56 switch (tex->op) {
57 case nir_texop_tex:
58 case nir_texop_txb:
59 case nir_texop_lod:
60 info->uses_derivatives = true;
61 break;
62 default:
63 break;
64 }
65 } else if (instr->type == nir_instr_type_intrinsic) {
66 nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);
67
68 switch (intr->intrinsic) {
69 case nir_intrinsic_load_front_face:
70 info->uses_frontface = 1;
71 break;
72 case nir_intrinsic_load_instance_id:
73 info->uses_instanceid = 1;
74 break;
75 case nir_intrinsic_load_vertex_id:
76 info->uses_vertexid = 1;
77 break;
78 case nir_intrinsic_load_vertex_id_zero_base:
79 info->uses_vertexid_nobase = 1;
80 break;
81 case nir_intrinsic_load_base_vertex:
82 info->uses_basevertex = 1;
83 break;
84 case nir_intrinsic_load_primitive_id:
85 info->uses_primid = 1;
86 break;
87 case nir_intrinsic_image_store:
88 case nir_intrinsic_image_atomic_add:
89 case nir_intrinsic_image_atomic_min:
90 case nir_intrinsic_image_atomic_max:
91 case nir_intrinsic_image_atomic_and:
92 case nir_intrinsic_image_atomic_or:
93 case nir_intrinsic_image_atomic_xor:
94 case nir_intrinsic_image_atomic_exchange:
95 case nir_intrinsic_image_atomic_comp_swap:
96 case nir_intrinsic_store_ssbo:
97 case nir_intrinsic_ssbo_atomic_add:
98 case nir_intrinsic_ssbo_atomic_imin:
99 case nir_intrinsic_ssbo_atomic_umin:
100 case nir_intrinsic_ssbo_atomic_imax:
101 case nir_intrinsic_ssbo_atomic_umax:
102 case nir_intrinsic_ssbo_atomic_and:
103 case nir_intrinsic_ssbo_atomic_or:
104 case nir_intrinsic_ssbo_atomic_xor:
105 case nir_intrinsic_ssbo_atomic_exchange:
106 case nir_intrinsic_ssbo_atomic_comp_swap:
107 info->writes_memory = true;
108 break;
109 default:
110 break;
111 }
112 }
113 }
114
115 void si_nir_scan_shader(const struct nir_shader *nir,
116 struct tgsi_shader_info *info)
117 {
118 nir_function *func;
119 unsigned i;
120
121 assert(nir->stage == MESA_SHADER_VERTEX ||
122 nir->stage == MESA_SHADER_FRAGMENT);
123
124 info->processor = pipe_shader_type_from_mesa(nir->stage);
125 info->num_tokens = 2; /* indicate that the shader is non-empty */
126 info->num_instructions = 2;
127
128 info->num_inputs = nir->num_inputs;
129 info->num_outputs = nir->num_outputs;
130
131 i = 0;
132 nir_foreach_variable(variable, &nir->inputs) {
133 unsigned semantic_name, semantic_index;
134 unsigned attrib_count = glsl_count_attribute_slots(variable->type,
135 nir->stage == MESA_SHADER_VERTEX);
136
137 assert(attrib_count == 1 && "not implemented");
138
139 /* Vertex shader inputs don't have semantics. The state
140 * tracker has already mapped them to attributes via
141 * variable->data.driver_location.
142 */
143 if (nir->stage == MESA_SHADER_VERTEX)
144 continue;
145
146 /* Fragment shader position is a system value. */
147 if (nir->stage == MESA_SHADER_FRAGMENT &&
148 variable->data.location == VARYING_SLOT_POS) {
149 if (variable->data.pixel_center_integer)
150 info->properties[TGSI_PROPERTY_FS_COORD_PIXEL_CENTER] =
151 TGSI_FS_COORD_PIXEL_CENTER_INTEGER;
152 continue;
153 }
154
155 tgsi_get_gl_varying_semantic(variable->data.location, true,
156 &semantic_name, &semantic_index);
157
158 info->input_semantic_name[i] = semantic_name;
159 info->input_semantic_index[i] = semantic_index;
160
161 if (variable->data.sample)
162 info->input_interpolate_loc[i] = TGSI_INTERPOLATE_LOC_SAMPLE;
163 else if (variable->data.centroid)
164 info->input_interpolate_loc[i] = TGSI_INTERPOLATE_LOC_CENTROID;
165 else
166 info->input_interpolate_loc[i] = TGSI_INTERPOLATE_LOC_CENTER;
167
168 enum glsl_base_type base_type =
169 glsl_get_base_type(glsl_without_array(variable->type));
170
171 switch (variable->data.interpolation) {
172 case INTERP_MODE_NONE:
173 if (glsl_base_type_is_integer(base_type)) {
174 info->input_interpolate[i] = TGSI_INTERPOLATE_CONSTANT;
175 break;
176 }
177
178 if (semantic_name == TGSI_SEMANTIC_COLOR) {
179 info->input_interpolate[i] = TGSI_INTERPOLATE_COLOR;
180 goto persp_locations;
181 }
182 /* fall-through */
183 case INTERP_MODE_SMOOTH:
184 assert(!glsl_base_type_is_integer(base_type));
185
186 info->input_interpolate[i] = TGSI_INTERPOLATE_PERSPECTIVE;
187
188 persp_locations:
189 if (variable->data.sample)
190 info->uses_persp_sample = true;
191 else if (variable->data.centroid)
192 info->uses_persp_centroid = true;
193 else
194 info->uses_persp_center = true;
195 break;
196
197 case INTERP_MODE_NOPERSPECTIVE:
198 assert(!glsl_base_type_is_integer(base_type));
199
200 info->input_interpolate[i] = TGSI_INTERPOLATE_LINEAR;
201
202 if (variable->data.sample)
203 info->uses_linear_sample = true;
204 else if (variable->data.centroid)
205 info->uses_linear_centroid = true;
206 else
207 info->uses_linear_center = true;
208 break;
209
210 case INTERP_MODE_FLAT:
211 info->input_interpolate[i] = TGSI_INTERPOLATE_CONSTANT;
212 break;
213 }
214
215 /* TODO make this more precise */
216 if (variable->data.location == VARYING_SLOT_COL0)
217 info->colors_read |= 0x0f;
218 else if (variable->data.location == VARYING_SLOT_COL1)
219 info->colors_read |= 0xf0;
220
221 i++;
222 }
223
224 i = 0;
225 nir_foreach_variable(variable, &nir->outputs) {
226 unsigned semantic_name, semantic_index;
227
228 if (nir->stage == MESA_SHADER_FRAGMENT) {
229 tgsi_get_gl_frag_result_semantic(variable->data.location,
230 &semantic_name, &semantic_index);
231 } else {
232 tgsi_get_gl_varying_semantic(variable->data.location, true,
233 &semantic_name, &semantic_index);
234 }
235
236 info->output_semantic_name[i] = semantic_name;
237 info->output_semantic_index[i] = semantic_index;
238 info->output_usagemask[i] = TGSI_WRITEMASK_XYZW;
239
240 switch (semantic_name) {
241 case TGSI_SEMANTIC_PRIMID:
242 info->writes_primid = true;
243 break;
244 case TGSI_SEMANTIC_VIEWPORT_INDEX:
245 info->writes_viewport_index = true;
246 break;
247 case TGSI_SEMANTIC_LAYER:
248 info->writes_layer = true;
249 break;
250 case TGSI_SEMANTIC_PSIZE:
251 info->writes_psize = true;
252 break;
253 case TGSI_SEMANTIC_CLIPVERTEX:
254 info->writes_clipvertex = true;
255 break;
256 case TGSI_SEMANTIC_COLOR:
257 info->colors_written |= 1 << semantic_index;
258 break;
259 case TGSI_SEMANTIC_STENCIL:
260 info->writes_stencil = true;
261 break;
262 case TGSI_SEMANTIC_SAMPLEMASK:
263 info->writes_samplemask = true;
264 break;
265 case TGSI_SEMANTIC_EDGEFLAG:
266 info->writes_edgeflag = true;
267 break;
268 case TGSI_SEMANTIC_POSITION:
269 if (info->processor == PIPE_SHADER_FRAGMENT)
270 info->writes_z = true;
271 else
272 info->writes_position = true;
273 break;
274 }
275
276 i++;
277 }
278
279 nir_foreach_variable(variable, &nir->uniforms) {
280 const struct glsl_type *type = variable->type;
281 enum glsl_base_type base_type =
282 glsl_get_base_type(glsl_without_array(type));
283 unsigned aoa_size = MAX2(1, glsl_get_aoa_size(type));
284
285 /* We rely on the fact that nir_lower_samplers_as_deref has
286 * eliminated struct dereferences.
287 */
288 if (base_type == GLSL_TYPE_SAMPLER)
289 info->samplers_declared |=
290 u_bit_consecutive(variable->data.binding, aoa_size);
291 else if (base_type == GLSL_TYPE_IMAGE)
292 info->images_declared |=
293 u_bit_consecutive(variable->data.binding, aoa_size);
294 }
295
296 info->num_written_clipdistance = nir->info.clip_distance_array_size;
297 info->num_written_culldistance = nir->info.cull_distance_array_size;
298 info->clipdist_writemask = u_bit_consecutive(0, info->num_written_clipdistance);
299 info->culldist_writemask = u_bit_consecutive(info->num_written_clipdistance,
300 info->num_written_culldistance);
301
302 if (info->processor == PIPE_SHADER_FRAGMENT)
303 info->uses_kill = nir->info.fs.uses_discard;
304
305 /* TODO make this more accurate */
306 info->const_buffers_declared = u_bit_consecutive(0, SI_NUM_CONST_BUFFERS);
307 info->shader_buffers_declared = u_bit_consecutive(0, SI_NUM_SHADER_BUFFERS);
308
309 func = (struct nir_function *)exec_list_get_head_const(&nir->functions);
310 nir_foreach_block(block, func->impl) {
311 nir_foreach_instr(instr, block)
312 scan_instruction(info, instr);
313 }
314 }
315
316 /**
317 * Perform "lowering" operations on the NIR that are run once when the shader
318 * selector is created.
319 */
320 void
321 si_lower_nir(struct si_shader_selector* sel)
322 {
323 /* Adjust the driver location of inputs and outputs. The state tracker
324 * interprets them as slots, while the ac/nir backend interprets them
325 * as individual components.
326 */
327 nir_foreach_variable(variable, &sel->nir->inputs)
328 variable->data.driver_location *= 4;
329
330 nir_foreach_variable(variable, &sel->nir->outputs) {
331 variable->data.driver_location *= 4;
332
333 if (sel->nir->stage == MESA_SHADER_FRAGMENT) {
334 if (variable->data.location == FRAG_RESULT_DEPTH)
335 variable->data.driver_location += 2;
336 else if (variable->data.location == FRAG_RESULT_STENCIL)
337 variable->data.driver_location += 1;
338 }
339 }
340 }
341
342 static void declare_nir_input_vs(struct si_shader_context *ctx,
343 struct nir_variable *variable, unsigned rel,
344 LLVMValueRef out[4])
345 {
346 si_llvm_load_input_vs(ctx, variable->data.driver_location / 4 + rel, out);
347 }
348
349 static void declare_nir_input_fs(struct si_shader_context *ctx,
350 struct nir_variable *variable, unsigned rel,
351 unsigned *fs_attr_idx,
352 LLVMValueRef out[4])
353 {
354 unsigned slot = variable->data.location + rel;
355
356 assert(variable->data.location >= VARYING_SLOT_VAR0 || rel == 0);
357
358 if (slot == VARYING_SLOT_POS) {
359 out[0] = LLVMGetParam(ctx->main_fn, SI_PARAM_POS_X_FLOAT);
360 out[1] = LLVMGetParam(ctx->main_fn, SI_PARAM_POS_Y_FLOAT);
361 out[2] = LLVMGetParam(ctx->main_fn, SI_PARAM_POS_Z_FLOAT);
362 out[3] = ac_build_fdiv(&ctx->ac, ctx->ac.f32_1,
363 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_W_FLOAT));
364 return;
365 }
366
367 si_llvm_load_input_fs(ctx, *fs_attr_idx, out);
368 (*fs_attr_idx)++;
369 }
370
371 static LLVMValueRef
372 si_nir_load_sampler_desc(struct ac_shader_abi *abi,
373 unsigned descriptor_set, unsigned base_index,
374 unsigned constant_index, LLVMValueRef dynamic_index,
375 enum ac_descriptor_type desc_type, bool image,
376 bool write)
377 {
378 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
379 LLVMBuilderRef builder = ctx->ac.builder;
380 LLVMValueRef list = LLVMGetParam(ctx->main_fn, ctx->param_samplers_and_images);
381 LLVMValueRef index = dynamic_index;
382
383 assert(!descriptor_set);
384
385 if (!index)
386 index = ctx->ac.i32_0;
387
388 index = LLVMBuildAdd(builder, index,
389 LLVMConstInt(ctx->ac.i32, base_index + constant_index, false),
390 "");
391
392 if (image) {
393 assert(desc_type == AC_DESC_IMAGE || desc_type == AC_DESC_BUFFER);
394 assert(base_index + constant_index < ctx->num_images);
395
396 if (dynamic_index)
397 index = si_llvm_bound_index(ctx, index, ctx->num_images);
398
399 index = LLVMBuildSub(ctx->gallivm.builder,
400 LLVMConstInt(ctx->i32, SI_NUM_IMAGES - 1, 0),
401 index, "");
402
403 /* TODO: be smarter about when we use dcc_off */
404 return si_load_image_desc(ctx, list, index, desc_type, write);
405 }
406
407 assert(base_index + constant_index < ctx->num_samplers);
408
409 if (dynamic_index)
410 index = si_llvm_bound_index(ctx, index, ctx->num_samplers);
411
412 index = LLVMBuildAdd(ctx->gallivm.builder, index,
413 LLVMConstInt(ctx->i32, SI_NUM_IMAGES / 2, 0), "");
414
415 return si_load_sampler_desc(ctx, list, index, desc_type);
416 }
417
418 bool si_nir_build_llvm(struct si_shader_context *ctx, struct nir_shader *nir)
419 {
420 struct tgsi_shader_info *info = &ctx->shader->selector->info;
421
422 unsigned fs_attr_idx = 0;
423 nir_foreach_variable(variable, &nir->inputs) {
424 unsigned attrib_count = glsl_count_attribute_slots(variable->type,
425 nir->stage == MESA_SHADER_VERTEX);
426 unsigned input_idx = variable->data.driver_location;
427
428 for (unsigned i = 0; i < attrib_count; ++i) {
429 LLVMValueRef data[4];
430
431 if (nir->stage == MESA_SHADER_VERTEX)
432 declare_nir_input_vs(ctx, variable, i, data);
433 else if (nir->stage == MESA_SHADER_FRAGMENT)
434 declare_nir_input_fs(ctx, variable, i, &fs_attr_idx, data);
435
436 for (unsigned chan = 0; chan < 4; chan++) {
437 ctx->inputs[input_idx + chan] =
438 LLVMBuildBitCast(ctx->ac.builder, data[chan], ctx->ac.i32, "");
439 }
440 }
441 }
442
443 ctx->abi.inputs = &ctx->inputs[0];
444 ctx->abi.load_sampler_desc = si_nir_load_sampler_desc;
445
446 ctx->num_samplers = util_last_bit(info->samplers_declared);
447 ctx->num_images = util_last_bit(info->images_declared);
448
449 ac_nir_translate(&ctx->ac, &ctx->abi, nir, NULL);
450
451 return true;
452 }