src/gallium/drivers/radeonsi/si_shader_nir.c

   1 /*
   2  * Copyright 2017 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 #include "si_shader.h"
  25 #include "si_shader_internal.h"
  26
  27 #include "ac_nir_to_llvm.h"
  28
  29 #include "tgsi/tgsi_from_mesa.h"
  30
  31 #include "compiler/nir/nir.h"
  32 #include "compiler/nir_types.h"
  33
  34
  35 static int
  36 type_size(const struct glsl_type *type)
  37 {
  38    return glsl_count_attribute_slots(type, false);
  39 }
  40
  41 static void scan_instruction(struct tgsi_shader_info *info,
  42                              nir_instr *instr)
  43 {
  44         if (instr->type == nir_instr_type_alu) {
  45                 nir_alu_instr *alu = nir_instr_as_alu(instr);
  46
  47                 switch (alu->op) {
  48                 case nir_op_fddx:
  49                 case nir_op_fddy:
  50                 case nir_op_fddx_fine:
  51                 case nir_op_fddy_fine:
  52                 case nir_op_fddx_coarse:
  53                 case nir_op_fddy_coarse:
  54                         info->uses_derivatives = true;
  55                         break;
  56                 default:
  57                         break;
  58                 }
  59         } else if (instr->type == nir_instr_type_tex) {
  60                 nir_tex_instr *tex = nir_instr_as_tex(instr);
  61
  62                 if (!tex->texture) {
  63                         info->samplers_declared |=
  64                                 u_bit_consecutive(tex->sampler_index, 1);
  65                 }
  66
  67                 switch (tex->op) {
  68                 case nir_texop_tex:
  69                 case nir_texop_txb:
  70                 case nir_texop_lod:
  71                         info->uses_derivatives = true;
  72                         break;
  73                 default:
  74                         break;
  75                 }
  76         } else if (instr->type == nir_instr_type_intrinsic) {
  77                 nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);
  78
  79                 switch (intr->intrinsic) {
  80                 case nir_intrinsic_load_front_face:
  81                         info->uses_frontface = 1;
  82                         break;
  83                 case nir_intrinsic_load_instance_id:
  84                         info->uses_instanceid = 1;
  85                         break;
  86                 case nir_intrinsic_load_invocation_id:
  87                         info->uses_invocationid = true;
  88                         break;
  89                 case nir_intrinsic_load_vertex_id:
  90                         info->uses_vertexid = 1;
  91                         break;
  92                 case nir_intrinsic_load_vertex_id_zero_base:
  93                         info->uses_vertexid_nobase = 1;
  94                         break;
  95                 case nir_intrinsic_load_base_vertex:
  96                         info->uses_basevertex = 1;
  97                         break;
  98                 case nir_intrinsic_load_primitive_id:
  99                         info->uses_primid = 1;
 100                         break;
 101                 case nir_intrinsic_load_sample_mask_in:
 102                         info->reads_samplemask = true;
 103                         break;
 104                 case nir_intrinsic_load_tess_level_inner:
 105                 case nir_intrinsic_load_tess_level_outer:
 106                         info->reads_tess_factors = true;
 107                         break;
 108                 case nir_intrinsic_image_store:
 109                 case nir_intrinsic_image_atomic_add:
 110                 case nir_intrinsic_image_atomic_min:
 111                 case nir_intrinsic_image_atomic_max:
 112                 case nir_intrinsic_image_atomic_and:
 113                 case nir_intrinsic_image_atomic_or:
 114                 case nir_intrinsic_image_atomic_xor:
 115                 case nir_intrinsic_image_atomic_exchange:
 116                 case nir_intrinsic_image_atomic_comp_swap:
 117                 case nir_intrinsic_store_ssbo:
 118                 case nir_intrinsic_ssbo_atomic_add:
 119                 case nir_intrinsic_ssbo_atomic_imin:
 120                 case nir_intrinsic_ssbo_atomic_umin:
 121                 case nir_intrinsic_ssbo_atomic_imax:
 122                 case nir_intrinsic_ssbo_atomic_umax:
 123                 case nir_intrinsic_ssbo_atomic_and:
 124                 case nir_intrinsic_ssbo_atomic_or:
 125                 case nir_intrinsic_ssbo_atomic_xor:
 126                 case nir_intrinsic_ssbo_atomic_exchange:
 127                 case nir_intrinsic_ssbo_atomic_comp_swap:
 128                         info->writes_memory = true;
 129                         break;
 130                 default:
 131                         break;
 132                 }
 133         }
 134 }
 135
 136 void si_nir_scan_tess_ctrl(const struct nir_shader *nir,
 137                            const struct tgsi_shader_info *info,
 138                            struct tgsi_tessctrl_info *out)
 139 {
 140         memset(out, 0, sizeof(*out));
 141
 142         if (nir->info.stage != MESA_SHADER_TESS_CTRL)
 143                 return;
 144
 145         /* Initial value = true. Here the pass will accumulate results from
 146          * multiple segments surrounded by barriers. If tess factors aren't
 147          * written at all, it's a shader bug and we don't care if this will be
 148          * true.
 149          */
 150         out->tessfactors_are_def_in_all_invocs = true;
 151
 152         /* TODO: Implement scanning of tess factors, see tgsi backend. */
 153 }
 154
 155 void si_nir_scan_shader(const struct nir_shader *nir,
 156                         struct tgsi_shader_info *info)
 157 {
 158         nir_function *func;
 159         unsigned i;
 160
 161         assert(nir->info.stage == MESA_SHADER_VERTEX ||
 162                nir->info.stage == MESA_SHADER_GEOMETRY ||
 163                nir->info.stage == MESA_SHADER_TESS_CTRL ||
 164                nir->info.stage == MESA_SHADER_TESS_EVAL ||
 165                nir->info.stage == MESA_SHADER_FRAGMENT);
 166
 167         info->processor = pipe_shader_type_from_mesa(nir->info.stage);
 168         info->num_tokens = 2; /* indicate that the shader is non-empty */
 169         info->num_instructions = 2;
 170
 171         if (nir->info.stage == MESA_SHADER_TESS_CTRL) {
 172                 info->properties[TGSI_PROPERTY_TCS_VERTICES_OUT] =
 173                         nir->info.tess.tcs_vertices_out;
 174         }
 175
 176         if (nir->info.stage == MESA_SHADER_TESS_EVAL) {
 177                 if (nir->info.tess.primitive_mode == GL_ISOLINES)
 178                         info->properties[TGSI_PROPERTY_TES_PRIM_MODE] = PIPE_PRIM_LINES;
 179                 else
 180                         info->properties[TGSI_PROPERTY_TES_PRIM_MODE] = nir->info.tess.primitive_mode;
 181
 182                 STATIC_ASSERT((TESS_SPACING_EQUAL + 1) % 3 == PIPE_TESS_SPACING_EQUAL);
 183                 STATIC_ASSERT((TESS_SPACING_FRACTIONAL_ODD + 1) % 3 ==
 184                               PIPE_TESS_SPACING_FRACTIONAL_ODD);
 185                 STATIC_ASSERT((TESS_SPACING_FRACTIONAL_EVEN + 1) % 3 ==
 186                               PIPE_TESS_SPACING_FRACTIONAL_EVEN);
 187
 188                 info->properties[TGSI_PROPERTY_TES_SPACING] = (nir->info.tess.spacing + 1) % 3;
 189                 info->properties[TGSI_PROPERTY_TES_VERTEX_ORDER_CW] = !nir->info.tess.ccw;
 190                 info->properties[TGSI_PROPERTY_TES_POINT_MODE] = nir->info.tess.point_mode;
 191         }
 192
 193         if (nir->info.stage == MESA_SHADER_GEOMETRY) {
 194                 info->properties[TGSI_PROPERTY_GS_INPUT_PRIM] = nir->info.gs.input_primitive;
 195                 info->properties[TGSI_PROPERTY_GS_OUTPUT_PRIM] = nir->info.gs.output_primitive;
 196                 info->properties[TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES] = nir->info.gs.vertices_out;
 197                 info->properties[TGSI_PROPERTY_GS_INVOCATIONS] = nir->info.gs.invocations;
 198         }
 199
 200         i = 0;
 201         uint64_t processed_inputs = 0;
 202         unsigned num_inputs = 0;
 203         nir_foreach_variable(variable, &nir->inputs) {
 204                 unsigned semantic_name, semantic_index;
 205                 unsigned attrib_count = glsl_count_attribute_slots(variable->type,
 206                                                                    nir->info.stage == MESA_SHADER_VERTEX);
 207
 208                 /* Vertex shader inputs don't have semantics. The state
 209                  * tracker has already mapped them to attributes via
 210                  * variable->data.driver_location.
 211                  */
 212                 if (nir->info.stage == MESA_SHADER_VERTEX)
 213                         continue;
 214
 215                 assert(nir->info.stage != MESA_SHADER_FRAGMENT ||
 216                        (attrib_count == 1 && "not implemented"));
 217
 218                 /* Fragment shader position is a system value. */
 219                 if (nir->info.stage == MESA_SHADER_FRAGMENT &&
 220                     variable->data.location == VARYING_SLOT_POS) {
 221                         if (variable->data.pixel_center_integer)
 222                                 info->properties[TGSI_PROPERTY_FS_COORD_PIXEL_CENTER] =
 223                                         TGSI_FS_COORD_PIXEL_CENTER_INTEGER;
 224
 225                         num_inputs++;
 226                         continue;
 227                 }
 228
 229                 i = variable->data.driver_location;
 230                 if (processed_inputs & ((uint64_t)1 << i))
 231                         continue;
 232
 233                 processed_inputs |= ((uint64_t)1 << i);
 234                 num_inputs++;
 235
 236                 tgsi_get_gl_varying_semantic(variable->data.location, true,
 237                                              &semantic_name, &semantic_index);
 238
 239                 info->input_semantic_name[i] = semantic_name;
 240                 info->input_semantic_index[i] = semantic_index;
 241
 242                 if (variable->data.sample)
 243                         info->input_interpolate_loc[i] = TGSI_INTERPOLATE_LOC_SAMPLE;
 244                 else if (variable->data.centroid)
 245                         info->input_interpolate_loc[i] = TGSI_INTERPOLATE_LOC_CENTROID;
 246                 else
 247                         info->input_interpolate_loc[i] = TGSI_INTERPOLATE_LOC_CENTER;
 248
 249                 enum glsl_base_type base_type =
 250                         glsl_get_base_type(glsl_without_array(variable->type));
 251
 252                 switch (variable->data.interpolation) {
 253                 case INTERP_MODE_NONE:
 254                         if (glsl_base_type_is_integer(base_type)) {
 255                                 info->input_interpolate[i] = TGSI_INTERPOLATE_CONSTANT;
 256                                 break;
 257                         }
 258
 259                         if (semantic_name == TGSI_SEMANTIC_COLOR) {
 260                                 info->input_interpolate[i] = TGSI_INTERPOLATE_COLOR;
 261                                 goto persp_locations;
 262                         }
 263                         /* fall-through */
 264                 case INTERP_MODE_SMOOTH:
 265                         assert(!glsl_base_type_is_integer(base_type));
 266
 267                         info->input_interpolate[i] = TGSI_INTERPOLATE_PERSPECTIVE;
 268
 269                 persp_locations:
 270                         if (variable->data.sample)
 271                                 info->uses_persp_sample = true;
 272                         else if (variable->data.centroid)
 273                                 info->uses_persp_centroid = true;
 274                         else
 275                                 info->uses_persp_center = true;
 276                         break;
 277
 278                 case INTERP_MODE_NOPERSPECTIVE:
 279                         assert(!glsl_base_type_is_integer(base_type));
 280
 281                         info->input_interpolate[i] = TGSI_INTERPOLATE_LINEAR;
 282
 283                         if (variable->data.sample)
 284                                 info->uses_linear_sample = true;
 285                         else if (variable->data.centroid)
 286                                 info->uses_linear_centroid = true;
 287                         else
 288                                 info->uses_linear_center = true;
 289                         break;
 290
 291                 case INTERP_MODE_FLAT:
 292                         info->input_interpolate[i] = TGSI_INTERPOLATE_CONSTANT;
 293                         break;
 294                 }
 295
 296                 /* TODO make this more precise */
 297                 if (variable->data.location == VARYING_SLOT_COL0)
 298                         info->colors_read |= 0x0f;
 299                 else if (variable->data.location == VARYING_SLOT_COL1)
 300                         info->colors_read |= 0xf0;
 301         }
 302
 303         if (nir->info.stage != MESA_SHADER_VERTEX)
 304                 info->num_inputs = num_inputs;
 305         else
 306                 info->num_inputs = nir->num_inputs;
 307
 308         i = 0;
 309         uint64_t processed_outputs = 0;
 310         unsigned num_outputs = 0;
 311         nir_foreach_variable(variable, &nir->outputs) {
 312                 unsigned semantic_name, semantic_index;
 313
 314                 if (nir->info.stage == MESA_SHADER_FRAGMENT) {
 315                         tgsi_get_gl_frag_result_semantic(variable->data.location,
 316                                 &semantic_name, &semantic_index);
 317                 } else {
 318                         tgsi_get_gl_varying_semantic(variable->data.location, true,
 319                                                      &semantic_name, &semantic_index);
 320                 }
 321
 322                 i = variable->data.driver_location;
 323                 if (processed_outputs & ((uint64_t)1 << i))
 324                         continue;
 325
 326                 processed_outputs |= ((uint64_t)1 << i);
 327                 num_outputs++;
 328
 329                 info->output_semantic_name[i] = semantic_name;
 330                 info->output_semantic_index[i] = semantic_index;
 331                 info->output_usagemask[i] = TGSI_WRITEMASK_XYZW;
 332
 333                 unsigned num_components = 4;
 334                 unsigned vector_elements = glsl_get_vector_elements(glsl_without_array(variable->type));
 335                 if (vector_elements)
 336                         num_components = vector_elements;
 337
 338                 unsigned gs_out_streams;
 339                 if (variable->data.stream & (1u << 31)) {
 340                         gs_out_streams = variable->data.stream & ~(1u << 31);
 341                 } else {
 342                         assert(variable->data.stream < 4);
 343                         gs_out_streams = 0;
 344                         for (unsigned j = 0; j < num_components; ++j)
 345                                 gs_out_streams |= variable->data.stream << (2 * (variable->data.location_frac + j));
 346                 }
 347
 348                 unsigned streamx = gs_out_streams & 3;
 349                 unsigned streamy = (gs_out_streams >> 2) & 3;
 350                 unsigned streamz = (gs_out_streams >> 4) & 3;
 351                 unsigned streamw = (gs_out_streams >> 6) & 3;
 352
 353                 if (info->output_usagemask[i] & TGSI_WRITEMASK_X) {
 354                         info->output_streams[i] |= streamx;
 355                         info->num_stream_output_components[streamx]++;
 356                 }
 357                 if (info->output_usagemask[i] & TGSI_WRITEMASK_Y) {
 358                         info->output_streams[i] |= streamy << 2;
 359                         info->num_stream_output_components[streamy]++;
 360                 }
 361                 if (info->output_usagemask[i] & TGSI_WRITEMASK_Z) {
 362                         info->output_streams[i] |= streamz << 4;
 363                         info->num_stream_output_components[streamz]++;
 364                 }
 365                 if (info->output_usagemask[i] & TGSI_WRITEMASK_W) {
 366                         info->output_streams[i] |= streamw << 6;
 367                         info->num_stream_output_components[streamw]++;
 368                 }
 369
 370                 switch (semantic_name) {
 371                 case TGSI_SEMANTIC_PRIMID:
 372                         info->writes_primid = true;
 373                         break;
 374                 case TGSI_SEMANTIC_VIEWPORT_INDEX:
 375                         info->writes_viewport_index = true;
 376                         break;
 377                 case TGSI_SEMANTIC_LAYER:
 378                         info->writes_layer = true;
 379                         break;
 380                 case TGSI_SEMANTIC_PSIZE:
 381                         info->writes_psize = true;
 382                         break;
 383                 case TGSI_SEMANTIC_CLIPVERTEX:
 384                         info->writes_clipvertex = true;
 385                         break;
 386                 case TGSI_SEMANTIC_COLOR:
 387                         info->colors_written |= 1 << semantic_index;
 388                         break;
 389                 case TGSI_SEMANTIC_STENCIL:
 390                         info->writes_stencil = true;
 391                         break;
 392                 case TGSI_SEMANTIC_SAMPLEMASK:
 393                         info->writes_samplemask = true;
 394                         break;
 395                 case TGSI_SEMANTIC_EDGEFLAG:
 396                         info->writes_edgeflag = true;
 397                         break;
 398                 case TGSI_SEMANTIC_POSITION:
 399                         if (info->processor == PIPE_SHADER_FRAGMENT)
 400                                 info->writes_z = true;
 401                         else
 402                                 info->writes_position = true;
 403                         break;
 404                 }
 405
 406                 if (nir->info.stage == MESA_SHADER_TESS_CTRL) {
 407                         switch (semantic_name) {
 408                         case TGSI_SEMANTIC_PATCH:
 409                                 info->reads_perpatch_outputs = true;
 410                         break;
 411                         case TGSI_SEMANTIC_TESSINNER:
 412                         case TGSI_SEMANTIC_TESSOUTER:
 413                                 info->reads_tessfactor_outputs = true;
 414                         break;
 415                         default:
 416                                 info->reads_pervertex_outputs = true;
 417                         }
 418                 }
 419         }
 420
 421         info->num_outputs = num_outputs;
 422
 423         nir_foreach_variable(variable, &nir->uniforms) {
 424                 const struct glsl_type *type = variable->type;
 425                 enum glsl_base_type base_type =
 426                         glsl_get_base_type(glsl_without_array(type));
 427                 unsigned aoa_size = MAX2(1, glsl_get_aoa_size(type));
 428
 429                 /* We rely on the fact that nir_lower_samplers_as_deref has
 430                  * eliminated struct dereferences.
 431                  */
 432                 if (base_type == GLSL_TYPE_SAMPLER)
 433                         info->samplers_declared |=
 434                                 u_bit_consecutive(variable->data.binding, aoa_size);
 435                 else if (base_type == GLSL_TYPE_IMAGE)
 436                         info->images_declared |=
 437                                 u_bit_consecutive(variable->data.binding, aoa_size);
 438         }
 439
 440         info->num_written_clipdistance = nir->info.clip_distance_array_size;
 441         info->num_written_culldistance = nir->info.cull_distance_array_size;
 442         info->clipdist_writemask = u_bit_consecutive(0, info->num_written_clipdistance);
 443         info->culldist_writemask = u_bit_consecutive(0, info->num_written_culldistance);
 444
 445         if (info->processor == PIPE_SHADER_FRAGMENT)
 446                 info->uses_kill = nir->info.fs.uses_discard;
 447
 448         /* TODO make this more accurate */
 449         info->const_buffers_declared = u_bit_consecutive(0, SI_NUM_CONST_BUFFERS);
 450         info->shader_buffers_declared = u_bit_consecutive(0, SI_NUM_SHADER_BUFFERS);
 451
 452         func = (struct nir_function *)exec_list_get_head_const(&nir->functions);
 453         nir_foreach_block(block, func->impl) {
 454                 nir_foreach_instr(instr, block)
 455                         scan_instruction(info, instr);
 456         }
 457 }
 458
 459 /**
 460  * Perform "lowering" operations on the NIR that are run once when the shader
 461  * selector is created.
 462  */
 463 void
 464 si_lower_nir(struct si_shader_selector* sel)
 465 {
 466         /* Adjust the driver location of inputs and outputs. The state tracker
 467          * interprets them as slots, while the ac/nir backend interprets them
 468          * as individual components.
 469          */
 470         nir_foreach_variable(variable, &sel->nir->inputs)
 471                 variable->data.driver_location *= 4;
 472
 473         nir_foreach_variable(variable, &sel->nir->outputs) {
 474                 variable->data.driver_location *= 4;
 475
 476                 if (sel->nir->info.stage == MESA_SHADER_FRAGMENT) {
 477                         if (variable->data.location == FRAG_RESULT_DEPTH)
 478                                 variable->data.driver_location += 2;
 479                         else if (variable->data.location == FRAG_RESULT_STENCIL)
 480                                 variable->data.driver_location += 1;
 481                 }
 482         }
 483
 484         /* Perform lowerings (and optimizations) of code.
 485          *
 486          * Performance considerations aside, we must:
 487          * - lower certain ALU operations
 488          * - ensure constant offsets for texture instructions are folded
 489          *   and copy-propagated
 490          */
 491         NIR_PASS_V(sel->nir, nir_lower_io, nir_var_uniform, type_size,
 492                    (nir_lower_io_options)0);
 493         NIR_PASS_V(sel->nir, nir_lower_uniforms_to_ubo);
 494
 495         NIR_PASS_V(sel->nir, nir_lower_returns);
 496         NIR_PASS_V(sel->nir, nir_lower_vars_to_ssa);
 497         NIR_PASS_V(sel->nir, nir_lower_alu_to_scalar);
 498         NIR_PASS_V(sel->nir, nir_lower_phis_to_scalar);
 499
 500         static const struct nir_lower_tex_options lower_tex_options = {
 501                 .lower_txp = ~0u,
 502         };
 503         NIR_PASS_V(sel->nir, nir_lower_tex, &lower_tex_options);
 504
 505         bool progress;
 506         do {
 507                 progress = false;
 508
 509                 /* (Constant) copy propagation is needed for txf with offsets. */
 510                 NIR_PASS(progress, sel->nir, nir_copy_prop);
 511                 NIR_PASS(progress, sel->nir, nir_opt_remove_phis);
 512                 NIR_PASS(progress, sel->nir, nir_opt_dce);
 513                 if (nir_opt_trivial_continues(sel->nir)) {
 514                         progress = true;
 515                         NIR_PASS(progress, sel->nir, nir_copy_prop);
 516                         NIR_PASS(progress, sel->nir, nir_opt_dce);
 517                 }
 518                 NIR_PASS(progress, sel->nir, nir_opt_if);
 519                 NIR_PASS(progress, sel->nir, nir_opt_dead_cf);
 520                 NIR_PASS(progress, sel->nir, nir_opt_cse);
 521                 NIR_PASS(progress, sel->nir, nir_opt_peephole_select, 8);
 522
 523                 /* Needed for algebraic lowering */
 524                 NIR_PASS(progress, sel->nir, nir_opt_algebraic);
 525                 NIR_PASS(progress, sel->nir, nir_opt_constant_folding);
 526
 527                 NIR_PASS(progress, sel->nir, nir_opt_undef);
 528                 NIR_PASS(progress, sel->nir, nir_opt_conditional_discard);
 529                 if (sel->nir->options->max_unroll_iterations) {
 530                         NIR_PASS(progress, sel->nir, nir_opt_loop_unroll, 0);
 531                 }
 532         } while (progress);
 533 }
 534
 535 static void declare_nir_input_vs(struct si_shader_context *ctx,
 536                                  struct nir_variable *variable,
 537                                  LLVMValueRef out[4])
 538 {
 539         si_llvm_load_input_vs(ctx, variable->data.driver_location / 4, out);
 540 }
 541
 542 static void declare_nir_input_fs(struct si_shader_context *ctx,
 543                                  struct nir_variable *variable,
 544                                  unsigned input_index,
 545                                  LLVMValueRef out[4])
 546 {
 547         unsigned slot = variable->data.location;
 548         if (slot == VARYING_SLOT_POS) {
 549                 out[0] = LLVMGetParam(ctx->main_fn, SI_PARAM_POS_X_FLOAT);
 550                 out[1] = LLVMGetParam(ctx->main_fn, SI_PARAM_POS_Y_FLOAT);
 551                 out[2] = LLVMGetParam(ctx->main_fn, SI_PARAM_POS_Z_FLOAT);
 552                 out[3] = ac_build_fdiv(&ctx->ac, ctx->ac.f32_1,
 553                                 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_W_FLOAT));
 554                 return;
 555         }
 556
 557         si_llvm_load_input_fs(ctx, input_index, out);
 558 }
 559
 560 LLVMValueRef si_nir_load_input_gs(struct ac_shader_abi *abi,
 561                                   unsigned location,
 562                                   unsigned driver_location,
 563                                   unsigned component,
 564                                   unsigned num_components,
 565                                   unsigned vertex_index,
 566                                   unsigned const_index,
 567                                   LLVMTypeRef type)
 568 {
 569         struct si_shader_context *ctx = si_shader_context_from_abi(abi);
 570
 571         LLVMValueRef value[4];
 572         for (unsigned i = component; i < num_components + component; i++) {
 573                 value[i] = si_llvm_load_input_gs(&ctx->abi, driver_location  / 4,
 574                                                  vertex_index, type, i);
 575         }
 576
 577         return ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
 578 }
 579
 580 static LLVMValueRef
 581 si_nir_load_sampler_desc(struct ac_shader_abi *abi,
 582                          unsigned descriptor_set, unsigned base_index,
 583                          unsigned constant_index, LLVMValueRef dynamic_index,
 584                          enum ac_descriptor_type desc_type, bool image,
 585                          bool write)
 586 {
 587         struct si_shader_context *ctx = si_shader_context_from_abi(abi);
 588         LLVMBuilderRef builder = ctx->ac.builder;
 589         LLVMValueRef list = LLVMGetParam(ctx->main_fn, ctx->param_samplers_and_images);
 590         LLVMValueRef index = dynamic_index;
 591
 592         assert(!descriptor_set);
 593
 594         if (!index)
 595                 index = ctx->ac.i32_0;
 596
 597         index = LLVMBuildAdd(builder, index,
 598                              LLVMConstInt(ctx->ac.i32, base_index + constant_index, false),
 599                              "");
 600
 601         if (image) {
 602                 assert(desc_type == AC_DESC_IMAGE || desc_type == AC_DESC_BUFFER);
 603                 assert(base_index + constant_index < ctx->num_images);
 604
 605                 if (dynamic_index)
 606                         index = si_llvm_bound_index(ctx, index, ctx->num_images);
 607
 608                 index = LLVMBuildSub(ctx->gallivm.builder,
 609                                      LLVMConstInt(ctx->i32, SI_NUM_IMAGES - 1, 0),
 610                                      index, "");
 611
 612                 /* TODO: be smarter about when we use dcc_off */
 613                 return si_load_image_desc(ctx, list, index, desc_type, write);
 614         }
 615
 616         assert(base_index + constant_index < ctx->num_samplers);
 617
 618         if (dynamic_index)
 619                 index = si_llvm_bound_index(ctx, index, ctx->num_samplers);
 620
 621         index = LLVMBuildAdd(ctx->gallivm.builder, index,
 622                              LLVMConstInt(ctx->i32, SI_NUM_IMAGES / 2, 0), "");
 623
 624         return si_load_sampler_desc(ctx, list, index, desc_type);
 625 }
 626
 627 bool si_nir_build_llvm(struct si_shader_context *ctx, struct nir_shader *nir)
 628 {
 629         struct tgsi_shader_info *info = &ctx->shader->selector->info;
 630
 631         if (nir->info.stage == MESA_SHADER_VERTEX ||
 632             nir->info.stage == MESA_SHADER_FRAGMENT) {
 633                 uint64_t processed_inputs = 0;
 634                 nir_foreach_variable(variable, &nir->inputs) {
 635                         unsigned attrib_count = glsl_count_attribute_slots(variable->type,
 636                                                                            nir->info.stage == MESA_SHADER_VERTEX);
 637                         unsigned input_idx = variable->data.driver_location;
 638
 639                         assert(attrib_count == 1);
 640
 641                         LLVMValueRef data[4];
 642                         unsigned loc = variable->data.location;
 643
 644                         /* Packed components share the same location so skip
 645                          * them if we have already processed the location.
 646                          */
 647                         if (processed_inputs & ((uint64_t)1 << loc))
 648                                 continue;
 649
 650                         if (nir->info.stage == MESA_SHADER_VERTEX)
 651                                 declare_nir_input_vs(ctx, variable, data);
 652                         else if (nir->info.stage == MESA_SHADER_FRAGMENT)
 653                                 declare_nir_input_fs(ctx, variable, input_idx / 4, data);
 654
 655                         for (unsigned chan = 0; chan < 4; chan++) {
 656                                 ctx->inputs[input_idx + chan] =
 657                                         LLVMBuildBitCast(ctx->ac.builder, data[chan], ctx->ac.i32, "");
 658                         }
 659                         processed_inputs |= ((uint64_t)1 << loc);
 660                 }
 661         }
 662
 663         ctx->abi.inputs = &ctx->inputs[0];
 664         ctx->abi.load_sampler_desc = si_nir_load_sampler_desc;
 665         ctx->abi.clamp_shadow_reference = true;
 666
 667         ctx->num_samplers = util_last_bit(info->samplers_declared);
 668         ctx->num_images = util_last_bit(info->images_declared);
 669
 670         ac_nir_translate(&ctx->ac, &ctx->abi, nir, NULL);
 671
 672         return true;
 673 }