src/gallium/drivers/radeonsi/si_shader_nir.c

   1 /*
   2  * Copyright 2017 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 #include "si_shader.h"
  25 #include "si_shader_internal.h"
  26
  27 #include "ac_nir_to_llvm.h"
  28
  29 #include "tgsi/tgsi_from_mesa.h"
  30
  31 #include "compiler/nir/nir.h"
  32 #include "compiler/nir_types.h"
  33
  34
  35 static int
  36 type_size(const struct glsl_type *type)
  37 {
  38    return glsl_count_attribute_slots(type, false);
  39 }
  40
  41 static void scan_instruction(struct tgsi_shader_info *info,
  42                              nir_instr *instr)
  43 {
  44         if (instr->type == nir_instr_type_alu) {
  45                 nir_alu_instr *alu = nir_instr_as_alu(instr);
  46
  47                 switch (alu->op) {
  48                 case nir_op_fddx:
  49                 case nir_op_fddy:
  50                 case nir_op_fddx_fine:
  51                 case nir_op_fddy_fine:
  52                 case nir_op_fddx_coarse:
  53                 case nir_op_fddy_coarse:
  54                         info->uses_derivatives = true;
  55                         break;
  56                 default:
  57                         break;
  58                 }
  59         } else if (instr->type == nir_instr_type_tex) {
  60                 nir_tex_instr *tex = nir_instr_as_tex(instr);
  61
  62                 if (!tex->texture) {
  63                         info->samplers_declared |=
  64                                 u_bit_consecutive(tex->sampler_index, 1);
  65                 }
  66
  67                 switch (tex->op) {
  68                 case nir_texop_tex:
  69                 case nir_texop_txb:
  70                 case nir_texop_lod:
  71                         info->uses_derivatives = true;
  72                         break;
  73                 default:
  74                         break;
  75                 }
  76         } else if (instr->type == nir_instr_type_intrinsic) {
  77                 nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);
  78
  79                 switch (intr->intrinsic) {
  80                 case nir_intrinsic_load_front_face:
  81                         info->uses_frontface = 1;
  82                         break;
  83                 case nir_intrinsic_load_instance_id:
  84                         info->uses_instanceid = 1;
  85                         break;
  86                 case nir_intrinsic_load_invocation_id:
  87                         info->uses_invocationid = true;
  88                         break;
  89                 case nir_intrinsic_load_vertex_id:
  90                         info->uses_vertexid = 1;
  91                         break;
  92                 case nir_intrinsic_load_vertex_id_zero_base:
  93                         info->uses_vertexid_nobase = 1;
  94                         break;
  95                 case nir_intrinsic_load_base_vertex:
  96                         info->uses_basevertex = 1;
  97                         break;
  98                 case nir_intrinsic_load_primitive_id:
  99                         info->uses_primid = 1;
 100                         break;
 101                 case nir_intrinsic_load_sample_mask_in:
 102                         info->reads_samplemask = true;
 103                         break;
 104                 case nir_intrinsic_load_tess_level_inner:
 105                 case nir_intrinsic_load_tess_level_outer:
 106                         info->reads_tess_factors = true;
 107                         break;
 108                 case nir_intrinsic_image_store:
 109                 case nir_intrinsic_image_atomic_add:
 110                 case nir_intrinsic_image_atomic_min:
 111                 case nir_intrinsic_image_atomic_max:
 112                 case nir_intrinsic_image_atomic_and:
 113                 case nir_intrinsic_image_atomic_or:
 114                 case nir_intrinsic_image_atomic_xor:
 115                 case nir_intrinsic_image_atomic_exchange:
 116                 case nir_intrinsic_image_atomic_comp_swap:
 117                 case nir_intrinsic_store_ssbo:
 118                 case nir_intrinsic_ssbo_atomic_add:
 119                 case nir_intrinsic_ssbo_atomic_imin:
 120                 case nir_intrinsic_ssbo_atomic_umin:
 121                 case nir_intrinsic_ssbo_atomic_imax:
 122                 case nir_intrinsic_ssbo_atomic_umax:
 123                 case nir_intrinsic_ssbo_atomic_and:
 124                 case nir_intrinsic_ssbo_atomic_or:
 125                 case nir_intrinsic_ssbo_atomic_xor:
 126                 case nir_intrinsic_ssbo_atomic_exchange:
 127                 case nir_intrinsic_ssbo_atomic_comp_swap:
 128                         info->writes_memory = true;
 129                         break;
 130                 default:
 131                         break;
 132                 }
 133         }
 134 }
 135
 136 void si_nir_scan_tess_ctrl(const struct nir_shader *nir,
 137                            const struct tgsi_shader_info *info,
 138                            struct tgsi_tessctrl_info *out)
 139 {
 140         memset(out, 0, sizeof(*out));
 141
 142         if (nir->info.stage != MESA_SHADER_TESS_CTRL)
 143                 return;
 144
 145         /* Initial value = true. Here the pass will accumulate results from
 146          * multiple segments surrounded by barriers. If tess factors aren't
 147          * written at all, it's a shader bug and we don't care if this will be
 148          * true.
 149          */
 150         out->tessfactors_are_def_in_all_invocs = true;
 151
 152         /* TODO: Implement scanning of tess factors, see tgsi backend. */
 153 }
 154
 155 void si_nir_scan_shader(const struct nir_shader *nir,
 156                         struct tgsi_shader_info *info)
 157 {
 158         nir_function *func;
 159         unsigned i;
 160
 161         assert(nir->info.stage == MESA_SHADER_VERTEX ||
 162                nir->info.stage == MESA_SHADER_GEOMETRY ||
 163                nir->info.stage == MESA_SHADER_TESS_CTRL ||
 164                nir->info.stage == MESA_SHADER_TESS_EVAL ||
 165                nir->info.stage == MESA_SHADER_FRAGMENT);
 166
 167         info->processor = pipe_shader_type_from_mesa(nir->info.stage);
 168         info->num_tokens = 2; /* indicate that the shader is non-empty */
 169         info->num_instructions = 2;
 170
 171         if (nir->info.stage == MESA_SHADER_TESS_CTRL) {
 172                 info->properties[TGSI_PROPERTY_TCS_VERTICES_OUT] =
 173                         nir->info.tess.tcs_vertices_out;
 174         }
 175
 176         if (nir->info.stage == MESA_SHADER_TESS_EVAL) {
 177                 if (nir->info.tess.primitive_mode == GL_ISOLINES)
 178                         info->properties[TGSI_PROPERTY_TES_PRIM_MODE] = PIPE_PRIM_LINES;
 179                 else
 180                         info->properties[TGSI_PROPERTY_TES_PRIM_MODE] = nir->info.tess.primitive_mode;
 181
 182                 STATIC_ASSERT((TESS_SPACING_EQUAL + 1) % 3 == PIPE_TESS_SPACING_EQUAL);
 183                 STATIC_ASSERT((TESS_SPACING_FRACTIONAL_ODD + 1) % 3 ==
 184                               PIPE_TESS_SPACING_FRACTIONAL_ODD);
 185                 STATIC_ASSERT((TESS_SPACING_FRACTIONAL_EVEN + 1) % 3 ==
 186                               PIPE_TESS_SPACING_FRACTIONAL_EVEN);
 187
 188                 info->properties[TGSI_PROPERTY_TES_SPACING] = (nir->info.tess.spacing + 1) % 3;
 189                 info->properties[TGSI_PROPERTY_TES_VERTEX_ORDER_CW] = !nir->info.tess.ccw;
 190                 info->properties[TGSI_PROPERTY_TES_POINT_MODE] = nir->info.tess.point_mode;
 191         }
 192
 193         if (nir->info.stage == MESA_SHADER_GEOMETRY) {
 194                 info->properties[TGSI_PROPERTY_GS_INPUT_PRIM] = nir->info.gs.input_primitive;
 195                 info->properties[TGSI_PROPERTY_GS_OUTPUT_PRIM] = nir->info.gs.output_primitive;
 196                 info->properties[TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES] = nir->info.gs.vertices_out;
 197                 info->properties[TGSI_PROPERTY_GS_INVOCATIONS] = nir->info.gs.invocations;
 198         }
 199
 200         i = 0;
 201         uint64_t processed_inputs = 0;
 202         unsigned num_inputs = 0;
 203         nir_foreach_variable(variable, &nir->inputs) {
 204                 unsigned semantic_name, semantic_index;
 205                 unsigned attrib_count = glsl_count_attribute_slots(variable->type,
 206                                                                    nir->info.stage == MESA_SHADER_VERTEX);
 207
 208                 /* Vertex shader inputs don't have semantics. The state
 209                  * tracker has already mapped them to attributes via
 210                  * variable->data.driver_location.
 211                  */
 212                 if (nir->info.stage == MESA_SHADER_VERTEX) {
 213                         if (glsl_type_is_dual_slot(variable->type))
 214                                 num_inputs += 2;
 215                         else
 216                                 num_inputs++;
 217                         continue;
 218                 }
 219
 220                 assert(nir->info.stage != MESA_SHADER_FRAGMENT ||
 221                        (attrib_count == 1 && "not implemented"));
 222
 223                 /* Fragment shader position is a system value. */
 224                 if (nir->info.stage == MESA_SHADER_FRAGMENT &&
 225                     variable->data.location == VARYING_SLOT_POS) {
 226                         if (variable->data.pixel_center_integer)
 227                                 info->properties[TGSI_PROPERTY_FS_COORD_PIXEL_CENTER] =
 228                                         TGSI_FS_COORD_PIXEL_CENTER_INTEGER;
 229
 230                         num_inputs++;
 231                         continue;
 232                 }
 233
 234                 i = variable->data.driver_location;
 235                 if (processed_inputs & ((uint64_t)1 << i))
 236                         continue;
 237
 238                 processed_inputs |= ((uint64_t)1 << i);
 239                 num_inputs++;
 240
 241                 tgsi_get_gl_varying_semantic(variable->data.location, true,
 242                                              &semantic_name, &semantic_index);
 243
 244                 info->input_semantic_name[i] = semantic_name;
 245                 info->input_semantic_index[i] = semantic_index;
 246
 247                 if (semantic_name == TGSI_SEMANTIC_PRIMID)
 248                         info->uses_primid = true;
 249
 250                 if (variable->data.sample)
 251                         info->input_interpolate_loc[i] = TGSI_INTERPOLATE_LOC_SAMPLE;
 252                 else if (variable->data.centroid)
 253                         info->input_interpolate_loc[i] = TGSI_INTERPOLATE_LOC_CENTROID;
 254                 else
 255                         info->input_interpolate_loc[i] = TGSI_INTERPOLATE_LOC_CENTER;
 256
 257                 enum glsl_base_type base_type =
 258                         glsl_get_base_type(glsl_without_array(variable->type));
 259
 260                 switch (variable->data.interpolation) {
 261                 case INTERP_MODE_NONE:
 262                         if (glsl_base_type_is_integer(base_type)) {
 263                                 info->input_interpolate[i] = TGSI_INTERPOLATE_CONSTANT;
 264                                 break;
 265                         }
 266
 267                         if (semantic_name == TGSI_SEMANTIC_COLOR) {
 268                                 info->input_interpolate[i] = TGSI_INTERPOLATE_COLOR;
 269                                 goto persp_locations;
 270                         }
 271                         /* fall-through */
 272                 case INTERP_MODE_SMOOTH:
 273                         assert(!glsl_base_type_is_integer(base_type));
 274
 275                         info->input_interpolate[i] = TGSI_INTERPOLATE_PERSPECTIVE;
 276
 277                 persp_locations:
 278                         if (variable->data.sample)
 279                                 info->uses_persp_sample = true;
 280                         else if (variable->data.centroid)
 281                                 info->uses_persp_centroid = true;
 282                         else
 283                                 info->uses_persp_center = true;
 284                         break;
 285
 286                 case INTERP_MODE_NOPERSPECTIVE:
 287                         assert(!glsl_base_type_is_integer(base_type));
 288
 289                         info->input_interpolate[i] = TGSI_INTERPOLATE_LINEAR;
 290
 291                         if (variable->data.sample)
 292                                 info->uses_linear_sample = true;
 293                         else if (variable->data.centroid)
 294                                 info->uses_linear_centroid = true;
 295                         else
 296                                 info->uses_linear_center = true;
 297                         break;
 298
 299                 case INTERP_MODE_FLAT:
 300                         info->input_interpolate[i] = TGSI_INTERPOLATE_CONSTANT;
 301                         break;
 302                 }
 303
 304                 /* TODO make this more precise */
 305                 if (variable->data.location == VARYING_SLOT_COL0)
 306                         info->colors_read |= 0x0f;
 307                 else if (variable->data.location == VARYING_SLOT_COL1)
 308                         info->colors_read |= 0xf0;
 309         }
 310
 311         info->num_inputs = num_inputs;
 312
 313
 314         i = 0;
 315         uint64_t processed_outputs = 0;
 316         unsigned num_outputs = 0;
 317         nir_foreach_variable(variable, &nir->outputs) {
 318                 unsigned semantic_name, semantic_index;
 319
 320                 if (nir->info.stage == MESA_SHADER_FRAGMENT) {
 321                         tgsi_get_gl_frag_result_semantic(variable->data.location,
 322                                 &semantic_name, &semantic_index);
 323
 324                         /* Adjust for dual source blending */
 325                         if (variable->data.index > 0) {
 326                                 semantic_index++;
 327                         }
 328                 } else {
 329                         tgsi_get_gl_varying_semantic(variable->data.location, true,
 330                                                      &semantic_name, &semantic_index);
 331                 }
 332
 333                 i = variable->data.driver_location;
 334                 if (processed_outputs & ((uint64_t)1 << i))
 335                         continue;
 336
 337                 processed_outputs |= ((uint64_t)1 << i);
 338                 num_outputs++;
 339
 340                 info->output_semantic_name[i] = semantic_name;
 341                 info->output_semantic_index[i] = semantic_index;
 342                 info->output_usagemask[i] = TGSI_WRITEMASK_XYZW;
 343
 344                 unsigned num_components = 4;
 345                 unsigned vector_elements = glsl_get_vector_elements(glsl_without_array(variable->type));
 346                 if (vector_elements)
 347                         num_components = vector_elements;
 348
 349                 unsigned gs_out_streams;
 350                 if (variable->data.stream & (1u << 31)) {
 351                         gs_out_streams = variable->data.stream & ~(1u << 31);
 352                 } else {
 353                         assert(variable->data.stream < 4);
 354                         gs_out_streams = 0;
 355                         for (unsigned j = 0; j < num_components; ++j)
 356                                 gs_out_streams |= variable->data.stream << (2 * (variable->data.location_frac + j));
 357                 }
 358
 359                 unsigned streamx = gs_out_streams & 3;
 360                 unsigned streamy = (gs_out_streams >> 2) & 3;
 361                 unsigned streamz = (gs_out_streams >> 4) & 3;
 362                 unsigned streamw = (gs_out_streams >> 6) & 3;
 363
 364                 if (info->output_usagemask[i] & TGSI_WRITEMASK_X) {
 365                         info->output_streams[i] |= streamx;
 366                         info->num_stream_output_components[streamx]++;
 367                 }
 368                 if (info->output_usagemask[i] & TGSI_WRITEMASK_Y) {
 369                         info->output_streams[i] |= streamy << 2;
 370                         info->num_stream_output_components[streamy]++;
 371                 }
 372                 if (info->output_usagemask[i] & TGSI_WRITEMASK_Z) {
 373                         info->output_streams[i] |= streamz << 4;
 374                         info->num_stream_output_components[streamz]++;
 375                 }
 376                 if (info->output_usagemask[i] & TGSI_WRITEMASK_W) {
 377                         info->output_streams[i] |= streamw << 6;
 378                         info->num_stream_output_components[streamw]++;
 379                 }
 380
 381                 switch (semantic_name) {
 382                 case TGSI_SEMANTIC_PRIMID:
 383                         info->writes_primid = true;
 384                         break;
 385                 case TGSI_SEMANTIC_VIEWPORT_INDEX:
 386                         info->writes_viewport_index = true;
 387                         break;
 388                 case TGSI_SEMANTIC_LAYER:
 389                         info->writes_layer = true;
 390                         break;
 391                 case TGSI_SEMANTIC_PSIZE:
 392                         info->writes_psize = true;
 393                         break;
 394                 case TGSI_SEMANTIC_CLIPVERTEX:
 395                         info->writes_clipvertex = true;
 396                         break;
 397                 case TGSI_SEMANTIC_COLOR:
 398                         info->colors_written |= 1 << semantic_index;
 399                         break;
 400                 case TGSI_SEMANTIC_STENCIL:
 401                         info->writes_stencil = true;
 402                         break;
 403                 case TGSI_SEMANTIC_SAMPLEMASK:
 404                         info->writes_samplemask = true;
 405                         break;
 406                 case TGSI_SEMANTIC_EDGEFLAG:
 407                         info->writes_edgeflag = true;
 408                         break;
 409                 case TGSI_SEMANTIC_POSITION:
 410                         if (info->processor == PIPE_SHADER_FRAGMENT)
 411                                 info->writes_z = true;
 412                         else
 413                                 info->writes_position = true;
 414                         break;
 415                 }
 416
 417                 if (nir->info.stage == MESA_SHADER_TESS_CTRL) {
 418                         switch (semantic_name) {
 419                         case TGSI_SEMANTIC_PATCH:
 420                                 info->reads_perpatch_outputs = true;
 421                         break;
 422                         case TGSI_SEMANTIC_TESSINNER:
 423                         case TGSI_SEMANTIC_TESSOUTER:
 424                                 info->reads_tessfactor_outputs = true;
 425                         break;
 426                         default:
 427                                 info->reads_pervertex_outputs = true;
 428                         }
 429                 }
 430         }
 431
 432         info->num_outputs = num_outputs;
 433
 434         nir_foreach_variable(variable, &nir->uniforms) {
 435                 const struct glsl_type *type = variable->type;
 436                 enum glsl_base_type base_type =
 437                         glsl_get_base_type(glsl_without_array(type));
 438                 unsigned aoa_size = MAX2(1, glsl_get_aoa_size(type));
 439
 440                 /* We rely on the fact that nir_lower_samplers_as_deref has
 441                  * eliminated struct dereferences.
 442                  */
 443                 if (base_type == GLSL_TYPE_SAMPLER)
 444                         info->samplers_declared |=
 445                                 u_bit_consecutive(variable->data.binding, aoa_size);
 446                 else if (base_type == GLSL_TYPE_IMAGE)
 447                         info->images_declared |=
 448                                 u_bit_consecutive(variable->data.binding, aoa_size);
 449         }
 450
 451         info->num_written_clipdistance = nir->info.clip_distance_array_size;
 452         info->num_written_culldistance = nir->info.cull_distance_array_size;
 453         info->clipdist_writemask = u_bit_consecutive(0, info->num_written_clipdistance);
 454         info->culldist_writemask = u_bit_consecutive(0, info->num_written_culldistance);
 455
 456         if (info->processor == PIPE_SHADER_FRAGMENT)
 457                 info->uses_kill = nir->info.fs.uses_discard;
 458
 459         /* TODO make this more accurate */
 460         info->const_buffers_declared = u_bit_consecutive(0, SI_NUM_CONST_BUFFERS);
 461         info->shader_buffers_declared = u_bit_consecutive(0, SI_NUM_SHADER_BUFFERS);
 462
 463         func = (struct nir_function *)exec_list_get_head_const(&nir->functions);
 464         nir_foreach_block(block, func->impl) {
 465                 nir_foreach_instr(instr, block)
 466                         scan_instruction(info, instr);
 467         }
 468 }
 469
 470 /**
 471  * Perform "lowering" operations on the NIR that are run once when the shader
 472  * selector is created.
 473  */
 474 void
 475 si_lower_nir(struct si_shader_selector* sel)
 476 {
 477         /* Adjust the driver location of inputs and outputs. The state tracker
 478          * interprets them as slots, while the ac/nir backend interprets them
 479          * as individual components.
 480          */
 481         nir_foreach_variable(variable, &sel->nir->inputs)
 482                 variable->data.driver_location *= 4;
 483
 484         nir_foreach_variable(variable, &sel->nir->outputs) {
 485                 variable->data.driver_location *= 4;
 486
 487                 if (sel->nir->info.stage == MESA_SHADER_FRAGMENT) {
 488                         if (variable->data.location == FRAG_RESULT_DEPTH)
 489                                 variable->data.driver_location += 2;
 490                         else if (variable->data.location == FRAG_RESULT_STENCIL)
 491                                 variable->data.driver_location += 1;
 492                 }
 493         }
 494
 495         /* Perform lowerings (and optimizations) of code.
 496          *
 497          * Performance considerations aside, we must:
 498          * - lower certain ALU operations
 499          * - ensure constant offsets for texture instructions are folded
 500          *   and copy-propagated
 501          */
 502         NIR_PASS_V(sel->nir, nir_lower_io, nir_var_uniform, type_size,
 503                    (nir_lower_io_options)0);
 504         NIR_PASS_V(sel->nir, nir_lower_uniforms_to_ubo);
 505
 506         NIR_PASS_V(sel->nir, nir_lower_returns);
 507         NIR_PASS_V(sel->nir, nir_lower_vars_to_ssa);
 508         NIR_PASS_V(sel->nir, nir_lower_alu_to_scalar);
 509         NIR_PASS_V(sel->nir, nir_lower_phis_to_scalar);
 510
 511         static const struct nir_lower_tex_options lower_tex_options = {
 512                 .lower_txp = ~0u,
 513         };
 514         NIR_PASS_V(sel->nir, nir_lower_tex, &lower_tex_options);
 515
 516         const nir_lower_subgroups_options subgroups_options = {
 517                 .subgroup_size = 64,
 518                 .ballot_bit_size = 32,
 519                 .lower_to_scalar = true,
 520                 .lower_subgroup_masks = true,
 521                 .lower_vote_trivial = false,
 522         };
 523         NIR_PASS_V(sel->nir, nir_lower_subgroups, &subgroups_options);
 524
 525         bool progress;
 526         do {
 527                 progress = false;
 528
 529                 /* (Constant) copy propagation is needed for txf with offsets. */
 530                 NIR_PASS(progress, sel->nir, nir_copy_prop);
 531                 NIR_PASS(progress, sel->nir, nir_opt_remove_phis);
 532                 NIR_PASS(progress, sel->nir, nir_opt_dce);
 533                 if (nir_opt_trivial_continues(sel->nir)) {
 534                         progress = true;
 535                         NIR_PASS(progress, sel->nir, nir_copy_prop);
 536                         NIR_PASS(progress, sel->nir, nir_opt_dce);
 537                 }
 538                 NIR_PASS(progress, sel->nir, nir_opt_if);
 539                 NIR_PASS(progress, sel->nir, nir_opt_dead_cf);
 540                 NIR_PASS(progress, sel->nir, nir_opt_cse);
 541                 NIR_PASS(progress, sel->nir, nir_opt_peephole_select, 8);
 542
 543                 /* Needed for algebraic lowering */
 544                 NIR_PASS(progress, sel->nir, nir_opt_algebraic);
 545                 NIR_PASS(progress, sel->nir, nir_opt_constant_folding);
 546
 547                 NIR_PASS(progress, sel->nir, nir_opt_undef);
 548                 NIR_PASS(progress, sel->nir, nir_opt_conditional_discard);
 549                 if (sel->nir->options->max_unroll_iterations) {
 550                         NIR_PASS(progress, sel->nir, nir_opt_loop_unroll, 0);
 551                 }
 552         } while (progress);
 553 }
 554
 555 static void declare_nir_input_vs(struct si_shader_context *ctx,
 556                                  struct nir_variable *variable,
 557                                  LLVMValueRef out[4])
 558 {
 559         si_llvm_load_input_vs(ctx, variable->data.driver_location / 4, out);
 560 }
 561
 562 static void declare_nir_input_fs(struct si_shader_context *ctx,
 563                                  struct nir_variable *variable,
 564                                  unsigned input_index,
 565                                  LLVMValueRef out[4])
 566 {
 567         unsigned slot = variable->data.location;
 568         if (slot == VARYING_SLOT_POS) {
 569                 out[0] = LLVMGetParam(ctx->main_fn, SI_PARAM_POS_X_FLOAT);
 570                 out[1] = LLVMGetParam(ctx->main_fn, SI_PARAM_POS_Y_FLOAT);
 571                 out[2] = LLVMGetParam(ctx->main_fn, SI_PARAM_POS_Z_FLOAT);
 572                 out[3] = ac_build_fdiv(&ctx->ac, ctx->ac.f32_1,
 573                                 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_W_FLOAT));
 574                 return;
 575         }
 576
 577         si_llvm_load_input_fs(ctx, input_index, out);
 578 }
 579
 580 LLVMValueRef si_nir_load_input_gs(struct ac_shader_abi *abi,
 581                                   unsigned location,
 582                                   unsigned driver_location,
 583                                   unsigned component,
 584                                   unsigned num_components,
 585                                   unsigned vertex_index,
 586                                   unsigned const_index,
 587                                   LLVMTypeRef type)
 588 {
 589         struct si_shader_context *ctx = si_shader_context_from_abi(abi);
 590
 591         LLVMValueRef value[4];
 592         for (unsigned i = component; i < num_components + component; i++) {
 593                 value[i] = si_llvm_load_input_gs(&ctx->abi, driver_location  / 4,
 594                                                  vertex_index, type, i);
 595         }
 596
 597         return ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
 598 }
 599
 600 static LLVMValueRef
 601 si_nir_load_sampler_desc(struct ac_shader_abi *abi,
 602                          unsigned descriptor_set, unsigned base_index,
 603                          unsigned constant_index, LLVMValueRef dynamic_index,
 604                          enum ac_descriptor_type desc_type, bool image,
 605                          bool write)
 606 {
 607         struct si_shader_context *ctx = si_shader_context_from_abi(abi);
 608         LLVMBuilderRef builder = ctx->ac.builder;
 609         LLVMValueRef list = LLVMGetParam(ctx->main_fn, ctx->param_samplers_and_images);
 610         LLVMValueRef index = dynamic_index;
 611
 612         assert(!descriptor_set);
 613
 614         if (!index)
 615                 index = ctx->ac.i32_0;
 616
 617         index = LLVMBuildAdd(builder, index,
 618                              LLVMConstInt(ctx->ac.i32, base_index + constant_index, false),
 619                              "");
 620
 621         if (image) {
 622                 assert(desc_type == AC_DESC_IMAGE || desc_type == AC_DESC_BUFFER);
 623                 assert(base_index + constant_index < ctx->num_images);
 624
 625                 if (dynamic_index)
 626                         index = si_llvm_bound_index(ctx, index, ctx->num_images);
 627
 628                 index = LLVMBuildSub(ctx->gallivm.builder,
 629                                      LLVMConstInt(ctx->i32, SI_NUM_IMAGES - 1, 0),
 630                                      index, "");
 631
 632                 /* TODO: be smarter about when we use dcc_off */
 633                 return si_load_image_desc(ctx, list, index, desc_type, write);
 634         }
 635
 636         assert(base_index + constant_index < ctx->num_samplers);
 637
 638         if (dynamic_index)
 639                 index = si_llvm_bound_index(ctx, index, ctx->num_samplers);
 640
 641         index = LLVMBuildAdd(ctx->gallivm.builder, index,
 642                              LLVMConstInt(ctx->i32, SI_NUM_IMAGES / 2, 0), "");
 643
 644         return si_load_sampler_desc(ctx, list, index, desc_type);
 645 }
 646
 647 static void bitcast_inputs(struct si_shader_context *ctx,
 648                            LLVMValueRef data[4],
 649                            unsigned input_idx)
 650 {
 651         for (unsigned chan = 0; chan < 4; chan++) {
 652                 ctx->inputs[input_idx + chan] =
 653                         LLVMBuildBitCast(ctx->ac.builder, data[chan], ctx->ac.i32, "");
 654         }
 655 }
 656
 657 bool si_nir_build_llvm(struct si_shader_context *ctx, struct nir_shader *nir)
 658 {
 659         struct tgsi_shader_info *info = &ctx->shader->selector->info;
 660
 661         if (nir->info.stage == MESA_SHADER_VERTEX ||
 662             nir->info.stage == MESA_SHADER_FRAGMENT) {
 663                 uint64_t processed_inputs = 0;
 664                 nir_foreach_variable(variable, &nir->inputs) {
 665                         unsigned attrib_count = glsl_count_attribute_slots(variable->type,
 666                                                                            nir->info.stage == MESA_SHADER_VERTEX);
 667                         unsigned input_idx = variable->data.driver_location;
 668
 669                         assert(attrib_count == 1);
 670
 671                         LLVMValueRef data[4];
 672                         unsigned loc = variable->data.location;
 673
 674                         /* Packed components share the same location so skip
 675                          * them if we have already processed the location.
 676                          */
 677                         if (processed_inputs & ((uint64_t)1 << loc))
 678                                 continue;
 679
 680                         if (nir->info.stage == MESA_SHADER_VERTEX) {
 681                                 declare_nir_input_vs(ctx, variable, data);
 682                                 bitcast_inputs(ctx, data, input_idx);
 683                         } else if (nir->info.stage == MESA_SHADER_FRAGMENT) {
 684                                 declare_nir_input_fs(ctx, variable, input_idx / 4, data);
 685                                 bitcast_inputs(ctx, data, input_idx);
 686                         }
 687
 688                         processed_inputs |= ((uint64_t)1 << loc);
 689                 }
 690         }
 691
 692         ctx->abi.inputs = &ctx->inputs[0];
 693         ctx->abi.load_sampler_desc = si_nir_load_sampler_desc;
 694         ctx->abi.clamp_shadow_reference = true;
 695
 696         ctx->num_samplers = util_last_bit(info->samplers_declared);
 697         ctx->num_images = util_last_bit(info->images_declared);
 698
 699         ac_nir_translate(&ctx->ac, &ctx->abi, nir, NULL);
 700
 701         return true;
 702 }