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radeonsi/nir: gather some missing fs info
[mesa.git] / src / gallium / drivers / radeonsi / si_shader_nir.c
1 /*
2 * Copyright 2017 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23
24 #include "si_shader.h"
25 #include "si_shader_internal.h"
26
27 #include "ac_nir_to_llvm.h"
28
29 #include "tgsi/tgsi_from_mesa.h"
30
31 #include "compiler/nir/nir.h"
32 #include "compiler/nir_types.h"
33
34
35 static int
36 type_size(const struct glsl_type *type)
37 {
38 return glsl_count_attribute_slots(type, false);
39 }
40
41 static void scan_instruction(struct tgsi_shader_info *info,
42 nir_instr *instr)
43 {
44 if (instr->type == nir_instr_type_alu) {
45 nir_alu_instr *alu = nir_instr_as_alu(instr);
46
47 switch (alu->op) {
48 case nir_op_fddx:
49 case nir_op_fddy:
50 case nir_op_fddx_fine:
51 case nir_op_fddy_fine:
52 case nir_op_fddx_coarse:
53 case nir_op_fddy_coarse:
54 info->uses_derivatives = true;
55 break;
56 default:
57 break;
58 }
59 } else if (instr->type == nir_instr_type_tex) {
60 nir_tex_instr *tex = nir_instr_as_tex(instr);
61
62 if (!tex->texture) {
63 info->samplers_declared |=
64 u_bit_consecutive(tex->sampler_index, 1);
65 }
66
67 switch (tex->op) {
68 case nir_texop_tex:
69 case nir_texop_txb:
70 case nir_texop_lod:
71 info->uses_derivatives = true;
72 break;
73 default:
74 break;
75 }
76 } else if (instr->type == nir_instr_type_intrinsic) {
77 nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);
78
79 switch (intr->intrinsic) {
80 case nir_intrinsic_load_front_face:
81 info->uses_frontface = 1;
82 break;
83 case nir_intrinsic_load_instance_id:
84 info->uses_instanceid = 1;
85 break;
86 case nir_intrinsic_load_invocation_id:
87 info->uses_invocationid = true;
88 break;
89 case nir_intrinsic_load_num_work_groups:
90 info->uses_grid_size = true;
91 break;
92 case nir_intrinsic_load_local_group_size:
93 /* The block size is translated to IMM with a fixed block size. */
94 if (info->properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] == 0)
95 info->uses_block_size = true;
96 break;
97 case nir_intrinsic_load_local_invocation_id:
98 case nir_intrinsic_load_work_group_id: {
99 unsigned mask = nir_ssa_def_components_read(&intr->dest.ssa);
100 while (mask) {
101 unsigned i = u_bit_scan(&mask);
102
103 if (intr->intrinsic == nir_intrinsic_load_work_group_id)
104 info->uses_block_id[i] = true;
105 else
106 info->uses_thread_id[i] = true;
107 }
108 break;
109 }
110 case nir_intrinsic_load_vertex_id:
111 info->uses_vertexid = 1;
112 break;
113 case nir_intrinsic_load_vertex_id_zero_base:
114 info->uses_vertexid_nobase = 1;
115 break;
116 case nir_intrinsic_load_base_vertex:
117 info->uses_basevertex = 1;
118 break;
119 case nir_intrinsic_load_primitive_id:
120 info->uses_primid = 1;
121 break;
122 case nir_intrinsic_load_sample_mask_in:
123 info->reads_samplemask = true;
124 break;
125 case nir_intrinsic_load_tess_level_inner:
126 case nir_intrinsic_load_tess_level_outer:
127 info->reads_tess_factors = true;
128 break;
129 case nir_intrinsic_image_store:
130 case nir_intrinsic_image_atomic_add:
131 case nir_intrinsic_image_atomic_min:
132 case nir_intrinsic_image_atomic_max:
133 case nir_intrinsic_image_atomic_and:
134 case nir_intrinsic_image_atomic_or:
135 case nir_intrinsic_image_atomic_xor:
136 case nir_intrinsic_image_atomic_exchange:
137 case nir_intrinsic_image_atomic_comp_swap:
138 case nir_intrinsic_store_ssbo:
139 case nir_intrinsic_ssbo_atomic_add:
140 case nir_intrinsic_ssbo_atomic_imin:
141 case nir_intrinsic_ssbo_atomic_umin:
142 case nir_intrinsic_ssbo_atomic_imax:
143 case nir_intrinsic_ssbo_atomic_umax:
144 case nir_intrinsic_ssbo_atomic_and:
145 case nir_intrinsic_ssbo_atomic_or:
146 case nir_intrinsic_ssbo_atomic_xor:
147 case nir_intrinsic_ssbo_atomic_exchange:
148 case nir_intrinsic_ssbo_atomic_comp_swap:
149 info->writes_memory = true;
150 break;
151 case nir_intrinsic_load_var: {
152 nir_variable *var = intr->variables[0]->var;
153 nir_variable_mode mode = var->data.mode;
154 enum glsl_base_type base_type =
155 glsl_get_base_type(glsl_without_array(var->type));
156
157 if (mode == nir_var_shader_in) {
158 switch (var->data.interpolation) {
159 case INTERP_MODE_NONE:
160 if (glsl_base_type_is_integer(base_type))
161 break;
162
163 /* fall-through */
164 case INTERP_MODE_SMOOTH:
165 if (var->data.sample)
166 info->uses_persp_sample = true;
167 else if (var->data.centroid)
168 info->uses_persp_centroid = true;
169 else
170 info->uses_persp_center = true;
171 break;
172
173 case INTERP_MODE_NOPERSPECTIVE:
174 if (var->data.sample)
175 info->uses_linear_sample = true;
176 else if (var->data.centroid)
177 info->uses_linear_centroid = true;
178 else
179 info->uses_linear_center = true;
180 break;
181 }
182 }
183 break;
184 }
185 case nir_intrinsic_interp_var_at_centroid:
186 case nir_intrinsic_interp_var_at_sample:
187 case nir_intrinsic_interp_var_at_offset: {
188 enum glsl_interp_mode interp =
189 intr->variables[0]->var->data.interpolation;
190 switch (interp) {
191 case INTERP_MODE_SMOOTH:
192 case INTERP_MODE_NONE:
193 if (intr->intrinsic == nir_intrinsic_interp_var_at_centroid)
194 info->uses_persp_opcode_interp_centroid = true;
195 else if (intr->intrinsic == nir_intrinsic_interp_var_at_sample)
196 info->uses_persp_opcode_interp_sample = true;
197 else
198 info->uses_persp_opcode_interp_offset = true;
199 break;
200 case INTERP_MODE_NOPERSPECTIVE:
201 if (intr->intrinsic == nir_intrinsic_interp_var_at_centroid)
202 info->uses_linear_opcode_interp_centroid = true;
203 else if (intr->intrinsic == nir_intrinsic_interp_var_at_sample)
204 info->uses_linear_opcode_interp_sample = true;
205 else
206 info->uses_linear_opcode_interp_offset = true;
207 break;
208 case INTERP_MODE_FLAT:
209 break;
210 default:
211 unreachable("Unsupported interpoation type");
212 }
213 break;
214 }
215 default:
216 break;
217 }
218 }
219 }
220
221 void si_nir_scan_tess_ctrl(const struct nir_shader *nir,
222 const struct tgsi_shader_info *info,
223 struct tgsi_tessctrl_info *out)
224 {
225 memset(out, 0, sizeof(*out));
226
227 if (nir->info.stage != MESA_SHADER_TESS_CTRL)
228 return;
229
230 /* Initial value = true. Here the pass will accumulate results from
231 * multiple segments surrounded by barriers. If tess factors aren't
232 * written at all, it's a shader bug and we don't care if this will be
233 * true.
234 */
235 out->tessfactors_are_def_in_all_invocs = true;
236
237 /* TODO: Implement scanning of tess factors, see tgsi backend. */
238 }
239
240 void si_nir_scan_shader(const struct nir_shader *nir,
241 struct tgsi_shader_info *info)
242 {
243 nir_function *func;
244 unsigned i;
245
246 info->processor = pipe_shader_type_from_mesa(nir->info.stage);
247 info->num_tokens = 2; /* indicate that the shader is non-empty */
248 info->num_instructions = 2;
249
250 if (nir->info.stage == MESA_SHADER_TESS_CTRL) {
251 info->properties[TGSI_PROPERTY_TCS_VERTICES_OUT] =
252 nir->info.tess.tcs_vertices_out;
253 }
254
255 if (nir->info.stage == MESA_SHADER_TESS_EVAL) {
256 if (nir->info.tess.primitive_mode == GL_ISOLINES)
257 info->properties[TGSI_PROPERTY_TES_PRIM_MODE] = PIPE_PRIM_LINES;
258 else
259 info->properties[TGSI_PROPERTY_TES_PRIM_MODE] = nir->info.tess.primitive_mode;
260
261 STATIC_ASSERT((TESS_SPACING_EQUAL + 1) % 3 == PIPE_TESS_SPACING_EQUAL);
262 STATIC_ASSERT((TESS_SPACING_FRACTIONAL_ODD + 1) % 3 ==
263 PIPE_TESS_SPACING_FRACTIONAL_ODD);
264 STATIC_ASSERT((TESS_SPACING_FRACTIONAL_EVEN + 1) % 3 ==
265 PIPE_TESS_SPACING_FRACTIONAL_EVEN);
266
267 info->properties[TGSI_PROPERTY_TES_SPACING] = (nir->info.tess.spacing + 1) % 3;
268 info->properties[TGSI_PROPERTY_TES_VERTEX_ORDER_CW] = !nir->info.tess.ccw;
269 info->properties[TGSI_PROPERTY_TES_POINT_MODE] = nir->info.tess.point_mode;
270 }
271
272 if (nir->info.stage == MESA_SHADER_GEOMETRY) {
273 info->properties[TGSI_PROPERTY_GS_INPUT_PRIM] = nir->info.gs.input_primitive;
274 info->properties[TGSI_PROPERTY_GS_OUTPUT_PRIM] = nir->info.gs.output_primitive;
275 info->properties[TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES] = nir->info.gs.vertices_out;
276 info->properties[TGSI_PROPERTY_GS_INVOCATIONS] = nir->info.gs.invocations;
277 }
278
279 if (nir->info.stage == MESA_SHADER_FRAGMENT) {
280 info->properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL] = nir->info.fs.early_fragment_tests;
281 info->properties[TGSI_PROPERTY_FS_POST_DEPTH_COVERAGE] = nir->info.fs.post_depth_coverage;
282 }
283
284 if (nir->info.stage == MESA_SHADER_COMPUTE) {
285 info->properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] = nir->info.cs.local_size[0];
286 info->properties[TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT] = nir->info.cs.local_size[1];
287 info->properties[TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH] = nir->info.cs.local_size[2];
288 }
289
290 i = 0;
291 uint64_t processed_inputs = 0;
292 unsigned num_inputs = 0;
293 nir_foreach_variable(variable, &nir->inputs) {
294 unsigned semantic_name, semantic_index;
295
296 const struct glsl_type *type = variable->type;
297 if (nir_is_per_vertex_io(variable, nir->info.stage)) {
298 assert(glsl_type_is_array(type));
299 type = glsl_get_array_element(type);
300 }
301
302 unsigned attrib_count = glsl_count_attribute_slots(type,
303 nir->info.stage == MESA_SHADER_VERTEX);
304
305 i = variable->data.driver_location;
306
307 /* Vertex shader inputs don't have semantics. The state
308 * tracker has already mapped them to attributes via
309 * variable->data.driver_location.
310 */
311 if (nir->info.stage == MESA_SHADER_VERTEX) {
312 /* TODO: gather the actual input useage and remove this. */
313 info->input_usage_mask[i] = TGSI_WRITEMASK_XYZW;
314
315 if (glsl_type_is_dual_slot(variable->type)) {
316 num_inputs += 2;
317
318 /* TODO: gather the actual input useage and remove this. */
319 info->input_usage_mask[i+1] = TGSI_WRITEMASK_XYZW;
320 } else
321 num_inputs++;
322 continue;
323 }
324
325 /* Fragment shader position is a system value. */
326 if (nir->info.stage == MESA_SHADER_FRAGMENT &&
327 variable->data.location == VARYING_SLOT_POS) {
328 if (variable->data.pixel_center_integer)
329 info->properties[TGSI_PROPERTY_FS_COORD_PIXEL_CENTER] =
330 TGSI_FS_COORD_PIXEL_CENTER_INTEGER;
331
332 num_inputs++;
333 continue;
334 }
335
336 for (unsigned j = 0; j < attrib_count; j++, i++) {
337
338 if (processed_inputs & ((uint64_t)1 << i))
339 continue;
340
341 processed_inputs |= ((uint64_t)1 << i);
342 num_inputs++;
343
344 tgsi_get_gl_varying_semantic(variable->data.location + j, true,
345 &semantic_name, &semantic_index);
346
347 info->input_semantic_name[i] = semantic_name;
348 info->input_semantic_index[i] = semantic_index;
349
350 if (semantic_name == TGSI_SEMANTIC_PRIMID)
351 info->uses_primid = true;
352
353 if (variable->data.sample)
354 info->input_interpolate_loc[i] = TGSI_INTERPOLATE_LOC_SAMPLE;
355 else if (variable->data.centroid)
356 info->input_interpolate_loc[i] = TGSI_INTERPOLATE_LOC_CENTROID;
357 else
358 info->input_interpolate_loc[i] = TGSI_INTERPOLATE_LOC_CENTER;
359
360 enum glsl_base_type base_type =
361 glsl_get_base_type(glsl_without_array(variable->type));
362
363 switch (variable->data.interpolation) {
364 case INTERP_MODE_NONE:
365 if (glsl_base_type_is_integer(base_type)) {
366 info->input_interpolate[i] = TGSI_INTERPOLATE_CONSTANT;
367 break;
368 }
369
370 if (semantic_name == TGSI_SEMANTIC_COLOR) {
371 info->input_interpolate[i] = TGSI_INTERPOLATE_COLOR;
372 break;
373 }
374 /* fall-through */
375
376 case INTERP_MODE_SMOOTH:
377 assert(!glsl_base_type_is_integer(base_type));
378
379 info->input_interpolate[i] = TGSI_INTERPOLATE_PERSPECTIVE;
380 break;
381
382 case INTERP_MODE_NOPERSPECTIVE:
383 assert(!glsl_base_type_is_integer(base_type));
384
385 info->input_interpolate[i] = TGSI_INTERPOLATE_LINEAR;
386 break;
387
388 case INTERP_MODE_FLAT:
389 info->input_interpolate[i] = TGSI_INTERPOLATE_CONSTANT;
390 break;
391 }
392
393 /* TODO make this more precise */
394 if (variable->data.location == VARYING_SLOT_COL0)
395 info->colors_read |= 0x0f;
396 else if (variable->data.location == VARYING_SLOT_COL1)
397 info->colors_read |= 0xf0;
398 }
399 }
400
401 info->num_inputs = num_inputs;
402
403
404 i = 0;
405 uint64_t processed_outputs = 0;
406 unsigned num_outputs = 0;
407 nir_foreach_variable(variable, &nir->outputs) {
408 unsigned semantic_name, semantic_index;
409
410 if (nir->info.stage == MESA_SHADER_FRAGMENT) {
411 tgsi_get_gl_frag_result_semantic(variable->data.location,
412 &semantic_name, &semantic_index);
413
414 /* Adjust for dual source blending */
415 if (variable->data.index > 0) {
416 semantic_index++;
417 }
418 } else {
419 tgsi_get_gl_varying_semantic(variable->data.location, true,
420 &semantic_name, &semantic_index);
421 }
422
423 i = variable->data.driver_location;
424 if (processed_outputs & ((uint64_t)1 << i))
425 continue;
426
427 processed_outputs |= ((uint64_t)1 << i);
428 num_outputs++;
429
430 info->output_semantic_name[i] = semantic_name;
431 info->output_semantic_index[i] = semantic_index;
432 info->output_usagemask[i] = TGSI_WRITEMASK_XYZW;
433
434 unsigned num_components = 4;
435 unsigned vector_elements = glsl_get_vector_elements(glsl_without_array(variable->type));
436 if (vector_elements)
437 num_components = vector_elements;
438
439 unsigned gs_out_streams;
440 if (variable->data.stream & (1u << 31)) {
441 gs_out_streams = variable->data.stream & ~(1u << 31);
442 } else {
443 assert(variable->data.stream < 4);
444 gs_out_streams = 0;
445 for (unsigned j = 0; j < num_components; ++j)
446 gs_out_streams |= variable->data.stream << (2 * (variable->data.location_frac + j));
447 }
448
449 unsigned streamx = gs_out_streams & 3;
450 unsigned streamy = (gs_out_streams >> 2) & 3;
451 unsigned streamz = (gs_out_streams >> 4) & 3;
452 unsigned streamw = (gs_out_streams >> 6) & 3;
453
454 if (info->output_usagemask[i] & TGSI_WRITEMASK_X) {
455 info->output_streams[i] |= streamx;
456 info->num_stream_output_components[streamx]++;
457 }
458 if (info->output_usagemask[i] & TGSI_WRITEMASK_Y) {
459 info->output_streams[i] |= streamy << 2;
460 info->num_stream_output_components[streamy]++;
461 }
462 if (info->output_usagemask[i] & TGSI_WRITEMASK_Z) {
463 info->output_streams[i] |= streamz << 4;
464 info->num_stream_output_components[streamz]++;
465 }
466 if (info->output_usagemask[i] & TGSI_WRITEMASK_W) {
467 info->output_streams[i] |= streamw << 6;
468 info->num_stream_output_components[streamw]++;
469 }
470
471 switch (semantic_name) {
472 case TGSI_SEMANTIC_PRIMID:
473 info->writes_primid = true;
474 break;
475 case TGSI_SEMANTIC_VIEWPORT_INDEX:
476 info->writes_viewport_index = true;
477 break;
478 case TGSI_SEMANTIC_LAYER:
479 info->writes_layer = true;
480 break;
481 case TGSI_SEMANTIC_PSIZE:
482 info->writes_psize = true;
483 break;
484 case TGSI_SEMANTIC_CLIPVERTEX:
485 info->writes_clipvertex = true;
486 break;
487 case TGSI_SEMANTIC_COLOR:
488 info->colors_written |= 1 << semantic_index;
489 break;
490 case TGSI_SEMANTIC_STENCIL:
491 info->writes_stencil = true;
492 break;
493 case TGSI_SEMANTIC_SAMPLEMASK:
494 info->writes_samplemask = true;
495 break;
496 case TGSI_SEMANTIC_EDGEFLAG:
497 info->writes_edgeflag = true;
498 break;
499 case TGSI_SEMANTIC_POSITION:
500 if (info->processor == PIPE_SHADER_FRAGMENT)
501 info->writes_z = true;
502 else
503 info->writes_position = true;
504 break;
505 }
506
507 if (nir->info.stage == MESA_SHADER_TESS_CTRL) {
508 switch (semantic_name) {
509 case TGSI_SEMANTIC_PATCH:
510 info->reads_perpatch_outputs = true;
511 break;
512 case TGSI_SEMANTIC_TESSINNER:
513 case TGSI_SEMANTIC_TESSOUTER:
514 info->reads_tessfactor_outputs = true;
515 break;
516 default:
517 info->reads_pervertex_outputs = true;
518 }
519 }
520 }
521
522 info->num_outputs = num_outputs;
523
524 nir_foreach_variable(variable, &nir->uniforms) {
525 const struct glsl_type *type = variable->type;
526 enum glsl_base_type base_type =
527 glsl_get_base_type(glsl_without_array(type));
528 unsigned aoa_size = MAX2(1, glsl_get_aoa_size(type));
529
530 /* We rely on the fact that nir_lower_samplers_as_deref has
531 * eliminated struct dereferences.
532 */
533 if (base_type == GLSL_TYPE_SAMPLER)
534 info->samplers_declared |=
535 u_bit_consecutive(variable->data.binding, aoa_size);
536 else if (base_type == GLSL_TYPE_IMAGE)
537 info->images_declared |=
538 u_bit_consecutive(variable->data.binding, aoa_size);
539 }
540
541 info->num_written_clipdistance = nir->info.clip_distance_array_size;
542 info->num_written_culldistance = nir->info.cull_distance_array_size;
543 info->clipdist_writemask = u_bit_consecutive(0, info->num_written_clipdistance);
544 info->culldist_writemask = u_bit_consecutive(0, info->num_written_culldistance);
545
546 if (info->processor == PIPE_SHADER_FRAGMENT)
547 info->uses_kill = nir->info.fs.uses_discard;
548
549 /* TODO make this more accurate */
550 info->const_buffers_declared = u_bit_consecutive(0, SI_NUM_CONST_BUFFERS);
551 info->shader_buffers_declared = u_bit_consecutive(0, SI_NUM_SHADER_BUFFERS);
552
553 func = (struct nir_function *)exec_list_get_head_const(&nir->functions);
554 nir_foreach_block(block, func->impl) {
555 nir_foreach_instr(instr, block)
556 scan_instruction(info, instr);
557 }
558 }
559
560 /**
561 * Perform "lowering" operations on the NIR that are run once when the shader
562 * selector is created.
563 */
564 void
565 si_lower_nir(struct si_shader_selector* sel)
566 {
567 /* Adjust the driver location of inputs and outputs. The state tracker
568 * interprets them as slots, while the ac/nir backend interprets them
569 * as individual components.
570 */
571 nir_foreach_variable(variable, &sel->nir->inputs)
572 variable->data.driver_location *= 4;
573
574 nir_foreach_variable(variable, &sel->nir->outputs) {
575 variable->data.driver_location *= 4;
576
577 if (sel->nir->info.stage == MESA_SHADER_FRAGMENT) {
578 if (variable->data.location == FRAG_RESULT_DEPTH)
579 variable->data.driver_location += 2;
580 else if (variable->data.location == FRAG_RESULT_STENCIL)
581 variable->data.driver_location += 1;
582 }
583 }
584
585 /* Perform lowerings (and optimizations) of code.
586 *
587 * Performance considerations aside, we must:
588 * - lower certain ALU operations
589 * - ensure constant offsets for texture instructions are folded
590 * and copy-propagated
591 */
592 NIR_PASS_V(sel->nir, nir_lower_io, nir_var_uniform, type_size,
593 (nir_lower_io_options)0);
594 NIR_PASS_V(sel->nir, nir_lower_uniforms_to_ubo);
595
596 NIR_PASS_V(sel->nir, nir_lower_returns);
597 NIR_PASS_V(sel->nir, nir_lower_vars_to_ssa);
598 NIR_PASS_V(sel->nir, nir_lower_alu_to_scalar);
599 NIR_PASS_V(sel->nir, nir_lower_phis_to_scalar);
600
601 static const struct nir_lower_tex_options lower_tex_options = {
602 .lower_txp = ~0u,
603 };
604 NIR_PASS_V(sel->nir, nir_lower_tex, &lower_tex_options);
605
606 const nir_lower_subgroups_options subgroups_options = {
607 .subgroup_size = 64,
608 .ballot_bit_size = 32,
609 .lower_to_scalar = true,
610 .lower_subgroup_masks = true,
611 .lower_vote_trivial = false,
612 };
613 NIR_PASS_V(sel->nir, nir_lower_subgroups, &subgroups_options);
614
615 bool progress;
616 do {
617 progress = false;
618
619 /* (Constant) copy propagation is needed for txf with offsets. */
620 NIR_PASS(progress, sel->nir, nir_copy_prop);
621 NIR_PASS(progress, sel->nir, nir_opt_remove_phis);
622 NIR_PASS(progress, sel->nir, nir_opt_dce);
623 if (nir_opt_trivial_continues(sel->nir)) {
624 progress = true;
625 NIR_PASS(progress, sel->nir, nir_copy_prop);
626 NIR_PASS(progress, sel->nir, nir_opt_dce);
627 }
628 NIR_PASS(progress, sel->nir, nir_opt_if);
629 NIR_PASS(progress, sel->nir, nir_opt_dead_cf);
630 NIR_PASS(progress, sel->nir, nir_opt_cse);
631 NIR_PASS(progress, sel->nir, nir_opt_peephole_select, 8);
632
633 /* Needed for algebraic lowering */
634 NIR_PASS(progress, sel->nir, nir_opt_algebraic);
635 NIR_PASS(progress, sel->nir, nir_opt_constant_folding);
636
637 NIR_PASS(progress, sel->nir, nir_opt_undef);
638 NIR_PASS(progress, sel->nir, nir_opt_conditional_discard);
639 if (sel->nir->options->max_unroll_iterations) {
640 NIR_PASS(progress, sel->nir, nir_opt_loop_unroll, 0);
641 }
642 } while (progress);
643 }
644
645 static void declare_nir_input_vs(struct si_shader_context *ctx,
646 struct nir_variable *variable,
647 unsigned input_index,
648 LLVMValueRef out[4])
649 {
650 si_llvm_load_input_vs(ctx, input_index, out);
651 }
652
653 static void declare_nir_input_fs(struct si_shader_context *ctx,
654 struct nir_variable *variable,
655 unsigned input_index,
656 LLVMValueRef out[4])
657 {
658 unsigned slot = variable->data.location;
659 if (slot == VARYING_SLOT_POS) {
660 out[0] = LLVMGetParam(ctx->main_fn, SI_PARAM_POS_X_FLOAT);
661 out[1] = LLVMGetParam(ctx->main_fn, SI_PARAM_POS_Y_FLOAT);
662 out[2] = LLVMGetParam(ctx->main_fn, SI_PARAM_POS_Z_FLOAT);
663 out[3] = ac_build_fdiv(&ctx->ac, ctx->ac.f32_1,
664 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_W_FLOAT));
665 return;
666 }
667
668 si_llvm_load_input_fs(ctx, input_index, out);
669 }
670
671 LLVMValueRef si_nir_load_input_gs(struct ac_shader_abi *abi,
672 unsigned location,
673 unsigned driver_location,
674 unsigned component,
675 unsigned num_components,
676 unsigned vertex_index,
677 unsigned const_index,
678 LLVMTypeRef type)
679 {
680 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
681
682 LLVMValueRef value[4];
683 for (unsigned i = component; i < num_components + component; i++) {
684 value[i] = si_llvm_load_input_gs(&ctx->abi, driver_location / 4,
685 vertex_index, type, i);
686 }
687
688 return ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
689 }
690
691 LLVMValueRef
692 si_nir_lookup_interp_param(struct ac_shader_abi *abi,
693 enum glsl_interp_mode interp, unsigned location)
694 {
695 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
696 int interp_param_idx = -1;
697
698 switch (interp) {
699 case INTERP_MODE_FLAT:
700 return NULL;
701 case INTERP_MODE_SMOOTH:
702 case INTERP_MODE_NONE:
703 if (location == INTERP_CENTER)
704 interp_param_idx = SI_PARAM_PERSP_CENTER;
705 else if (location == INTERP_CENTROID)
706 interp_param_idx = SI_PARAM_PERSP_CENTROID;
707 else if (location == INTERP_SAMPLE)
708 interp_param_idx = SI_PARAM_PERSP_SAMPLE;
709 break;
710 case INTERP_MODE_NOPERSPECTIVE:
711 if (location == INTERP_CENTER)
712 interp_param_idx = SI_PARAM_LINEAR_CENTER;
713 else if (location == INTERP_CENTROID)
714 interp_param_idx = SI_PARAM_LINEAR_CENTROID;
715 else if (location == INTERP_SAMPLE)
716 interp_param_idx = SI_PARAM_LINEAR_SAMPLE;
717 break;
718 default:
719 assert(!"Unhandled interpolation mode.");
720 return NULL;
721 }
722
723 return interp_param_idx != -1 ?
724 LLVMGetParam(ctx->main_fn, interp_param_idx) : NULL;
725 }
726
727 static LLVMValueRef
728 si_nir_load_sampler_desc(struct ac_shader_abi *abi,
729 unsigned descriptor_set, unsigned base_index,
730 unsigned constant_index, LLVMValueRef dynamic_index,
731 enum ac_descriptor_type desc_type, bool image,
732 bool write)
733 {
734 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
735 LLVMBuilderRef builder = ctx->ac.builder;
736 LLVMValueRef list = LLVMGetParam(ctx->main_fn, ctx->param_samplers_and_images);
737 LLVMValueRef index = dynamic_index;
738
739 assert(!descriptor_set);
740
741 if (!index)
742 index = ctx->ac.i32_0;
743
744 index = LLVMBuildAdd(builder, index,
745 LLVMConstInt(ctx->ac.i32, base_index + constant_index, false),
746 "");
747
748 if (image) {
749 assert(desc_type == AC_DESC_IMAGE || desc_type == AC_DESC_BUFFER);
750 assert(base_index + constant_index < ctx->num_images);
751
752 if (dynamic_index)
753 index = si_llvm_bound_index(ctx, index, ctx->num_images);
754
755 index = LLVMBuildSub(ctx->gallivm.builder,
756 LLVMConstInt(ctx->i32, SI_NUM_IMAGES - 1, 0),
757 index, "");
758
759 /* TODO: be smarter about when we use dcc_off */
760 return si_load_image_desc(ctx, list, index, desc_type, write);
761 }
762
763 assert(base_index + constant_index < ctx->num_samplers);
764
765 if (dynamic_index)
766 index = si_llvm_bound_index(ctx, index, ctx->num_samplers);
767
768 index = LLVMBuildAdd(ctx->gallivm.builder, index,
769 LLVMConstInt(ctx->i32, SI_NUM_IMAGES / 2, 0), "");
770
771 return si_load_sampler_desc(ctx, list, index, desc_type);
772 }
773
774 static void bitcast_inputs(struct si_shader_context *ctx,
775 LLVMValueRef data[4],
776 unsigned input_idx)
777 {
778 for (unsigned chan = 0; chan < 4; chan++) {
779 ctx->inputs[input_idx + chan] =
780 LLVMBuildBitCast(ctx->ac.builder, data[chan], ctx->ac.i32, "");
781 }
782 }
783
784 bool si_nir_build_llvm(struct si_shader_context *ctx, struct nir_shader *nir)
785 {
786 struct tgsi_shader_info *info = &ctx->shader->selector->info;
787
788 if (nir->info.stage == MESA_SHADER_VERTEX ||
789 nir->info.stage == MESA_SHADER_FRAGMENT) {
790 uint64_t processed_inputs = 0;
791 nir_foreach_variable(variable, &nir->inputs) {
792 unsigned attrib_count = glsl_count_attribute_slots(variable->type,
793 nir->info.stage == MESA_SHADER_VERTEX);
794 unsigned input_idx = variable->data.driver_location;
795
796 LLVMValueRef data[4];
797 unsigned loc = variable->data.location;
798
799 for (unsigned i = 0; i < attrib_count; i++) {
800 /* Packed components share the same location so skip
801 * them if we have already processed the location.
802 */
803 if (processed_inputs & ((uint64_t)1 << loc)) {
804 input_idx += 4;
805 continue;
806 }
807
808 if (nir->info.stage == MESA_SHADER_VERTEX) {
809 declare_nir_input_vs(ctx, variable, input_idx / 4, data);
810 bitcast_inputs(ctx, data, input_idx);
811 if (glsl_type_is_dual_slot(variable->type)) {
812 input_idx += 4;
813 declare_nir_input_vs(ctx, variable, input_idx / 4, data);
814 bitcast_inputs(ctx, data, input_idx);
815 }
816 } else if (nir->info.stage == MESA_SHADER_FRAGMENT) {
817 declare_nir_input_fs(ctx, variable, input_idx / 4, data);
818 bitcast_inputs(ctx, data, input_idx);
819 }
820
821 processed_inputs |= ((uint64_t)1 << loc);
822 loc++;
823 input_idx += 4;
824 }
825 }
826 }
827
828 ctx->abi.inputs = &ctx->inputs[0];
829 ctx->abi.load_sampler_desc = si_nir_load_sampler_desc;
830 ctx->abi.clamp_shadow_reference = true;
831
832 ctx->num_samplers = util_last_bit(info->samplers_declared);
833 ctx->num_images = util_last_bit(info->images_declared);
834
835 ac_nir_translate(&ctx->ac, &ctx->abi, nir, NULL);
836
837 return true;
838 }